blob: 1a5d10e1c470e8ed7ab27ce4ca0637d677865846 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
|
# Makefile template for Configure for the CRIS simulator, based on a mix
# of the ones for m32r and i960.
#
# Copyright (C) 2004-2021 Free Software Foundation, Inc.
# Contributed by Axis Communications.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
## COMMON_PRE_CONFIG_FRAG
CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o modelv10.o mloopv10f.o
CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o modelv32.o mloopv32f.o
SIM_OBJS = \
$(SIM_NEW_COMMON_OBJS) \
cgen-utils.o cgen-trace.o cgen-scache.o \
cgen-run.o \
sim-if.o arch.o \
$(CRISV10F_OBJS) \
$(CRISV32F_OBJS) \
traps.o
SIM_EXTRA_HW_DEVICES = rv cris cris_900000xx
# Extra headers included by sim-main.h.
# FIXME: $(srccom)/cgen-ops.h should be in CGEN_INCLUDE_DEPS.
SIM_EXTRA_DEPS = \
$(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \
arch.h cpuall.h cris-sim.h engv10.h engv32.h
SIM_EXTRA_CLEAN = cris-clean
## COMMON_POST_CONFIG_FRAG
arch = cris
# rvdummy is just used for testing. It does nothing if
# --enable-sim-hardware isn't active.
all: rvdummy$(EXEEXT)
check: rvdummy$(EXEEXT)
rvdummy$(EXEEXT): rvdummy.o $(EXTRA_LIBDEPS)
$(ECHO_CCLD) $(CC) $(ALL_CFLAGS) -o rvdummy$(EXEEXT) rvdummy.o $(EXTRA_LIBS)
rvdummy.o: rvdummy.c $(remote_sim_h) $(callback_h)
# CRISV10 objs
CRISV10F_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpuv10.h decodev10.h engv10.h
# CRISV32 objs
CRISV32F_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpuv32.h decodev32.h engv32.h
cris-clean:
-rm -f stamp-arch
-rm -f tmp-* rvdummy$(EXEEXT)
# Useful when making CGEN-generated files manually, without --enable-cgen-maint.
stamps: stamp-arch stamp-v10fcpu stamp-v32fcpu
stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CPU_DIR)/cris.cpu Makefile
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=crisv10,crisv32 \
archfile=$(CPU_DIR)/cris.cpu \
FLAGS="with-scache with-profile=fn"
$(SILENCE) touch $@
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
# The sed-hack is supposed to be temporary, until we get CGEN to emit it.
stamp-v10fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/cris.cpu Makefile
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
archfile=$(CPU_DIR)/cris.cpu \
cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
$(SILENCE) $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv10-switch.c $(srcdir)/semcrisv10f-switch.c
$(SILENCE) touch $@
cpuv10.h cpuv10.c semcrisv10f-switch.c modelv10.c decodev10.c decodev10.h: $(CGEN_MAINT) stamp-v10fcpu
stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/cris.cpu Makefile
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
archfile=$(CPU_DIR)/cris.cpu \
cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
$(SILENCE) $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv32-switch.c $(srcdir)/semcrisv32f-switch.c
$(SILENCE) touch $@
cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu
|
