1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
|
/* Simulator parallel routines for CGEN simulators (and maybe others).
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of the GNU instruction set simulator.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-par.h"
/* Functions required by the cgen interface. These functions add various
kinds of writes to the write queue. */
void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_BI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.bi_write.target = target;
element->kinds.bi_write.value = value;
}
void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_QI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.qi_write.target = target;
element->kinds.qi_write.value = value;
}
void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_SI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.si_write.target = target;
element->kinds.si_write.value = value;
}
void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_SF_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.sf_write.target = target;
element->kinds.sf_write.value = value;
}
void sim_queue_pc_write (SIM_CPU *cpu, USI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_PC_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.pc_write.value = value;
}
void sim_queue_fn_hi_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, UHI),
UINT regno,
UHI value
)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_HI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_hi_write.function = write_function;
element->kinds.fn_hi_write.regno = regno;
element->kinds.fn_hi_write.value = value;
}
void sim_queue_fn_si_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, USI),
UINT regno,
SI value
)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_SI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_si_write.function = write_function;
element->kinds.fn_si_write.regno = regno;
element->kinds.fn_si_write.value = value;
}
void sim_queue_fn_di_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, DI),
UINT regno,
DI value
)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_DI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_di_write.function = write_function;
element->kinds.fn_di_write.regno = regno;
element->kinds.fn_di_write.value = value;
}
void sim_queue_fn_df_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, UINT, DI),
UINT regno,
DF value
)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_DF_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_df_write.function = write_function;
element->kinds.fn_df_write.regno = regno;
element->kinds.fn_df_write.value = value;
}
void sim_queue_fn_pc_write (
SIM_CPU *cpu,
void (*write_function)(SIM_CPU *cpu, USI),
USI value
)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_FN_PC_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.fn_pc_write.function = write_function;
element->kinds.fn_pc_write.value = value;
}
void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_QI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_qi_write.address = address;
element->kinds.mem_qi_write.value = value;
}
void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_HI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_hi_write.address = address;
element->kinds.mem_hi_write.value = value;
}
void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_SI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_si_write.address = address;
element->kinds.mem_si_write.value = value;
}
void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_DI_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_di_write.address = address;
element->kinds.mem_di_write.value = value;
}
void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
{
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
element->kind = CGEN_MEM_DF_WRITE;
element->insn_address = CPU_PC_GET (cpu);
element->kinds.mem_df_write.address = address;
element->kinds.mem_df_write.value = value;
}
/* Execute a write stored on the write queue. */
void
cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
{
IADDR pc;
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
{
case CGEN_BI_WRITE:
*item->kinds.bi_write.target = item->kinds.bi_write.value;
break;
case CGEN_QI_WRITE:
*item->kinds.qi_write.target = item->kinds.qi_write.value;
break;
case CGEN_SI_WRITE:
*item->kinds.si_write.target = item->kinds.si_write.value;
break;
case CGEN_SF_WRITE:
*item->kinds.sf_write.target = item->kinds.sf_write.value;
break;
case CGEN_PC_WRITE:
CPU_PC_SET (cpu, item->kinds.pc_write.value);
break;
case CGEN_FN_HI_WRITE:
item->kinds.fn_hi_write.function (cpu,
item->kinds.fn_hi_write.regno,
item->kinds.fn_hi_write.value);
break;
case CGEN_FN_SI_WRITE:
item->kinds.fn_si_write.function (cpu,
item->kinds.fn_si_write.regno,
item->kinds.fn_si_write.value);
break;
case CGEN_FN_DI_WRITE:
item->kinds.fn_di_write.function (cpu,
item->kinds.fn_di_write.regno,
item->kinds.fn_di_write.value);
break;
case CGEN_FN_DF_WRITE:
item->kinds.fn_df_write.function (cpu,
item->kinds.fn_df_write.regno,
item->kinds.fn_df_write.value);
break;
case CGEN_FN_PC_WRITE:
item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
break;
case CGEN_MEM_QI_WRITE:
pc = item->insn_address;
SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
item->kinds.mem_qi_write.value);
break;
case CGEN_MEM_HI_WRITE:
pc = item->insn_address;
SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
item->kinds.mem_hi_write.value);
break;
case CGEN_MEM_SI_WRITE:
pc = item->insn_address;
SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
item->kinds.mem_si_write.value);
break;
case CGEN_MEM_DI_WRITE:
pc = item->insn_address;
SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
item->kinds.mem_di_write.value);
break;
case CGEN_MEM_DF_WRITE:
pc = item->insn_address;
SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
item->kinds.mem_df_write.value);
break;
default:
break; /* FIXME: for now....print message later. */
}
}
/* Utilities for the write queue. */
CGEN_WRITE_QUEUE_ELEMENT *
cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
{
abort (); /* FIXME: for now....print message later. */
return 0;
}
|
