1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
|
/* Opcode table for TI TMS320C80 (MVP).
Copyright 1996 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include "ansidecl.h"
#include "opcode/tic80.h"
/* This file holds the TMS320C80 (MVP) opcode table. The table is
strictly constant data, so the compiler should be able to put it in
the .text section.
This file also holds the operand table. All knowledge about
inserting operands into instructions and vice-versa is kept in this
file. */
/* The operands table. The fields are:
bits, shift, insertion function, extraction function, flags
*/
const struct tic80_operand tic80_operands[] =
{
/* The zero index is used to indicate the end of the list of operands. */
#define UNUSED (0)
{ 0, 0, 0, 0, 0 },
/* Short signed immediate value in bits 14-0. */
#define SSI (UNUSED + 1)
{ 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
/* Short unsigned immediate value in bits 14-0 */
#define SUI (SSI + 1)
{ 15, 0, NULL, NULL, 0 },
/* Short unsigned bitfield in bits 14-0. We distinguish this
from a regular unsigned immediate value only for the convenience
of the disassembler and the user. */
#define SUBF (SUI + 1)
{ 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
/* Long signed immediate in following 32 bit word */
#define LSI (SUBF + 1)
{ 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
/* Long unsigned immediate in following 32 bit word */
#define LUI (LSI + 1)
{ 32, 0, NULL, NULL, 0 },
/* Long unsigned bitfield in following 32 bit word. We distinguish
this from a regular unsigned immediate value only for the
convenience of the disassembler and the user. */
#define LUBF (LUI + 1)
{ 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
/* Register in bits 4-0 */
#define REG0 (LUBF + 1)
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
/* Register in bits 26-22 */
#define REG22 (REG0 + 1)
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
/* Register in bits 31-27 */
#define REG27 (REG22 + 1)
{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
};
const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
/* Macros used to generate entries for the opcodes table. */
#define FIXME 0
/* Short-Immediate Format Instructions */
#define OP_SI(x) (((x) & 0x7F) << 15)
#define MASK_SI OP_SI(0x7F)
#define MASK_SI_M OP_SI(0x7B) /* Short-Immediate with embedded M bit */
/* Long-Immediate Format Instructions */
#define OP_LI(x) (((x) & 0x3FF) << 12)
#define MASK_LI OP_LI(0x3FF)
#define MASK_LI_M OP_LI(0x3F7) /* Long-Immediate with embedded M bit */
/* Register Format Instructions */
#define OP_REG(x) OP_LI(x) /* For readability */
#define MASK_REG MASK_LI /* For readability */
#define MASK_REG_M MASK_LI_M /* For readability */
const struct tic80_opcode tic80_opcodes[] = {
/* Signed integer ADD */
{"add", OP_SI(0x58), MASK_SI, FMT_SI, {SSI, REG22, REG27} },
{"add", OP_LI(0x3B1), MASK_LI, FMT_LI, {LSI, REG22, REG27} },
{"add", OP_REG(0x3B0), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
/* Unsigned integer ADD */
{"addu", OP_SI(0x59), MASK_SI, FMT_SI, {SSI, REG22, REG27} },
{"addu", OP_LI(0x3B3), MASK_LI, FMT_LI, {LSI, REG22, REG27} },
{"addu", OP_REG(0x3B2), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
/* Bitwise AND */
{"and", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
{"and", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
{"and", OP_REG(0x322), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
{"and.tt", OP_SI(0x11), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
{"and.tt", OP_LI(0x323), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
{"and.tt", OP_REG(0x322), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
/* Bitwise AND with ones complement of both sources */
{"and.ff", OP_SI(0x18), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
{"and.ff", OP_LI(0x331), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
{"and.ff", OP_REG(0x330), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
/* Bitwise AND with ones complement of source 1 */
{"and.ft", OP_SI(0x14), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
{"and.ft", OP_LI(0x329), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
{"and.ft", OP_REG(0x328), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
/* Bitwise AND with ones complement of source 2 */
{"and.tf", OP_SI(0x12), MASK_SI, FMT_SI, {SUBF, REG22, REG27} },
{"and.tf", OP_LI(0x325), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
{"and.tf", OP_REG(0x324), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
/* WORK IN PROGRESS BELOW THIS POINT */
{"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, FIXME},
{"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, FIXME},
{"brcr", OP_SI(0x6), MASK_SI, FMT_SI, FIXME},
{"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, FIXME},
{"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, FIXME},
{"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, FIXME},
{"illop0", OP_SI(0), MASK_SI, FMT_SI, FIXME},
{"ld", OP_LI(0x345), MASK_LI_M, FMT_LI, FIXME},
{"ld", OP_REG(0x344), MASK_REG_M, FMT_REG, FIXME},
{"ld", OP_SI(0x22), MASK_SI_M, FMT_SI, FIXME},
{"ld.b", OP_LI(0x341), MASK_LI_M, FMT_LI, FIXME},
{"ld.b", OP_REG(0x340), MASK_REG_M, FMT_REG, FIXME},
{"ld.b", OP_SI(0x20), MASK_SI_M, FMT_SI, FIXME},
{"ld.d", OP_LI(0x347), MASK_LI_M, FMT_LI, FIXME},
{"ld.d", OP_REG(0x346), MASK_REG_M, FMT_REG, FIXME},
{"ld.d", OP_SI(0x23), MASK_SI_M, FMT_SI, FIXME},
{"ld.h", OP_LI(0x343), MASK_LI_M, FMT_LI, FIXME},
{"ld.h", OP_REG(0x342), MASK_REG_M, FMT_REG, FIXME},
{"ld.h", OP_SI(0x21), MASK_SI_M, FMT_SI, FIXME},
{"ld.u", OP_LI(0x355), MASK_LI_M, FMT_LI, FIXME},
{"ld.u", OP_REG(0x354), MASK_REG_M, FMT_REG, FIXME},
{"ld.u", OP_SI(0x2A), MASK_SI_M, FMT_SI, FIXME},
{"ld.ub", OP_LI(0x351), MASK_LI_M, FMT_LI, FIXME},
{"ld.ub", OP_REG(0x350), MASK_REG_M, FMT_REG, FIXME},
{"ld.ub", OP_SI(0x28), MASK_SI_M, FMT_SI, FIXME},
{"ld.ud", OP_LI(0x357), MASK_LI_M, FMT_LI, FIXME},
{"ld.ud", OP_REG(0x356), MASK_REG_M, FMT_REG, FIXME},
{"ld.ud", OP_SI(0x2B), MASK_SI_M, FMT_SI, FIXME},
{"ld.uh", OP_LI(0x353), MASK_LI_M, FMT_LI, FIXME},
{"ld.uh", OP_REG(0x352), MASK_REG_M, FMT_REG, FIXME},
{"ld.uh", OP_SI(0x29), MASK_SI_M, FMT_SI, FIXME},
{"or.ff", OP_LI(0x33D), MASK_LI, FMT_LI, FIXME},
{"or.ff", OP_REG(0x33C), MASK_REG, FMT_REG, FIXME},
{"or.ff", OP_SI(0x1E), MASK_SI, FMT_SI, FIXME},
{"or.ft", OP_LI(0x33B), MASK_LI, FMT_LI, FIXME},
{"or.ft", OP_REG(0x33A), MASK_REG, FMT_REG, FIXME},
{"or.ft", OP_SI(0x1D), MASK_SI, FMT_SI, FIXME},
{"or.tf", OP_LI(0x337), MASK_LI, FMT_LI, FIXME},
{"or.tf", OP_REG(0x336), MASK_REG, FMT_REG, FIXME},
{"or.tf", OP_SI(0x1B), MASK_SI, FMT_SI, FIXME},
{"or.tt", OP_LI(0x32F), MASK_LI, FMT_LI, FIXME},
{"or.tt", OP_REG(0x32E), MASK_REG, FMT_REG, FIXME},
{"or.tt", OP_SI(0x17), MASK_SI, FMT_SI, FIXME},
{"rdcr", OP_LI(0x309), MASK_LI, FMT_LI, FIXME},
{"rdcr", OP_REG(0x308), MASK_REG, FMT_REG, FIXME},
{"rdcr", OP_SI(0x4), MASK_SI, FMT_SI, FIXME},
{"shift.dm", OP_REG(0x312), MASK_REG, FMT_REG, FIXME},
{"shift.dm", OP_SI(0x9), MASK_SI, FMT_SI, FIXME},
{"shift.ds", OP_REG(0x314), MASK_REG, FMT_REG, FIXME},
{"shift.ds", OP_SI(0xA), MASK_SI, FMT_SI, FIXME},
{"shift.dz", OP_REG(0x310), MASK_REG, FMT_REG, FIXME},
{"shift.dz", OP_SI(0x8), MASK_SI, FMT_SI, FIXME},
{"shift.em", OP_REG(0x318), MASK_REG, FMT_REG, FIXME},
{"shift.em", OP_SI(0xC), MASK_SI, FMT_SI, FIXME},
{"shift.es", OP_REG(0x31A), MASK_REG, FMT_REG, FIXME},
{"shift.es", OP_SI(0xD), MASK_SI, FMT_SI, FIXME},
{"shift.ez", OP_REG(0x316), MASK_REG, FMT_REG, FIXME},
{"shift.ez", OP_SI(0xB), MASK_SI, FMT_SI, FIXME},
{"shift.im", OP_REG(0x31E), MASK_REG, FMT_REG, FIXME},
{"shift.im", OP_SI(0xF), MASK_SI, FMT_SI, FIXME},
{"shift.iz", OP_REG(0x31C), MASK_REG, FMT_REG, FIXME},
{"shift.iz", OP_SI(0xE), MASK_SI, FMT_SI, FIXME},
{"st", OP_LI(0x365), MASK_LI_M, FMT_LI, FIXME},
{"st", OP_REG(0x364), MASK_REG_M, FMT_REG, FIXME},
{"st", OP_SI(0x32), MASK_SI_M, FMT_SI, FIXME},
{"st.b", OP_LI(0x361), MASK_LI_M, FMT_LI, FIXME},
{"st.b", OP_REG(0x360), MASK_REG_M, FMT_REG, FIXME},
{"st.b", OP_SI(0x30), MASK_SI_M, FMT_SI, FIXME},
{"st.d", OP_LI(0x367), MASK_LI_M, FMT_LI, FIXME},
{"st.d", OP_REG(0x366), MASK_REG_M, FMT_REG, FIXME},
{"st.d", OP_SI(0x33), MASK_SI_M, FMT_SI, FIXME},
{"st.h", OP_LI(0x363), MASK_LI_M, FMT_LI, FIXME},
{"st.h", OP_REG(0x362), MASK_REG_M, FMT_REG, FIXME},
{"st.h", OP_SI(0x31), MASK_SI_M, FMT_SI, FIXME},
{"swcr", OP_LI(0x30B), MASK_LI, FMT_LI, FIXME},
{"swcr", OP_REG(0x30A), MASK_REG, FMT_REG, FIXME},
{"swcr", OP_SI(0x5), MASK_SI, FMT_SI, FIXME},
{"trap", OP_LI(0x303), MASK_LI, FMT_LI, FIXME},
{"trap", OP_REG(0x302), MASK_REG, FMT_REG, FIXME},
{"trap", OP_SI(0x1), MASK_SI, FMT_SI, FIXME},
{"xnor", OP_LI(0x333), MASK_LI, FMT_LI, FIXME},
{"xnor", OP_REG(0x332), MASK_REG, FMT_REG, FIXME},
{"xnor", OP_SI(0x19), MASK_SI, FMT_SI, FIXME},
{"xor", OP_LI(0x32D), MASK_LI, FMT_LI, FIXME},
{"xor", OP_REG(0x32C), MASK_REG, FMT_REG, FIXME},
{"xor", OP_SI(0x16), MASK_SI, FMT_SI, FIXME},
};
const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
|
