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|
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
entries.
* i386-dis-evex-len.h (evex_len_table): Likewise.
* i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
EVEX_W_0F3A43_L_n): New.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
* i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
* i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
0F385B, 0F38C6, and 0F38C7 entries.
* i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
0F38C6 and 0F38C7.
* i386-dis-evex-w.h: No longer link to evex_len_table[] for
opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0): Delete.
MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
(prefix_table): No longer link to vex_len_table[] for opcodes
0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
0F92, 0F93, 0F98, and 0F99.
(vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
REG_VEX_0F73_M_0 respectively.
(MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
MOD_VEX_0F73_REG_7): Delete.
(MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
(PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
PREFIX_VEX_0F3AF0_L_0 respectively.
(VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
(VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
VEX_LEN_0F38F7): New.
(VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
(reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
0F72, and 0F73. No longer link to vex_len_table[] for opcode
0F38F3.
(prefix_table): No longer link to vex_len_table[] for opcodes
0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
(vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
0F38F6, 0F38F7, and 0F3AF0.
(vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
(mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
0F73.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
(MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
(MOD_0F71, MOD_0F72, MOD_0F73): New.
(dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
73.
(reg_table): No longer link to mod_table[] for opcodes 0F71,
0F72, and 0F73.
(mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
0F73.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
(reg_table): Don't link to mod_table[] where not needed. Add
PREFIX_IGNORED to nop entries.
(prefix_table): Replace PREFIX_OPCODE in nop entries.
(mod_table): Add nop entries next to prefetch ones. Drop
MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
(rm_table): Add PREFIX_IGNORED to nop entries. Drop
PREFIX_OPCODE from endbr* entries.
(get_valid_dis386): Also consider entry's name when zapping
vindex.
(print_insn): Handle PREFIX_IGNORED.
2021-03-09 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
element.
* opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
(PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
(struct i386_opcode_modifier): Delete notrackprefixok,
islockable, hleprefixok, and repprefixok fields. Add prefixok
field.
* opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
(mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
Replace HLEPrefixOk.
* opcodes/i386-tbl.h: Re-generate.
2021-03-09 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
* opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
64-bit form.
* opcodes/i386-tbl.h: Re-generate.
2021-03-03 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Don't get operand count. Look
for {} instead of {0}. Don't look for '0'.
* i386-opc.tbl: Drop operand count field. Drop redundant operand
size specifiers.
2021-02-19 Nelson Chu <nelson.chu@sifive.com>
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
2021-02-18 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
(default_priv_spec): Updated type to riscv_spec_class.
(parse_riscv_dis_option): Updated.
* riscv-opc.c: Moved stuff and make the file tidy.
2021-02-17 Alan Modra <amodra@gmail.com>
* wasm32-dis.c: Include limits.h.
(CHAR_BIT): Provide backup define.
(wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
Correct signed overflow checking.
2021-02-16 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
* i386-tbl.h: Re-generate.
2021-02-16 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
Oword.
* i386-opc.tbl (CpuFP, Mmword, Oword): Define.
2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch14 as cpu string.
* s390-opc.txt: Add new arch14 instructions.
2021-02-04 Nick Alcock <nick.alcock@oracle.com>
* configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
favour of LIBINTL.
* configure: Regenerated.
2021-02-08 Mike Frysinger <vapier@gentoo.org>
* tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
* tic54x-opc.c (regs): Rename to ...
(tic54x_regs): ... this.
(mmregs): Rename to ...
(tic54x_mmregs): ... this.
(condition_codes): Rename to ...
(tic54x_condition_codes): ... this.
(cc2_codes): Rename to ...
(tic54x_cc2_codes): ... this.
(cc3_codes): Rename to ...
(tic54x_cc3_codes): ... this.
(status_bits): Rename to ...
(tic54x_status_bits): ... this.
(misc_symbols): Rename to ...
(tic54x_misc_symbols): ... this.
2021-02-04 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (MASK_RVB_IMM): Removed.
(riscv_opcodes): Removed zb* instructions.
(riscv_ext_version_table): Removed versions for zb*.
2021-01-26 Alan Modra <amodra@gmail.com>
* i386-gen.c (parse_template): Ensure entire template_instance
is initialised.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
(riscv_fpr_names_abi): Likewise.
(riscv_opcodes): Likewise.
(riscv_insn_types): Likewise.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c: Comments tidy and improvement.
* riscv-opc.c: Likewise.
2021-01-13 Alan Modra <amodra@gmail.com>
* Makefile.in: Regenerate.
2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26792
* configure.ac: Use GNU_MAKE_JOBSERVER.
* aclocal.m4: Regenerated.
* configure: Likewise.
2021-01-12 Nick Clifton <nickc@redhat.com>
* po/sr.po: Updated Serbian translation.
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27173
* configure: Regenerated.
2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-opc.c (aarch64_print_operand):
Delete handling of AARCH64_OPND_CSRE_CSR.
* aarch64-tbl.h (aarch64_feature_csre): Delete.
(CSRE): Likewise.
(_CSRE_INSN): Likewise.
(aarch64_opcode_table): Delete csr.
2021-01-11 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/fr.po: Updated French translation.
* po/pt_BR.po: Updated Brazilian Portuguese translation.
* po/sv.po: Updated Swedish translation.
* po/uk.po: Updated Ukranian translation.
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
2021-01-09 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
2021-01-08 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (insert_dw, (extract_dw): New functions.
(DW, (XRC_MASK): Define.
(powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
2021-01-09 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2021-01-08 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
2021-01-08 Nick Clifton <nickc@redhat.com>
PR 27129
* aarch64-dis.c (determine_disassembling_preference): Move call to
aarch64_match_operands_constraint outside of the assertion.
* aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
Replace with a return of FALSE.
PR 27139
* aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
core system register.
2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
* configure: Regenerate.
2021-01-07 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
2021-01-07 Fredrik Noring <noring@nocrew.org>
* m68k-opc.c (chkl): Change minimum architecture requirement to
m68020.
2021-01-07 Philipp Tomsich <prt@gnu.org>
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2021-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
For older changes see ChangeLog-2020
Copyright (C) 2021 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
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