1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
|
2018-01-17 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
(cpu_flags): Add CpuIBT, CpuSHSTK.
* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
(i386_cpu_flags): Add cpuibt, cpushstk.
* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-16 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portugese translation.
* po/de.po: Updated German translation.
2018-01-15 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-15 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
2018-01-13 Nick Clifton <nickc@redhat.com>
* po/opcodes.pot: Regenerated.
2018-01-13 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
2018-01-13 Nick Clifton <nickc@redhat.com>
2.30 branch created.
2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
* i386-tbl.h: Regenerate.
2018-01-10 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
* i386-tbl.h: Re-generate.
2018-01-10 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
Disp8MemShift of AVX512VL forms.
* i386-tbl.h: Re-generate.
2018-01-09 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/22681
* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
Remove AVX512 vmovd with 64-bit operands.
* i386-tbl.h: Regenerated.
2018-01-05 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
jalr.
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
2018-01-02 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
and OPERAND_TYPE_REGZMM entries.
For older changes see ChangeLog-2017
Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
|
