1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
|
2021-05-17 Alex Coplan <alex.coplan@arm.com>
* arm-dis.c (mve_opcodes): Fix disassembly of
MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
(is_mve_encoding_conflict): MVE vector loads should not match
when P = W = 0.
(is_mve_unpredictable): It's not unpredictable to use the same
source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-11 Nick Clifton <nickc@redhat.com>
PR 27840
* tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
the end of the code buffer.
2021-05-06 Stafford Horne <shorne@gmail.com>
PR 21464
* or1k-asm.c: Regenerate.
2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
* xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
info->insn_info_valid.
2021-04-26 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (lea): Add Optimize.
* opcodes/i386-tbl.h: Re-generate.
2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
* xtensa-dis.c (print_xtensa_operand): For PC-relative operand
of l32r fetch and display referenced literal value.
2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
* xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
to 4 for literal disassembly.
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
for TLBI instruction.
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
DC instruction.
2021-04-19 Jan Beulich <jbeulich@suse.com>
* aarch64-asm.c (encode_asimd_fcvt): Add initializer for
"qualifier".
(convert_mov_to_movewide): Add initializer for "value".
2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add RME system registers.
2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
* riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
"addi d,CV,z" to "c.mv d,CV".
2021-04-12 Alan Modra <amodra@gmail.com>
* configure.ac (--enable-checking): Add support.
* config.in: Regenerate.
* configure: Regenerate.
2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
* aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
LD64/ST64 instructions to lse_atomic instead of ldstexcl.
2021-04-09 Alan Modra <amodra@gmail.com>
* ppc-dis.c (struct dis_private): Add "special".
(POWERPC_DIALECT): Delete. Replace uses with..
(private_data): ..this. New inline function.
(disassemble_init_powerpc): Init "special" names.
(skip_optional_operands): Add is_pcrel arg, set when detecting R
field of prefix instructions.
(bsearch_reloc, print_got_plt): New functions.
(print_insn_powerpc): For pcrel instructions, print target address
and symbol if known, and decode plt and got loads too.
2021-04-08 Alan Modra <amodra@gmail.com>
PR 27684
* ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
2021-04-08 Alan Modra <amodra@gmail.com>
PR 27676
* ppc-opc.c (DCBT_EO): Move earlier.
(insert_thct, extract_thct, insert_thds, extract_thds): New functions.
(powerpc_operands): Add THCT and THDS entries.
(powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
2021-04-06 Alan Modra <amodra@gmail.com>
* dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
* s12z-dis.c (decode_possible_symbol): Use symbol returned from
symbol_at_address_func.
2021-04-05 Alan Modra <amodra@gmail.com>
* configure.ac: Don't check for limits.h, string.h, strings.h or
stdlib.h.
(AC_ISC_POSIX): Don't invoke.
* sysdep.h: Include stdlib.h and string.h unconditionally.
* i386-opc.h: Include limits.h unconditionally.
* wasm32-dis.c: Likewise.
* cgen-opc.c: Don't include alloca-conf.h.
* config.in: Regenerate.
* configure: Regenerate.
2021-04-01 Martin Liska <mliska@suse.cz>
* arm-dis.c (strneq): Remove strneq and use startswith.
* cr16-dis.c (print_insn_cr16): Likewise.
* score-dis.c (streq): Likewise.
(strneq): Likewise.
* score7-dis.c (strneq): Likewise.
2021-04-01 Alan Modra <amodra@gmail.com>
PR 27675
* ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
2021-03-31 Alan Modra <amodra@gmail.com>
* sysdep.h (POISON_BFD_BOOLEAN): Define.
* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
and TRUE with true throughout.
2021-03-31 Alan Modra <amodra@gmail.com>
* aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
* aarch64-dis.h: Likewise.
* aarch64-opc.c: Likewise.
* avr-dis.c: Likewise.
* csky-dis.c: Likewise.
* nds32-asm.c: Likewise.
* nds32-dis.c: Likewise.
* nfp-dis.c: Likewise.
* riscv-dis.c: Likewise.
* s12z-dis.c: Likewise.
* wasm32-dis.c: Likewise.
2021-03-30 Jan Beulich <jbeulich@suse.com>
* i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
(i386_seg_prefixes): New.
* i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
(i386_seg_prefixes): Declare.
2021-03-30 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
2021-03-30 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
* i386-reg.tbl (st): Move down.
(st(0)): Delete. Extend comment.
* i386-tbl.h: Re-generate.
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movq, movabs): Move next to mov counterparts.
(cmpsd): Move next to cmps.
(movsd): Move next to movs.
(cmpxchg16b): Move to separate section.
(fisttp, fisttpll): Likewise.
(monitor, mwait): Likewise.
* i386-tbl.h: Re-generate.
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (psadbw): Add <sse2:comm>.
(vpsadbw): Add C.
* i386-tbl.h: Re-generate.
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
pclmul, gfni): New templates. Use them wherever possible. Move
SSE4.1 pextrw into respective section.
* i386-tbl.h: Re-generate.
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
strtoull(). Bump upper loop bound. Widen masks. Sanity check
"length".
* i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
Convert all of their uses to representation in opcode.
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (struct insn_template): Shrink base_opcode to 16
bits. Shrink extension_opcode to 9 bits. Make it signed. Change
value of None. Shrink operands to 3 bits.
2021-03-29 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (process_i386_opcode_modifier): New parameter
"space".
(output_i386_opcode): New local variable "space". Adjust
process_i386_opcode_modifier() invocation.
(process_i386_opcodes): Adjust process_i386_opcode_modifier()
invocation.
* i386-tbl.h: Re-generate.
2021-03-29 Alan Modra <amodra@gmail.com>
* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
(fp_qualifier_p, get_data_pattern): Likewise.
(aarch64_get_operand_modifier_from_value): Likewise.
(aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
(operand_variant_qualifier_p): Likewise.
(qualifier_value_in_range_constraint_p): Likewise.
(aarch64_get_qualifier_esize): Likewise.
(aarch64_get_qualifier_nelem): Likewise.
(aarch64_get_qualifier_standard_value): Likewise.
(get_lower_bound, get_upper_bound): Likewise.
(aarch64_find_best_match, match_operands_qualifier): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
(operand_need_sign_extension, operand_need_shift_by_two): Likewise.
(operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
* arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
* tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
(print_insn_tic6x): Likewise.
2021-03-29 Alan Modra <amodra@gmail.com>
* arc-dis.c (extract_operand_value): Correct NULL cast.
* frv-opc.h: Regenerate.
2021-03-26 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
MMX form.
* i386-tbl.h: Re-generate.
2021-03-25 Abid Qadeer <abidh@codesourcery.com>
* nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
immediate in br.n instruction.
2021-03-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (XMGatherD, VexGatherD): New.
(vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
(print_insn): Check masking for S/G insns.
(OP_E_memory): New local variable check_gather. Extend mandatory
SIB check. Check register conflicts for (EVEX-encoded) gathers.
Extend check for disallowed 16-bit addressing.
(OP_VEX): New local variables modrm_reg and sib_index. Convert
if()s to switch(). Check register conflicts for (VEX-encoded)
gathers. Drop no longer reachable cases.
* i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
vgatherdp*.
2021-03-25 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
zeroing-masking without masking.
2021-03-25 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (invlpgb): Fix multi-operand form.
(pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
single-operand forms as deprecated.
* i386-tbl.h: Re-generate.
2021-03-25 Alan Modra <amodra@gmail.com>
PR 27647
* ppc-opc.c (XLOCB_MASK): Delete.
(XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
XLBH_MASK.
(powerpc_opcodes): Accept a BH field on all extended forms of
bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
2021-03-24 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Drop processing of
opcode_length. Calculate length from base_opcode. Adjust prefix
encoding determination.
(process_i386_opcodes): Drop output of fake opcode_length.
* i386-opc.h (struct insn_template): Drop opcode_length field.
* i386-opc.tbl: Drop opcode length field from all templates.
* i386-tbl.h: Re-generate.
2021-03-24 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (process_i386_opcode_modifier): Return void. New
parameter "prefix". Drop local variable "regular_encoding".
Record prefix setting / check for consistency.
(output_i386_opcode): Parse opcode_length and base_opcode
earlier. Derive prefix encoding. Drop no longer applicable
consistency checking. Adjust process_i386_opcode_modifier()
invocation.
(process_i386_opcodes): Adjust process_i386_opcode_modifier()
invocation.
* i386-tbl.h: Re-generate.
2021-03-24 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
check.
* i386-opc.h (Prefix_*): Move #define-s.
* i386-opc.tbl: Move pseudo prefix enumerator values to
extension opcode field. Introduce pseudopfx template.
* i386-tbl.h: Re-generate.
2021-03-23 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
comment.
* i386-tbl.h: Re-generate.
2021-03-23 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (struct insn_template): Move cpu_flags field past
opcode_modifier one.
* i386-tbl.h: Re-generate.
2021-03-23 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (opcode_modifiers): New OpcodeSpace element.
* i386-opc.h (OpcodeSpace): New enumerator.
(VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
(SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
SPACE_XOP09, SPACE_XOP0A): ... respectively.
(struct i386_opcode_modifier): New field opcodespace. Shrink
opcodeprefix field.
i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
SpaceXOP09, SpaceXOP0A): Define. Use them to replace
OpcodePrefix uses.
* i386-tbl.h: Re-generate.
2021-03-22 Martin Liska <mliska@suse.cz>
* aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
* arc-dis.c (parse_option): Likewise.
* arm-dis.c (parse_arm_disassembler_options): Likewise.
* cris-dis.c (print_with_operands): Likewise.
* h8300-dis.c (bfd_h8_disassemble): Likewise.
* i386-dis.c (print_insn): Likewise.
* ia64-gen.c (fetch_insn_class): Likewise.
(parse_resource_users): Likewise.
(in_iclass): Likewise.
(lookup_specifier): Likewise.
(insert_opcode_dependencies): Likewise.
* mips-dis.c (parse_mips_ase_option): Likewise.
(parse_mips_dis_option): Likewise.
* s390-dis.c (disassemble_init_s390): Likewise.
* wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
2021-03-12 Alan Modra <amodra@gmail.com>
* i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
2021-03-11 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_XMM): Re-order checks.
2021-03-11 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (putop): Drop need_vex check when also checking
vex.evex.
(intel_operand_size, OP_E_memory): Drop vex.evex check when also
checking vex.b.
2021-03-11 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
checks. Move case label past broadcast check.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
EVEX_W_0F38C7_M_0_L_2): Delete.
(REG_EVEX_0F38C7_M_0_L_2): New.
(intel_operand_size): Handle VEX and EVEX the same for
vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
(OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
vex_vsib_q_w_d_mode uses.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
0F38A1, and 0F38A3 entries.
* i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
entry.
* i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
* i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
0F38A3 entries.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
MOD_VEX_0FXOP_09_12): Rename to ...
(REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
(MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
(reg_table): Adjust comments.
(x86_64_table): Move X86_64_0F24, X86_64_0F26,
X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
(xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
(vex_len_table): Adjust opcode 0A_12 entry.
(mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
MOD_C5_32BIT, and MOD_XOP_09_12 entries.
(rm_table): Move hreset entry.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
(EVEX_LEN_0F3816, EVEX_W_0FD6): New.
(get_valid_dis386): Also handle 512-bit vector length when
vectoring into vex_len_table[].
* i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
entries.
* i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
* i386-dis-evex-prefix.h: Adjust 0F7E entry.
* i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
entries.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
entries.
* i386-dis-evex-len.h (evex_len_table): Likewise.
* i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
EVEX_W_0F3A43_L_n): New.
* i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
* i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
* i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
0F385B, 0F38C6, and 0F38C7 entries.
* i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
0F38C6 and 0F38C7.
* i386-dis-evex-w.h: No longer link to evex_len_table[] for
opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0): Delete.
MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
(prefix_table): No longer link to vex_len_table[] for opcodes
0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
0F92, 0F93, 0F98, and 0F99.
(vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
(mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
0F98, and 0F99.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
REG_VEX_0F73_M_0 respectively.
(MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
MOD_VEX_0F73_REG_7): Delete.
(MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
(PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
PREFIX_VEX_0F3AF0_L_0 respectively.
(VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
(VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
VEX_LEN_0F38F7): New.
(VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
(reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
0F72, and 0F73. No longer link to vex_len_table[] for opcode
0F38F3.
(prefix_table): No longer link to vex_len_table[] for opcodes
0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
(vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
0F38F6, 0F38F7, and 0F3AF0.
(vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
(mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
0F73.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
(MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
(MOD_0F71, MOD_0F72, MOD_0F73): New.
(dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
73.
(reg_table): No longer link to mod_table[] for opcodes 0F71,
0F72, and 0F73.
(mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
0F73.
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
(reg_table): Don't link to mod_table[] where not needed. Add
PREFIX_IGNORED to nop entries.
(prefix_table): Replace PREFIX_OPCODE in nop entries.
(mod_table): Add nop entries next to prefetch ones. Drop
MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
(rm_table): Add PREFIX_IGNORED to nop entries. Drop
PREFIX_OPCODE from endbr* entries.
(get_valid_dis386): Also consider entry's name when zapping
vindex.
(print_insn): Handle PREFIX_IGNORED.
2021-03-09 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
element.
* opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
(PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
(struct i386_opcode_modifier): Delete notrackprefixok,
islockable, hleprefixok, and repprefixok fields. Add prefixok
field.
* opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
(mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
Replace HLEPrefixOk.
* opcodes/i386-tbl.h: Re-generate.
2021-03-09 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
* opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
64-bit form.
* opcodes/i386-tbl.h: Re-generate.
2021-03-03 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (output_i386_opcode): Don't get operand count. Look
for {} instead of {0}. Don't look for '0'.
* i386-opc.tbl: Drop operand count field. Drop redundant operand
size specifiers.
2021-02-19 Nelson Chu <nelson.chu@sifive.com>
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
2021-02-18 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
(default_priv_spec): Updated type to riscv_spec_class.
(parse_riscv_dis_option): Updated.
* riscv-opc.c: Moved stuff and make the file tidy.
2021-02-17 Alan Modra <amodra@gmail.com>
* wasm32-dis.c: Include limits.h.
(CHAR_BIT): Provide backup define.
(wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
Correct signed overflow checking.
2021-02-16 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
* i386-tbl.h: Re-generate.
2021-02-16 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
Oword.
* i386-opc.tbl (CpuFP, Mmword, Oword): Define.
2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch14 as cpu string.
* s390-opc.txt: Add new arch14 instructions.
2021-02-04 Nick Alcock <nick.alcock@oracle.com>
* configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
favour of LIBINTL.
* configure: Regenerated.
2021-02-08 Mike Frysinger <vapier@gentoo.org>
* tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
* tic54x-opc.c (regs): Rename to ...
(tic54x_regs): ... this.
(mmregs): Rename to ...
(tic54x_mmregs): ... this.
(condition_codes): Rename to ...
(tic54x_condition_codes): ... this.
(cc2_codes): Rename to ...
(tic54x_cc2_codes): ... this.
(cc3_codes): Rename to ...
(tic54x_cc3_codes): ... this.
(status_bits): Rename to ...
(tic54x_status_bits): ... this.
(misc_symbols): Rename to ...
(tic54x_misc_symbols): ... this.
2021-02-04 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (MASK_RVB_IMM): Removed.
(riscv_opcodes): Removed zb* instructions.
(riscv_ext_version_table): Removed versions for zb*.
2021-01-26 Alan Modra <amodra@gmail.com>
* i386-gen.c (parse_template): Ensure entire template_instance
is initialised.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
(riscv_fpr_names_abi): Likewise.
(riscv_opcodes): Likewise.
(riscv_insn_types): Likewise.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c: Comments tidy and improvement.
* riscv-opc.c: Likewise.
2021-01-13 Alan Modra <amodra@gmail.com>
* Makefile.in: Regenerate.
2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26792
* configure.ac: Use GNU_MAKE_JOBSERVER.
* aclocal.m4: Regenerated.
* configure: Likewise.
2021-01-12 Nick Clifton <nickc@redhat.com>
* po/sr.po: Updated Serbian translation.
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27173
* configure: Regenerated.
2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-opc.c (aarch64_print_operand):
Delete handling of AARCH64_OPND_CSRE_CSR.
* aarch64-tbl.h (aarch64_feature_csre): Delete.
(CSRE): Likewise.
(_CSRE_INSN): Likewise.
(aarch64_opcode_table): Delete csr.
2021-01-11 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/fr.po: Updated French translation.
* po/pt_BR.po: Updated Brazilian Portuguese translation.
* po/sv.po: Updated Swedish translation.
* po/uk.po: Updated Ukranian translation.
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
2021-01-09 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
2021-01-08 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (insert_dw, (extract_dw): New functions.
(DW, (XRC_MASK): Define.
(powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
2021-01-09 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2021-01-08 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
2021-01-08 Nick Clifton <nickc@redhat.com>
PR 27129
* aarch64-dis.c (determine_disassembling_preference): Move call to
aarch64_match_operands_constraint outside of the assertion.
* aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
Replace with a return of FALSE.
PR 27139
* aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
core system register.
2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
* configure: Regenerate.
2021-01-07 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
2021-01-07 Fredrik Noring <noring@nocrew.org>
* m68k-opc.c (chkl): Change minimum architecture requirement to
m68020.
2021-01-07 Philipp Tomsich <prt@gnu.org>
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
(MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2021-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
For older changes see ChangeLog-2020
Copyright (C) 2021 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
|
