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<target>
<xi:include href="core-regs.xml"/>
<feature name="extra">
<vector id="v4int8" type="int8" count="4"/>
<vector id="v2int16" type="int16" count="2"/>
<union id="vecint">
<field name="v4" type="v4int8"/>
<field name="v2" type="v2int16"/>
</union>
<struct id="struct1">
<field name="v4" type="v4int8"/>
<field name="v2" type="v2int16"/>
</struct>
<struct id="struct2" size="8">
<field name="f1" start="0" end="34"/>
<field name="f2" start="63" end="63"/>
</struct>
<flags id="flags" size="4">
<field name="X" start="0" end="0"/>
<field name="Y" start="2" end="2"/>
</flags>
<reg name="extrareg" bitsize="32"/>
<reg name="uintreg" bitsize="32" type="uint32"/>
<reg name="vecreg" bitsize="32" type="v4int8"/>
<reg name="unionreg" bitsize="32" type="vecint"/>
<reg name="structreg" bitsize="64" type="struct1"/>
<reg name="bitfields" bitsize="64" type="struct2"/>
<reg name="flags" bitsize="32" type="flags"/>
</feature>
</target>
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