1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
|
# Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
if $tracelevel then {
strace $tracelevel
}
#
# Test the use of VSX registers, for Powerpc.
#
if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
verbose "Skipping vsx register tests."
return
}
set testfile "vsx-regs"
set binfile ${objdir}/${subdir}/${testfile}
set srcfile ${testfile}.c
set compile_flags {debug nowarnings quiet}
if [get_compiler_info $binfile] {
warning "get_compiler failed"
return -1
}
if [test_compiler_info gcc*] {
set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
} elseif [test_compiler_info xlc*] {
set compile_flags "$compile_flags additional_flags=-qaltivec"
} else {
warning "unknown compiler"
return -1
}
if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
untested vsx-regs.exp
return -1
}
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${binfile}
# Run to `main' where we begin our tests.
if ![runto_main] then {
gdb_suppress_tests
}
# Data sets used throughout the test
set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
set float_register ".raw 0xdeadbeefdeadbeef."
# First run the F0~F31/VS0~VS31 tests
# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
for {set i 0} {$i < 32} {incr i 1} {
gdb_test_no_output "set \$f$i = 1\.3"
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
}
# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
for {set i 0} {$i < 32} {incr i 1} {
for {set j 0} {$j < 4} {incr j 1} {
gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
}
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
}
# Now run the VR0~VR31/VS32~VS63 tests
# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
for {set i 0} {$i < 32} {incr i 1} {
for {set j 0} {$j < 4} {incr j 1} {
gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
}
}
for {set i 32} {$i < 64} {incr i 1} {
gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
}
# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
for {set i 32} {$i < 64} {incr i 1} {
for {set j 0} {$j < 4} {incr j 1} {
gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
}
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
}
# Create a core file. We create the core file before the F32~F63/VR0~VR31 test
# below because then we'll have more interesting register values to verify
# later when loading the core file (i.e., different register values for different
# vector register banks).
set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]
set core_supported 0
gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
"Save a VSX-enabled corefile" \
{
-re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" {
pass "Save a VSX-enabled corefile"
global core_supported
set core_supported 1
}
-re "Can't create a corefile\[\r\n\]+$gdb_prompt $" {
unsupported "Save a VSX-enabled corefile"
global core_supported
set core_supported 0
}
}
# Now run the F32~F63/VR0~VR31 tests.
# 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
for {set i 32} {$i < 64} {incr i 1} {
gdb_test_no_output "set \$f$i = 1\.3"
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
}
# 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
for {set i 0} {$i < 32} {incr i 1} {
for {set j 0} {$j < 4} {incr j 1} {
gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
}
}
for {set i 32} {$i < 64} {incr i 1} {
gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
}
# Test reading the core file.
if {!$core_supported} {
return -1
}
gdb_exit
gdb_start
gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${binfile}
gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \
"re-load generated corefile" \
{
-re ".* is not a core dump:.*$gdb_prompt $" {
fail "re-load generated corefile (bad file format)"
# No use proceeding from here.
return;
}
-re ".*: No such file or directory.*$gdb_prompt $" {
fail "re-load generated corefile (file not found)"
# No use proceeding from here.
return;
}
-re ".*Couldn't find .* registers in core file.*$gdb_prompt $" {
fail "re-load generated corefile (incomplete note section)"
}
-re "Core was generated by .*$gdb_prompt $" {
pass "re-load generated corefile"
}
-re ".*$gdb_prompt $" {
fail "re-load generated corefile"
}
timeout {
fail "re-load generated corefile (timeout)"
}
}
for {set i 0} {$i < 32} {incr i 1} {
gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file"
}
for {set i 32} {$i < 64} {incr i 1} {
gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file"
}
|
