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/* vms.h -- Header file for VMS (Alpha and Vax) support.
   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007
   Free Software Foundation, Inc.

   Written by Klaus K"ampf (kkaempf@rmi.de)

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#undef vms
#ifndef VMS_H
#define VMS_H

/* Constants starting with 'Exxx_' are for openVMS/Alpha (EVAX object language)  */

/* VMS Text, information and relocation record (TIR/ETIR) definitions.  */

#define TIR_S_C_STA_GBL		0
#define TIR_S_C_STA_SB		1
#define TIR_S_C_STA_SW		2
#define TIR_S_C_STA_LW		3
#define TIR_S_C_STA_PB		4
#define TIR_S_C_STA_PW		5
#define TIR_S_C_STA_PL		6
#define TIR_S_C_STA_UB  	7
#define TIR_S_C_STA_UW  	8
#define TIR_S_C_STA_BFI 	9
#define TIR_S_C_STA_WFI 	10
#define TIR_S_C_STA_LFI 	11
#define TIR_S_C_STA_EPM 	12
#define TIR_S_C_STA_CKARG       13
#define TIR_S_C_STA_WPB 	14
#define TIR_S_C_STA_WPW 	15
#define TIR_S_C_STA_WPL 	16
#define TIR_S_C_STA_LSY 	17
#define TIR_S_C_STA_LIT 	18
#define TIR_S_C_STA_LEPM        19
#define TIR_S_C_MAXSTACOD       19
#define TIR_S_C_MINSTOCOD       20
#define TIR_S_C_STO_SB  	20
#define TIR_S_C_STO_SW  	21
#define TIR_S_C_STO_L   	22
#define TIR_S_C_STO_LW  	22
#define TIR_S_C_STO_BD  	23
#define TIR_S_C_STO_WD  	24
#define TIR_S_C_STO_LD  	25
#define TIR_S_C_STO_LI  	26
#define TIR_S_C_STO_PIDR        27
#define TIR_S_C_STO_PICR        28
#define TIR_S_C_STO_RSB 	29
#define TIR_S_C_STO_RSW 	30
#define TIR_S_C_STO_RL  	31
#define TIR_S_C_STO_VPS 	32
#define TIR_S_C_STO_USB 	33
#define TIR_S_C_STO_USW 	34
#define TIR_S_C_STO_RUB 	35
#define TIR_S_C_STO_RUW 	36
#define TIR_S_C_STO_B   	37
#define TIR_S_C_STO_W   	38
#define TIR_S_C_STO_RB  	39
#define TIR_S_C_STO_RW  	40
#define TIR_S_C_STO_RIVB        41
#define TIR_S_C_STO_PIRR        42
#define TIR_S_C_MAXSTOCOD       42
#define TIR_S_C_MINOPRCOD       50
#define TIR_S_C_OPR_NOP 	50
#define TIR_S_C_OPR_ADD 	51
#define TIR_S_C_OPR_SUB 	52
#define TIR_S_C_OPR_MUL 	53
#define TIR_S_C_OPR_DIV 	54
#define TIR_S_C_OPR_AND 	55
#define TIR_S_C_OPR_IOR 	56
#define TIR_S_C_OPR_EOR 	57
#define TIR_S_C_OPR_NEG 	58
#define TIR_S_C_OPR_COM 	59
#define TIR_S_C_OPR_INSV        60
#define TIR_S_C_OPR_ASH 	61
#define TIR_S_C_OPR_USH 	62
#define TIR_S_C_OPR_ROT 	63
#define TIR_S_C_OPR_SEL 	64
#define TIR_S_C_OPR_REDEF       65
#define TIR_S_C_OPR_DFLIT       66
#define TIR_S_C_MAXOPRCOD       66
#define TIR_S_C_MINCTLCOD       80
#define TIR_S_C_CTL_SETRB       80
#define TIR_S_C_CTL_AUGRB       81
#define TIR_S_C_CTL_DFLOC       82
#define TIR_S_C_CTL_STLOC       83
#define TIR_S_C_CTL_STKDL       84
#define TIR_S_C_MAXCTLCOD       84

#define ETIR_S_C_MINSTACOD 0		/* Minimum store code.		*/
#define ETIR_S_C_STA_GBL 0		/* Stack global symbol value.	*/
#define ETIR_S_C_STA_LW 1		/* Stack longword.		*/
#define ETIR_S_C_STA_QW 2		/* Stack quadword.		*/
#define ETIR_S_C_STA_PQ 3		/* Stack psect base plus quadword offset.  */
#define ETIR_S_C_STA_LI 4		/* Stack literal.		*/
#define ETIR_S_C_STA_MOD 5		/* Stack module.		*/
#define ETIR_S_C_STA_CKARG 6		/* Check Arguments.		*/
#define ETIR_S_C_MAXSTACOD 6		/* Maximum stack code.		*/
#define ETIR_S_C_MINSTOCOD 50		/* Minimum store code.		*/
#define ETIR_S_C_STO_B 50		/* Store byte.			*/
#define ETIR_S_C_STO_W 51		/* Store word.			*/
#define ETIR_S_C_STO_LW 52		/* Store longword.		*/
#define ETIR_S_C_STO_QW 53		/* Store quadword.		*/
#define ETIR_S_C_STO_IMMR 54		/* Store immediate Repeated.	*/
#define ETIR_S_C_STO_GBL 55		/* Store global.		*/
#define ETIR_S_C_STO_CA 56		/* Store code address.		*/
#define ETIR_S_C_STO_RB 57		/* Store relative branch.	*/
#define ETIR_S_C_STO_AB 58		/* Store absolute branch.	*/
#define ETIR_S_C_STO_OFF 59		/* Store offset within psect.	*/
#define ETIR_S_C_STO_IMM 61		/* Store immediate.		*/
#define ETIR_S_C_STO_GBL_LW 62		/* Store global Longword.	*/
#define ETIR_S_C_STO_LP_PSB 63		/* STO_LP_PSB not valid in level 2 use STC_LP_PSB.  */
#define ETIR_S_C_STO_HINT_GBL 64	/* Store 14 bit HINT at global address.  */
#define ETIR_S_C_STO_HINT_PS 65		/* Store 14 bit HINT at psect + offset */
#define ETIR_S_C_MAXSTOCOD 65		/* Maximum store code.		*/
#define ETIR_S_C_MINOPRCOD 100		/* Minimum operate code.	*/
#define ETIR_S_C_OPR_NOP 100		/* No-op.			*/
#define ETIR_S_C_OPR_ADD 101		/* Add.				*/
#define ETIR_S_C_OPR_SUB 102		/* Subtract.			*/
#define ETIR_S_C_OPR_MUL 103		/* Multiply.			*/
#define ETIR_S_C_OPR_DIV 104		/* Divide.			*/
#define ETIR_S_C_OPR_AND 105		/* Logical AND.			*/
#define ETIR_S_C_OPR_IOR 106		/* Logical inclusive OR.	*/
#define ETIR_S_C_OPR_EOR 107		/* Logical exclusive OR.	*/
#define ETIR_S_C_OPR_NEG 108		/* Negate.			*/
#define ETIR_S_C_OPR_COM 109		/* Complement.			*/
#define ETIR_S_C_OPR_INSV 110		/* Insert bit field.		*/
#define ETIR_S_C_OPR_ASH 111		/* Arithmetic shift.		*/
#define ETIR_S_C_OPR_USH 112		/* Unsigned shift.		*/
#define ETIR_S_C_OPR_ROT 113		/* Rotate.			*/
#define ETIR_S_C_OPR_SEL 114		/* Select one of three longwords on top of stack.   */
#define ETIR_S_C_OPR_REDEF 115		/* Redefine this symbol after pass 2.  */
#define ETIR_S_C_OPR_DFLIT 116		/* Define a literal.		*/
#define ETIR_S_C_MAXOPRCOD 116		/* Maximum operate code.	*/
#define ETIR_S_C_MINCTLCOD 150		/* Minimum control code.	*/
#define ETIR_S_C_CTL_SETRB 150		/* Set relocation base.		*/
#define ETIR_S_C_CTL_AUGRB 151		/* Augment relocation base.	*/
#define ETIR_S_C_CTL_DFLOC 152		/* Define debug location.	*/
#define ETIR_S_C_CTL_STLOC 153		/* Set debug location.		*/
#define ETIR_S_C_CTL_STKDL 154		/* Stack debug location.	*/
#define ETIR_S_C_MAXCTLCOD 154		/* Maximum control code.	*/
#define ETIR_S_C_MINSTCCOD 200		/* Minimum store-conditional code.   */
#define ETIR_S_C_STC_LP 200		/* Store-conditional Linkage Pair.   */
#define ETIR_S_C_STC_LP_PSB 201		/* Store-conditional Linkage Pair with Procedure Signature.  */
#define ETIR_S_C_STC_GBL 202		/* Store-conditional Address at global address.  */
#define ETIR_S_C_STC_GCA 203		/* Store-conditional Code Address at global address.  */
#define ETIR_S_C_STC_PS 204		/* Store-conditional Address at psect + offset.  */
#define ETIR_S_C_STC_NOP_GBL 205	/* Store-conditional NOP at address of global.  */
#define ETIR_S_C_STC_NOP_PS 206		/* Store-conditional NOP at pect + offset.  */
#define ETIR_S_C_STC_BSR_GBL 207	/* Store-conditional BSR at global address.  */
#define ETIR_S_C_STC_BSR_PS 208		/* Store-conditional BSR at pect + offset.  */
#define ETIR_S_C_STC_LDA_GBL 209	/* Store-conditional LDA at global address.  */
#define ETIR_S_C_STC_LDA_PS 210		/* Store-conditional LDA at psect + offset.  */
#define ETIR_S_C_STC_BOH_GBL 211	/* Store-conditional BSR or Hint at global address.  */
#define ETIR_S_C_STC_BOH_PS 212		/* Store-conditional BSR or Hint at pect + offset.  */
#define ETIR_S_C_STC_NBH_GBL 213	/* Store-conditional NOP,BSR or HINT at global address.  */
#define ETIR_S_C_STC_NBH_PS 214		/* Store-conditional NOP,BSR or HINT at psect + offset.  */
#define ETIR_S_C_MAXSTCCOD 214		/* Maximum store-conditional code.   */

/* VMS Global symbol definition record (GSD/EGSD).  */

#define GSD_S_K_ENTRIES 1
#define GSD_S_C_ENTRIES 1
#define GSD_S_C_PSC     0
#define GSD_S_C_SYM     1
#define GSD_S_C_EPM     2
#define GSD_S_C_PRO     3
#define GSD_S_C_SYMW    4
#define GSD_S_C_EPMW    5
#define GSD_S_C_PROW    6
#define GSD_S_C_IDC     7
#define GSD_S_C_ENV     8
#define GSD_S_C_LSY     9
#define GSD_S_C_LEPM    10
#define GSD_S_C_LPRO    11
#define GSD_S_C_SPSC    12
#define GSD_S_C_SYMV    13
#define GSD_S_C_EPMV    14
#define GSD_S_C_PROV    15
#define GSD_S_C_MAXRECTYP       15

#define EGSD_S_K_ENTRIES 2	/* Offset to first entry in record.	*/
#define EGSD_S_C_ENTRIES 2	/* Offset to first entry in record.	*/
#define EGSD_S_C_PSC 0		/* Psect definition.			*/
#define EGSD_S_C_SYM 1		/* Symbol specification.		*/
#define EGSD_S_C_IDC 2		/* Random entity check.			*/
#define EGSD_S_C_SPSC 5		/* Shareable image psect definition.	*/
#define EGSD_S_C_SYMV 6		/* Vectored (dual-valued) versions of SYM.  */
#define EGSD_S_C_SYMM 7		/* Masked versions of SYM.		*/
#define EGSD_S_C_SYMG 8		/* EGST - gst version of SYM.		*/
#define EGSD_S_C_MAXRECTYP 8	/* Maximum entry type defined.		*/

#define GPS_S_M_PIC     1
#define GPS_S_M_LIB     2
#define GPS_S_M_OVR     4
#define GPS_S_M_REL     8
#define GPS_S_M_GBL     16
#define GPS_S_M_SHR     32
#define GPS_S_M_EXE     64
#define GPS_S_M_RD      128
#define GPS_S_M_WRT     256
#define GPS_S_M_VEC     512
#define GPS_S_K_NAME    9
#define GPS_S_C_NAME    9

#define EGPS_S_V_PIC	0x0001
#define EGPS_S_V_LIB	0x0002
#define EGPS_S_V_OVR	0x0004
#define EGPS_S_V_REL	0x0008
#define EGPS_S_V_GBL	0x0010
#define EGPS_S_V_SHR	0x0020
#define EGPS_S_V_EXE	0x0040
#define EGPS_S_V_RD	0x0080
#define EGPS_S_V_WRT	0x0100
#define EGPS_S_V_VEC	0x0200
#define EGPS_S_V_NOMOD	0x0400
#define EGPS_S_V_COM	0x0800

#define GSY_S_M_WEAK    1
#define GSY_S_M_DEF     2
#define GSY_S_M_UNI     4
#define GSY_S_M_REL     8

#define EGSY_S_V_WEAK	0x0001
#define EGSY_S_V_DEF	0x0002
#define EGSY_S_V_UNI	0x0004
#define EGSY_S_V_REL	0x0008
#define EGSY_S_V_COMM	0x0010
#define EGSY_S_V_VECEP	0x0020
#define EGSY_S_V_NORM	0x0040

#define LSY_S_M_DEF     2
#define LSY_S_M_REL     8

#define ENV_S_M_DEF     1
#define ENV_S_M_NESTED  2

/* Debugger symbol definitions:  These are done by hand,
   as no machine-readable version seems to be available.  */
#define DST_S_C_C		  7	/* Language == "C".	*/
#define DST_S_C_CXX		 15	/* Language == "C++".	*/
#define DST_S_C_VERSION		153
#define	DST_S_C_SOURCE		155	/* Source file.		*/
#define DST_S_C_PROLOG		162
#define	DST_S_C_BLKBEG		176	/* Beginning of block.	*/
#define	DST_S_C_BLKEND		177	/* End of block.	*/
#define DST_S_C_ENTRY		181
#define DST_S_C_PSECT		184
#define	DST_S_C_LINE_NUM	185	/* Line Number.		*/
#define DST_S_C_LBLORLIT	186
#define DST_S_C_LABEL		187
#define	DST_S_C_MODBEG		188	/* Beginning of module. */
#define	DST_S_C_MODEND		189	/* End of module.	*/
#define	DST_S_C_RTNBEG		190	/* Beginning of routine.*/
#define	DST_S_C_RTNEND		191	/* End of routine.	*/
#define	DST_S_C_DELTA_PC_W	1	/* Incr PC.		*/
#define	DST_S_C_INCR_LINUM	2	/* Incr Line #. 	*/
#define	DST_S_C_INCR_LINUM_W	3	/* Incr Line #. 	*/
#define DST_S_C_SET_LINUM_INCR	4
#define DST_S_C_SET_LINUM_INCR_W 5
#define DST_S_C_RESET_LINUM_INCR 6
#define DST_S_C_BEG_STMT_MODE	7
#define DST_S_C_END_STMT_MODE	8
#define	DST_S_C_SET_LINE_NUM	9	/* Set Line #.		*/
#define DST_S_C_SET_PC		10
#define DST_S_C_SET_PC_W	11
#define DST_S_C_SET_PC_L	12
#define DST_S_C_SET_STMTNUM	13
#define DST_S_C_TERM		14	/* End of lines.	*/
#define DST_S_C_TERM_W		15	/* End of lines.	*/
#define	DST_S_C_SET_ABS_PC	16	/* Set PC.		*/
#define	DST_S_C_DELTA_PC_L	17	/* Incr PC.		*/
#define DST_S_C_INCR_LINUM_L	18	/* Incr Line #.		*/
#define DST_S_C_SET_LINUM_B	19	/* Set Line #.		*/
#define DST_S_C_SET_LINUM_L	20	/* Set Line #.		*/
#define	DST_S_C_TERM_L		21	/* End of lines.	*/
/* These are used with DST_S_C_SOURCE */
#define DST_S_C_SRC_DECLFILE	 1	/* Declare source file.  */
#define DST_S_C_SRC_SETFILE	 2	/* Set source file.	 */
#define DST_S_C_SRC_SETREC_L	 3	/* Set record, longword value.  */
#define DST_S_C_SRC_SETREC_W	 4	/* Set record, word value.  */
#define DST_S_C_SRC_DEFLINES_W	10	/* # of line, word counter.  */
#define DST_S_C_SRC_DEFLINES_B	11	/* # of line, byte counter.  */
#define DST_S_C_SRC_FORMFEED	16	/* ^L counts as a record.  */
/* The following are the codes for the various data types.  Anything not on
   the list is included under 'advanced_type'.  */
#define DBG_S_C_UCHAR		0x02
#define DBG_S_C_USINT		0x03
#define DBG_S_C_ULINT		0x04
#define DBG_S_C_UQUAD		0x05
#define DBG_S_C_SCHAR		0x06
#define DBG_S_C_SSINT		0x07
#define DBG_S_C_SLINT		0x08
#define DBG_S_C_SQUAD		0x09
#define DBG_S_C_REAL4		0x0a
#define DBG_S_C_REAL8		0x0b	/* D_float double.  */
#define DBG_S_C_COMPLX4		0x0c	/* 2xF_float complex float.  */
#define DBG_S_C_COMPLX8		0x0d	/* 2xD_float complex double.  */
#define DBG_S_C_REAL8_G		0x1b	/* G_float double.  */
#define DBG_S_C_COMPLX8_G	0x1d	/* 2xG_float complex double.  */
#define DBG_S_C_FUNCTION_ADDR	0x17
#define DBG_S_C_ADVANCED_TYPE	0xa3
/*  Some of these are just for future reference.  [pr].  */
#define DBG_S_C_UBITA		0x01	/* Unsigned, aligned bit field.  */
#define DBG_S_C_UBITU		0x22	/* Unsigned, unaligned bit field.  */
#define DBG_S_C_SBITA		0x29	/* Signed, aligned bit field.  */
#define DBG_S_C_SBITU		0x2a	/* Signed, unaligned bit field.  */
#define DBG_S_C_CSTRING		0x2e	/* Asciz ('\0' terminated) string.  */
#define DBG_S_C_WCHAR		0x38	/* Wchar_t.  */
/*  These are descriptor class codes.  */
#define DSC_K_CLASS_S		0x01	/* Static (fixed length).  */
#define DSC_K_CLASS_D		0x02	/* Dynamic string (not via malloc!).  */
#define DSC_K_CLASS_A		0x04	/* Array.  */
#define DSC_K_CLASS_UBS		0x0d	/* Unaligned bit string.  */
/*  These are the codes that are used to generate the definitions of struct
    union and enum records.  */
#define DBG_S_C_ENUM_ITEM		0xa4
#define DBG_S_C_ENUM_START		0xa5
#define DBG_S_C_ENUM_END		0xa6
#define DBG_S_C_STRUCT_ITEM		DST_K_VFLAGS_BITOFFS	/* 0xff */
#define DBG_S_C_STRUCT_START		0xab
#define DBG_S_C_STRUCT_END		0xac
#define DST_K_TYPSPEC			0xaf		/* Type specification.  */
/* These codes are used in the generation of the symbol definition records.  */
#define DST_K_VFLAGS_NOVAL		0x80	/* Struct definition only.  */
#define DST_K_VFLAGS_DSC		0xfa	/* Descriptor used.  */
#define DST_K_VFLAGS_TVS		0xfb	/* Trailing value specified.  */
#define DST_K_VS_FOLLOWS		0xfd	/* Value spec follows.  */
#define DST_K_VFLAGS_BITOFFS		0xff	/* Value contains bit offset.  */
#define DST_K_VALKIND_LITERAL	0
#define DST_K_VALKIND_ADDR	1
#define DST_K_VALKIND_DESC	2
#define DST_K_VALKIND_REG	3
#define DST_K_REG_VAX_AP	0x0c	/* R12.  */
#define DST_K_REG_VAX_FP	0x0d	/* R13.  */
#define DST_K_REG_VAX_SP	0x0e	/* R14.  */
#define DST_V_VALKIND		0	/* Offset of valkind field.  */
#define DST_V_INDIRECT		2	/* Offset to indirect bit.  */
#define DST_V_DISP		3	/* Offset to displacement bit.  */
#define DST_V_REGNUM		4	/* Offset to register number.  */
#define DST_M_INDIRECT		(1<<DST_V_INDIRECT)
#define DST_M_DISP		(1<<DST_V_DISP)
#define DBG_C_FUNCTION_PARAM	/* 0xc9 */	\
	(DST_K_VALKIND_ADDR|DST_M_DISP|(DST_K_REG_VAX_AP<<DST_V_REGNUM))
#define DBG_C_LOCAL_SYM		/* 0xd9 */	\
	(DST_K_VALKIND_ADDR|DST_M_DISP|(DST_K_REG_VAX_FP<<DST_V_REGNUM))
/* Kinds of value specifications.   */
#define DST_K_VS_ALLOC_SPLIT	3	/* Split lifetime.  */
/* Kinds of type specifications.  */
#define DST_K_TS_ATOM		0x01	/* Atomic type specification.  */
#define DST_K_TS_DSC		0x02	/* Descriptor type spec.  */
#define DST_K_TS_IND		0x03	/* Indirect type specification.  */
#define DST_K_TS_TPTR		0x04	/* Typed pointer type spec.  */
#define DST_K_TS_PTR		0x05	/* Pointer type spec.  */
#define DST_K_TS_ARRAY		0x07	/* Array type spec.  */
#define DST_K_TS_NOV_LENG	0x0e	/* Novel length type spec.  */
/* These are the codes that are used in the suffix records to determine the
   actual data type.  */
#define DBG_S_C_BASIC			DST_K_TS_ATOM
#define DBG_S_C_BASIC_ARRAY		DST_K_TS_DSC
#define DBG_S_C_STRUCT			DST_K_TS_IND
#define DBG_S_C_POINTER			DST_K_TS_TPTR
#define DBG_S_C_VOID			DST_K_TS_PTR
#define DBG_S_C_COMPLEX_ARRAY		DST_K_TS_ARRAY

/* VMS Module header record (EMH) definitions.  */

#define MHD_S_C_MHD 0
#define MHD_S_C_LNM 1
#define MHD_S_C_SRC 2
#define MHD_S_C_TTL 3
#define MHD_S_C_CPR 4
#define MHD_S_C_MTC 5
#define MHD_S_C_GTX 6
#define MHD_S_C_MAXHDRTYP 6

#define EMH_S_C_MHD 0		/* Main header record.		*/
#define EMH_S_C_LNM 1		/* Language name and version.	*/
#define EMH_S_C_SRC 2		/* Source file specification.	*/
#define EMH_S_C_TTL 3		/* Title text of module.	*/
#define EMH_S_C_CPR 4		/* Copyright notice.		*/
#define EMH_S_C_MTC 5		/* Maintenance status.		*/
#define EMH_S_C_GTX 6		/* General text.		*/
#define EMH_S_C_MAXHDRTYP 6	/* Maximum allowable type.	*/

/* vms.c.  */

extern asymbol *_bfd_vms_make_empty_symbol (bfd *);

/* vms-gsd.c.  */

extern int _bfd_vms_slurp_gsd (bfd *, int);
extern int _bfd_vms_write_gsd (bfd *, int);

/* vms-mhd.c.  */

extern int _bfd_vms_slurp_hdr (bfd *, int);
extern int _bfd_vms_write_hdr (bfd *, int);
extern int _bfd_vms_slurp_eom (bfd *, int);
extern int _bfd_vms_write_eom (bfd *, int);

/* vms-tir.c.  */

extern int _bfd_vms_slurp_tir (bfd *, int);
extern int _bfd_vms_slurp_dbg (bfd *, int);
extern int _bfd_vms_slurp_tbt (bfd *, int);
extern int _bfd_vms_slurp_lnk (bfd *, int);
				    	 
extern int _bfd_vms_write_tir (bfd *, int);
extern int _bfd_vms_write_tbt (bfd *, int);
extern int _bfd_vms_write_dbg (bfd *, int);
					 
/* The r_type field in a reloc is one of he following values.  */
#define ALPHA_R_IGNORE		0	 
#define ALPHA_R_REFQUAD		1	 
#define ALPHA_R_BRADDR		2	 
#define ALPHA_R_HINT		3	 
#define ALPHA_R_SREL16		4	 
#define ALPHA_R_SREL32		5	 
#define ALPHA_R_SREL64		6	 
#define ALPHA_R_OP_PUSH		7	 
#define ALPHA_R_OP_STORE	8	 
#define ALPHA_R_OP_PSUB		9	 
#define ALPHA_R_OP_PRSHIFT	10	 
#define ALPHA_R_LINKAGE		11	 
#define ALPHA_R_REFLONG		12	 
#define ALPHA_R_CODEADDR	13	 
					 
/* Object language definitions.  */	 
					 
#define OBJ_S_C_HDR 0		/* VAX moule header record.		*/
#define OBJ_S_C_GSD 1		/* VAX glbal symbol definition record.	*/
#define OBJ_S_C_TIR 2		/* VAX tet information record.		*/
#define OBJ_S_C_EOM 3		/* VAX en of module record.		*/
#define OBJ_S_C_DBG 4		/* VAX Deugger information record.	*/
#define OBJ_S_C_TBT 5		/* VAX Trceback information record.	*/
#define OBJ_S_C_LNK 6		/* VAX liker options record.		*/
#define OBJ_S_C_EOMW 7		/* VAX en of module word-psect record.	*/
#define OBJ_S_C_MAXRECTYP 7	/* VAX Lat assigned record type.	*/
#define EOBJ_S_C_EMH 8		/* EVAX mdule header record.		*/
#define EOBJ_S_C_EEOM 9		/* EVAX ed of module record.		*/
#define EOBJ_S_C_EGSD 10	/* EVAX gobal symbol definition record.*/
#define EOBJ_S_C_ETIR 11	/* EVAX txt information record.	*/
#define EOBJ_S_C_EDBG 12	/* EVAX Dbugger information record.	*/
#define EOBJ_S_C_ETBT 13	/* EVAX Taceback information record.	*/
#define EOBJ_S_C_MAXRECTYP 13	/* EVAX Lst assigned record type.	*/
#define OBJ_S_K_SUBTYP 1		 
#define OBJ_S_C_SUBTYP 1		 
#define EOBJ_S_K_SUBTYP 4		 
#define EOBJ_S_C_SUBTYP 4		 
#define OBJ_S_C_MAXRECSIZ 2048	/* Maximu legal record size.           */
#define EOBJ_S_C_MAXRECSIZ 8192 /* Maximu legal record size.           */
#define OBJ_S_C_STRLVL 0	/* Structre level.                     */
#define EOBJ_S_C_STRLVL 2	/* Structre level.                     */
#define OBJ_S_C_SYMSIZ 31	/* Maximu symbol length.		*/
#define EOBJ_S_C_SYMSIZ 64	/* Maximu symbol length.		*/
#define EOBJ_S_C_SECSIZ 31	/* Maximu section name length.		*/
#define OBJ_S_C_STOREPLIM -1	/* Maximu repeat count on store commands.  */
#define EOBJ_S_C_STOREPLIM -1	/* Maximu repeat count on store commands.  */
#define OBJ_S_C_PSCALILIM 9	/* Maximu p-sect alignment.            */
#define EOBJ_S_C_PSCALILIM 16	/* Maximu p-sect alignment.            */
					 
#define EVAX_OFFSET	256	/* Type ofset for EVAX codes in switch.  */
/* Miscellaneous definitions.  */	 

#if __GNUC__				 
typedef unsigned long long uquad;	 
#else					 
typedef unsigned long uquad;		 
#endif					 
					 
#define MAX_OUTREC_SIZE 4096		 
#define MIN_OUTREC_LUFT 64		 
					 
typedef struct _vms_section		 
{					 
  unsigned char *contents;		 
  bfd_vma offset;			 
  bfd_size_type size;			 
  struct _vms_section *next;		 
} vms_section;				 
					 
extern vms_section * _bfd_get_vms_section (bfd *, int);
					 
typedef struct _vms_reloc		 
{					 
  struct _vms_reloc *next;		 
  arelent *reloc;			 
  asection *section;			 
} vms_reloc;				 
					 
/* VMS module header.  */		 
					 
struct hdr_struc			 
{					 
  int    hdr_b_strlvl;			 
  long   hdr_l_arch1;			 
  long   hdr_l_arch2;			 
  long   hdr_l_recsiz;			 
  char * hdr_t_name;			 
  char * hdr_t_version;			 
  char * hdr_t_date;			 
  char * hdr_c_lnm;			 
  char * hdr_c_src;			 
  char * hdr_c_ttl;			 
};					 
					 
/* VMS end of module.  */		 
					 
struct eom_struc			 
{					 
  long          eom_l_total_lps;	 
  unsigned char eom_b_comcod;		 
  bfd_boolean   eom_has_transfer;	 
  unsigned char eom_b_tfrflg;		 
  long          eom_l_psindx;		 
  long          eom_l_tfradr;		 
};					 
					 
enum file_format_enum { FF_UNKNOWN, FF_FOREIGN, FF_NATIVE, FF_VAX };
					 
typedef struct vms_symbol_struct	 
{					 
  struct bfd_hash_entry bfd_hash;	 
  asymbol *symbol;			 
} vms_symbol_entry;			 
					 
/* Stack value for push/pop commands.  */
					 
struct stack_struct			 
{					 
  uquad value;				 
  int psect;				 
};					 
#define STACKSIZE 8192			 
					 
/* location stack definitions for CTL_DFLC, CTL_STLOC, and CTL_STKDL  */
					 
struct location_struct			 
{					 
  unsigned long value;			 
  int psect;				 
};					 
#define LOCATION_SAVE_SIZE 32		 
					 
#define VMS_SECTION_COUNT 1024		 
					 
struct vms_private_data_struct		 
{					 
  bfd_boolean is_vax;				 
  bfd_boolean fixup_done;		/* Flag to indicate if all
					   section pointers and PRIV(sections)
					   are set up correctly.  */
  unsigned char *vms_buf;		/* Buffer to record.  */
  int buf_size;				/* Max size of buffer.  */
  unsigned char *vms_rec;		/* Actual record ptr.  */
  int rec_length;			/* Remaining record length.  */
  int rec_size;				/* Actual record size.  */
  int rec_type;				/* Actual record type.  */
  enum file_format_enum file_format;	 
					 
  struct hdr_struc hdr_data;		/* Data from HDR/EMH record.  */
  struct eom_struc eom_data;		/* Data from EOM/EEOM record.  */
  unsigned int section_count;		/* # of sections in following array.  */
  asection **sections;			/* Array of GSD/EGSD sections.  */
  int gsd_sym_count;			/* # of GSD/EGSD symbols.  */
  asymbol **symbols;			/* Vector of GSD/EGSD symbols.  */
  struct proc_value *procedure;		 
					 
  struct stack_struct *stack;		 
  int stackptr;				 
					 
  vms_section *vms_section_table[VMS_SECTION_COUNT];
					 
  struct bfd_hash_table *vms_symbol_table;
  struct bfd_symbol **symcache;		 
  int symnum;				 
					 
  struct location_struct *location_stack;
					 
  asection *image_section;		/* Section for image_ptr.  */
  unsigned char *image_ptr;		/* A pointer to section->contents.  */
					 
  unsigned char pdsc[8];		/* Procedure descriptor.  */
					 
  /* Output routine storage.  */	 
  unsigned char *output_buf;		/* Output data.  */
  int push_level;			 
  int pushed_size;			 
  int length_pos;			 
  int output_size;			 
  int output_alignment;			 
					 
  /* Linkage index counter		 
     used by conditional store commands (TIR_S_C_STC_).   */
  int vms_linkage_index;		 
					 
  /* see tc-alpha.c of gas for a descripton.  */
  int flag_hash_long_names;	/* -+, hash instead of truncate.  */
  int flag_show_after_trunc;	/* -H, shw hashing/truncation.  */
};					 
					 
#define PRIV(name)	((struct vms_private_data_struct *) abfd->tdata.any)->name
					 
#define SECTION_NAME_TEMPLATE "__SEC__%d"
					 
#if VMS_DEBUG				 
extern void _bfd_vms_debug (int, char *, ...) ATTRIBUTE_PRINTF_2;
extern void _bfd_hexdump   (int, unsigned char *, int, int);
					 
#define vms_debug _bfd_vms_debug	 
#endif					 
					 
extern struct bfd_hash_entry * _bfd_vms_hash_newfunc (struct bfd_hash_entry *, struct bfd_hash_table *, const char *);
extern void        _bfd_vms_get_header_values (bfd *, unsigned char *, int *, int *);
extern int         _bfd_vms_get_record  (bfd *abf);
extern int         _bfd_vms_next_record (bfd *abf);
extern char *      _bfd_vms_save_sized_string (unsigned char *, int);
extern char *      _bfd_vms_save_counted_string (unsigned char *);
extern void        _bfd_vms_push (bfd *, uquad, int);
extern uquad       _bfd_vms_pop (bfd *, int *);
extern bfd_boolean _bfd_save_vms_section (bfd *, asection *, const void *, file_ptr, bfd_size_type);
extern void        _bfd_vms_output_begin (bfd *, int, int);
extern void        _bfd_vms_output_alignment (bfd *, int);
extern void        _bfd_vms_output_push (bfd *);
extern void        _bfd_vms_output_pop (bfd *);
extern void        _bfd_vms_output_flush (bfd *);
extern void        _bfd_vms_output_end (bfd *);
extern int         _bfd_vms_output_check (bfd *, int);
extern void        _bfd_vms_output_byte (bfd *, unsigned);
extern void        _bfd_vms_output_short (bfd *, unsigned);
extern void        _bfd_vms_output_long (bfd *, unsigned long);
extern void        _bfd_vms_output_quad (bfd *, uquad);
extern void        _bfd_vms_output_counted (bfd *, char *);
extern void        _bfd_vms_output_dump (bfd *, unsigned char *, int);
extern void        _bfd_vms_output_fill (bfd *, int, int);
extern char *      _bfd_vms_length_hash_symbol (bfd *, const char *, int);
extern vms_symbol_entry * _bfd_vms_enter_symbol (bfd *, char *);

#endif /* VMS_H */
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/* tc-m68k.c -- Assemble for the m68k family
   Copyright (C) 1987-2022 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

#include "as.h"
#include "safe-ctype.h"
#include "obstack.h"
#include "subsegs.h"
#include "dwarf2dbg.h"
#include "dw2gencfi.h"

#include "opcode/m68k.h"
#include "m68k-parse.h"
#include "elf/m68k.h"

static void m68k_elf_cons (int);
static void m68k_elf_gnu_attribute (int);

/* This string holds the chars that always start a comment.  If the
   pre-processor is disabled, these aren't very useful.  The macro
   tc_comment_chars points to this.  We use this, rather than the
   usual comment_chars, so that the --bitwise-or option will work.  */
#if defined (TE_SVR4) || defined (TE_DELTA)
const char *m68k_comment_chars = "|#";
#else
const char *m68k_comment_chars = "|";
#endif

/* This array holds the chars that only start a comment at the beginning of
   a line.  If the line seems to have the form '# 123 filename'
   .line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
   first line of the input file.  This is because the compiler outputs
   #NO_APP at the beginning of its output.  */
/* Also note that comments like this one will always work.  */
const char line_comment_chars[] = "#*";

const char line_separator_chars[] = ";";

/* Chars that can be used to separate mant from exp in floating point nums.  */
const char EXP_CHARS[] = "eE";

/* Chars that mean this number is a floating point constant, as
   in "0f12.456" or "0d1.2345e12".  */

const char FLT_CHARS[] = "rRsSfFdDxXeEpP";

/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
   changed in read.c .  Ideally it shouldn't have to know about it at all,
   but nothing is ideal around here.  */

/* Are we trying to generate PIC code?  If so, absolute references
   ought to be made into linkage table references or pc-relative
   references.  Not implemented.  For ELF there are other means
   to denote pic relocations.  */
int flag_want_pic;

static int flag_short_refs;	/* -l option.  */
static int flag_long_jumps;	/* -S option.  */
static int flag_keep_pcrel;	/* --pcrel option.  */

#ifdef REGISTER_PREFIX_OPTIONAL
int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
#else
int flag_reg_prefix_optional;
#endif

/* Whether --register-prefix-optional was used on the command line.  */
static int reg_prefix_optional_seen;

/* The floating point coprocessor to use by default.  */
static enum m68k_register m68k_float_copnum = COP1;

/* If this is non-zero, then references to number(%pc) will be taken
   to refer to number, rather than to %pc + number.  */
static int m68k_abspcadd;

/* If this is non-zero, then the quick forms of the move, add, and sub
   instructions are used when possible.  */
static int m68k_quick = 1;

/* If this is non-zero, then if the size is not specified for a base
   or outer displacement, the assembler assumes that the size should
   be 32 bits.  */
static int m68k_rel32 = 1;

/* This is non-zero if m68k_rel32 was set from the command line.  */
static int m68k_rel32_from_cmdline;

/* The default width to use for an index register when using a base
   displacement.  */
static enum m68k_size m68k_index_width_default = SIZE_LONG;

/* The current label.  */

static struct m68k_tc_sy *current_label;

/* Pointer to list holding the opcodes sorted by name.  */
static struct m68k_opcode const ** m68k_sorted_opcodes;

/* It's an arbitrary name:  This means I don't approve of it.
   See flames below.  */
static struct obstack robyn;

struct m68k_incant
  {
    const char *m_operands;
    unsigned long m_opcode;
    short m_opnum;
    short m_codenum;
    int m_arch;
    struct m68k_incant *m_next;
  };

#define getone(x)	((((x)->m_opcode)>>16)&0xffff)
#define gettwo(x)	(((x)->m_opcode)&0xffff)

static const enum m68k_register m68000_ctrl[] = { 0 };
static const enum m68k_register m68010_ctrl[] = {
  SFC, DFC, USP, VBR,
  0
};
static const enum m68k_register m68020_ctrl[] = {
  SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
  0
};
static const enum m68k_register m68040_ctrl[] = {
  SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
  USP, VBR, MSP, ISP, MMUSR, URP, SRP,
  0
};
static const enum m68k_register m68060_ctrl[] = {
  SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
  USP, VBR, URP, SRP, PCR,
  0
};
static const enum m68k_register mcf_ctrl[] = {
  CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
  RAMBAR0, RAMBAR1, RAMBAR, MBAR,
  0
};
static const enum m68k_register mcf51_ctrl[] = {
  VBR, CPUCR,
  0
};
static const enum m68k_register mcf5206_ctrl[] = {
  CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
  0
};
static const enum m68k_register mcf5208_ctrl[] = {
  CACR, ACR0, ACR1, VBR,  RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5210a_ctrl[] = {
  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
  0
};
static const enum m68k_register mcf5213_ctrl[] = {
  VBR, RAMBAR, RAMBAR1, FLASHBAR,
  0
};
static const enum m68k_register mcf5216_ctrl[] = {
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5221x_ctrl[] = {
  VBR, FLASHBAR, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf52223_ctrl[] = {
  VBR, FLASHBAR, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf52235_ctrl[] = {
  VBR, FLASHBAR, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5225_ctrl[] = {
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf52259_ctrl[] = {
  VBR, FLASHBAR, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf52277_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5235_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5249_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
  0
};
static const enum m68k_register mcf5250_ctrl[] = {
  VBR,
  0
};
static const enum m68k_register mcf5253_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
  0
};
static const enum m68k_register mcf5271_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5272_ctrl[] = {
  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
  0
};
static const enum m68k_register mcf5275_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5282_ctrl[] = {
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf53017_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5307_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
  0
};
static const enum m68k_register mcf5329_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcf5373_ctrl[] = {
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
  0
};
static const enum m68k_register mcfv4e_ctrl[] = {
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
  VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
  MBAR, SECMBAR,
  MPCR /* Multiprocessor Control register */,
  EDRAMBAR /* Embedded DRAM Base Address Register */,
  /* Permutation control registers.  */
  PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
  PCR3U0, PCR3L0, PCR3U1, PCR3L1,
  /* Legacy names */
  TC /* ASID */, BUSCR /* MMUBAR */,
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
  MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
  ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
  0
};
static const enum m68k_register mcf5407_ctrl[] = {
  CACR, ASID, ACR0, ACR1, ACR2, ACR3,
  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
  /* Legacy names */
  TC /* ASID */,
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
  0
};
static const enum m68k_register mcf54418_ctrl[] = {
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
  VBR, PC, RAMBAR1,
  /* Legacy names */
  TC /* ASID */, BUSCR /* MMUBAR */,
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
  RAMBAR /* RAMBAR1 */,
  0
};
static const enum m68k_register mcf54455_ctrl[] = {
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
  VBR, PC, RAMBAR1,
  /* Legacy names */
  TC /* ASID */, BUSCR /* MMUBAR */,
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
  RAMBAR /* RAMBAR1 */,
  0
};
static const enum m68k_register mcf5475_ctrl[] = {
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
  /* Legacy names */
  TC /* ASID */, BUSCR /* MMUBAR */,
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
  0
};
static const enum m68k_register mcf5485_ctrl[] = {
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
  /* Legacy names */
  TC /* ASID */, BUSCR /* MMUBAR */,
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
  0
};
static const enum m68k_register fido_ctrl[] = {
  SFC, DFC, USP, VBR, CAC, MBO,
  0
};
#define cpu32_ctrl m68010_ctrl

static const enum m68k_register *control_regs;

/* Internal form of a 68020 instruction.  */
struct m68k_it
{
  const char *error;
  const char *args;		/* List of opcode info.  */
  int numargs;

  int numo;			/* Number of shorts in opcode.  */
  short opcode[11];

  struct m68k_op operands[6];

  int nexp;			/* Number of exprs in use.  */
  struct m68k_exp exprs[4];

  int nfrag;			/* Number of frags we have to produce.  */
  struct
    {
      int fragoff;		/* Where in the current opcode the frag ends.  */
      symbolS *fadd;
      offsetT foff;
      int fragty;
    }
  fragb[4];

  int nrel;			/* Num of reloc structs in use.  */
  struct
    {
      int n;
      expressionS exp;
      char wid;
      char pcrel;
      /* In a pc relative address the difference between the address
	 of the offset and the address that the offset is relative
	 to.  This depends on the addressing mode.  Basically this
	 is the value to put in the offset field to address the
	 first byte of the offset, without regarding the special
	 significance of some values (in the branch instruction, for
	 example).  */
      int pcrel_fix;
      /* Whether this expression needs special pic relocation, and if
	 so, which.  */
      enum pic_relocation pic_reloc;
    }
  reloc[5];			/* Five is enough???  */
};

#define cpu_of_arch(x)		((x) & (m68000up | mcfisa_a | fido_a))
#define float_of_arch(x)	((x) & mfloat)
#define mmu_of_arch(x)		((x) & mmmu)
#define arch_coldfire_p(x)	((x) & mcfisa_a)
#define arch_coldfire_fpu(x)	((x) & cfloat)

/* Macros for determining if cpu supports a specific addressing mode.  */
#define HAVE_LONG_DISP(x)	\
	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
#define HAVE_LONG_CALL(x)	\
	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
#define HAVE_LONG_COND(x)	\
	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
#define HAVE_LONG_BRANCH(x)	\
	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))

static struct m68k_it the_ins;	/* The instruction being assembled.  */

#define op(ex)		((ex)->exp.X_op)
#define adds(ex)	((ex)->exp.X_add_symbol)
#define subs(ex)	((ex)->exp.X_op_symbol)
#define offs(ex)	((ex)->exp.X_add_number)

/* Macros for adding things to the m68k_it struct.  */
#define addword(w)	(the_ins.opcode[the_ins.numo++] = (w))

/* Like addword, but goes BEFORE general operands.  */

static void
insop (int w, const struct m68k_incant *opcode)
{
  int z;
  for (z = the_ins.numo; z > opcode->m_codenum; --z)
    the_ins.opcode[z] = the_ins.opcode[z - 1];
  for (z = 0; z < the_ins.nrel; z++)
    the_ins.reloc[z].n += 2;
  for (z = 0; z < the_ins.nfrag; z++)
    the_ins.fragb[z].fragoff++;
  the_ins.opcode[opcode->m_codenum] = w;
  the_ins.numo++;
}

/* The numo+1 kludge is so we can hit the low order byte of the prev word.
   Blecch.  */
static void
add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
{
  the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
				   ? the_ins.numo * 2 - 1
				   : (width == 'b'
				      ? the_ins.numo * 2 + 1
				      : the_ins.numo * 2));
  the_ins.reloc[the_ins.nrel].exp = exp->exp;
  the_ins.reloc[the_ins.nrel].wid = width;
  the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
  the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
  the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
}

/* Cause an extra frag to be generated here, inserting up to 10 bytes
   (that value is chosen in the frag_var call in md_assemble).  TYPE
   is the subtype of the frag to be generated; its primary type is
   rs_machine_dependent.

   The TYPE parameter is also used by md_convert_frag_1 and
   md_estimate_size_before_relax.  The appropriate type of fixup will
   be emitted by md_convert_frag_1.

   ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
static void
add_frag (symbolS *add, offsetT off, int type)
{
  the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
  the_ins.fragb[the_ins.nfrag].fadd = add;
  the_ins.fragb[the_ins.nfrag].foff = off;
  the_ins.fragb[the_ins.nfrag++].fragty = type;
}

#define isvar(ex) \
  (op (ex) != O_constant && op (ex) != O_big)

static char *crack_operand (char *str, struct m68k_op *opP);
static int get_num (struct m68k_exp *exp, int ok);
static int reverse_16_bits (int in);
static int reverse_8_bits (int in);
static void install_gen_operand (int mode, int val);
static void install_operand (int mode, int val);
static void s_bss (int);
static void s_data1 (int);
static void s_data2 (int);
static void s_even (int);
static void s_proc (int);
static void s_chip (int);
static void s_fopt (int);
static void s_opt (int);
static void s_reg (int);
static void s_restore (int);
static void s_save (int);
static void s_mri_if (int);
static void s_mri_else (int);
static void s_mri_endi (int);
static void s_mri_break (int);
static void s_mri_next (int);
static void s_mri_for (int);
static void s_mri_endf (int);
static void s_mri_repeat (int);
static void s_mri_until (int);
static void s_mri_while (int);
static void s_mri_endw (int);
static void s_m68k_cpu (int);
static void s_m68k_arch (int);

struct m68k_cpu
{
  unsigned long arch;	/* Architecture features.  */
  const enum m68k_register *control_regs;	/* Control regs on chip */
  const char *name;	/* Name */
  int alias;       	/* Alias for a canonical name.  If 1, then
			   succeeds canonical name, if -1 then
			   succeeds canonical name, if <-1 ||>1 this is a
			   deprecated name, and the next/previous name
			   should be used. */
};

/* We hold flags for features explicitly enabled and explicitly
   disabled.  */
static int current_architecture;
static int not_current_architecture;
static const struct m68k_cpu *selected_arch;
static const struct m68k_cpu *selected_cpu;
static int initialized;

/* Architecture models.  */
static const struct m68k_cpu m68k_archs[] =
{
  {m68000,					m68000_ctrl, "68000", 0},
  {m68010,					m68010_ctrl, "68010", 0},
  {m68020|m68881|m68851,			m68020_ctrl, "68020", 0},
  {m68030|m68881|m68851,			m68020_ctrl, "68030", 0},
  {m68040,					m68040_ctrl, "68040", 0},
  {m68060,					m68060_ctrl, "68060", 0},
  {cpu32|m68881,				cpu32_ctrl, "cpu32", 0},
  {fido_a,					fido_ctrl, "fidoa", 0},
  {mcfisa_a|mcfhwdiv,				NULL, "isaa", 0},
  {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp,		NULL, "isaaplus", 0},
  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp,		NULL, "isab", 0},
  {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp,		NULL, "isac", 0},
  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp,	mcf_ctrl, "cfv4", 0},
  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
  {0,0,NULL, 0}
};

/* For -mno-mac we want to turn off all types of mac.  */
static const unsigned no_mac = mcfmac | mcfemac;

/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
   for either.  */
static const struct m68k_cpu m68k_extensions[] =
{
  {m68851,					NULL, "68851", -1},
  {m68881,					NULL, "68881", -1},
  {m68881,					NULL, "68882", -1},

  {cfloat|m68881,				NULL, "float", 0},

  {mcfhwdiv,					NULL, "div", 1},
  {mcfusp,					NULL, "usp", 1},
  {mcfmac,					(void *)&no_mac, "mac", 1},
  {mcfemac,					NULL, "emac", 1},

  {0,NULL,NULL, 0}
};

/* Processor list */
static const struct m68k_cpu m68k_cpus[] =
{
  {m68000,					m68000_ctrl, "68000", 0},
  {m68000,					m68000_ctrl, "68ec000", 1},
  {m68000,					m68000_ctrl, "68hc000", 1},
  {m68000,					m68000_ctrl, "68hc001", 1},
  {m68000,					m68000_ctrl, "68008", 1},
  {m68000,					m68000_ctrl, "68302", 1},
  {m68000,					m68000_ctrl, "68306", 1},
  {m68000,					m68000_ctrl, "68307", 1},
  {m68000,					m68000_ctrl, "68322", 1},
  {m68000,					m68000_ctrl, "68356", 1},
  {m68010,					m68010_ctrl, "68010", 0},
  {m68020|m68881|m68851,			m68020_ctrl, "68020", 0},
  {m68020|m68881|m68851,			m68020_ctrl, "68k", 1},
  {m68020|m68881|m68851,			m68020_ctrl, "68ec020", 1},
  {m68030|m68881|m68851,			m68020_ctrl, "68030", 0},
  {m68030|m68881|m68851,			m68020_ctrl, "68ec030", 1},
  {m68040,					m68040_ctrl, "68040", 0},
  {m68040,					m68040_ctrl, "68ec040", 1},
  {m68060,					m68060_ctrl, "68060", 0},
  {m68060,					m68060_ctrl, "68ec060", 1},

  {cpu32|m68881,				cpu32_ctrl, "cpu32",  0},
  {cpu32|m68881,				cpu32_ctrl, "68330", 1},
  {cpu32|m68881,				cpu32_ctrl, "68331", 1},
  {cpu32|m68881,				cpu32_ctrl, "68332", 1},
  {cpu32|m68881,				cpu32_ctrl, "68333", 1},
  {cpu32|m68881,				cpu32_ctrl, "68334", 1},
  {cpu32|m68881,				cpu32_ctrl, "68336", 1},
  {cpu32|m68881,				cpu32_ctrl, "68340", 1},
  {cpu32|m68881,				cpu32_ctrl, "68341", 1},
  {cpu32|m68881,				cpu32_ctrl, "68349", 1},
  {cpu32|m68881,				cpu32_ctrl, "68360", 1},

  {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51", 0},
  {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51ac", 1},
  {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51ag", 1},
  {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51cn", 1},
  {mcfisa_a|mcfisa_c|mcfusp|mcfmac,  		mcf51_ctrl, "51em", 1},
  {mcfisa_a|mcfisa_c|mcfusp|mcfmac,  		mcf51_ctrl, "51je", 1},
  {mcfisa_a|mcfisa_c|mcfusp|mcfemac,            mcf51_ctrl, "51jf", 1},
  {mcfisa_a|mcfisa_c|mcfusp|mcfemac,            mcf51_ctrl, "51jg", 1},
  {mcfisa_a|mcfisa_c|mcfusp,  			mcf51_ctrl, "51jm", 1},
  {mcfisa_a|mcfisa_c|mcfusp|mcfmac,  		mcf51_ctrl, "51mm", 1},
  {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51qe", 1},
  {mcfisa_a|mcfisa_c|mcfusp|mcfemac,            mcf51_ctrl, "51qm", 1},

  {mcfisa_a,					mcf_ctrl, "5200", 0},
  {mcfisa_a,					mcf_ctrl, "5202", 1},
  {mcfisa_a,					mcf_ctrl, "5204", 1},
  {mcfisa_a,					mcf5206_ctrl, "5206", 1},

  {mcfisa_a|mcfhwdiv|mcfmac,			mcf5206_ctrl, "5206e", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5207", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5208", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5210a_ctrl, "5210a", 0},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5210a_ctrl, "5211a", 1},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5211", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5212", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5213", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5214", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5216", 0},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "521x", 2},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5221x_ctrl, "5221x", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52221", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52223", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52230", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52233", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52234", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52235", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5224", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5225", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52277_ctrl, "52274", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52277_ctrl, "52277", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5232", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5233", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5234", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5235", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "523x", 0},

  {mcfisa_a|mcfhwdiv|mcfemac,			mcf5249_ctrl, "5249", 0},
  {mcfisa_a|mcfhwdiv|mcfemac,			mcf5250_ctrl, "5250", 0},
  {mcfisa_a|mcfhwdiv|mcfemac, 			mcf5253_ctrl, "5253", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52252", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52254", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52255", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52256", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52258", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52259", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5270", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5271", 0},

  {mcfisa_a|mcfhwdiv|mcfmac,			mcf5272_ctrl, "5272", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5275_ctrl, "5274", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5275_ctrl, "5275", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5280", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5281", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5282", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "528x", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53011", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53012", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53013", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53014", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53015", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53016", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53017", 0},

  {mcfisa_a|mcfhwdiv|mcfmac,			mcf5307_ctrl, "5307", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5327", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5328", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5329", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "532x", 0},

  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "5372", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "5373", -1},
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "537x", 0},

  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac,		mcf5407_ctrl, "5407",0},

  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54410", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54415", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54416", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54417", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54418", 0},

  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54450", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54451", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54452", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54453", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54454", -1},
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54455", 0},

  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},

  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},

  {fido_a,				fido_ctrl, "fidoa", 0},
  {fido_a,				fido_ctrl, "fido", 1},

  {0,NULL,NULL, 0}
  };

static const struct m68k_cpu *m68k_lookup_cpu
(const char *, const struct m68k_cpu *, int, int *);
static int m68k_set_arch (const char *, int, int);
static int m68k_set_cpu (const char *, int, int);
static int m68k_set_extension (const char *, int, int);
static void m68k_init_arch (void);

/* This is the assembler relaxation table for m68k. m68k is a rich CISC
   architecture and we have a lot of relaxation modes.  */

/* Macros used in the relaxation code.  */
#define TAB(x,y)	(((x) << 2) + (y))
#define TABTYPE(x)      ((x) >> 2)

/* Relaxation states.  */
#define BYTE		0
#define SHORT		1
#define LONG		2
#define SZ_UNDEF	3

/* Here are all the relaxation modes we support.  First we can relax ordinary
   branches.  On 68020 and higher and on CPU32 all branch instructions take
   three forms, so on these CPUs all branches always remain as such.  When we
   have to expand to the LONG form on a 68000, though, we substitute an
   absolute jump instead.  This is a direct replacement for unconditional
   branches and a branch over a jump for conditional branches.  However, if the
   user requires PIC and disables this with --pcrel, we can only relax between
   BYTE and SHORT forms, punting if that isn't enough.  This gives us four
   different relaxation modes for branches:  */

#define BRANCHBWL	0	/* Branch byte, word, or long.  */
#define BRABSJUNC	1	/* Absolute jump for LONG, unconditional.  */
#define BRABSJCOND	2	/* Absolute jump for LONG, conditional.  */
#define BRANCHBW	3	/* Branch byte or word.  */

/* We also relax coprocessor branches and DBcc's.  All CPUs that support
   coprocessor branches support them in word and long forms, so we have only
   one relaxation mode for them.  DBcc's are word only on all CPUs.  We can
   relax them to the LONG form with a branch-around sequence.  This sequence
   can use a long branch (if available) or an absolute jump (if acceptable).
   This gives us two relaxation modes.  If long branches are not available and
   absolute jumps are not acceptable, we don't relax DBcc's.  */

#define FBRANCH		4	/* Coprocessor branch.  */
#define DBCCLBR		5	/* DBcc relaxable with a long branch.  */
#define DBCCABSJ	6	/* DBcc relaxable with an absolute jump.  */

/* That's all for instruction relaxation.  However, we also relax PC-relative
   operands.  Specifically, we have three operand relaxation modes.  On the
   68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
   on CPU32 they may be 16-bit or 32-bit.  For the latter we relax between the
   two.  Also PC+displacement+index operands in their simple form (with a non-
   suppressed index without memory indirection) are supported on all CPUs, but
   on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
   and on CPU32 we relax it to SHORT and LONG forms as well using the extended
   form of the PC+displacement+index operand.  Finally, some absolute operands
   can be relaxed down to 16-bit PC-relative.  */

#define PCREL1632	7	/* 16-bit or 32-bit PC-relative.  */
#define PCINDEX		8	/* PC + displacement + index. */
#define ABSTOPCREL	9	/* Absolute relax down to 16-bit PC-relative.  */

/* This relaxation is required for branches where there is no long
   branch and we are in pcrel mode.  We generate a bne/beq pair.  */
#define BRANCHBWPL	10      /* Branch byte, word or pair of longs
				   */

/* Note that calls to frag_var need to specify the maximum expansion
   needed; this is currently 12 bytes for bne/beq pair.  */
#define FRAG_VAR_SIZE 12

/* The fields are:
   How far Forward this mode will reach:
   How far Backward this mode will reach:
   How many bytes this mode will add to the size of the frag
   Which mode to go to if the offset won't fit in this one

   Please check tc-m68k.h:md_prepare_relax_scan if changing this table.  */
relax_typeS md_relax_table[] =
{
  {   127,   -128,  0, TAB (BRANCHBWL, SHORT) },
  { 32767, -32768,  2, TAB (BRANCHBWL, LONG) },
  {     0,	0,  4, 0 },
  {     1,	1,  0, 0 },

  {   127,   -128,  0, TAB (BRABSJUNC, SHORT) },
  { 32767, -32768,  2, TAB (BRABSJUNC, LONG) },
  {	0,	0,  4, 0 },
  {	1,	1,  0, 0 },

  {   127,   -128,  0, TAB (BRABSJCOND, SHORT) },
  { 32767, -32768,  2, TAB (BRABSJCOND, LONG) },
  {	0,	0,  6, 0 },
  {	1,	1,  0, 0 },

  {   127,   -128,  0, TAB (BRANCHBW, SHORT) },
  {	0,	0,  2, 0 },
  {	1,	1,  0, 0 },
  {	1,	1,  0, 0 },

  {	1, 	1,  0, 0 },		/* FBRANCH doesn't come BYTE.  */
  { 32767, -32768,  2, TAB (FBRANCH, LONG) },
  {	0,	0,  4, 0 },
  {	1, 	1,  0, 0 },

  {	1,	1,  0, 0 },		/* DBCC doesn't come BYTE.  */
  { 32767, -32768,  2, TAB (DBCCLBR, LONG) },
  {	0,	0, 10, 0 },
  {	1,	1,  0, 0 },

  {	1,	1,  0, 0 },		/* DBCC doesn't come BYTE.  */
  { 32767, -32768,  2, TAB (DBCCABSJ, LONG) },
  {	0,	0, 10, 0 },
  {	1,	1,  0, 0 },

  {	1, 	1,  0, 0 },		/* PCREL1632 doesn't come BYTE.  */
  { 32767, -32768,  2, TAB (PCREL1632, LONG) },
  {	0,	0,  6, 0 },
  {	1,	1,  0, 0 },

  {   125,   -130,  0, TAB (PCINDEX, SHORT) },
  { 32765, -32770,  2, TAB (PCINDEX, LONG) },
  {	0,	0,  4, 0 },
  {	1,	1,  0, 0 },

  {	1,	1,  0, 0 },		/* ABSTOPCREL doesn't come BYTE.  */
  { 32767, -32768,  2, TAB (ABSTOPCREL, LONG) },
  {	0,	0,  4, 0 },
  {	1,	1,  0, 0 },

  {   127,   -128,  0, TAB (BRANCHBWPL, SHORT) },
  { 32767, -32768,  2, TAB (BRANCHBWPL, LONG) },
  {     0,	0,  10, 0 },
  {     1,	1,  0, 0 },
};

/* These are the machine dependent pseudo-ops.  These are included so
   the assembler can work on the output from the SUN C compiler, which
   generates these.  */

/* This table describes all the machine specific pseudo-ops the assembler
   has to support.  The fields are:
   pseudo-op name without dot
   function to call to execute this pseudo-op
   Integer arg to pass to the function.  */
const pseudo_typeS md_pseudo_table[] =
{
  {"data1", s_data1, 0},
  {"data2", s_data2, 0},
  {"bss", s_bss, 0},
  {"even", s_even, 0},
  {"skip", s_space, 0},
  {"proc", s_proc, 0},
  {"align", s_align_bytes, 0},
  {"swbeg", s_ignore, 0},
  {"long", m68k_elf_cons, 4},
  {"extend", float_cons, 'x'},
  {"ldouble", float_cons, 'x'},

  {"arch", s_m68k_arch, 0},
  {"cpu", s_m68k_cpu, 0},
  {"gnu_attribute", m68k_elf_gnu_attribute, 0},

  /* The following pseudo-ops are supported for MRI compatibility.  */
  {"chip", s_chip, 0},
  {"comline", s_space, 1},
  {"fopt", s_fopt, 0},
  {"mask2", s_ignore, 0},
  {"opt", s_opt, 0},
  {"reg", s_reg, 0},
  {"restore", s_restore, 0},
  {"save", s_save, 0},

  {"if", s_mri_if, 0},
  {"if.b", s_mri_if, 'b'},
  {"if.w", s_mri_if, 'w'},
  {"if.l", s_mri_if, 'l'},
  {"else", s_mri_else, 0},
  {"else.s", s_mri_else, 's'},
  {"else.l", s_mri_else, 'l'},
  {"endi", s_mri_endi, 0},
  {"break", s_mri_break, 0},
  {"break.s", s_mri_break, 's'},
  {"break.l", s_mri_break, 'l'},
  {"next", s_mri_next, 0},
  {"next.s", s_mri_next, 's'},
  {"next.l", s_mri_next, 'l'},
  {"for", s_mri_for, 0},
  {"for.b", s_mri_for, 'b'},
  {"for.w", s_mri_for, 'w'},
  {"for.l", s_mri_for, 'l'},
  {"endf", s_mri_endf, 0},
  {"repeat", s_mri_repeat, 0},
  {"until", s_mri_until, 0},
  {"until.b", s_mri_until, 'b'},
  {"until.w", s_mri_until, 'w'},
  {"until.l", s_mri_until, 'l'},
  {"while", s_mri_while, 0},
  {"while.b", s_mri_while, 'b'},
  {"while.w", s_mri_while, 'w'},
  {"while.l", s_mri_while, 'l'},
  {"endw", s_mri_endw, 0},

  {0, 0, 0}
};

/* The mote pseudo ops are put into the opcode table, since they
   don't start with a . they look like opcodes to gas.  */

const pseudo_typeS mote_pseudo_table[] =
{

  {"dcl", cons, 4},
  {"dc", cons, 2},
  {"dcw", cons, 2},
  {"dcb", cons, 1},

  {"dsl", s_space, 4},
  {"ds", s_space, 2},
  {"dsw", s_space, 2},
  {"dsb", s_space, 1},

  {"xdef", s_globl, 0},
  {"align", s_align_bytes, 0},
  {0, 0, 0}
};

/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
   gives identical results to a 32-bit host.  */
#define TRUNC(X)	((valueT) (X) & 0xffffffff)
#define SEXT(X)		((TRUNC (X) ^ 0x80000000) - 0x80000000)

#define issbyte(x)	((valueT) SEXT (x) + 0x80 < 0x100)
#define isubyte(x)	((valueT) TRUNC (x) < 0x100)
#define issword(x)	((valueT) SEXT (x) + 0x8000 < 0x10000)
#define isuword(x)	((valueT) TRUNC (x) < 0x10000)

#define isbyte(x)	((valueT) SEXT (x) + 0xff < 0x1ff)
#define isword(x)	((valueT) SEXT (x) + 0xffff < 0x1ffff)
#define islong(x)	(1)

static char notend_table[256];
static char alt_notend_table[256];
#define notend(s)						\
  (! (notend_table[(unsigned char) *s]				\
      || (*s == ':'						\
	  && alt_notend_table[(unsigned char) s[1]])))


/* Return zero if the reference to SYMBOL from within the same segment may
   be relaxed.  */

/* On an ELF system, we can't relax an externally visible symbol,
   because it may be overridden by a shared library.  However, if
   TARGET_OS is "elf", then we presume that we are assembling for an
   embedded system, in which case we don't have to worry about shared
   libraries, and we can relax any external sym.  */

#define relaxable_symbol(symbol) \
  (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
     || S_IS_WEAK (symbol)))

/* Compute the relocation code for a fixup of SIZE bytes, using pc
   relative relocation if PCREL is non-zero.  PIC says whether a special
   pic relocation was requested.  */

static bfd_reloc_code_real_type
get_reloc_code (int size, int pcrel, enum pic_relocation pic)
{
  switch (pic)
    {
    case pic_got_pcrel:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_8_GOT_PCREL;
	case 2:
	  return BFD_RELOC_16_GOT_PCREL;
	case 4:
	  return BFD_RELOC_32_GOT_PCREL;
	}
      break;

    case pic_got_off:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_8_GOTOFF;
	case 2:
	  return BFD_RELOC_16_GOTOFF;
	case 4:
	  return BFD_RELOC_32_GOTOFF;
	}
      break;

    case pic_plt_pcrel:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_8_PLT_PCREL;
	case 2:
	  return BFD_RELOC_16_PLT_PCREL;
	case 4:
	  return BFD_RELOC_32_PLT_PCREL;
	}
      break;

    case pic_plt_off:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_8_PLTOFF;
	case 2:
	  return BFD_RELOC_16_PLTOFF;
	case 4:
	  return BFD_RELOC_32_PLTOFF;
	}
      break;

    case pic_tls_gd:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_68K_TLS_GD8;
	case 2:
	  return BFD_RELOC_68K_TLS_GD16;
	case 4:
	  return BFD_RELOC_68K_TLS_GD32;
	}
      break;

    case pic_tls_ldm:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_68K_TLS_LDM8;
	case 2:
	  return BFD_RELOC_68K_TLS_LDM16;
	case 4:
	  return BFD_RELOC_68K_TLS_LDM32;
	}
      break;

    case pic_tls_ldo:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_68K_TLS_LDO8;
	case 2:
	  return BFD_RELOC_68K_TLS_LDO16;
	case 4:
	  return BFD_RELOC_68K_TLS_LDO32;
	}
      break;

    case pic_tls_ie:
      switch (size)
	{
	case 1:
	  return BFD_RELOC_68K_TLS_IE8;
	case 2:
	  return BFD_RELOC_68K_TLS_IE16;
	case 4:
	  return BFD_RELOC_68K_TLS_IE32;
	}