# Instruction cache rules
#
#   This file is part of the program psim.
#
#   Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
#
#   This program is free software; you can redistribute it and/or modify
#   it under the terms of the GNU General Public License as published by
#   the Free Software Foundation; either version 2 of the License, or
#   (at your option) any later version.
#
#   This program is distributed in the hope that it will be useful,
#   but WITHOUT ANY WARRANTY; without even the implied warranty of
#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#   GNU General Public License for more details.
#
#   You should have received a copy of the GNU General Public License
#   along with this program; if not, write to the Free Software
#   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
#
compute:RA:RA::
compute:RA:Ra:signed32 *:(&GPR[RA])
compute:RA:RaH:signed16 *:AH2_4(Ra)
compute:RA:RaL:signed16 *:AL2_4(Ra)
compute:RA:val_Ra:signed32:(RA == 0 ? 0 : GPR[RA])
#
compute:RB:RB::
compute:RB:Rb:signed32:(RB == 0 ? 0 : GPR[RB])
compute:RB:RbU:unsigned32:(RB == 0 ? 0 : GPR[RB])
compute:RB:RbH:signed16:VH2_4(Rb)
compute:RB:RbL:signed16:VL2_4(Rb)
compute:RB:RbHU:unsigned16:VH2_4(Rb)
compute:RB:RbLU:unsigned16:VL2_4(Rb)
#
compute:RC:RC::
compute:RC:Rc:signed32:(RC == 0 ? 0 : GPR[RC])
compute:RC:RcU:unsigned32:(RC == 0 ? 0 : GPR[RC])
compute:RC:RcH:signed16:VH2_4(Rc)
compute:RC:RcL:signed16:VL2_4(Rc)
#
#
compute:IMM_6S:IMM_6S::
compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6)
# NB - for short imm[HL] are the same value
compute:IMM_6S:immHL:signed32:((imm << 16) | MASKED32(imm, 16, 31))
compute:IMM_6S:immH:signed32:imm
compute:IMM_6S:immL:signed32:imm
compute:IMM_6S:imm_6:signed32:IMM_6S
compute:IMM_6S:imm_5:signed32:LSMASKED32(IMM_6S, 4, 0)
compute:IMM_6S:imm_6u:unsigned32:(IMM_6S & 0x3f)
#
compute:RC:pcdisp:signed32:(Rc & ~0x7)
compute:RC:pcaddr:signed32:pcdisp
#
compute:IMM_18S:IMM_18S::
compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3)
compute:IMM_18S:pcaddr:signed32:pcdisp
compute:IMM_12S:IMM_12S::
compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3)
compute:IMM_12S:pcaddr:signed32:pcdisp
#
compute:IMM_8L:IMM_8L::
compute:IMM_18L:IMM_18L::
compute:IMM_6L:IMM_6L::
compute:IMM_6L:imm:signed32:((((IMM_6L << 8) | IMM_8L) << 18) | IMM_18L)
compute:IMM_6L:immHL:signed32:imm
compute:IMM_6L:immH:signed32:EXTRACTED32(imm, 0, 15)
compute:IMM_6L:immL:signed32:EXTRACTED32(imm, 16, 31)
compute:IMM_6L:pcdisp:signed32:(imm & ~0x7)
compute:IMM_6L:pcaddr:signed32:pcdisp
#
#
compute:SRC_6:SRC_6::
compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6])
#
#
compute:AA:AA::
compute:AA:Aa:unsigned64*:((CPU)->regs.accumulator + AA)
compute:AB:AB::
compute:AB:Ab:unsigned64*:((CPU)->regs.accumulator + AB)