/* Generic opcode table support for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator This file is used to generate m32r-opc.c. Copyright (C) 1998 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include #include "ansidecl.h" #include "libiberty.h" #include "bfd.h" #include "symcat.h" #include "m32r-opc.h" /* Look up instruction INSN_VALUE and extract its fields. If non-null INSN is the insn table entry. Otherwise INSN_VALUE is examined to compute it. LENGTH is the bit length of INSN_VALUE if known, otherwise 0. ALIAS_P is non-zero if alias insns are to be included in the search. The result a pointer to the insn table entry, or NULL if the instruction wasn't recognized. */ const CGEN_INSN * m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p) const CGEN_INSN *insn; cgen_insn_t insn_value; int length; CGEN_FIELDS *fields; { char buf[16]; if (!insn) { const CGEN_INSN_LIST *insn_list; #ifdef CGEN_INT_INSN switch (length) { case 8: buf[0] = insn_value; break; case 16: if (cgen_current_endian == CGEN_ENDIAN_BIG) bfd_putb16 (insn_value, buf); else bfd_putl16 (insn_value, buf); break; case 32: if (cgen_current_endian == CGEN_ENDIAN_BIG) bfd_putb32 (insn_value, buf); else bfd_putl32 (insn_value, buf); break; default: abort (); } #else abort (); /* FIXME: unfinished */ #endif /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value); while (insn_list != NULL) { insn = insn_list->insn; if (alias_p || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) { /* Basic bit mask must be correct. */ /* ??? May wish to allow target to defer this check until the extract handler. */ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn)) { length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields); if (length > 0) return insn; } } insn_list = CGEN_DIS_NEXT_INSN (insn_list); } } else { /* Sanity check: can't pass an alias insn if ! alias_p. */ if (! alias_p && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) abort (); length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields); if (length > 0) return insn; } return NULL; } /* Fill in the operand instances used by insn INSN_VALUE. If non-null INS is the insn table entry. Otherwise INSN_VALUE is examined to compute it. LENGTH is the number of bits in INSN_VALUE if known, otherwise 0. INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled in. The result a pointer to the insn table entry, or NULL if the instruction wasn't recognized. */ const CGEN_INSN * m32r_cgen_get_insn_operands (insn, insn_value, length, indices) const CGEN_INSN *insn; cgen_insn_t insn_value; int length; int *indices; { CGEN_FIELDS fields; const CGEN_OPERAND_INSTANCE *opinst; int i; /* FIXME: ALIAS insns are in transition from being record in the insn table to being recorded separately as macros. They don't have semantic code so they can't be used here. Thus we currently always ignore the INSN argument. */ insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0); if (! insn) return NULL; for (i = 0, opinst = CGEN_INSN_OPERANDS (insn); opinst != NULL && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END; ++i, ++opinst) { const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst); if (op == NULL) indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); else indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields); } return insn; } /* Attributes. */ static const CGEN_ATTR_ENTRY MACH_attr[] = { { "m32r", MACH_M32R }, /* start-sanitize-m32rx */ { "m32rx", MACH_M32RX }, /* end-sanitize-m32rx */ { "max", MACH_MAX }, { 0, 0 } }; /* start-sanitize-m32rx */ static const CGEN_ATTR_ENTRY PIPE_attr[] = { { "NONE", PIPE_NONE }, { "O", PIPE_O }, { "S", PIPE_S }, { "OS", PIPE_OS }, { 0, 0 } }; /* end-sanitize-m32rx */ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = { { "ABS-ADDR", NULL }, { "FAKE", NULL }, { "HASH-PREFIX", NULL }, { "NEGATIVE", NULL }, { "PC", NULL }, { "PCREL-ADDR", NULL }, { "RELAX", NULL }, { "RELOC", NULL }, { "SIGN-OPT", NULL }, { "UNSIGNED", NULL }, { 0, 0 } }; const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = { { "MACH", & MACH_attr[0] }, /* start-sanitize-m32rx */ { "PIPE", & PIPE_attr[0] }, /* end-sanitize-m32rx */ { "ALIAS", NULL }, { "COND-CTI", NULL }, { "FILL-SLOT", NULL }, { "PARALLEL", NULL }, { "RELAX", NULL }, { "RELAXABLE", NULL }, { "UNCOND-CTI", NULL }, { 0, 0 } }; CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = { { "fp", 13 }, { "lr", 14 }, { "sp", 15 }, { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 }, { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 } }; CGEN_KEYWORD m32r_cgen_opval_h_gr = { & m32r_cgen_opval_h_gr_entries[0], 19 }; CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = { { "psw", 0 }, { "cbr", 1 }, { "spi", 2 }, { "spu", 3 }, { "bpc", 6 }, { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 }, { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 } }; CGEN_KEYWORD m32r_cgen_opval_h_cr = { & m32r_cgen_opval_h_cr_entries[0], 12 }; /* start-sanitize-m32rx */ CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = { { "a0", 0 }, { "a1", 1 } }; CGEN_KEYWORD m32r_cgen_opval_h_accums = { & m32r_cgen_opval_h_accums_entries[0], 2 }; /* end-sanitize-m32rx */ /* The hardware table. */ #define HW_ENT(n) m32r_cgen_hw_entries[n] static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] = { { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr }, { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr }, { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 }, /* start-sanitize-m32rx */ { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums }, /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 }, /* end-sanitize-m32rx */ { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 }, { 0 } }; /* The operand table. */ #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)] const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] = { /* pc: program counter */ { "pc", & HW_ENT (HW_H_PC), 0, 0, { 0, 0|(1<f_r2 = * valuep; break; case M32R_OPERAND_DR : fields->f_r1 = * valuep; break; case M32R_OPERAND_SRC1 : fields->f_r1 = * valuep; break; case M32R_OPERAND_SRC2 : fields->f_r2 = * valuep; break; case M32R_OPERAND_SCR : fields->f_r2 = * valuep; break; case M32R_OPERAND_DCR : fields->f_r1 = * valuep; break; case M32R_OPERAND_SIMM8 : fields->f_simm8 = * valuep; break; case M32R_OPERAND_SIMM16 : fields->f_simm16 = * valuep; break; case M32R_OPERAND_UIMM4 : fields->f_uimm4 = * valuep; break; case M32R_OPERAND_UIMM5 : fields->f_uimm5 = * valuep; break; case M32R_OPERAND_UIMM16 : fields->f_uimm16 = * valuep; break; /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : fields->f_imm1 = * valuep; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCD : fields->f_accd = * valuep; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCS : fields->f_accs = * valuep; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACC : fields->f_acc = * valuep; break; /* end-sanitize-m32rx */ case M32R_OPERAND_HASH : fields->f_nil = * valuep; break; case M32R_OPERAND_HI16 : fields->f_hi16 = * valuep; break; case M32R_OPERAND_SLO16 : fields->f_simm16 = * valuep; break; case M32R_OPERAND_ULO16 : fields->f_uimm16 = * valuep; break; case M32R_OPERAND_UIMM24 : fields->f_uimm24 = * valuep; break; case M32R_OPERAND_DISP8 : fields->f_disp8 = * valuep; break; case M32R_OPERAND_DISP16 : fields->f_disp16 = * valuep; break; case M32R_OPERAND_DISP24 : fields->f_disp24 = * valuep; break; default : fprintf (stderr, "Unrecognized field %d while setting operand.\n", opindex); abort (); } } /* Main entry point for getting values from cgen_fields. */ long m32r_cgen_get_operand (opindex, fields) int opindex; const CGEN_FIELDS * fields; { long value; switch (opindex) { case M32R_OPERAND_SR : value = fields->f_r2; break; case M32R_OPERAND_DR : value = fields->f_r1; break; case M32R_OPERAND_SRC1 : value = fields->f_r1; break; case M32R_OPERAND_SRC2 : value = fields->f_r2; break; case M32R_OPERAND_SCR : value = fields->f_r2; break; case M32R_OPERAND_DCR : value = fields->f_r1; break; case M32R_OPERAND_SIMM8 : value = fields->f_simm8; break; case M32R_OPERAND_SIMM16 : value = fields->f_simm16; break; case M32R_OPERAND_UIMM4 : value = fields->f_uimm4; break; case M32R_OPERAND_UIMM5 : value = fields->f_uimm5; break; case M32R_OPERAND_UIMM16 : value = fields->f_uimm16; break; /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : value = fields->f_imm1; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCD : value = fields->f_accd; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCS : value = fields->f_accs; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACC : value = fields->f_acc; break; /* end-sanitize-m32rx */ case M32R_OPERAND_HASH : value = fields->f_nil; break; case M32R_OPERAND_HI16 : value = fields->f_hi16; break; case M32R_OPERAND_SLO16 : value = fields->f_simm16; break; case M32R_OPERAND_ULO16 : value = fields->f_uimm16; break; case M32R_OPERAND_UIMM24 : value = fields->f_uimm24; break; case M32R_OPERAND_DISP8 : value = fields->f_disp8; break; case M32R_OPERAND_DISP16 : value = fields->f_disp16; break; case M32R_OPERAND_DISP24 : value = fields->f_disp24; break; default : fprintf (stderr, "Unrecognized field %d while getting operand.\n", opindex); abort (); } return value; }