/* Common target dependent code for GDB on ARM systems. Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. This file is part of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #include /* XXX for isupper () */ #include "defs.h" #include "frame.h" #include "inferior.h" #include "gdbcmd.h" #include "gdbcore.h" #include "gdb_string.h" #include "dis-asm.h" /* For register styles. */ #include "regcache.h" #include "doublest.h" #include "value.h" #include "arch-utils.h" #include "osabi.h" #include "frame-unwind.h" #include "frame-base.h" #include "trad-frame.h" #include "objfiles.h" #include "dwarf2-frame.h" #include "gdbtypes.h" #include "prologue-value.h" #include "target-descriptions.h" #include "user-regs.h" #include "arm-tdep.h" #include "gdb/sim-arm.h" #include "elf-bfd.h" #include "coff/internal.h" #include "elf/arm.h" #include "gdb_assert.h" #include "vec.h" #include "features/arm-with-m.c" static int arm_debug; /* Macros for setting and testing a bit in a minimal symbol that marks it as Thumb function. The MSB of the minimal symbol's "info" field is used for this purpose. MSYMBOL_SET_SPECIAL Actually sets the "special" bit. MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ #define MSYMBOL_SET_SPECIAL(msym) \ MSYMBOL_TARGET_FLAG_1 (msym) = 1 #define MSYMBOL_IS_SPECIAL(msym) \ MSYMBOL_TARGET_FLAG_1 (msym) /* Per-objfile data used for mapping symbols. */ static const struct objfile_data *arm_objfile_data_key; struct arm_mapping_symbol { bfd_vma value; char type; }; typedef struct arm_mapping_symbol arm_mapping_symbol_s; DEF_VEC_O(arm_mapping_symbol_s); struct arm_per_objfile { VEC(arm_mapping_symbol_s) **section_maps; }; /* The list of available "set arm ..." and "show arm ..." commands. */ static struct cmd_list_element *setarmcmdlist = NULL; static struct cmd_list_element *showarmcmdlist = NULL; /* The type of floating-point to use. Keep this in sync with enum arm_float_model, and the help string in _initialize_arm_tdep. */ static const char *fp_model_strings[] = { "auto", "softfpa", "fpa", "softvfp", "vfp", NULL }; /* A variable that can be configured by the user. */ static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; static const char *current_fp_model = "auto"; /* The ABI to use. Keep this in sync with arm_abi_kind. */ static const char *arm_abi_strings[] = { "auto", "APCS", "AAPCS", NULL }; /* A variable that can be configured by the user. */ static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; static const char *arm_abi_string = "auto"; /* The execution mode to assume. */ static const char *arm_mode_strings[] = { "auto", "arm", "thumb" }; static const char *arm_fallback_mode_string = "auto"; static const char *arm_force_mode_string = "auto"; /* Number of different reg name sets (options). */ static int num_disassembly_options; /* The standard register names, and all the valid aliases for them. */ static const struct { const char *name; int regnum; } arm_register_aliases[] = { /* Basic register numbers. */ { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 }, { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 }, /* Synonyms (argument and variable registers). */ { "a1", 0 }, { "a2", 1 }, { "a3", 2 }, { "a4", 3 }, { "v1", 4 }, { "v2", 5 }, { "v3", 6 }, { "v4", 7 }, { "v5", 8 }, { "v6", 9 }, { "v7", 10 }, { "v8", 11 }, /* Other platform-specific names for r9. */ { "sb", 9 }, { "tr", 9 }, /* Special names. */ { "ip", 12 }, { "sp", 13 }, { "lr", 14 }, { "pc", 15 }, /* Names used by GCC (not listed in the ARM EABI). */ { "sl", 10 }, { "fp", 11 }, /* A special name from the older ATPCS. */ { "wr", 7 }, }; static const char *const arm_register_names[] = {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ "r4", "r5", "r6", "r7", /* 4 5 6 7 */ "r8", "r9", "r10", "r11", /* 8 9 10 11 */ "r12", "sp", "lr", "pc", /* 12 13 14 15 */ "f0", "f1", "f2", "f3", /* 16 17 18 19 */ "f4", "f5", "f6", "f7", /* 20 21 22 23 */ "fps", "cpsr" }; /* 24 25 */ /* Valid register name styles. */ static const char **valid_disassembly_styles; /* Disassembly style to use. Default to "std" register names. */ static const char *disassembly_style; /* This is used to keep the bfd arch_info in sync with the disassembly style. */ static void set_disassembly_style_sfunc(char *, int, struct cmd_list_element *); static void set_disassembly_style (void); static void convert_from_extended (const struct floatformat *, const void *, void *, int); static void convert_to_extended (const struct floatformat *, void *, const void *, int); static void arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache, int regnum, gdb_byte *buf); static void arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf); struct arm_prologue_cache { /* The stack pointer at the time this frame was created; i.e. the caller's stack pointer when this function was called. It is used to identify this frame. */ CORE_ADDR prev_sp; /* The frame base for this frame is just prev_sp - frame size. FRAMESIZE is the distance from the frame pointer to the initial stack pointer. */ int framesize; /* The register used to hold the frame pointer for this frame. */ int framereg; /* Saved register offsets. */ struct trad_frame_saved_reg *saved_regs; }; static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache); /* Architecture version for displaced stepping. This effects the behaviour of certain instructions, and really should not be hard-wired. */ #define DISPLACED_STEPPING_ARCH_VERSION 5 /* Addresses for calling Thumb functions have the bit 0 set. Here are some macros to test, set, or clear bit 0 of addresses. */ #define IS_THUMB_ADDR(addr) ((addr) & 1) #define MAKE_THUMB_ADDR(addr) ((addr) | 1) #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) /* Set to true if the 32-bit mode is in use. */ int arm_apcs_32 = 1; /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ static int arm_psr_thumb_bit (struct gdbarch *gdbarch) { if (gdbarch_tdep (gdbarch)->is_m) return XPSR_T; else return CPSR_T; } /* Determine if FRAME is executing in Thumb mode. */ int arm_frame_is_thumb (struct frame_info *frame) { CORE_ADDR cpsr; ULONGEST t_bit = arm_psr_thumb_bit (get_frame_arch (frame)); /* Every ARM frame unwinder can unwind the T bit of the CPSR, either directly (from a signal frame or dummy frame) or by interpreting the saved LR (from a prologue or DWARF frame). So consult it and trust the unwinders. */ cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); return (cpsr & t_bit) != 0; } /* Callback for VEC_lower_bound. */ static inline int arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, const struct arm_mapping_symbol *rhs) { return lhs->value < rhs->value; } /* Search for the mapping symbol covering MEMADDR. If one is found, return its type. Otherwise, return 0. If START is non-NULL, set *START to the location of the mapping symbol. */ static char arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) { struct obj_section *sec; /* If there are mapping symbols, consult them. */ sec = find_pc_section (memaddr); if (sec != NULL) { struct arm_per_objfile *data; VEC(arm_mapping_symbol_s) *map; struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), 0 }; unsigned int idx; data = objfile_data (sec->objfile, arm_objfile_data_key); if (data != NULL) { map = data->section_maps[sec->the_bfd_section->index]; if (!VEC_empty (arm_mapping_symbol_s, map)) { struct arm_mapping_symbol *map_sym; idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, arm_compare_mapping_symbols); /* VEC_lower_bound finds the earliest ordered insertion point. If the following symbol starts at this exact address, we use that; otherwise, the preceding mapping symbol covers this address. */ if (idx < VEC_length (arm_mapping_symbol_s, map)) { map_sym = VEC_index (arm_mapping_symbol_s, map, idx); if (map_sym->value == map_key.value) { if (start) *start = map_sym->value + obj_section_addr (sec); return map_sym->type; } } if (idx > 0) { map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); if (start) *start = map_sym->value + obj_section_addr (sec); return map_sym->type; } } } } return 0; } static CORE_ADDR arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt); /* Determine if the program counter specified in MEMADDR is in a Thumb function. This function should be called for addresses unrelated to any executing frame; otherwise, prefer arm_frame_is_thumb. */ static int arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) { struct obj_section *sec; struct minimal_symbol *sym; char type; /* If bit 0 of the address is set, assume this is a Thumb address. */ if (IS_THUMB_ADDR (memaddr)) return 1; /* If the user wants to override the symbol table, let him. */ if (strcmp (arm_force_mode_string, "arm") == 0) return 0; if (strcmp (arm_force_mode_string, "thumb") == 0) return 1; /* ARM v6-M and v7-M are always in Thumb mode. */ if (gdbarch_tdep (gdbarch)->is_m) return 1; /* If there are mapping symbols, consult them. */ type = arm_find_mapping_symbol (memaddr, NULL); if (type) return type == 't'; /* Thumb functions have a "special" bit set in minimal symbols. */ sym = lookup_minimal_symbol_by_pc (memaddr); if (sym) return (MSYMBOL_IS_SPECIAL (sym)); /* If the user wants to override the fallback mode, let them. */ if (strcmp (arm_fallback_mode_string, "arm") == 0) return 0; if (strcmp (arm_fallback_mode_string, "thumb") == 0) return 1; /* If we couldn't find any symbol, but we're talking to a running target, then trust the current value of $cpsr. This lets "display/i $pc" always show the correct mode (though if there is a symbol table we will not reach here, so it still may not be displayed in the mode it will be executed). As a further heuristic if we detect that we are doing a single-step we see what state executing the current instruction ends up with us being in. */ if (target_has_registers) { struct frame_info *current_frame = get_current_frame (); CORE_ADDR current_pc = get_frame_pc (current_frame); int is_thumb = arm_frame_is_thumb (current_frame); CORE_ADDR next_pc; if (memaddr == current_pc) return is_thumb; else { struct gdbarch *gdbarch = get_frame_arch (current_frame); next_pc = arm_get_next_pc_raw (current_frame, current_pc, FALSE); if (memaddr == gdbarch_addr_bits_remove (gdbarch, next_pc)) return IS_THUMB_ADDR (next_pc); else return is_thumb; } } /* Otherwise we're out of luck; we assume ARM. */ return 0; } /* Remove useless bits from addresses in a running program. */ static CORE_ADDR arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) { if (arm_apcs_32) return UNMAKE_THUMB_ADDR (val); else return (val & 0x03fffffc); } /* When reading symbols, we need to zap the low bit of the address, which may be set to 1 for Thumb functions. */ static CORE_ADDR arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val) { return val & ~1; } /* Return 1 if PC is the start of a compiler helper function which can be safely ignored during prologue skipping. */ static int skip_prologue_function (CORE_ADDR pc) { struct minimal_symbol *msym; const char *name; msym = lookup_minimal_symbol_by_pc (pc); if (msym == NULL || SYMBOL_VALUE_ADDRESS (msym) != pc) return 0; name = SYMBOL_LINKAGE_NAME (msym); if (name == NULL) return 0; /* The GNU linker's Thumb call stub to foo is named __foo_from_thumb. */ if (strstr (name, "_from_thumb") != NULL) name += 2; /* On soft-float targets, __truncdfsf2 is called to convert promoted arguments to their argument types in non-prototyped functions. */ if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0) return 1; if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0) return 1; return 0; } /* Support routines for instruction parsing. */ #define submask(x) ((1L << ((x) + 1)) - 1) #define bit(obj,st) (((obj) >> (st)) & 1) #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) #define sbits(obj,st,fn) \ ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) #define BranchDest(addr,instr) \ ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) /* Analyze a Thumb prologue, looking for a recognizable stack frame and frame pointer. Scan until we encounter a store that could clobber the stack frame unexpectedly, or an unknown instruction. Return the last address which is definitely safe to skip for an initial breakpoint. */ static CORE_ADDR thumb_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR limit, struct arm_prologue_cache *cache) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); int i; pv_t regs[16]; struct pv_area *stack; struct cleanup *back_to; CORE_ADDR offset; for (i = 0; i < 16; i++) regs[i] = pv_register (i, 0); stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); back_to = make_cleanup_free_pv_area (stack); while (start < limit) { unsigned short insn; insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ { int regno; int mask; if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) break; /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says whether to save LR (R14). */ mask = (insn & 0xff) | ((insn & 0x100) << 6); /* Calculate offsets of saved R0-R7 and LR. */ for (regno = ARM_LR_REGNUM; regno >= 0; regno--) if (mask & (1 << regno)) { regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); } } else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ { offset = (insn & 0x7f) << 2; /* get scaled offset */ if (insn & 0x80) /* Check for SUB. */ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -offset); else regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], offset); } else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], (insn & 0xff) << 2); else if ((insn & 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */ && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) regs[bits (insn, 0, 2)] = pv_add_constant (regs[bits (insn, 3, 5)], bits (insn, 6, 8)); else if ((insn & 0xf800) == 0x3000 /* add Rd, #imm */ && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) regs[bits (insn, 8, 10)] = pv_add_constant (regs[bits (insn, 8, 10)], bits (insn, 0, 7)); else if ((insn & 0xfe00) == 0x1800 /* add Rd, Rn, Rm */ && pv_is_register (regs[bits (insn, 6, 8)], ARM_SP_REGNUM) && pv_is_constant (regs[bits (insn, 3, 5)])) regs[bits (insn, 0, 2)] = pv_add (regs[bits (insn, 3, 5)], regs[bits (insn, 6, 8)]); else if ((insn & 0xff00) == 0x4400 /* add Rd, Rm */ && pv_is_constant (regs[bits (insn, 3, 6)])) { int rd = (bit (insn, 7) << 3) + bits (insn, 0, 2); int rm = bits (insn, 3, 6); regs[rd] = pv_add (regs[rd], regs[rm]); } else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ { int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); int src_reg = (insn & 0x78) >> 3; regs[dst_reg] = regs[src_reg]; } else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ { /* Handle stores to the stack. Normally pushes are used, but with GCC -mtpcs-frame, there may be other stores in the prologue to create the frame. */ int regno = (insn >> 8) & 0x7; pv_t addr; offset = (insn & 0xff) << 2; addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); if (pv_area_store_would_trash (stack, addr)) break; pv_area_store (stack, addr, 4, regs[regno]); } else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */ { int rd = bits (insn, 0, 2); int rn = bits (insn, 3, 5); pv_t addr; offset = bits (insn, 6, 10) << 2; addr = pv_add_constant (regs[rn], offset); if (pv_area_store_would_trash (stack, addr)) break; pv_area_store (stack, addr, 4, regs[rd]); } else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */ || (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */ && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM)) /* Ignore stores of argument registers to the stack. */ ; else if ((insn & 0xf800) == 0xc800 /* ldmia Rn!, { registers } */ && pv_is_register (regs[bits (insn, 8, 10)], ARM_SP_REGNUM)) /* Ignore block loads from the stack, potentially copying parameters from memory. */ ; else if ((insn & 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */ || ((insn & 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */ && pv_is_register (regs[bits (insn, 3, 5)], ARM_SP_REGNUM))) /* Similarly ignore single loads from the stack. */ ; else if ((insn & 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */ || (insn & 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */ /* Skip register copies, i.e. saves to another register instead of the stack. */ ; else if ((insn & 0xf800) == 0x2000) /* movs Rd, #imm */ /* Recognize constant loads; even with small stacks these are necessary on Thumb. */ regs[bits (insn, 8, 10)] = pv_constant (bits (insn, 0, 7)); else if ((insn & 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */ { /* Constant pool loads, for the same reason. */ unsigned int constant; CORE_ADDR loc; loc = start + 4 + bits (insn, 0, 7) * 4; constant = read_memory_unsigned_integer (loc, 4, byte_order); regs[bits (insn, 8, 10)] = pv_constant (constant); } else if ((insn & 0xe000) == 0xe000 && cache == NULL) { /* Only recognize 32-bit instructions for prologue skipping. */ unsigned short inst2; inst2 = read_memory_unsigned_integer (start + 2, 2, byte_order_for_code); if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) { /* BL, BLX. Allow some special function calls when skipping the prologue; GCC generates these before storing arguments to the stack. */ CORE_ADDR nextpc; int j1, j2, imm1, imm2; imm1 = sbits (insn, 0, 10); imm2 = bits (inst2, 0, 10); j1 = bit (inst2, 13); j2 = bit (inst2, 11); offset = ((imm1 << 12) + (imm2 << 1)); offset ^= ((!j2) << 22) | ((!j1) << 23); nextpc = start + 4 + offset; /* For BLX make sure to clear the low bits. */ if (bit (inst2, 12) == 0) nextpc = nextpc & 0xfffffffc; if (!skip_prologue_function (nextpc)) break; } else if ((insn & 0xfe50) == 0xe800 /* stm{db,ia} Rn[!], { registers } */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) ; else if ((insn & 0xfe50) == 0xe840 /* strd Rt, Rt2, [Rn, #imm] */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) ; else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */ && (inst2 & 0x8000) == 0x0000 && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) ; else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */ && (inst2 & 0x8000) == 0x0000) /* Since we only recognize this for prologue skipping, do not bother to compute the constant. */ regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)]; else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm12 */ && (inst2 & 0x8000) == 0x0000) /* Since we only recognize this for prologue skipping, do not bother to compute the constant. */ regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)]; else if ((insn & 0xfbf0) == 0xf2a0 /* sub.w Rd, Rn, #imm8 */ && (inst2 & 0x8000) == 0x0000) /* Since we only recognize this for prologue skipping, do not bother to compute the constant. */ regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)]; else if ((insn & 0xff50) == 0xf850 /* ldr.w Rd, [Rn, #imm]{!} */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) ; else if ((insn & 0xff50) == 0xe950 /* ldrd Rt, Rt2, [Rn, #imm]{!} */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) ; else if ((insn & 0xff50) == 0xf800 /* strb.w or strh.w */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) ; else { /* We don't know what this instruction is. We're finished scanning. NOTE: Recognizing more safe-to-ignore instructions here will improve support for optimized code. */ break; } start += 2; } else { /* We don't know what this instruction is. We're finished scanning. NOTE: Recognizing more safe-to-ignore instructions here will improve support for optimized code. */ break; } start += 2; } if (arm_debug) fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", paddress (gdbarch, start)); if (cache == NULL) { do_cleanups (back_to); return start; } if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) { /* Frame pointer is fp. Frame size is constant. */ cache->framereg = ARM_FP_REGNUM; cache->framesize = -regs[ARM_FP_REGNUM].k; } else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) { /* Frame pointer is r7. Frame size is constant. */ cache->framereg = THUMB_FP_REGNUM; cache->framesize = -regs[THUMB_FP_REGNUM].k; } else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) { /* Try the stack pointer... this is a bit desperate. */ cache->framereg = ARM_SP_REGNUM; cache->framesize = -regs[ARM_SP_REGNUM].k; } else { /* We're just out of luck. We don't know where the frame is. */ cache->framereg = -1; cache->framesize = 0; } for (i = 0; i < 16; i++) if (pv_area_find_reg (stack, gdbarch, i, &offset)) cache->saved_regs[i].addr = offset; do_cleanups (back_to); return start; } /* Advance the PC across any function entry prologue instructions to reach some "real" code. The APCS (ARM Procedure Call Standard) defines the following prologue: mov ip, sp [stmfd sp!, {a1,a2,a3,a4}] stmfd sp!, {...,fp,ip,lr,pc} [stfe f7, [sp, #-12]!] [stfe f6, [sp, #-12]!] [stfe f5, [sp, #-12]!] [stfe f4, [sp, #-12]!] sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ static CORE_ADDR arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned long inst; CORE_ADDR skip_pc; CORE_ADDR func_addr, limit_pc; struct symtab_and_line sal; /* See if we can determine the end of the prologue via the symbol table. If so, then return either PC, or the PC after the prologue, whichever is greater. */ if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) { CORE_ADDR post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); struct symtab *s = find_pc_symtab (func_addr); /* GCC always emits a line note before the prologue and another one after, even if the two are at the same address or on the same line. Take advantage of this so that we do not need to know every instruction that might appear in the prologue. We will have producer information for most binaries; if it is missing (e.g. for -gstabs), assuming the GNU tools. */ if (post_prologue_pc && (s == NULL || s->producer == NULL || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0)) return post_prologue_pc; if (post_prologue_pc != 0) { CORE_ADDR analyzed_limit; /* For non-GCC compilers, make sure the entire line is an acceptable prologue; GDB will round this function's return value up to the end of the following line so we can not skip just part of a line (and we do not want to). RealView does not treat the prologue specially, but does associate prologue code with the opening brace; so this lets us skip the first line if we think it is the opening brace. */ if (arm_pc_is_thumb (gdbarch, func_addr)) analyzed_limit = thumb_analyze_prologue (gdbarch, func_addr, post_prologue_pc, NULL); else analyzed_limit = arm_analyze_prologue (gdbarch, func_addr, post_prologue_pc, NULL); if (analyzed_limit != post_prologue_pc) return func_addr; return post_prologue_pc; } } /* Can't determine prologue from the symbol table, need to examine instructions. */ /* Find an upper limit on the function prologue using the debug information. If the debug information could not be used to provide that bound, then use an arbitrary large number as the upper bound. */ /* Like arm_scan_prologue, stop no later than pc + 64. */ limit_pc = skip_prologue_using_sal (gdbarch, pc); if (limit_pc == 0) limit_pc = pc + 64; /* Magic. */ /* Check if this is Thumb code. */ if (arm_pc_is_thumb (gdbarch, pc)) return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) { inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); /* "mov ip, sp" is no longer a required part of the prologue. */ if (inst == 0xe1a0c00d) /* mov ip, sp */ continue; if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ continue; if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ continue; /* Some prologues begin with "str lr, [sp, #-4]!". */ if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ continue; if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ continue; if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ continue; /* Any insns after this point may float into the code, if it makes for better instruction scheduling, so we skip them only if we find them, but still consider the function to be frame-ful. */ /* We may have either one sfmfd instruction here, or several stfe insns, depending on the version of floating point code we support. */ if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, , [sp]! */ continue; if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ continue; if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ continue; if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ continue; if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */ || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */ || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ continue; if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */ || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */ || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ continue; /* Un-recognized instruction; stop scanning. */ break; } return skip_pc; /* End of prologue */ } /* *INDENT-OFF* */ /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) This function decodes a Thumb function prologue to determine: 1) the size of the stack frame 2) which registers are saved on it 3) the offsets of saved regs 4) the offset from the stack pointer to the frame pointer A typical Thumb function prologue would create this stack frame (offsets relative to FP) old SP -> 24 stack parameters 20 LR 16 R7 R7 -> 0 local variables (16 bytes) SP -> -12 additional stack space (12 bytes) The frame size would thus be 36 bytes, and the frame offset would be 12 bytes. The frame register is R7. The comments for thumb_skip_prolog() describe the algorithm we use to detect the end of the prolog. */ /* *INDENT-ON* */ static void thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, CORE_ADDR block_addr, struct arm_prologue_cache *cache) { CORE_ADDR prologue_start; CORE_ADDR prologue_end; CORE_ADDR current_pc; if (find_pc_partial_function (block_addr, NULL, &prologue_start, &prologue_end)) { struct symtab_and_line sal = find_pc_line (prologue_start, 0); if (sal.line == 0) /* no line info, use current PC */ prologue_end = prev_pc; else if (sal.end < prologue_end) /* next line begins after fn end */ prologue_end = sal.end; /* (probably means no prologue) */ } else /* We're in the boondocks: we have no idea where the start of the function is. */ return; prologue_end = min (prologue_end, prev_pc); thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); } /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */ static int arm_instruction_changes_pc (uint32_t this_instr) { if (bits (this_instr, 28, 31) == INST_NV) /* Unconditional instructions. */ switch (bits (this_instr, 24, 27)) { case 0xa: case 0xb: /* Branch with Link and change to Thumb. */ return 1; case 0xc: case 0xd: case 0xe: /* Coprocessor register transfer. */ if (bits (this_instr, 12, 15) == 15) error (_("Invalid update to pc in instruction")); return 0; default: return 0; } else switch (bits (this_instr, 25, 27)) { case 0x0: if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0) { /* Multiplies and extra load/stores. */ if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1) /* Neither multiplies nor extension load/stores are allowed to modify PC. */ return 0; /* Otherwise, miscellaneous instructions. */ /* BX , BXJ , BLX */ if (bits (this_instr, 4, 27) == 0x12fff1 || bits (this_instr, 4, 27) == 0x12fff2 || bits (this_instr, 4, 27) == 0x12fff3) return 1; /* Other miscellaneous instructions are unpredictable if they modify PC. */ return 0; } /* Data processing instruction. Fall through. */ case 0x1: if (bits (this_instr, 12, 15) == 15) return 1; else return 0; case 0x2: case 0x3: /* Media instructions and architecturally undefined instructions. */ if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1) return 0; /* Stores. */ if (bit (this_instr, 20) == 0) return 0; /* Loads. */ if (bits (this_instr, 12, 15) == ARM_PC_REGNUM) return 1; else return 0; case 0x4: /* Load/store multiple. */ if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1) return 1; else return 0; case 0x5: /* Branch and branch with link. */ return 1; case 0x6: case 0x7: /* Coprocessor transfers or SWIs can not affect PC. */ return 0; default: internal_error (__FILE__, __LINE__, "bad value in switch"); } } /* Analyze an ARM mode prologue starting at PROLOGUE_START and continuing no further than PROLOGUE_END. If CACHE is non-NULL, fill it in. Return the first address not recognized as a prologue instruction. We recognize all the instructions typically found in ARM prologues, plus harmless instructions which can be skipped (either for analysis purposes, or a more restrictive set that can be skipped when finding the end of the prologue). */ static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); int regno; CORE_ADDR offset, current_pc; pv_t regs[ARM_FPS_REGNUM]; struct pv_area *stack; struct cleanup *back_to; int framereg, framesize; CORE_ADDR unrecognized_pc = 0; /* Search the prologue looking for instructions that set up the frame pointer, adjust the stack pointer, and save registers. Be careful, however, and if it doesn't look like a prologue, don't try to scan it. If, for instance, a frameless function begins with stmfd sp!, then we will tell ourselves there is a frame, which will confuse stack traceback, as well as "finish" and other operations that rely on a knowledge of the stack traceback. */ for (regno = 0; regno < ARM_FPS_REGNUM; regno++) regs[regno] = pv_register (regno, 0); stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); back_to = make_cleanup_free_pv_area (stack); for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 4) { unsigned int insn = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); if (insn == 0xe1a0c00d) /* mov ip, sp */ { regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; continue; } else if ((insn & 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */ && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) { unsigned imm = insn & 0xff; /* immediate value */ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ int rd = bits (insn, 12, 15); imm = (imm >> rot) | (imm << (32 - rot)); regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], imm); continue; } else if ((insn & 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */ && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) { unsigned imm = insn & 0xff; /* immediate value */ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ int rd = bits (insn, 12, 15); imm = (imm >> rot) | (imm << (32 - rot)); regs[rd] = pv_add_constant (regs[bits (insn, 16, 19)], -imm); continue; } else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */ { if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) break; regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[bits (insn, 12, 15)]); continue; } else if ((insn & 0xffff0000) == 0xe92d0000) /* stmfd sp!, {..., fp, ip, lr, pc} or stmfd sp!, {a1, a2, a3, a4} */ { int mask = insn & 0xffff; if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) break; /* Calculate offsets of saved registers. */ for (regno = ARM_PC_REGNUM; regno >= 0; regno--) if (mask & (1 << regno)) { regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); } } else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */ || (insn & 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ { /* No need to add this to saved_regs -- it's just an arg reg. */ continue; } else if ((insn & 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */ || (insn & 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ { /* No need to add this to saved_regs -- it's just an arg reg. */ continue; } else if ((insn & 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */ && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) { /* No need to add this to saved_regs -- it's just arg regs. */ continue; } else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ { unsigned imm = insn & 0xff; /* immediate value */ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ imm = (imm >> rot) | (imm << (32 - rot)); regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); } else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ { unsigned imm = insn & 0xff; /* immediate value */ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ imm = (imm >> rot) | (imm << (32 - rot)); regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); } else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ && gdbarch_tdep (gdbarch)->have_fpa_registers) { if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) break; regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); } else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ && gdbarch_tdep (gdbarch)->have_fpa_registers) { int n_saved_fp_regs; unsigned int fp_start_reg, fp_bound_reg; if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) break; if ((insn & 0x800) == 0x800) /* N0 is set */ { if ((insn & 0x40000) == 0x40000) /* N1 is set */ n_saved_fp_regs = 3; else n_saved_fp_regs = 1; } else { if ((insn & 0x40000) == 0x40000) /* N1 is set */ n_saved_fp_regs = 2; else n_saved_fp_regs = 4; } fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); fp_bound_reg = fp_start_reg + n_saved_fp_regs; for (; fp_start_reg < fp_bound_reg; fp_start_reg++) { regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[fp_start_reg++]); } } else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */ { /* Allow some special function calls when skipping the prologue; GCC generates these before storing arguments to the stack. */ CORE_ADDR dest = BranchDest (current_pc, insn); if (skip_prologue_function (dest)) continue; else break; } else if ((insn & 0xf0000000) != 0xe0000000) break; /* Condition not true, exit early */ else if (arm_instruction_changes_pc (insn)) /* Don't scan past anything that might change control flow. */ break; else if ((insn & 0xfe500000) == 0xe8100000) /* ldm */ { /* Ignore block loads from the stack, potentially copying parameters from memory. */ if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) continue; else break; } else if ((insn & 0xfc500000) == 0xe4100000) { /* Similarly ignore single loads from the stack. */ if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) continue; else break; } else if ((insn & 0xffff0ff0) == 0xe1a00000) /* MOV Rd, Rm. Skip register copies, i.e. saves to another register instead of the stack. */ continue; else { /* The optimizer might shove anything into the prologue, so we just skip what we don't recognize. */ unrecognized_pc = current_pc; continue; } } if (unrecognized_pc == 0) unrecognized_pc = current_pc; /* The frame size is just the distance from the frame register to the original stack pointer. */ if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) { /* Frame pointer is fp. */ framereg = ARM_FP_REGNUM; framesize = -regs[ARM_FP_REGNUM].k; } else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) { /* Try the stack pointer... this is a bit desperate. */ framereg = ARM_SP_REGNUM; framesize = -regs[ARM_SP_REGNUM].k; } else { /* We're just out of luck. We don't know where the frame is. */ framereg = -1; framesize = 0; } if (cache) { cache->framereg = framereg; cache->framesize = framesize; for (regno = 0; regno < ARM_FPS_REGNUM; regno++) if (pv_area_find_reg (stack, gdbarch, regno, &offset)) cache->saved_regs[regno].addr = offset; } if (arm_debug) fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n", paddress (gdbarch, unrecognized_pc)); do_cleanups (back_to); return unrecognized_pc; } static void arm_scan_prologue (struct frame_info *this_frame, struct arm_prologue_cache *cache) { struct gdbarch *gdbarch = get_frame_arch (this_frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int regno; CORE_ADDR prologue_start, prologue_end, current_pc; CORE_ADDR prev_pc = get_frame_pc (this_frame); CORE_ADDR block_addr = get_frame_address_in_block (this_frame); pv_t regs[ARM_FPS_REGNUM]; struct pv_area *stack; struct cleanup *back_to; CORE_ADDR offset; /* Assume there is no frame until proven otherwise. */ cache->framereg = ARM_SP_REGNUM; cache->framesize = 0; /* Check for Thumb prologue. */ if (arm_frame_is_thumb (this_frame)) { thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); return; } /* Find the function prologue. If we can't find the function in the symbol table, peek in the stack frame to find the PC. */ if (find_pc_partial_function (block_addr, NULL, &prologue_start, &prologue_end)) { /* One way to find the end of the prologue (which works well for unoptimized code) is to do the following: struct symtab_and_line sal = find_pc_line (prologue_start, 0); if (sal.line == 0) prologue_end = prev_pc; else if (sal.end < prologue_end) prologue_end = sal.end; This mechanism is very accurate so long as the optimizer doesn't move any instructions from the function body into the prologue. If this happens, sal.end will be the last instruction in the first hunk of prologue code just before the first instruction that the scheduler has moved from the body to the prologue. In order to make sure that we scan all of the prologue instructions, we use a slightly less accurate mechanism which may scan more than necessary. To help compensate for this lack of accuracy, the prologue scanning loop below contains several clauses which'll cause the loop to terminate early if an implausible prologue instruction is encountered. The expression prologue_start + 64 is a suitable endpoint since it accounts for the largest possible prologue plus up to five instructions inserted by the scheduler. */ if (prologue_end > prologue_start + 64) { prologue_end = prologue_start + 64; /* See above. */ } } else { /* We have no symbol information. Our only option is to assume this function has a standard stack frame and the normal frame register. Then, we can find the value of our frame pointer on entrance to the callee (or at the present moment if this is the innermost frame). The value stored there should be the address of the stmfd + 8. */ CORE_ADDR frame_loc; LONGEST return_value; frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) return; else { prologue_start = gdbarch_addr_bits_remove (gdbarch, return_value) - 8; prologue_end = prologue_start + 64; /* See above. */ } } if (prev_pc < prologue_end) prologue_end = prev_pc; arm_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); } static struct arm_prologue_cache * arm_make_prologue_cache (struct frame_info *this_frame) { int reg; struct arm_prologue_cache *cache; CORE_ADDR unwound_fp; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); arm_scan_prologue (this_frame, cache); unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); if (unwound_fp == 0) return cache; cache->prev_sp = unwound_fp + cache->framesize; /* Calculate actual addresses of saved registers using offsets determined by arm_scan_prologue. */ for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) if (trad_frame_addr_p (cache->saved_regs, reg)) cache->saved_regs[reg].addr += cache->prev_sp; return cache; } /* Our frame ID for a normal frame is the current function's starting PC and the caller's SP when we were called. */ static void arm_prologue_this_id (struct frame_info *this_frame, void **this_cache, struct frame_id *this_id) { struct arm_prologue_cache *cache; struct frame_id id; CORE_ADDR pc, func; if (*this_cache == NULL) *this_cache = arm_make_prologue_cache (this_frame); cache = *this_cache; /* This is meant to halt the backtrace at "_start". */ pc = get_frame_pc (this_frame); if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) return; /* If we've hit a wall, stop. */ if (cache->prev_sp == 0) return; func = get_frame_func (this_frame); id = frame_id_build (cache->prev_sp, func); *this_id = id; } static struct value * arm_prologue_prev_register (struct frame_info *this_frame, void **this_cache, int prev_regnum) { struct gdbarch *gdbarch = get_frame_arch (this_frame); struct arm_prologue_cache *cache; if (*this_cache == NULL) *this_cache = arm_make_prologue_cache (this_frame); cache = *this_cache; /* If we are asked to unwind the PC, then we need to return the LR instead. The prologue may save PC, but it will point into this frame's prologue, not the next frame's resume location. Also strip the saved T bit. A valid LR may have the low bit set, but a valid PC never does. */ if (prev_regnum == ARM_PC_REGNUM) { CORE_ADDR lr; lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); return frame_unwind_got_constant (this_frame, prev_regnum, arm_addr_bits_remove (gdbarch, lr)); } /* SP is generally not saved to the stack, but this frame is identified by the next frame's stack pointer at the time of the call. The value was already reconstructed into PREV_SP. */ if (prev_regnum == ARM_SP_REGNUM) return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); /* The CPSR may have been changed by the call instruction and by the called function. The only bit we can reconstruct is the T bit, by checking the low bit of LR as of the call. This is a reliable indicator of Thumb-ness except for some ARM v4T pre-interworking Thumb code, which could get away with a clear low bit as long as the called function did not use bx. Guess that all other bits are unchanged; the condition flags are presumably lost, but the processor status is likely valid. */ if (prev_regnum == ARM_PS_REGNUM) { CORE_ADDR lr, cpsr; ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); cpsr = get_frame_register_unsigned (this_frame, prev_regnum); lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); if (IS_THUMB_ADDR (lr)) cpsr |= t_bit; else cpsr &= ~t_bit; return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); } return trad_frame_get_prev_register (this_frame, cache->saved_regs, prev_regnum); } struct frame_unwind arm_prologue_unwind = { NORMAL_FRAME, arm_prologue_this_id, arm_prologue_prev_register, NULL, default_frame_sniffer }; static struct arm_prologue_cache * arm_make_stub_cache (struct frame_info *this_frame) { struct arm_prologue_cache *cache; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); return cache; } /* Our frame ID for a stub frame is the current SP and LR. */ static void arm_stub_this_id (struct frame_info *this_frame, void **this_cache, struct frame_id *this_id) { struct arm_prologue_cache *cache; if (*this_cache == NULL) *this_cache = arm_make_stub_cache (this_frame); cache = *this_cache; *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); } static int arm_stub_unwind_sniffer (const struct frame_unwind *self, struct frame_info *this_frame, void **this_prologue_cache) { CORE_ADDR addr_in_block; char dummy[4]; addr_in_block = get_frame_address_in_block (this_frame); if (in_plt_section (addr_in_block, NULL) /* We also use the stub winder if the target memory is unreadable to avoid having the prologue unwinder trying to read it. */ || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) return 1; return 0; } struct frame_unwind arm_stub_unwind = { NORMAL_FRAME, arm_stub_this_id, arm_prologue_prev_register, NULL, arm_stub_unwind_sniffer }; static CORE_ADDR arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) { struct arm_prologue_cache *cache; if (*this_cache == NULL) *this_cache = arm_make_prologue_cache (this_frame); cache = *this_cache; return cache->prev_sp - cache->framesize; } struct frame_base arm_normal_base = { &arm_prologue_unwind, arm_normal_frame_base, arm_normal_frame_base, arm_normal_frame_base }; /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy frame. The frame ID's base needs to match the TOS value saved by save_dummy_frame_tos() and returned from arm_push_dummy_call, and the PC needs to match the dummy frame's breakpoint. */ static struct frame_id arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) { return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), get_frame_pc (this_frame)); } /* Given THIS_FRAME, find the previous frame's resume PC (which will be used to construct the previous frame's ID, after looking up the containing function). */ static CORE_ADDR arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) { CORE_ADDR pc; pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); return arm_addr_bits_remove (gdbarch, pc); } static CORE_ADDR arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) { return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); } static struct value * arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, int regnum) { struct gdbarch * gdbarch = get_frame_arch (this_frame); CORE_ADDR lr, cpsr; ULONGEST t_bit = arm_psr_thumb_bit (gdbarch); switch (regnum) { case ARM_PC_REGNUM: /* The PC is normally copied from the return column, which describes saves of LR. However, that version may have an extra bit set to indicate Thumb state. The bit is not part of the PC. */ lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); return frame_unwind_got_constant (this_frame, regnum, arm_addr_bits_remove (gdbarch, lr)); case ARM_PS_REGNUM: /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ cpsr = get_frame_register_unsigned (this_frame, regnum); lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); if (IS_THUMB_ADDR (lr)) cpsr |= t_bit; else cpsr &= ~t_bit; return frame_unwind_got_constant (this_frame, regnum, cpsr); default: internal_error (__FILE__, __LINE__, _("Unexpected register %d"), regnum); } } static void arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame) { switch (regnum) { case ARM_PC_REGNUM: case ARM_PS_REGNUM: reg->how = DWARF2_FRAME_REG_FN; reg->loc.fn = arm_dwarf2_prev_register; break; case ARM_SP_REGNUM: reg->how = DWARF2_FRAME_REG_CFA; break; } } /* Return true if we are in the function's epilogue, i.e. after the instruction that destroyed the function's stack frame. */ static int thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned int insn, insn2; int found_return = 0, found_stack_adjust = 0; CORE_ADDR func_start, func_end; CORE_ADDR scan_pc; gdb_byte buf[4]; if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) return 0; /* The epilogue is a sequence of instructions along the following lines: - add stack frame size to SP or FP - [if frame pointer used] restore SP from FP - restore registers from SP [may include PC] - a return-type instruction [if PC wasn't already restored] In a first pass, we scan forward from the current PC and verify the instructions we find as compatible with this sequence, ending in a return instruction. However, this is not sufficient to distinguish indirect function calls within a function from indirect tail calls in the epilogue in some cases. Therefore, if we didn't already find any SP-changing instruction during forward scan, we add a backward scanning heuristic to ensure we actually are in the epilogue. */ scan_pc = pc; while (scan_pc < func_end && !found_return) { if (target_read_memory (scan_pc, buf, 2)) break; scan_pc += 2; insn = extract_unsigned_integer (buf, 2, byte_order_for_code); if ((insn & 0xff80) == 0x4700) /* bx */ found_return = 1; else if (insn == 0x46f7) /* mov pc, lr */ found_return = 1; else if (insn == 0x46bd) /* mov sp, r7 */ found_stack_adjust = 1; else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */ found_stack_adjust = 1; else if ((insn & 0xfe00) == 0xbc00) /* pop */ { found_stack_adjust = 1; if (insn & 0x0100) /* include PC. */ found_return = 1; } else if ((insn & 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */ { if (target_read_memory (scan_pc, buf, 2)) break; scan_pc += 2; insn2 = extract_unsigned_integer (buf, 2, byte_order_for_code); if (insn == 0xe8bd) /* ldm.w sp!, */ { found_stack_adjust = 1; if (insn2 & 0x8000) /* include PC. */ found_return = 1; } else if (insn == 0xf85d /* ldr.w , [sp], #4 */ && (insn2 & 0x0fff) == 0x0b04) { found_stack_adjust = 1; if ((insn2 & 0xf000) == 0xf000) /* is PC. */ found_return = 1; } else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, */ && (insn2 & 0x0e00) == 0x0a00) found_stack_adjust = 1; else break; } else break; } if (!found_return) return 0; /* Since any instruction in the epilogue sequence, with the possible exception of return itself, updates the stack pointer, we need to scan backwards for at most one instruction. Try either a 16-bit or a 32-bit instruction. This is just a heuristic, so we do not worry too much about false positives.*/ if (!found_stack_adjust) { if (pc - 4 < func_start) return 0; if (target_read_memory (pc - 4, buf, 4)) return 0; insn = extract_unsigned_integer (buf, 2, byte_order_for_code); insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); if (insn2 == 0x46bd) /* mov sp, r7 */ found_stack_adjust = 1; else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */ found_stack_adjust = 1; else if ((insn2 & 0xff00) == 0xbc00) /* pop without PC */ found_stack_adjust = 1; else if (insn == 0xe8bd) /* ldm.w sp!, */ found_stack_adjust = 1; else if (insn == 0xf85d /* ldr.w , [sp], #4 */ && (insn2 & 0x0fff) == 0x0b04) found_stack_adjust = 1; else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, */ && (insn2 & 0x0e00) == 0x0a00) found_stack_adjust = 1; } return found_stack_adjust; } /* Return true if we are in the function's epilogue, i.e. after the instruction that destroyed the function's stack frame. */ static int arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned int insn; int found_return, found_stack_adjust; CORE_ADDR func_start, func_end; if (arm_pc_is_thumb (gdbarch, pc)) return thumb_in_function_epilogue_p (gdbarch, pc); if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) return 0; /* We are in the epilogue if the previous instruction was a stack adjustment and the next instruction is a possible return (bx, mov pc, or pop). We could have to scan backwards to find the stack adjustment, or forwards to find the return, but this is a decent approximation. First scan forwards. */ found_return = 0; insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); if (bits (insn, 28, 31) != INST_NV) { if ((insn & 0x0ffffff0) == 0x012fff10) /* BX. */ found_return = 1; else if ((insn & 0x0ffffff0) == 0x01a0f000) /* MOV PC. */ found_return = 1; else if ((insn & 0x0fff0000) == 0x08bd0000 && (insn & 0x0000c000) != 0) /* POP (LDMIA), including PC or LR. */ found_return = 1; } if (!found_return) return 0; /* Scan backwards. This is just a heuristic, so do not worry about false positives from mode changes. */ if (pc < func_start + 4) return 0; insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); if (bits (insn, 28, 31) != INST_NV) { if ((insn & 0x0df0f000) == 0x0080d000) /* ADD SP (register or immediate). */ found_stack_adjust = 1; else if ((insn & 0x0df0f000) == 0x0040d000) /* SUB SP (register or immediate). */ found_stack_adjust = 1; else if ((insn & 0x0ffffff0) == 0x01a0d000) /* MOV SP. */ found_return = 1; else if ((insn & 0x0fff0000) == 0x08bd0000) /* POP (LDMIA). */ found_stack_adjust = 1; } if (found_stack_adjust) return 1; return 0; } /* When arguments must be pushed onto the stack, they go on in reverse order. The code below implements a FILO (stack) to do this. */ struct stack_item { int len; struct stack_item *prev; void *data; }; static struct stack_item * push_stack_item (struct stack_item *prev, const void *contents, int len) { struct stack_item *si; si = xmalloc (sizeof (struct stack_item)); si->data = xmalloc (len); si->len = len; si->prev = prev; memcpy (si->data, contents, len); return si; } static struct stack_item * pop_stack_item (struct stack_item *si) { struct stack_item *dead = si; si = si->prev; xfree (dead->data); xfree (dead); return si; } /* Return the alignment (in bytes) of the given type. */ static int arm_type_align (struct type *t) { int n; int align; int falign; t = check_typedef (t); switch (TYPE_CODE (t)) { default: /* Should never happen. */ internal_error (__FILE__, __LINE__, _("unknown type alignment")); return 4; case TYPE_CODE_PTR: case TYPE_CODE_ENUM: case TYPE_CODE_INT: case TYPE_CODE_FLT: case TYPE_CODE_SET: case TYPE_CODE_RANGE: case TYPE_CODE_BITSTRING: case TYPE_CODE_REF: case TYPE_CODE_CHAR: case TYPE_CODE_BOOL: return TYPE_LENGTH (t); case TYPE_CODE_ARRAY: case TYPE_CODE_COMPLEX: /* TODO: What about vector types? */ return arm_type_align (TYPE_TARGET_TYPE (t)); case TYPE_CODE_STRUCT: case TYPE_CODE_UNION: align = 1; for (n = 0; n < TYPE_NFIELDS (t); n++) { falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); if (falign > align) align = falign; } return align; } } /* Possible base types for a candidate for passing and returning in VFP registers. */ enum arm_vfp_cprc_base_type { VFP_CPRC_UNKNOWN, VFP_CPRC_SINGLE, VFP_CPRC_DOUBLE, VFP_CPRC_VEC64, VFP_CPRC_VEC128 }; /* The length of one element of base type B. */ static unsigned arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) { switch (b) { case VFP_CPRC_SINGLE: return 4; case VFP_CPRC_DOUBLE: return 8; case VFP_CPRC_VEC64: return 8; case VFP_CPRC_VEC128: return 16; default: internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), (int) b); } } /* The character ('s', 'd' or 'q') for the type of VFP register used for passing base type B. */ static int arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) { switch (b) { case VFP_CPRC_SINGLE: return 's'; case VFP_CPRC_DOUBLE: return 'd'; case VFP_CPRC_VEC64: return 'd'; case VFP_CPRC_VEC128: return 'q'; default: internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), (int) b); } } /* Determine whether T may be part of a candidate for passing and returning in VFP registers, ignoring the limit on the total number of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the classification of the first valid component found; if it is not VFP_CPRC_UNKNOWN, all components must have the same classification as *BASE_TYPE. If it is found that T contains a type not permitted for passing and returning in VFP registers, a type differently classified from *BASE_TYPE, or two types differently classified from each other, return -1, otherwise return the total number of base-type elements found (possibly 0 in an empty structure or array). Vectors and complex types are not currently supported, matching the generic AAPCS support. */ static int arm_vfp_cprc_sub_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type) { t = check_typedef (t); switch (TYPE_CODE (t)) { case TYPE_CODE_FLT: switch (TYPE_LENGTH (t)) { case 4: if (*base_type == VFP_CPRC_UNKNOWN) *base_type = VFP_CPRC_SINGLE; else if (*base_type != VFP_CPRC_SINGLE) return -1; return 1; case 8: if (*base_type == VFP_CPRC_UNKNOWN) *base_type = VFP_CPRC_DOUBLE; else if (*base_type != VFP_CPRC_DOUBLE) return -1; return 1; default: return -1; } break; case TYPE_CODE_ARRAY: { int count; unsigned unitlen; count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type); if (count == -1) return -1; if (TYPE_LENGTH (t) == 0) { gdb_assert (count == 0); return 0; } else if (count == 0) return -1; unitlen = arm_vfp_cprc_unit_length (*base_type); gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); return TYPE_LENGTH (t) / unitlen; } break; case TYPE_CODE_STRUCT: { int count = 0; unsigned unitlen; int i; for (i = 0; i < TYPE_NFIELDS (t); i++) { int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), base_type); if (sub_count == -1) return -1; count += sub_count; } if (TYPE_LENGTH (t) == 0) { gdb_assert (count == 0); return 0; } else if (count == 0) return -1; unitlen = arm_vfp_cprc_unit_length (*base_type); if (TYPE_LENGTH (t) != unitlen * count) return -1; return count; } case TYPE_CODE_UNION: { int count = 0; unsigned unitlen; int i; for (i = 0; i < TYPE_NFIELDS (t); i++) { int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), base_type); if (sub_count == -1) return -1; count = (count > sub_count ? count : sub_count); } if (TYPE_LENGTH (t) == 0) { gdb_assert (count == 0); return 0; } else if (count == 0) return -1; unitlen = arm_vfp_cprc_unit_length (*base_type); if (TYPE_LENGTH (t) != unitlen * count) return -1; return count; } default: break; } return -1; } /* Determine whether T is a VFP co-processor register candidate (CPRC) if passed to or returned from a non-variadic function with the VFP ABI in effect. Return 1 if it is, 0 otherwise. If it is, set *BASE_TYPE to the base type for T and *COUNT to the number of elements of that base type before returning. */ static int arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, int *count) { enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; int c = arm_vfp_cprc_sub_candidate (t, &b); if (c <= 0 || c > 4) return 0; *base_type = b; *count = c; return 1; } /* Return 1 if the VFP ABI should be used for passing arguments to and returning values from a function of type FUNC_TYPE, 0 otherwise. */ static int arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); /* Variadic functions always use the base ABI. Assume that functions without debug info are not variadic. */ if (func_type && TYPE_VARARGS (check_typedef (func_type))) return 0; /* The VFP ABI is only supported as a variant of AAPCS. */ if (tdep->arm_abi != ARM_ABI_AAPCS) return 0; return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; } /* We currently only support passing parameters in integer registers, which conforms with GCC's default model, and VFP argument passing following the VFP variant of AAPCS. Several other variants exist and we should probably support some of them based on the selected ABI. */ static CORE_ADDR arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int argnum; int argreg; int nstack; struct stack_item *si = NULL; int use_vfp_abi; struct type *ftype; unsigned vfp_regs_free = (1 << 16) - 1; /* Determine the type of this function and whether the VFP ABI applies. */ ftype = check_typedef (value_type (function)); if (TYPE_CODE (ftype) == TYPE_CODE_PTR) ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); /* Set the return address. For the ARM, the return breakpoint is always at BP_ADDR. */ if (arm_pc_is_thumb (gdbarch, bp_addr)) bp_addr |= 1; regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); /* Walk through the list of args and determine how large a temporary stack is required. Need to take care here as structs may be passed on the stack, and we have to to push them. */ nstack = 0; argreg = ARM_A1_REGNUM; nstack = 0; /* The struct_return pointer occupies the first parameter passing register. */ if (struct_return) { if (arm_debug) fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", gdbarch_register_name (gdbarch, argreg), paddress (gdbarch, struct_addr)); regcache_cooked_write_unsigned (regcache, argreg, struct_addr); argreg++; } for (argnum = 0; argnum < nargs; argnum++) { int len; struct type *arg_type; struct type *target_type; enum type_code typecode; const bfd_byte *val; int align; enum arm_vfp_cprc_base_type vfp_base_type; int vfp_base_count; int may_use_core_reg = 1; arg_type = check_typedef (value_type (args[argnum])); len = TYPE_LENGTH (arg_type); target_type = TYPE_TARGET_TYPE (arg_type); typecode = TYPE_CODE (arg_type); val = value_contents (args[argnum]); align = arm_type_align (arg_type); /* Round alignment up to a whole number of words. */ align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); /* Different ABIs have different maximum alignments. */ if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) { /* The APCS ABI only requires word alignment. */ align = INT_REGISTER_SIZE; } else { /* The AAPCS requires at most doubleword alignment. */ if (align > INT_REGISTER_SIZE * 2) align = INT_REGISTER_SIZE * 2; } if (use_vfp_abi && arm_vfp_call_candidate (arg_type, &vfp_base_type, &vfp_base_count)) { int regno; int unit_length; int shift; unsigned mask; /* Because this is a CPRC it cannot go in a core register or cause a core register to be skipped for alignment. Either it goes in VFP registers and the rest of this loop iteration is skipped for this argument, or it goes on the stack (and the stack alignment code is correct for this case). */ may_use_core_reg = 0; unit_length = arm_vfp_cprc_unit_length (vfp_base_type); shift = unit_length / 4; mask = (1 << (shift * vfp_base_count)) - 1; for (regno = 0; regno < 16; regno += shift) if (((vfp_regs_free >> regno) & mask) == mask) break; if (regno < 16) { int reg_char; int reg_scaled; int i; vfp_regs_free &= ~(mask << regno); reg_scaled = regno / shift; reg_char = arm_vfp_cprc_reg_char (vfp_base_type); for (i = 0; i < vfp_base_count; i++) { char name_buf[4]; int regnum; if (reg_char == 'q') arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, val + i * unit_length); else { sprintf (name_buf, "%c%d", reg_char, reg_scaled + i); regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, strlen (name_buf)); regcache_cooked_write (regcache, regnum, val + i * unit_length); } } continue; } else { /* This CPRC could not go in VFP registers, so all VFP registers are now marked as used. */ vfp_regs_free = 0; } } /* Push stack padding for dowubleword alignment. */ if (nstack & (align - 1)) { si = push_stack_item (si, val, INT_REGISTER_SIZE); nstack += INT_REGISTER_SIZE; } /* Doubleword aligned quantities must go in even register pairs. */ if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM && align > INT_REGISTER_SIZE && argreg & 1) argreg++; /* If the argument is a pointer to a function, and it is a Thumb function, create a LOCAL copy of the value and set the THUMB bit in it. */ if (TYPE_CODE_PTR == typecode && target_type != NULL && TYPE_CODE_FUNC == TYPE_CODE (check_typedef (target_type))) { CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); if (arm_pc_is_thumb (gdbarch, regval)) { bfd_byte *copy = alloca (len); store_unsigned_integer (copy, len, byte_order, MAKE_THUMB_ADDR (regval)); val = copy; } } /* Copy the argument to general registers or the stack in register-sized pieces. Large arguments are split between registers and stack. */ while (len > 0) { int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) { /* The argument is being passed in a general purpose register. */ CORE_ADDR regval = extract_unsigned_integer (val, partial_len, byte_order); if (byte_order == BFD_ENDIAN_BIG) regval <<= (INT_REGISTER_SIZE - partial_len) * 8; if (arm_debug) fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", argnum, gdbarch_register_name (gdbarch, argreg), phex (regval, INT_REGISTER_SIZE)); regcache_cooked_write_unsigned (regcache, argreg, regval); argreg++; } else { /* Push the arguments onto the stack. */ if (arm_debug) fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", argnum, nstack); si = push_stack_item (si, val, INT_REGISTER_SIZE); nstack += INT_REGISTER_SIZE; } len -= partial_len; val += partial_len; } } /* If we have an odd number of words to push, then decrement the stack by one word now, so first stack argument will be dword aligned. */ if (nstack & 4) sp -= 4; while (si) { sp -= si->len; write_memory (sp, si->data, si->len); si = pop_stack_item (si); } /* Finally, update teh SP register. */ regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); return sp; } /* Always align the frame to an 8-byte boundary. This is required on some platforms and harmless on the rest. */ static CORE_ADDR arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) { /* Align the stack to eight bytes. */ return sp & ~ (CORE_ADDR) 7; } static void print_fpu_flags (int flags) { if (flags & (1 << 0)) fputs ("IVO ", stdout); if (flags & (1 << 1)) fputs ("DVZ ", stdout); if (flags & (1 << 2)) fputs ("OFL ", stdout); if (flags & (1 << 3)) fputs ("UFL ", stdout); if (flags & (1 << 4)) fputs ("INX ", stdout); putchar ('\n'); } /* Print interesting information about the floating point processor (if present) or emulator. */ static void arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, struct frame_info *frame, const char *args) { unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); int type; type = (status >> 24) & 127; if (status & (1 << 31)) printf (_("Hardware FPU type %d\n"), type); else printf (_("Software FPU type %d\n"), type); /* i18n: [floating point unit] mask */ fputs (_("mask: "), stdout); print_fpu_flags (status >> 16); /* i18n: [floating point unit] flags */ fputs (_("flags: "), stdout); print_fpu_flags (status); } /* Construct the ARM extended floating point type. */ static struct type * arm_ext_type (struct gdbarch *gdbarch) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); if (!tdep->arm_ext_type) tdep->arm_ext_type = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", floatformats_arm_ext); return tdep->arm_ext_type; } static struct type * arm_neon_double_type (struct gdbarch *gdbarch) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); if (tdep->neon_double_type == NULL) { struct type *t, *elem; t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", TYPE_CODE_UNION); elem = builtin_type (gdbarch)->builtin_uint8; append_composite_type_field (t, "u8", init_vector_type (elem, 8)); elem = builtin_type (gdbarch)->builtin_uint16; append_composite_type_field (t, "u16", init_vector_type (elem, 4)); elem = builtin_type (gdbarch)->builtin_uint32; append_composite_type_field (t, "u32", init_vector_type (elem, 2)); elem = builtin_type (gdbarch)->builtin_uint64; append_composite_type_field (t, "u64", elem); elem = builtin_type (gdbarch)->builtin_float; append_composite_type_field (t, "f32", init_vector_type (elem, 2)); elem = builtin_type (gdbarch)->builtin_double; append_composite_type_field (t, "f64", elem); TYPE_VECTOR (t) = 1; TYPE_NAME (t) = "neon_d"; tdep->neon_double_type = t; } return tdep->neon_double_type; } /* FIXME: The vector types are not correctly ordered on big-endian targets. Just as s0 is the low bits of d0, d0[0] is also the low bits of d0 - regardless of what unit size is being held in d0. So the offset of the first uint8 in d0 is 7, but the offset of the first float is 4. This code works as-is for little-endian targets. */ static struct type * arm_neon_quad_type (struct gdbarch *gdbarch) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); if (tdep->neon_quad_type == NULL) { struct type *t, *elem; t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", TYPE_CODE_UNION); elem = builtin_type (gdbarch)->builtin_uint8; append_composite_type_field (t, "u8", init_vector_type (elem, 16)); elem = builtin_type (gdbarch)->builtin_uint16; append_composite_type_field (t, "u16", init_vector_type (elem, 8)); elem = builtin_type (gdbarch)->builtin_uint32; append_composite_type_field (t, "u32", init_vector_type (elem, 4)); elem = builtin_type (gdbarch)->builtin_uint64; append_composite_type_field (t, "u64", init_vector_type (elem, 2)); elem = builtin_type (gdbarch)->builtin_float; append_composite_type_field (t, "f32", init_vector_type (elem, 4)); elem = builtin_type (gdbarch)->builtin_double; append_composite_type_field (t, "f64", init_vector_type (elem, 2)); TYPE_VECTOR (t) = 1; TYPE_NAME (t) = "neon_q"; tdep->neon_quad_type = t; } return tdep->neon_quad_type; } /* Return the GDB type object for the "standard" data type of data in register N. */ static struct type * arm_register_type (struct gdbarch *gdbarch, int regnum) { int num_regs = gdbarch_num_regs (gdbarch); if (gdbarch_tdep (gdbarch)->have_vfp_pseudos && regnum >= num_regs && regnum < num_regs + 32) return builtin_type (gdbarch)->builtin_float; if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) return arm_neon_quad_type (gdbarch); /* If the target description has register information, we are only in this function so that we can override the types of double-precision registers for NEON. */ if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) { struct type *t = tdesc_register_type (gdbarch, regnum); if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 && TYPE_CODE (t) == TYPE_CODE_FLT && gdbarch_tdep (gdbarch)->have_neon) return arm_neon_double_type (gdbarch); else return t; } if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) { if (!gdbarch_tdep (gdbarch)->have_fpa_registers) return builtin_type (gdbarch)->builtin_void; return arm_ext_type (gdbarch); } else if (regnum == ARM_SP_REGNUM) return builtin_type (gdbarch)->builtin_data_ptr; else if (regnum == ARM_PC_REGNUM) return builtin_type (gdbarch)->builtin_func_ptr; else if (regnum >= ARRAY_SIZE (arm_register_names)) /* These registers are only supported on targets which supply an XML description. */ return builtin_type (gdbarch)->builtin_int0; else return builtin_type (gdbarch)->builtin_uint32; } /* Map a DWARF register REGNUM onto the appropriate GDB register number. */ static int arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) { /* Core integer regs. */ if (reg >= 0 && reg <= 15) return reg; /* Legacy FPA encoding. These were once used in a way which overlapped with VFP register numbering, so their use is discouraged, but GDB doesn't support the ARM toolchain which used them for VFP. */ if (reg >= 16 && reg <= 23) return ARM_F0_REGNUM + reg - 16; /* New assignments for the FPA registers. */ if (reg >= 96 && reg <= 103) return ARM_F0_REGNUM + reg - 96; /* WMMX register assignments. */ if (reg >= 104 && reg <= 111) return ARM_WCGR0_REGNUM + reg - 104; if (reg >= 112 && reg <= 127) return ARM_WR0_REGNUM + reg - 112; if (reg >= 192 && reg <= 199) return ARM_WC0_REGNUM + reg - 192; /* VFP v2 registers. A double precision value is actually in d1 rather than s2, but the ABI only defines numbering for the single precision registers. This will "just work" in GDB for little endian targets (we'll read eight bytes, starting in s0 and then progressing to s1), but will be reversed on big endian targets with VFP. This won't be a problem for the new Neon quad registers; you're supposed to use DW_OP_piece for those. */ if (reg >= 64 && reg <= 95) { char name_buf[4]; sprintf (name_buf, "s%d", reg - 64); return user_reg_map_name_to_regnum (gdbarch, name_buf, strlen (name_buf)); } /* VFP v3 / Neon registers. This range is also used for VFP v2 registers, except that it now describes d0 instead of s0. */ if (reg >= 256 && reg <= 287) { char name_buf[4]; sprintf (name_buf, "d%d", reg - 256); return user_reg_map_name_to_regnum (gdbarch, name_buf, strlen (name_buf)); } return -1; } /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ static int arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) { int reg = regnum; gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; if (reg < NUM_GREGS) return SIM_ARM_R0_REGNUM + reg; reg -= NUM_GREGS; if (reg < NUM_FREGS) return SIM_ARM_FP0_REGNUM + reg; reg -= NUM_FREGS; if (reg < NUM_SREGS) return SIM_ARM_FPS_REGNUM + reg; reg -= NUM_SREGS; internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); } /* NOTE: cagney/2001-08-20: Both convert_from_extended() and convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. It is thought that this is is the floating-point register format on little-endian systems. */ static void convert_from_extended (const struct floatformat *fmt, const void *ptr, void *dbl, int endianess) { DOUBLEST d; if (endianess == BFD_ENDIAN_BIG) floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); else floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, ptr, &d); floatformat_from_doublest (fmt, &d, dbl); } static void convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, int endianess) { DOUBLEST d; floatformat_to_doublest (fmt, ptr, &d); if (endianess == BFD_ENDIAN_BIG) floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); else floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, &d, dbl); } static int condition_true (unsigned long cond, unsigned long status_reg) { if (cond == INST_AL || cond == INST_NV) return 1; switch (cond) { case INST_EQ: return ((status_reg & FLAG_Z) != 0); case INST_NE: return ((status_reg & FLAG_Z) == 0); case INST_CS: return ((status_reg & FLAG_C) != 0); case INST_CC: return ((status_reg & FLAG_C) == 0); case INST_MI: return ((status_reg & FLAG_N) != 0); case INST_PL: return ((status_reg & FLAG_N) == 0); case INST_VS: return ((status_reg & FLAG_V) != 0); case INST_VC: return ((status_reg & FLAG_V) == 0); case INST_HI: return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); case INST_LS: return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); case INST_GE: return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); case INST_LT: return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); case INST_GT: return (((status_reg & FLAG_Z) == 0) && (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); case INST_LE: return (((status_reg & FLAG_Z) != 0) || (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); } return 1; } static unsigned long shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, unsigned long pc_val, unsigned long status_reg) { unsigned long res, shift; int rm = bits (inst, 0, 3); unsigned long shifttype = bits (inst, 5, 6); if (bit (inst, 4)) { int rs = bits (inst, 8, 11); shift = (rs == 15 ? pc_val + 8 : get_frame_register_unsigned (frame, rs)) & 0xFF; } else shift = bits (inst, 7, 11); res = (rm == 15 ? (pc_val + (bit (inst, 4) ? 12 : 8)) : get_frame_register_unsigned (frame, rm)); switch (shifttype) { case 0: /* LSL */ res = shift >= 32 ? 0 : res << shift; break; case 1: /* LSR */ res = shift >= 32 ? 0 : res >> shift; break; case 2: /* ASR */ if (shift >= 32) shift = 31; res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift); break; case 3: /* ROR/RRX */ shift &= 31; if (shift == 0) res = (res >> 1) | (carry ? 0x80000000L : 0); else res = (res >> shift) | (res << (32 - shift)); break; } return res & 0xffffffff; } /* Return number of 1-bits in VAL. */ static int bitcount (unsigned long val) { int nbits; for (nbits = 0; val != 0; nbits++) val &= val - 1; /* delete rightmost 1-bit in val */ return nbits; } /* Return the size in bytes of the complete Thumb instruction whose first halfword is INST1. */ static int thumb_insn_size (unsigned short inst1) { if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) return 4; else return 2; } static int thumb_advance_itstate (unsigned int itstate) { /* Preserve IT[7:5], the first three bits of the condition. Shift the upcoming condition flags left by one bit. */ itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f); /* If we have finished the IT block, clear the state. */ if ((itstate & 0x0f) == 0) itstate = 0; return itstate; } /* Find the next PC after the current instruction executes. In some cases we can not statically determine the answer (see the IT state handling in this function); in that case, a breakpoint may be inserted in addition to the returned PC, which will be used to set another breakpoint by our caller. */ static CORE_ADDR thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt) { struct gdbarch *gdbarch = get_frame_arch (frame); struct address_space *aspace = get_frame_address_space (frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ unsigned short inst1; CORE_ADDR nextpc = pc + 2; /* default is next instruction */ unsigned long offset; ULONGEST status, itstate; nextpc = MAKE_THUMB_ADDR (nextpc); pc_val = MAKE_THUMB_ADDR (pc_val); inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); /* Thumb-2 conditional execution support. There are eight bits in the CPSR which describe conditional execution state. Once reconstructed (they're in a funny order), the low five bits describe the low bit of the condition for each instruction and how many instructions remain. The high three bits describe the base condition. One of the low four bits will be set if an IT block is active. These bits read as zero on earlier processors. */ status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); /* If-Then handling. On GNU/Linux, where this routine is used, we use an undefined instruction as a breakpoint. Unlike BKPT, IT can disable execution of the undefined instruction. So we might miss the breakpoint if we set it on a skipped conditional instruction. Because conditional instructions can change the flags, affecting the execution of further instructions, we may need to set two breakpoints. */ if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL) { if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) { /* An IT instruction. Because this instruction does not modify the flags, we can accurately predict the next executed instruction. */ itstate = inst1 & 0x00ff; pc += thumb_insn_size (inst1); while (itstate != 0 && ! condition_true (itstate >> 4, status)) { inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); pc += thumb_insn_size (inst1); itstate = thumb_advance_itstate (itstate); } return MAKE_THUMB_ADDR (pc); } else if (itstate != 0) { /* We are in a conditional block. Check the condition. */ if (! condition_true (itstate >> 4, status)) { /* Advance to the next executed instruction. */ pc += thumb_insn_size (inst1); itstate = thumb_advance_itstate (itstate); while (itstate != 0 && ! condition_true (itstate >> 4, status)) { inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); pc += thumb_insn_size (inst1); itstate = thumb_advance_itstate (itstate); } return MAKE_THUMB_ADDR (pc); } else if ((itstate & 0x0f) == 0x08) { /* This is the last instruction of the conditional block, and it is executed. We can handle it normally because the following instruction is not conditional, and we must handle it normally because it is permitted to branch. Fall through. */ } else { int cond_negated; /* There are conditional instructions after this one. If this instruction modifies the flags, then we can not predict what the next executed instruction will be. Fortunately, this instruction is architecturally forbidden to branch; we know it will fall through. Start by skipping past it. */ pc += thumb_insn_size (inst1); itstate = thumb_advance_itstate (itstate); /* Set a breakpoint on the following instruction. */ gdb_assert ((itstate & 0x0f) != 0); if (insert_bkpt) insert_single_step_breakpoint (gdbarch, aspace, pc); cond_negated = (itstate >> 4) & 1; /* Skip all following instructions with the same condition. If there is a later instruction in the IT block with the opposite condition, set the other breakpoint there. If not, then set a breakpoint on the instruction after the IT block. */ do { inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); pc += thumb_insn_size (inst1); itstate = thumb_advance_itstate (itstate); } while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated); return MAKE_THUMB_ADDR (pc); } } } else if (itstate & 0x0f) { /* We are in a conditional block. Check the condition. */ int cond = itstate >> 4; if (! condition_true (cond, status)) { /* Advance to the next instruction. All the 32-bit instructions share a common prefix. */ if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) return MAKE_THUMB_ADDR (pc + 4); else return MAKE_THUMB_ADDR (pc + 2); } /* Otherwise, handle the instruction normally. */ } if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ { CORE_ADDR sp; /* Fetch the saved PC from the stack. It's stored above all of the other registers. */ offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); } else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ { unsigned long cond = bits (inst1, 8, 11); if (cond == 0x0f) /* 0x0f = SWI */ { struct gdbarch_tdep *tdep; tdep = gdbarch_tdep (gdbarch); if (tdep->syscall_next_pc != NULL) nextpc = tdep->syscall_next_pc (frame); } else if (cond != 0x0f && condition_true (cond, status)) nextpc = pc_val + (sbits (inst1, 0, 7) << 1); } else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ { nextpc = pc_val + (sbits (inst1, 0, 10) << 1); } else if ((inst1 & 0xe000) == 0xe000) /* 32-bit instruction */ { unsigned short inst2; inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); /* Default to the next instruction. */ nextpc = pc + 4; nextpc = MAKE_THUMB_ADDR (nextpc); if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) { /* Branches and miscellaneous control instructions. */ if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) { /* B, BL, BLX. */ int j1, j2, imm1, imm2; imm1 = sbits (inst1, 0, 10); imm2 = bits (inst2, 0, 10); j1 = bit (inst2, 13); j2 = bit (inst2, 11); offset = ((imm1 << 12) + (imm2 << 1)); offset ^= ((!j2) << 22) | ((!j1) << 23); nextpc = pc_val + offset; /* For BLX make sure to clear the low bits. */ if (bit (inst2, 12) == 0) nextpc = nextpc & 0xfffffffc; } else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) { /* SUBS PC, LR, #imm8. */ nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM); nextpc -= inst2 & 0x00ff; } else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) { /* Conditional branch. */ if (condition_true (bits (inst1, 6, 9), status)) { int sign, j1, j2, imm1, imm2; sign = sbits (inst1, 10, 10); imm1 = bits (inst1, 0, 5); imm2 = bits (inst2, 0, 10); j1 = bit (inst2, 13); j2 = bit (inst2, 11); offset = (sign << 20) + (j2 << 19) + (j1 << 18); offset += (imm1 << 12) + (imm2 << 1); nextpc = pc_val + offset; } } } else if ((inst1 & 0xfe50) == 0xe810) { /* Load multiple or RFE. */ int rn, offset, load_pc = 1; rn = bits (inst1, 0, 3); if (bit (inst1, 7) && !bit (inst1, 8)) { /* LDMIA or POP */ if (!bit (inst2, 15)) load_pc = 0; offset = bitcount (inst2) * 4 - 4; } else if (!bit (inst1, 7) && bit (inst1, 8)) { /* LDMDB */ if (!bit (inst2, 15)) load_pc = 0; offset = -4; } else if (bit (inst1, 7) && bit (inst1, 8)) { /* RFEIA */ offset = 0; } else if (!bit (inst1, 7) && !bit (inst1, 8)) { /* RFEDB */ offset = -8; } else load_pc = 0; if (load_pc) { CORE_ADDR addr = get_frame_register_unsigned (frame, rn); nextpc = get_frame_memory_unsigned (frame, addr + offset, 4); } } else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) { /* MOV PC or MOVS PC. */ nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); nextpc = MAKE_THUMB_ADDR (nextpc); } else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) { /* LDR PC. */ CORE_ADDR base; int rn, load_pc = 1; rn = bits (inst1, 0, 3); base = get_frame_register_unsigned (frame, rn); if (rn == 15) { base = (base + 4) & ~(CORE_ADDR) 0x3; if (bit (inst1, 7)) base += bits (inst2, 0, 11); else base -= bits (inst2, 0, 11); } else if (bit (inst1, 7)) base += bits (inst2, 0, 11); else if (bit (inst2, 11)) { if (bit (inst2, 10)) { if (bit (inst2, 9)) base += bits (inst2, 0, 7); else base -= bits (inst2, 0, 7); } } else if ((inst2 & 0x0fc0) == 0x0000) { int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3); base += get_frame_register_unsigned (frame, rm) << shift; } else /* Reserved. */ load_pc = 0; if (load_pc) nextpc = get_frame_memory_unsigned (frame, base, 4); } else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) { /* TBB. */ CORE_ADDR tbl_reg, table, offset, length; tbl_reg = bits (inst1, 0, 3); if (tbl_reg == 0x0f) table = pc + 4; /* Regcache copy of PC isn't right yet. */ else table = get_frame_register_unsigned (frame, tbl_reg); offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); length = 2 * get_frame_memory_unsigned (frame, table + offset, 1); nextpc = pc_val + length; } else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010) { /* TBH. */ CORE_ADDR tbl_reg, table, offset, length; tbl_reg = bits (inst1, 0, 3); if (tbl_reg == 0x0f) table = pc + 4; /* Regcache copy of PC isn't right yet. */ else table = get_frame_register_unsigned (frame, tbl_reg); offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3)); length = 2 * get_frame_memory_unsigned (frame, table + offset, 2); nextpc = pc_val + length; } } else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ { if (bits (inst1, 3, 6) == 0x0f) nextpc = pc_val; else nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); } else if ((inst1 & 0xf500) == 0xb100) { /* CBNZ or CBZ. */ int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1); ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2)); if (bit (inst1, 11) && reg != 0) nextpc = pc_val + imm; else if (!bit (inst1, 11) && reg == 0) nextpc = pc_val + imm; } return nextpc; } /* Get the raw next address. PC is the current program counter, in FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on the alternative next instruction if there are two options. The value returned has the execution state of the next instruction encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory address. */ static CORE_ADDR arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt) { struct gdbarch *gdbarch = get_frame_arch (frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned long pc_val; unsigned long this_instr; unsigned long status; CORE_ADDR nextpc; if (arm_frame_is_thumb (frame)) return thumb_get_next_pc_raw (frame, pc, insert_bkpt); pc_val = (unsigned long) pc; this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ if (bits (this_instr, 28, 31) == INST_NV) switch (bits (this_instr, 24, 27)) { case 0xa: case 0xb: { /* Branch with Link and change to Thumb. */ nextpc = BranchDest (pc, this_instr); nextpc |= bit (this_instr, 24) << 1; nextpc = MAKE_THUMB_ADDR (nextpc); break; } case 0xc: case 0xd: case 0xe: /* Coprocessor register transfer. */ if (bits (this_instr, 12, 15) == 15) error (_("Invalid update to pc in instruction")); break; } else if (condition_true (bits (this_instr, 28, 31), status)) { switch (bits (this_instr, 24, 27)) { case 0x0: case 0x1: /* data processing */ case 0x2: case 0x3: { unsigned long operand1, operand2, result = 0; unsigned long rn; int c; if (bits (this_instr, 12, 15) != 15) break; if (bits (this_instr, 22, 25) == 0 && bits (this_instr, 4, 7) == 9) /* multiply */ error (_("Invalid update to pc in instruction")); /* BX , BLX */ if (bits (this_instr, 4, 27) == 0x12fff1 || bits (this_instr, 4, 27) == 0x12fff3) { rn = bits (this_instr, 0, 3); nextpc = (rn == 15) ? pc_val + 8 : get_frame_register_unsigned (frame, rn); return nextpc; } /* Multiply into PC */ c = (status & FLAG_C) ? 1 : 0; rn = bits (this_instr, 16, 19); operand1 = (rn == 15) ? pc_val + 8 : get_frame_register_unsigned (frame, rn); if (bit (this_instr, 25)) { unsigned long immval = bits (this_instr, 0, 7); unsigned long rotate = 2 * bits (this_instr, 8, 11); operand2 = ((immval >> rotate) | (immval << (32 - rotate))) & 0xffffffff; } else /* operand 2 is a shifted register */ operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); switch (bits (this_instr, 21, 24)) { case 0x0: /*and */ result = operand1 & operand2; break; case 0x1: /*eor */ result = operand1 ^ operand2; break; case 0x2: /*sub */ result = operand1 - operand2; break; case 0x3: /*rsb */ result = operand2 - operand1; break; case 0x4: /*add */ result = operand1 + operand2; break; case 0x5: /*adc */ result = operand1 + operand2 + c; break; case 0x6: /*sbc */ result = operand1 - operand2 + c; break; case 0x7: /*rsc */ result = operand2 - operand1 + c; break; case 0x8: case 0x9: case 0xa: case 0xb: /* tst, teq, cmp, cmn */ result = (unsigned long) nextpc; break; case 0xc: /*orr */ result = operand1 | operand2; break; case 0xd: /*mov */ /* Always step into a function. */ result = operand2; break; case 0xe: /*bic */ result = operand1 & ~operand2; break; case 0xf: /*mvn */ result = ~operand2; break; } /* In 26-bit APCS the bottom two bits of the result are ignored, and we always end up in ARM state. */ if (!arm_apcs_32) nextpc = arm_addr_bits_remove (gdbarch, result); else nextpc = result; break; } case 0x4: case 0x5: /* data transfer */ case 0x6: case 0x7: if (bit (this_instr, 20)) { /* load */ if (bits (this_instr, 12, 15) == 15) { /* rd == pc */ unsigned long rn; unsigned long base; if (bit (this_instr, 22)) error (_("Invalid update to pc in instruction")); /* byte write to PC */ rn = bits (this_instr, 16, 19); base = (rn == 15) ? pc_val + 8 : get_frame_register_unsigned (frame, rn); if (bit (this_instr, 24)) { /* pre-indexed */ int c = (status & FLAG_C) ? 1 : 0; unsigned long offset = (bit (this_instr, 25) ? shifted_reg_val (frame, this_instr, c, pc_val, status) : bits (this_instr, 0, 11)); if (bit (this_instr, 23)) base += offset; else base -= offset; } nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, 4, byte_order); } } break; case 0x8: case 0x9: /* block transfer */ if (bit (this_instr, 20)) { /* LDM */ if (bit (this_instr, 15)) { /* loading pc */ int offset = 0; if (bit (this_instr, 23)) { /* up */ unsigned long reglist = bits (this_instr, 0, 14); offset = bitcount (reglist) * 4; if (bit (this_instr, 24)) /* pre */ offset += 4; } else if (bit (this_instr, 24)) offset = -4; { unsigned long rn_val = get_frame_register_unsigned (frame, bits (this_instr, 16, 19)); nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val + offset), 4, byte_order); } } } break; case 0xb: /* branch & link */ case 0xa: /* branch */ { nextpc = BranchDest (pc, this_instr); break; } case 0xc: case 0xd: case 0xe: /* coproc ops */ break; case 0xf: /* SWI */ { struct gdbarch_tdep *tdep; tdep = gdbarch_tdep (gdbarch); if (tdep->syscall_next_pc != NULL) nextpc = tdep->syscall_next_pc (frame); } break; default: fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); return (pc); } } return nextpc; } CORE_ADDR arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) { struct gdbarch *gdbarch = get_frame_arch (frame); CORE_ADDR nextpc = gdbarch_addr_bits_remove (gdbarch, arm_get_next_pc_raw (frame, pc, TRUE)); if (nextpc == pc) error (_("Infinite loop detected")); return nextpc; } /* single_step() is called just before we want to resume the inferior, if we want to single-step it but there is no hardware or kernel single-step support. We find the target of the coming instruction and breakpoint it. */ int arm_software_single_step (struct frame_info *frame) { struct gdbarch *gdbarch = get_frame_arch (frame); struct address_space *aspace = get_frame_address_space (frame); /* NOTE: This may insert the wrong breakpoint instruction when single-stepping over a mode-changing instruction, if the CPSR heuristics are used. */ CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); insert_single_step_breakpoint (gdbarch, aspace, next_pc); return 1; } /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand the buffer to be NEW_LEN bytes ending at ENDADDR. Return NULL if an error occurs. BUF is freed. */ static gdb_byte * extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, int old_len, int new_len) { gdb_byte *new_buf, *middle; int bytes_to_read = new_len - old_len; new_buf = xmalloc (new_len); memcpy (new_buf + bytes_to_read, buf, old_len); xfree (buf); if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0) { xfree (new_buf); return NULL; } return new_buf; } /* An IT block is at most the 2-byte IT instruction followed by four 4-byte instructions. The furthest back we must search to find an IT block that affects the current instruction is thus 2 + 3 * 4 == 14 bytes. */ #define MAX_IT_BLOCK_PREFIX 14 /* Use a quick scan if there are more than this many bytes of code. */ #define IT_SCAN_THRESHOLD 32 /* Adjust a breakpoint's address to move breakpoints out of IT blocks. A breakpoint in an IT block may not be hit, depending on the condition flags. */ static CORE_ADDR arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) { gdb_byte *buf; char map_type; CORE_ADDR boundary, func_start; int buf_len, buf2_len; enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); int i, any, last_it, last_it_count; /* If we are using BKPT breakpoints, none of this is necessary. */ if (gdbarch_tdep (gdbarch)->thumb2_breakpoint == NULL) return bpaddr; /* ARM mode does not have this problem. */ if (!arm_pc_is_thumb (gdbarch, bpaddr)) return bpaddr; /* We are setting a breakpoint in Thumb code that could potentially contain an IT block. The first step is to find how much Thumb code there is; we do not need to read outside of known Thumb sequences. */ map_type = arm_find_mapping_symbol (bpaddr, &boundary); if (map_type == 0) /* Thumb-2 code must have mapping symbols to have a chance. */ return bpaddr; bpaddr = gdbarch_addr_bits_remove (gdbarch, bpaddr); if (find_pc_partial_function (bpaddr, NULL, &func_start, NULL) && func_start > boundary) boundary = func_start; /* Search for a candidate IT instruction. We have to do some fancy footwork to distinguish a real IT instruction from the second half of a 32-bit instruction, but there is no need for that if there's no candidate. */ buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX); if (buf_len == 0) /* No room for an IT instruction. */ return bpaddr; buf = xmalloc (buf_len); if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0) return bpaddr; any = 0; for (i = 0; i < buf_len; i += 2) { unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) { any = 1; break; } } if (any == 0) { xfree (buf); return bpaddr; } /* OK, the code bytes before this instruction contain at least one halfword which resembles an IT instruction. We know that it's Thumb code, but there are still two possibilities. Either the halfword really is an IT instruction, or it is the second half of a 32-bit Thumb instruction. The only way we can tell is to scan forwards from a known instruction boundary. */ if (bpaddr - boundary > IT_SCAN_THRESHOLD) { int definite; /* There's a lot of code before this instruction. Start with an optimistic search; it's easy to recognize halfwords that can not be the start of a 32-bit instruction, and use that to lock on to the instruction boundaries. */ buf = extend_buffer_earlier (buf, bpaddr, buf_len, IT_SCAN_THRESHOLD); if (buf == NULL) return bpaddr; buf_len = IT_SCAN_THRESHOLD; definite = 0; for (i = 0; i < buf_len - sizeof (buf) && ! definite; i += 2) { unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); if (thumb_insn_size (inst1) == 2) { definite = 1; break; } } /* At this point, if DEFINITE, BUF[I] is the first place we are sure that we know the instruction boundaries, and it is far enough from BPADDR that we could not miss an IT instruction affecting BPADDR. If ! DEFINITE, give up - start from a known boundary. */ if (! definite) { buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); if (buf == NULL) return bpaddr; buf_len = bpaddr - boundary; i = 0; } } else { buf = extend_buffer_earlier (buf, bpaddr, buf_len, bpaddr - boundary); if (buf == NULL) return bpaddr; buf_len = bpaddr - boundary; i = 0; } /* Scan forwards. Find the last IT instruction before BPADDR. */ last_it = -1; last_it_count = 0; while (i < buf_len) { unsigned short inst1 = extract_unsigned_integer (&buf[i], 2, order); last_it_count--; if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) { last_it = i; if (inst1 & 0x0001) last_it_count = 4; else if (inst1 & 0x0002) last_it_count = 3; else if (inst1 & 0x0004) last_it_count = 2; else last_it_count = 1; } i += thumb_insn_size (inst1); } xfree (buf); if (last_it == -1) /* There wasn't really an IT instruction after all. */ return bpaddr; if (last_it_count < 1) /* It was too far away. */ return bpaddr; /* This really is a trouble spot. Move the breakpoint to the IT instruction. */ return bpaddr - buf_len + last_it; } /* ARM displaced stepping support. Generally ARM displaced stepping works as follows: 1. When an instruction is to be single-stepped, it is first decoded by arm_process_displaced_insn (called from arm_displaced_step_copy_insn). Depending on the type of instruction, it is then copied to a scratch location, possibly in a modified form. The copy_* set of functions performs such modification, as necessary. A breakpoint is placed after the modified instruction in the scratch space to return control to GDB. Note in particular that instructions which modify the PC will no longer do so after modification. 2. The instruction is single-stepped, by setting the PC to the scratch location address, and resuming. Control returns to GDB when the breakpoint is hit. 3. A cleanup function (cleanup_*) is called corresponding to the copy_* function used for the current instruction. This function's job is to put the CPU/memory state back to what it would have been if the instruction had been executed unmodified in its original location. */ /* NOP instruction (mov r0, r0). */ #define ARM_NOP 0xe1a00000 /* Helper for register reads for displaced stepping. In particular, this returns the PC as it would be seen by the instruction at its original location. */ ULONGEST displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno) { ULONGEST ret; if (regno == 15) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n", (unsigned long) from + 8); return (ULONGEST) from + 8; /* Pipeline offset. */ } else { regcache_cooked_read_unsigned (regs, regno, &ret); if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n", regno, (unsigned long) ret); return ret; } } static int displaced_in_arm_mode (struct regcache *regs) { ULONGEST ps; ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs)); regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); return (ps & t_bit) == 0; } /* Write to the PC as from a branch instruction. */ static void branch_write_pc (struct regcache *regs, ULONGEST val) { if (displaced_in_arm_mode (regs)) /* Note: If bits 0/1 are set, this branch would be unpredictable for architecture versions < 6. */ regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3); else regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1); } /* Write to the PC as from a branch-exchange instruction. */ static void bx_write_pc (struct regcache *regs, ULONGEST val) { ULONGEST ps; ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs)); regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); if ((val & 1) == 1) { regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | t_bit); regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); } else if ((val & 2) == 0) { regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); } else { /* Unpredictable behaviour. Try to do something sensible (switch to ARM mode, align dest to 4 bytes). */ warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); } } /* Write to the PC as if from a load instruction. */ static void load_write_pc (struct regcache *regs, ULONGEST val) { if (DISPLACED_STEPPING_ARCH_VERSION >= 5) bx_write_pc (regs, val); else branch_write_pc (regs, val); } /* Write to the PC as if from an ALU instruction. */ static void alu_write_pc (struct regcache *regs, ULONGEST val) { if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && displaced_in_arm_mode (regs)) bx_write_pc (regs, val); else branch_write_pc (regs, val); } /* Helper for writing to registers for displaced stepping. Writing to the PC has a varying effects depending on the instruction which does the write: this is controlled by the WRITE_PC argument. */ void displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc) { if (regno == 15) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", (unsigned long) val); switch (write_pc) { case BRANCH_WRITE_PC: branch_write_pc (regs, val); break; case BX_WRITE_PC: bx_write_pc (regs, val); break; case LOAD_WRITE_PC: load_write_pc (regs, val); break; case ALU_WRITE_PC: alu_write_pc (regs, val); break; case CANNOT_WRITE_PC: warning (_("Instruction wrote to PC in an unexpected way when " "single-stepping")); break; default: internal_error (__FILE__, __LINE__, _("Invalid argument to displaced_write_reg")); } dsc->wrote_to_pc = 1; } else { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n", regno, (unsigned long) val); regcache_cooked_write_unsigned (regs, regno, val); } } /* This function is used to concisely determine if an instruction INSN references PC. Register fields of interest in INSN should have the corresponding fields of BITMASK set to 0b1111. The function returns return 1 if any of these fields in INSN reference the PC (also 0b1111, r15), else it returns 0. */ static int insn_references_pc (uint32_t insn, uint32_t bitmask) { uint32_t lowbit = 1; while (bitmask != 0) { uint32_t mask; for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) ; if (!lowbit) break; mask = lowbit * 0xf; if ((insn & mask) == mask) return 1; bitmask &= ~mask; } return 0; } /* The simplest copy function. Many instructions have the same effect no matter what address they are executed at: in those cases, use this. */ static int copy_unmodified (struct gdbarch *gdbarch, uint32_t insn, const char *iname, struct displaced_step_closure *dsc) { if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " "opcode/class '%s' unmodified\n", (unsigned long) insn, iname); dsc->modinsn[0] = insn; return 0; } /* Preload instructions with immediate offset. */ static void cleanup_preload (struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc) { displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); if (!dsc->u.preload.immed) displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); } static int copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int rn = bits (insn, 16, 19); ULONGEST rn_val; CORE_ADDR from = dsc->insn_addr; if (!insn_references_pc (insn, 0x000f0000ul)) return copy_unmodified (gdbarch, insn, "preload", dsc); if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", (unsigned long) insn); /* Preload instructions: {pli/pld} [rn, #+/-imm] -> {pli/pld} [r0, #+/-imm]. */ dsc->tmp[0] = displaced_read_reg (regs, from, 0); rn_val = displaced_read_reg (regs, from, rn); displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); dsc->u.preload.immed = 1; dsc->modinsn[0] = insn & 0xfff0ffff; dsc->cleanup = &cleanup_preload; return 0; } /* Preload instructions with register offset. */ static int copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int rn = bits (insn, 16, 19); unsigned int rm = bits (insn, 0, 3); ULONGEST rn_val, rm_val; CORE_ADDR from = dsc->insn_addr; if (!insn_references_pc (insn, 0x000f000ful)) return copy_unmodified (gdbarch, insn, "preload reg", dsc); if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", (unsigned long) insn); /* Preload register-offset instructions: {pli/pld} [rn, rm {, shift}] -> {pli/pld} [r0, r1 {, shift}]. */ dsc->tmp[0] = displaced_read_reg (regs, from, 0); dsc->tmp[1] = displaced_read_reg (regs, from, 1); rn_val = displaced_read_reg (regs, from, rn); rm_val = displaced_read_reg (regs, from, rm); displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); dsc->u.preload.immed = 0; dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; dsc->cleanup = &cleanup_preload; return 0; } /* Copy/cleanup coprocessor load and store instructions. */ static void cleanup_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc) { ULONGEST rn_val = displaced_read_reg (regs, dsc->insn_addr, 0); displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); if (dsc->u.ldst.writeback) displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); } static int copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int rn = bits (insn, 16, 19); ULONGEST rn_val; CORE_ADDR from = dsc->insn_addr; if (!insn_references_pc (insn, 0x000f0000ul)) return copy_unmodified (gdbarch, insn, "copro load/store", dsc); if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " "load/store insn %.8lx\n", (unsigned long) insn); /* Coprocessor load/store instructions: {stc/stc2} [, #+/-imm] (and other immediate addressing modes) -> {stc/stc2} [r0, #+/-imm]. ldc/ldc2 are handled identically. */ dsc->tmp[0] = displaced_read_reg (regs, from, 0); rn_val = displaced_read_reg (regs, from, rn); displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); dsc->u.ldst.writeback = bit (insn, 25); dsc->u.ldst.rn = rn; dsc->modinsn[0] = insn & 0xfff0ffff; dsc->cleanup = &cleanup_copro_load_store; return 0; } /* Clean up branch instructions (actually perform the branch, by setting PC). */ static void cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs, struct displaced_step_closure *dsc) { ULONGEST from = dsc->insn_addr; uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); int branch_taken = condition_true (dsc->u.branch.cond, status); enum pc_write_style write_pc = dsc->u.branch.exchange ? BX_WRITE_PC : BRANCH_WRITE_PC; if (!branch_taken) return; if (dsc->u.branch.link) { ULONGEST pc = displaced_read_reg (regs, from, 15); displaced_write_reg (regs, dsc, 14, pc - 4, CANNOT_WRITE_PC); } displaced_write_reg (regs, dsc, 15, dsc->u.branch.dest, write_pc); } /* Copy B/BL/BLX instructions with immediate destinations. */ static int copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int cond = bits (insn, 28, 31); int exchange = (cond == 0xf); int link = exchange || bit (insn, 24); CORE_ADDR from = dsc->insn_addr; long offset; if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn " "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b", (unsigned long) insn); /* Implement "BL