From fbd93201df80d4028b0e4762e701b20f96cff8bb Mon Sep 17 00:00:00 2001 From: Dave Brolley Date: Tue, 9 Sep 2003 22:34:53 +0000 Subject: 2003-09-09 Dave Brolley * sim/frv/maddaccs.cgs: move to fr400 subdirectory. * sim/frv/msubaccs.cgs: move to fr400 subdirectory. * sim/frv/masaccs.cgs: move to fr400 subdirectory. --- sim/testsuite/ChangeLog | 6 ++ sim/testsuite/lib/sim-defs.exp | 8 +- sim/testsuite/sim/frv/fr400/maddaccs.cgs | 131 +++++++++++++++++++++++++++ sim/testsuite/sim/frv/fr400/masaccs.cgs | 151 +++++++++++++++++++++++++++++++ sim/testsuite/sim/frv/fr400/msubaccs.cgs | 131 +++++++++++++++++++++++++++ sim/testsuite/sim/frv/maddaccs.cgs | 131 --------------------------- sim/testsuite/sim/frv/masaccs.cgs | 151 ------------------------------- sim/testsuite/sim/frv/msubaccs.cgs | 131 --------------------------- 8 files changed, 423 insertions(+), 417 deletions(-) create mode 100644 sim/testsuite/sim/frv/fr400/maddaccs.cgs create mode 100644 sim/testsuite/sim/frv/fr400/masaccs.cgs create mode 100644 sim/testsuite/sim/frv/fr400/msubaccs.cgs delete mode 100644 sim/testsuite/sim/frv/maddaccs.cgs delete mode 100644 sim/testsuite/sim/frv/masaccs.cgs delete mode 100644 sim/testsuite/sim/frv/msubaccs.cgs (limited to 'sim') diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index 423cffd..56b16f3 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2003-09-09 Dave Brolley + + * sim/frv/maddaccs.cgs: move to fr400 subdirectory. + * sim/frv/msubaccs.cgs: move to fr400 subdirectory. + * sim/frv/masaccs.cgs: move to fr400 subdirectory. + 2003-09-03 Michael Snyder * sim/frv/fr500/mclracc.cgs: Change mach to 'all', to be diff --git a/sim/testsuite/lib/sim-defs.exp b/sim/testsuite/lib/sim-defs.exp index 42374e0..017fcef 100644 --- a/sim/testsuite/lib/sim-defs.exp +++ b/sim/testsuite/lib/sim-defs.exp @@ -331,20 +331,20 @@ proc slurp_options { file } { # whitespace is ignored anywhere except within the options list; # option names are alphabetic only set pat "^#${ws}(\[a-zA-Z\]*)\\(?(\[^):\]*)\\)?$ws:${ws}(.*)$ws\$" - # Allow comment as first line of file. - set firstline 1 + # Allow arbitrary lines until the first option is seen. + set seen_opt 0 while { [gets $f line] != -1 } { set line [string trim $line] # Whitespace here is space-tab. if [regexp $pat $line xxx opt_name opt_machs opt_val] { # match! lappend opt_array [list $opt_name $opt_machs $opt_val] + set seen_opt 1 } else { - if { ! $firstline } { + if { $seen_opt } { break } } - set firstline 0 } close $f return $opt_array diff --git a/sim/testsuite/sim/frv/fr400/maddaccs.cgs b/sim/testsuite/sim/frv/fr400/maddaccs.cgs new file mode 100644 index 0000000..98659c4 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/maddaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for maddaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global maddaccs +maddaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdead,0xbeef,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xbeef,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x2345,0x6789,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5677,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + maddaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + maddaccs.p acc0,acc1 + maddaccs acc2,acc3 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0002,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/masaccs.cgs b/sim/testsuite/sim/frv/fr400/masaccs.cgs new file mode 100644 index 0000000..8fbde91 --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/masaccs.cgs @@ -0,0 +1,151 @@ +# frv testcase for masaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global masaccs +masaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xdead,0xbeef,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0xbeef,0xdead,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x2345,0x6789,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 1,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg2 + test_acc_limmed 0x1234,0x5677,acc2 + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffe7ffe,acc0 + set_accg_immed 0x0,accg1 + set_acc_immed 0x00020001,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xfffc,0x7ffd,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + masaccs acc0,acc2 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg2 + test_acc_limmed 0x0000,0x0000,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0003,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x7f,accg3 + set_acc_immed 0xffffffff,acc3 + masaccs.p acc0,acc0 + masaccs acc2,acc2 + test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg0 + test_acc_limmed 0x0000,0x0002,acc0 + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg2 + test_acc_limmed 0xffff,0xffff,acc2 + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0002,acc3 + + pass diff --git a/sim/testsuite/sim/frv/fr400/msubaccs.cgs b/sim/testsuite/sim/frv/fr400/msubaccs.cgs new file mode 100644 index 0000000..f0aba1d --- /dev/null +++ b/sim/testsuite/sim/frv/fr400/msubaccs.cgs @@ -0,0 +1,131 @@ +# frv testcase for msubaccs $ACC40Si,$ACC40Sk +# mach: fr400 + + .include "../testutils.inc" + + start + + .global msubaccs +msubaccs: + set_accg_immed 0,accg0 + set_acc_immed 0x00000000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0xdead0000,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x0000beef,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0xdeac,0x4111,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x0000dead,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xbeef0000,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x4111,0xdead,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x11111111,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x0123,0x4567,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0xff,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_accg_immed 0,accg0 + set_acc_immed 0x12345678,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xffffffff,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 1,0,0,msr0 ; msr0.aovf not set + test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set + test_accg_immed 0,accg3 + test_acc_limmed 0x1234,0x5679,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x7f,accg0 + set_acc_immed 0xfffffffe,acc0 + set_accg_immed 0xff,accg1 + set_acc_immed 0xfffffffe,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + set_spr_immed 0,msr0 + set_accg_immed 0x80,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000002,acc1 + msubaccs acc0,acc3 + test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set + test_spr_bits 2,1,1,msr0 ; msr0.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0x80,accg3 + test_acc_limmed 0x0000,0x0000,acc3 + + set_spr_immed 0,msr0 + set_spr_immed 0,msr1 + set_accg_immed 0,accg0 + set_acc_immed 0x00000001,acc0 + set_accg_immed 0,accg1 + set_acc_immed 0x00000001,acc1 + set_accg_immed 0,accg2 + set_acc_immed 0x00000001,acc2 + set_accg_immed 0x80,accg3 + set_acc_immed 0x00000000,acc3 + msubaccs.p acc0,acc1 + msubaccs acc2,acc3 + test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear + test_spr_bits 2,1,0,msr0 ; msr0.ovf not set + test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set + test_spr_bits 2,1,1,msr1 ; msr1.ovf set + test_spr_bits 1,0,1,msr0 ; msr0.aovf set + test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set + test_accg_immed 0,accg1 + test_acc_limmed 0x0000,0x0000,acc1 + test_accg_immed 0x7f,accg3 + test_acc_limmed 0xffff,0xffff,acc3 + + pass diff --git a/sim/testsuite/sim/frv/maddaccs.cgs b/sim/testsuite/sim/frv/maddaccs.cgs deleted file mode 100644 index aa178fe..0000000 --- a/sim/testsuite/sim/frv/maddaccs.cgs +++ /dev/null @@ -1,131 +0,0 @@ -# frv testcase for maddaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global maddaccs -maddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xbeef,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - maddaccs.p acc0,acc1 - maddaccs acc2,acc3 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/masaccs.cgs b/sim/testsuite/sim/frv/masaccs.cgs deleted file mode 100644 index 7369a71..0000000 --- a/sim/testsuite/sim/frv/masaccs.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for masaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global masaccs -masaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xfffc,0x7ffd,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - masaccs.p acc0,acc0 - masaccs acc2,acc2 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/msubaccs.cgs b/sim/testsuite/sim/frv/msubaccs.cgs deleted file mode 100644 index f793e9a..0000000 --- a/sim/testsuite/sim/frv/msubaccs.cgs +++ /dev/null @@ -1,131 +0,0 @@ -# frv testcase for msubaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global msubaccs -msubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000002,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - msubaccs.p acc0,acc1 - msubaccs acc2,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass -- cgit v1.1