From c10ae9ad33b261235bc7b63b89a3bb6d0ca7a291 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Tue, 9 Dec 1997 05:46:48 +0000 Subject: Test/fix d10v RTE instruction. --- sim/testsuite/d10v-elf/.Sanitize | 1 + sim/testsuite/d10v-elf/t-rte.s | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 sim/testsuite/d10v-elf/t-rte.s (limited to 'sim') diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize index dcdaad8..25ed0ae 100644 --- a/sim/testsuite/d10v-elf/.Sanitize +++ b/sim/testsuite/d10v-elf/.Sanitize @@ -15,6 +15,7 @@ t-msbu.s t-rac.s t-rachi.s t-rep.s +t-rte.s t-mulxu.s t-sub.s t-subi.s diff --git a/sim/testsuite/d10v-elf/t-rte.s b/sim/testsuite/d10v-elf/t-rte.s new file mode 100644 index 0000000..5ce31dd --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rte.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, bpc + ldi r6, #PSW_BITS + mvtc r6, bpsw + +test_rte: + RTE + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 -- cgit v1.1