From 96baa820df8126165bd3c4a33c561556b21203af Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Mon, 9 Aug 1999 21:36:23 +0000 Subject: import gdb-1999-08-09 snapshot --- sim/common/ChangeLog | 32 + sim/common/cgen-cpu.h | 4 +- sim/common/cgen-defs.h | 9 + sim/common/cgen-engine.h | 132 +- sim/common/cgen-scache.c | 7 + sim/common/cgen-scache.h | 8 +- sim/common/genmloop.sh | 303 ++- sim/fr30/ChangeLog | 8 + sim/fr30/cpu.h | 783 +++----- sim/fr30/cpuall.h | 3 + sim/fr30/decode.c | 1339 +++++++------ sim/fr30/decode.h | 224 +-- sim/fr30/model.c | 330 ++-- sim/fr30/sem-switch.c | 404 ++-- sim/fr30/sem.c | 946 +++++---- sim/i960/ChangeLog | 9 + sim/i960/cpu.h | 1883 +++--------------- sim/i960/cpuall.h | 3 + sim/i960/decode.c | 4825 +++++++++++++++++++--------------------------- sim/i960/decode.h | 357 +--- sim/i960/i960-desc.h | 3 + sim/i960/model.c | 1164 +++++------ sim/i960/sem-switch.c | 670 +++---- sim/i960/sem.c | 1590 +++++++++------ sim/m32r/ChangeLog | 9 + sim/m32r/cpu.h | 656 ++----- sim/m32r/cpuall.h | 3 + sim/m32r/decode.c | 1184 ++++++------ sim/m32r/decode.h | 146 +- sim/m32r/model.c | 396 ++-- sim/m32r/sem-switch.c | 240 +-- sim/m32r/sem.c | 584 +++--- 32 files changed, 7891 insertions(+), 10363 deletions(-) (limited to 'sim') diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index bc2bb01..26dcb3c 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,35 @@ +1999-08-08 Doug Evans + + * cgen-engine.h (SEM_FN_NAME,SEMF_FN_NAME): Delete. + (insn_sem): Rewrite. + (sem_fn_desc): New struct. + (idesc): Rewrite. + * genmloop.sh (scache case,@cpu@_scache_lookup): Profile scache hit, + misses if ! FAST_P. + (scache case): Split into non-parallel/parallel versions. + (@cpu@_engine_run_{full,fast}): Call @cpu@_{sem,semf}_init_idesc_table + if not use semantic switch version. + +1999-08-04 Doug Evans + + * cgen-defs.h (SEM_BRANCH_TYPE): New enum. + * cgen-engine.h (SEM_BRANCH_UNTAKEN,SEM_BRANCH_UNCACHEABLE): Delete. + (SEM_BRANCH_INIT_EXTRACT): Delete. + (SEM_BRANCH_INIT): Replace npc_ptr with br_type. + (SEM_BRANCH_FINI): Ditto. + (SEM_BRANCH_VIA_ADDR): Ditto. + (SEM_BRANCH_VIA_CACHE): Ditto. Delete cachvarptr arg. + (SEM_BRANCH_ADDR_CACHE): Delete. + (SEM_SKIP_COMPILE,SEM_SKIP_INSN): New macros. + * cgen-scache.h (cpu_scache): Replace member pbb_pr_npc_ptr with + pbb_br_type. + * genmloop.sh (eng.hin): Update prototype of ${cpu}_pbb_cti_chain. + (@cpu@_pbb_begin): Initialize branch_target. + (@cpu@_pbb_cti_chain): Replace arg new_vpc_ptr with br_type. + (@cpu@_engine_run_full): Replace local pbb_br_npc_ptr with + pbb_br_type. + (@cpu@_engine_run_fast): Ditto. + Fri Jul 16 14:47:53 1999 Dave Brolley * cgen-utils.c (RORSI): New function. diff --git a/sim/common/cgen-cpu.h b/sim/common/cgen-cpu.h index c807182..914fb45 100644 --- a/sim/common/cgen-cpu.h +++ b/sim/common/cgen-cpu.h @@ -63,8 +63,8 @@ typedef struct { IDESC *idesc; #define CPU_IDESC(cpu) ((cpu)->cgen_cpu.idesc) - /* Whether the read,write,semantic entries (computed goto labels) have been - initialized or not. */ + /* Whether the read,write,semantic entries (function pointers or computed + goto labels) have been initialized or not. */ int idesc_read_init_p; #define CPU_IDESC_READ_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_read_init_p) int idesc_write_init_p; diff --git a/sim/common/cgen-defs.h b/sim/common/cgen-defs.h index d3c9a8a..1faa2ee 100644 --- a/sim/common/cgen-defs.h +++ b/sim/common/cgen-defs.h @@ -92,6 +92,15 @@ typedef SCACHE *SEM_PC; #else typedef IADDR SEM_PC; #endif + +/* Kinds of branches. */ +typedef enum { + SEM_BRANCH_UNTAKEN, + /* Branch to an uncacheable address (e.g. j reg). */ + SEM_BRANCH_UNCACHEABLE, + /* Branch to a cacheable (fixed) address. */ + SEM_BRANCH_CACHEABLE +} SEM_BRANCH_TYPE; /* Virtual insn support. */ diff --git a/sim/common/cgen-engine.h b/sim/common/cgen-engine.h index e7d27e0..fbcf3e5 100644 --- a/sim/common/cgen-engine.h +++ b/sim/common/cgen-engine.h @@ -180,11 +180,6 @@ do { \ & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \ != 0) -/* These are used so that we can compile two copies of the semantic code, - one with full feature support and one without that runs fast(er). */ -#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) -#define SEMF_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) - /* Return pointer to ARGBUF given ptr to SCACHE. */ #define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf) @@ -217,22 +212,11 @@ do { \ #define PBB_UPDATE_INSN_COUNT(cpu,sc) \ (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count) -/* Value for br_addr_ptr indicating branch wasn't taken. */ -#define SEM_BRANCH_UNTAKEN ((SEM_PC *) 0) - -/* Value for br_addr_ptr indicating branch was taken to uncacheable - address (e.g. j reg). */ -#define SEM_BRANCH_UNCACHEABLE ((SEM_PC *) 1) - -/* Initialize next-pbb link for SEM_BRANCH_VIA_CACHE. */ -#define SEM_BRANCH_INIT_EXTRACT(abuf) \ -do { (abuf)->fields.cti.addr_cache = 0; } while (0) - /* Do not append a `;' to invocations of this. - npc,npc_ptr are for communication between the cti insn and cti-chain. */ + npc,br_type are for communication between the cti insn and cti-chain. */ #define SEM_BRANCH_INIT \ IADDR npc = 0; /* assign a value for -Wall */ \ - SEM_PC *npc_ptr = SEM_BRANCH_UNTAKEN; + SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN; /* SEM_IN_SWITCH is defined at the top of the mainloop.c files generated by genmloop.sh. It exists so generated semantic code needn't @@ -241,30 +225,36 @@ do { (abuf)->fields.cti.addr_cache = 0; } while (0) #define SEM_BRANCH_FINI(pcvar) \ do { \ pbb_br_npc = npc; \ - pbb_br_npc_ptr = npc_ptr; \ + pbb_br_type = br_type; \ } while (0) #else /* 1 semantic function per instruction */ #define SEM_BRANCH_FINI(pcvar) \ do { \ CPU_PBB_BR_NPC (current_cpu) = npc; \ - CPU_PBB_BR_NPC_PTR (current_cpu) = npc_ptr; \ + CPU_PBB_BR_TYPE (current_cpu) = br_type; \ } while (0) #endif -/* Return address of cached branch address value. */ -#define SEM_BRANCH_ADDR_CACHE(sem_arg) \ - (& SEM_ARGBUF (sem_arg)->fields.cti.addr_cache) - -#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar, cachevarptr) \ +#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \ do { \ npc = (newval); \ - npc_ptr = (cachevarptr); \ + br_type = SEM_BRANCH_CACHEABLE; \ } while (0) #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \ do { \ npc = (newval); \ - npc_ptr = SEM_BRANCH_UNCACHEABLE; \ + br_type = SEM_BRANCH_UNCACHEABLE; \ +} while (0) + +#define SEM_SKIP_COMPILE(cpu, sc, skip) \ +do { \ + SEM_ARGBUF (sc) -> skip_count = (skip); \ +} while (0) + +#define SEM_SKIP_INSN(cpu, sc, vpcvar) \ +do { \ + (vpcvar) += SEM_ARGBUF (sc) -> skip_count; \ } while (0) #else /* ! WITH_SCACHE_PBB */ @@ -273,8 +263,6 @@ do { \ #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len)) -#define SEM_BRANCH_INIT_EXTRACT(abuf) do { } while (0) - /* ??? May wish to move taken_p out of here and make it explicit. */ #define SEM_BRANCH_INIT \ int taken_p = 0; @@ -285,9 +273,7 @@ do { \ #define SEM_BRANCH_FINI(pcvar) \ do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0) -#define SEM_BRANCH_ADDR_CACHE(sem_arg) shouldnt_be_used - -#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar, cachevar) \ +#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \ do { \ (pcvar) = (newval); \ taken_p = 1; \ @@ -314,9 +300,7 @@ do { \ #define SEM_BRANCH_INIT \ int taken_p = 0; -#define SEM_BRANCH_ADDR_CACHE(sem_arg) shouldnt_be_used - -#define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar, cachevar) \ +#define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \ do { \ (pcvar) = (newval); \ taken_p = 1; \ @@ -344,10 +328,12 @@ do { \ /* Instruction information. */ -/* Compile time computable instruction data. +/* Sanity check, at most one of these may be true. */ +#if WITH_PARALLEL_READ && WITH_PARALLEL_WRITE +#error "Both WITH_PARALLEL_READ && WITH_PARALLEL_WRITE can't be true." +#endif - ??? May wish to move parallel execution support into its own struct. - It's a fair bit of "clutter" for the "normal" case. */ +/* Compile time computable instruction data. */ struct insn_sem { /* The instruction type (a number that identifies each insn over the @@ -357,10 +343,8 @@ struct insn_sem { /* Index in IDESC table. */ int index; - /* Sanity check, at most one of these may be true. */ -#if WITH_PARALLEL_READ && WITH_PARALLEL_WRITE -#error "Both WITH_PARALLEL_READ && WITH_PARALLEL_WRITE can't be true." -#endif + /* Semantic format number. */ + int sfmt; #if WITH_PARALLEL_READ || WITH_PARALLEL_WRITE /* Index in IDESC table of parallel handler. */ @@ -368,50 +352,38 @@ struct insn_sem { #endif #if WITH_PARALLEL_READ -#ifndef __GNUC__ - /* Semantic format number of pre-read handler. - Only used by chips that support parallel execution of several insns. - It is always implemented as a `switch'. In the case of GNUC we use - computed gotos. When not GNUC, this is the argument to `switch'. */ - int fmt; -#endif + /* Index in IDESC table of read handler. */ + int read_index; #endif #if WITH_PARALLEL_WRITE - /* Index in IDESC table of writeback handler. - Only used by chips that support parallel execution of several insns. */ + /* Index in IDESC table of writeback handler. */ int write_index; #endif +}; - /* Routines to execute the insn. - The full version has all features (profiling,tracing) compiled in. - The fast version has none of that. */ -#if ! WITH_SEM_SWITCH_FULL - SEMANTIC_FN *sem_full; -#endif -#if WITH_FAST && ! WITH_SEM_SWITCH_FAST - SEMANTIC_FN *sem_fast; -#endif +/* Entry in semantic function table. + This information is copied to the insn descriptor table at run-time. */ + +struct sem_fn_desc { + /* Index in IDESC table. */ + int index; + + /* Function to perform the semantics of the insn. */ + SEMANTIC_FN *fn; }; /* Run-time computed instruction descriptor. */ struct idesc { - /* Parallel read-before-exec support. */ -#if WITH_PARALLEL_READ - struct idesc *par_idesc; +#if WITH_SEM_SWITCH_FAST #ifdef __GNUC__ - void *read; + void *sem_fast_lab; #else - int fmt; -#endif + /* nothing needed, switch's on `num' member */ #endif - - /* Parallel write-after-exec support. */ -#if WITH_PARALLEL_WRITE - /* Pointer to parallel handler if serial insn. - Pointer to writeback handler if parallel insn. */ - struct idesc *par_idesc; +#else + SEMANTIC_FN *sem_fast; #endif #if WITH_SEM_SWITCH_FULL @@ -424,20 +396,20 @@ struct idesc { SEMANTIC_FN *sem_full; #endif -#if WITH_SEM_SWITCH_FAST -#ifdef __GNUC__ - void *sem_fast_lab; -#else - /* nothing needed, switch's on `num' member */ -#endif -#else - SEMANTIC_FN *sem_fast; + /* Parallel support. */ +#if WITH_PARALLEL_READ || WITH_PARALLEL_WRITE + /* Pointer to parallel handler if serial insn. + Pointer to readahead/writeback handler if parallel insn. */ + struct idesc *par_idesc; #endif /* Instruction number (index in IDESC table, profile table). Also used to switch on in non-gcc semantic switches. */ int num; + /* Semantic format id. */ + int sfmt; + /* instruction data (name, attributes, size, etc.) */ const CGEN_INSN *idata; diff --git a/sim/common/cgen-scache.c b/sim/common/cgen-scache.c index c5ea075..890afc8 100644 --- a/sim/common/cgen-scache.c +++ b/sim/common/cgen-scache.c @@ -313,6 +313,8 @@ scache_flush_cpu (SIM_CPU *cpu) SCACHE * scache_lookup (SIM_CPU *cpu, IADDR pc) { + /* FIXME: hash computation is wrong, doesn't take into account + NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); SCACHE_MAP *scm; @@ -343,6 +345,8 @@ scache_lookup (SIM_CPU *cpu, IADDR pc) SCACHE * scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp) { + /* FIXME: hash computation is wrong, doesn't take into account + NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); SCACHE_MAP *scm; @@ -372,6 +376,7 @@ scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp) static int next_free = 0; scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; + /* FIXME: This seems rather clumsy. */ for (i = 0; i < next_free; ++i, ++scm) continue; ++next_free; @@ -381,6 +386,8 @@ scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp) /* At this point SCM points to the hash table entry to use. Now make sure there's room in the cache. */ + /* FIXME: Kinda weird to use a next_free adjusted scm when cache is + flushed. */ { int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); diff --git a/sim/common/cgen-scache.h b/sim/common/cgen-scache.h index 7ca4e65..b7a20de 100644 --- a/sim/common/cgen-scache.h +++ b/sim/common/cgen-scache.h @@ -69,10 +69,10 @@ typedef struct cpu_scache { SCACHE *next_free; #define CPU_SCACHE_NEXT_FREE(cpu) ((cpu) -> cgen_cpu.scache.next_free) - /* Address of cti-chain insn, only used by functional semantics, - not switch form. */ - SCACHE **pbb_br_npc_ptr; -#define CPU_PBB_BR_NPC_PTR(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_npc_ptr) + /* Kind of branch being taken. + Only used by functional semantics, not switch form. */ + SEM_BRANCH_TYPE pbb_br_type; +#define CPU_PBB_BR_TYPE(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_type) /* Target's branch address. */ IADDR pbb_br_npc; #define CPU_PBB_BR_NPC(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_npc) diff --git a/sim/common/genmloop.sh b/sim/common/genmloop.sh index 6720799..8a1b8d6 100644 --- a/sim/common/genmloop.sh +++ b/sim/common/genmloop.sh @@ -238,7 +238,7 @@ if [ x$pbb = xyes ] ; then echo "" echo "extern SEM_PC ${cpu}_pbb_begin (SIM_CPU *, int);" echo "extern SEM_PC ${cpu}_pbb_chain (SIM_CPU *, SEM_ARG);" - echo "extern SEM_PC ${cpu}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_PC *, PCADDR);" + echo "extern SEM_PC ${cpu}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);" echo "extern void ${cpu}_pbb_before (SIM_CPU *, SCACHE *);" echo "extern void ${cpu}_pbb_after (SIM_CPU *, SCACHE *);" fi @@ -372,10 +372,10 @@ fi # Note that this code may declare some locals. ${SHELL} $infile init -if [ x$parallel != xno ] ; then +if [ x$parallel = xread ] ; then cat << EOF -#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__) +#if defined (__GNUC__) { if (! CPU_IDESC_READ_INIT_P (current_cpu)) { @@ -392,17 +392,19 @@ fi cat << EOF -#if WITH_SEM_SWITCH_FULL && defined (__GNUC__) - { - if (! CPU_IDESC_SEM_INIT_P (current_cpu)) - { + if (! CPU_IDESC_SEM_INIT_P (current_cpu)) + { +#if WITH_SEM_SWITCH_FULL +#if defined (__GNUC__) /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */ #define DEFINE_LABELS #include "$switch" - CPU_IDESC_SEM_INIT_P (current_cpu) = 1; - } - } #endif +#else + @cpu@_sem_init_idesc_table (current_cpu); +#endif + CPU_IDESC_SEM_INIT_P (current_cpu) = 1; + } do { @@ -446,9 +448,10 @@ fi # simple engine ########################################################################## -# Scache engine: lookup insn in scache, fetch if missing, then execute it. +# Non-parallel scache engine: lookup insn in scache, fetch if missing, +# then execute it. -if [ x$scache = xyes ] ; then +if [ x$scache = xyes -a x$parallel = xno ] ; then cat << EOF @@ -463,7 +466,7 @@ static INLINE SCACHE * fetch and decode the instruction. */ if (sc->argbuf.addr != vpc) { - if (FAST_P) + if (! FAST_P) PROFILE_COUNT_SCACHE_MISS (current_cpu); /* begin extract-scache */ @@ -474,7 +477,7 @@ ${SHELL} $infile extract-scache cat << EOF /* end extract-scache */ } - else if (FAST_P) + else if (! FAST_P) { PROFILE_COUNT_SCACHE_HIT (current_cpu); /* Make core access statistics come out right. @@ -497,22 +500,182 @@ void EOF -if [ x$parallel != xno ] ; then - cat << EOF - PAREXEC pbufs[MAX_PARALLEL_INSNS]; - PAREXEC *par_exec; +# Any initialization code before looping starts. +# Note that this code may declare some locals. +${SHELL} $infile init + +cat << EOF + + if (! CPU_IDESC_SEM_INIT_P (current_cpu)) + { +#if ! WITH_SEM_SWITCH_FULL + @cpu@_sem_init_idesc_table (current_cpu); +#endif + CPU_IDESC_SEM_INIT_P (current_cpu) = 1; + } + + vpc = GET_H_PC (); + + do + { + SCACHE *sc; + + sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P); + +/* begin full-exec-scache */ +EOF + +${SHELL} $infile full-exec-scache + +cat << EOF +/* end full-exec-scache */ + + SET_H_PC (vpc); + + ++ CPU_INSN_COUNT (current_cpu); + } + while (0 /*CPU_RUNNING_P (current_cpu)*/); +} + +#undef FAST_P + +EOF + +#################################### + +# Non-parallel scache engine: fast version. + +if [ x$fast = xyes ] ; then + + cat << EOF + +#define FAST_P 1 + +void +@cpu@_engine_run_fast (SIM_CPU *current_cpu) +{ + SIM_DESC current_state = CPU_STATE (current_cpu); + SCACHE *scache = CPU_SCACHE_CACHE (current_cpu); + unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu); + SEM_PC vpc; EOF -fi # Any initialization code before looping starts. # Note that this code may declare some locals. ${SHELL} $infile init -if [ x$parallel != xno ] ; then - cat << EOF +cat << EOF -#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__) + if (! CPU_IDESC_SEM_INIT_P (current_cpu)) + { +#if WITH_SEM_SWITCH_FAST +#if defined (__GNUC__) +/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */ +#define DEFINE_LABELS +#include "$switch" +#endif +#else + @cpu@_semf_init_idesc_table (current_cpu); +#endif + CPU_IDESC_SEM_INIT_P (current_cpu) = 1; + } + + vpc = GET_H_PC (); + + do + { + SCACHE *sc; + + sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P); + +/* begin fast-exec-scache */ +EOF + +${SHELL} $infile fast-exec-scache + +cat << EOF +/* end fast-exec-scache */ + + SET_H_PC (vpc); + + ++ CPU_INSN_COUNT (current_cpu); + } + while (0 /*CPU_RUNNING_P (current_cpu)*/); +} + +#undef FAST_P + +EOF + +fi # -fast + +fi # -scache && ! parallel + +########################################################################## + +# Parallel scache engine: lookup insn in scache, fetch if missing, +# then execute it. +# For the parallel case we give the target more flexibility. + +if [ x$scache = xyes -a x$parallel != xno ] ; then + + cat << EOF + +static INLINE SCACHE * +@cpu@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache, + unsigned int hash_mask, int *last_insn_p, int FAST_P) +{ + /* First step: look up current insn in hash table. */ + SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask); + + /* If the entry isn't the one we want (cache miss), + fetch and decode the instruction. */ + if (sc->argbuf.addr != vpc) + { + if (! FAST_P) + PROFILE_COUNT_SCACHE_MISS (current_cpu); + +#define SET_LAST_INSN_P(last_p) do { *last_insn_p = (last_p); } while (0) +/* begin extract-scache */ +EOF + +${SHELL} $infile extract-scache + +cat << EOF +/* end extract-scache */ +#undef SET_LAST_INSN_P + } + else if (! FAST_P) + { + PROFILE_COUNT_SCACHE_HIT (current_cpu); + /* Make core access statistics come out right. + The size is a guess, but it's currently not used either. */ + PROFILE_COUNT_CORE (current_cpu, vpc, 2, exec_map); + } + + return sc; +} + +#define FAST_P 0 + +void +@cpu@_engine_run_full (SIM_CPU *current_cpu) +{ + SIM_DESC current_state = CPU_STATE (current_cpu); + SCACHE *scache = CPU_SCACHE_CACHE (current_cpu); + unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu); + SEM_PC vpc; + +EOF + +# Any initialization code before looping starts. +# Note that this code may declare some locals. +${SHELL} $infile init + +if [ x$parallel = xread ] ; then +cat << EOF +#if defined (__GNUC__) { if (! CPU_IDESC_READ_INIT_P (current_cpu)) { @@ -529,14 +692,18 @@ fi cat << EOF + if (! CPU_IDESC_SEM_INIT_P (current_cpu)) + { +#if ! WITH_SEM_SWITCH_FULL + @cpu@_sem_init_idesc_table (current_cpu); +#endif + CPU_IDESC_SEM_INIT_P (current_cpu) = 1; + } + vpc = GET_H_PC (); do { - SCACHE *sc; - - sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P); - /* begin full-exec-scache */ EOF @@ -544,10 +711,6 @@ ${SHELL} $infile full-exec-scache cat << EOF /* end full-exec-scache */ - - SET_H_PC (vpc); - - ++ CPU_INSN_COUNT (current_cpu); } while (0 /*CPU_RUNNING_P (current_cpu)*/); } @@ -558,7 +721,7 @@ EOF #################################### -# Scache engine: fast version. +# Parallel scache engine: fast version. if [ x$fast = xyes ] ; then @@ -573,25 +736,19 @@ void SCACHE *scache = CPU_SCACHE_CACHE (current_cpu); unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu); SEM_PC vpc; - -EOF - -if [ x$parallel != xno ] ; then - cat << EOF PAREXEC pbufs[MAX_PARALLEL_INSNS]; PAREXEC *par_exec; EOF -fi # Any initialization code before looping starts. # Note that this code may declare some locals. ${SHELL} $infile init -if [ x$parallel != xno ] ; then - cat << EOF +if [ x$parallel = xread ] ; then +cat << EOF -#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__) +#if defined (__GNUC__) { if (! CPU_IDESC_READ_INIT_P (current_cpu)) { @@ -604,30 +761,28 @@ if [ x$parallel != xno ] ; then #endif EOF -fi # parallel != no +fi cat << EOF -#if WITH_SEM_SWITCH_FAST && defined (__GNUC__) - { - if (! CPU_IDESC_SEM_INIT_P (current_cpu)) - { + if (! CPU_IDESC_SEM_INIT_P (current_cpu)) + { +#if WITH_SEM_SWITCH_FAST +#if defined (__GNUC__) /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */ #define DEFINE_LABELS #include "$switch" - CPU_IDESC_SEM_INIT_P (current_cpu) = 1; - } - } #endif +#else + @cpu@_semf_init_idesc_table (current_cpu); +#endif + CPU_IDESC_SEM_INIT_P (current_cpu) = 1; + } vpc = GET_H_PC (); do { - SCACHE *sc; - - sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P); - /* begin fast-exec-scache */ EOF @@ -635,10 +790,6 @@ ${SHELL} $infile fast-exec-scache cat << EOF /* end fast-exec-scache */ - - SET_H_PC (vpc); - - ++ CPU_INSN_COUNT (current_cpu); } while (0 /*CPU_RUNNING_P (current_cpu)*/); } @@ -649,7 +800,7 @@ EOF fi # -fast -fi # -scache +fi # -scache && parallel ########################################################################## @@ -766,6 +917,7 @@ cat << EOF sc->argbuf.addr = pc; sc->argbuf.fields.chain.insn_count = _insn_count; sc->argbuf.fields.chain.next = 0; + sc->argbuf.fields.chain.branch_target = 0; ++sc; } @@ -817,15 +969,17 @@ INLINE SEM_PC } /* Chain to the next block from a cti terminated previous block. - NEW_VPC_PTR is one of SEM_BRANCH_UNTAKEN, SEM_BRANCH_UNCACHEABLE, or - a pointer to a location containing the SEM_PC of the branch's address. + BR_TYPE indicates whether the branch was taken and whether we can cache + the vpc of the branch target. NEW_PC is the target's branch address, and is only valid if - NEW_VPC_PTR != SEM_BRANCH_UNTAKEN. */ + BR_TYPE != SEM_BRANCH_UNTAKEN. */ INLINE SEM_PC @cpu@_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg, - SEM_PC *new_vpc_ptr, PCADDR new_pc) + SEM_BRANCH_TYPE br_type, PCADDR new_pc) { + SEM_PC *new_vpc_ptr; + PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg); /* If not running forever, exit back to main loop. */ @@ -841,7 +995,7 @@ INLINE SEM_PC /* Restart compiler if we branched to an uncacheable address (e.g. "j reg"). */ - if (new_vpc_ptr == SEM_BRANCH_UNCACHEABLE) + if (br_type == SEM_BRANCH_UNCACHEABLE) { SET_H_PC (new_pc); return CPU_SCACHE_PBB_BEGIN (current_cpu); @@ -849,22 +1003,25 @@ INLINE SEM_PC /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our next chain ptr. */ - if (new_vpc_ptr == SEM_BRANCH_UNTAKEN) + if (br_type == SEM_BRANCH_UNTAKEN) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); - SET_H_PC (abuf->addr); + new_pc = abuf->addr; + SET_H_PC (new_pc); new_vpc_ptr = &abuf->fields.chain.next; } else { + ARGBUF *abuf = SEM_ARGBUF (sem_arg); SET_H_PC (new_pc); + new_vpc_ptr = &abuf->fields.chain.branch_target; } /* If chained to next block, go straight to it. */ if (*new_vpc_ptr) return *new_vpc_ptr; /* See if next block has already been compiled. */ - *new_vpc_ptr = scache_lookup (current_cpu, GET_H_PC ()); + *new_vpc_ptr = scache_lookup (current_cpu, new_pc); if (*new_vpc_ptr) return *new_vpc_ptr; /* Nope, so next insn is a virtual insn to invoke the compiler @@ -955,8 +1112,8 @@ void SEM_PC vpc; #if WITH_SEM_SWITCH_FULL /* For communication between cti's and cti-chain. */ + SEM_BRANCH_TYPE pbb_br_type; PCADDR pbb_br_npc; - SEM_PC *pbb_br_npc_ptr; #endif EOF @@ -983,11 +1140,15 @@ cat << EOF a pbb). And in the "let's run until we're done" case we don't return until the program exits. */ -#if WITH_SEM_SWITCH_FULL && defined (__GNUC__) +#if WITH_SEM_SWITCH_FULL +#if defined (__GNUC__) /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */ #define DEFINE_LABELS #include "$switch" #endif +#else + @cpu@_sem_init_idesc_table (current_cpu); +#endif /* Initialize the "begin (compile) a pbb" virtual insn. */ vpc = CPU_SCACHE_PBB_BEGIN (current_cpu); @@ -1041,8 +1202,8 @@ void SEM_PC vpc; #if WITH_SEM_SWITCH_FAST /* For communication between cti's and cti-chain. */ + SEM_BRANCH_TYPE pbb_br_type; PCADDR pbb_br_npc; - SEM_PC *pbb_br_npc_ptr; #endif EOF @@ -1069,11 +1230,15 @@ cat << EOF a pbb). And in the "let's run until we're done" case we don't return until the program exits. */ -#if WITH_SEM_SWITCH_FAST && defined (__GNUC__) +#if WITH_SEM_SWITCH_FAST +#if defined (__GNUC__) /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */ #define DEFINE_LABELS #include "$switch" #endif +#else + @cpu@_semf_init_idesc_table (current_cpu); +#endif /* Initialize the "begin (compile) a pbb" virtual insn. */ vpc = CPU_SCACHE_PBB_BEGIN (current_cpu); diff --git a/sim/fr30/ChangeLog b/sim/fr30/ChangeLog index 16ad6d4..7b39970 100644 --- a/sim/fr30/ChangeLog +++ b/sim/fr30/ChangeLog @@ -1,3 +1,11 @@ +1999-08-09 Doug Evans + + * cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild. + +1999-08-04 Doug Evans + + * cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild. + 1999-07-06 Doug Evans * cpu.h,decode.h,model.c,sem-switch.c,sem.c: Rebuild. diff --git a/sim/fr30/cpu.h b/sim/fr30/cpu.h index fa07884..27745da1 100644 --- a/sim/fr30/cpu.h +++ b/sim/fr30/cpu.h @@ -189,536 +189,227 @@ typedef struct { UINT load_regs_pending; } MODEL_FR30_1_DATA; +/* Instruction argument buffer. */ + union sem_fields { - struct { /* empty sformat for unspecified field list */ - int empty; - } fmt_empty; - struct { /* e.g. add $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_add; - struct { /* e.g. add $u4,$Ri */ - UINT f_u4; - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_addi; - struct { /* e.g. add2 $m4,$Ri */ - SI f_m4; - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_add2; - struct { /* e.g. addc $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_addc; - struct { /* e.g. addn $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_addn; - struct { /* e.g. addn $u4,$Ri */ - UINT f_u4; - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_addni; - struct { /* e.g. addn2 $m4,$Ri */ - SI f_m4; - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_addn2; - struct { /* e.g. cmp $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_cmp; - struct { /* e.g. cmp $u4,$Ri */ - UINT f_u4; - SI * i_Ri; - unsigned char in_Ri; - } fmt_cmpi; - struct { /* e.g. cmp2 $m4,$Ri */ - SI f_m4; - SI * i_Ri; - unsigned char in_Ri; - } fmt_cmp2; - struct { /* e.g. and $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_and; - struct { /* e.g. and $Rj,@$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_andm; - struct { /* e.g. andh $Rj,@$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_andh; - struct { /* e.g. andb $Rj,@$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_andb; - struct { /* e.g. bandl $u4,@$Ri */ - UINT f_u4; - SI * i_Ri; - unsigned char in_Ri; - } fmt_bandl; - struct { /* e.g. btstl $u4,@$Ri */ - UINT f_u4; - SI * i_Ri; - unsigned char in_Ri; - } fmt_btstl; - struct { /* e.g. mul $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_mul; - struct { /* e.g. mulu $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_mulu; - struct { /* e.g. mulh $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_mulh; - struct { /* e.g. div0s $Ri */ - SI * i_Ri; - unsigned char in_Ri; - } fmt_div0s; - struct { /* e.g. div0u $Ri */ - int empty; - } fmt_div0u; - struct { /* e.g. div1 $Ri */ - SI * i_Ri; - unsigned char in_Ri; - } fmt_div1; - struct { /* e.g. div2 $Ri */ - SI * i_Ri; - unsigned char in_Ri; - } fmt_div2; - struct { /* e.g. div3 */ - int empty; - } fmt_div3; - struct { /* e.g. div4s */ - int empty; - } fmt_div4s; - struct { /* e.g. lsl $Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_lsl; - struct { /* e.g. lsl $u4,$Ri */ - UINT f_u4; - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_lsli; - struct { /* e.g. ldi:8 $i8,$Ri */ - UINT f_i8; - SI * i_Ri; - unsigned char out_Ri; - } fmt_ldi8; - struct { /* e.g. ldi:20 $i20,$Ri */ - UINT f_i20; - SI * i_Ri; - unsigned char out_Ri; - } fmt_ldi20; - struct { /* e.g. ldi:32 $i32,$Ri */ - UINT f_i32; - SI * i_Ri; - unsigned char out_Ri; - } fmt_ldi32; - struct { /* e.g. ld @$Rj,$Ri */ - SI * i_Rj; - SI * i_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_ld; - struct { /* e.g. ld @($R13,$Rj),$Ri */ - SI * i_Rj; - SI * i_Ri; - unsigned char in_Rj; - unsigned char in_h_gr_13; - unsigned char out_Ri; - } fmt_ldr13; - struct { /* e.g. ld @($R14,$disp10),$Ri */ - SI f_disp10; - SI * i_Ri; - unsigned char in_h_gr_14; - unsigned char out_Ri; - } fmt_ldr14; - struct { /* e.g. lduh @($R14,$disp9),$Ri */ - SI f_disp9; - SI * i_Ri; - unsigned char in_h_gr_14; - unsigned char out_Ri; - } fmt_ldr14uh; - struct { /* e.g. ldub @($R14,$disp8),$Ri */ - INT f_disp8; - SI * i_Ri; - unsigned char in_h_gr_14; - unsigned char out_Ri; - } fmt_ldr14ub; - struct { /* e.g. ld @($R15,$udisp6),$Ri */ - USI f_udisp6; - SI * i_Ri; - unsigned char in_h_gr_15; - unsigned char out_Ri; - } fmt_ldr15; - struct { /* e.g. ld @$R15+,$Ri */ - UINT f_Ri; - SI * i_Ri; - unsigned char in_h_gr_15; - unsigned char out_Ri; - unsigned char out_h_gr_15; - } fmt_ldr15gr; - struct { /* e.g. ld @$R15+,$Rs2 */ - UINT f_Rs2; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_ldr15dr; - struct { /* e.g. ld @$R15+,$ps */ - int empty; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_ldr15ps; - struct { /* e.g. st $Ri,@$Rj */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - } fmt_st; - struct { /* e.g. st $Ri,@($R13,$Rj) */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char in_h_gr_13; - } fmt_str13; - struct { /* e.g. st $Ri,@($R14,$disp10) */ - SI f_disp10; - SI * i_Ri; - unsigned char in_Ri; - unsigned char in_h_gr_14; - } fmt_str14; - struct { /* e.g. sth $Ri,@($R14,$disp9) */ - SI f_disp9; - SI * i_Ri; - unsigned char in_Ri; - unsigned char in_h_gr_14; - } fmt_str14h; - struct { /* e.g. stb $Ri,@($R14,$disp8) */ - INT f_disp8; - SI * i_Ri; - unsigned char in_Ri; - unsigned char in_h_gr_14; - } fmt_str14b; - struct { /* e.g. st $Ri,@($R15,$udisp6) */ - USI f_udisp6; - SI * i_Ri; - unsigned char in_Ri; - unsigned char in_h_gr_15; - } fmt_str15; - struct { /* e.g. st $Ri,@-$R15 */ - SI * i_Ri; - unsigned char in_Ri; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_str15gr; - struct { /* e.g. st $Rs2,@-$R15 */ - UINT f_Rs2; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_str15dr; - struct { /* e.g. st $ps,@-$R15 */ - int empty; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_str15ps; - struct { /* e.g. mov $Rj,$Ri */ - SI * i_Rj; - SI * i_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_mov; - struct { /* e.g. mov $Rs1,$Ri */ - UINT f_Rs1; - SI * i_Ri; - unsigned char out_Ri; - } fmt_movdr; - struct { /* e.g. mov $ps,$Ri */ - SI * i_Ri; - unsigned char out_Ri; - } fmt_movps; - struct { /* e.g. mov $Ri,$Rs1 */ - UINT f_Rs1; - SI * i_Ri; - unsigned char in_Ri; - } fmt_mov2dr; - struct { /* e.g. mov $Ri,$ps */ - SI * i_Ri; - unsigned char in_Ri; - } fmt_mov2ps; - struct { /* e.g. bno:d $label9 */ - int empty; - } fmt_bnod; - struct { /* e.g. dmov $R13,@$dir10 */ - USI f_dir10; - unsigned char in_h_gr_13; - } fmt_dmovr13; - struct { /* e.g. dmovh $R13,@$dir9 */ - USI f_dir9; - unsigned char in_h_gr_13; - } fmt_dmovr13h; - struct { /* e.g. dmovb $R13,@$dir8 */ - UINT f_dir8; - unsigned char in_h_gr_13; - } fmt_dmovr13b; - struct { /* e.g. dmov @$R13+,@$dir10 */ - USI f_dir10; - unsigned char in_h_gr_13; - unsigned char out_h_gr_13; - } fmt_dmovr13pi; - struct { /* e.g. dmovh @$R13+,@$dir9 */ - USI f_dir9; - unsigned char in_h_gr_13; - unsigned char out_h_gr_13; - } fmt_dmovr13pih; - struct { /* e.g. dmovb @$R13+,@$dir8 */ - UINT f_dir8; - unsigned char in_h_gr_13; - unsigned char out_h_gr_13; - } fmt_dmovr13pib; - struct { /* e.g. dmov @$R15+,@$dir10 */ - USI f_dir10; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_dmovr15pi; - struct { /* e.g. dmov @$dir10,$R13 */ - USI f_dir10; - unsigned char out_h_gr_13; - } fmt_dmov2r13; - struct { /* e.g. dmovh @$dir9,$R13 */ - USI f_dir9; - unsigned char out_h_gr_13; - } fmt_dmov2r13h; - struct { /* e.g. dmovb @$dir8,$R13 */ - UINT f_dir8; - unsigned char out_h_gr_13; - } fmt_dmov2r13b; - struct { /* e.g. dmov @$dir10,@$R13+ */ - USI f_dir10; - unsigned char in_h_gr_13; - unsigned char out_h_gr_13; - } fmt_dmov2r13pi; - struct { /* e.g. dmovh @$dir9,@$R13+ */ - USI f_dir9; - unsigned char in_h_gr_13; - unsigned char out_h_gr_13; - } fmt_dmov2r13pih; - struct { /* e.g. dmovb @$dir8,@$R13+ */ - UINT f_dir8; - unsigned char in_h_gr_13; - unsigned char out_h_gr_13; - } fmt_dmov2r13pib; - struct { /* e.g. dmov @$dir10,@-$R15 */ - USI f_dir10; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_dmov2r15pd; - struct { /* e.g. ldres @$Ri+,$u4 */ - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_ldres; - struct { /* e.g. copop $u4c,$ccc,$CRj,$CRi */ - int empty; - } fmt_copop; - struct { /* e.g. andccr $u8 */ - UINT f_u8; - } fmt_andccr; - struct { /* e.g. stilm $u8 */ - UINT f_u8; - } fmt_stilm; - struct { /* e.g. addsp $s10 */ - SI f_s10; - unsigned char in_h_gr_15; - unsigned char out_h_gr_15; - } fmt_addsp; - struct { /* e.g. extsb $Ri */ - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_extsb; - struct { /* e.g. extub $Ri */ - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_extub; - struct { /* e.g. extsh $Ri */ - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_extsh; - struct { /* e.g. extuh $Ri */ - SI * i_Ri; - unsigned char in_Ri; - unsigned char out_Ri; - } fmt_extuh; - struct { /* e.g. ldm0 ($reglist_low_ld) */ - UINT f_reglist_low_ld; - unsigned char in_h_gr_15; - unsigned char out_h_gr_0; - unsigned char out_h_gr_1; - unsigned char out_h_gr_15; - unsigned char out_h_gr_2; - unsigned char out_h_gr_3; - unsigned char out_h_gr_4; - unsigned char out_h_gr_5; - unsigned char out_h_gr_6; - unsigned char out_h_gr_7; - } fmt_ldm0; - struct { /* e.g. ldm1 ($reglist_hi_ld) */ - UINT f_reglist_hi_ld; - unsigned char in_h_gr_15; - unsigned char out_h_gr_10; - unsigned char out_h_gr_11; - unsigned char out_h_gr_12; - unsigned char out_h_gr_13; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - unsigned char out_h_gr_8; - unsigned char out_h_gr_9; - } fmt_ldm1; - struct { /* e.g. stm0 ($reglist_low_st) */ - UINT f_reglist_low_st; - unsigned char in_h_gr_0; - unsigned char in_h_gr_1; - unsigned char in_h_gr_15; - unsigned char in_h_gr_2; - unsigned char in_h_gr_3; - unsigned char in_h_gr_4; - unsigned char in_h_gr_5; - unsigned char in_h_gr_6; - unsigned char in_h_gr_7; - unsigned char out_h_gr_15; - } fmt_stm0; - struct { /* e.g. stm1 ($reglist_hi_st) */ - UINT f_reglist_hi_st; - unsigned char in_h_gr_10; - unsigned char in_h_gr_11; - unsigned char in_h_gr_12; - unsigned char in_h_gr_13; - unsigned char in_h_gr_14; - unsigned char in_h_gr_15; - unsigned char in_h_gr_8; - unsigned char in_h_gr_9; - unsigned char out_h_gr_15; - } fmt_stm1; - struct { /* e.g. enter $u10 */ - USI f_u10; - unsigned char in_h_gr_14; - unsigned char in_h_gr_15; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - } fmt_enter; - struct { /* e.g. leave */ - int empty; - unsigned char in_h_gr_14; - unsigned char in_h_gr_15; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - } fmt_leave; - struct { /* e.g. xchb @$Rj,$Ri */ - SI * i_Ri; - SI * i_Rj; - unsigned char in_Ri; - unsigned char in_Rj; - unsigned char out_Ri; - } fmt_xchb; - /* cti insns, kept separately so addr_cache is in fixed place */ - struct { - union { - struct { /* e.g. jmp @$Ri */ - SI * i_Ri; - unsigned char in_Ri; - } fmt_jmp; - struct { /* e.g. call @$Ri */ - SI * i_Ri; - unsigned char in_Ri; - } fmt_callr; - struct { /* e.g. call $label12 */ - IADDR i_label12; - } fmt_call; - struct { /* e.g. ret */ - int empty; - } fmt_ret; - struct { /* e.g. int $u8 */ - UINT f_u8; - } fmt_int; - struct { /* e.g. inte */ - int empty; - } fmt_inte; - struct { /* e.g. reti */ - int empty; - } fmt_reti; - struct { /* e.g. bra:d $label9 */ - IADDR i_label9; - } fmt_brad; - struct { /* e.g. beq:d $label9 */ - IADDR i_label9; - } fmt_beqd; - struct { /* e.g. bc:d $label9 */ - IADDR i_label9; - } fmt_bcd; - struct { /* e.g. bn:d $label9 */ - IADDR i_label9; - } fmt_bnd; - struct { /* e.g. bv:d $label9 */ - IADDR i_label9; - } fmt_bvd; - struct { /* e.g. blt:d $label9 */ - IADDR i_label9; - } fmt_bltd; - struct { /* e.g. ble:d $label9 */ - IADDR i_label9; - } fmt_bled; - struct { /* e.g. bls:d $label9 */ - IADDR i_label9; - } fmt_blsd; - } fields; -#if WITH_SCACHE_PBB - SEM_PC addr_cache; -#endif - } cti; + struct { /* no operands */ + int empty; + } fmt_empty; + struct { /* */ + IADDR i_label9; + } sfmt_brad; + struct { /* */ + UINT f_u8; + } sfmt_int; + struct { /* */ + IADDR i_label12; + } sfmt_call; + struct { /* */ + SI f_s10; + unsigned char in_h_gr_15; + unsigned char out_h_gr_15; + } sfmt_addsp; + struct { /* */ + USI f_dir10; + unsigned char in_h_gr_15; + unsigned char out_h_gr_15; + } sfmt_dmovr15pi; + struct { /* */ + UINT f_dir8; + unsigned char in_h_gr_13; + unsigned char out_h_gr_13; + } sfmt_dmovr13pib; + struct { /* */ + USI f_dir9; + unsigned char in_h_gr_13; + unsigned char out_h_gr_13; + } sfmt_dmovr13pih; + struct { /* */ + USI f_dir10; + unsigned char in_h_gr_13; + unsigned char out_h_gr_13; + } sfmt_dmovr13pi; + struct { /* */ + SI* i_Ri; + UINT f_Rs1; + unsigned char in_Ri; + } sfmt_mov2dr; + struct { /* */ + SI* i_Ri; + UINT f_Rs1; + unsigned char out_Ri; + } sfmt_movdr; + struct { /* */ + UINT f_Rs2; + unsigned char in_h_gr_15; + unsigned char out_h_gr_15; + } sfmt_ldr15dr; + struct { /* */ + SI* i_Ri; + UINT f_i32; + unsigned char out_Ri; + } sfmt_ldi32; + struct { /* */ + SI* i_Ri; + UINT f_i20; + unsigned char out_Ri; + } sfmt_ldi20; + struct { /* */ + SI* i_Ri; + UINT f_i8; + unsigned char out_Ri; + } sfmt_ldi8; + struct { /* */ + SI* i_Ri; + unsigned char in_Ri; + unsigned char in_h_gr_15; + unsigned char out_h_gr_15; + } sfmt_str15gr; + struct { /* */ + SI* i_Ri; + USI f_udisp6; + unsigned char in_Ri; + unsigned char in_h_gr_15; + } sfmt_str15; + struct { /* */ + SI* i_Ri; + INT f_disp8; + unsigned char in_Ri; + unsigned char in_h_gr_14; + } sfmt_str14b; + struct { /* */ + SI* i_Ri; + SI f_disp9; + unsigned char in_Ri; + unsigned char in_h_gr_14; + } sfmt_str14h; + struct { /* */ + SI* i_Ri; + SI f_disp10; + unsigned char in_Ri; + unsigned char in_h_gr_14; + } sfmt_str14; + struct { /* */ + SI* i_Ri; + USI f_udisp6; + unsigned char in_h_gr_15; + unsigned char out_Ri; + } sfmt_ldr15; + struct { /* */ + SI* i_Ri; + INT f_disp8; + unsigned char in_h_gr_14; + unsigned char out_Ri; + } sfmt_ldr14ub; + struct { /* */ + SI* i_Ri; + SI f_disp9; + unsigned char in_h_gr_14; + unsigned char out_Ri; + } sfmt_ldr14uh; + struct { /* */ + SI* i_Ri; + SI f_disp10; + unsigned char in_h_gr_14; + unsigned char out_Ri; + } sfmt_ldr14; + struct { /* */ + SI* i_Ri; + SI f_m4; + unsigned char in_Ri; + unsigned char out_Ri; + } sfmt_add2; + struct { /* */ + SI* i_Ri; + UINT f_u4; + unsigned char in_Ri; + unsigned char out_Ri; + } sfmt_addi; + struct { /* */ + USI f_u10; + unsigned char in_h_gr_14; + unsigned char in_h_gr_15; + unsigned char out_h_gr_14; + unsigned char out_h_gr_15; + } sfmt_enter; + struct { /* */ + SI* i_Ri; + SI* i_Rj; + unsigned char in_Ri; + unsigned char in_Rj; + unsigned char in_h_gr_13; + } sfmt_str13; + struct { /* */ + SI* i_Ri; + UINT f_Ri; + unsigned char in_h_gr_15; + unsigned char out_Ri; + unsigned char out_h_gr_15; + } sfmt_ldr15gr; + struct { /* */ + SI* i_Ri; + SI* i_Rj; + unsigned char in_Rj; + unsigned char in_h_gr_13; + unsigned char out_Ri; + } sfmt_ldr13; + struct { /* */ + SI* i_Ri; + SI* i_Rj; + unsigned char in_Ri; + unsigned char in_Rj; + unsigned char out_Ri; + } sfmt_add; + struct { /* */ + UINT f_reglist_hi_st; + unsigned char in_h_gr_10; + unsigned char in_h_gr_11; + unsigned char in_h_gr_12; + unsigned char in_h_gr_13; + unsigned char in_h_gr_14; + unsigned char in_h_gr_15; + unsigned char in_h_gr_8; + unsigned char in_h_gr_9; + unsigned char out_h_gr_15; + } sfmt_stm1; + struct { /* */ + UINT f_reglist_hi_ld; + unsigned char in_h_gr_15; + unsigned char out_h_gr_10; + unsigned char out_h_gr_11; + unsigned char out_h_gr_12; + unsigned char out_h_gr_13; + unsigned char out_h_gr_14; + unsigned char out_h_gr_15; + unsigned char out_h_gr_8; + unsigned char out_h_gr_9; + } sfmt_ldm1; + struct { /* */ + UINT f_reglist_low_st; + unsigned char in_h_gr_0; + unsigned char in_h_gr_1; + unsigned char in_h_gr_15; + unsigned char in_h_gr_2; + unsigned char in_h_gr_3; + unsigned char in_h_gr_4; + unsigned char in_h_gr_5; + unsigned char in_h_gr_6; + unsigned char in_h_gr_7; + unsigned char out_h_gr_15; + } sfmt_stm0; + struct { /* */ + UINT f_reglist_low_ld; + unsigned char in_h_gr_15; + unsigned char out_h_gr_0; + unsigned char out_h_gr_1; + unsigned char out_h_gr_15; + unsigned char out_h_gr_2; + unsigned char out_h_gr_3; + unsigned char out_h_gr_4; + unsigned char out_h_gr_5; + unsigned char out_h_gr_6; + unsigned char out_h_gr_7; + } sfmt_ldm0; #if WITH_SCACHE_PBB /* Writeback handler. */ struct { @@ -740,6 +431,7 @@ union sem_fields { int insn_count; /* Next pbb to execute. */ SCACHE *next; + SCACHE *branch_target; } chain; #endif }; @@ -751,6 +443,9 @@ struct argbuf { const IDESC *idesc; char trace_p; char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; /* cpu specific data follows */ union sem semantic; int written; @@ -771,13 +466,11 @@ struct scache { These define and assign the local vars that contain the insn's fields. */ #define EXTRACT_IFMT_EMPTY_VARS \ - /* Instruction fields. */ \ unsigned int length; #define EXTRACT_IFMT_EMPTY_CODE \ length = 0; \ #define EXTRACT_IFMT_ADD_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_Rj; \ @@ -791,7 +484,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_ADDI_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_u4; \ @@ -805,7 +497,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_ADD2_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ SI f_m4; \ @@ -819,7 +510,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_DIV0S_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_op3; \ @@ -833,7 +523,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_DIV3_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_op3; \ @@ -847,7 +536,6 @@ struct scache { f_op4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDI8_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_i8; \ UINT f_Ri; \ @@ -859,7 +547,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDI20_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_i20_4; \ UINT f_i20_16; \ @@ -882,7 +569,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDI32_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_i32; \ UINT f_op2; \ @@ -903,7 +589,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDR14_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ SI f_disp10; \ UINT f_Ri; \ @@ -915,7 +600,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDR14UH_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ SI f_disp9; \ UINT f_Ri; \ @@ -927,7 +611,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDR14UB_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ INT f_disp8; \ UINT f_Ri; \ @@ -939,7 +622,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDR15_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ USI f_udisp6; \ @@ -953,7 +635,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LDR15DR_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_op3; \ @@ -967,7 +648,6 @@ struct scache { f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_MOVDR_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_Rs1; \ @@ -981,7 +661,6 @@ struct scache { f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_CALL_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op5; \ SI f_rel12; \ @@ -993,7 +672,6 @@ struct scache { f_rel12 = ((((EXTRACT_MSB0_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \ #define EXTRACT_IFMT_INT_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_u8; \ @@ -1005,7 +683,6 @@ struct scache { f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_BRAD_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_cc; \ SI f_rel9; \ @@ -1017,7 +694,6 @@ struct scache { f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \ #define EXTRACT_IFMT_DMOVR13_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ USI f_dir10; \ @@ -1029,7 +705,6 @@ struct scache { f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \ #define EXTRACT_IFMT_DMOVR13H_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ USI f_dir9; \ @@ -1041,7 +716,6 @@ struct scache { f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \ #define EXTRACT_IFMT_DMOVR13B_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_dir8; \ @@ -1053,7 +727,6 @@ struct scache { f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_COPOP_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_ccc; \ UINT f_op2; \ @@ -1076,7 +749,6 @@ struct scache { f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \ #define EXTRACT_IFMT_COPLD_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_ccc; \ UINT f_op2; \ @@ -1099,7 +771,6 @@ struct scache { f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \ #define EXTRACT_IFMT_COPST_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_ccc; \ UINT f_op2; \ @@ -1122,7 +793,6 @@ struct scache { f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \ #define EXTRACT_IFMT_ADDSP_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ SI f_s10; \ @@ -1134,7 +804,6 @@ struct scache { f_s10 = ((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2)); \ #define EXTRACT_IFMT_LDM0_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_reglist_low_ld; \ @@ -1146,7 +815,6 @@ struct scache { f_reglist_low_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_LDM1_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_reglist_hi_ld; \ @@ -1158,7 +826,6 @@ struct scache { f_reglist_hi_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_STM0_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_reglist_low_st; \ @@ -1170,7 +837,6 @@ struct scache { f_reglist_low_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_STM1_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ UINT f_reglist_hi_st; \ @@ -1182,7 +848,6 @@ struct scache { f_reglist_hi_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_ENTER_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_op2; \ USI f_u10; \ diff --git a/sim/fr30/cpuall.h b/sim/fr30/cpuall.h index dc8ed96..f0ebb90 100644 --- a/sim/fr30/cpuall.h +++ b/sim/fr30/cpuall.h @@ -44,6 +44,9 @@ struct argbuf { const IDESC *idesc; char trace_p; char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; /* cpu specific data follows */ }; #endif diff --git a/sim/fr30/decode.c b/sim/fr30/decode.c index ef87676..3ed6a11 100644 --- a/sim/fr30/decode.c +++ b/sim/fr30/decode.c @@ -28,29 +28,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-main.h" #include "sim-assert.h" -/* FIXME: Need to review choices for the following. */ - -#if WITH_SEM_SWITCH_FULL -#define FULL(fn) -#else -#define FULL(fn) CONCAT3 (fr30bf,_sem_,fn) , -#endif - -#if WITH_FAST -#if WITH_SEM_SWITCH_FAST -#define FAST(fn) -#else -#define FAST(fn) CONCAT3 (fr30bf,_semf_,fn) , /* f for fast */ -#endif -#else -#define FAST(fn) -#endif - -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (FR30BF_,insn) -#define TYPE(insn) CONCAT2 (FR30_,insn) - /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -63,190 +40,183 @@ static IDESC fr30bf_insn_data[FR30BF_INSN_MAX]; static const struct insn_sem fr30bf_insn_sem[] = { - { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, - { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, - { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, - { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, - { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, - { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, - { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) }, - { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) }, - { TYPE (INSN_ADD2), IDX (INSN_ADD2), FULL (add2) FAST (add2) }, - { TYPE (INSN_ADDC), IDX (INSN_ADDC), FULL (addc) FAST (addc) }, - { TYPE (INSN_ADDN), IDX (INSN_ADDN), FULL (addn) FAST (addn) }, - { TYPE (INSN_ADDNI), IDX (INSN_ADDNI), FULL (addni) FAST (addni) }, - { TYPE (INSN_ADDN2), IDX (INSN_ADDN2), FULL (addn2) FAST (addn2) }, - { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) }, - { TYPE (INSN_SUBC), IDX (INSN_SUBC), FULL (subc) FAST (subc) }, - { TYPE (INSN_SUBN), IDX (INSN_SUBN), FULL (subn) FAST (subn) }, - { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) }, - { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) }, - { TYPE (INSN_CMP2), IDX (INSN_CMP2), FULL (cmp2) FAST (cmp2) }, - { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, - { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, - { TYPE (INSN_EOR), IDX (INSN_EOR), FULL (eor) FAST (eor) }, - { TYPE (INSN_ANDM), IDX (INSN_ANDM), FULL (andm) FAST (andm) }, - { TYPE (INSN_ANDH), IDX (INSN_ANDH), FULL (andh) FAST (andh) }, - { TYPE (INSN_ANDB), IDX (INSN_ANDB), FULL (andb) FAST (andb) }, - { TYPE (INSN_ORM), IDX (INSN_ORM), FULL (orm) FAST (orm) }, - { TYPE (INSN_ORH), IDX (INSN_ORH), FULL (orh) FAST (orh) }, - { TYPE (INSN_ORB), IDX (INSN_ORB), FULL (orb) FAST (orb) }, - { TYPE (INSN_EORM), IDX (INSN_EORM), FULL (eorm) FAST (eorm) }, - { TYPE (INSN_EORH), IDX (INSN_EORH), FULL (eorh) FAST (eorh) }, - { TYPE (INSN_EORB), IDX (INSN_EORB), FULL (eorb) FAST (eorb) }, - { TYPE (INSN_BANDL), IDX (INSN_BANDL), FULL (bandl) FAST (bandl) }, - { TYPE (INSN_BORL), IDX (INSN_BORL), FULL (borl) FAST (borl) }, - { TYPE (INSN_BEORL), IDX (INSN_BEORL), FULL (beorl) FAST (beorl) }, - { TYPE (INSN_BANDH), IDX (INSN_BANDH), FULL (bandh) FAST (bandh) }, - { TYPE (INSN_BORH), IDX (INSN_BORH), FULL (borh) FAST (borh) }, - { TYPE (INSN_BEORH), IDX (INSN_BEORH), FULL (beorh) FAST (beorh) }, - { TYPE (INSN_BTSTL), IDX (INSN_BTSTL), FULL (btstl) FAST (btstl) }, - { TYPE (INSN_BTSTH), IDX (INSN_BTSTH), FULL (btsth) FAST (btsth) }, - { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) }, - { TYPE (INSN_MULU), IDX (INSN_MULU), FULL (mulu) FAST (mulu) }, - { TYPE (INSN_MULH), IDX (INSN_MULH), FULL (mulh) FAST (mulh) }, - { TYPE (INSN_MULUH), IDX (INSN_MULUH), FULL (muluh) FAST (muluh) }, - { TYPE (INSN_DIV0S), IDX (INSN_DIV0S), FULL (div0s) FAST (div0s) }, - { TYPE (INSN_DIV0U), IDX (INSN_DIV0U), FULL (div0u) FAST (div0u) }, - { TYPE (INSN_DIV1), IDX (INSN_DIV1), FULL (div1) FAST (div1) }, - { TYPE (INSN_DIV2), IDX (INSN_DIV2), FULL (div2) FAST (div2) }, - { TYPE (INSN_DIV3), IDX (INSN_DIV3), FULL (div3) FAST (div3) }, - { TYPE (INSN_DIV4S), IDX (INSN_DIV4S), FULL (div4s) FAST (div4s) }, - { TYPE (INSN_LSL), IDX (INSN_LSL), FULL (lsl) FAST (lsl) }, - { TYPE (INSN_LSLI), IDX (INSN_LSLI), FULL (lsli) FAST (lsli) }, - { TYPE (INSN_LSL2), IDX (INSN_LSL2), FULL (lsl2) FAST (lsl2) }, - { TYPE (INSN_LSR), IDX (INSN_LSR), FULL (lsr) FAST (lsr) }, - { TYPE (INSN_LSRI), IDX (INSN_LSRI), FULL (lsri) FAST (lsri) }, - { TYPE (INSN_LSR2), IDX (INSN_LSR2), FULL (lsr2) FAST (lsr2) }, - { TYPE (INSN_ASR), IDX (INSN_ASR), FULL (asr) FAST (asr) }, - { TYPE (INSN_ASRI), IDX (INSN_ASRI), FULL (asri) FAST (asri) }, - { TYPE (INSN_ASR2), IDX (INSN_ASR2), FULL (asr2) FAST (asr2) }, - { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) }, - { TYPE (INSN_LDI20), IDX (INSN_LDI20), FULL (ldi20) FAST (ldi20) }, - { TYPE (INSN_LDI32), IDX (INSN_LDI32), FULL (ldi32) FAST (ldi32) }, - { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) }, - { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) }, - { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) }, - { TYPE (INSN_LDR13), IDX (INSN_LDR13), FULL (ldr13) FAST (ldr13) }, - { TYPE (INSN_LDR13UH), IDX (INSN_LDR13UH), FULL (ldr13uh) FAST (ldr13uh) }, - { TYPE (INSN_LDR13UB), IDX (INSN_LDR13UB), FULL (ldr13ub) FAST (ldr13ub) }, - { TYPE (INSN_LDR14), IDX (INSN_LDR14), FULL (ldr14) FAST (ldr14) }, - { TYPE (INSN_LDR14UH), IDX (INSN_LDR14UH), FULL (ldr14uh) FAST (ldr14uh) }, - { TYPE (INSN_LDR14UB), IDX (INSN_LDR14UB), FULL (ldr14ub) FAST (ldr14ub) }, - { TYPE (INSN_LDR15), IDX (INSN_LDR15), FULL (ldr15) FAST (ldr15) }, - { TYPE (INSN_LDR15GR), IDX (INSN_LDR15GR), FULL (ldr15gr) FAST (ldr15gr) }, - { TYPE (INSN_LDR15DR), IDX (INSN_LDR15DR), FULL (ldr15dr) FAST (ldr15dr) }, - { TYPE (INSN_LDR15PS), IDX (INSN_LDR15PS), FULL (ldr15ps) FAST (ldr15ps) }, - { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) }, - { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) }, - { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) }, - { TYPE (INSN_STR13), IDX (INSN_STR13), FULL (str13) FAST (str13) }, - { TYPE (INSN_STR13H), IDX (INSN_STR13H), FULL (str13h) FAST (str13h) }, - { TYPE (INSN_STR13B), IDX (INSN_STR13B), FULL (str13b) FAST (str13b) }, - { TYPE (INSN_STR14), IDX (INSN_STR14), FULL (str14) FAST (str14) }, - { TYPE (INSN_STR14H), IDX (INSN_STR14H), FULL (str14h) FAST (str14h) }, - { TYPE (INSN_STR14B), IDX (INSN_STR14B), FULL (str14b) FAST (str14b) }, - { TYPE (INSN_STR15), IDX (INSN_STR15), FULL (str15) FAST (str15) }, - { TYPE (INSN_STR15GR), IDX (INSN_STR15GR), FULL (str15gr) FAST (str15gr) }, - { TYPE (INSN_STR15DR), IDX (INSN_STR15DR), FULL (str15dr) FAST (str15dr) }, - { TYPE (INSN_STR15PS), IDX (INSN_STR15PS), FULL (str15ps) FAST (str15ps) }, - { TYPE (INSN_MOV), IDX (INSN_MOV), FULL (mov) FAST (mov) }, - { TYPE (INSN_MOVDR), IDX (INSN_MOVDR), FULL (movdr) FAST (movdr) }, - { TYPE (INSN_MOVPS), IDX (INSN_MOVPS), FULL (movps) FAST (movps) }, - { TYPE (INSN_MOV2DR), IDX (INSN_MOV2DR), FULL (mov2dr) FAST (mov2dr) }, - { TYPE (INSN_MOV2PS), IDX (INSN_MOV2PS), FULL (mov2ps) FAST (mov2ps) }, - { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) }, - { TYPE (INSN_JMPD), IDX (INSN_JMPD), FULL (jmpd) FAST (jmpd) }, - { TYPE (INSN_CALLR), IDX (INSN_CALLR), FULL (callr) FAST (callr) }, - { TYPE (INSN_CALLRD), IDX (INSN_CALLRD), FULL (callrd) FAST (callrd) }, - { TYPE (INSN_CALL), IDX (INSN_CALL), FULL (call) FAST (call) }, - { TYPE (INSN_CALLD), IDX (INSN_CALLD), FULL (calld) FAST (calld) }, - { TYPE (INSN_RET), IDX (INSN_RET), FULL (ret) FAST (ret) }, - { TYPE (INSN_RET_D), IDX (INSN_RET_D), FULL (ret_d) FAST (ret_d) }, - { TYPE (INSN_INT), IDX (INSN_INT), FULL (int) FAST (int) }, - { TYPE (INSN_INTE), IDX (INSN_INTE), FULL (inte) FAST (inte) }, - { TYPE (INSN_RETI), IDX (INSN_RETI), FULL (reti) FAST (reti) }, - { TYPE (INSN_BRAD), IDX (INSN_BRAD), FULL (brad) FAST (brad) }, - { TYPE (INSN_BRA), IDX (INSN_BRA), FULL (bra) FAST (bra) }, - { TYPE (INSN_BNOD), IDX (INSN_BNOD), FULL (bnod) FAST (bnod) }, - { TYPE (INSN_BNO), IDX (INSN_BNO), FULL (bno) FAST (bno) }, - { TYPE (INSN_BEQD), IDX (INSN_BEQD), FULL (beqd) FAST (beqd) }, - { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) }, - { TYPE (INSN_BNED), IDX (INSN_BNED), FULL (bned) FAST (bned) }, - { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, - { TYPE (INSN_BCD), IDX (INSN_BCD), FULL (bcd) FAST (bcd) }, - { TYPE (INSN_BC), IDX (INSN_BC), FULL (bc) FAST (bc) }, - { TYPE (INSN_BNCD), IDX (INSN_BNCD), FULL (bncd) FAST (bncd) }, - { TYPE (INSN_BNC), IDX (INSN_BNC), FULL (bnc) FAST (bnc) }, - { TYPE (INSN_BND), IDX (INSN_BND), FULL (bnd) FAST (bnd) }, - { TYPE (INSN_BN), IDX (INSN_BN), FULL (bn) FAST (bn) }, - { TYPE (INSN_BPD), IDX (INSN_BPD), FULL (bpd) FAST (bpd) }, - { TYPE (INSN_BP), IDX (INSN_BP), FULL (bp) FAST (bp) }, - { TYPE (INSN_BVD), IDX (INSN_BVD), FULL (bvd) FAST (bvd) }, - { TYPE (INSN_BV), IDX (INSN_BV), FULL (bv) FAST (bv) }, - { TYPE (INSN_BNVD), IDX (INSN_BNVD), FULL (bnvd) FAST (bnvd) }, - { TYPE (INSN_BNV), IDX (INSN_BNV), FULL (bnv) FAST (bnv) }, - { TYPE (INSN_BLTD), IDX (INSN_BLTD), FULL (bltd) FAST (bltd) }, - { TYPE (INSN_BLT), IDX (INSN_BLT), FULL (blt) FAST (blt) }, - { TYPE (INSN_BGED), IDX (INSN_BGED), FULL (bged) FAST (bged) }, - { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, - { TYPE (INSN_BLED), IDX (INSN_BLED), FULL (bled) FAST (bled) }, - { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, - { TYPE (INSN_BGTD), IDX (INSN_BGTD), FULL (bgtd) FAST (bgtd) }, - { TYPE (INSN_BGT), IDX (INSN_BGT), FULL (bgt) FAST (bgt) }, - { TYPE (INSN_BLSD), IDX (INSN_BLSD), FULL (blsd) FAST (blsd) }, - { TYPE (INSN_BLS), IDX (INSN_BLS), FULL (bls) FAST (bls) }, - { TYPE (INSN_BHID), IDX (INSN_BHID), FULL (bhid) FAST (bhid) }, - { TYPE (INSN_BHI), IDX (INSN_BHI), FULL (bhi) FAST (bhi) }, - { TYPE (INSN_DMOVR13), IDX (INSN_DMOVR13), FULL (dmovr13) FAST (dmovr13) }, - { TYPE (INSN_DMOVR13H), IDX (INSN_DMOVR13H), FULL (dmovr13h) FAST (dmovr13h) }, - { TYPE (INSN_DMOVR13B), IDX (INSN_DMOVR13B), FULL (dmovr13b) FAST (dmovr13b) }, - { TYPE (INSN_DMOVR13PI), IDX (INSN_DMOVR13PI), FULL (dmovr13pi) FAST (dmovr13pi) }, - { TYPE (INSN_DMOVR13PIH), IDX (INSN_DMOVR13PIH), FULL (dmovr13pih) FAST (dmovr13pih) }, - { TYPE (INSN_DMOVR13PIB), IDX (INSN_DMOVR13PIB), FULL (dmovr13pib) FAST (dmovr13pib) }, - { TYPE (INSN_DMOVR15PI), IDX (INSN_DMOVR15PI), FULL (dmovr15pi) FAST (dmovr15pi) }, - { TYPE (INSN_DMOV2R13), IDX (INSN_DMOV2R13), FULL (dmov2r13) FAST (dmov2r13) }, - { TYPE (INSN_DMOV2R13H), IDX (INSN_DMOV2R13H), FULL (dmov2r13h) FAST (dmov2r13h) }, - { TYPE (INSN_DMOV2R13B), IDX (INSN_DMOV2R13B), FULL (dmov2r13b) FAST (dmov2r13b) }, - { TYPE (INSN_DMOV2R13PI), IDX (INSN_DMOV2R13PI), FULL (dmov2r13pi) FAST (dmov2r13pi) }, - { TYPE (INSN_DMOV2R13PIH), IDX (INSN_DMOV2R13PIH), FULL (dmov2r13pih) FAST (dmov2r13pih) }, - { TYPE (INSN_DMOV2R13PIB), IDX (INSN_DMOV2R13PIB), FULL (dmov2r13pib) FAST (dmov2r13pib) }, - { TYPE (INSN_DMOV2R15PD), IDX (INSN_DMOV2R15PD), FULL (dmov2r15pd) FAST (dmov2r15pd) }, - { TYPE (INSN_LDRES), IDX (INSN_LDRES), FULL (ldres) FAST (ldres) }, - { TYPE (INSN_STRES), IDX (INSN_STRES), FULL (stres) FAST (stres) }, - { TYPE (INSN_COPOP), IDX (INSN_COPOP), FULL (copop) FAST (copop) }, - { TYPE (INSN_COPLD), IDX (INSN_COPLD), FULL (copld) FAST (copld) }, - { TYPE (INSN_COPST), IDX (INSN_COPST), FULL (copst) FAST (copst) }, - { TYPE (INSN_COPSV), IDX (INSN_COPSV), FULL (copsv) FAST (copsv) }, - { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) }, - { TYPE (INSN_ANDCCR), IDX (INSN_ANDCCR), FULL (andccr) FAST (andccr) }, - { TYPE (INSN_ORCCR), IDX (INSN_ORCCR), FULL (orccr) FAST (orccr) }, - { TYPE (INSN_STILM), IDX (INSN_STILM), FULL (stilm) FAST (stilm) }, - { TYPE (INSN_ADDSP), IDX (INSN_ADDSP), FULL (addsp) FAST (addsp) }, - { TYPE (INSN_EXTSB), IDX (INSN_EXTSB), FULL (extsb) FAST (extsb) }, - { TYPE (INSN_EXTUB), IDX (INSN_EXTUB), FULL (extub) FAST (extub) }, - { TYPE (INSN_EXTSH), IDX (INSN_EXTSH), FULL (extsh) FAST (extsh) }, - { TYPE (INSN_EXTUH), IDX (INSN_EXTUH), FULL (extuh) FAST (extuh) }, - { TYPE (INSN_LDM0), IDX (INSN_LDM0), FULL (ldm0) FAST (ldm0) }, - { TYPE (INSN_LDM1), IDX (INSN_LDM1), FULL (ldm1) FAST (ldm1) }, - { TYPE (INSN_STM0), IDX (INSN_STM0), FULL (stm0) FAST (stm0) }, - { TYPE (INSN_STM1), IDX (INSN_STM1), FULL (stm1) FAST (stm1) }, - { TYPE (INSN_ENTER), IDX (INSN_ENTER), FULL (enter) FAST (enter) }, - { TYPE (INSN_LEAVE), IDX (INSN_LEAVE), FULL (leave) FAST (leave) }, - { TYPE (INSN_XCHB), IDX (INSN_XCHB), FULL (xchb) FAST (xchb) }, + { VIRTUAL_INSN_X_INVALID, FR30BF_INSN_X_INVALID, FR30BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, FR30BF_INSN_X_AFTER, FR30BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, FR30BF_INSN_X_BEFORE, FR30BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, FR30BF_INSN_X_CTI_CHAIN, FR30BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, FR30BF_INSN_X_CHAIN, FR30BF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, FR30BF_INSN_X_BEGIN, FR30BF_SFMT_EMPTY }, + { FR30_INSN_ADD, FR30BF_INSN_ADD, FR30BF_SFMT_ADD }, + { FR30_INSN_ADDI, FR30BF_INSN_ADDI, FR30BF_SFMT_ADDI }, + { FR30_INSN_ADD2, FR30BF_INSN_ADD2, FR30BF_SFMT_ADD2 }, + { FR30_INSN_ADDC, FR30BF_INSN_ADDC, FR30BF_SFMT_ADDC }, + { FR30_INSN_ADDN, FR30BF_INSN_ADDN, FR30BF_SFMT_ADDN }, + { FR30_INSN_ADDNI, FR30BF_INSN_ADDNI, FR30BF_SFMT_ADDNI }, + { FR30_INSN_ADDN2, FR30BF_INSN_ADDN2, FR30BF_SFMT_ADDN2 }, + { FR30_INSN_SUB, FR30BF_INSN_SUB, FR30BF_SFMT_ADD }, + { FR30_INSN_SUBC, FR30BF_INSN_SUBC, FR30BF_SFMT_ADDC }, + { FR30_INSN_SUBN, FR30BF_INSN_SUBN, FR30BF_SFMT_ADDN }, + { FR30_INSN_CMP, FR30BF_INSN_CMP, FR30BF_SFMT_CMP }, + { FR30_INSN_CMPI, FR30BF_INSN_CMPI, FR30BF_SFMT_CMPI }, + { FR30_INSN_CMP2, FR30BF_INSN_CMP2, FR30BF_SFMT_CMP2 }, + { FR30_INSN_AND, FR30BF_INSN_AND, FR30BF_SFMT_AND }, + { FR30_INSN_OR, FR30BF_INSN_OR, FR30BF_SFMT_AND }, + { FR30_INSN_EOR, FR30BF_INSN_EOR, FR30BF_SFMT_AND }, + { FR30_INSN_ANDM, FR30BF_INSN_ANDM, FR30BF_SFMT_ANDM }, + { FR30_INSN_ANDH, FR30BF_INSN_ANDH, FR30BF_SFMT_ANDH }, + { FR30_INSN_ANDB, FR30BF_INSN_ANDB, FR30BF_SFMT_ANDB }, + { FR30_INSN_ORM, FR30BF_INSN_ORM, FR30BF_SFMT_ANDM }, + { FR30_INSN_ORH, FR30BF_INSN_ORH, FR30BF_SFMT_ANDH }, + { FR30_INSN_ORB, FR30BF_INSN_ORB, FR30BF_SFMT_ANDB }, + { FR30_INSN_EORM, FR30BF_INSN_EORM, FR30BF_SFMT_ANDM }, + { FR30_INSN_EORH, FR30BF_INSN_EORH, FR30BF_SFMT_ANDH }, + { FR30_INSN_EORB, FR30BF_INSN_EORB, FR30BF_SFMT_ANDB }, + { FR30_INSN_BANDL, FR30BF_INSN_BANDL, FR30BF_SFMT_BANDL }, + { FR30_INSN_BORL, FR30BF_INSN_BORL, FR30BF_SFMT_BANDL }, + { FR30_INSN_BEORL, FR30BF_INSN_BEORL, FR30BF_SFMT_BANDL }, + { FR30_INSN_BANDH, FR30BF_INSN_BANDH, FR30BF_SFMT_BANDL }, + { FR30_INSN_BORH, FR30BF_INSN_BORH, FR30BF_SFMT_BANDL }, + { FR30_INSN_BEORH, FR30BF_INSN_BEORH, FR30BF_SFMT_BANDL }, + { FR30_INSN_BTSTL, FR30BF_INSN_BTSTL, FR30BF_SFMT_BTSTL }, + { FR30_INSN_BTSTH, FR30BF_INSN_BTSTH, FR30BF_SFMT_BTSTL }, + { FR30_INSN_MUL, FR30BF_INSN_MUL, FR30BF_SFMT_MUL }, + { FR30_INSN_MULU, FR30BF_INSN_MULU, FR30BF_SFMT_MULU }, + { FR30_INSN_MULH, FR30BF_INSN_MULH, FR30BF_SFMT_MULH }, + { FR30_INSN_MULUH, FR30BF_INSN_MULUH, FR30BF_SFMT_MULH }, + { FR30_INSN_DIV0S, FR30BF_INSN_DIV0S, FR30BF_SFMT_DIV0S }, + { FR30_INSN_DIV0U, FR30BF_INSN_DIV0U, FR30BF_SFMT_DIV0U }, + { FR30_INSN_DIV1, FR30BF_INSN_DIV1, FR30BF_SFMT_DIV1 }, + { FR30_INSN_DIV2, FR30BF_INSN_DIV2, FR30BF_SFMT_DIV2 }, + { FR30_INSN_DIV3, FR30BF_INSN_DIV3, FR30BF_SFMT_DIV3 }, + { FR30_INSN_DIV4S, FR30BF_INSN_DIV4S, FR30BF_SFMT_DIV4S }, + { FR30_INSN_LSL, FR30BF_INSN_LSL, FR30BF_SFMT_LSL }, + { FR30_INSN_LSLI, FR30BF_INSN_LSLI, FR30BF_SFMT_LSLI }, + { FR30_INSN_LSL2, FR30BF_INSN_LSL2, FR30BF_SFMT_LSLI }, + { FR30_INSN_LSR, FR30BF_INSN_LSR, FR30BF_SFMT_LSL }, + { FR30_INSN_LSRI, FR30BF_INSN_LSRI, FR30BF_SFMT_LSLI }, + { FR30_INSN_LSR2, FR30BF_INSN_LSR2, FR30BF_SFMT_LSLI }, + { FR30_INSN_ASR, FR30BF_INSN_ASR, FR30BF_SFMT_LSL }, + { FR30_INSN_ASRI, FR30BF_INSN_ASRI, FR30BF_SFMT_LSLI }, + { FR30_INSN_ASR2, FR30BF_INSN_ASR2, FR30BF_SFMT_LSLI }, + { FR30_INSN_LDI8, FR30BF_INSN_LDI8, FR30BF_SFMT_LDI8 }, + { FR30_INSN_LDI20, FR30BF_INSN_LDI20, FR30BF_SFMT_LDI20 }, + { FR30_INSN_LDI32, FR30BF_INSN_LDI32, FR30BF_SFMT_LDI32 }, + { FR30_INSN_LD, FR30BF_INSN_LD, FR30BF_SFMT_LD }, + { FR30_INSN_LDUH, FR30BF_INSN_LDUH, FR30BF_SFMT_LD }, + { FR30_INSN_LDUB, FR30BF_INSN_LDUB, FR30BF_SFMT_LD }, + { FR30_INSN_LDR13, FR30BF_INSN_LDR13, FR30BF_SFMT_LDR13 }, + { FR30_INSN_LDR13UH, FR30BF_INSN_LDR13UH, FR30BF_SFMT_LDR13 }, + { FR30_INSN_LDR13UB, FR30BF_INSN_LDR13UB, FR30BF_SFMT_LDR13 }, + { FR30_INSN_LDR14, FR30BF_INSN_LDR14, FR30BF_SFMT_LDR14 }, + { FR30_INSN_LDR14UH, FR30BF_INSN_LDR14UH, FR30BF_SFMT_LDR14UH }, + { FR30_INSN_LDR14UB, FR30BF_INSN_LDR14UB, FR30BF_SFMT_LDR14UB }, + { FR30_INSN_LDR15, FR30BF_INSN_LDR15, FR30BF_SFMT_LDR15 }, + { FR30_INSN_LDR15GR, FR30BF_INSN_LDR15GR, FR30BF_SFMT_LDR15GR }, + { FR30_INSN_LDR15DR, FR30BF_INSN_LDR15DR, FR30BF_SFMT_LDR15DR }, + { FR30_INSN_LDR15PS, FR30BF_INSN_LDR15PS, FR30BF_SFMT_LDR15PS }, + { FR30_INSN_ST, FR30BF_INSN_ST, FR30BF_SFMT_ST }, + { FR30_INSN_STH, FR30BF_INSN_STH, FR30BF_SFMT_ST }, + { FR30_INSN_STB, FR30BF_INSN_STB, FR30BF_SFMT_ST }, + { FR30_INSN_STR13, FR30BF_INSN_STR13, FR30BF_SFMT_STR13 }, + { FR30_INSN_STR13H, FR30BF_INSN_STR13H, FR30BF_SFMT_STR13 }, + { FR30_INSN_STR13B, FR30BF_INSN_STR13B, FR30BF_SFMT_STR13 }, + { FR30_INSN_STR14, FR30BF_INSN_STR14, FR30BF_SFMT_STR14 }, + { FR30_INSN_STR14H, FR30BF_INSN_STR14H, FR30BF_SFMT_STR14H }, + { FR30_INSN_STR14B, FR30BF_INSN_STR14B, FR30BF_SFMT_STR14B }, + { FR30_INSN_STR15, FR30BF_INSN_STR15, FR30BF_SFMT_STR15 }, + { FR30_INSN_STR15GR, FR30BF_INSN_STR15GR, FR30BF_SFMT_STR15GR }, + { FR30_INSN_STR15DR, FR30BF_INSN_STR15DR, FR30BF_SFMT_STR15DR }, + { FR30_INSN_STR15PS, FR30BF_INSN_STR15PS, FR30BF_SFMT_STR15PS }, + { FR30_INSN_MOV, FR30BF_INSN_MOV, FR30BF_SFMT_MOV }, + { FR30_INSN_MOVDR, FR30BF_INSN_MOVDR, FR30BF_SFMT_MOVDR }, + { FR30_INSN_MOVPS, FR30BF_INSN_MOVPS, FR30BF_SFMT_MOVPS }, + { FR30_INSN_MOV2DR, FR30BF_INSN_MOV2DR, FR30BF_SFMT_MOV2DR }, + { FR30_INSN_MOV2PS, FR30BF_INSN_MOV2PS, FR30BF_SFMT_MOV2PS }, + { FR30_INSN_JMP, FR30BF_INSN_JMP, FR30BF_SFMT_JMP }, + { FR30_INSN_JMPD, FR30BF_INSN_JMPD, FR30BF_SFMT_JMP }, + { FR30_INSN_CALLR, FR30BF_INSN_CALLR, FR30BF_SFMT_CALLR }, + { FR30_INSN_CALLRD, FR30BF_INSN_CALLRD, FR30BF_SFMT_CALLR }, + { FR30_INSN_CALL, FR30BF_INSN_CALL, FR30BF_SFMT_CALL }, + { FR30_INSN_CALLD, FR30BF_INSN_CALLD, FR30BF_SFMT_CALL }, + { FR30_INSN_RET, FR30BF_INSN_RET, FR30BF_SFMT_RET }, + { FR30_INSN_RET_D, FR30BF_INSN_RET_D, FR30BF_SFMT_RET }, + { FR30_INSN_INT, FR30BF_INSN_INT, FR30BF_SFMT_INT }, + { FR30_INSN_INTE, FR30BF_INSN_INTE, FR30BF_SFMT_INTE }, + { FR30_INSN_RETI, FR30BF_INSN_RETI, FR30BF_SFMT_RETI }, + { FR30_INSN_BRAD, FR30BF_INSN_BRAD, FR30BF_SFMT_BRAD }, + { FR30_INSN_BRA, FR30BF_INSN_BRA, FR30BF_SFMT_BRAD }, + { FR30_INSN_BNOD, FR30BF_INSN_BNOD, FR30BF_SFMT_BNOD }, + { FR30_INSN_BNO, FR30BF_INSN_BNO, FR30BF_SFMT_BNOD }, + { FR30_INSN_BEQD, FR30BF_INSN_BEQD, FR30BF_SFMT_BEQD }, + { FR30_INSN_BEQ, FR30BF_INSN_BEQ, FR30BF_SFMT_BEQD }, + { FR30_INSN_BNED, FR30BF_INSN_BNED, FR30BF_SFMT_BEQD }, + { FR30_INSN_BNE, FR30BF_INSN_BNE, FR30BF_SFMT_BEQD }, + { FR30_INSN_BCD, FR30BF_INSN_BCD, FR30BF_SFMT_BCD }, + { FR30_INSN_BC, FR30BF_INSN_BC, FR30BF_SFMT_BCD }, + { FR30_INSN_BNCD, FR30BF_INSN_BNCD, FR30BF_SFMT_BCD }, + { FR30_INSN_BNC, FR30BF_INSN_BNC, FR30BF_SFMT_BCD }, + { FR30_INSN_BND, FR30BF_INSN_BND, FR30BF_SFMT_BND }, + { FR30_INSN_BN, FR30BF_INSN_BN, FR30BF_SFMT_BND }, + { FR30_INSN_BPD, FR30BF_INSN_BPD, FR30BF_SFMT_BND }, + { FR30_INSN_BP, FR30BF_INSN_BP, FR30BF_SFMT_BND }, + { FR30_INSN_BVD, FR30BF_INSN_BVD, FR30BF_SFMT_BVD }, + { FR30_INSN_BV, FR30BF_INSN_BV, FR30BF_SFMT_BVD }, + { FR30_INSN_BNVD, FR30BF_INSN_BNVD, FR30BF_SFMT_BVD }, + { FR30_INSN_BNV, FR30BF_INSN_BNV, FR30BF_SFMT_BVD }, + { FR30_INSN_BLTD, FR30BF_INSN_BLTD, FR30BF_SFMT_BLTD }, + { FR30_INSN_BLT, FR30BF_INSN_BLT, FR30BF_SFMT_BLTD }, + { FR30_INSN_BGED, FR30BF_INSN_BGED, FR30BF_SFMT_BLTD }, + { FR30_INSN_BGE, FR30BF_INSN_BGE, FR30BF_SFMT_BLTD }, + { FR30_INSN_BLED, FR30BF_INSN_BLED, FR30BF_SFMT_BLED }, + { FR30_INSN_BLE, FR30BF_INSN_BLE, FR30BF_SFMT_BLED }, + { FR30_INSN_BGTD, FR30BF_INSN_BGTD, FR30BF_SFMT_BLED }, + { FR30_INSN_BGT, FR30BF_INSN_BGT, FR30BF_SFMT_BLED }, + { FR30_INSN_BLSD, FR30BF_INSN_BLSD, FR30BF_SFMT_BLSD }, + { FR30_INSN_BLS, FR30BF_INSN_BLS, FR30BF_SFMT_BLSD }, + { FR30_INSN_BHID, FR30BF_INSN_BHID, FR30BF_SFMT_BLSD }, + { FR30_INSN_BHI, FR30BF_INSN_BHI, FR30BF_SFMT_BLSD }, + { FR30_INSN_DMOVR13, FR30BF_INSN_DMOVR13, FR30BF_SFMT_DMOVR13 }, + { FR30_INSN_DMOVR13H, FR30BF_INSN_DMOVR13H, FR30BF_SFMT_DMOVR13H }, + { FR30_INSN_DMOVR13B, FR30BF_INSN_DMOVR13B, FR30BF_SFMT_DMOVR13B }, + { FR30_INSN_DMOVR13PI, FR30BF_INSN_DMOVR13PI, FR30BF_SFMT_DMOVR13PI }, + { FR30_INSN_DMOVR13PIH, FR30BF_INSN_DMOVR13PIH, FR30BF_SFMT_DMOVR13PIH }, + { FR30_INSN_DMOVR13PIB, FR30BF_INSN_DMOVR13PIB, FR30BF_SFMT_DMOVR13PIB }, + { FR30_INSN_DMOVR15PI, FR30BF_INSN_DMOVR15PI, FR30BF_SFMT_DMOVR15PI }, + { FR30_INSN_DMOV2R13, FR30BF_INSN_DMOV2R13, FR30BF_SFMT_DMOV2R13 }, + { FR30_INSN_DMOV2R13H, FR30BF_INSN_DMOV2R13H, FR30BF_SFMT_DMOV2R13H }, + { FR30_INSN_DMOV2R13B, FR30BF_INSN_DMOV2R13B, FR30BF_SFMT_DMOV2R13B }, + { FR30_INSN_DMOV2R13PI, FR30BF_INSN_DMOV2R13PI, FR30BF_SFMT_DMOV2R13PI }, + { FR30_INSN_DMOV2R13PIH, FR30BF_INSN_DMOV2R13PIH, FR30BF_SFMT_DMOV2R13PIH }, + { FR30_INSN_DMOV2R13PIB, FR30BF_INSN_DMOV2R13PIB, FR30BF_SFMT_DMOV2R13PIB }, + { FR30_INSN_DMOV2R15PD, FR30BF_INSN_DMOV2R15PD, FR30BF_SFMT_DMOV2R15PD }, + { FR30_INSN_LDRES, FR30BF_INSN_LDRES, FR30BF_SFMT_LDRES }, + { FR30_INSN_STRES, FR30BF_INSN_STRES, FR30BF_SFMT_LDRES }, + { FR30_INSN_COPOP, FR30BF_INSN_COPOP, FR30BF_SFMT_COPOP }, + { FR30_INSN_COPLD, FR30BF_INSN_COPLD, FR30BF_SFMT_COPOP }, + { FR30_INSN_COPST, FR30BF_INSN_COPST, FR30BF_SFMT_COPOP }, + { FR30_INSN_COPSV, FR30BF_INSN_COPSV, FR30BF_SFMT_COPOP }, + { FR30_INSN_NOP, FR30BF_INSN_NOP, FR30BF_SFMT_BNOD }, + { FR30_INSN_ANDCCR, FR30BF_INSN_ANDCCR, FR30BF_SFMT_ANDCCR }, + { FR30_INSN_ORCCR, FR30BF_INSN_ORCCR, FR30BF_SFMT_ANDCCR }, + { FR30_INSN_STILM, FR30BF_INSN_STILM, FR30BF_SFMT_STILM }, + { FR30_INSN_ADDSP, FR30BF_INSN_ADDSP, FR30BF_SFMT_ADDSP }, + { FR30_INSN_EXTSB, FR30BF_INSN_EXTSB, FR30BF_SFMT_EXTSB }, + { FR30_INSN_EXTUB, FR30BF_INSN_EXTUB, FR30BF_SFMT_EXTUB }, + { FR30_INSN_EXTSH, FR30BF_INSN_EXTSH, FR30BF_SFMT_EXTSH }, + { FR30_INSN_EXTUH, FR30BF_INSN_EXTUH, FR30BF_SFMT_EXTUH }, + { FR30_INSN_LDM0, FR30BF_INSN_LDM0, FR30BF_SFMT_LDM0 }, + { FR30_INSN_LDM1, FR30BF_INSN_LDM1, FR30BF_SFMT_LDM1 }, + { FR30_INSN_STM0, FR30BF_INSN_STM0, FR30BF_SFMT_STM0 }, + { FR30_INSN_STM1, FR30BF_INSN_STM1, FR30BF_SFMT_STM1 }, + { FR30_INSN_ENTER, FR30BF_INSN_ENTER, FR30BF_SFMT_ENTER }, + { FR30_INSN_LEAVE, FR30BF_INSN_LEAVE, FR30BF_SFMT_LEAVE }, + { FR30_INSN_XCHB, FR30BF_INSN_XCHB, FR30BF_SFMT_XCHB }, }; -static const struct insn_sem fr30bf_insn_sem_invalid = -{ - VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) +static const struct insn_sem fr30bf_insn_sem_invalid = { + VIRTUAL_INSN_X_INVALID, FR30BF_INSN_X_INVALID, FR30BF_SFMT_EMPTY }; -#undef FMT -#undef FULL -#undef FAST -#undef IDX -#undef TYPE - /* Initialize an IDESC from the compile-time computable parts. */ static INLINE void @@ -255,6 +225,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; id->num = t->index; + id->sfmt = t->sfmt; if ((int) t->type <= 0) id->idata = & cgen_virtual_insn_table[- (int) t->type]; else @@ -262,12 +233,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) id->attrs = CGEN_INSN_ATTRS (id->idata); /* Oh my god, a magic number. */ id->length = CGEN_INSN_BITSIZE (id->idata) / 8; -#if ! WITH_SEM_SWITCH_FULL - id->sem_full = t->sem_full; -#endif -#if WITH_FAST && ! WITH_SEM_SWITCH_FAST - id->sem_fast = t->sem_fast; -#endif + #if WITH_PROFILE_MODEL_P id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; { @@ -275,6 +241,8 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) SIM_ASSERT (t->index == id->timing->num); } #endif + + /* Semantic pointers are initialized elsewhere. */ } /* Initialize the instruction descriptor table. */ @@ -322,60 +290,60 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 8) & (255 << 0))); switch (val) { - case 0 : itype = FR30BF_INSN_LDR13; goto extract_fmt_ldr13; - case 1 : itype = FR30BF_INSN_LDR13UH; goto extract_fmt_ldr13; - case 2 : itype = FR30BF_INSN_LDR13UB; goto extract_fmt_ldr13; - case 3 : itype = FR30BF_INSN_LDR15; goto extract_fmt_ldr15; - case 4 : itype = FR30BF_INSN_LD; goto extract_fmt_ld; - case 5 : itype = FR30BF_INSN_LDUH; goto extract_fmt_ld; - case 6 : itype = FR30BF_INSN_LDUB; goto extract_fmt_ld; + case 0 : itype = FR30BF_INSN_LDR13; goto extract_sfmt_ldr13; + case 1 : itype = FR30BF_INSN_LDR13UH; goto extract_sfmt_ldr13; + case 2 : itype = FR30BF_INSN_LDR13UB; goto extract_sfmt_ldr13; + case 3 : itype = FR30BF_INSN_LDR15; goto extract_sfmt_ldr15; + case 4 : itype = FR30BF_INSN_LD; goto extract_sfmt_ld; + case 5 : itype = FR30BF_INSN_LDUH; goto extract_sfmt_ld; + case 6 : itype = FR30BF_INSN_LDUB; goto extract_sfmt_ld; case 7 : { unsigned int val = (((insn >> 4) & (15 << 0))); switch (val) { - case 0 : itype = FR30BF_INSN_LDR15GR; goto extract_fmt_ldr15gr; - case 1 : itype = FR30BF_INSN_MOV2PS; goto extract_fmt_mov2ps; - case 8 : itype = FR30BF_INSN_LDR15DR; goto extract_fmt_ldr15dr; - case 9 : itype = FR30BF_INSN_LDR15PS; goto extract_fmt_ldr15ps; - default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = FR30BF_INSN_LDR15GR; goto extract_sfmt_ldr15gr; + case 1 : itype = FR30BF_INSN_MOV2PS; goto extract_sfmt_mov2ps; + case 8 : itype = FR30BF_INSN_LDR15DR; goto extract_sfmt_ldr15dr; + case 9 : itype = FR30BF_INSN_LDR15PS; goto extract_sfmt_ldr15ps; + default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 8 : itype = FR30BF_INSN_DMOV2R13; goto extract_fmt_dmov2r13; - case 9 : itype = FR30BF_INSN_DMOV2R13H; goto extract_fmt_dmov2r13h; - case 10 : itype = FR30BF_INSN_DMOV2R13B; goto extract_fmt_dmov2r13b; - case 11 : itype = FR30BF_INSN_DMOV2R15PD; goto extract_fmt_dmov2r15pd; - case 12 : itype = FR30BF_INSN_DMOV2R13PI; goto extract_fmt_dmov2r13pi; - case 13 : itype = FR30BF_INSN_DMOV2R13PIH; goto extract_fmt_dmov2r13pih; - case 14 : itype = FR30BF_INSN_DMOV2R13PIB; goto extract_fmt_dmov2r13pib; - case 15 : itype = FR30BF_INSN_ENTER; goto extract_fmt_enter; - case 16 : itype = FR30BF_INSN_STR13; goto extract_fmt_str13; - case 17 : itype = FR30BF_INSN_STR13H; goto extract_fmt_str13; - case 18 : itype = FR30BF_INSN_STR13B; goto extract_fmt_str13; - case 19 : itype = FR30BF_INSN_STR15; goto extract_fmt_str15; - case 20 : itype = FR30BF_INSN_ST; goto extract_fmt_st; - case 21 : itype = FR30BF_INSN_STH; goto extract_fmt_st; - case 22 : itype = FR30BF_INSN_STB; goto extract_fmt_st; + case 8 : itype = FR30BF_INSN_DMOV2R13; goto extract_sfmt_dmov2r13; + case 9 : itype = FR30BF_INSN_DMOV2R13H; goto extract_sfmt_dmov2r13h; + case 10 : itype = FR30BF_INSN_DMOV2R13B; goto extract_sfmt_dmov2r13b; + case 11 : itype = FR30BF_INSN_DMOV2R15PD; goto extract_sfmt_dmov2r15pd; + case 12 : itype = FR30BF_INSN_DMOV2R13PI; goto extract_sfmt_dmov2r13pi; + case 13 : itype = FR30BF_INSN_DMOV2R13PIH; goto extract_sfmt_dmov2r13pih; + case 14 : itype = FR30BF_INSN_DMOV2R13PIB; goto extract_sfmt_dmov2r13pib; + case 15 : itype = FR30BF_INSN_ENTER; goto extract_sfmt_enter; + case 16 : itype = FR30BF_INSN_STR13; goto extract_sfmt_str13; + case 17 : itype = FR30BF_INSN_STR13H; goto extract_sfmt_str13; + case 18 : itype = FR30BF_INSN_STR13B; goto extract_sfmt_str13; + case 19 : itype = FR30BF_INSN_STR15; goto extract_sfmt_str15; + case 20 : itype = FR30BF_INSN_ST; goto extract_sfmt_st; + case 21 : itype = FR30BF_INSN_STH; goto extract_sfmt_st; + case 22 : itype = FR30BF_INSN_STB; goto extract_sfmt_st; case 23 : { unsigned int val = (((insn >> 4) & (15 << 0))); switch (val) { - case 0 : itype = FR30BF_INSN_STR15GR; goto extract_fmt_str15gr; - case 1 : itype = FR30BF_INSN_MOVPS; goto extract_fmt_movps; - case 8 : itype = FR30BF_INSN_STR15DR; goto extract_fmt_str15dr; - case 9 : itype = FR30BF_INSN_STR15PS; goto extract_fmt_str15ps; - default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = FR30BF_INSN_STR15GR; goto extract_sfmt_str15gr; + case 1 : itype = FR30BF_INSN_MOVPS; goto extract_sfmt_movps; + case 8 : itype = FR30BF_INSN_STR15DR; goto extract_sfmt_str15dr; + case 9 : itype = FR30BF_INSN_STR15PS; goto extract_sfmt_str15ps; + default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 24 : itype = FR30BF_INSN_DMOVR13; goto extract_fmt_dmovr13; - case 25 : itype = FR30BF_INSN_DMOVR13H; goto extract_fmt_dmovr13h; - case 26 : itype = FR30BF_INSN_DMOVR13B; goto extract_fmt_dmovr13b; - case 27 : itype = FR30BF_INSN_DMOVR15PI; goto extract_fmt_dmovr15pi; - case 28 : itype = FR30BF_INSN_DMOVR13PI; goto extract_fmt_dmovr13pi; - case 29 : itype = FR30BF_INSN_DMOVR13PIH; goto extract_fmt_dmovr13pih; - case 30 : itype = FR30BF_INSN_DMOVR13PIB; goto extract_fmt_dmovr13pib; - case 31 : itype = FR30BF_INSN_INT; goto extract_fmt_int; + case 24 : itype = FR30BF_INSN_DMOVR13; goto extract_sfmt_dmovr13; + case 25 : itype = FR30BF_INSN_DMOVR13H; goto extract_sfmt_dmovr13h; + case 26 : itype = FR30BF_INSN_DMOVR13B; goto extract_sfmt_dmovr13b; + case 27 : itype = FR30BF_INSN_DMOVR15PI; goto extract_sfmt_dmovr15pi; + case 28 : itype = FR30BF_INSN_DMOVR13PI; goto extract_sfmt_dmovr13pi; + case 29 : itype = FR30BF_INSN_DMOVR13PIH; goto extract_sfmt_dmovr13pih; + case 30 : itype = FR30BF_INSN_DMOVR13PIB; goto extract_sfmt_dmovr13pib; + case 31 : itype = FR30BF_INSN_INT; goto extract_sfmt_int; case 32 : /* fall through */ case 33 : /* fall through */ case 34 : /* fall through */ @@ -391,7 +359,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 44 : /* fall through */ case 45 : /* fall through */ case 46 : /* fall through */ - case 47 : itype = FR30BF_INSN_LDR14; goto extract_fmt_ldr14; + case 47 : itype = FR30BF_INSN_LDR14; goto extract_sfmt_ldr14; case 48 : /* fall through */ case 49 : /* fall through */ case 50 : /* fall through */ @@ -407,7 +375,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 60 : /* fall through */ case 61 : /* fall through */ case 62 : /* fall through */ - case 63 : itype = FR30BF_INSN_STR14; goto extract_fmt_str14; + case 63 : itype = FR30BF_INSN_STR14; goto extract_sfmt_str14; case 64 : /* fall through */ case 65 : /* fall through */ case 66 : /* fall through */ @@ -423,7 +391,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 76 : /* fall through */ case 77 : /* fall through */ case 78 : /* fall through */ - case 79 : itype = FR30BF_INSN_LDR14UH; goto extract_fmt_ldr14uh; + case 79 : itype = FR30BF_INSN_LDR14UH; goto extract_sfmt_ldr14uh; case 80 : /* fall through */ case 81 : /* fall through */ case 82 : /* fall through */ @@ -439,7 +407,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 92 : /* fall through */ case 93 : /* fall through */ case 94 : /* fall through */ - case 95 : itype = FR30BF_INSN_STR14H; goto extract_fmt_str14h; + case 95 : itype = FR30BF_INSN_STR14H; goto extract_sfmt_str14h; case 96 : /* fall through */ case 97 : /* fall through */ case 98 : /* fall through */ @@ -455,7 +423,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 108 : /* fall through */ case 109 : /* fall through */ case 110 : /* fall through */ - case 111 : itype = FR30BF_INSN_LDR14UB; goto extract_fmt_ldr14ub; + case 111 : itype = FR30BF_INSN_LDR14UB; goto extract_sfmt_ldr14ub; case 112 : /* fall through */ case 113 : /* fall through */ case 114 : /* fall through */ @@ -471,109 +439,109 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 124 : /* fall through */ case 125 : /* fall through */ case 126 : /* fall through */ - case 127 : itype = FR30BF_INSN_STR14B; goto extract_fmt_str14b; - case 128 : itype = FR30BF_INSN_BANDL; goto extract_fmt_bandl; - case 129 : itype = FR30BF_INSN_BANDH; goto extract_fmt_bandl; - case 130 : itype = FR30BF_INSN_AND; goto extract_fmt_and; - case 131 : itype = FR30BF_INSN_ANDCCR; goto extract_fmt_andccr; - case 132 : itype = FR30BF_INSN_ANDM; goto extract_fmt_andm; - case 133 : itype = FR30BF_INSN_ANDH; goto extract_fmt_andh; - case 134 : itype = FR30BF_INSN_ANDB; goto extract_fmt_andb; - case 135 : itype = FR30BF_INSN_STILM; goto extract_fmt_stilm; - case 136 : itype = FR30BF_INSN_BTSTL; goto extract_fmt_btstl; - case 137 : itype = FR30BF_INSN_BTSTH; goto extract_fmt_btstl; - case 138 : itype = FR30BF_INSN_XCHB; goto extract_fmt_xchb; - case 139 : itype = FR30BF_INSN_MOV; goto extract_fmt_mov; - case 140 : itype = FR30BF_INSN_LDM0; goto extract_fmt_ldm0; - case 141 : itype = FR30BF_INSN_LDM1; goto extract_fmt_ldm1; - case 142 : itype = FR30BF_INSN_STM0; goto extract_fmt_stm0; - case 143 : itype = FR30BF_INSN_STM1; goto extract_fmt_stm1; - case 144 : itype = FR30BF_INSN_BORL; goto extract_fmt_bandl; - case 145 : itype = FR30BF_INSN_BORH; goto extract_fmt_bandl; - case 146 : itype = FR30BF_INSN_OR; goto extract_fmt_and; - case 147 : itype = FR30BF_INSN_ORCCR; goto extract_fmt_andccr; - case 148 : itype = FR30BF_INSN_ORM; goto extract_fmt_andm; - case 149 : itype = FR30BF_INSN_ORH; goto extract_fmt_andh; - case 150 : itype = FR30BF_INSN_ORB; goto extract_fmt_andb; + case 127 : itype = FR30BF_INSN_STR14B; goto extract_sfmt_str14b; + case 128 : itype = FR30BF_INSN_BANDL; goto extract_sfmt_bandl; + case 129 : itype = FR30BF_INSN_BANDH; goto extract_sfmt_bandl; + case 130 : itype = FR30BF_INSN_AND; goto extract_sfmt_and; + case 131 : itype = FR30BF_INSN_ANDCCR; goto extract_sfmt_andccr; + case 132 : itype = FR30BF_INSN_ANDM; goto extract_sfmt_andm; + case 133 : itype = FR30BF_INSN_ANDH; goto extract_sfmt_andh; + case 134 : itype = FR30BF_INSN_ANDB; goto extract_sfmt_andb; + case 135 : itype = FR30BF_INSN_STILM; goto extract_sfmt_stilm; + case 136 : itype = FR30BF_INSN_BTSTL; goto extract_sfmt_btstl; + case 137 : itype = FR30BF_INSN_BTSTH; goto extract_sfmt_btstl; + case 138 : itype = FR30BF_INSN_XCHB; goto extract_sfmt_xchb; + case 139 : itype = FR30BF_INSN_MOV; goto extract_sfmt_mov; + case 140 : itype = FR30BF_INSN_LDM0; goto extract_sfmt_ldm0; + case 141 : itype = FR30BF_INSN_LDM1; goto extract_sfmt_ldm1; + case 142 : itype = FR30BF_INSN_STM0; goto extract_sfmt_stm0; + case 143 : itype = FR30BF_INSN_STM1; goto extract_sfmt_stm1; + case 144 : itype = FR30BF_INSN_BORL; goto extract_sfmt_bandl; + case 145 : itype = FR30BF_INSN_BORH; goto extract_sfmt_bandl; + case 146 : itype = FR30BF_INSN_OR; goto extract_sfmt_and; + case 147 : itype = FR30BF_INSN_ORCCR; goto extract_sfmt_andccr; + case 148 : itype = FR30BF_INSN_ORM; goto extract_sfmt_andm; + case 149 : itype = FR30BF_INSN_ORH; goto extract_sfmt_andh; + case 150 : itype = FR30BF_INSN_ORB; goto extract_sfmt_andb; case 151 : { unsigned int val = (((insn >> 4) & (15 << 0))); switch (val) { - case 0 : itype = FR30BF_INSN_JMP; goto extract_fmt_jmp; - case 1 : itype = FR30BF_INSN_CALLR; goto extract_fmt_callr; - case 2 : itype = FR30BF_INSN_RET; goto extract_fmt_ret; - case 3 : itype = FR30BF_INSN_RETI; goto extract_fmt_reti; - case 4 : itype = FR30BF_INSN_DIV0S; goto extract_fmt_div0s; - case 5 : itype = FR30BF_INSN_DIV0U; goto extract_fmt_div0u; - case 6 : itype = FR30BF_INSN_DIV1; goto extract_fmt_div1; - case 7 : itype = FR30BF_INSN_DIV2; goto extract_fmt_div2; - case 8 : itype = FR30BF_INSN_EXTSB; goto extract_fmt_extsb; - case 9 : itype = FR30BF_INSN_EXTUB; goto extract_fmt_extub; - case 10 : itype = FR30BF_INSN_EXTSH; goto extract_fmt_extsh; - case 11 : itype = FR30BF_INSN_EXTUH; goto extract_fmt_extuh; - default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = FR30BF_INSN_JMP; goto extract_sfmt_jmp; + case 1 : itype = FR30BF_INSN_CALLR; goto extract_sfmt_callr; + case 2 : itype = FR30BF_INSN_RET; goto extract_sfmt_ret; + case 3 : itype = FR30BF_INSN_RETI; goto extract_sfmt_reti; + case 4 : itype = FR30BF_INSN_DIV0S; goto extract_sfmt_div0s; + case 5 : itype = FR30BF_INSN_DIV0U; goto extract_sfmt_div0u; + case 6 : itype = FR30BF_INSN_DIV1; goto extract_sfmt_div1; + case 7 : itype = FR30BF_INSN_DIV2; goto extract_sfmt_div2; + case 8 : itype = FR30BF_INSN_EXTSB; goto extract_sfmt_extsb; + case 9 : itype = FR30BF_INSN_EXTUB; goto extract_sfmt_extub; + case 10 : itype = FR30BF_INSN_EXTSH; goto extract_sfmt_extsh; + case 11 : itype = FR30BF_INSN_EXTUH; goto extract_sfmt_extuh; + default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 152 : itype = FR30BF_INSN_BEORL; goto extract_fmt_bandl; - case 153 : itype = FR30BF_INSN_BEORH; goto extract_fmt_bandl; - case 154 : itype = FR30BF_INSN_EOR; goto extract_fmt_and; - case 155 : itype = FR30BF_INSN_LDI20; goto extract_fmt_ldi20; - case 156 : itype = FR30BF_INSN_EORM; goto extract_fmt_andm; - case 157 : itype = FR30BF_INSN_EORH; goto extract_fmt_andh; - case 158 : itype = FR30BF_INSN_EORB; goto extract_fmt_andb; + case 152 : itype = FR30BF_INSN_BEORL; goto extract_sfmt_bandl; + case 153 : itype = FR30BF_INSN_BEORH; goto extract_sfmt_bandl; + case 154 : itype = FR30BF_INSN_EOR; goto extract_sfmt_and; + case 155 : itype = FR30BF_INSN_LDI20; goto extract_sfmt_ldi20; + case 156 : itype = FR30BF_INSN_EORM; goto extract_sfmt_andm; + case 157 : itype = FR30BF_INSN_EORH; goto extract_sfmt_andh; + case 158 : itype = FR30BF_INSN_EORB; goto extract_sfmt_andb; case 159 : { unsigned int val = (((insn >> 4) & (15 << 0))); switch (val) { - case 0 : itype = FR30BF_INSN_JMPD; goto extract_fmt_jmp; - case 1 : itype = FR30BF_INSN_CALLRD; goto extract_fmt_callr; - case 2 : itype = FR30BF_INSN_RET_D; goto extract_fmt_ret; - case 3 : itype = FR30BF_INSN_INTE; goto extract_fmt_inte; - case 6 : itype = FR30BF_INSN_DIV3; goto extract_fmt_div3; - case 7 : itype = FR30BF_INSN_DIV4S; goto extract_fmt_div4s; - case 8 : itype = FR30BF_INSN_LDI32; goto extract_fmt_ldi32; - case 9 : itype = FR30BF_INSN_LEAVE; goto extract_fmt_leave; - case 10 : itype = FR30BF_INSN_NOP; goto extract_fmt_bnod; - case 12 : itype = FR30BF_INSN_COPOP; goto extract_fmt_copop; - case 13 : itype = FR30BF_INSN_COPLD; goto extract_fmt_copop; - case 14 : itype = FR30BF_INSN_COPST; goto extract_fmt_copop; - case 15 : itype = FR30BF_INSN_COPSV; goto extract_fmt_copop; - default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = FR30BF_INSN_JMPD; goto extract_sfmt_jmp; + case 1 : itype = FR30BF_INSN_CALLRD; goto extract_sfmt_callr; + case 2 : itype = FR30BF_INSN_RET_D; goto extract_sfmt_ret; + case 3 : itype = FR30BF_INSN_INTE; goto extract_sfmt_inte; + case 6 : itype = FR30BF_INSN_DIV3; goto extract_sfmt_div3; + case 7 : itype = FR30BF_INSN_DIV4S; goto extract_sfmt_div4s; + case 8 : itype = FR30BF_INSN_LDI32; goto extract_sfmt_ldi32; + case 9 : itype = FR30BF_INSN_LEAVE; goto extract_sfmt_leave; + case 10 : itype = FR30BF_INSN_NOP; goto extract_sfmt_bnod; + case 12 : itype = FR30BF_INSN_COPOP; goto extract_sfmt_copop; + case 13 : itype = FR30BF_INSN_COPLD; goto extract_sfmt_copop; + case 14 : itype = FR30BF_INSN_COPST; goto extract_sfmt_copop; + case 15 : itype = FR30BF_INSN_COPSV; goto extract_sfmt_copop; + default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 160 : itype = FR30BF_INSN_ADDNI; goto extract_fmt_addni; - case 161 : itype = FR30BF_INSN_ADDN2; goto extract_fmt_addn2; - case 162 : itype = FR30BF_INSN_ADDN; goto extract_fmt_addn; - case 163 : itype = FR30BF_INSN_ADDSP; goto extract_fmt_addsp; - case 164 : itype = FR30BF_INSN_ADDI; goto extract_fmt_addi; - case 165 : itype = FR30BF_INSN_ADD2; goto extract_fmt_add2; - case 166 : itype = FR30BF_INSN_ADD; goto extract_fmt_add; - case 167 : itype = FR30BF_INSN_ADDC; goto extract_fmt_addc; - case 168 : itype = FR30BF_INSN_CMPI; goto extract_fmt_cmpi; - case 169 : itype = FR30BF_INSN_CMP2; goto extract_fmt_cmp2; - case 170 : itype = FR30BF_INSN_CMP; goto extract_fmt_cmp; - case 171 : itype = FR30BF_INSN_MULU; goto extract_fmt_mulu; - case 172 : itype = FR30BF_INSN_SUB; goto extract_fmt_add; - case 173 : itype = FR30BF_INSN_SUBC; goto extract_fmt_addc; - case 174 : itype = FR30BF_INSN_SUBN; goto extract_fmt_addn; - case 175 : itype = FR30BF_INSN_MUL; goto extract_fmt_mul; - case 176 : itype = FR30BF_INSN_LSRI; goto extract_fmt_lsli; - case 177 : itype = FR30BF_INSN_LSR2; goto extract_fmt_lsli; - case 178 : itype = FR30BF_INSN_LSR; goto extract_fmt_lsl; - case 179 : itype = FR30BF_INSN_MOV2DR; goto extract_fmt_mov2dr; - case 180 : itype = FR30BF_INSN_LSLI; goto extract_fmt_lsli; - case 181 : itype = FR30BF_INSN_LSL2; goto extract_fmt_lsli; - case 182 : itype = FR30BF_INSN_LSL; goto extract_fmt_lsl; - case 183 : itype = FR30BF_INSN_MOVDR; goto extract_fmt_movdr; - case 184 : itype = FR30BF_INSN_ASRI; goto extract_fmt_lsli; - case 185 : itype = FR30BF_INSN_ASR2; goto extract_fmt_lsli; - case 186 : itype = FR30BF_INSN_ASR; goto extract_fmt_lsl; - case 187 : itype = FR30BF_INSN_MULUH; goto extract_fmt_mulh; - case 188 : itype = FR30BF_INSN_LDRES; goto extract_fmt_ldres; - case 189 : itype = FR30BF_INSN_STRES; goto extract_fmt_ldres; - case 191 : itype = FR30BF_INSN_MULH; goto extract_fmt_mulh; + case 160 : itype = FR30BF_INSN_ADDNI; goto extract_sfmt_addni; + case 161 : itype = FR30BF_INSN_ADDN2; goto extract_sfmt_addn2; + case 162 : itype = FR30BF_INSN_ADDN; goto extract_sfmt_addn; + case 163 : itype = FR30BF_INSN_ADDSP; goto extract_sfmt_addsp; + case 164 : itype = FR30BF_INSN_ADDI; goto extract_sfmt_addi; + case 165 : itype = FR30BF_INSN_ADD2; goto extract_sfmt_add2; + case 166 : itype = FR30BF_INSN_ADD; goto extract_sfmt_add; + case 167 : itype = FR30BF_INSN_ADDC; goto extract_sfmt_addc; + case 168 : itype = FR30BF_INSN_CMPI; goto extract_sfmt_cmpi; + case 169 : itype = FR30BF_INSN_CMP2; goto extract_sfmt_cmp2; + case 170 : itype = FR30BF_INSN_CMP; goto extract_sfmt_cmp; + case 171 : itype = FR30BF_INSN_MULU; goto extract_sfmt_mulu; + case 172 : itype = FR30BF_INSN_SUB; goto extract_sfmt_add; + case 173 : itype = FR30BF_INSN_SUBC; goto extract_sfmt_addc; + case 174 : itype = FR30BF_INSN_SUBN; goto extract_sfmt_addn; + case 175 : itype = FR30BF_INSN_MUL; goto extract_sfmt_mul; + case 176 : itype = FR30BF_INSN_LSRI; goto extract_sfmt_lsli; + case 177 : itype = FR30BF_INSN_LSR2; goto extract_sfmt_lsli; + case 178 : itype = FR30BF_INSN_LSR; goto extract_sfmt_lsl; + case 179 : itype = FR30BF_INSN_MOV2DR; goto extract_sfmt_mov2dr; + case 180 : itype = FR30BF_INSN_LSLI; goto extract_sfmt_lsli; + case 181 : itype = FR30BF_INSN_LSL2; goto extract_sfmt_lsli; + case 182 : itype = FR30BF_INSN_LSL; goto extract_sfmt_lsl; + case 183 : itype = FR30BF_INSN_MOVDR; goto extract_sfmt_movdr; + case 184 : itype = FR30BF_INSN_ASRI; goto extract_sfmt_lsli; + case 185 : itype = FR30BF_INSN_ASR2; goto extract_sfmt_lsli; + case 186 : itype = FR30BF_INSN_ASR; goto extract_sfmt_lsl; + case 187 : itype = FR30BF_INSN_MULUH; goto extract_sfmt_mulh; + case 188 : itype = FR30BF_INSN_LDRES; goto extract_sfmt_ldres; + case 189 : itype = FR30BF_INSN_STRES; goto extract_sfmt_ldres; + case 191 : itype = FR30BF_INSN_MULH; goto extract_sfmt_mulh; case 192 : /* fall through */ case 193 : /* fall through */ case 194 : /* fall through */ @@ -589,7 +557,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 204 : /* fall through */ case 205 : /* fall through */ case 206 : /* fall through */ - case 207 : itype = FR30BF_INSN_LDI8; goto extract_fmt_ldi8; + case 207 : itype = FR30BF_INSN_LDI8; goto extract_sfmt_ldi8; case 208 : /* fall through */ case 209 : /* fall through */ case 210 : /* fall through */ @@ -597,7 +565,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 212 : /* fall through */ case 213 : /* fall through */ case 214 : /* fall through */ - case 215 : itype = FR30BF_INSN_CALL; goto extract_fmt_call; + case 215 : itype = FR30BF_INSN_CALL; goto extract_sfmt_call; case 216 : /* fall through */ case 217 : /* fall through */ case 218 : /* fall through */ @@ -605,47 +573,47 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, case 220 : /* fall through */ case 221 : /* fall through */ case 222 : /* fall through */ - case 223 : itype = FR30BF_INSN_CALLD; goto extract_fmt_call; - case 224 : itype = FR30BF_INSN_BRA; goto extract_fmt_brad; - case 225 : itype = FR30BF_INSN_BNO; goto extract_fmt_bnod; - case 226 : itype = FR30BF_INSN_BEQ; goto extract_fmt_beqd; - case 227 : itype = FR30BF_INSN_BNE; goto extract_fmt_beqd; - case 228 : itype = FR30BF_INSN_BC; goto extract_fmt_bcd; - case 229 : itype = FR30BF_INSN_BNC; goto extract_fmt_bcd; - case 230 : itype = FR30BF_INSN_BN; goto extract_fmt_bnd; - case 231 : itype = FR30BF_INSN_BP; goto extract_fmt_bnd; - case 232 : itype = FR30BF_INSN_BV; goto extract_fmt_bvd; - case 233 : itype = FR30BF_INSN_BNV; goto extract_fmt_bvd; - case 234 : itype = FR30BF_INSN_BLT; goto extract_fmt_bltd; - case 235 : itype = FR30BF_INSN_BGE; goto extract_fmt_bltd; - case 236 : itype = FR30BF_INSN_BLE; goto extract_fmt_bled; - case 237 : itype = FR30BF_INSN_BGT; goto extract_fmt_bled; - case 238 : itype = FR30BF_INSN_BLS; goto extract_fmt_blsd; - case 239 : itype = FR30BF_INSN_BHI; goto extract_fmt_blsd; - case 240 : itype = FR30BF_INSN_BRAD; goto extract_fmt_brad; - case 241 : itype = FR30BF_INSN_BNOD; goto extract_fmt_bnod; - case 242 : itype = FR30BF_INSN_BEQD; goto extract_fmt_beqd; - case 243 : itype = FR30BF_INSN_BNED; goto extract_fmt_beqd; - case 244 : itype = FR30BF_INSN_BCD; goto extract_fmt_bcd; - case 245 : itype = FR30BF_INSN_BNCD; goto extract_fmt_bcd; - case 246 : itype = FR30BF_INSN_BND; goto extract_fmt_bnd; - case 247 : itype = FR30BF_INSN_BPD; goto extract_fmt_bnd; - case 248 : itype = FR30BF_INSN_BVD; goto extract_fmt_bvd; - case 249 : itype = FR30BF_INSN_BNVD; goto extract_fmt_bvd; - case 250 : itype = FR30BF_INSN_BLTD; goto extract_fmt_bltd; - case 251 : itype = FR30BF_INSN_BGED; goto extract_fmt_bltd; - case 252 : itype = FR30BF_INSN_BLED; goto extract_fmt_bled; - case 253 : itype = FR30BF_INSN_BGTD; goto extract_fmt_bled; - case 254 : itype = FR30BF_INSN_BLSD; goto extract_fmt_blsd; - case 255 : itype = FR30BF_INSN_BHID; goto extract_fmt_blsd; - default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + case 223 : itype = FR30BF_INSN_CALLD; goto extract_sfmt_call; + case 224 : itype = FR30BF_INSN_BRA; goto extract_sfmt_brad; + case 225 : itype = FR30BF_INSN_BNO; goto extract_sfmt_bnod; + case 226 : itype = FR30BF_INSN_BEQ; goto extract_sfmt_beqd; + case 227 : itype = FR30BF_INSN_BNE; goto extract_sfmt_beqd; + case 228 : itype = FR30BF_INSN_BC; goto extract_sfmt_bcd; + case 229 : itype = FR30BF_INSN_BNC; goto extract_sfmt_bcd; + case 230 : itype = FR30BF_INSN_BN; goto extract_sfmt_bnd; + case 231 : itype = FR30BF_INSN_BP; goto extract_sfmt_bnd; + case 232 : itype = FR30BF_INSN_BV; goto extract_sfmt_bvd; + case 233 : itype = FR30BF_INSN_BNV; goto extract_sfmt_bvd; + case 234 : itype = FR30BF_INSN_BLT; goto extract_sfmt_bltd; + case 235 : itype = FR30BF_INSN_BGE; goto extract_sfmt_bltd; + case 236 : itype = FR30BF_INSN_BLE; goto extract_sfmt_bled; + case 237 : itype = FR30BF_INSN_BGT; goto extract_sfmt_bled; + case 238 : itype = FR30BF_INSN_BLS; goto extract_sfmt_blsd; + case 239 : itype = FR30BF_INSN_BHI; goto extract_sfmt_blsd; + case 240 : itype = FR30BF_INSN_BRAD; goto extract_sfmt_brad; + case 241 : itype = FR30BF_INSN_BNOD; goto extract_sfmt_bnod; + case 242 : itype = FR30BF_INSN_BEQD; goto extract_sfmt_beqd; + case 243 : itype = FR30BF_INSN_BNED; goto extract_sfmt_beqd; + case 244 : itype = FR30BF_INSN_BCD; goto extract_sfmt_bcd; + case 245 : itype = FR30BF_INSN_BNCD; goto extract_sfmt_bcd; + case 246 : itype = FR30BF_INSN_BND; goto extract_sfmt_bnd; + case 247 : itype = FR30BF_INSN_BPD; goto extract_sfmt_bnd; + case 248 : itype = FR30BF_INSN_BVD; goto extract_sfmt_bvd; + case 249 : itype = FR30BF_INSN_BNVD; goto extract_sfmt_bvd; + case 250 : itype = FR30BF_INSN_BLTD; goto extract_sfmt_bltd; + case 251 : itype = FR30BF_INSN_BGED; goto extract_sfmt_bltd; + case 252 : itype = FR30BF_INSN_BLED; goto extract_sfmt_bled; + case 253 : itype = FR30BF_INSN_BGTD; goto extract_sfmt_bled; + case 254 : itype = FR30BF_INSN_BLSD; goto extract_sfmt_blsd; + case 255 : itype = FR30BF_INSN_BHID; goto extract_sfmt_blsd; + default : itype = FR30BF_INSN_X_INVALID; goto extract_sfmt_empty; } } } /* The instruction has been decoded, now extract the fields. */ - extract_fmt_empty: + extract_sfmt_empty: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; @@ -653,17 +621,17 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); #undef FLD return idesc; } - extract_fmt_add: + extract_sfmt_add: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f UINT f_Rj; UINT f_Ri; @@ -673,7 +641,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -688,11 +656,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addi: + extract_sfmt_addi: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f UINT f_u4; UINT f_Ri; @@ -702,7 +670,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_u4) = f_u4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -716,11 +684,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_add2: + extract_sfmt_add2: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_add2.f +#define FLD(f) abuf->fields.sfmt_add2.f SI f_m4; UINT f_Ri; @@ -730,7 +698,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_m4) = f_m4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -744,11 +712,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addc: + extract_sfmt_addc: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f UINT f_Rj; UINT f_Ri; @@ -758,7 +726,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addc", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addc", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -773,11 +741,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addn: + extract_sfmt_addn: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f UINT f_Rj; UINT f_Ri; @@ -787,7 +755,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addn", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addn", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -802,11 +770,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addni: + extract_sfmt_addni: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_addni.f +#define FLD(f) abuf->fields.sfmt_addi.f UINT f_u4; UINT f_Ri; @@ -816,7 +784,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_u4) = f_u4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addni", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addni", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -830,11 +798,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addn2: + extract_sfmt_addn2: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_addn2.f +#define FLD(f) abuf->fields.sfmt_add2.f SI f_m4; UINT f_Ri; @@ -844,7 +812,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_m4) = f_m4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addn2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addn2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -858,11 +826,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmp: + extract_sfmt_cmp: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -872,7 +840,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -886,11 +854,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpi: + extract_sfmt_cmpi: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_addi.f UINT f_u4; UINT f_Ri; @@ -900,7 +868,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_u4) = f_u4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -913,11 +881,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmp2: + extract_sfmt_cmp2: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmp2.f +#define FLD(f) abuf->fields.sfmt_add2.f SI f_m4; UINT f_Ri; @@ -927,7 +895,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_m4) = f_m4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp2", "f_m4 0x%x", 'x', f_m4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -940,11 +908,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_and: + extract_sfmt_and: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f UINT f_Rj; UINT f_Ri; @@ -954,7 +922,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -969,11 +937,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_andm: + extract_sfmt_andm: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -983,7 +951,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andm", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andm", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -997,11 +965,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_andh: + extract_sfmt_andh: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1011,7 +979,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andh", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andh", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1025,11 +993,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_andb: + extract_sfmt_andb: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1039,7 +1007,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1053,11 +1021,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bandl: + extract_sfmt_bandl: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f UINT f_u4; UINT f_Ri; @@ -1067,7 +1035,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_u4) = f_u4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bandl", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bandl", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1080,11 +1048,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_btstl: + extract_sfmt_btstl: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f UINT f_u4; UINT f_Ri; @@ -1094,7 +1062,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_u4) = f_u4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_btstl", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btstl", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1107,11 +1075,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mul: + extract_sfmt_mul: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mul.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1121,7 +1089,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mul", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mul", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1135,11 +1103,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mulu: + extract_sfmt_mulu: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mulu.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1149,7 +1117,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulu", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulu", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1163,11 +1131,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mulh: + extract_sfmt_mulh: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1177,7 +1145,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulh", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulh", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1191,18 +1159,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_div0s: + extract_sfmt_div0s: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_div0s.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div0s", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0s", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1215,32 +1183,32 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_div0u: + extract_sfmt_div0u: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_div0u.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div0u", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0u", (char *) 0)); #undef FLD return idesc; } - extract_fmt_div1: + extract_sfmt_div1: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_div1.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div1", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div1", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1253,18 +1221,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_div2: + extract_sfmt_div2: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_div2.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div2", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div2", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1277,39 +1245,39 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_div3: + extract_sfmt_div3: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_div3.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div3", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div3", (char *) 0)); #undef FLD return idesc; } - extract_fmt_div4s: + extract_sfmt_div4s: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_div4s.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div4s", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div4s", (char *) 0)); #undef FLD return idesc; } - extract_fmt_lsl: + extract_sfmt_lsl: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f UINT f_Rj; UINT f_Ri; @@ -1319,7 +1287,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lsl", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lsl", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1334,11 +1302,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lsli: + extract_sfmt_lsli: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f UINT f_u4; UINT f_Ri; @@ -1348,7 +1316,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_u4) = f_u4; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lsli", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lsli", "f_u4 0x%x", 'x', f_u4, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1362,11 +1330,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldi8: + extract_sfmt_ldi8: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_ldi8.f UINT f_i8; UINT f_Ri; @@ -1376,7 +1344,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_i8) = f_i8; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_i8 0x%x", 'x', f_i8, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_i8 0x%x", 'x', f_i8, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1389,11 +1357,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldi20: + extract_sfmt_ldi20: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldi20.f +#define FLD(f) abuf->fields.sfmt_ldi20.f UINT f_i20_16; UINT f_i20_4; UINT f_Ri; @@ -1412,7 +1380,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_i20) = f_i20; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi20", "f_i20 0x%x", 'x', f_i20, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi20", "f_i20 0x%x", 'x', f_i20, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1425,11 +1393,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldi32: + extract_sfmt_ldi32: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldi32.f +#define FLD(f) abuf->fields.sfmt_ldi32.f UINT f_i32; UINT f_Ri; /* Contents of trailing part of insn. */ @@ -1444,7 +1412,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_i32) = f_i32; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi32", "f_i32 0x%x", 'x', f_i32, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi32", "f_i32 0x%x", 'x', f_i32, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1457,11 +1425,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld: + extract_sfmt_ld: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f UINT f_Rj; UINT f_Ri; @@ -1471,7 +1439,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Rj) = & CPU (h_gr)[f_Rj]; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1485,11 +1453,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr13: + extract_sfmt_ldr13: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f UINT f_Rj; UINT f_Ri; @@ -1499,7 +1467,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Rj) = & CPU (h_gr)[f_Rj]; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr13", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr13", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1514,11 +1482,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr14: + extract_sfmt_ldr14: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr14.f +#define FLD(f) abuf->fields.sfmt_ldr14.f SI f_disp10; UINT f_Ri; @@ -1528,7 +1496,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_disp10) = f_disp10; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr14", "f_disp10 0x%x", 'x', f_disp10, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr14", "f_disp10 0x%x", 'x', f_disp10, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1542,11 +1510,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr14uh: + extract_sfmt_ldr14uh: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr14uh.f +#define FLD(f) abuf->fields.sfmt_ldr14uh.f SI f_disp9; UINT f_Ri; @@ -1556,7 +1524,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_disp9) = f_disp9; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr14uh", "f_disp9 0x%x", 'x', f_disp9, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr14uh", "f_disp9 0x%x", 'x', f_disp9, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1570,11 +1538,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr14ub: + extract_sfmt_ldr14ub: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr14ub.f +#define FLD(f) abuf->fields.sfmt_ldr14ub.f INT f_disp8; UINT f_Ri; @@ -1584,7 +1552,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_disp8) = f_disp8; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr14ub", "f_disp8 0x%x", 'x', f_disp8, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr14ub", "f_disp8 0x%x", 'x', f_disp8, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1598,11 +1566,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr15: + extract_sfmt_ldr15: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr15.f +#define FLD(f) abuf->fields.sfmt_ldr15.f USI f_udisp6; UINT f_Ri; @@ -1612,7 +1580,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_udisp6) = f_udisp6; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15", "f_udisp6 0x%x", 'x', f_udisp6, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr15", "f_udisp6 0x%x", 'x', f_udisp6, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1626,11 +1594,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr15gr: + extract_sfmt_ldr15gr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr15gr.f +#define FLD(f) abuf->fields.sfmt_ldr15gr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); @@ -1638,7 +1606,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_Ri) = f_Ri; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15gr", "f_Ri 0x%x", 'x', f_Ri, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr15gr", "f_Ri 0x%x", 'x', f_Ri, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1653,18 +1621,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr15dr: + extract_sfmt_ldr15dr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f UINT f_Rs2; f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_Rs2) = f_Rs2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15dr", "f_Rs2 0x%x", 'x', f_Rs2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr15dr", "f_Rs2 0x%x", 'x', f_Rs2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1678,15 +1646,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldr15ps: + extract_sfmt_ldr15ps: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldr15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldr15ps", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldr15ps", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1700,11 +1668,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_st: + extract_sfmt_st: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1714,7 +1682,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1728,11 +1696,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str13: + extract_sfmt_str13: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f UINT f_Rj; UINT f_Ri; @@ -1742,7 +1710,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str13", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str13", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1757,11 +1725,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str14: + extract_sfmt_str14: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str14.f +#define FLD(f) abuf->fields.sfmt_str14.f SI f_disp10; UINT f_Ri; @@ -1771,7 +1739,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_disp10) = f_disp10; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str14", "f_disp10 0x%x", 'x', f_disp10, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str14", "f_disp10 0x%x", 'x', f_disp10, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1785,11 +1753,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str14h: + extract_sfmt_str14h: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str14h.f +#define FLD(f) abuf->fields.sfmt_str14h.f SI f_disp9; UINT f_Ri; @@ -1799,7 +1767,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_disp9) = f_disp9; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str14h", "f_disp9 0x%x", 'x', f_disp9, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str14h", "f_disp9 0x%x", 'x', f_disp9, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1813,11 +1781,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str14b: + extract_sfmt_str14b: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str14b.f +#define FLD(f) abuf->fields.sfmt_str14b.f INT f_disp8; UINT f_Ri; @@ -1827,7 +1795,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_disp8) = f_disp8; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str14b", "f_disp8 0x%x", 'x', f_disp8, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str14b", "f_disp8 0x%x", 'x', f_disp8, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1841,11 +1809,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str15: + extract_sfmt_str15: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str15.f +#define FLD(f) abuf->fields.sfmt_str15.f USI f_udisp6; UINT f_Ri; @@ -1855,7 +1823,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_udisp6) = f_udisp6; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15", "f_udisp6 0x%x", 'x', f_udisp6, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str15", "f_udisp6 0x%x", 'x', f_udisp6, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1869,18 +1837,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str15gr: + extract_sfmt_str15gr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str15gr.f +#define FLD(f) abuf->fields.sfmt_str15gr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15gr", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str15gr", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1895,18 +1863,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str15dr: + extract_sfmt_str15dr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f UINT f_Rs2; f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_Rs2) = f_Rs2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15dr", "f_Rs2 0x%x", 'x', f_Rs2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str15dr", "f_Rs2 0x%x", 'x', f_Rs2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1920,15 +1888,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_str15ps: + extract_sfmt_str15ps: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_str15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_str15ps", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_str15ps", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1942,11 +1910,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mov: + extract_sfmt_mov: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mov.f +#define FLD(f) abuf->fields.sfmt_ldr13.f UINT f_Rj; UINT f_Ri; @@ -1956,7 +1924,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Rj) = & CPU (h_gr)[f_Rj]; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mov", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov", "Rj 0x%x", 'x', f_Rj, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1970,11 +1938,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movdr: + extract_sfmt_movdr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movdr.f +#define FLD(f) abuf->fields.sfmt_movdr.f UINT f_Rs1; UINT f_Ri; @@ -1984,7 +1952,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_Rs1) = f_Rs1; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movdr", "f_Rs1 0x%x", 'x', f_Rs1, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movdr", "f_Rs1 0x%x", 'x', f_Rs1, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1997,18 +1965,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movps: + extract_sfmt_movps: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movps.f +#define FLD(f) abuf->fields.sfmt_movdr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movps", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movps", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2021,11 +1989,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mov2dr: + extract_sfmt_mov2dr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mov2dr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Rs1; UINT f_Ri; @@ -2035,7 +2003,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (f_Rs1) = f_Rs1; FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mov2dr", "f_Rs1 0x%x", 'x', f_Rs1, "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov2dr", "f_Rs1 0x%x", 'x', f_Rs1, "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2048,18 +2016,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mov2ps: + extract_sfmt_mov2ps: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mov2ps.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mov2ps", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov2ps", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2072,19 +2040,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_jmp: + extract_sfmt_jmp: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2097,19 +2064,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_callr: + extract_sfmt_callr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callr", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callr", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2122,19 +2088,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_call: + extract_sfmt_call: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f SI f_rel12; f_rel12 = ((((EXTRACT_MSB0_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label12) = f_rel12; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_call", "label12 0x%x", 'x', f_rel12, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "label12 0x%x", 'x', f_rel12, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2146,16 +2111,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ret: + extract_sfmt_ret: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ret", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ret", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2167,19 +2131,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_int: + extract_sfmt_int: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_int.f +#define FLD(f) abuf->fields.sfmt_int.f UINT f_u8; f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_u8) = f_u8; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_int", "f_u8 0x%x", 'x', f_u8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_int", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2191,16 +2154,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_inte: + extract_sfmt_inte: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_inte.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_inte", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_inte", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2212,16 +2174,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_reti: + extract_sfmt_reti: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_reti.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_reti", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_reti", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2233,19 +2194,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_brad: + extract_sfmt_brad: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_brad", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brad", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2257,33 +2217,32 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bnod: + extract_sfmt_bnod: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bnod", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bnod", (char *) 0)); #undef FLD return idesc; } - extract_fmt_beqd: + extract_sfmt_beqd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqd", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqd", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2295,19 +2254,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bcd: + extract_sfmt_bcd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcd", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcd", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2319,19 +2277,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bnd: + extract_sfmt_bnd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bnd", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bnd", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2343,19 +2300,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bvd: + extract_sfmt_bvd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bvd", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bvd", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2367,19 +2323,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bltd: + extract_sfmt_bltd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bltd", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bltd", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2391,19 +2346,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bled: + extract_sfmt_bled: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bled", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bled", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2415,19 +2369,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_blsd: + extract_sfmt_blsd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f SI f_rel9; f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); /* Record the fields for the semantic handler. */ FLD (i_label9) = f_rel9; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_blsd", "label9 0x%x", 'x', f_rel9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blsd", "label9 0x%x", 'x', f_rel9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2439,18 +2392,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr13: + extract_sfmt_dmovr13: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f USI f_dir10; f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_dir10) = f_dir10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr13", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2463,18 +2416,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr13h: + extract_sfmt_dmovr13h: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f USI f_dir9; f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_dir9) = f_dir9; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13h", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr13h", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2487,18 +2440,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr13b: + extract_sfmt_dmovr13b: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f UINT f_dir8; f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_dir8) = f_dir8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13b", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr13b", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2511,18 +2464,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr13pi: + extract_sfmt_dmovr13pi: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f USI f_dir10; f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_dir10) = f_dir10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr13pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2536,18 +2489,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr13pih: + extract_sfmt_dmovr13pih: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f USI f_dir9; f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_dir9) = f_dir9; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13pih", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr13pih", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2561,18 +2514,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr13pib: + extract_sfmt_dmovr13pib: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f UINT f_dir8; f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_dir8) = f_dir8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr13pib", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr13pib", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2586,18 +2539,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmovr15pi: + extract_sfmt_dmovr15pi: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmovr15pi.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f USI f_dir10; f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_dir10) = f_dir10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmovr15pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmovr15pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2611,18 +2564,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r13: + extract_sfmt_dmov2r13: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f USI f_dir10; f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_dir10) = f_dir10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r13", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2635,18 +2588,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r13h: + extract_sfmt_dmov2r13h: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f USI f_dir9; f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_dir9) = f_dir9; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13h", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r13h", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2659,18 +2612,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r13b: + extract_sfmt_dmov2r13b: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f UINT f_dir8; f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_dir8) = f_dir8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13b", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r13b", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2683,18 +2636,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r13pi: + extract_sfmt_dmov2r13pi: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f USI f_dir10; f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_dir10) = f_dir10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r13pi", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2708,18 +2661,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r13pih: + extract_sfmt_dmov2r13pih: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f USI f_dir9; f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_dir9) = f_dir9; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13pih", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r13pih", "f_dir9 0x%x", 'x', f_dir9, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2733,18 +2686,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r13pib: + extract_sfmt_dmov2r13pib: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f UINT f_dir8; f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_dir8) = f_dir8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r13pib", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r13pib", "f_dir8 0x%x", 'x', f_dir8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2758,18 +2711,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_dmov2r15pd: + extract_sfmt_dmov2r15pd: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_dmov2r15pd.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f USI f_dir10; f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_dir10) = f_dir10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_dmov2r15pd", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmov2r15pd", "f_dir10 0x%x", 'x', f_dir10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2783,18 +2736,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldres: + extract_sfmt_ldres: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldres", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldres", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2808,69 +2761,69 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_copop: + extract_sfmt_copop: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f /* Contents of trailing part of insn. */ UINT word_1; word_1 = GETIMEMUHI (current_cpu, pc + 2); /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copop", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_copop", (char *) 0)); #undef FLD return idesc; } - extract_fmt_andccr: + extract_sfmt_andccr: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f UINT f_u8; f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_u8) = f_u8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andccr", "f_u8 0x%x", 'x', f_u8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andccr", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #undef FLD return idesc; } - extract_fmt_stilm: + extract_sfmt_stilm: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stilm.f +#define FLD(f) abuf->fields.sfmt_int.f UINT f_u8; f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_u8) = f_u8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stilm", "f_u8 0x%x", 'x', f_u8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stilm", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #undef FLD return idesc; } - extract_fmt_addsp: + extract_sfmt_addsp: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_addsp.f +#define FLD(f) abuf->fields.sfmt_addsp.f SI f_s10; f_s10 = ((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_s10) = f_s10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addsp", "f_s10 0x%x", 'x', f_s10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addsp", "f_s10 0x%x", 'x', f_s10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2884,18 +2837,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_extsb: + extract_sfmt_extsb: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_extsb.f +#define FLD(f) abuf->fields.sfmt_add2.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extsb", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extsb", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2909,18 +2862,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_extub: + extract_sfmt_extub: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_extub.f +#define FLD(f) abuf->fields.sfmt_add2.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extub", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extub", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2934,18 +2887,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_extsh: + extract_sfmt_extsh: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_extsh.f +#define FLD(f) abuf->fields.sfmt_add2.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extsh", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extsh", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2959,18 +2912,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_extuh: + extract_sfmt_extuh: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_extuh.f +#define FLD(f) abuf->fields.sfmt_add2.f UINT f_Ri; f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_extuh", "Ri 0x%x", 'x', f_Ri, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extuh", "Ri 0x%x", 'x', f_Ri, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2984,18 +2937,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldm0: + extract_sfmt_ldm0: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldm0.f +#define FLD(f) abuf->fields.sfmt_ldm0.f UINT f_reglist_low_ld; f_reglist_low_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_reglist_low_ld) = f_reglist_low_ld; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldm0", "f_reglist_low_ld 0x%x", 'x', f_reglist_low_ld, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldm0", "f_reglist_low_ld 0x%x", 'x', f_reglist_low_ld, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3017,18 +2970,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldm1: + extract_sfmt_ldm1: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldm1.f +#define FLD(f) abuf->fields.sfmt_ldm1.f UINT f_reglist_hi_ld; f_reglist_hi_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_reglist_hi_ld) = f_reglist_hi_ld; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldm1", "f_reglist_hi_ld 0x%x", 'x', f_reglist_hi_ld, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldm1", "f_reglist_hi_ld 0x%x", 'x', f_reglist_hi_ld, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3049,18 +3002,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stm0: + extract_sfmt_stm0: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stm0.f +#define FLD(f) abuf->fields.sfmt_stm0.f UINT f_reglist_low_st; f_reglist_low_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_reglist_low_st) = f_reglist_low_st; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stm0", "f_reglist_low_st 0x%x", 'x', f_reglist_low_st, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stm0", "f_reglist_low_st 0x%x", 'x', f_reglist_low_st, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3082,18 +3035,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stm1: + extract_sfmt_stm1: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stm1.f +#define FLD(f) abuf->fields.sfmt_stm1.f UINT f_reglist_hi_st; f_reglist_hi_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_reglist_hi_st) = f_reglist_hi_st; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stm1", "f_reglist_hi_st 0x%x", 'x', f_reglist_hi_st, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stm1", "f_reglist_hi_st 0x%x", 'x', f_reglist_hi_st, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3114,18 +3067,18 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_enter: + extract_sfmt_enter: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_enter.f +#define FLD(f) abuf->fields.sfmt_enter.f USI f_u10; f_u10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_u10) = f_u10; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_enter", "f_u10 0x%x", 'x', f_u10, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_enter", "f_u10 0x%x", 'x', f_u10, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3141,15 +3094,15 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_leave: + extract_sfmt_leave: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_leave.f +#define FLD(f) abuf->fields.sfmt_enter.f /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_leave", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_leave", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3165,11 +3118,11 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_xchb: + extract_sfmt_xchb: { const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_xchb.f +#define FLD(f) abuf->fields.sfmt_add.f UINT f_Rj; UINT f_Ri; @@ -3179,7 +3132,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ FLD (i_Ri) = & CPU (h_gr)[f_Ri]; FLD (i_Rj) = & CPU (h_gr)[f_Rj]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_xchb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xchb", "Ri 0x%x", 'x', f_Ri, "Rj 0x%x", 'x', f_Rj, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ diff --git a/sim/fr30/decode.h b/sim/fr30/decode.h index 4bc943e..eda9c55 100644 --- a/sim/fr30/decode.h +++ b/sim/fr30/decode.h @@ -29,6 +29,8 @@ extern const IDESC *fr30bf_decode (SIM_CPU *, IADDR, CGEN_INSN_INT, ARGBUF *); extern void fr30bf_init_idesc_table (SIM_CPU *); +extern void fr30bf_sem_init_idesc_table (SIM_CPU *); +extern void fr30bf_semf_init_idesc_table (SIM_CPU *); /* Enum declaration for instructions in cpu family fr30bf. */ typedef enum fr30bf_insn_type { @@ -77,200 +79,34 @@ typedef enum fr30bf_insn_type { , FR30BF_INSN_ENTER, FR30BF_INSN_LEAVE, FR30BF_INSN_XCHB, FR30BF_INSN_MAX } FR30BF_INSN_TYPE; -#if ! WITH_SEM_SWITCH_FULL -#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,fn); -#else -#define SEMFULL(fn) -#endif - -#if ! WITH_SEM_SWITCH_FAST -#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (fr30bf,_semf_,fn); -#else -#define SEMFAST(fn) -#endif - -#define SEM(fn) SEMFULL (fn) SEMFAST (fn) - -/* The function version of the before/after handlers is always needed, - so we always want the SEMFULL declaration of them. */ -extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,x_before); -extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,x_after); - -SEM (x_invalid) -SEM (x_after) -SEM (x_before) -SEM (x_cti_chain) -SEM (x_chain) -SEM (x_begin) -SEM (add) -SEM (addi) -SEM (add2) -SEM (addc) -SEM (addn) -SEM (addni) -SEM (addn2) -SEM (sub) -SEM (subc) -SEM (subn) -SEM (cmp) -SEM (cmpi) -SEM (cmp2) -SEM (and) -SEM (or) -SEM (eor) -SEM (andm) -SEM (andh) -SEM (andb) -SEM (orm) -SEM (orh) -SEM (orb) -SEM (eorm) -SEM (eorh) -SEM (eorb) -SEM (bandl) -SEM (borl) -SEM (beorl) -SEM (bandh) -SEM (borh) -SEM (beorh) -SEM (btstl) -SEM (btsth) -SEM (mul) -SEM (mulu) -SEM (mulh) -SEM (muluh) -SEM (div0s) -SEM (div0u) -SEM (div1) -SEM (div2) -SEM (div3) -SEM (div4s) -SEM (lsl) -SEM (lsli) -SEM (lsl2) -SEM (lsr) -SEM (lsri) -SEM (lsr2) -SEM (asr) -SEM (asri) -SEM (asr2) -SEM (ldi8) -SEM (ldi20) -SEM (ldi32) -SEM (ld) -SEM (lduh) -SEM (ldub) -SEM (ldr13) -SEM (ldr13uh) -SEM (ldr13ub) -SEM (ldr14) -SEM (ldr14uh) -SEM (ldr14ub) -SEM (ldr15) -SEM (ldr15gr) -SEM (ldr15dr) -SEM (ldr15ps) -SEM (st) -SEM (sth) -SEM (stb) -SEM (str13) -SEM (str13h) -SEM (str13b) -SEM (str14) -SEM (str14h) -SEM (str14b) -SEM (str15) -SEM (str15gr) -SEM (str15dr) -SEM (str15ps) -SEM (mov) -SEM (movdr) -SEM (movps) -SEM (mov2dr) -SEM (mov2ps) -SEM (jmp) -SEM (jmpd) -SEM (callr) -SEM (callrd) -SEM (call) -SEM (calld) -SEM (ret) -SEM (ret_d) -SEM (int) -SEM (inte) -SEM (reti) -SEM (brad) -SEM (bra) -SEM (bnod) -SEM (bno) -SEM (beqd) -SEM (beq) -SEM (bned) -SEM (bne) -SEM (bcd) -SEM (bc) -SEM (bncd) -SEM (bnc) -SEM (bnd) -SEM (bn) -SEM (bpd) -SEM (bp) -SEM (bvd) -SEM (bv) -SEM (bnvd) -SEM (bnv) -SEM (bltd) -SEM (blt) -SEM (bged) -SEM (bge) -SEM (bled) -SEM (ble) -SEM (bgtd) -SEM (bgt) -SEM (blsd) -SEM (bls) -SEM (bhid) -SEM (bhi) -SEM (dmovr13) -SEM (dmovr13h) -SEM (dmovr13b) -SEM (dmovr13pi) -SEM (dmovr13pih) -SEM (dmovr13pib) -SEM (dmovr15pi) -SEM (dmov2r13) -SEM (dmov2r13h) -SEM (dmov2r13b) -SEM (dmov2r13pi) -SEM (dmov2r13pih) -SEM (dmov2r13pib) -SEM (dmov2r15pd) -SEM (ldres) -SEM (stres) -SEM (copop) -SEM (copld) -SEM (copst) -SEM (copsv) -SEM (nop) -SEM (andccr) -SEM (orccr) -SEM (stilm) -SEM (addsp) -SEM (extsb) -SEM (extub) -SEM (extsh) -SEM (extuh) -SEM (ldm0) -SEM (ldm1) -SEM (stm0) -SEM (stm1) -SEM (enter) -SEM (leave) -SEM (xchb) - -#undef SEMFULL -#undef SEMFAST -#undef SEM +/* Enum declaration for semantic formats in cpu family fr30bf. */ +typedef enum fr30bf_sfmt_type { + FR30BF_SFMT_EMPTY, FR30BF_SFMT_ADD, FR30BF_SFMT_ADDI, FR30BF_SFMT_ADD2 + , FR30BF_SFMT_ADDC, FR30BF_SFMT_ADDN, FR30BF_SFMT_ADDNI, FR30BF_SFMT_ADDN2 + , FR30BF_SFMT_CMP, FR30BF_SFMT_CMPI, FR30BF_SFMT_CMP2, FR30BF_SFMT_AND + , FR30BF_SFMT_ANDM, FR30BF_SFMT_ANDH, FR30BF_SFMT_ANDB, FR30BF_SFMT_BANDL + , FR30BF_SFMT_BTSTL, FR30BF_SFMT_MUL, FR30BF_SFMT_MULU, FR30BF_SFMT_MULH + , FR30BF_SFMT_DIV0S, FR30BF_SFMT_DIV0U, FR30BF_SFMT_DIV1, FR30BF_SFMT_DIV2 + , FR30BF_SFMT_DIV3, FR30BF_SFMT_DIV4S, FR30BF_SFMT_LSL, FR30BF_SFMT_LSLI + , FR30BF_SFMT_LDI8, FR30BF_SFMT_LDI20, FR30BF_SFMT_LDI32, FR30BF_SFMT_LD + , FR30BF_SFMT_LDR13, FR30BF_SFMT_LDR14, FR30BF_SFMT_LDR14UH, FR30BF_SFMT_LDR14UB + , FR30BF_SFMT_LDR15, FR30BF_SFMT_LDR15GR, FR30BF_SFMT_LDR15DR, FR30BF_SFMT_LDR15PS + , FR30BF_SFMT_ST, FR30BF_SFMT_STR13, FR30BF_SFMT_STR14, FR30BF_SFMT_STR14H + , FR30BF_SFMT_STR14B, FR30BF_SFMT_STR15, FR30BF_SFMT_STR15GR, FR30BF_SFMT_STR15DR + , FR30BF_SFMT_STR15PS, FR30BF_SFMT_MOV, FR30BF_SFMT_MOVDR, FR30BF_SFMT_MOVPS + , FR30BF_SFMT_MOV2DR, FR30BF_SFMT_MOV2PS, FR30BF_SFMT_JMP, FR30BF_SFMT_CALLR + , FR30BF_SFMT_CALL, FR30BF_SFMT_RET, FR30BF_SFMT_INT, FR30BF_SFMT_INTE + , FR30BF_SFMT_RETI, FR30BF_SFMT_BRAD, FR30BF_SFMT_BNOD, FR30BF_SFMT_BEQD + , FR30BF_SFMT_BCD, FR30BF_SFMT_BND, FR30BF_SFMT_BVD, FR30BF_SFMT_BLTD + , FR30BF_SFMT_BLED, FR30BF_SFMT_BLSD, FR30BF_SFMT_DMOVR13, FR30BF_SFMT_DMOVR13H + , FR30BF_SFMT_DMOVR13B, FR30BF_SFMT_DMOVR13PI, FR30BF_SFMT_DMOVR13PIH, FR30BF_SFMT_DMOVR13PIB + , FR30BF_SFMT_DMOVR15PI, FR30BF_SFMT_DMOV2R13, FR30BF_SFMT_DMOV2R13H, FR30BF_SFMT_DMOV2R13B + , FR30BF_SFMT_DMOV2R13PI, FR30BF_SFMT_DMOV2R13PIH, FR30BF_SFMT_DMOV2R13PIB, FR30BF_SFMT_DMOV2R15PD + , FR30BF_SFMT_LDRES, FR30BF_SFMT_COPOP, FR30BF_SFMT_ANDCCR, FR30BF_SFMT_STILM + , FR30BF_SFMT_ADDSP, FR30BF_SFMT_EXTSB, FR30BF_SFMT_EXTUB, FR30BF_SFMT_EXTSH + , FR30BF_SFMT_EXTUH, FR30BF_SFMT_LDM0, FR30BF_SFMT_LDM1, FR30BF_SFMT_STM0 + , FR30BF_SFMT_STM1, FR30BF_SFMT_ENTER, FR30BF_SFMT_LEAVE, FR30BF_SFMT_XCHB +} FR30BF_SFMT_TYPE; /* Function unit handlers (user written). */ diff --git a/sim/fr30/model.c b/sim/fr30/model.c index 9dd6612..59e6901 100644 --- a/sim/fr30/model.c +++ b/sim/fr30/model.c @@ -37,7 +37,7 @@ with this program; if not, write to the Free Software Foundation, Inc., static int model_fr30_1_add (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -62,7 +62,7 @@ model_fr30_1_add (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_addi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -85,7 +85,7 @@ model_fr30_1_addi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_add2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add2.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -108,7 +108,7 @@ model_fr30_1_add2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_addc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -133,7 +133,7 @@ model_fr30_1_addc (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_addn (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -158,7 +158,7 @@ model_fr30_1_addn (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_addni (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addni.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -181,7 +181,7 @@ model_fr30_1_addni (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_addn2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addn2.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -204,7 +204,7 @@ model_fr30_1_addn2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_sub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -229,7 +229,7 @@ model_fr30_1_sub (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_subc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -254,7 +254,7 @@ model_fr30_1_subc (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_subn (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -279,7 +279,7 @@ model_fr30_1_subn (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_cmp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -302,7 +302,7 @@ model_fr30_1_cmp (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_cmpi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -323,7 +323,7 @@ model_fr30_1_cmpi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_cmp2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp2.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -344,7 +344,7 @@ model_fr30_1_cmp2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_and (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -369,7 +369,7 @@ model_fr30_1_and (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_or (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -394,7 +394,7 @@ model_fr30_1_or (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_eor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -419,7 +419,7 @@ model_fr30_1_eor (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_andm (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -462,7 +462,7 @@ model_fr30_1_andm (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_andh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -505,7 +505,7 @@ model_fr30_1_andh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_andb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -548,7 +548,7 @@ model_fr30_1_andb (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_orm (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -591,7 +591,7 @@ model_fr30_1_orm (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_orh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -634,7 +634,7 @@ model_fr30_1_orh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_orb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -677,7 +677,7 @@ model_fr30_1_orb (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_eorm (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -720,7 +720,7 @@ model_fr30_1_eorm (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_eorh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -763,7 +763,7 @@ model_fr30_1_eorh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_eorb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -806,7 +806,7 @@ model_fr30_1_eorb (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bandl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -843,7 +843,7 @@ model_fr30_1_bandl (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_borl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -880,7 +880,7 @@ model_fr30_1_borl (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_beorl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -917,7 +917,7 @@ model_fr30_1_beorl (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bandh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -954,7 +954,7 @@ model_fr30_1_bandh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_borh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -991,7 +991,7 @@ model_fr30_1_borh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_beorh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1028,7 +1028,7 @@ model_fr30_1_beorh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_btstl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1056,7 +1056,7 @@ model_fr30_1_btstl (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_btsth (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1084,7 +1084,7 @@ model_fr30_1_btsth (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_mul (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mul.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1107,7 +1107,7 @@ model_fr30_1_mul (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_mulu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulu.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1130,7 +1130,7 @@ model_fr30_1_mulu (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_mulh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1153,7 +1153,7 @@ model_fr30_1_mulh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_muluh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1176,7 +1176,7 @@ model_fr30_1_muluh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_div0s (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div0s.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1197,7 +1197,7 @@ model_fr30_1_div0s (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_div0u (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div0u.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1216,7 +1216,7 @@ model_fr30_1_div0u (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_div1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div1.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1237,7 +1237,7 @@ model_fr30_1_div1 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_div2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div2.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1258,7 +1258,7 @@ model_fr30_1_div2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_div3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div3.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1277,7 +1277,7 @@ model_fr30_1_div3 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_div4s (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div4s.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1296,7 +1296,7 @@ model_fr30_1_div4s (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lsl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1321,7 +1321,7 @@ model_fr30_1_lsl (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lsli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1344,7 +1344,7 @@ model_fr30_1_lsli (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lsl2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1367,7 +1367,7 @@ model_fr30_1_lsl2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lsr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1392,7 +1392,7 @@ model_fr30_1_lsr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lsri (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1415,7 +1415,7 @@ model_fr30_1_lsri (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lsr2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1438,7 +1438,7 @@ model_fr30_1_lsr2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_asr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1463,7 +1463,7 @@ model_fr30_1_asr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_asri (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1486,7 +1486,7 @@ model_fr30_1_asri (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_asr2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1509,7 +1509,7 @@ model_fr30_1_asr2 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldi8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_ldi8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1530,7 +1530,7 @@ model_fr30_1_ldi8 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldi20 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi20.f +#define FLD(f) abuf->fields.sfmt_ldi20.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1551,7 +1551,7 @@ model_fr30_1_ldi20 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldi32 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi32.f +#define FLD(f) abuf->fields.sfmt_ldi32.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1572,7 +1572,7 @@ model_fr30_1_ldi32 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ld (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1594,7 +1594,7 @@ model_fr30_1_ld (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_lduh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1616,7 +1616,7 @@ model_fr30_1_lduh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1638,7 +1638,7 @@ model_fr30_1_ldub (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr13 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1660,7 +1660,7 @@ model_fr30_1_ldr13 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr13uh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1682,7 +1682,7 @@ model_fr30_1_ldr13uh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr13ub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1704,7 +1704,7 @@ model_fr30_1_ldr13ub (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr14 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr14.f +#define FLD(f) abuf->fields.sfmt_ldr14.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1724,7 +1724,7 @@ model_fr30_1_ldr14 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr14uh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr14uh.f +#define FLD(f) abuf->fields.sfmt_ldr14uh.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1744,7 +1744,7 @@ model_fr30_1_ldr14uh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr14ub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr14ub.f +#define FLD(f) abuf->fields.sfmt_ldr14ub.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1764,7 +1764,7 @@ model_fr30_1_ldr14ub (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr15 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15.f +#define FLD(f) abuf->fields.sfmt_ldr15.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1784,7 +1784,7 @@ model_fr30_1_ldr15 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr15gr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15gr.f +#define FLD(f) abuf->fields.sfmt_ldr15gr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1804,7 +1804,7 @@ model_fr30_1_ldr15gr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr15dr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1822,7 +1822,7 @@ model_fr30_1_ldr15dr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldr15ps (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1840,7 +1840,7 @@ model_fr30_1_ldr15ps (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_st (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1862,7 +1862,7 @@ model_fr30_1_st (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_sth (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1884,7 +1884,7 @@ model_fr30_1_sth (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_stb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1906,7 +1906,7 @@ model_fr30_1_stb (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str13 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1928,7 +1928,7 @@ model_fr30_1_str13 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str13h (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1950,7 +1950,7 @@ model_fr30_1_str13h (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str13b (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1972,7 +1972,7 @@ model_fr30_1_str13b (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str14 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str14.f +#define FLD(f) abuf->fields.sfmt_str14.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1992,7 +1992,7 @@ model_fr30_1_str14 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str14h (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str14h.f +#define FLD(f) abuf->fields.sfmt_str14h.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2012,7 +2012,7 @@ model_fr30_1_str14h (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str14b (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str14b.f +#define FLD(f) abuf->fields.sfmt_str14b.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2032,7 +2032,7 @@ model_fr30_1_str14b (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str15 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str15.f +#define FLD(f) abuf->fields.sfmt_str15.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2052,7 +2052,7 @@ model_fr30_1_str15 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str15gr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str15gr.f +#define FLD(f) abuf->fields.sfmt_str15gr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2072,7 +2072,7 @@ model_fr30_1_str15gr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str15dr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2090,7 +2090,7 @@ model_fr30_1_str15dr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_str15ps (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_str15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2108,7 +2108,7 @@ model_fr30_1_str15ps (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_mov (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mov.f +#define FLD(f) abuf->fields.sfmt_ldr13.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2131,7 +2131,7 @@ model_fr30_1_mov (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_movdr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movdr.f +#define FLD(f) abuf->fields.sfmt_movdr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2152,7 +2152,7 @@ model_fr30_1_movdr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_movps (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movps.f +#define FLD(f) abuf->fields.sfmt_movdr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2173,7 +2173,7 @@ model_fr30_1_movps (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_mov2dr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mov2dr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2194,7 +2194,7 @@ model_fr30_1_mov2dr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_mov2ps (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mov2ps.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2215,7 +2215,7 @@ model_fr30_1_mov2ps (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_jmp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2235,7 +2235,7 @@ model_fr30_1_jmp (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_jmpd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2255,7 +2255,7 @@ model_fr30_1_jmpd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_callr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2275,7 +2275,7 @@ model_fr30_1_callr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_callrd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2295,7 +2295,7 @@ model_fr30_1_callrd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_call (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2313,7 +2313,7 @@ model_fr30_1_call (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_calld (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2331,7 +2331,7 @@ model_fr30_1_calld (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ret (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2349,7 +2349,7 @@ model_fr30_1_ret (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ret_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2367,7 +2367,7 @@ model_fr30_1_ret_d (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_int (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_int.f +#define FLD(f) abuf->fields.sfmt_int.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2386,7 +2386,7 @@ model_fr30_1_int (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_inte (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_inte.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2405,7 +2405,7 @@ model_fr30_1_inte (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_reti (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_reti.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2424,7 +2424,7 @@ model_fr30_1_reti (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_brad (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2442,7 +2442,7 @@ model_fr30_1_brad (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bra (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2460,7 +2460,7 @@ model_fr30_1_bra (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bnod (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2477,7 +2477,7 @@ model_fr30_1_bnod (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bno (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2494,7 +2494,7 @@ model_fr30_1_bno (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_beqd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2512,7 +2512,7 @@ model_fr30_1_beqd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_beq (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2530,7 +2530,7 @@ model_fr30_1_beq (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bned (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2548,7 +2548,7 @@ model_fr30_1_bned (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bne (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2566,7 +2566,7 @@ model_fr30_1_bne (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bcd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2584,7 +2584,7 @@ model_fr30_1_bcd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2602,7 +2602,7 @@ model_fr30_1_bc (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bncd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2620,7 +2620,7 @@ model_fr30_1_bncd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bnc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2638,7 +2638,7 @@ model_fr30_1_bnc (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bnd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2656,7 +2656,7 @@ model_fr30_1_bnd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bn (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2674,7 +2674,7 @@ model_fr30_1_bn (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bpd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2692,7 +2692,7 @@ model_fr30_1_bpd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2710,7 +2710,7 @@ model_fr30_1_bp (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bvd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2728,7 +2728,7 @@ model_fr30_1_bvd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2746,7 +2746,7 @@ model_fr30_1_bv (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bnvd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2764,7 +2764,7 @@ model_fr30_1_bnvd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bnv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2782,7 +2782,7 @@ model_fr30_1_bnv (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bltd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2800,7 +2800,7 @@ model_fr30_1_bltd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_blt (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2818,7 +2818,7 @@ model_fr30_1_blt (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bged (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2836,7 +2836,7 @@ model_fr30_1_bged (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bge (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2854,7 +2854,7 @@ model_fr30_1_bge (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bled (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2872,7 +2872,7 @@ model_fr30_1_bled (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ble (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2890,7 +2890,7 @@ model_fr30_1_ble (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bgtd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2908,7 +2908,7 @@ model_fr30_1_bgtd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bgt (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2926,7 +2926,7 @@ model_fr30_1_bgt (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_blsd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2944,7 +2944,7 @@ model_fr30_1_blsd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bls (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2962,7 +2962,7 @@ model_fr30_1_bls (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bhid (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2980,7 +2980,7 @@ model_fr30_1_bhid (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_bhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2998,7 +2998,7 @@ model_fr30_1_bhi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr13 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3016,7 +3016,7 @@ model_fr30_1_dmovr13 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr13h (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3034,7 +3034,7 @@ model_fr30_1_dmovr13h (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr13b (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3052,7 +3052,7 @@ model_fr30_1_dmovr13b (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr13pi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3077,7 +3077,7 @@ model_fr30_1_dmovr13pi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr13pih (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3102,7 +3102,7 @@ model_fr30_1_dmovr13pih (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr13pib (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3127,7 +3127,7 @@ model_fr30_1_dmovr13pib (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmovr15pi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr15pi.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3152,7 +3152,7 @@ model_fr30_1_dmovr15pi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r13 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3170,7 +3170,7 @@ model_fr30_1_dmov2r13 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r13h (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3188,7 +3188,7 @@ model_fr30_1_dmov2r13h (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r13b (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3206,7 +3206,7 @@ model_fr30_1_dmov2r13b (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r13pi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3231,7 +3231,7 @@ model_fr30_1_dmov2r13pi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r13pih (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3256,7 +3256,7 @@ model_fr30_1_dmov2r13pih (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r13pib (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3281,7 +3281,7 @@ model_fr30_1_dmov2r13pib (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_dmov2r15pd (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r15pd.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3306,7 +3306,7 @@ model_fr30_1_dmov2r15pd (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldres (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3329,7 +3329,7 @@ model_fr30_1_ldres (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_stres (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3352,7 +3352,7 @@ model_fr30_1_stres (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_copop (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3371,7 +3371,7 @@ model_fr30_1_copop (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_copld (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3390,7 +3390,7 @@ model_fr30_1_copld (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_copst (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3409,7 +3409,7 @@ model_fr30_1_copst (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_copsv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3428,7 +3428,7 @@ model_fr30_1_copsv (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_nop (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3447,7 +3447,7 @@ model_fr30_1_nop (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_andccr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3466,7 +3466,7 @@ model_fr30_1_andccr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_orccr (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3485,7 +3485,7 @@ model_fr30_1_orccr (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_stilm (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stilm.f +#define FLD(f) abuf->fields.sfmt_int.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3504,7 +3504,7 @@ model_fr30_1_stilm (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_addsp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addsp.f +#define FLD(f) abuf->fields.sfmt_addsp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3523,7 +3523,7 @@ model_fr30_1_addsp (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_extsb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_extsb.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3546,7 +3546,7 @@ model_fr30_1_extsb (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_extub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_extub.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3569,7 +3569,7 @@ model_fr30_1_extub (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_extsh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_extsh.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3592,7 +3592,7 @@ model_fr30_1_extsh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_extuh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_extuh.f +#define FLD(f) abuf->fields.sfmt_add2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3615,7 +3615,7 @@ model_fr30_1_extuh (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldm0 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldm0.f +#define FLD(f) abuf->fields.sfmt_ldm0.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3632,7 +3632,7 @@ model_fr30_1_ldm0 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_ldm1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldm1.f +#define FLD(f) abuf->fields.sfmt_ldm1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3649,7 +3649,7 @@ model_fr30_1_ldm1 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_stm0 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stm0.f +#define FLD(f) abuf->fields.sfmt_stm0.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3666,7 +3666,7 @@ model_fr30_1_stm0 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_stm1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stm1.f +#define FLD(f) abuf->fields.sfmt_stm1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3683,7 +3683,7 @@ model_fr30_1_stm1 (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_enter (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_enter.f +#define FLD(f) abuf->fields.sfmt_enter.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3702,7 +3702,7 @@ model_fr30_1_enter (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_leave (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_leave.f +#define FLD(f) abuf->fields.sfmt_enter.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3721,7 +3721,7 @@ model_fr30_1_leave (SIM_CPU *current_cpu, void *sem_arg) static int model_fr30_1_xchb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_xchb.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; diff --git a/sim/fr30/sem-switch.c b/sim/fr30/sem-switch.c index 2f8827e..f73f11a 100644 --- a/sim/fr30/sem-switch.c +++ b/sim/fr30/sem-switch.c @@ -208,11 +208,13 @@ with this program; if not, write to the Free Software Foundation, Inc., int i; for (i = 0; labels[i].label != 0; ++i) + { #if FAST_P - CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; + CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; #else - CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; + CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; #endif + } #undef DEFINE_LABELS #endif /* DEFINE_LABELS */ @@ -332,12 +334,12 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) #if WITH_SCACHE_PBB_FR30BF #ifdef DEFINE_SWITCH vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); + pbb_br_type, pbb_br_npc); BREAK (sem); #else /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_TYPE (current_cpu), CPU_PBB_BR_NPC (current_cpu)); #endif #endif @@ -398,7 +400,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -441,7 +443,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -484,7 +486,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add2.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -527,7 +529,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -572,7 +574,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -591,7 +593,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addni.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -610,7 +612,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addn2.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -629,7 +631,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -672,7 +674,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -717,7 +719,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -736,7 +738,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -776,7 +778,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -816,7 +818,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmp2.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -856,7 +858,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -889,7 +891,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -922,7 +924,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -955,7 +957,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -990,7 +992,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1025,7 +1027,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1060,7 +1062,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1095,7 +1097,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1130,7 +1132,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1165,7 +1167,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1200,7 +1202,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1235,7 +1237,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1270,7 +1272,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1289,7 +1291,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1308,7 +1310,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1327,7 +1329,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1346,7 +1348,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1365,7 +1367,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1384,7 +1386,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1412,7 +1414,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1440,7 +1442,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mul.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1483,7 +1485,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulu.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1526,7 +1528,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1557,7 +1559,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1588,7 +1590,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div0s.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1630,7 +1632,7 @@ if (NEBI (CPU (h_d0bit), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div0u.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1661,7 +1663,7 @@ if (NEBI (CPU (h_d0bit), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div1.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1736,7 +1738,7 @@ if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div2.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1798,7 +1800,7 @@ if (EQSI (tmp_tmp, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div3.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1821,7 +1823,7 @@ if (EQBI (CPU (h_zbit), 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div4s.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1844,7 +1846,7 @@ if (EQBI (CPU (h_d1bit), 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1896,7 +1898,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1948,7 +1950,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2000,7 +2002,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2052,7 +2054,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2104,7 +2106,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2156,7 +2158,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2208,7 +2210,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2260,7 +2262,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2312,7 +2314,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_ldi8.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2331,7 +2333,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldi20.f +#define FLD(f) abuf->fields.sfmt_ldi20.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2350,7 +2352,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldi32.f +#define FLD(f) abuf->fields.sfmt_ldi32.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -2369,7 +2371,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2388,7 +2390,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2407,7 +2409,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2426,7 +2428,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2445,7 +2447,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2464,7 +2466,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2483,7 +2485,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr14.f +#define FLD(f) abuf->fields.sfmt_ldr14.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2502,7 +2504,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr14uh.f +#define FLD(f) abuf->fields.sfmt_ldr14uh.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2521,7 +2523,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr14ub.f +#define FLD(f) abuf->fields.sfmt_ldr14ub.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2540,7 +2542,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr15.f +#define FLD(f) abuf->fields.sfmt_ldr15.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2559,7 +2561,7 @@ if (NESI (tmp_shift, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr15gr.f +#define FLD(f) abuf->fields.sfmt_ldr15gr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2589,7 +2591,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2617,7 +2619,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldr15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2643,7 +2645,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2662,7 +2664,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2681,7 +2683,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2700,7 +2702,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2719,7 +2721,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2738,7 +2740,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2757,7 +2759,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str14.f +#define FLD(f) abuf->fields.sfmt_str14.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2776,7 +2778,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str14h.f +#define FLD(f) abuf->fields.sfmt_str14h.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2795,7 +2797,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str14b.f +#define FLD(f) abuf->fields.sfmt_str14b.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2814,7 +2816,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str15.f +#define FLD(f) abuf->fields.sfmt_str15.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2833,7 +2835,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str15gr.f +#define FLD(f) abuf->fields.sfmt_str15gr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2861,7 +2863,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2889,7 +2891,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_str15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2915,7 +2917,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mov.f +#define FLD(f) abuf->fields.sfmt_ldr13.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2934,7 +2936,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movdr.f +#define FLD(f) abuf->fields.sfmt_movdr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2953,7 +2955,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movps.f +#define FLD(f) abuf->fields.sfmt_movdr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2972,7 +2974,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mov2dr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2991,7 +2993,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mov2ps.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3010,7 +3012,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3031,7 +3033,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3054,7 +3056,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3082,7 +3084,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3112,7 +3114,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3126,7 +3128,7 @@ if (NESI (FLD (f_Ri), 15)) { } { USI opval = FLD (i_label12); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -3140,7 +3142,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3155,7 +3157,7 @@ if (NESI (FLD (f_Ri), 15)) { } { USI opval = FLD (i_label12); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -3170,7 +3172,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3191,7 +3193,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3214,7 +3216,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_int.f +#define FLD(f) abuf->fields.sfmt_int.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3240,7 +3242,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_inte.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3266,7 +3268,7 @@ if (NESI (FLD (f_Ri), 15)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_reti.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3338,7 +3340,7 @@ if (EQBI (GET_H_SBIT (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3347,7 +3349,7 @@ if (EQBI (GET_H_SBIT (), 0)) { { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -3361,7 +3363,7 @@ if (EQBI (GET_H_SBIT (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3369,7 +3371,7 @@ if (EQBI (GET_H_SBIT (), 0)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3382,7 +3384,7 @@ if (EQBI (GET_H_SBIT (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3399,7 +3401,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3414,7 +3416,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3424,7 +3426,7 @@ do { } while (0); /*nop*/ if (CPU (h_zbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3441,7 +3443,7 @@ if (CPU (h_zbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3450,7 +3452,7 @@ if (CPU (h_zbit)) { if (CPU (h_zbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3466,7 +3468,7 @@ if (CPU (h_zbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3476,7 +3478,7 @@ if (CPU (h_zbit)) { if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3493,7 +3495,7 @@ if (NOTBI (CPU (h_zbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3502,7 +3504,7 @@ if (NOTBI (CPU (h_zbit))) { if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3518,7 +3520,7 @@ if (NOTBI (CPU (h_zbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3528,7 +3530,7 @@ if (NOTBI (CPU (h_zbit))) { if (CPU (h_cbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3545,7 +3547,7 @@ if (CPU (h_cbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3554,7 +3556,7 @@ if (CPU (h_cbit)) { if (CPU (h_cbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3570,7 +3572,7 @@ if (CPU (h_cbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3580,7 +3582,7 @@ if (CPU (h_cbit)) { if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3597,7 +3599,7 @@ if (NOTBI (CPU (h_cbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3606,7 +3608,7 @@ if (NOTBI (CPU (h_cbit))) { if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3622,7 +3624,7 @@ if (NOTBI (CPU (h_cbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3632,7 +3634,7 @@ if (NOTBI (CPU (h_cbit))) { if (CPU (h_nbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3649,7 +3651,7 @@ if (CPU (h_nbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3658,7 +3660,7 @@ if (CPU (h_nbit)) { if (CPU (h_nbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3674,7 +3676,7 @@ if (CPU (h_nbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3684,7 +3686,7 @@ if (CPU (h_nbit)) { if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3701,7 +3703,7 @@ if (NOTBI (CPU (h_nbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3710,7 +3712,7 @@ if (NOTBI (CPU (h_nbit))) { if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3726,7 +3728,7 @@ if (NOTBI (CPU (h_nbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3736,7 +3738,7 @@ if (NOTBI (CPU (h_nbit))) { if (CPU (h_vbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3753,7 +3755,7 @@ if (CPU (h_vbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3762,7 +3764,7 @@ if (CPU (h_vbit)) { if (CPU (h_vbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3778,7 +3780,7 @@ if (CPU (h_vbit)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3788,7 +3790,7 @@ if (CPU (h_vbit)) { if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3805,7 +3807,7 @@ if (NOTBI (CPU (h_vbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3814,7 +3816,7 @@ if (NOTBI (CPU (h_vbit))) { if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3830,7 +3832,7 @@ if (NOTBI (CPU (h_vbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3840,7 +3842,7 @@ if (NOTBI (CPU (h_vbit))) { if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3857,7 +3859,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3866,7 +3868,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3882,7 +3884,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3892,7 +3894,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3909,7 +3911,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3918,7 +3920,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3934,7 +3936,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3944,7 +3946,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3961,7 +3963,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3970,7 +3972,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3986,7 +3988,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -3996,7 +3998,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4013,7 +4015,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -4022,7 +4024,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4038,7 +4040,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -4048,7 +4050,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4065,7 +4067,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -4074,7 +4076,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4090,7 +4092,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -4100,7 +4102,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4117,7 +4119,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -4126,7 +4128,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4142,7 +4144,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4161,7 +4163,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4180,7 +4182,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4199,7 +4201,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4225,7 +4227,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4251,7 +4253,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4277,7 +4279,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmovr15pi.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4303,7 +4305,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4322,7 +4324,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4341,7 +4343,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4360,7 +4362,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4386,7 +4388,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4412,7 +4414,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4438,7 +4440,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_dmov2r15pd.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4464,7 +4466,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4483,7 +4485,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4502,7 +4504,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4517,7 +4519,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4532,7 +4534,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4547,7 +4549,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4562,7 +4564,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4577,7 +4579,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4596,7 +4598,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4615,7 +4617,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stilm.f +#define FLD(f) abuf->fields.sfmt_int.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4634,7 +4636,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addsp.f +#define FLD(f) abuf->fields.sfmt_addsp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4653,7 +4655,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_extsb.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4672,7 +4674,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_extub.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4691,7 +4693,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_extsh.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4710,7 +4712,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_extuh.f +#define FLD(f) abuf->fields.sfmt_add2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4729,7 +4731,7 @@ do { } while (0); /*nop*/ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldm0.f +#define FLD(f) abuf->fields.sfmt_ldm0.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4874,7 +4876,7 @@ if (ANDSI (FLD (f_reglist_low_ld), 128)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldm1.f +#define FLD(f) abuf->fields.sfmt_ldm1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -5011,7 +5013,7 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stm0.f +#define FLD(f) abuf->fields.sfmt_stm0.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -5156,7 +5158,7 @@ if (ANDSI (FLD (f_reglist_low_st), 128)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stm1.f +#define FLD(f) abuf->fields.sfmt_stm1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -5303,7 +5305,7 @@ if (ANDSI (FLD (f_reglist_hi_st), 128)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_enter.f +#define FLD(f) abuf->fields.sfmt_enter.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -5336,7 +5338,7 @@ if (ANDSI (FLD (f_reglist_hi_st), 128)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_leave.f +#define FLD(f) abuf->fields.sfmt_enter.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -5362,7 +5364,7 @@ if (ANDSI (FLD (f_reglist_hi_st), 128)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_xchb.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); diff --git a/sim/fr30/sem.c b/sim/fr30/sem.c index 40c1936..9d05ecd 100644 --- a/sim/fr30/sem.c +++ b/sim/fr30/sem.c @@ -32,9 +32,20 @@ with this program; if not, write to the Free Software Foundation, Inc., #undef GET_ATTR #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + /* x-invalid: --invalid-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -59,7 +70,7 @@ SEM_FN_NAME (fr30bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-after: --after-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -80,7 +91,7 @@ SEM_FN_NAME (fr30bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-before: --before-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -101,7 +112,7 @@ SEM_FN_NAME (fr30bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-cti-chain: --cti-chain-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -114,12 +125,12 @@ SEM_FN_NAME (fr30bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #if WITH_SCACHE_PBB_FR30BF #ifdef DEFINE_SWITCH vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); + pbb_br_type, pbb_br_npc); BREAK (sem); #else /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_TYPE (current_cpu), CPU_PBB_BR_NPC (current_cpu)); #endif #endif @@ -131,7 +142,7 @@ SEM_FN_NAME (fr30bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-chain: --chain-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -155,7 +166,7 @@ SEM_FN_NAME (fr30bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-begin: --begin-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -182,10 +193,10 @@ SEM_FN_NAME (fr30bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* add: add $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -227,10 +238,10 @@ SEM_FN_NAME (fr30bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addi: add $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -272,10 +283,10 @@ SEM_FN_NAME (fr30bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* add2: add2 $m4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,add2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add2.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -317,10 +328,10 @@ SEM_FN_NAME (fr30bf,add2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addc: addc $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -364,10 +375,10 @@ SEM_FN_NAME (fr30bf,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addn: addn $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,addn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -385,10 +396,10 @@ SEM_FN_NAME (fr30bf,addn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addni: addn $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,addni) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addni.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -406,10 +417,10 @@ SEM_FN_NAME (fr30bf,addni) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addn2: addn2 $m4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,addn2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addn2.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -427,10 +438,10 @@ SEM_FN_NAME (fr30bf,addn2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sub: sub $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -472,10 +483,10 @@ SEM_FN_NAME (fr30bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subc: subc $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addc.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -519,10 +530,10 @@ SEM_FN_NAME (fr30bf,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subn: subn $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,subn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addn.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -540,10 +551,10 @@ SEM_FN_NAME (fr30bf,subn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmp: cmp $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -582,10 +593,10 @@ SEM_FN_NAME (fr30bf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpi: cmp $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -624,10 +635,10 @@ SEM_FN_NAME (fr30bf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmp2: cmp2 $m4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,cmp2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp2.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -666,10 +677,10 @@ SEM_FN_NAME (fr30bf,cmp2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and: and $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -701,10 +712,10 @@ SEM_FN_NAME (fr30bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or: or $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -736,10 +747,10 @@ SEM_FN_NAME (fr30bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* eor: eor $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,eor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_and.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -771,10 +782,10 @@ SEM_FN_NAME (fr30bf,eor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andm: and $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,andm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -808,10 +819,10 @@ SEM_FN_NAME (fr30bf,andm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andh: andh $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,andh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -845,10 +856,10 @@ SEM_FN_NAME (fr30bf,andh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andb: andb $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,andb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -882,10 +893,10 @@ SEM_FN_NAME (fr30bf,andb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* orm: or $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,orm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -919,10 +930,10 @@ SEM_FN_NAME (fr30bf,orm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* orh: orh $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,orh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -956,10 +967,10 @@ SEM_FN_NAME (fr30bf,orh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* orb: orb $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,orb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -993,10 +1004,10 @@ SEM_FN_NAME (fr30bf,orb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* eorm: eor $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,eorm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andm.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1030,10 +1041,10 @@ SEM_FN_NAME (fr30bf,eorm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* eorh: eorh $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,eorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andh.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1067,10 +1078,10 @@ SEM_FN_NAME (fr30bf,eorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* eorb: eorb $Rj,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,eorb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andb.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1104,10 +1115,10 @@ SEM_FN_NAME (fr30bf,eorb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bandl: bandl $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bandl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1125,10 +1136,10 @@ SEM_FN_NAME (fr30bf,bandl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* borl: borl $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,borl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1146,10 +1157,10 @@ SEM_FN_NAME (fr30bf,borl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* beorl: beorl $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,beorl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1167,10 +1178,10 @@ SEM_FN_NAME (fr30bf,beorl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bandh: bandh $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bandh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1188,10 +1199,10 @@ SEM_FN_NAME (fr30bf,bandh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* borh: borh $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,borh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1209,10 +1220,10 @@ SEM_FN_NAME (fr30bf,borh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* beorh: beorh $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,beorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bandl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1230,10 +1241,10 @@ SEM_FN_NAME (fr30bf,beorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* btstl: btstl $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,btstl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1260,10 +1271,10 @@ SEM_FN_NAME (fr30bf,btstl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* btsth: btsth $u4,@$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,btsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_btstl.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1290,10 +1301,10 @@ SEM_FN_NAME (fr30bf,btsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mul: mul $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mul.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1335,10 +1346,10 @@ SEM_FN_NAME (fr30bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulu: mulu $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulu.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1380,10 +1391,10 @@ SEM_FN_NAME (fr30bf,mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulh: mulh $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,mulh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1413,10 +1424,10 @@ SEM_FN_NAME (fr30bf,mulh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* muluh: muluh $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,muluh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulh.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1446,10 +1457,10 @@ SEM_FN_NAME (fr30bf,muluh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* div0s: div0s $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,div0s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div0s.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1490,10 +1501,10 @@ if (NEBI (CPU (h_d0bit), 0)) { /* div0u: div0u $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,div0u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div0u.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1523,10 +1534,10 @@ SEM_FN_NAME (fr30bf,div0u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* div1: div1 $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,div1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div1.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1600,10 +1611,10 @@ if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) { /* div2: div2 $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,div2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div2.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1664,10 +1675,10 @@ if (EQSI (tmp_tmp, 0)) { /* div3: div3 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,div3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div3.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1689,10 +1700,10 @@ if (EQBI (CPU (h_zbit), 1)) { /* div4s: div4s */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,div4s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div4s.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1714,10 +1725,10 @@ if (EQBI (CPU (h_d1bit), 1)) { /* lsl: lsl $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1768,10 +1779,10 @@ if (NESI (tmp_shift, 0)) { /* lsli: lsl $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lsli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1822,10 +1833,10 @@ if (NESI (tmp_shift, 0)) { /* lsl2: lsl2 $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lsl2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1876,10 +1887,10 @@ if (NESI (tmp_shift, 0)) { /* lsr: lsr $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1930,10 +1941,10 @@ if (NESI (tmp_shift, 0)) { /* lsri: lsr $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lsri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1984,10 +1995,10 @@ if (NESI (tmp_shift, 0)) { /* lsr2: lsr2 $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lsr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2038,10 +2049,10 @@ if (NESI (tmp_shift, 0)) { /* asr: asr $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsl.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2092,10 +2103,10 @@ if (NESI (tmp_shift, 0)) { /* asri: asr $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,asri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2146,10 +2157,10 @@ if (NESI (tmp_shift, 0)) { /* asr2: asr2 $u4,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,asr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lsli.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2200,10 +2211,10 @@ if (NESI (tmp_shift, 0)) { /* ldi8: ldi:8 $i8,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_ldi8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2221,10 +2232,10 @@ SEM_FN_NAME (fr30bf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldi20: ldi:20 $i20,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldi20) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi20.f +#define FLD(f) abuf->fields.sfmt_ldi20.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2242,10 +2253,10 @@ SEM_FN_NAME (fr30bf,ldi20) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldi32: ldi:32 $i32,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldi32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi32.f +#define FLD(f) abuf->fields.sfmt_ldi32.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2263,10 +2274,10 @@ SEM_FN_NAME (fr30bf,ldi32) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld: ld @$Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2284,10 +2295,10 @@ SEM_FN_NAME (fr30bf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lduh: lduh @$Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2305,10 +2316,10 @@ SEM_FN_NAME (fr30bf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldub: ldub @$Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2326,10 +2337,10 @@ SEM_FN_NAME (fr30bf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr13: ld @($R13,$Rj),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2347,10 +2358,10 @@ SEM_FN_NAME (fr30bf,ldr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr13uh: lduh @($R13,$Rj),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr13uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2368,10 +2379,10 @@ SEM_FN_NAME (fr30bf,ldr13uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr13ub: ldub @($R13,$Rj),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr13ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr13.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2389,10 +2400,10 @@ SEM_FN_NAME (fr30bf,ldr13ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr14: ld @($R14,$disp10),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr14) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr14.f +#define FLD(f) abuf->fields.sfmt_ldr14.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2410,10 +2421,10 @@ SEM_FN_NAME (fr30bf,ldr14) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr14uh: lduh @($R14,$disp9),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr14uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr14uh.f +#define FLD(f) abuf->fields.sfmt_ldr14uh.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2431,10 +2442,10 @@ SEM_FN_NAME (fr30bf,ldr14uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr14ub: ldub @($R14,$disp8),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr14ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr14ub.f +#define FLD(f) abuf->fields.sfmt_ldr14ub.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2452,10 +2463,10 @@ SEM_FN_NAME (fr30bf,ldr14ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr15: ld @($R15,$udisp6),$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr15) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15.f +#define FLD(f) abuf->fields.sfmt_ldr15.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2473,10 +2484,10 @@ SEM_FN_NAME (fr30bf,ldr15) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr15gr: ld @$R15+,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15gr.f +#define FLD(f) abuf->fields.sfmt_ldr15gr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2505,10 +2516,10 @@ if (NESI (FLD (f_Ri), 15)) { /* ldr15dr: ld @$R15+,$Rs2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2535,10 +2546,10 @@ SEM_FN_NAME (fr30bf,ldr15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldr15ps: ld @$R15+,$ps */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldr15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldr15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2563,10 +2574,10 @@ SEM_FN_NAME (fr30bf,ldr15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st: st $Ri,@$Rj */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2584,10 +2595,10 @@ SEM_FN_NAME (fr30bf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sth: sth $Ri,@$Rj */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2605,10 +2616,10 @@ SEM_FN_NAME (fr30bf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stb: stb $Ri,@$Rj */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2626,10 +2637,10 @@ SEM_FN_NAME (fr30bf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str13: st $Ri,@($R13,$Rj) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2647,10 +2658,10 @@ SEM_FN_NAME (fr30bf,str13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str13h: sth $Ri,@($R13,$Rj) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2668,10 +2679,10 @@ SEM_FN_NAME (fr30bf,str13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str13b: stb $Ri,@($R13,$Rj) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str13.f +#define FLD(f) abuf->fields.sfmt_str13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2689,10 +2700,10 @@ SEM_FN_NAME (fr30bf,str13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str14: st $Ri,@($R14,$disp10) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str14) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str14.f +#define FLD(f) abuf->fields.sfmt_str14.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2710,10 +2721,10 @@ SEM_FN_NAME (fr30bf,str14) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str14h: sth $Ri,@($R14,$disp9) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str14h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str14h.f +#define FLD(f) abuf->fields.sfmt_str14h.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2731,10 +2742,10 @@ SEM_FN_NAME (fr30bf,str14h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str14b: stb $Ri,@($R14,$disp8) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str14b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str14b.f +#define FLD(f) abuf->fields.sfmt_str14b.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2752,10 +2763,10 @@ SEM_FN_NAME (fr30bf,str14b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str15: st $Ri,@($R15,$udisp6) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str15) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str15.f +#define FLD(f) abuf->fields.sfmt_str15.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2773,10 +2784,10 @@ SEM_FN_NAME (fr30bf,str15) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str15gr: st $Ri,@-$R15 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str15gr.f +#define FLD(f) abuf->fields.sfmt_str15gr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2803,10 +2814,10 @@ SEM_FN_NAME (fr30bf,str15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str15dr: st $Rs2,@-$R15 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str15dr.f +#define FLD(f) abuf->fields.sfmt_ldr15dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2833,10 +2844,10 @@ SEM_FN_NAME (fr30bf,str15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* str15ps: st $ps,@-$R15 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,str15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_str15ps.f +#define FLD(f) abuf->fields.sfmt_addsp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2861,10 +2872,10 @@ SEM_FN_NAME (fr30bf,str15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mov: mov $Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,mov) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mov.f +#define FLD(f) abuf->fields.sfmt_ldr13.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2882,10 +2893,10 @@ SEM_FN_NAME (fr30bf,mov) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movdr: mov $Rs1,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,movdr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movdr.f +#define FLD(f) abuf->fields.sfmt_movdr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2903,10 +2914,10 @@ SEM_FN_NAME (fr30bf,movdr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movps: mov $ps,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,movps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movps.f +#define FLD(f) abuf->fields.sfmt_movdr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2924,10 +2935,10 @@ SEM_FN_NAME (fr30bf,movps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mov2dr: mov $Ri,$Rs1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,mov2dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mov2dr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2945,10 +2956,10 @@ SEM_FN_NAME (fr30bf,mov2dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mov2ps: mov $Ri,$ps */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,mov2ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mov2ps.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2966,10 +2977,10 @@ SEM_FN_NAME (fr30bf,mov2ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* jmp: jmp @$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2989,10 +3000,10 @@ SEM_FN_NAME (fr30bf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* jmpd: jmp:d @$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,jmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3014,10 +3025,10 @@ SEM_FN_NAME (fr30bf,jmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* callr: call @$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,callr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3044,10 +3055,10 @@ SEM_FN_NAME (fr30bf,callr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* callrd: call:d @$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,callrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callr.f +#define FLD(f) abuf->fields.sfmt_mov2dr.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3076,10 +3087,10 @@ SEM_FN_NAME (fr30bf,callrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* call: call $label12 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3094,7 +3105,7 @@ SEM_FN_NAME (fr30bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg) } { USI opval = FLD (i_label12); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -3106,10 +3117,10 @@ SEM_FN_NAME (fr30bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* calld: call:d $label12 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,calld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_call.f +#define FLD(f) abuf->fields.sfmt_call.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3125,7 +3136,7 @@ SEM_FN_NAME (fr30bf,calld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) } { USI opval = FLD (i_label12); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -3138,10 +3149,10 @@ SEM_FN_NAME (fr30bf,calld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ret: ret */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3161,10 +3172,10 @@ SEM_FN_NAME (fr30bf,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ret:d: ret:d */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ret_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3186,10 +3197,10 @@ SEM_FN_NAME (fr30bf,ret_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* int: int $u8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,int) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_int.f +#define FLD(f) abuf->fields.sfmt_int.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3214,10 +3225,10 @@ SEM_FN_NAME (fr30bf,int) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* inte: inte */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,inte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_inte.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3242,10 +3253,10 @@ SEM_FN_NAME (fr30bf,inte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* reti: reti */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,reti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_reti.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3316,10 +3327,10 @@ if (EQBI (GET_H_SBIT (), 0)) { /* brad: bra:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,brad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3329,7 +3340,7 @@ SEM_FN_NAME (fr30bf,brad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -3341,10 +3352,10 @@ SEM_FN_NAME (fr30bf,brad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bra: bra $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_brad.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3353,7 +3364,7 @@ SEM_FN_NAME (fr30bf,bra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3364,10 +3375,10 @@ SEM_FN_NAME (fr30bf,bra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bnod: bno:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bnod) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3383,10 +3394,10 @@ do { } while (0); /*nop*/ /* bno: bno $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3400,10 +3411,10 @@ do { } while (0); /*nop*/ /* beqd: beq:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,beqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3414,7 +3425,7 @@ SEM_FN_NAME (fr30bf,beqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_zbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3429,10 +3440,10 @@ if (CPU (h_zbit)) { /* beq: beq $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3442,7 +3453,7 @@ SEM_FN_NAME (fr30bf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_zbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3456,10 +3467,10 @@ if (CPU (h_zbit)) { /* bned: bne:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bned) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3470,7 +3481,7 @@ SEM_FN_NAME (fr30bf,bned) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3485,10 +3496,10 @@ if (NOTBI (CPU (h_zbit))) { /* bne: bne $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3498,7 +3509,7 @@ SEM_FN_NAME (fr30bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3512,10 +3523,10 @@ if (NOTBI (CPU (h_zbit))) { /* bcd: bc:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bcd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3526,7 +3537,7 @@ SEM_FN_NAME (fr30bf,bcd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_cbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3541,10 +3552,10 @@ if (CPU (h_cbit)) { /* bc: bc $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3554,7 +3565,7 @@ SEM_FN_NAME (fr30bf,bc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_cbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3568,10 +3579,10 @@ if (CPU (h_cbit)) { /* bncd: bnc:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bncd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3582,7 +3593,7 @@ SEM_FN_NAME (fr30bf,bncd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3597,10 +3608,10 @@ if (NOTBI (CPU (h_cbit))) { /* bnc: bnc $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bcd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3610,7 +3621,7 @@ SEM_FN_NAME (fr30bf,bnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3624,10 +3635,10 @@ if (NOTBI (CPU (h_cbit))) { /* bnd: bn:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bnd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3638,7 +3649,7 @@ SEM_FN_NAME (fr30bf,bnd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_nbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3653,10 +3664,10 @@ if (CPU (h_nbit)) { /* bn: bn $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3666,7 +3677,7 @@ SEM_FN_NAME (fr30bf,bn) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_nbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3680,10 +3691,10 @@ if (CPU (h_nbit)) { /* bpd: bp:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3694,7 +3705,7 @@ SEM_FN_NAME (fr30bf,bpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3709,10 +3720,10 @@ if (NOTBI (CPU (h_nbit))) { /* bp: bp $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bnd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3722,7 +3733,7 @@ SEM_FN_NAME (fr30bf,bp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3736,10 +3747,10 @@ if (NOTBI (CPU (h_nbit))) { /* bvd: bv:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3750,7 +3761,7 @@ SEM_FN_NAME (fr30bf,bvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_vbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3765,10 +3776,10 @@ if (CPU (h_vbit)) { /* bv: bv $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3778,7 +3789,7 @@ SEM_FN_NAME (fr30bf,bv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_vbit)) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3792,10 +3803,10 @@ if (CPU (h_vbit)) { /* bnvd: bnv:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bnvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3806,7 +3817,7 @@ SEM_FN_NAME (fr30bf,bnvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3821,10 +3832,10 @@ if (NOTBI (CPU (h_vbit))) { /* bnv: bnv $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bvd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3834,7 +3845,7 @@ SEM_FN_NAME (fr30bf,bnv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3848,10 +3859,10 @@ if (NOTBI (CPU (h_vbit))) { /* bltd: blt:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bltd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3862,7 +3873,7 @@ SEM_FN_NAME (fr30bf,bltd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3877,10 +3888,10 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { /* blt: blt $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,blt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3890,7 +3901,7 @@ SEM_FN_NAME (fr30bf,blt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3904,10 +3915,10 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { /* bged: bge:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bged) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3918,7 +3929,7 @@ SEM_FN_NAME (fr30bf,bged) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3933,10 +3944,10 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { /* bge: bge $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bltd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3946,7 +3957,7 @@ SEM_FN_NAME (fr30bf,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3960,10 +3971,10 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { /* bled: ble:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bled) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3974,7 +3985,7 @@ SEM_FN_NAME (fr30bf,bled) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -3989,10 +4000,10 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { /* ble: ble $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4002,7 +4013,7 @@ SEM_FN_NAME (fr30bf,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4016,10 +4027,10 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { /* bgtd: bgt:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4030,7 +4041,7 @@ SEM_FN_NAME (fr30bf,bgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4045,10 +4056,10 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { /* bgt: bgt $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bled.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4058,7 +4069,7 @@ SEM_FN_NAME (fr30bf,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4072,10 +4083,10 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { /* blsd: bls:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,blsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4086,7 +4097,7 @@ SEM_FN_NAME (fr30bf,blsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4101,10 +4112,10 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { /* bls: bls $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4114,7 +4125,7 @@ SEM_FN_NAME (fr30bf,bls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4128,10 +4139,10 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { /* bhid: bhi:d $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bhid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4142,7 +4153,7 @@ SEM_FN_NAME (fr30bf,bhid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4157,10 +4168,10 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { /* bhi: bhi $label9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,bhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_blsd.f +#define FLD(f) abuf->fields.sfmt_brad.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4170,7 +4181,7 @@ SEM_FN_NAME (fr30bf,bhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -4184,10 +4195,10 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { /* dmovr13: dmov $R13,@$dir10 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4205,10 +4216,10 @@ SEM_FN_NAME (fr30bf,dmovr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmovr13h: dmovh $R13,@$dir9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4226,10 +4237,10 @@ SEM_FN_NAME (fr30bf,dmovr13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmovr13b: dmovb $R13,@$dir8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4247,10 +4258,10 @@ SEM_FN_NAME (fr30bf,dmovr13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmovr13pi: dmov @$R13+,@$dir10 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4275,10 +4286,10 @@ SEM_FN_NAME (fr30bf,dmovr13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmovr13pih: dmovh @$R13+,@$dir9 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4303,10 +4314,10 @@ SEM_FN_NAME (fr30bf,dmovr13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmovr13pib: dmovb @$R13+,@$dir8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4331,10 +4342,10 @@ SEM_FN_NAME (fr30bf,dmovr13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmovr15pi: dmov @$R15+,@$dir10 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmovr15pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmovr15pi.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4359,10 +4370,10 @@ SEM_FN_NAME (fr30bf,dmovr15pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r13: dmov @$dir10,$R13 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4380,10 +4391,10 @@ SEM_FN_NAME (fr30bf,dmov2r13) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r13h: dmovh @$dir9,$R13 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13h.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4401,10 +4412,10 @@ SEM_FN_NAME (fr30bf,dmov2r13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r13b: dmovb @$dir8,$R13 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13b.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4422,10 +4433,10 @@ SEM_FN_NAME (fr30bf,dmov2r13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r13pi: dmov @$dir10,@$R13+ */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13pi.f +#define FLD(f) abuf->fields.sfmt_dmovr13pi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4450,10 +4461,10 @@ SEM_FN_NAME (fr30bf,dmov2r13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r13pih: dmovh @$dir9,@$R13+ */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13pih.f +#define FLD(f) abuf->fields.sfmt_dmovr13pih.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4478,10 +4489,10 @@ SEM_FN_NAME (fr30bf,dmov2r13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r13pib: dmovb @$dir8,@$R13+ */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r13pib.f +#define FLD(f) abuf->fields.sfmt_dmovr13pib.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4506,10 +4517,10 @@ SEM_FN_NAME (fr30bf,dmov2r13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* dmov2r15pd: dmov @$dir10,@-$R15 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,dmov2r15pd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_dmov2r15pd.f +#define FLD(f) abuf->fields.sfmt_dmovr15pi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4534,10 +4545,10 @@ SEM_FN_NAME (fr30bf,dmov2r15pd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldres: ldres @$Ri+,$u4 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldres) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4555,10 +4566,10 @@ SEM_FN_NAME (fr30bf,ldres) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stres: stres $u4,@$Ri+ */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,stres) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldres.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4576,10 +4587,10 @@ SEM_FN_NAME (fr30bf,stres) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* copop: copop $u4c,$ccc,$CRj,$CRi */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,copop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4593,10 +4604,10 @@ do { } while (0); /*nop*/ /* copld: copld $u4c,$ccc,$Rjc,$CRi */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,copld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4610,10 +4621,10 @@ do { } while (0); /*nop*/ /* copst: copst $u4c,$ccc,$CRj,$Ric */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,copst) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4627,10 +4638,10 @@ do { } while (0); /*nop*/ /* copsv: copsv $u4c,$ccc,$CRj,$Ric */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,copsv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_copop.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4644,10 +4655,10 @@ do { } while (0); /*nop*/ /* nop: nop */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_bnod.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4661,10 +4672,10 @@ do { } while (0); /*nop*/ /* andccr: andccr $u8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,andccr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4682,10 +4693,10 @@ SEM_FN_NAME (fr30bf,andccr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* orccr: orccr $u8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,orccr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_andccr.f +#define FLD(f) abuf->fields.sfmt_int.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4703,10 +4714,10 @@ SEM_FN_NAME (fr30bf,orccr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stilm: stilm $u8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,stilm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stilm.f +#define FLD(f) abuf->fields.sfmt_int.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4724,10 +4735,10 @@ SEM_FN_NAME (fr30bf,stilm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addsp: addsp $s10 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,addsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addsp.f +#define FLD(f) abuf->fields.sfmt_addsp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4745,10 +4756,10 @@ SEM_FN_NAME (fr30bf,addsp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* extsb: extsb $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,extsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_extsb.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4766,10 +4777,10 @@ SEM_FN_NAME (fr30bf,extsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* extub: extub $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,extub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_extub.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4787,10 +4798,10 @@ SEM_FN_NAME (fr30bf,extub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* extsh: extsh $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,extsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_extsh.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4808,10 +4819,10 @@ SEM_FN_NAME (fr30bf,extsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* extuh: extuh $Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,extuh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_extuh.f +#define FLD(f) abuf->fields.sfmt_add2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4829,10 +4840,10 @@ SEM_FN_NAME (fr30bf,extuh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldm0: ldm0 ($reglist_low_ld) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldm0.f +#define FLD(f) abuf->fields.sfmt_ldm0.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4976,10 +4987,10 @@ if (ANDSI (FLD (f_reglist_low_ld), 128)) { /* ldm1: ldm1 ($reglist_hi_ld) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,ldm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldm1.f +#define FLD(f) abuf->fields.sfmt_ldm1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5115,10 +5126,10 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { /* stm0: stm0 ($reglist_low_st) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,stm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stm0.f +#define FLD(f) abuf->fields.sfmt_stm0.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5262,10 +5273,10 @@ if (ANDSI (FLD (f_reglist_low_st), 128)) { /* stm1: stm1 ($reglist_hi_st) */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,stm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stm1.f +#define FLD(f) abuf->fields.sfmt_stm1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5411,10 +5422,10 @@ if (ANDSI (FLD (f_reglist_hi_st), 128)) { /* enter: enter $u10 */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,enter) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_enter.f +#define FLD(f) abuf->fields.sfmt_enter.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5446,10 +5457,10 @@ SEM_FN_NAME (fr30bf,enter) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* leave: leave */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,leave) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_leave.f +#define FLD(f) abuf->fields.sfmt_enter.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5474,10 +5485,10 @@ SEM_FN_NAME (fr30bf,leave) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xchb: xchb @$Rj,$Ri */ -SEM_PC +static SEM_PC SEM_FN_NAME (fr30bf,xchb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_xchb.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5502,3 +5513,198 @@ SEM_FN_NAME (fr30bf,xchb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { FR30BF_INSN_X_INVALID, SEM_FN_NAME (fr30bf,x_invalid) }, + { FR30BF_INSN_X_AFTER, SEM_FN_NAME (fr30bf,x_after) }, + { FR30BF_INSN_X_BEFORE, SEM_FN_NAME (fr30bf,x_before) }, + { FR30BF_INSN_X_CTI_CHAIN, SEM_FN_NAME (fr30bf,x_cti_chain) }, + { FR30BF_INSN_X_CHAIN, SEM_FN_NAME (fr30bf,x_chain) }, + { FR30BF_INSN_X_BEGIN, SEM_FN_NAME (fr30bf,x_begin) }, + { FR30BF_INSN_ADD, SEM_FN_NAME (fr30bf,add) }, + { FR30BF_INSN_ADDI, SEM_FN_NAME (fr30bf,addi) }, + { FR30BF_INSN_ADD2, SEM_FN_NAME (fr30bf,add2) }, + { FR30BF_INSN_ADDC, SEM_FN_NAME (fr30bf,addc) }, + { FR30BF_INSN_ADDN, SEM_FN_NAME (fr30bf,addn) }, + { FR30BF_INSN_ADDNI, SEM_FN_NAME (fr30bf,addni) }, + { FR30BF_INSN_ADDN2, SEM_FN_NAME (fr30bf,addn2) }, + { FR30BF_INSN_SUB, SEM_FN_NAME (fr30bf,sub) }, + { FR30BF_INSN_SUBC, SEM_FN_NAME (fr30bf,subc) }, + { FR30BF_INSN_SUBN, SEM_FN_NAME (fr30bf,subn) }, + { FR30BF_INSN_CMP, SEM_FN_NAME (fr30bf,cmp) }, + { FR30BF_INSN_CMPI, SEM_FN_NAME (fr30bf,cmpi) }, + { FR30BF_INSN_CMP2, SEM_FN_NAME (fr30bf,cmp2) }, + { FR30BF_INSN_AND, SEM_FN_NAME (fr30bf,and) }, + { FR30BF_INSN_OR, SEM_FN_NAME (fr30bf,or) }, + { FR30BF_INSN_EOR, SEM_FN_NAME (fr30bf,eor) }, + { FR30BF_INSN_ANDM, SEM_FN_NAME (fr30bf,andm) }, + { FR30BF_INSN_ANDH, SEM_FN_NAME (fr30bf,andh) }, + { FR30BF_INSN_ANDB, SEM_FN_NAME (fr30bf,andb) }, + { FR30BF_INSN_ORM, SEM_FN_NAME (fr30bf,orm) }, + { FR30BF_INSN_ORH, SEM_FN_NAME (fr30bf,orh) }, + { FR30BF_INSN_ORB, SEM_FN_NAME (fr30bf,orb) }, + { FR30BF_INSN_EORM, SEM_FN_NAME (fr30bf,eorm) }, + { FR30BF_INSN_EORH, SEM_FN_NAME (fr30bf,eorh) }, + { FR30BF_INSN_EORB, SEM_FN_NAME (fr30bf,eorb) }, + { FR30BF_INSN_BANDL, SEM_FN_NAME (fr30bf,bandl) }, + { FR30BF_INSN_BORL, SEM_FN_NAME (fr30bf,borl) }, + { FR30BF_INSN_BEORL, SEM_FN_NAME (fr30bf,beorl) }, + { FR30BF_INSN_BANDH, SEM_FN_NAME (fr30bf,bandh) }, + { FR30BF_INSN_BORH, SEM_FN_NAME (fr30bf,borh) }, + { FR30BF_INSN_BEORH, SEM_FN_NAME (fr30bf,beorh) }, + { FR30BF_INSN_BTSTL, SEM_FN_NAME (fr30bf,btstl) }, + { FR30BF_INSN_BTSTH, SEM_FN_NAME (fr30bf,btsth) }, + { FR30BF_INSN_MUL, SEM_FN_NAME (fr30bf,mul) }, + { FR30BF_INSN_MULU, SEM_FN_NAME (fr30bf,mulu) }, + { FR30BF_INSN_MULH, SEM_FN_NAME (fr30bf,mulh) }, + { FR30BF_INSN_MULUH, SEM_FN_NAME (fr30bf,muluh) }, + { FR30BF_INSN_DIV0S, SEM_FN_NAME (fr30bf,div0s) }, + { FR30BF_INSN_DIV0U, SEM_FN_NAME (fr30bf,div0u) }, + { FR30BF_INSN_DIV1, SEM_FN_NAME (fr30bf,div1) }, + { FR30BF_INSN_DIV2, SEM_FN_NAME (fr30bf,div2) }, + { FR30BF_INSN_DIV3, SEM_FN_NAME (fr30bf,div3) }, + { FR30BF_INSN_DIV4S, SEM_FN_NAME (fr30bf,div4s) }, + { FR30BF_INSN_LSL, SEM_FN_NAME (fr30bf,lsl) }, + { FR30BF_INSN_LSLI, SEM_FN_NAME (fr30bf,lsli) }, + { FR30BF_INSN_LSL2, SEM_FN_NAME (fr30bf,lsl2) }, + { FR30BF_INSN_LSR, SEM_FN_NAME (fr30bf,lsr) }, + { FR30BF_INSN_LSRI, SEM_FN_NAME (fr30bf,lsri) }, + { FR30BF_INSN_LSR2, SEM_FN_NAME (fr30bf,lsr2) }, + { FR30BF_INSN_ASR, SEM_FN_NAME (fr30bf,asr) }, + { FR30BF_INSN_ASRI, SEM_FN_NAME (fr30bf,asri) }, + { FR30BF_INSN_ASR2, SEM_FN_NAME (fr30bf,asr2) }, + { FR30BF_INSN_LDI8, SEM_FN_NAME (fr30bf,ldi8) }, + { FR30BF_INSN_LDI20, SEM_FN_NAME (fr30bf,ldi20) }, + { FR30BF_INSN_LDI32, SEM_FN_NAME (fr30bf,ldi32) }, + { FR30BF_INSN_LD, SEM_FN_NAME (fr30bf,ld) }, + { FR30BF_INSN_LDUH, SEM_FN_NAME (fr30bf,lduh) }, + { FR30BF_INSN_LDUB, SEM_FN_NAME (fr30bf,ldub) }, + { FR30BF_INSN_LDR13, SEM_FN_NAME (fr30bf,ldr13) }, + { FR30BF_INSN_LDR13UH, SEM_FN_NAME (fr30bf,ldr13uh) }, + { FR30BF_INSN_LDR13UB, SEM_FN_NAME (fr30bf,ldr13ub) }, + { FR30BF_INSN_LDR14, SEM_FN_NAME (fr30bf,ldr14) }, + { FR30BF_INSN_LDR14UH, SEM_FN_NAME (fr30bf,ldr14uh) }, + { FR30BF_INSN_LDR14UB, SEM_FN_NAME (fr30bf,ldr14ub) }, + { FR30BF_INSN_LDR15, SEM_FN_NAME (fr30bf,ldr15) }, + { FR30BF_INSN_LDR15GR, SEM_FN_NAME (fr30bf,ldr15gr) }, + { FR30BF_INSN_LDR15DR, SEM_FN_NAME (fr30bf,ldr15dr) }, + { FR30BF_INSN_LDR15PS, SEM_FN_NAME (fr30bf,ldr15ps) }, + { FR30BF_INSN_ST, SEM_FN_NAME (fr30bf,st) }, + { FR30BF_INSN_STH, SEM_FN_NAME (fr30bf,sth) }, + { FR30BF_INSN_STB, SEM_FN_NAME (fr30bf,stb) }, + { FR30BF_INSN_STR13, SEM_FN_NAME (fr30bf,str13) }, + { FR30BF_INSN_STR13H, SEM_FN_NAME (fr30bf,str13h) }, + { FR30BF_INSN_STR13B, SEM_FN_NAME (fr30bf,str13b) }, + { FR30BF_INSN_STR14, SEM_FN_NAME (fr30bf,str14) }, + { FR30BF_INSN_STR14H, SEM_FN_NAME (fr30bf,str14h) }, + { FR30BF_INSN_STR14B, SEM_FN_NAME (fr30bf,str14b) }, + { FR30BF_INSN_STR15, SEM_FN_NAME (fr30bf,str15) }, + { FR30BF_INSN_STR15GR, SEM_FN_NAME (fr30bf,str15gr) }, + { FR30BF_INSN_STR15DR, SEM_FN_NAME (fr30bf,str15dr) }, + { FR30BF_INSN_STR15PS, SEM_FN_NAME (fr30bf,str15ps) }, + { FR30BF_INSN_MOV, SEM_FN_NAME (fr30bf,mov) }, + { FR30BF_INSN_MOVDR, SEM_FN_NAME (fr30bf,movdr) }, + { FR30BF_INSN_MOVPS, SEM_FN_NAME (fr30bf,movps) }, + { FR30BF_INSN_MOV2DR, SEM_FN_NAME (fr30bf,mov2dr) }, + { FR30BF_INSN_MOV2PS, SEM_FN_NAME (fr30bf,mov2ps) }, + { FR30BF_INSN_JMP, SEM_FN_NAME (fr30bf,jmp) }, + { FR30BF_INSN_JMPD, SEM_FN_NAME (fr30bf,jmpd) }, + { FR30BF_INSN_CALLR, SEM_FN_NAME (fr30bf,callr) }, + { FR30BF_INSN_CALLRD, SEM_FN_NAME (fr30bf,callrd) }, + { FR30BF_INSN_CALL, SEM_FN_NAME (fr30bf,call) }, + { FR30BF_INSN_CALLD, SEM_FN_NAME (fr30bf,calld) }, + { FR30BF_INSN_RET, SEM_FN_NAME (fr30bf,ret) }, + { FR30BF_INSN_RET_D, SEM_FN_NAME (fr30bf,ret_d) }, + { FR30BF_INSN_INT, SEM_FN_NAME (fr30bf,int) }, + { FR30BF_INSN_INTE, SEM_FN_NAME (fr30bf,inte) }, + { FR30BF_INSN_RETI, SEM_FN_NAME (fr30bf,reti) }, + { FR30BF_INSN_BRAD, SEM_FN_NAME (fr30bf,brad) }, + { FR30BF_INSN_BRA, SEM_FN_NAME (fr30bf,bra) }, + { FR30BF_INSN_BNOD, SEM_FN_NAME (fr30bf,bnod) }, + { FR30BF_INSN_BNO, SEM_FN_NAME (fr30bf,bno) }, + { FR30BF_INSN_BEQD, SEM_FN_NAME (fr30bf,beqd) }, + { FR30BF_INSN_BEQ, SEM_FN_NAME (fr30bf,beq) }, + { FR30BF_INSN_BNED, SEM_FN_NAME (fr30bf,bned) }, + { FR30BF_INSN_BNE, SEM_FN_NAME (fr30bf,bne) }, + { FR30BF_INSN_BCD, SEM_FN_NAME (fr30bf,bcd) }, + { FR30BF_INSN_BC, SEM_FN_NAME (fr30bf,bc) }, + { FR30BF_INSN_BNCD, SEM_FN_NAME (fr30bf,bncd) }, + { FR30BF_INSN_BNC, SEM_FN_NAME (fr30bf,bnc) }, + { FR30BF_INSN_BND, SEM_FN_NAME (fr30bf,bnd) }, + { FR30BF_INSN_BN, SEM_FN_NAME (fr30bf,bn) }, + { FR30BF_INSN_BPD, SEM_FN_NAME (fr30bf,bpd) }, + { FR30BF_INSN_BP, SEM_FN_NAME (fr30bf,bp) }, + { FR30BF_INSN_BVD, SEM_FN_NAME (fr30bf,bvd) }, + { FR30BF_INSN_BV, SEM_FN_NAME (fr30bf,bv) }, + { FR30BF_INSN_BNVD, SEM_FN_NAME (fr30bf,bnvd) }, + { FR30BF_INSN_BNV, SEM_FN_NAME (fr30bf,bnv) }, + { FR30BF_INSN_BLTD, SEM_FN_NAME (fr30bf,bltd) }, + { FR30BF_INSN_BLT, SEM_FN_NAME (fr30bf,blt) }, + { FR30BF_INSN_BGED, SEM_FN_NAME (fr30bf,bged) }, + { FR30BF_INSN_BGE, SEM_FN_NAME (fr30bf,bge) }, + { FR30BF_INSN_BLED, SEM_FN_NAME (fr30bf,bled) }, + { FR30BF_INSN_BLE, SEM_FN_NAME (fr30bf,ble) }, + { FR30BF_INSN_BGTD, SEM_FN_NAME (fr30bf,bgtd) }, + { FR30BF_INSN_BGT, SEM_FN_NAME (fr30bf,bgt) }, + { FR30BF_INSN_BLSD, SEM_FN_NAME (fr30bf,blsd) }, + { FR30BF_INSN_BLS, SEM_FN_NAME (fr30bf,bls) }, + { FR30BF_INSN_BHID, SEM_FN_NAME (fr30bf,bhid) }, + { FR30BF_INSN_BHI, SEM_FN_NAME (fr30bf,bhi) }, + { FR30BF_INSN_DMOVR13, SEM_FN_NAME (fr30bf,dmovr13) }, + { FR30BF_INSN_DMOVR13H, SEM_FN_NAME (fr30bf,dmovr13h) }, + { FR30BF_INSN_DMOVR13B, SEM_FN_NAME (fr30bf,dmovr13b) }, + { FR30BF_INSN_DMOVR13PI, SEM_FN_NAME (fr30bf,dmovr13pi) }, + { FR30BF_INSN_DMOVR13PIH, SEM_FN_NAME (fr30bf,dmovr13pih) }, + { FR30BF_INSN_DMOVR13PIB, SEM_FN_NAME (fr30bf,dmovr13pib) }, + { FR30BF_INSN_DMOVR15PI, SEM_FN_NAME (fr30bf,dmovr15pi) }, + { FR30BF_INSN_DMOV2R13, SEM_FN_NAME (fr30bf,dmov2r13) }, + { FR30BF_INSN_DMOV2R13H, SEM_FN_NAME (fr30bf,dmov2r13h) }, + { FR30BF_INSN_DMOV2R13B, SEM_FN_NAME (fr30bf,dmov2r13b) }, + { FR30BF_INSN_DMOV2R13PI, SEM_FN_NAME (fr30bf,dmov2r13pi) }, + { FR30BF_INSN_DMOV2R13PIH, SEM_FN_NAME (fr30bf,dmov2r13pih) }, + { FR30BF_INSN_DMOV2R13PIB, SEM_FN_NAME (fr30bf,dmov2r13pib) }, + { FR30BF_INSN_DMOV2R15PD, SEM_FN_NAME (fr30bf,dmov2r15pd) }, + { FR30BF_INSN_LDRES, SEM_FN_NAME (fr30bf,ldres) }, + { FR30BF_INSN_STRES, SEM_FN_NAME (fr30bf,stres) }, + { FR30BF_INSN_COPOP, SEM_FN_NAME (fr30bf,copop) }, + { FR30BF_INSN_COPLD, SEM_FN_NAME (fr30bf,copld) }, + { FR30BF_INSN_COPST, SEM_FN_NAME (fr30bf,copst) }, + { FR30BF_INSN_COPSV, SEM_FN_NAME (fr30bf,copsv) }, + { FR30BF_INSN_NOP, SEM_FN_NAME (fr30bf,nop) }, + { FR30BF_INSN_ANDCCR, SEM_FN_NAME (fr30bf,andccr) }, + { FR30BF_INSN_ORCCR, SEM_FN_NAME (fr30bf,orccr) }, + { FR30BF_INSN_STILM, SEM_FN_NAME (fr30bf,stilm) }, + { FR30BF_INSN_ADDSP, SEM_FN_NAME (fr30bf,addsp) }, + { FR30BF_INSN_EXTSB, SEM_FN_NAME (fr30bf,extsb) }, + { FR30BF_INSN_EXTUB, SEM_FN_NAME (fr30bf,extub) }, + { FR30BF_INSN_EXTSH, SEM_FN_NAME (fr30bf,extsh) }, + { FR30BF_INSN_EXTUH, SEM_FN_NAME (fr30bf,extuh) }, + { FR30BF_INSN_LDM0, SEM_FN_NAME (fr30bf,ldm0) }, + { FR30BF_INSN_LDM1, SEM_FN_NAME (fr30bf,ldm1) }, + { FR30BF_INSN_STM0, SEM_FN_NAME (fr30bf,stm0) }, + { FR30BF_INSN_STM1, SEM_FN_NAME (fr30bf,stm1) }, + { FR30BF_INSN_ENTER, SEM_FN_NAME (fr30bf,enter) }, + { FR30BF_INSN_LEAVE, SEM_FN_NAME (fr30bf,leave) }, + { FR30BF_INSN_XCHB, SEM_FN_NAME (fr30bf,xchb) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (fr30bf,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { +#if FAST_P + idesc_table[sf->index].sem_fast = sf->fn; +#else + idesc_table[sf->index].sem_full = sf->fn; +#endif + } +} + diff --git a/sim/i960/ChangeLog b/sim/i960/ChangeLog index 4978b8b..f6582fc 100644 --- a/sim/i960/ChangeLog +++ b/sim/i960/ChangeLog @@ -1,3 +1,12 @@ +1999-08-09 Doug Evans + + * cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild. + +1999-08-04 Doug Evans + + * cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild. + * i960-desc.h: Rebuild. + 1999-05-08 Felix Lee * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/i960/cpu.h b/sim/i960/cpu.h index 9887906..17701d3 100644 --- a/sim/i960/cpu.h +++ b/sim/i960/cpu.h @@ -72,1485 +72,208 @@ typedef struct { int empty; } MODEL_I960CA_DATA; +/* Instruction argument buffer. */ + union sem_fields { - struct { /* empty sformat for unspecified field list */ - int empty; - } fmt_empty; - struct { /* e.g. mulo $src1, $src2, $dst */ - SI * i_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src1; - unsigned char in_src2; - unsigned char out_dst; - } fmt_mulo; - struct { /* e.g. mulo $lit1, $src2, $dst */ - UINT f_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src2; - unsigned char out_dst; - } fmt_mulo1; - struct { /* e.g. mulo $src1, $lit2, $dst */ - UINT f_src2; - SI * i_src1; - SI * i_dst; - unsigned char in_src1; - unsigned char out_dst; - } fmt_mulo2; - struct { /* e.g. mulo $lit1, $lit2, $dst */ - UINT f_src1; - UINT f_src2; - SI * i_dst; - unsigned char out_dst; - } fmt_mulo3; - struct { /* e.g. notbit $src1, $src2, $dst */ - SI * i_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src1; - unsigned char in_src2; - unsigned char out_dst; - } fmt_notbit; - struct { /* e.g. notbit $lit1, $src2, $dst */ - UINT f_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src2; - unsigned char out_dst; - } fmt_notbit1; - struct { /* e.g. notbit $src1, $lit2, $dst */ - UINT f_src2; - SI * i_src1; - SI * i_dst; - unsigned char in_src1; - unsigned char out_dst; - } fmt_notbit2; - struct { /* e.g. notbit $lit1, $lit2, $dst */ - UINT f_src1; - UINT f_src2; - SI * i_dst; - unsigned char out_dst; - } fmt_notbit3; - struct { /* e.g. not $src1, $src2, $dst */ - SI * i_src1; - SI * i_dst; - unsigned char in_src1; - unsigned char out_dst; - } fmt_not; - struct { /* e.g. not $lit1, $src2, $dst */ - UINT f_src1; - SI * i_dst; - unsigned char out_dst; - } fmt_not1; - struct { /* e.g. not $src1, $lit2, $dst */ - SI * i_src1; - SI * i_dst; - unsigned char in_src1; - unsigned char out_dst; - } fmt_not2; - struct { /* e.g. not $lit1, $lit2, $dst */ - UINT f_src1; - SI * i_dst; - unsigned char out_dst; - } fmt_not3; - struct { /* e.g. shlo $src1, $src2, $dst */ - SI * i_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src1; - unsigned char in_src2; - unsigned char out_dst; - } fmt_shlo; - struct { /* e.g. shlo $lit1, $src2, $dst */ - UINT f_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src2; - unsigned char out_dst; - } fmt_shlo1; - struct { /* e.g. shlo $src1, $lit2, $dst */ - UINT f_src2; - SI * i_src1; - SI * i_dst; - unsigned char in_src1; - unsigned char out_dst; - } fmt_shlo2; - struct { /* e.g. shlo $lit1, $lit2, $dst */ - UINT f_src1; - UINT f_src2; - SI * i_dst; - unsigned char out_dst; - } fmt_shlo3; - struct { /* e.g. emul $src1, $src2, $dst */ - UINT f_srcdst; - SI * i_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src1; - unsigned char in_src2; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_emul; - struct { /* e.g. emul $lit1, $src2, $dst */ - UINT f_srcdst; - UINT f_src1; - SI * i_src2; - SI * i_dst; - unsigned char in_src2; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_emul1; - struct { /* e.g. emul $src1, $lit2, $dst */ - UINT f_srcdst; - UINT f_src2; - SI * i_src1; - SI * i_dst; - unsigned char in_src1; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_emul2; - struct { /* e.g. emul $lit1, $lit2, $dst */ - UINT f_srcdst; - UINT f_src1; - UINT f_src2; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_emul3; - struct { /* e.g. movl $src1, $dst */ - UINT f_src1; - UINT f_srcdst; - SI * i_src1; - SI * i_dst; - unsigned char in_h_gr_add__VM_index_of_src1_1; - unsigned char in_src1; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_movl; - struct { /* e.g. movl $lit1, $dst */ - UINT f_srcdst; - UINT f_src1; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_movl1; - struct { /* e.g. movt $src1, $dst */ - UINT f_src1; - UINT f_srcdst; - SI * i_src1; - SI * i_dst; - unsigned char in_h_gr_add__VM_index_of_src1_1; - unsigned char in_h_gr_add__VM_index_of_src1_2; - unsigned char in_src1; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_movt; - struct { /* e.g. movt $lit1, $dst */ - UINT f_srcdst; - UINT f_src1; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_movt1; - struct { /* e.g. movq $src1, $dst */ - UINT f_src1; - UINT f_srcdst; - SI * i_src1; - SI * i_dst; - unsigned char in_h_gr_add__VM_index_of_src1_1; - unsigned char in_h_gr_add__VM_index_of_src1_2; - unsigned char in_h_gr_add__VM_index_of_src1_3; - unsigned char in_src1; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_movq; - struct { /* e.g. movq $lit1, $dst */ - UINT f_srcdst; - UINT f_src1; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_movq1; - struct { /* e.g. modpc $src1, $src2, $dst */ - SI * i_src2; - SI * i_dst; - unsigned char in_src2; - unsigned char out_dst; - } fmt_modpc; - struct { /* e.g. lda $offset, $dst */ - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - } fmt_lda_offset; - struct { /* e.g. lda $offset($abase), $dst */ - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_lda_indirect_offset; - struct { /* e.g. lda ($abase), $dst */ - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_lda_indirect; - struct { /* e.g. lda ($abase)[$index*S$scale], $dst */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_lda_indirect_index; - struct { /* e.g. lda $optdisp, $dst */ - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - } fmt_lda_disp; - struct { /* e.g. lda $optdisp($abase), $dst */ - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_lda_indirect_disp; - struct { /* e.g. lda $optdisp[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - } fmt_lda_index_disp; - struct { /* e.g. lda $optdisp($abase)[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_lda_indirect_index_disp; - struct { /* e.g. ld $offset, $dst */ - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - } fmt_ld_offset; - struct { /* e.g. ld $offset($abase), $dst */ - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ld_indirect_offset; - struct { /* e.g. ld ($abase), $dst */ - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ld_indirect; - struct { /* e.g. ld ($abase)[$index*S$scale], $dst */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ld_indirect_index; - struct { /* e.g. ld $optdisp, $dst */ - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - } fmt_ld_disp; - struct { /* e.g. ld $optdisp($abase), $dst */ - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ld_indirect_disp; - struct { /* e.g. ld $optdisp[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - } fmt_ld_index_disp; - struct { /* e.g. ld $optdisp($abase)[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ld_indirect_index_disp; - struct { /* e.g. ldob $offset, $dst */ - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - } fmt_ldob_offset; - struct { /* e.g. ldob $offset($abase), $dst */ - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldob_indirect_offset; - struct { /* e.g. ldob ($abase), $dst */ - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldob_indirect; - struct { /* e.g. ldob ($abase)[$index*S$scale], $dst */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldob_indirect_index; - struct { /* e.g. ldob $optdisp, $dst */ - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - } fmt_ldob_disp; - struct { /* e.g. ldob $optdisp($abase), $dst */ - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldob_indirect_disp; - struct { /* e.g. ldob $optdisp[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldob_index_disp; - struct { /* e.g. ldob $optdisp($abase)[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldob_indirect_index_disp; - struct { /* e.g. ldos $offset, $dst */ - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - } fmt_ldos_offset; - struct { /* e.g. ldos $offset($abase), $dst */ - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldos_indirect_offset; - struct { /* e.g. ldos ($abase), $dst */ - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldos_indirect; - struct { /* e.g. ldos ($abase)[$index*S$scale], $dst */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldos_indirect_index; - struct { /* e.g. ldos $optdisp, $dst */ - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - } fmt_ldos_disp; - struct { /* e.g. ldos $optdisp($abase), $dst */ - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldos_indirect_disp; - struct { /* e.g. ldos $optdisp[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldos_index_disp; - struct { /* e.g. ldos $optdisp($abase)[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldos_indirect_index_disp; - struct { /* e.g. ldib $offset, $dst */ - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - } fmt_ldib_offset; - struct { /* e.g. ldib $offset($abase), $dst */ - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldib_indirect_offset; - struct { /* e.g. ldib ($abase), $dst */ - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldib_indirect; - struct { /* e.g. ldib ($abase)[$index*S$scale], $dst */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldib_indirect_index; - struct { /* e.g. ldib $optdisp, $dst */ - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - } fmt_ldib_disp; - struct { /* e.g. ldib $optdisp($abase), $dst */ - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldib_indirect_disp; - struct { /* e.g. ldib $optdisp[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldib_index_disp; - struct { /* e.g. ldib $optdisp($abase)[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldib_indirect_index_disp; - struct { /* e.g. ldis $offset, $dst */ - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - } fmt_ldis_offset; - struct { /* e.g. ldis $offset($abase), $dst */ - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldis_indirect_offset; - struct { /* e.g. ldis ($abase), $dst */ - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldis_indirect; - struct { /* e.g. ldis ($abase)[$index*S$scale], $dst */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldis_indirect_index; - struct { /* e.g. ldis $optdisp, $dst */ - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - } fmt_ldis_disp; - struct { /* e.g. ldis $optdisp($abase), $dst */ - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - } fmt_ldis_indirect_disp; - struct { /* e.g. ldis $optdisp[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldis_index_disp; - struct { /* e.g. ldis $optdisp($abase)[$index*S$scale], $dst */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - } fmt_ldis_indirect_index_disp; - struct { /* e.g. ldl $offset, $dst */ - UINT f_srcdst; - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_offset; - struct { /* e.g. ldl $offset($abase), $dst */ - UINT f_srcdst; - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_indirect_offset; - struct { /* e.g. ldl ($abase), $dst */ - UINT f_srcdst; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_indirect; - struct { /* e.g. ldl ($abase)[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_indirect_index; - struct { /* e.g. ldl $optdisp, $dst */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_disp; - struct { /* e.g. ldl $optdisp($abase), $dst */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_indirect_disp; - struct { /* e.g. ldl $optdisp[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_index_disp; - struct { /* e.g. ldl $optdisp($abase)[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - } fmt_ldl_indirect_index_disp; - struct { /* e.g. ldt $offset, $dst */ - UINT f_srcdst; - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_offset; - struct { /* e.g. ldt $offset($abase), $dst */ - UINT f_srcdst; - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_indirect_offset; - struct { /* e.g. ldt ($abase), $dst */ - UINT f_srcdst; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_indirect; - struct { /* e.g. ldt ($abase)[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_indirect_index; - struct { /* e.g. ldt $optdisp, $dst */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_disp; - struct { /* e.g. ldt $optdisp($abase), $dst */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_indirect_disp; - struct { /* e.g. ldt $optdisp[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_index_disp; - struct { /* e.g. ldt $optdisp($abase)[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - } fmt_ldt_indirect_index_disp; - struct { /* e.g. ldq $offset, $dst */ - UINT f_srcdst; - UINT f_offset; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_offset; - struct { /* e.g. ldq $offset($abase), $dst */ - UINT f_srcdst; - UINT f_offset; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_indirect_offset; - struct { /* e.g. ldq ($abase), $dst */ - UINT f_srcdst; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_indirect; - struct { /* e.g. ldq ($abase)[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_indirect_index; - struct { /* e.g. ldq $optdisp, $dst */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_dst; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_disp; - struct { /* e.g. ldq $optdisp($abase), $dst */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_abase; - SI * i_dst; - unsigned char in_abase; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_indirect_disp; - struct { /* e.g. ldq $optdisp[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_dst; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_index_disp; - struct { /* e.g. ldq $optdisp($abase)[$index*S$scale], $dst */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_dst; - unsigned char in_abase; - unsigned char in_index; - unsigned char out_dst; - unsigned char out_h_gr_add__VM_index_of_dst_1; - unsigned char out_h_gr_add__VM_index_of_dst_2; - unsigned char out_h_gr_add__VM_index_of_dst_3; - } fmt_ldq_indirect_index_disp; - struct { /* e.g. st $st_src, $offset */ - UINT f_offset; - SI * i_st_src; - unsigned char in_st_src; - } fmt_st_offset; - struct { /* e.g. st $st_src, $offset($abase) */ - UINT f_offset; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_st_indirect_offset; - struct { /* e.g. st $st_src, ($abase) */ - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_st_indirect; - struct { /* e.g. st $st_src, ($abase)[$index*S$scale] */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_index; - unsigned char in_st_src; - } fmt_st_indirect_index; - struct { /* e.g. st $st_src, $optdisp */ - UINT f_optdisp; - SI * i_st_src; - unsigned char in_st_src; - } fmt_st_disp; - struct { /* e.g. st $st_src, $optdisp($abase) */ - UINT f_optdisp; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_st_indirect_disp; - struct { /* e.g. st $st_src, $optdisp[$index*S$scale */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_st_src; - unsigned char in_index; - unsigned char in_st_src; - } fmt_st_index_disp; - struct { /* e.g. st $st_src, $optdisp($abase)[$index*S$scale] */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_index; - unsigned char in_st_src; - } fmt_st_indirect_index_disp; - struct { /* e.g. stob $st_src, $offset */ - UINT f_offset; - SI * i_st_src; - unsigned char in_st_src; - } fmt_stob_offset; - struct { /* e.g. stob $st_src, $offset($abase) */ - UINT f_offset; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_stob_indirect_offset; - struct { /* e.g. stob $st_src, ($abase) */ - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_stob_indirect; - struct { /* e.g. stob $st_src, ($abase)[$index*S$scale] */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stob_indirect_index; - struct { /* e.g. stob $st_src, $optdisp */ - UINT f_optdisp; - SI * i_st_src; - unsigned char in_st_src; - } fmt_stob_disp; - struct { /* e.g. stob $st_src, $optdisp($abase) */ - UINT f_optdisp; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_stob_indirect_disp; - struct { /* e.g. stob $st_src, $optdisp[$index*S$scale */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_st_src; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stob_index_disp; - struct { /* e.g. stob $st_src, $optdisp($abase)[$index*S$scale] */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stob_indirect_index_disp; - struct { /* e.g. stos $st_src, $offset */ - UINT f_offset; - SI * i_st_src; - unsigned char in_st_src; - } fmt_stos_offset; - struct { /* e.g. stos $st_src, $offset($abase) */ - UINT f_offset; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_stos_indirect_offset; - struct { /* e.g. stos $st_src, ($abase) */ - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_stos_indirect; - struct { /* e.g. stos $st_src, ($abase)[$index*S$scale] */ - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stos_indirect_index; - struct { /* e.g. stos $st_src, $optdisp */ - UINT f_optdisp; - SI * i_st_src; - unsigned char in_st_src; - } fmt_stos_disp; - struct { /* e.g. stos $st_src, $optdisp($abase) */ - UINT f_optdisp; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_st_src; - } fmt_stos_indirect_disp; - struct { /* e.g. stos $st_src, $optdisp[$index*S$scale */ - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_st_src; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stos_index_disp; - struct { /* e.g. stos $st_src, $optdisp($abase)[$index*S$scale] */ - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stos_indirect_index_disp; - struct { /* e.g. stl $st_src, $offset */ - UINT f_srcdst; - UINT f_offset; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_st_src; - } fmt_stl_offset; - struct { /* e.g. stl $st_src, $offset($abase) */ - UINT f_srcdst; - UINT f_offset; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_st_src; - } fmt_stl_indirect_offset; - struct { /* e.g. stl $st_src, ($abase) */ - UINT f_srcdst; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_st_src; - } fmt_stl_indirect; - struct { /* e.g. stl $st_src, ($abase)[$index*S$scale] */ - UINT f_srcdst; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stl_indirect_index; - struct { /* e.g. stl $st_src, $optdisp */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_st_src; - } fmt_stl_disp; - struct { /* e.g. stl $st_src, $optdisp($abase) */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_st_src; - } fmt_stl_indirect_disp; - struct { /* e.g. stl $st_src, $optdisp[$index*S$scale */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stl_index_disp; - struct { /* e.g. stl $st_src, $optdisp($abase)[$index*S$scale] */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stl_indirect_index_disp; - struct { /* e.g. stt $st_src, $offset */ - UINT f_srcdst; - UINT f_offset; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_st_src; - } fmt_stt_offset; - struct { /* e.g. stt $st_src, $offset($abase) */ - UINT f_srcdst; - UINT f_offset; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_st_src; - } fmt_stt_indirect_offset; - struct { /* e.g. stt $st_src, ($abase) */ - UINT f_srcdst; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_st_src; - } fmt_stt_indirect; - struct { /* e.g. stt $st_src, ($abase)[$index*S$scale] */ - UINT f_srcdst; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stt_indirect_index; - struct { /* e.g. stt $st_src, $optdisp */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_st_src; - } fmt_stt_disp; - struct { /* e.g. stt $st_src, $optdisp($abase) */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_st_src; - } fmt_stt_indirect_disp; - struct { /* e.g. stt $st_src, $optdisp[$index*S$scale */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stt_index_disp; - struct { /* e.g. stt $st_src, $optdisp($abase)[$index*S$scale] */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stt_indirect_index_disp; - struct { /* e.g. stq $st_src, $offset */ - UINT f_srcdst; - UINT f_offset; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_st_src; - } fmt_stq_offset; - struct { /* e.g. stq $st_src, $offset($abase) */ - UINT f_srcdst; - UINT f_offset; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_st_src; - } fmt_stq_indirect_offset; - struct { /* e.g. stq $st_src, ($abase) */ - UINT f_srcdst; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_st_src; - } fmt_stq_indirect; - struct { /* e.g. stq $st_src, ($abase)[$index*S$scale] */ - UINT f_srcdst; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stq_indirect_index; - struct { /* e.g. stq $st_src, $optdisp */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_st_src; - } fmt_stq_disp; - struct { /* e.g. stq $st_src, $optdisp($abase) */ - UINT f_srcdst; - UINT f_optdisp; - SI * i_abase; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_st_src; - } fmt_stq_indirect_disp; - struct { /* e.g. stq $st_src, $optdisp[$index*S$scale */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_index; - SI * i_st_src; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stq_index_disp; - struct { /* e.g. stq $st_src, $optdisp($abase)[$index*S$scale] */ - UINT f_srcdst; - UINT f_optdisp; - UINT f_scale; - SI * i_abase; - SI * i_index; - SI * i_st_src; - unsigned char in_abase; - unsigned char in_h_gr_add__VM_index_of_st_src_1; - unsigned char in_h_gr_add__VM_index_of_st_src_2; - unsigned char in_h_gr_add__VM_index_of_st_src_3; - unsigned char in_index; - unsigned char in_st_src; - } fmt_stq_indirect_index_disp; - struct { /* e.g. cmpi $src1, $src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_cmpi; - struct { /* e.g. cmpi $lit1, $src2 */ - UINT f_src1; - SI * i_src2; - unsigned char in_src2; - } fmt_cmpi1; - struct { /* e.g. cmpi $src1, $lit2 */ - UINT f_src2; - SI * i_src1; - unsigned char in_src1; - } fmt_cmpi2; - struct { /* e.g. cmpi $lit1, $lit2 */ - UINT f_src1; - UINT f_src2; - } fmt_cmpi3; - struct { /* e.g. cmpo $src1, $src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_cmpo; - struct { /* e.g. cmpo $lit1, $src2 */ - UINT f_src1; - SI * i_src2; - unsigned char in_src2; - } fmt_cmpo1; - struct { /* e.g. cmpo $src1, $lit2 */ - UINT f_src2; - SI * i_src1; - unsigned char in_src1; - } fmt_cmpo2; - struct { /* e.g. cmpo $lit1, $lit2 */ - UINT f_src1; - UINT f_src2; - } fmt_cmpo3; - struct { /* e.g. testno $br_src1 */ - SI * i_br_src1; - unsigned char out_br_src1; - } fmt_testno_reg; - struct { /* e.g. flushreg */ - int empty; - } fmt_flushreg; - /* cti insns, kept separately so addr_cache is in fixed place */ - struct { - union { - struct { /* e.g. cmpobe $br_src1, $br_src2, $br_disp */ - IADDR i_br_disp; - SI * i_br_src1; - SI * i_br_src2; - unsigned char in_br_src1; - unsigned char in_br_src2; - } fmt_cmpobe_reg; - struct { /* e.g. cmpobe $br_lit1, $br_src2, $br_disp */ - UINT f_br_src1; - IADDR i_br_disp; - SI * i_br_src2; - unsigned char in_br_src2; - } fmt_cmpobe_lit; - struct { /* e.g. cmpobl $br_src1, $br_src2, $br_disp */ - IADDR i_br_disp; - SI * i_br_src1; - SI * i_br_src2; - unsigned char in_br_src1; - unsigned char in_br_src2; - } fmt_cmpobl_reg; - struct { /* e.g. cmpobl $br_lit1, $br_src2, $br_disp */ - UINT f_br_src1; - IADDR i_br_disp; - SI * i_br_src2; - unsigned char in_br_src2; - } fmt_cmpobl_lit; - struct { /* e.g. bbc $br_src1, $br_src2, $br_disp */ - IADDR i_br_disp; - SI * i_br_src1; - SI * i_br_src2; - unsigned char in_br_src1; - unsigned char in_br_src2; - } fmt_bbc_reg; - struct { /* e.g. bbc $br_lit1, $br_src2, $br_disp */ - UINT f_br_src1; - IADDR i_br_disp; - SI * i_br_src2; - unsigned char in_br_src2; - } fmt_bbc_lit; - struct { /* e.g. bno $ctrl_disp */ - IADDR i_ctrl_disp; - } fmt_bno; - struct { /* e.g. b $ctrl_disp */ - IADDR i_ctrl_disp; - } fmt_b; - struct { /* e.g. bx $offset($abase) */ - UINT f_offset; - SI * i_abase; - unsigned char in_abase; - } fmt_bx_indirect_offset; - struct { /* e.g. bx ($abase) */ - SI * i_abase; - unsigned char in_abase; - } fmt_bx_indirect; - struct { /* e.g. bx ($abase)[$index*S$scale] */ - UINT f_scale; - SI * i_abase; - SI * i_index; - unsigned char in_abase; - unsigned char in_index; - } fmt_bx_indirect_index; - struct { /* e.g. bx $optdisp */ - UINT f_optdisp; - } fmt_bx_disp; - struct { /* e.g. bx $optdisp($abase) */ - UINT f_optdisp; - SI * i_abase; - unsigned char in_abase; - } fmt_bx_indirect_disp; - struct { /* e.g. callx $optdisp */ - UINT f_optdisp; - unsigned char in_h_gr_0; - unsigned char in_h_gr_1; - unsigned char in_h_gr_10; - unsigned char in_h_gr_11; - unsigned char in_h_gr_12; - unsigned char in_h_gr_13; - unsigned char in_h_gr_14; - unsigned char in_h_gr_15; - unsigned char in_h_gr_2; - unsigned char in_h_gr_3; - unsigned char in_h_gr_31; - unsigned char in_h_gr_4; - unsigned char in_h_gr_5; - unsigned char in_h_gr_6; - unsigned char in_h_gr_7; - unsigned char in_h_gr_8; - unsigned char in_h_gr_9; - unsigned char out_h_gr_0; - unsigned char out_h_gr_1; - unsigned char out_h_gr_10; - unsigned char out_h_gr_11; - unsigned char out_h_gr_12; - unsigned char out_h_gr_13; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - unsigned char out_h_gr_2; - unsigned char out_h_gr_3; - unsigned char out_h_gr_31; - unsigned char out_h_gr_4; - unsigned char out_h_gr_5; - unsigned char out_h_gr_6; - unsigned char out_h_gr_7; - unsigned char out_h_gr_8; - unsigned char out_h_gr_9; - } fmt_callx_disp; - struct { /* e.g. callx ($abase) */ - SI * i_abase; - unsigned char in_abase; - unsigned char in_h_gr_0; - unsigned char in_h_gr_1; - unsigned char in_h_gr_10; - unsigned char in_h_gr_11; - unsigned char in_h_gr_12; - unsigned char in_h_gr_13; - unsigned char in_h_gr_14; - unsigned char in_h_gr_15; - unsigned char in_h_gr_2; - unsigned char in_h_gr_3; - unsigned char in_h_gr_31; - unsigned char in_h_gr_4; - unsigned char in_h_gr_5; - unsigned char in_h_gr_6; - unsigned char in_h_gr_7; - unsigned char in_h_gr_8; - unsigned char in_h_gr_9; - unsigned char out_h_gr_0; - unsigned char out_h_gr_1; - unsigned char out_h_gr_10; - unsigned char out_h_gr_11; - unsigned char out_h_gr_12; - unsigned char out_h_gr_13; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - unsigned char out_h_gr_2; - unsigned char out_h_gr_3; - unsigned char out_h_gr_31; - unsigned char out_h_gr_4; - unsigned char out_h_gr_5; - unsigned char out_h_gr_6; - unsigned char out_h_gr_7; - unsigned char out_h_gr_8; - unsigned char out_h_gr_9; - } fmt_callx_indirect; - struct { /* e.g. callx $offset($abase) */ - UINT f_offset; - SI * i_abase; - unsigned char in_abase; - unsigned char in_h_gr_0; - unsigned char in_h_gr_1; - unsigned char in_h_gr_10; - unsigned char in_h_gr_11; - unsigned char in_h_gr_12; - unsigned char in_h_gr_13; - unsigned char in_h_gr_14; - unsigned char in_h_gr_15; - unsigned char in_h_gr_2; - unsigned char in_h_gr_3; - unsigned char in_h_gr_31; - unsigned char in_h_gr_4; - unsigned char in_h_gr_5; - unsigned char in_h_gr_6; - unsigned char in_h_gr_7; - unsigned char in_h_gr_8; - unsigned char in_h_gr_9; - unsigned char out_h_gr_0; - unsigned char out_h_gr_1; - unsigned char out_h_gr_10; - unsigned char out_h_gr_11; - unsigned char out_h_gr_12; - unsigned char out_h_gr_13; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - unsigned char out_h_gr_2; - unsigned char out_h_gr_3; - unsigned char out_h_gr_31; - unsigned char out_h_gr_4; - unsigned char out_h_gr_5; - unsigned char out_h_gr_6; - unsigned char out_h_gr_7; - unsigned char out_h_gr_8; - unsigned char out_h_gr_9; - } fmt_callx_indirect_offset; - struct { /* e.g. ret */ - int empty; - unsigned char in_h_gr_0; - unsigned char in_h_gr_2; - unsigned char in_h_gr_31; - unsigned char out_h_gr_0; - unsigned char out_h_gr_1; - unsigned char out_h_gr_10; - unsigned char out_h_gr_11; - unsigned char out_h_gr_12; - unsigned char out_h_gr_13; - unsigned char out_h_gr_14; - unsigned char out_h_gr_15; - unsigned char out_h_gr_2; - unsigned char out_h_gr_3; - unsigned char out_h_gr_31; - unsigned char out_h_gr_4; - unsigned char out_h_gr_5; - unsigned char out_h_gr_6; - unsigned char out_h_gr_7; - unsigned char out_h_gr_8; - unsigned char out_h_gr_9; - } fmt_ret; - struct { /* e.g. calls $src1 */ - SI * i_src1; - unsigned char in_src1; - } fmt_calls; - struct { /* e.g. fmark */ - int empty; - } fmt_fmark; - } fields; -#if WITH_SCACHE_PBB - SEM_PC addr_cache; -#endif - } cti; + struct { /* no operands */ + int empty; + } fmt_empty; + struct { /* */ + IADDR i_ctrl_disp; + } sfmt_bno; + struct { /* */ + SI* i_br_src1; + unsigned char out_br_src1; + } sfmt_testno_reg; + struct { /* */ + IADDR i_br_disp; + SI* i_br_src2; + UINT f_br_src1; + unsigned char in_br_src2; + } sfmt_cmpobe_lit; + struct { /* */ + IADDR i_br_disp; + SI* i_br_src1; + SI* i_br_src2; + unsigned char in_br_src1; + unsigned char in_br_src2; + } sfmt_cmpobe_reg; + struct { /* */ + SI* i_dst; + UINT f_src1; + UINT f_src2; + UINT f_srcdst; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + } sfmt_emul3; + struct { /* */ + SI* i_dst; + SI* i_src1; + UINT f_src2; + UINT f_srcdst; + unsigned char in_src1; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + } sfmt_emul2; + struct { /* */ + SI* i_dst; + SI* i_src2; + UINT f_src1; + UINT f_srcdst; + unsigned char in_src2; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + } sfmt_emul1; + struct { /* */ + SI* i_dst; + SI* i_src1; + SI* i_src2; + UINT f_srcdst; + unsigned char in_src1; + unsigned char in_src2; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + } sfmt_emul; + struct { /* */ + SI* i_abase; + SI* i_st_src; + UINT f_offset; + UINT f_srcdst; + unsigned char in_abase; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; + unsigned char in_st_src; + } sfmt_stq_indirect_offset; + struct { /* */ + SI* i_abase; + SI* i_dst; + UINT f_offset; + UINT f_srcdst; + unsigned char in_abase; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; + } sfmt_ldq_indirect_offset; + struct { /* */ + SI* i_abase; + SI* i_index; + SI* i_st_src; + UINT f_optdisp; + UINT f_scale; + UINT f_srcdst; + unsigned char in_abase; + unsigned char in_h_gr_add__VM_index_of_st_src_1; + unsigned char in_h_gr_add__VM_index_of_st_src_2; + unsigned char in_h_gr_add__VM_index_of_st_src_3; + unsigned char in_index; + unsigned char in_st_src; + } sfmt_stq_indirect_index_disp; + struct { /* */ + SI* i_abase; + SI* i_dst; + SI* i_index; + UINT f_optdisp; + UINT f_scale; + UINT f_srcdst; + unsigned char in_abase; + unsigned char in_index; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; + } sfmt_ldq_indirect_index_disp; + struct { /* */ + SI* i_dst; + SI* i_src1; + UINT f_src1; + UINT f_srcdst; + unsigned char in_h_gr_add__VM_index_of_src1_1; + unsigned char in_h_gr_add__VM_index_of_src1_2; + unsigned char in_h_gr_add__VM_index_of_src1_3; + unsigned char in_src1; + unsigned char out_dst; + unsigned char out_h_gr_add__VM_index_of_dst_1; + unsigned char out_h_gr_add__VM_index_of_dst_2; + unsigned char out_h_gr_add__VM_index_of_dst_3; + } sfmt_movq; + struct { /* */ + UINT f_optdisp; + unsigned char in_h_gr_0; + unsigned char in_h_gr_1; + unsigned char in_h_gr_10; + unsigned char in_h_gr_11; + unsigned char in_h_gr_12; + unsigned char in_h_gr_13; + unsigned char in_h_gr_14; + unsigned char in_h_gr_15; + unsigned char in_h_gr_2; + unsigned char in_h_gr_3; + unsigned char in_h_gr_31; + unsigned char in_h_gr_4; + unsigned char in_h_gr_5; + unsigned char in_h_gr_6; + unsigned char in_h_gr_7; + unsigned char in_h_gr_8; + unsigned char in_h_gr_9; + unsigned char out_h_gr_0; + unsigned char out_h_gr_1; + unsigned char out_h_gr_10; + unsigned char out_h_gr_11; + unsigned char out_h_gr_12; + unsigned char out_h_gr_13; + unsigned char out_h_gr_14; + unsigned char out_h_gr_15; + unsigned char out_h_gr_2; + unsigned char out_h_gr_3; + unsigned char out_h_gr_31; + unsigned char out_h_gr_4; + unsigned char out_h_gr_5; + unsigned char out_h_gr_6; + unsigned char out_h_gr_7; + unsigned char out_h_gr_8; + unsigned char out_h_gr_9; + } sfmt_callx_disp; + struct { /* */ + SI* i_abase; + UINT f_offset; + unsigned char in_abase; + unsigned char in_h_gr_0; + unsigned char in_h_gr_1; + unsigned char in_h_gr_10; + unsigned char in_h_gr_11; + unsigned char in_h_gr_12; + unsigned char in_h_gr_13; + unsigned char in_h_gr_14; + unsigned char in_h_gr_15; + unsigned char in_h_gr_2; + unsigned char in_h_gr_3; + unsigned char in_h_gr_31; + unsigned char in_h_gr_4; + unsigned char in_h_gr_5; + unsigned char in_h_gr_6; + unsigned char in_h_gr_7; + unsigned char in_h_gr_8; + unsigned char in_h_gr_9; + unsigned char out_h_gr_0; + unsigned char out_h_gr_1; + unsigned char out_h_gr_10; + unsigned char out_h_gr_11; + unsigned char out_h_gr_12; + unsigned char out_h_gr_13; + unsigned char out_h_gr_14; + unsigned char out_h_gr_15; + unsigned char out_h_gr_2; + unsigned char out_h_gr_3; + unsigned char out_h_gr_31; + unsigned char out_h_gr_4; + unsigned char out_h_gr_5; + unsigned char out_h_gr_6; + unsigned char out_h_gr_7; + unsigned char out_h_gr_8; + unsigned char out_h_gr_9; + } sfmt_callx_indirect_offset; #if WITH_SCACHE_PBB /* Writeback handler. */ struct { @@ -1572,6 +295,7 @@ union sem_fields { int insn_count; /* Next pbb to execute. */ SCACHE *next; + SCACHE *branch_target; } chain; #endif }; @@ -1583,6 +307,9 @@ struct argbuf { const IDESC *idesc; char trace_p; char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; /* cpu specific data follows */ union sem semantic; int written; @@ -1603,13 +330,11 @@ struct scache { These define and assign the local vars that contain the insn's fields. */ #define EXTRACT_IFMT_EMPTY_VARS \ - /* Instruction fields. */ \ unsigned int length; #define EXTRACT_IFMT_EMPTY_CODE \ length = 0; \ #define EXTRACT_IFMT_MULO_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_src2; \ @@ -1622,18 +347,17 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MULO_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \ - f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \ - f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \ - f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \ - f_zero = EXTRACT_UINT (insn, 32, 25, 2); \ - f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \ + f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \ + f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \ + f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_MULO1_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_src2; \ @@ -1646,18 +370,17 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MULO1_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \ - f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \ - f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \ - f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \ - f_zero = EXTRACT_UINT (insn, 32, 25, 2); \ - f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \ + f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \ + f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \ + f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_MULO2_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_src2; \ @@ -1670,18 +393,17 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MULO2_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \ - f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \ - f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \ - f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \ - f_zero = EXTRACT_UINT (insn, 32, 25, 2); \ - f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \ + f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \ + f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \ + f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_MULO3_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_src2; \ @@ -1694,18 +416,17 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MULO3_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_src2 = EXTRACT_UINT (insn, 32, 13, 5); \ - f_m3 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_m2 = EXTRACT_UINT (insn, 32, 19, 1); \ - f_m1 = EXTRACT_UINT (insn, 32, 20, 1); \ - f_opcode2 = EXTRACT_UINT (insn, 32, 21, 4); \ - f_zero = EXTRACT_UINT (insn, 32, 25, 2); \ - f_src1 = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \ + f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \ + f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \ + f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_LDA_OFFSET_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_abase; \ @@ -1715,15 +436,14 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_LDA_OFFSET_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_abase = EXTRACT_UINT (insn, 32, 13, 5); \ - f_modea = EXTRACT_UINT (insn, 32, 18, 1); \ - f_zeroa = EXTRACT_UINT (insn, 32, 19, 1); \ - f_offset = EXTRACT_UINT (insn, 32, 20, 12); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \ + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \ #define EXTRACT_IFMT_LDA_INDIRECT_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_abase; \ @@ -1734,16 +454,15 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_LDA_INDIRECT_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_abase = EXTRACT_UINT (insn, 32, 13, 5); \ - f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \ - f_scale = EXTRACT_UINT (insn, 32, 22, 3); \ - f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \ - f_index = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \ + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \ + f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_LDA_DISP_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_optdisp; \ UINT f_srcdst; \ @@ -1758,17 +477,16 @@ struct scache { #define EXTRACT_IFMT_LDA_DISP_CODE \ length = 8; \ word_1 = GETIMEMUSI (current_cpu, pc + 4); \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_optdisp = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_abase = EXTRACT_UINT (insn, 32, 13, 5); \ - f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \ - f_scale = EXTRACT_UINT (insn, 32, 22, 3); \ - f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \ - f_index = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \ + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \ + f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_ST_OFFSET_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_abase; \ @@ -1778,15 +496,14 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ST_OFFSET_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_abase = EXTRACT_UINT (insn, 32, 13, 5); \ - f_modea = EXTRACT_UINT (insn, 32, 18, 1); \ - f_zeroa = EXTRACT_UINT (insn, 32, 19, 1); \ - f_offset = EXTRACT_UINT (insn, 32, 20, 12); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \ + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \ #define EXTRACT_IFMT_ST_INDIRECT_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_srcdst; \ UINT f_abase; \ @@ -1797,16 +514,15 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ST_INDIRECT_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_abase = EXTRACT_UINT (insn, 32, 13, 5); \ - f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \ - f_scale = EXTRACT_UINT (insn, 32, 22, 3); \ - f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \ - f_index = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \ + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \ + f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_ST_DISP_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_optdisp; \ UINT f_srcdst; \ @@ -1821,17 +537,16 @@ struct scache { #define EXTRACT_IFMT_ST_DISP_CODE \ length = 8; \ word_1 = GETIMEMUSI (current_cpu, pc + 4); \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_optdisp = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \ - f_srcdst = EXTRACT_UINT (insn, 32, 8, 5); \ - f_abase = EXTRACT_UINT (insn, 32, 13, 5); \ - f_modeb = EXTRACT_UINT (insn, 32, 18, 4); \ - f_scale = EXTRACT_UINT (insn, 32, 22, 3); \ - f_zerob = EXTRACT_UINT (insn, 32, 25, 2); \ - f_index = EXTRACT_UINT (insn, 32, 27, 5); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \ + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \ + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \ + f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \ + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \ #define EXTRACT_IFMT_CMPOBE_REG_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_br_src1; \ UINT f_br_src2; \ @@ -1841,15 +556,14 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_CMPOBE_REG_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_br_src1 = EXTRACT_UINT (insn, 32, 8, 5); \ - f_br_src2 = EXTRACT_UINT (insn, 32, 13, 5); \ - f_br_m1 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_br_disp = ((((EXTRACT_INT (insn, 32, 19, 11)) << (2))) + (pc)); \ - f_br_zero = EXTRACT_UINT (insn, 32, 30, 2); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \ + f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \ #define EXTRACT_IFMT_CMPOBE_LIT_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ UINT f_br_src1; \ UINT f_br_src2; \ @@ -1859,24 +573,23 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_CMPOBE_LIT_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_br_src1 = EXTRACT_UINT (insn, 32, 8, 5); \ - f_br_src2 = EXTRACT_UINT (insn, 32, 13, 5); \ - f_br_m1 = EXTRACT_UINT (insn, 32, 18, 1); \ - f_br_disp = ((((EXTRACT_INT (insn, 32, 19, 11)) << (2))) + (pc)); \ - f_br_zero = EXTRACT_UINT (insn, 32, 30, 2); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \ + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \ + f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \ + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \ + f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \ #define EXTRACT_IFMT_BNO_VARS \ - /* Instruction fields. */ \ UINT f_opcode; \ SI f_ctrl_disp; \ UINT f_ctrl_zero; \ unsigned int length; #define EXTRACT_IFMT_BNO_CODE \ length = 4; \ - f_opcode = EXTRACT_UINT (insn, 32, 0, 8); \ - f_ctrl_disp = ((((EXTRACT_INT (insn, 32, 8, 22)) << (2))) + (pc)); \ - f_ctrl_zero = EXTRACT_UINT (insn, 32, 30, 2); \ + f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \ + f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); \ + f_ctrl_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \ /* Collection of various things for the trace handler to use. */ diff --git a/sim/i960/cpuall.h b/sim/i960/cpuall.h index a22e559..772cd9f 100644 --- a/sim/i960/cpuall.h +++ b/sim/i960/cpuall.h @@ -45,6 +45,9 @@ struct argbuf { const IDESC *idesc; char trace_p; char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; /* cpu specific data follows */ }; #endif diff --git a/sim/i960/decode.c b/sim/i960/decode.c index a3ac523..a0f1526 100644 --- a/sim/i960/decode.c +++ b/sim/i960/decode.c @@ -28,29 +28,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-main.h" #include "sim-assert.h" -/* FIXME: Need to review choices for the following. */ - -#if WITH_SEM_SWITCH_FULL -#define FULL(fn) -#else -#define FULL(fn) CONCAT3 (i960base,_sem_,fn) , -#endif - -#if WITH_FAST -#if WITH_SEM_SWITCH_FAST -#define FAST(fn) -#else -#define FAST(fn) CONCAT3 (i960base,_semf_,fn) , /* f for fast */ -#endif -#else -#define FAST(fn) -#endif - -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (I960BASE_,insn) -#define TYPE(insn) CONCAT2 (I960_,insn) - /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -63,316 +40,309 @@ static IDESC i960base_insn_data[I960BASE_INSN_MAX]; static const struct insn_sem i960base_insn_sem[] = { - { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, - { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, - { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, - { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, - { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, - { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, - { TYPE (INSN_MULO), IDX (INSN_MULO), FULL (mulo) FAST (mulo) }, - { TYPE (INSN_MULO1), IDX (INSN_MULO1), FULL (mulo1) FAST (mulo1) }, - { TYPE (INSN_MULO2), IDX (INSN_MULO2), FULL (mulo2) FAST (mulo2) }, - { TYPE (INSN_MULO3), IDX (INSN_MULO3), FULL (mulo3) FAST (mulo3) }, - { TYPE (INSN_REMO), IDX (INSN_REMO), FULL (remo) FAST (remo) }, - { TYPE (INSN_REMO1), IDX (INSN_REMO1), FULL (remo1) FAST (remo1) }, - { TYPE (INSN_REMO2), IDX (INSN_REMO2), FULL (remo2) FAST (remo2) }, - { TYPE (INSN_REMO3), IDX (INSN_REMO3), FULL (remo3) FAST (remo3) }, - { TYPE (INSN_DIVO), IDX (INSN_DIVO), FULL (divo) FAST (divo) }, - { TYPE (INSN_DIVO1), IDX (INSN_DIVO1), FULL (divo1) FAST (divo1) }, - { TYPE (INSN_DIVO2), IDX (INSN_DIVO2), FULL (divo2) FAST (divo2) }, - { TYPE (INSN_DIVO3), IDX (INSN_DIVO3), FULL (divo3) FAST (divo3) }, - { TYPE (INSN_REMI), IDX (INSN_REMI), FULL (remi) FAST (remi) }, - { TYPE (INSN_REMI1), IDX (INSN_REMI1), FULL (remi1) FAST (remi1) }, - { TYPE (INSN_REMI2), IDX (INSN_REMI2), FULL (remi2) FAST (remi2) }, - { TYPE (INSN_REMI3), IDX (INSN_REMI3), FULL (remi3) FAST (remi3) }, - { TYPE (INSN_DIVI), IDX (INSN_DIVI), FULL (divi) FAST (divi) }, - { TYPE (INSN_DIVI1), IDX (INSN_DIVI1), FULL (divi1) FAST (divi1) }, - { TYPE (INSN_DIVI2), IDX (INSN_DIVI2), FULL (divi2) FAST (divi2) }, - { TYPE (INSN_DIVI3), IDX (INSN_DIVI3), FULL (divi3) FAST (divi3) }, - { TYPE (INSN_ADDO), IDX (INSN_ADDO), FULL (addo) FAST (addo) }, - { TYPE (INSN_ADDO1), IDX (INSN_ADDO1), FULL (addo1) FAST (addo1) }, - { TYPE (INSN_ADDO2), IDX (INSN_ADDO2), FULL (addo2) FAST (addo2) }, - { TYPE (INSN_ADDO3), IDX (INSN_ADDO3), FULL (addo3) FAST (addo3) }, - { TYPE (INSN_SUBO), IDX (INSN_SUBO), FULL (subo) FAST (subo) }, - { TYPE (INSN_SUBO1), IDX (INSN_SUBO1), FULL (subo1) FAST (subo1) }, - { TYPE (INSN_SUBO2), IDX (INSN_SUBO2), FULL (subo2) FAST (subo2) }, - { TYPE (INSN_SUBO3), IDX (INSN_SUBO3), FULL (subo3) FAST (subo3) }, - { TYPE (INSN_NOTBIT), IDX (INSN_NOTBIT), FULL (notbit) FAST (notbit) }, - { TYPE (INSN_NOTBIT1), IDX (INSN_NOTBIT1), FULL (notbit1) FAST (notbit1) }, - { TYPE (INSN_NOTBIT2), IDX (INSN_NOTBIT2), FULL (notbit2) FAST (notbit2) }, - { TYPE (INSN_NOTBIT3), IDX (INSN_NOTBIT3), FULL (notbit3) FAST (notbit3) }, - { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, - { TYPE (INSN_AND1), IDX (INSN_AND1), FULL (and1) FAST (and1) }, - { TYPE (INSN_AND2), IDX (INSN_AND2), FULL (and2) FAST (and2) }, - { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) }, - { TYPE (INSN_ANDNOT), IDX (INSN_ANDNOT), FULL (andnot) FAST (andnot) }, - { TYPE (INSN_ANDNOT1), IDX (INSN_ANDNOT1), FULL (andnot1) FAST (andnot1) }, - { TYPE (INSN_ANDNOT2), IDX (INSN_ANDNOT2), FULL (andnot2) FAST (andnot2) }, - { TYPE (INSN_ANDNOT3), IDX (INSN_ANDNOT3), FULL (andnot3) FAST (andnot3) }, - { TYPE (INSN_SETBIT), IDX (INSN_SETBIT), FULL (setbit) FAST (setbit) }, - { TYPE (INSN_SETBIT1), IDX (INSN_SETBIT1), FULL (setbit1) FAST (setbit1) }, - { TYPE (INSN_SETBIT2), IDX (INSN_SETBIT2), FULL (setbit2) FAST (setbit2) }, - { TYPE (INSN_SETBIT3), IDX (INSN_SETBIT3), FULL (setbit3) FAST (setbit3) }, - { TYPE (INSN_NOTAND), IDX (INSN_NOTAND), FULL (notand) FAST (notand) }, - { TYPE (INSN_NOTAND1), IDX (INSN_NOTAND1), FULL (notand1) FAST (notand1) }, - { TYPE (INSN_NOTAND2), IDX (INSN_NOTAND2), FULL (notand2) FAST (notand2) }, - { TYPE (INSN_NOTAND3), IDX (INSN_NOTAND3), FULL (notand3) FAST (notand3) }, - { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, - { TYPE (INSN_XOR1), IDX (INSN_XOR1), FULL (xor1) FAST (xor1) }, - { TYPE (INSN_XOR2), IDX (INSN_XOR2), FULL (xor2) FAST (xor2) }, - { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) }, - { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, - { TYPE (INSN_OR1), IDX (INSN_OR1), FULL (or1) FAST (or1) }, - { TYPE (INSN_OR2), IDX (INSN_OR2), FULL (or2) FAST (or2) }, - { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) }, - { TYPE (INSN_NOR), IDX (INSN_NOR), FULL (nor) FAST (nor) }, - { TYPE (INSN_NOR1), IDX (INSN_NOR1), FULL (nor1) FAST (nor1) }, - { TYPE (INSN_NOR2), IDX (INSN_NOR2), FULL (nor2) FAST (nor2) }, - { TYPE (INSN_NOR3), IDX (INSN_NOR3), FULL (nor3) FAST (nor3) }, - { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) }, - { TYPE (INSN_XNOR1), IDX (INSN_XNOR1), FULL (xnor1) FAST (xnor1) }, - { TYPE (INSN_XNOR2), IDX (INSN_XNOR2), FULL (xnor2) FAST (xnor2) }, - { TYPE (INSN_XNOR3), IDX (INSN_XNOR3), FULL (xnor3) FAST (xnor3) }, - { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) }, - { TYPE (INSN_NOT1), IDX (INSN_NOT1), FULL (not1) FAST (not1) }, - { TYPE (INSN_NOT2), IDX (INSN_NOT2), FULL (not2) FAST (not2) }, - { TYPE (INSN_NOT3), IDX (INSN_NOT3), FULL (not3) FAST (not3) }, - { TYPE (INSN_ORNOT), IDX (INSN_ORNOT), FULL (ornot) FAST (ornot) }, - { TYPE (INSN_ORNOT1), IDX (INSN_ORNOT1), FULL (ornot1) FAST (ornot1) }, - { TYPE (INSN_ORNOT2), IDX (INSN_ORNOT2), FULL (ornot2) FAST (ornot2) }, - { TYPE (INSN_ORNOT3), IDX (INSN_ORNOT3), FULL (ornot3) FAST (ornot3) }, - { TYPE (INSN_CLRBIT), IDX (INSN_CLRBIT), FULL (clrbit) FAST (clrbit) }, - { TYPE (INSN_CLRBIT1), IDX (INSN_CLRBIT1), FULL (clrbit1) FAST (clrbit1) }, - { TYPE (INSN_CLRBIT2), IDX (INSN_CLRBIT2), FULL (clrbit2) FAST (clrbit2) }, - { TYPE (INSN_CLRBIT3), IDX (INSN_CLRBIT3), FULL (clrbit3) FAST (clrbit3) }, - { TYPE (INSN_SHLO), IDX (INSN_SHLO), FULL (shlo) FAST (shlo) }, - { TYPE (INSN_SHLO1), IDX (INSN_SHLO1), FULL (shlo1) FAST (shlo1) }, - { TYPE (INSN_SHLO2), IDX (INSN_SHLO2), FULL (shlo2) FAST (shlo2) }, - { TYPE (INSN_SHLO3), IDX (INSN_SHLO3), FULL (shlo3) FAST (shlo3) }, - { TYPE (INSN_SHRO), IDX (INSN_SHRO), FULL (shro) FAST (shro) }, - { TYPE (INSN_SHRO1), IDX (INSN_SHRO1), FULL (shro1) FAST (shro1) }, - { TYPE (INSN_SHRO2), IDX (INSN_SHRO2), FULL (shro2) FAST (shro2) }, - { TYPE (INSN_SHRO3), IDX (INSN_SHRO3), FULL (shro3) FAST (shro3) }, - { TYPE (INSN_SHLI), IDX (INSN_SHLI), FULL (shli) FAST (shli) }, - { TYPE (INSN_SHLI1), IDX (INSN_SHLI1), FULL (shli1) FAST (shli1) }, - { TYPE (INSN_SHLI2), IDX (INSN_SHLI2), FULL (shli2) FAST (shli2) }, - { TYPE (INSN_SHLI3), IDX (INSN_SHLI3), FULL (shli3) FAST (shli3) }, - { TYPE (INSN_SHRI), IDX (INSN_SHRI), FULL (shri) FAST (shri) }, - { TYPE (INSN_SHRI1), IDX (INSN_SHRI1), FULL (shri1) FAST (shri1) }, - { TYPE (INSN_SHRI2), IDX (INSN_SHRI2), FULL (shri2) FAST (shri2) }, - { TYPE (INSN_SHRI3), IDX (INSN_SHRI3), FULL (shri3) FAST (shri3) }, - { TYPE (INSN_EMUL), IDX (INSN_EMUL), FULL (emul) FAST (emul) }, - { TYPE (INSN_EMUL1), IDX (INSN_EMUL1), FULL (emul1) FAST (emul1) }, - { TYPE (INSN_EMUL2), IDX (INSN_EMUL2), FULL (emul2) FAST (emul2) }, - { TYPE (INSN_EMUL3), IDX (INSN_EMUL3), FULL (emul3) FAST (emul3) }, - { TYPE (INSN_MOV), IDX (INSN_MOV), FULL (mov) FAST (mov) }, - { TYPE (INSN_MOV1), IDX (INSN_MOV1), FULL (mov1) FAST (mov1) }, - { TYPE (INSN_MOVL), IDX (INSN_MOVL), FULL (movl) FAST (movl) }, - { TYPE (INSN_MOVL1), IDX (INSN_MOVL1), FULL (movl1) FAST (movl1) }, - { TYPE (INSN_MOVT), IDX (INSN_MOVT), FULL (movt) FAST (movt) }, - { TYPE (INSN_MOVT1), IDX (INSN_MOVT1), FULL (movt1) FAST (movt1) }, - { TYPE (INSN_MOVQ), IDX (INSN_MOVQ), FULL (movq) FAST (movq) }, - { TYPE (INSN_MOVQ1), IDX (INSN_MOVQ1), FULL (movq1) FAST (movq1) }, - { TYPE (INSN_MODPC), IDX (INSN_MODPC), FULL (modpc) FAST (modpc) }, - { TYPE (INSN_MODAC), IDX (INSN_MODAC), FULL (modac) FAST (modac) }, - { TYPE (INSN_LDA_OFFSET), IDX (INSN_LDA_OFFSET), FULL (lda_offset) FAST (lda_offset) }, - { TYPE (INSN_LDA_INDIRECT_OFFSET), IDX (INSN_LDA_INDIRECT_OFFSET), FULL (lda_indirect_offset) FAST (lda_indirect_offset) }, - { TYPE (INSN_LDA_INDIRECT), IDX (INSN_LDA_INDIRECT), FULL (lda_indirect) FAST (lda_indirect) }, - { TYPE (INSN_LDA_INDIRECT_INDEX), IDX (INSN_LDA_INDIRECT_INDEX), FULL (lda_indirect_index) FAST (lda_indirect_index) }, - { TYPE (INSN_LDA_DISP), IDX (INSN_LDA_DISP), FULL (lda_disp) FAST (lda_disp) }, - { TYPE (INSN_LDA_INDIRECT_DISP), IDX (INSN_LDA_INDIRECT_DISP), FULL (lda_indirect_disp) FAST (lda_indirect_disp) }, - { TYPE (INSN_LDA_INDEX_DISP), IDX (INSN_LDA_INDEX_DISP), FULL (lda_index_disp) FAST (lda_index_disp) }, - { TYPE (INSN_LDA_INDIRECT_INDEX_DISP), IDX (INSN_LDA_INDIRECT_INDEX_DISP), FULL (lda_indirect_index_disp) FAST (lda_indirect_index_disp) }, - { TYPE (INSN_LD_OFFSET), IDX (INSN_LD_OFFSET), FULL (ld_offset) FAST (ld_offset) }, - { TYPE (INSN_LD_INDIRECT_OFFSET), IDX (INSN_LD_INDIRECT_OFFSET), FULL (ld_indirect_offset) FAST (ld_indirect_offset) }, - { TYPE (INSN_LD_INDIRECT), IDX (INSN_LD_INDIRECT), FULL (ld_indirect) FAST (ld_indirect) }, - { TYPE (INSN_LD_INDIRECT_INDEX), IDX (INSN_LD_INDIRECT_INDEX), FULL (ld_indirect_index) FAST (ld_indirect_index) }, - { TYPE (INSN_LD_DISP), IDX (INSN_LD_DISP), FULL (ld_disp) FAST (ld_disp) }, - { TYPE (INSN_LD_INDIRECT_DISP), IDX (INSN_LD_INDIRECT_DISP), FULL (ld_indirect_disp) FAST (ld_indirect_disp) }, - { TYPE (INSN_LD_INDEX_DISP), IDX (INSN_LD_INDEX_DISP), FULL (ld_index_disp) FAST (ld_index_disp) }, - { TYPE (INSN_LD_INDIRECT_INDEX_DISP), IDX (INSN_LD_INDIRECT_INDEX_DISP), FULL (ld_indirect_index_disp) FAST (ld_indirect_index_disp) }, - { TYPE (INSN_LDOB_OFFSET), IDX (INSN_LDOB_OFFSET), FULL (ldob_offset) FAST (ldob_offset) }, - { TYPE (INSN_LDOB_INDIRECT_OFFSET), IDX (INSN_LDOB_INDIRECT_OFFSET), FULL (ldob_indirect_offset) FAST (ldob_indirect_offset) }, - { TYPE (INSN_LDOB_INDIRECT), IDX (INSN_LDOB_INDIRECT), FULL (ldob_indirect) FAST (ldob_indirect) }, - { TYPE (INSN_LDOB_INDIRECT_INDEX), IDX (INSN_LDOB_INDIRECT_INDEX), FULL (ldob_indirect_index) FAST (ldob_indirect_index) }, - { TYPE (INSN_LDOB_DISP), IDX (INSN_LDOB_DISP), FULL (ldob_disp) FAST (ldob_disp) }, - { TYPE (INSN_LDOB_INDIRECT_DISP), IDX (INSN_LDOB_INDIRECT_DISP), FULL (ldob_indirect_disp) FAST (ldob_indirect_disp) }, - { TYPE (INSN_LDOB_INDEX_DISP), IDX (INSN_LDOB_INDEX_DISP), FULL (ldob_index_disp) FAST (ldob_index_disp) }, - { TYPE (INSN_LDOB_INDIRECT_INDEX_DISP), IDX (INSN_LDOB_INDIRECT_INDEX_DISP), FULL (ldob_indirect_index_disp) FAST (ldob_indirect_index_disp) }, - { TYPE (INSN_LDOS_OFFSET), IDX (INSN_LDOS_OFFSET), FULL (ldos_offset) FAST (ldos_offset) }, - { TYPE (INSN_LDOS_INDIRECT_OFFSET), IDX (INSN_LDOS_INDIRECT_OFFSET), FULL (ldos_indirect_offset) FAST (ldos_indirect_offset) }, - { TYPE (INSN_LDOS_INDIRECT), IDX (INSN_LDOS_INDIRECT), FULL (ldos_indirect) FAST (ldos_indirect) }, - { TYPE (INSN_LDOS_INDIRECT_INDEX), IDX (INSN_LDOS_INDIRECT_INDEX), FULL (ldos_indirect_index) FAST (ldos_indirect_index) }, - { TYPE (INSN_LDOS_DISP), IDX (INSN_LDOS_DISP), FULL (ldos_disp) FAST (ldos_disp) }, - { TYPE (INSN_LDOS_INDIRECT_DISP), IDX (INSN_LDOS_INDIRECT_DISP), FULL (ldos_indirect_disp) FAST (ldos_indirect_disp) }, - { TYPE (INSN_LDOS_INDEX_DISP), IDX (INSN_LDOS_INDEX_DISP), FULL (ldos_index_disp) FAST (ldos_index_disp) }, - { TYPE (INSN_LDOS_INDIRECT_INDEX_DISP), IDX (INSN_LDOS_INDIRECT_INDEX_DISP), FULL (ldos_indirect_index_disp) FAST (ldos_indirect_index_disp) }, - { TYPE (INSN_LDIB_OFFSET), IDX (INSN_LDIB_OFFSET), FULL (ldib_offset) FAST (ldib_offset) }, - { TYPE (INSN_LDIB_INDIRECT_OFFSET), IDX (INSN_LDIB_INDIRECT_OFFSET), FULL (ldib_indirect_offset) FAST (ldib_indirect_offset) }, - { TYPE (INSN_LDIB_INDIRECT), IDX (INSN_LDIB_INDIRECT), FULL (ldib_indirect) FAST (ldib_indirect) }, - { TYPE (INSN_LDIB_INDIRECT_INDEX), IDX (INSN_LDIB_INDIRECT_INDEX), FULL (ldib_indirect_index) FAST (ldib_indirect_index) }, - { TYPE (INSN_LDIB_DISP), IDX (INSN_LDIB_DISP), FULL (ldib_disp) FAST (ldib_disp) }, - { TYPE (INSN_LDIB_INDIRECT_DISP), IDX (INSN_LDIB_INDIRECT_DISP), FULL (ldib_indirect_disp) FAST (ldib_indirect_disp) }, - { TYPE (INSN_LDIB_INDEX_DISP), IDX (INSN_LDIB_INDEX_DISP), FULL (ldib_index_disp) FAST (ldib_index_disp) }, - { TYPE (INSN_LDIB_INDIRECT_INDEX_DISP), IDX (INSN_LDIB_INDIRECT_INDEX_DISP), FULL (ldib_indirect_index_disp) FAST (ldib_indirect_index_disp) }, - { TYPE (INSN_LDIS_OFFSET), IDX (INSN_LDIS_OFFSET), FULL (ldis_offset) FAST (ldis_offset) }, - { TYPE (INSN_LDIS_INDIRECT_OFFSET), IDX (INSN_LDIS_INDIRECT_OFFSET), FULL (ldis_indirect_offset) FAST (ldis_indirect_offset) }, - { TYPE (INSN_LDIS_INDIRECT), IDX (INSN_LDIS_INDIRECT), FULL (ldis_indirect) FAST (ldis_indirect) }, - { TYPE (INSN_LDIS_INDIRECT_INDEX), IDX (INSN_LDIS_INDIRECT_INDEX), FULL (ldis_indirect_index) FAST (ldis_indirect_index) }, - { TYPE (INSN_LDIS_DISP), IDX (INSN_LDIS_DISP), FULL (ldis_disp) FAST (ldis_disp) }, - { TYPE (INSN_LDIS_INDIRECT_DISP), IDX (INSN_LDIS_INDIRECT_DISP), FULL (ldis_indirect_disp) FAST (ldis_indirect_disp) }, - { TYPE (INSN_LDIS_INDEX_DISP), IDX (INSN_LDIS_INDEX_DISP), FULL (ldis_index_disp) FAST (ldis_index_disp) }, - { TYPE (INSN_LDIS_INDIRECT_INDEX_DISP), IDX (INSN_LDIS_INDIRECT_INDEX_DISP), FULL (ldis_indirect_index_disp) FAST (ldis_indirect_index_disp) }, - { TYPE (INSN_LDL_OFFSET), IDX (INSN_LDL_OFFSET), FULL (ldl_offset) FAST (ldl_offset) }, - { TYPE (INSN_LDL_INDIRECT_OFFSET), IDX (INSN_LDL_INDIRECT_OFFSET), FULL (ldl_indirect_offset) FAST (ldl_indirect_offset) }, - { TYPE (INSN_LDL_INDIRECT), IDX (INSN_LDL_INDIRECT), FULL (ldl_indirect) FAST (ldl_indirect) }, - { TYPE (INSN_LDL_INDIRECT_INDEX), IDX (INSN_LDL_INDIRECT_INDEX), FULL (ldl_indirect_index) FAST (ldl_indirect_index) }, - { TYPE (INSN_LDL_DISP), IDX (INSN_LDL_DISP), FULL (ldl_disp) FAST (ldl_disp) }, - { TYPE (INSN_LDL_INDIRECT_DISP), IDX (INSN_LDL_INDIRECT_DISP), FULL (ldl_indirect_disp) FAST (ldl_indirect_disp) }, - { TYPE (INSN_LDL_INDEX_DISP), IDX (INSN_LDL_INDEX_DISP), FULL (ldl_index_disp) FAST (ldl_index_disp) }, - { TYPE (INSN_LDL_INDIRECT_INDEX_DISP), IDX (INSN_LDL_INDIRECT_INDEX_DISP), FULL (ldl_indirect_index_disp) FAST (ldl_indirect_index_disp) }, - { TYPE (INSN_LDT_OFFSET), IDX (INSN_LDT_OFFSET), FULL (ldt_offset) FAST (ldt_offset) }, - { TYPE (INSN_LDT_INDIRECT_OFFSET), IDX (INSN_LDT_INDIRECT_OFFSET), FULL (ldt_indirect_offset) FAST (ldt_indirect_offset) }, - { TYPE (INSN_LDT_INDIRECT), IDX (INSN_LDT_INDIRECT), FULL (ldt_indirect) FAST (ldt_indirect) }, - { TYPE (INSN_LDT_INDIRECT_INDEX), IDX (INSN_LDT_INDIRECT_INDEX), FULL (ldt_indirect_index) FAST (ldt_indirect_index) }, - { TYPE (INSN_LDT_DISP), IDX (INSN_LDT_DISP), FULL (ldt_disp) FAST (ldt_disp) }, - { TYPE (INSN_LDT_INDIRECT_DISP), IDX (INSN_LDT_INDIRECT_DISP), FULL (ldt_indirect_disp) FAST (ldt_indirect_disp) }, - { TYPE (INSN_LDT_INDEX_DISP), IDX (INSN_LDT_INDEX_DISP), FULL (ldt_index_disp) FAST (ldt_index_disp) }, - { TYPE (INSN_LDT_INDIRECT_INDEX_DISP), IDX (INSN_LDT_INDIRECT_INDEX_DISP), FULL (ldt_indirect_index_disp) FAST (ldt_indirect_index_disp) }, - { TYPE (INSN_LDQ_OFFSET), IDX (INSN_LDQ_OFFSET), FULL (ldq_offset) FAST (ldq_offset) }, - { TYPE (INSN_LDQ_INDIRECT_OFFSET), IDX (INSN_LDQ_INDIRECT_OFFSET), FULL (ldq_indirect_offset) FAST (ldq_indirect_offset) }, - { TYPE (INSN_LDQ_INDIRECT), IDX (INSN_LDQ_INDIRECT), FULL (ldq_indirect) FAST (ldq_indirect) }, - { TYPE (INSN_LDQ_INDIRECT_INDEX), IDX (INSN_LDQ_INDIRECT_INDEX), FULL (ldq_indirect_index) FAST (ldq_indirect_index) }, - { TYPE (INSN_LDQ_DISP), IDX (INSN_LDQ_DISP), FULL (ldq_disp) FAST (ldq_disp) }, - { TYPE (INSN_LDQ_INDIRECT_DISP), IDX (INSN_LDQ_INDIRECT_DISP), FULL (ldq_indirect_disp) FAST (ldq_indirect_disp) }, - { TYPE (INSN_LDQ_INDEX_DISP), IDX (INSN_LDQ_INDEX_DISP), FULL (ldq_index_disp) FAST (ldq_index_disp) }, - { TYPE (INSN_LDQ_INDIRECT_INDEX_DISP), IDX (INSN_LDQ_INDIRECT_INDEX_DISP), FULL (ldq_indirect_index_disp) FAST (ldq_indirect_index_disp) }, - { TYPE (INSN_ST_OFFSET), IDX (INSN_ST_OFFSET), FULL (st_offset) FAST (st_offset) }, - { TYPE (INSN_ST_INDIRECT_OFFSET), IDX (INSN_ST_INDIRECT_OFFSET), FULL (st_indirect_offset) FAST (st_indirect_offset) }, - { TYPE (INSN_ST_INDIRECT), IDX (INSN_ST_INDIRECT), FULL (st_indirect) FAST (st_indirect) }, - { TYPE (INSN_ST_INDIRECT_INDEX), IDX (INSN_ST_INDIRECT_INDEX), FULL (st_indirect_index) FAST (st_indirect_index) }, - { TYPE (INSN_ST_DISP), IDX (INSN_ST_DISP), FULL (st_disp) FAST (st_disp) }, - { TYPE (INSN_ST_INDIRECT_DISP), IDX (INSN_ST_INDIRECT_DISP), FULL (st_indirect_disp) FAST (st_indirect_disp) }, - { TYPE (INSN_ST_INDEX_DISP), IDX (INSN_ST_INDEX_DISP), FULL (st_index_disp) FAST (st_index_disp) }, - { TYPE (INSN_ST_INDIRECT_INDEX_DISP), IDX (INSN_ST_INDIRECT_INDEX_DISP), FULL (st_indirect_index_disp) FAST (st_indirect_index_disp) }, - { TYPE (INSN_STOB_OFFSET), IDX (INSN_STOB_OFFSET), FULL (stob_offset) FAST (stob_offset) }, - { TYPE (INSN_STOB_INDIRECT_OFFSET), IDX (INSN_STOB_INDIRECT_OFFSET), FULL (stob_indirect_offset) FAST (stob_indirect_offset) }, - { TYPE (INSN_STOB_INDIRECT), IDX (INSN_STOB_INDIRECT), FULL (stob_indirect) FAST (stob_indirect) }, - { TYPE (INSN_STOB_INDIRECT_INDEX), IDX (INSN_STOB_INDIRECT_INDEX), FULL (stob_indirect_index) FAST (stob_indirect_index) }, - { TYPE (INSN_STOB_DISP), IDX (INSN_STOB_DISP), FULL (stob_disp) FAST (stob_disp) }, - { TYPE (INSN_STOB_INDIRECT_DISP), IDX (INSN_STOB_INDIRECT_DISP), FULL (stob_indirect_disp) FAST (stob_indirect_disp) }, - { TYPE (INSN_STOB_INDEX_DISP), IDX (INSN_STOB_INDEX_DISP), FULL (stob_index_disp) FAST (stob_index_disp) }, - { TYPE (INSN_STOB_INDIRECT_INDEX_DISP), IDX (INSN_STOB_INDIRECT_INDEX_DISP), FULL (stob_indirect_index_disp) FAST (stob_indirect_index_disp) }, - { TYPE (INSN_STOS_OFFSET), IDX (INSN_STOS_OFFSET), FULL (stos_offset) FAST (stos_offset) }, - { TYPE (INSN_STOS_INDIRECT_OFFSET), IDX (INSN_STOS_INDIRECT_OFFSET), FULL (stos_indirect_offset) FAST (stos_indirect_offset) }, - { TYPE (INSN_STOS_INDIRECT), IDX (INSN_STOS_INDIRECT), FULL (stos_indirect) FAST (stos_indirect) }, - { TYPE (INSN_STOS_INDIRECT_INDEX), IDX (INSN_STOS_INDIRECT_INDEX), FULL (stos_indirect_index) FAST (stos_indirect_index) }, - { TYPE (INSN_STOS_DISP), IDX (INSN_STOS_DISP), FULL (stos_disp) FAST (stos_disp) }, - { TYPE (INSN_STOS_INDIRECT_DISP), IDX (INSN_STOS_INDIRECT_DISP), FULL (stos_indirect_disp) FAST (stos_indirect_disp) }, - { TYPE (INSN_STOS_INDEX_DISP), IDX (INSN_STOS_INDEX_DISP), FULL (stos_index_disp) FAST (stos_index_disp) }, - { TYPE (INSN_STOS_INDIRECT_INDEX_DISP), IDX (INSN_STOS_INDIRECT_INDEX_DISP), FULL (stos_indirect_index_disp) FAST (stos_indirect_index_disp) }, - { TYPE (INSN_STL_OFFSET), IDX (INSN_STL_OFFSET), FULL (stl_offset) FAST (stl_offset) }, - { TYPE (INSN_STL_INDIRECT_OFFSET), IDX (INSN_STL_INDIRECT_OFFSET), FULL (stl_indirect_offset) FAST (stl_indirect_offset) }, - { TYPE (INSN_STL_INDIRECT), IDX (INSN_STL_INDIRECT), FULL (stl_indirect) FAST (stl_indirect) }, - { TYPE (INSN_STL_INDIRECT_INDEX), IDX (INSN_STL_INDIRECT_INDEX), FULL (stl_indirect_index) FAST (stl_indirect_index) }, - { TYPE (INSN_STL_DISP), IDX (INSN_STL_DISP), FULL (stl_disp) FAST (stl_disp) }, - { TYPE (INSN_STL_INDIRECT_DISP), IDX (INSN_STL_INDIRECT_DISP), FULL (stl_indirect_disp) FAST (stl_indirect_disp) }, - { TYPE (INSN_STL_INDEX_DISP), IDX (INSN_STL_INDEX_DISP), FULL (stl_index_disp) FAST (stl_index_disp) }, - { TYPE (INSN_STL_INDIRECT_INDEX_DISP), IDX (INSN_STL_INDIRECT_INDEX_DISP), FULL (stl_indirect_index_disp) FAST (stl_indirect_index_disp) }, - { TYPE (INSN_STT_OFFSET), IDX (INSN_STT_OFFSET), FULL (stt_offset) FAST (stt_offset) }, - { TYPE (INSN_STT_INDIRECT_OFFSET), IDX (INSN_STT_INDIRECT_OFFSET), FULL (stt_indirect_offset) FAST (stt_indirect_offset) }, - { TYPE (INSN_STT_INDIRECT), IDX (INSN_STT_INDIRECT), FULL (stt_indirect) FAST (stt_indirect) }, - { TYPE (INSN_STT_INDIRECT_INDEX), IDX (INSN_STT_INDIRECT_INDEX), FULL (stt_indirect_index) FAST (stt_indirect_index) }, - { TYPE (INSN_STT_DISP), IDX (INSN_STT_DISP), FULL (stt_disp) FAST (stt_disp) }, - { TYPE (INSN_STT_INDIRECT_DISP), IDX (INSN_STT_INDIRECT_DISP), FULL (stt_indirect_disp) FAST (stt_indirect_disp) }, - { TYPE (INSN_STT_INDEX_DISP), IDX (INSN_STT_INDEX_DISP), FULL (stt_index_disp) FAST (stt_index_disp) }, - { TYPE (INSN_STT_INDIRECT_INDEX_DISP), IDX (INSN_STT_INDIRECT_INDEX_DISP), FULL (stt_indirect_index_disp) FAST (stt_indirect_index_disp) }, - { TYPE (INSN_STQ_OFFSET), IDX (INSN_STQ_OFFSET), FULL (stq_offset) FAST (stq_offset) }, - { TYPE (INSN_STQ_INDIRECT_OFFSET), IDX (INSN_STQ_INDIRECT_OFFSET), FULL (stq_indirect_offset) FAST (stq_indirect_offset) }, - { TYPE (INSN_STQ_INDIRECT), IDX (INSN_STQ_INDIRECT), FULL (stq_indirect) FAST (stq_indirect) }, - { TYPE (INSN_STQ_INDIRECT_INDEX), IDX (INSN_STQ_INDIRECT_INDEX), FULL (stq_indirect_index) FAST (stq_indirect_index) }, - { TYPE (INSN_STQ_DISP), IDX (INSN_STQ_DISP), FULL (stq_disp) FAST (stq_disp) }, - { TYPE (INSN_STQ_INDIRECT_DISP), IDX (INSN_STQ_INDIRECT_DISP), FULL (stq_indirect_disp) FAST (stq_indirect_disp) }, - { TYPE (INSN_STQ_INDEX_DISP), IDX (INSN_STQ_INDEX_DISP), FULL (stq_index_disp) FAST (stq_index_disp) }, - { TYPE (INSN_STQ_INDIRECT_INDEX_DISP), IDX (INSN_STQ_INDIRECT_INDEX_DISP), FULL (stq_indirect_index_disp) FAST (stq_indirect_index_disp) }, - { TYPE (INSN_CMPOBE_REG), IDX (INSN_CMPOBE_REG), FULL (cmpobe_reg) FAST (cmpobe_reg) }, - { TYPE (INSN_CMPOBE_LIT), IDX (INSN_CMPOBE_LIT), FULL (cmpobe_lit) FAST (cmpobe_lit) }, - { TYPE (INSN_CMPOBNE_REG), IDX (INSN_CMPOBNE_REG), FULL (cmpobne_reg) FAST (cmpobne_reg) }, - { TYPE (INSN_CMPOBNE_LIT), IDX (INSN_CMPOBNE_LIT), FULL (cmpobne_lit) FAST (cmpobne_lit) }, - { TYPE (INSN_CMPOBL_REG), IDX (INSN_CMPOBL_REG), FULL (cmpobl_reg) FAST (cmpobl_reg) }, - { TYPE (INSN_CMPOBL_LIT), IDX (INSN_CMPOBL_LIT), FULL (cmpobl_lit) FAST (cmpobl_lit) }, - { TYPE (INSN_CMPOBLE_REG), IDX (INSN_CMPOBLE_REG), FULL (cmpoble_reg) FAST (cmpoble_reg) }, - { TYPE (INSN_CMPOBLE_LIT), IDX (INSN_CMPOBLE_LIT), FULL (cmpoble_lit) FAST (cmpoble_lit) }, - { TYPE (INSN_CMPOBG_REG), IDX (INSN_CMPOBG_REG), FULL (cmpobg_reg) FAST (cmpobg_reg) }, - { TYPE (INSN_CMPOBG_LIT), IDX (INSN_CMPOBG_LIT), FULL (cmpobg_lit) FAST (cmpobg_lit) }, - { TYPE (INSN_CMPOBGE_REG), IDX (INSN_CMPOBGE_REG), FULL (cmpobge_reg) FAST (cmpobge_reg) }, - { TYPE (INSN_CMPOBGE_LIT), IDX (INSN_CMPOBGE_LIT), FULL (cmpobge_lit) FAST (cmpobge_lit) }, - { TYPE (INSN_CMPIBE_REG), IDX (INSN_CMPIBE_REG), FULL (cmpibe_reg) FAST (cmpibe_reg) }, - { TYPE (INSN_CMPIBE_LIT), IDX (INSN_CMPIBE_LIT), FULL (cmpibe_lit) FAST (cmpibe_lit) }, - { TYPE (INSN_CMPIBNE_REG), IDX (INSN_CMPIBNE_REG), FULL (cmpibne_reg) FAST (cmpibne_reg) }, - { TYPE (INSN_CMPIBNE_LIT), IDX (INSN_CMPIBNE_LIT), FULL (cmpibne_lit) FAST (cmpibne_lit) }, - { TYPE (INSN_CMPIBL_REG), IDX (INSN_CMPIBL_REG), FULL (cmpibl_reg) FAST (cmpibl_reg) }, - { TYPE (INSN_CMPIBL_LIT), IDX (INSN_CMPIBL_LIT), FULL (cmpibl_lit) FAST (cmpibl_lit) }, - { TYPE (INSN_CMPIBLE_REG), IDX (INSN_CMPIBLE_REG), FULL (cmpible_reg) FAST (cmpible_reg) }, - { TYPE (INSN_CMPIBLE_LIT), IDX (INSN_CMPIBLE_LIT), FULL (cmpible_lit) FAST (cmpible_lit) }, - { TYPE (INSN_CMPIBG_REG), IDX (INSN_CMPIBG_REG), FULL (cmpibg_reg) FAST (cmpibg_reg) }, - { TYPE (INSN_CMPIBG_LIT), IDX (INSN_CMPIBG_LIT), FULL (cmpibg_lit) FAST (cmpibg_lit) }, - { TYPE (INSN_CMPIBGE_REG), IDX (INSN_CMPIBGE_REG), FULL (cmpibge_reg) FAST (cmpibge_reg) }, - { TYPE (INSN_CMPIBGE_LIT), IDX (INSN_CMPIBGE_LIT), FULL (cmpibge_lit) FAST (cmpibge_lit) }, - { TYPE (INSN_BBC_REG), IDX (INSN_BBC_REG), FULL (bbc_reg) FAST (bbc_reg) }, - { TYPE (INSN_BBC_LIT), IDX (INSN_BBC_LIT), FULL (bbc_lit) FAST (bbc_lit) }, - { TYPE (INSN_BBS_REG), IDX (INSN_BBS_REG), FULL (bbs_reg) FAST (bbs_reg) }, - { TYPE (INSN_BBS_LIT), IDX (INSN_BBS_LIT), FULL (bbs_lit) FAST (bbs_lit) }, - { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) }, - { TYPE (INSN_CMPI1), IDX (INSN_CMPI1), FULL (cmpi1) FAST (cmpi1) }, - { TYPE (INSN_CMPI2), IDX (INSN_CMPI2), FULL (cmpi2) FAST (cmpi2) }, - { TYPE (INSN_CMPI3), IDX (INSN_CMPI3), FULL (cmpi3) FAST (cmpi3) }, - { TYPE (INSN_CMPO), IDX (INSN_CMPO), FULL (cmpo) FAST (cmpo) }, - { TYPE (INSN_CMPO1), IDX (INSN_CMPO1), FULL (cmpo1) FAST (cmpo1) }, - { TYPE (INSN_CMPO2), IDX (INSN_CMPO2), FULL (cmpo2) FAST (cmpo2) }, - { TYPE (INSN_CMPO3), IDX (INSN_CMPO3), FULL (cmpo3) FAST (cmpo3) }, - { TYPE (INSN_TESTNO_REG), IDX (INSN_TESTNO_REG), FULL (testno_reg) FAST (testno_reg) }, - { TYPE (INSN_TESTG_REG), IDX (INSN_TESTG_REG), FULL (testg_reg) FAST (testg_reg) }, - { TYPE (INSN_TESTE_REG), IDX (INSN_TESTE_REG), FULL (teste_reg) FAST (teste_reg) }, - { TYPE (INSN_TESTGE_REG), IDX (INSN_TESTGE_REG), FULL (testge_reg) FAST (testge_reg) }, - { TYPE (INSN_TESTL_REG), IDX (INSN_TESTL_REG), FULL (testl_reg) FAST (testl_reg) }, - { TYPE (INSN_TESTNE_REG), IDX (INSN_TESTNE_REG), FULL (testne_reg) FAST (testne_reg) }, - { TYPE (INSN_TESTLE_REG), IDX (INSN_TESTLE_REG), FULL (testle_reg) FAST (testle_reg) }, - { TYPE (INSN_TESTO_REG), IDX (INSN_TESTO_REG), FULL (testo_reg) FAST (testo_reg) }, - { TYPE (INSN_BNO), IDX (INSN_BNO), FULL (bno) FAST (bno) }, - { TYPE (INSN_BG), IDX (INSN_BG), FULL (bg) FAST (bg) }, - { TYPE (INSN_BE), IDX (INSN_BE), FULL (be) FAST (be) }, - { TYPE (INSN_BGE), IDX (INSN_BGE), FULL (bge) FAST (bge) }, - { TYPE (INSN_BL), IDX (INSN_BL), FULL (bl) FAST (bl) }, - { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, - { TYPE (INSN_BLE), IDX (INSN_BLE), FULL (ble) FAST (ble) }, - { TYPE (INSN_BO), IDX (INSN_BO), FULL (bo) FAST (bo) }, - { TYPE (INSN_B), IDX (INSN_B), FULL (b) FAST (b) }, - { TYPE (INSN_BX_INDIRECT_OFFSET), IDX (INSN_BX_INDIRECT_OFFSET), FULL (bx_indirect_offset) FAST (bx_indirect_offset) }, - { TYPE (INSN_BX_INDIRECT), IDX (INSN_BX_INDIRECT), FULL (bx_indirect) FAST (bx_indirect) }, - { TYPE (INSN_BX_INDIRECT_INDEX), IDX (INSN_BX_INDIRECT_INDEX), FULL (bx_indirect_index) FAST (bx_indirect_index) }, - { TYPE (INSN_BX_DISP), IDX (INSN_BX_DISP), FULL (bx_disp) FAST (bx_disp) }, - { TYPE (INSN_BX_INDIRECT_DISP), IDX (INSN_BX_INDIRECT_DISP), FULL (bx_indirect_disp) FAST (bx_indirect_disp) }, - { TYPE (INSN_CALLX_DISP), IDX (INSN_CALLX_DISP), FULL (callx_disp) FAST (callx_disp) }, - { TYPE (INSN_CALLX_INDIRECT), IDX (INSN_CALLX_INDIRECT), FULL (callx_indirect) FAST (callx_indirect) }, - { TYPE (INSN_CALLX_INDIRECT_OFFSET), IDX (INSN_CALLX_INDIRECT_OFFSET), FULL (callx_indirect_offset) FAST (callx_indirect_offset) }, - { TYPE (INSN_RET), IDX (INSN_RET), FULL (ret) FAST (ret) }, - { TYPE (INSN_CALLS), IDX (INSN_CALLS), FULL (calls) FAST (calls) }, - { TYPE (INSN_FMARK), IDX (INSN_FMARK), FULL (fmark) FAST (fmark) }, - { TYPE (INSN_FLUSHREG), IDX (INSN_FLUSHREG), FULL (flushreg) FAST (flushreg) }, + { VIRTUAL_INSN_X_INVALID, I960BASE_INSN_X_INVALID, I960BASE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, I960BASE_INSN_X_AFTER, I960BASE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, I960BASE_INSN_X_BEFORE, I960BASE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, I960BASE_INSN_X_CTI_CHAIN, I960BASE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, I960BASE_INSN_X_CHAIN, I960BASE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, I960BASE_INSN_X_BEGIN, I960BASE_SFMT_EMPTY }, + { I960_INSN_MULO, I960BASE_INSN_MULO, I960BASE_SFMT_MULO }, + { I960_INSN_MULO1, I960BASE_INSN_MULO1, I960BASE_SFMT_MULO1 }, + { I960_INSN_MULO2, I960BASE_INSN_MULO2, I960BASE_SFMT_MULO2 }, + { I960_INSN_MULO3, I960BASE_INSN_MULO3, I960BASE_SFMT_MULO3 }, + { I960_INSN_REMO, I960BASE_INSN_REMO, I960BASE_SFMT_MULO }, + { I960_INSN_REMO1, I960BASE_INSN_REMO1, I960BASE_SFMT_MULO1 }, + { I960_INSN_REMO2, I960BASE_INSN_REMO2, I960BASE_SFMT_MULO2 }, + { I960_INSN_REMO3, I960BASE_INSN_REMO3, I960BASE_SFMT_MULO3 }, + { I960_INSN_DIVO, I960BASE_INSN_DIVO, I960BASE_SFMT_MULO }, + { I960_INSN_DIVO1, I960BASE_INSN_DIVO1, I960BASE_SFMT_MULO1 }, + { I960_INSN_DIVO2, I960BASE_INSN_DIVO2, I960BASE_SFMT_MULO2 }, + { I960_INSN_DIVO3, I960BASE_INSN_DIVO3, I960BASE_SFMT_MULO3 }, + { I960_INSN_REMI, I960BASE_INSN_REMI, I960BASE_SFMT_MULO }, + { I960_INSN_REMI1, I960BASE_INSN_REMI1, I960BASE_SFMT_MULO1 }, + { I960_INSN_REMI2, I960BASE_INSN_REMI2, I960BASE_SFMT_MULO2 }, + { I960_INSN_REMI3, I960BASE_INSN_REMI3, I960BASE_SFMT_MULO3 }, + { I960_INSN_DIVI, I960BASE_INSN_DIVI, I960BASE_SFMT_MULO }, + { I960_INSN_DIVI1, I960BASE_INSN_DIVI1, I960BASE_SFMT_MULO1 }, + { I960_INSN_DIVI2, I960BASE_INSN_DIVI2, I960BASE_SFMT_MULO2 }, + { I960_INSN_DIVI3, I960BASE_INSN_DIVI3, I960BASE_SFMT_MULO3 }, + { I960_INSN_ADDO, I960BASE_INSN_ADDO, I960BASE_SFMT_MULO }, + { I960_INSN_ADDO1, I960BASE_INSN_ADDO1, I960BASE_SFMT_MULO1 }, + { I960_INSN_ADDO2, I960BASE_INSN_ADDO2, I960BASE_SFMT_MULO2 }, + { I960_INSN_ADDO3, I960BASE_INSN_ADDO3, I960BASE_SFMT_MULO3 }, + { I960_INSN_SUBO, I960BASE_INSN_SUBO, I960BASE_SFMT_MULO }, + { I960_INSN_SUBO1, I960BASE_INSN_SUBO1, I960BASE_SFMT_MULO1 }, + { I960_INSN_SUBO2, I960BASE_INSN_SUBO2, I960BASE_SFMT_MULO2 }, + { I960_INSN_SUBO3, I960BASE_INSN_SUBO3, I960BASE_SFMT_MULO3 }, + { I960_INSN_NOTBIT, I960BASE_INSN_NOTBIT, I960BASE_SFMT_NOTBIT }, + { I960_INSN_NOTBIT1, I960BASE_INSN_NOTBIT1, I960BASE_SFMT_NOTBIT1 }, + { I960_INSN_NOTBIT2, I960BASE_INSN_NOTBIT2, I960BASE_SFMT_NOTBIT2 }, + { I960_INSN_NOTBIT3, I960BASE_INSN_NOTBIT3, I960BASE_SFMT_NOTBIT3 }, + { I960_INSN_AND, I960BASE_INSN_AND, I960BASE_SFMT_MULO }, + { I960_INSN_AND1, I960BASE_INSN_AND1, I960BASE_SFMT_MULO1 }, + { I960_INSN_AND2, I960BASE_INSN_AND2, I960BASE_SFMT_MULO2 }, + { I960_INSN_AND3, I960BASE_INSN_AND3, I960BASE_SFMT_MULO3 }, + { I960_INSN_ANDNOT, I960BASE_INSN_ANDNOT, I960BASE_SFMT_MULO }, + { I960_INSN_ANDNOT1, I960BASE_INSN_ANDNOT1, I960BASE_SFMT_MULO1 }, + { I960_INSN_ANDNOT2, I960BASE_INSN_ANDNOT2, I960BASE_SFMT_MULO2 }, + { I960_INSN_ANDNOT3, I960BASE_INSN_ANDNOT3, I960BASE_SFMT_MULO3 }, + { I960_INSN_SETBIT, I960BASE_INSN_SETBIT, I960BASE_SFMT_NOTBIT }, + { I960_INSN_SETBIT1, I960BASE_INSN_SETBIT1, I960BASE_SFMT_NOTBIT1 }, + { I960_INSN_SETBIT2, I960BASE_INSN_SETBIT2, I960BASE_SFMT_NOTBIT2 }, + { I960_INSN_SETBIT3, I960BASE_INSN_SETBIT3, I960BASE_SFMT_NOTBIT3 }, + { I960_INSN_NOTAND, I960BASE_INSN_NOTAND, I960BASE_SFMT_MULO }, + { I960_INSN_NOTAND1, I960BASE_INSN_NOTAND1, I960BASE_SFMT_MULO1 }, + { I960_INSN_NOTAND2, I960BASE_INSN_NOTAND2, I960BASE_SFMT_MULO2 }, + { I960_INSN_NOTAND3, I960BASE_INSN_NOTAND3, I960BASE_SFMT_MULO3 }, + { I960_INSN_XOR, I960BASE_INSN_XOR, I960BASE_SFMT_MULO }, + { I960_INSN_XOR1, I960BASE_INSN_XOR1, I960BASE_SFMT_MULO1 }, + { I960_INSN_XOR2, I960BASE_INSN_XOR2, I960BASE_SFMT_MULO2 }, + { I960_INSN_XOR3, I960BASE_INSN_XOR3, I960BASE_SFMT_MULO3 }, + { I960_INSN_OR, I960BASE_INSN_OR, I960BASE_SFMT_MULO }, + { I960_INSN_OR1, I960BASE_INSN_OR1, I960BASE_SFMT_MULO1 }, + { I960_INSN_OR2, I960BASE_INSN_OR2, I960BASE_SFMT_MULO2 }, + { I960_INSN_OR3, I960BASE_INSN_OR3, I960BASE_SFMT_MULO3 }, + { I960_INSN_NOR, I960BASE_INSN_NOR, I960BASE_SFMT_MULO }, + { I960_INSN_NOR1, I960BASE_INSN_NOR1, I960BASE_SFMT_MULO1 }, + { I960_INSN_NOR2, I960BASE_INSN_NOR2, I960BASE_SFMT_MULO2 }, + { I960_INSN_NOR3, I960BASE_INSN_NOR3, I960BASE_SFMT_MULO3 }, + { I960_INSN_XNOR, I960BASE_INSN_XNOR, I960BASE_SFMT_MULO }, + { I960_INSN_XNOR1, I960BASE_INSN_XNOR1, I960BASE_SFMT_MULO1 }, + { I960_INSN_XNOR2, I960BASE_INSN_XNOR2, I960BASE_SFMT_MULO2 }, + { I960_INSN_XNOR3, I960BASE_INSN_XNOR3, I960BASE_SFMT_MULO3 }, + { I960_INSN_NOT, I960BASE_INSN_NOT, I960BASE_SFMT_NOT }, + { I960_INSN_NOT1, I960BASE_INSN_NOT1, I960BASE_SFMT_NOT1 }, + { I960_INSN_NOT2, I960BASE_INSN_NOT2, I960BASE_SFMT_NOT }, + { I960_INSN_NOT3, I960BASE_INSN_NOT3, I960BASE_SFMT_NOT1 }, + { I960_INSN_ORNOT, I960BASE_INSN_ORNOT, I960BASE_SFMT_MULO }, + { I960_INSN_ORNOT1, I960BASE_INSN_ORNOT1, I960BASE_SFMT_MULO1 }, + { I960_INSN_ORNOT2, I960BASE_INSN_ORNOT2, I960BASE_SFMT_MULO2 }, + { I960_INSN_ORNOT3, I960BASE_INSN_ORNOT3, I960BASE_SFMT_MULO3 }, + { I960_INSN_CLRBIT, I960BASE_INSN_CLRBIT, I960BASE_SFMT_NOTBIT }, + { I960_INSN_CLRBIT1, I960BASE_INSN_CLRBIT1, I960BASE_SFMT_NOTBIT1 }, + { I960_INSN_CLRBIT2, I960BASE_INSN_CLRBIT2, I960BASE_SFMT_NOTBIT2 }, + { I960_INSN_CLRBIT3, I960BASE_INSN_CLRBIT3, I960BASE_SFMT_NOTBIT3 }, + { I960_INSN_SHLO, I960BASE_INSN_SHLO, I960BASE_SFMT_SHLO }, + { I960_INSN_SHLO1, I960BASE_INSN_SHLO1, I960BASE_SFMT_SHLO1 }, + { I960_INSN_SHLO2, I960BASE_INSN_SHLO2, I960BASE_SFMT_SHLO2 }, + { I960_INSN_SHLO3, I960BASE_INSN_SHLO3, I960BASE_SFMT_SHLO3 }, + { I960_INSN_SHRO, I960BASE_INSN_SHRO, I960BASE_SFMT_SHLO }, + { I960_INSN_SHRO1, I960BASE_INSN_SHRO1, I960BASE_SFMT_SHLO1 }, + { I960_INSN_SHRO2, I960BASE_INSN_SHRO2, I960BASE_SFMT_SHLO2 }, + { I960_INSN_SHRO3, I960BASE_INSN_SHRO3, I960BASE_SFMT_SHLO3 }, + { I960_INSN_SHLI, I960BASE_INSN_SHLI, I960BASE_SFMT_SHLO }, + { I960_INSN_SHLI1, I960BASE_INSN_SHLI1, I960BASE_SFMT_SHLO1 }, + { I960_INSN_SHLI2, I960BASE_INSN_SHLI2, I960BASE_SFMT_SHLO2 }, + { I960_INSN_SHLI3, I960BASE_INSN_SHLI3, I960BASE_SFMT_SHLO3 }, + { I960_INSN_SHRI, I960BASE_INSN_SHRI, I960BASE_SFMT_SHLO }, + { I960_INSN_SHRI1, I960BASE_INSN_SHRI1, I960BASE_SFMT_SHLO1 }, + { I960_INSN_SHRI2, I960BASE_INSN_SHRI2, I960BASE_SFMT_SHLO2 }, + { I960_INSN_SHRI3, I960BASE_INSN_SHRI3, I960BASE_SFMT_SHLO3 }, + { I960_INSN_EMUL, I960BASE_INSN_EMUL, I960BASE_SFMT_EMUL }, + { I960_INSN_EMUL1, I960BASE_INSN_EMUL1, I960BASE_SFMT_EMUL1 }, + { I960_INSN_EMUL2, I960BASE_INSN_EMUL2, I960BASE_SFMT_EMUL2 }, + { I960_INSN_EMUL3, I960BASE_INSN_EMUL3, I960BASE_SFMT_EMUL3 }, + { I960_INSN_MOV, I960BASE_INSN_MOV, I960BASE_SFMT_NOT }, + { I960_INSN_MOV1, I960BASE_INSN_MOV1, I960BASE_SFMT_NOT1 }, + { I960_INSN_MOVL, I960BASE_INSN_MOVL, I960BASE_SFMT_MOVL }, + { I960_INSN_MOVL1, I960BASE_INSN_MOVL1, I960BASE_SFMT_MOVL1 }, + { I960_INSN_MOVT, I960BASE_INSN_MOVT, I960BASE_SFMT_MOVT }, + { I960_INSN_MOVT1, I960BASE_INSN_MOVT1, I960BASE_SFMT_MOVT1 }, + { I960_INSN_MOVQ, I960BASE_INSN_MOVQ, I960BASE_SFMT_MOVQ }, + { I960_INSN_MOVQ1, I960BASE_INSN_MOVQ1, I960BASE_SFMT_MOVQ1 }, + { I960_INSN_MODPC, I960BASE_INSN_MODPC, I960BASE_SFMT_MODPC }, + { I960_INSN_MODAC, I960BASE_INSN_MODAC, I960BASE_SFMT_MODPC }, + { I960_INSN_LDA_OFFSET, I960BASE_INSN_LDA_OFFSET, I960BASE_SFMT_LDA_OFFSET }, + { I960_INSN_LDA_INDIRECT_OFFSET, I960BASE_INSN_LDA_INDIRECT_OFFSET, I960BASE_SFMT_LDA_INDIRECT_OFFSET }, + { I960_INSN_LDA_INDIRECT, I960BASE_INSN_LDA_INDIRECT, I960BASE_SFMT_LDA_INDIRECT }, + { I960_INSN_LDA_INDIRECT_INDEX, I960BASE_INSN_LDA_INDIRECT_INDEX, I960BASE_SFMT_LDA_INDIRECT_INDEX }, + { I960_INSN_LDA_DISP, I960BASE_INSN_LDA_DISP, I960BASE_SFMT_LDA_DISP }, + { I960_INSN_LDA_INDIRECT_DISP, I960BASE_INSN_LDA_INDIRECT_DISP, I960BASE_SFMT_LDA_INDIRECT_DISP }, + { I960_INSN_LDA_INDEX_DISP, I960BASE_INSN_LDA_INDEX_DISP, I960BASE_SFMT_LDA_INDEX_DISP }, + { I960_INSN_LDA_INDIRECT_INDEX_DISP, I960BASE_INSN_LDA_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDA_INDIRECT_INDEX_DISP }, + { I960_INSN_LD_OFFSET, I960BASE_INSN_LD_OFFSET, I960BASE_SFMT_LD_OFFSET }, + { I960_INSN_LD_INDIRECT_OFFSET, I960BASE_INSN_LD_INDIRECT_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET }, + { I960_INSN_LD_INDIRECT, I960BASE_INSN_LD_INDIRECT, I960BASE_SFMT_LD_INDIRECT }, + { I960_INSN_LD_INDIRECT_INDEX, I960BASE_INSN_LD_INDIRECT_INDEX, I960BASE_SFMT_LD_INDIRECT_INDEX }, + { I960_INSN_LD_DISP, I960BASE_INSN_LD_DISP, I960BASE_SFMT_LD_DISP }, + { I960_INSN_LD_INDIRECT_DISP, I960BASE_INSN_LD_INDIRECT_DISP, I960BASE_SFMT_LD_INDIRECT_DISP }, + { I960_INSN_LD_INDEX_DISP, I960BASE_INSN_LD_INDEX_DISP, I960BASE_SFMT_LD_INDEX_DISP }, + { I960_INSN_LD_INDIRECT_INDEX_DISP, I960BASE_INSN_LD_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP }, + { I960_INSN_LDOB_OFFSET, I960BASE_INSN_LDOB_OFFSET, I960BASE_SFMT_LD_OFFSET }, + { I960_INSN_LDOB_INDIRECT_OFFSET, I960BASE_INSN_LDOB_INDIRECT_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET }, + { I960_INSN_LDOB_INDIRECT, I960BASE_INSN_LDOB_INDIRECT, I960BASE_SFMT_LD_INDIRECT }, + { I960_INSN_LDOB_INDIRECT_INDEX, I960BASE_INSN_LDOB_INDIRECT_INDEX, I960BASE_SFMT_LD_INDIRECT_INDEX }, + { I960_INSN_LDOB_DISP, I960BASE_INSN_LDOB_DISP, I960BASE_SFMT_LD_DISP }, + { I960_INSN_LDOB_INDIRECT_DISP, I960BASE_INSN_LDOB_INDIRECT_DISP, I960BASE_SFMT_LD_INDIRECT_DISP }, + { I960_INSN_LDOB_INDEX_DISP, I960BASE_INSN_LDOB_INDEX_DISP, I960BASE_SFMT_LD_INDEX_DISP }, + { I960_INSN_LDOB_INDIRECT_INDEX_DISP, I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP }, + { I960_INSN_LDOS_OFFSET, I960BASE_INSN_LDOS_OFFSET, I960BASE_SFMT_LD_OFFSET }, + { I960_INSN_LDOS_INDIRECT_OFFSET, I960BASE_INSN_LDOS_INDIRECT_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET }, + { I960_INSN_LDOS_INDIRECT, I960BASE_INSN_LDOS_INDIRECT, I960BASE_SFMT_LD_INDIRECT }, + { I960_INSN_LDOS_INDIRECT_INDEX, I960BASE_INSN_LDOS_INDIRECT_INDEX, I960BASE_SFMT_LD_INDIRECT_INDEX }, + { I960_INSN_LDOS_DISP, I960BASE_INSN_LDOS_DISP, I960BASE_SFMT_LD_DISP }, + { I960_INSN_LDOS_INDIRECT_DISP, I960BASE_INSN_LDOS_INDIRECT_DISP, I960BASE_SFMT_LD_INDIRECT_DISP }, + { I960_INSN_LDOS_INDEX_DISP, I960BASE_INSN_LDOS_INDEX_DISP, I960BASE_SFMT_LD_INDEX_DISP }, + { I960_INSN_LDOS_INDIRECT_INDEX_DISP, I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP }, + { I960_INSN_LDIB_OFFSET, I960BASE_INSN_LDIB_OFFSET, I960BASE_SFMT_LD_OFFSET }, + { I960_INSN_LDIB_INDIRECT_OFFSET, I960BASE_INSN_LDIB_INDIRECT_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET }, + { I960_INSN_LDIB_INDIRECT, I960BASE_INSN_LDIB_INDIRECT, I960BASE_SFMT_LD_INDIRECT }, + { I960_INSN_LDIB_INDIRECT_INDEX, I960BASE_INSN_LDIB_INDIRECT_INDEX, I960BASE_SFMT_LD_INDIRECT_INDEX }, + { I960_INSN_LDIB_DISP, I960BASE_INSN_LDIB_DISP, I960BASE_SFMT_LD_DISP }, + { I960_INSN_LDIB_INDIRECT_DISP, I960BASE_INSN_LDIB_INDIRECT_DISP, I960BASE_SFMT_LD_INDIRECT_DISP }, + { I960_INSN_LDIB_INDEX_DISP, I960BASE_INSN_LDIB_INDEX_DISP, I960BASE_SFMT_LD_INDEX_DISP }, + { I960_INSN_LDIB_INDIRECT_INDEX_DISP, I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP }, + { I960_INSN_LDIS_OFFSET, I960BASE_INSN_LDIS_OFFSET, I960BASE_SFMT_LD_OFFSET }, + { I960_INSN_LDIS_INDIRECT_OFFSET, I960BASE_INSN_LDIS_INDIRECT_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET }, + { I960_INSN_LDIS_INDIRECT, I960BASE_INSN_LDIS_INDIRECT, I960BASE_SFMT_LD_INDIRECT }, + { I960_INSN_LDIS_INDIRECT_INDEX, I960BASE_INSN_LDIS_INDIRECT_INDEX, I960BASE_SFMT_LD_INDIRECT_INDEX }, + { I960_INSN_LDIS_DISP, I960BASE_INSN_LDIS_DISP, I960BASE_SFMT_LD_DISP }, + { I960_INSN_LDIS_INDIRECT_DISP, I960BASE_INSN_LDIS_INDIRECT_DISP, I960BASE_SFMT_LD_INDIRECT_DISP }, + { I960_INSN_LDIS_INDEX_DISP, I960BASE_INSN_LDIS_INDEX_DISP, I960BASE_SFMT_LD_INDEX_DISP }, + { I960_INSN_LDIS_INDIRECT_INDEX_DISP, I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP }, + { I960_INSN_LDL_OFFSET, I960BASE_INSN_LDL_OFFSET, I960BASE_SFMT_LDL_OFFSET }, + { I960_INSN_LDL_INDIRECT_OFFSET, I960BASE_INSN_LDL_INDIRECT_OFFSET, I960BASE_SFMT_LDL_INDIRECT_OFFSET }, + { I960_INSN_LDL_INDIRECT, I960BASE_INSN_LDL_INDIRECT, I960BASE_SFMT_LDL_INDIRECT }, + { I960_INSN_LDL_INDIRECT_INDEX, I960BASE_INSN_LDL_INDIRECT_INDEX, I960BASE_SFMT_LDL_INDIRECT_INDEX }, + { I960_INSN_LDL_DISP, I960BASE_INSN_LDL_DISP, I960BASE_SFMT_LDL_DISP }, + { I960_INSN_LDL_INDIRECT_DISP, I960BASE_INSN_LDL_INDIRECT_DISP, I960BASE_SFMT_LDL_INDIRECT_DISP }, + { I960_INSN_LDL_INDEX_DISP, I960BASE_INSN_LDL_INDEX_DISP, I960BASE_SFMT_LDL_INDEX_DISP }, + { I960_INSN_LDL_INDIRECT_INDEX_DISP, I960BASE_INSN_LDL_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDL_INDIRECT_INDEX_DISP }, + { I960_INSN_LDT_OFFSET, I960BASE_INSN_LDT_OFFSET, I960BASE_SFMT_LDT_OFFSET }, + { I960_INSN_LDT_INDIRECT_OFFSET, I960BASE_INSN_LDT_INDIRECT_OFFSET, I960BASE_SFMT_LDT_INDIRECT_OFFSET }, + { I960_INSN_LDT_INDIRECT, I960BASE_INSN_LDT_INDIRECT, I960BASE_SFMT_LDT_INDIRECT }, + { I960_INSN_LDT_INDIRECT_INDEX, I960BASE_INSN_LDT_INDIRECT_INDEX, I960BASE_SFMT_LDT_INDIRECT_INDEX }, + { I960_INSN_LDT_DISP, I960BASE_INSN_LDT_DISP, I960BASE_SFMT_LDT_DISP }, + { I960_INSN_LDT_INDIRECT_DISP, I960BASE_INSN_LDT_INDIRECT_DISP, I960BASE_SFMT_LDT_INDIRECT_DISP }, + { I960_INSN_LDT_INDEX_DISP, I960BASE_INSN_LDT_INDEX_DISP, I960BASE_SFMT_LDT_INDEX_DISP }, + { I960_INSN_LDT_INDIRECT_INDEX_DISP, I960BASE_INSN_LDT_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDT_INDIRECT_INDEX_DISP }, + { I960_INSN_LDQ_OFFSET, I960BASE_INSN_LDQ_OFFSET, I960BASE_SFMT_LDQ_OFFSET }, + { I960_INSN_LDQ_INDIRECT_OFFSET, I960BASE_INSN_LDQ_INDIRECT_OFFSET, I960BASE_SFMT_LDQ_INDIRECT_OFFSET }, + { I960_INSN_LDQ_INDIRECT, I960BASE_INSN_LDQ_INDIRECT, I960BASE_SFMT_LDQ_INDIRECT }, + { I960_INSN_LDQ_INDIRECT_INDEX, I960BASE_INSN_LDQ_INDIRECT_INDEX, I960BASE_SFMT_LDQ_INDIRECT_INDEX }, + { I960_INSN_LDQ_DISP, I960BASE_INSN_LDQ_DISP, I960BASE_SFMT_LDQ_DISP }, + { I960_INSN_LDQ_INDIRECT_DISP, I960BASE_INSN_LDQ_INDIRECT_DISP, I960BASE_SFMT_LDQ_INDIRECT_DISP }, + { I960_INSN_LDQ_INDEX_DISP, I960BASE_INSN_LDQ_INDEX_DISP, I960BASE_SFMT_LDQ_INDEX_DISP }, + { I960_INSN_LDQ_INDIRECT_INDEX_DISP, I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDQ_INDIRECT_INDEX_DISP }, + { I960_INSN_ST_OFFSET, I960BASE_INSN_ST_OFFSET, I960BASE_SFMT_ST_OFFSET }, + { I960_INSN_ST_INDIRECT_OFFSET, I960BASE_INSN_ST_INDIRECT_OFFSET, I960BASE_SFMT_ST_INDIRECT_OFFSET }, + { I960_INSN_ST_INDIRECT, I960BASE_INSN_ST_INDIRECT, I960BASE_SFMT_ST_INDIRECT }, + { I960_INSN_ST_INDIRECT_INDEX, I960BASE_INSN_ST_INDIRECT_INDEX, I960BASE_SFMT_ST_INDIRECT_INDEX }, + { I960_INSN_ST_DISP, I960BASE_INSN_ST_DISP, I960BASE_SFMT_ST_DISP }, + { I960_INSN_ST_INDIRECT_DISP, I960BASE_INSN_ST_INDIRECT_DISP, I960BASE_SFMT_ST_INDIRECT_DISP }, + { I960_INSN_ST_INDEX_DISP, I960BASE_INSN_ST_INDEX_DISP, I960BASE_SFMT_ST_INDEX_DISP }, + { I960_INSN_ST_INDIRECT_INDEX_DISP, I960BASE_INSN_ST_INDIRECT_INDEX_DISP, I960BASE_SFMT_ST_INDIRECT_INDEX_DISP }, + { I960_INSN_STOB_OFFSET, I960BASE_INSN_STOB_OFFSET, I960BASE_SFMT_ST_OFFSET }, + { I960_INSN_STOB_INDIRECT_OFFSET, I960BASE_INSN_STOB_INDIRECT_OFFSET, I960BASE_SFMT_ST_INDIRECT_OFFSET }, + { I960_INSN_STOB_INDIRECT, I960BASE_INSN_STOB_INDIRECT, I960BASE_SFMT_ST_INDIRECT }, + { I960_INSN_STOB_INDIRECT_INDEX, I960BASE_INSN_STOB_INDIRECT_INDEX, I960BASE_SFMT_ST_INDIRECT_INDEX }, + { I960_INSN_STOB_DISP, I960BASE_INSN_STOB_DISP, I960BASE_SFMT_ST_DISP }, + { I960_INSN_STOB_INDIRECT_DISP, I960BASE_INSN_STOB_INDIRECT_DISP, I960BASE_SFMT_ST_INDIRECT_DISP }, + { I960_INSN_STOB_INDEX_DISP, I960BASE_INSN_STOB_INDEX_DISP, I960BASE_SFMT_ST_INDEX_DISP }, + { I960_INSN_STOB_INDIRECT_INDEX_DISP, I960BASE_INSN_STOB_INDIRECT_INDEX_DISP, I960BASE_SFMT_ST_INDIRECT_INDEX_DISP }, + { I960_INSN_STOS_OFFSET, I960BASE_INSN_STOS_OFFSET, I960BASE_SFMT_ST_OFFSET }, + { I960_INSN_STOS_INDIRECT_OFFSET, I960BASE_INSN_STOS_INDIRECT_OFFSET, I960BASE_SFMT_ST_INDIRECT_OFFSET }, + { I960_INSN_STOS_INDIRECT, I960BASE_INSN_STOS_INDIRECT, I960BASE_SFMT_ST_INDIRECT }, + { I960_INSN_STOS_INDIRECT_INDEX, I960BASE_INSN_STOS_INDIRECT_INDEX, I960BASE_SFMT_ST_INDIRECT_INDEX }, + { I960_INSN_STOS_DISP, I960BASE_INSN_STOS_DISP, I960BASE_SFMT_ST_DISP }, + { I960_INSN_STOS_INDIRECT_DISP, I960BASE_INSN_STOS_INDIRECT_DISP, I960BASE_SFMT_ST_INDIRECT_DISP }, + { I960_INSN_STOS_INDEX_DISP, I960BASE_INSN_STOS_INDEX_DISP, I960BASE_SFMT_ST_INDEX_DISP }, + { I960_INSN_STOS_INDIRECT_INDEX_DISP, I960BASE_INSN_STOS_INDIRECT_INDEX_DISP, I960BASE_SFMT_ST_INDIRECT_INDEX_DISP }, + { I960_INSN_STL_OFFSET, I960BASE_INSN_STL_OFFSET, I960BASE_SFMT_STL_OFFSET }, + { I960_INSN_STL_INDIRECT_OFFSET, I960BASE_INSN_STL_INDIRECT_OFFSET, I960BASE_SFMT_STL_INDIRECT_OFFSET }, + { I960_INSN_STL_INDIRECT, I960BASE_INSN_STL_INDIRECT, I960BASE_SFMT_STL_INDIRECT }, + { I960_INSN_STL_INDIRECT_INDEX, I960BASE_INSN_STL_INDIRECT_INDEX, I960BASE_SFMT_STL_INDIRECT_INDEX }, + { I960_INSN_STL_DISP, I960BASE_INSN_STL_DISP, I960BASE_SFMT_STL_DISP }, + { I960_INSN_STL_INDIRECT_DISP, I960BASE_INSN_STL_INDIRECT_DISP, I960BASE_SFMT_STL_INDIRECT_DISP }, + { I960_INSN_STL_INDEX_DISP, I960BASE_INSN_STL_INDEX_DISP, I960BASE_SFMT_STL_INDEX_DISP }, + { I960_INSN_STL_INDIRECT_INDEX_DISP, I960BASE_INSN_STL_INDIRECT_INDEX_DISP, I960BASE_SFMT_STL_INDIRECT_INDEX_DISP }, + { I960_INSN_STT_OFFSET, I960BASE_INSN_STT_OFFSET, I960BASE_SFMT_STT_OFFSET }, + { I960_INSN_STT_INDIRECT_OFFSET, I960BASE_INSN_STT_INDIRECT_OFFSET, I960BASE_SFMT_STT_INDIRECT_OFFSET }, + { I960_INSN_STT_INDIRECT, I960BASE_INSN_STT_INDIRECT, I960BASE_SFMT_STT_INDIRECT }, + { I960_INSN_STT_INDIRECT_INDEX, I960BASE_INSN_STT_INDIRECT_INDEX, I960BASE_SFMT_STT_INDIRECT_INDEX }, + { I960_INSN_STT_DISP, I960BASE_INSN_STT_DISP, I960BASE_SFMT_STT_DISP }, + { I960_INSN_STT_INDIRECT_DISP, I960BASE_INSN_STT_INDIRECT_DISP, I960BASE_SFMT_STT_INDIRECT_DISP }, + { I960_INSN_STT_INDEX_DISP, I960BASE_INSN_STT_INDEX_DISP, I960BASE_SFMT_STT_INDEX_DISP }, + { I960_INSN_STT_INDIRECT_INDEX_DISP, I960BASE_INSN_STT_INDIRECT_INDEX_DISP, I960BASE_SFMT_STT_INDIRECT_INDEX_DISP }, + { I960_INSN_STQ_OFFSET, I960BASE_INSN_STQ_OFFSET, I960BASE_SFMT_STQ_OFFSET }, + { I960_INSN_STQ_INDIRECT_OFFSET, I960BASE_INSN_STQ_INDIRECT_OFFSET, I960BASE_SFMT_STQ_INDIRECT_OFFSET }, + { I960_INSN_STQ_INDIRECT, I960BASE_INSN_STQ_INDIRECT, I960BASE_SFMT_STQ_INDIRECT }, + { I960_INSN_STQ_INDIRECT_INDEX, I960BASE_INSN_STQ_INDIRECT_INDEX, I960BASE_SFMT_STQ_INDIRECT_INDEX }, + { I960_INSN_STQ_DISP, I960BASE_INSN_STQ_DISP, I960BASE_SFMT_STQ_DISP }, + { I960_INSN_STQ_INDIRECT_DISP, I960BASE_INSN_STQ_INDIRECT_DISP, I960BASE_SFMT_STQ_INDIRECT_DISP }, + { I960_INSN_STQ_INDEX_DISP, I960BASE_INSN_STQ_INDEX_DISP, I960BASE_SFMT_STQ_INDEX_DISP }, + { I960_INSN_STQ_INDIRECT_INDEX_DISP, I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_STQ_INDIRECT_INDEX_DISP }, + { I960_INSN_CMPOBE_REG, I960BASE_INSN_CMPOBE_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPOBE_LIT, I960BASE_INSN_CMPOBE_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPOBNE_REG, I960BASE_INSN_CMPOBNE_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPOBNE_LIT, I960BASE_INSN_CMPOBNE_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPOBL_REG, I960BASE_INSN_CMPOBL_REG, I960BASE_SFMT_CMPOBL_REG }, + { I960_INSN_CMPOBL_LIT, I960BASE_INSN_CMPOBL_LIT, I960BASE_SFMT_CMPOBL_LIT }, + { I960_INSN_CMPOBLE_REG, I960BASE_INSN_CMPOBLE_REG, I960BASE_SFMT_CMPOBL_REG }, + { I960_INSN_CMPOBLE_LIT, I960BASE_INSN_CMPOBLE_LIT, I960BASE_SFMT_CMPOBL_LIT }, + { I960_INSN_CMPOBG_REG, I960BASE_INSN_CMPOBG_REG, I960BASE_SFMT_CMPOBL_REG }, + { I960_INSN_CMPOBG_LIT, I960BASE_INSN_CMPOBG_LIT, I960BASE_SFMT_CMPOBL_LIT }, + { I960_INSN_CMPOBGE_REG, I960BASE_INSN_CMPOBGE_REG, I960BASE_SFMT_CMPOBL_REG }, + { I960_INSN_CMPOBGE_LIT, I960BASE_INSN_CMPOBGE_LIT, I960BASE_SFMT_CMPOBL_LIT }, + { I960_INSN_CMPIBE_REG, I960BASE_INSN_CMPIBE_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPIBE_LIT, I960BASE_INSN_CMPIBE_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPIBNE_REG, I960BASE_INSN_CMPIBNE_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPIBNE_LIT, I960BASE_INSN_CMPIBNE_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPIBL_REG, I960BASE_INSN_CMPIBL_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPIBL_LIT, I960BASE_INSN_CMPIBL_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPIBLE_REG, I960BASE_INSN_CMPIBLE_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPIBLE_LIT, I960BASE_INSN_CMPIBLE_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPIBG_REG, I960BASE_INSN_CMPIBG_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPIBG_LIT, I960BASE_INSN_CMPIBG_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_CMPIBGE_REG, I960BASE_INSN_CMPIBGE_REG, I960BASE_SFMT_CMPOBE_REG }, + { I960_INSN_CMPIBGE_LIT, I960BASE_INSN_CMPIBGE_LIT, I960BASE_SFMT_CMPOBE_LIT }, + { I960_INSN_BBC_REG, I960BASE_INSN_BBC_REG, I960BASE_SFMT_BBC_REG }, + { I960_INSN_BBC_LIT, I960BASE_INSN_BBC_LIT, I960BASE_SFMT_BBC_LIT }, + { I960_INSN_BBS_REG, I960BASE_INSN_BBS_REG, I960BASE_SFMT_BBC_REG }, + { I960_INSN_BBS_LIT, I960BASE_INSN_BBS_LIT, I960BASE_SFMT_BBC_LIT }, + { I960_INSN_CMPI, I960BASE_INSN_CMPI, I960BASE_SFMT_CMPI }, + { I960_INSN_CMPI1, I960BASE_INSN_CMPI1, I960BASE_SFMT_CMPI1 }, + { I960_INSN_CMPI2, I960BASE_INSN_CMPI2, I960BASE_SFMT_CMPI2 }, + { I960_INSN_CMPI3, I960BASE_INSN_CMPI3, I960BASE_SFMT_CMPI3 }, + { I960_INSN_CMPO, I960BASE_INSN_CMPO, I960BASE_SFMT_CMPO }, + { I960_INSN_CMPO1, I960BASE_INSN_CMPO1, I960BASE_SFMT_CMPO1 }, + { I960_INSN_CMPO2, I960BASE_INSN_CMPO2, I960BASE_SFMT_CMPO2 }, + { I960_INSN_CMPO3, I960BASE_INSN_CMPO3, I960BASE_SFMT_CMPO3 }, + { I960_INSN_TESTNO_REG, I960BASE_INSN_TESTNO_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTG_REG, I960BASE_INSN_TESTG_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTE_REG, I960BASE_INSN_TESTE_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTGE_REG, I960BASE_INSN_TESTGE_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTL_REG, I960BASE_INSN_TESTL_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTNE_REG, I960BASE_INSN_TESTNE_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTLE_REG, I960BASE_INSN_TESTLE_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_TESTO_REG, I960BASE_INSN_TESTO_REG, I960BASE_SFMT_TESTNO_REG }, + { I960_INSN_BNO, I960BASE_INSN_BNO, I960BASE_SFMT_BNO }, + { I960_INSN_BG, I960BASE_INSN_BG, I960BASE_SFMT_BNO }, + { I960_INSN_BE, I960BASE_INSN_BE, I960BASE_SFMT_BNO }, + { I960_INSN_BGE, I960BASE_INSN_BGE, I960BASE_SFMT_BNO }, + { I960_INSN_BL, I960BASE_INSN_BL, I960BASE_SFMT_BNO }, + { I960_INSN_BNE, I960BASE_INSN_BNE, I960BASE_SFMT_BNO }, + { I960_INSN_BLE, I960BASE_INSN_BLE, I960BASE_SFMT_BNO }, + { I960_INSN_BO, I960BASE_INSN_BO, I960BASE_SFMT_BNO }, + { I960_INSN_B, I960BASE_INSN_B, I960BASE_SFMT_B }, + { I960_INSN_BX_INDIRECT_OFFSET, I960BASE_INSN_BX_INDIRECT_OFFSET, I960BASE_SFMT_BX_INDIRECT_OFFSET }, + { I960_INSN_BX_INDIRECT, I960BASE_INSN_BX_INDIRECT, I960BASE_SFMT_BX_INDIRECT }, + { I960_INSN_BX_INDIRECT_INDEX, I960BASE_INSN_BX_INDIRECT_INDEX, I960BASE_SFMT_BX_INDIRECT_INDEX }, + { I960_INSN_BX_DISP, I960BASE_INSN_BX_DISP, I960BASE_SFMT_BX_DISP }, + { I960_INSN_BX_INDIRECT_DISP, I960BASE_INSN_BX_INDIRECT_DISP, I960BASE_SFMT_BX_INDIRECT_DISP }, + { I960_INSN_CALLX_DISP, I960BASE_INSN_CALLX_DISP, I960BASE_SFMT_CALLX_DISP }, + { I960_INSN_CALLX_INDIRECT, I960BASE_INSN_CALLX_INDIRECT, I960BASE_SFMT_CALLX_INDIRECT }, + { I960_INSN_CALLX_INDIRECT_OFFSET, I960BASE_INSN_CALLX_INDIRECT_OFFSET, I960BASE_SFMT_CALLX_INDIRECT_OFFSET }, + { I960_INSN_RET, I960BASE_INSN_RET, I960BASE_SFMT_RET }, + { I960_INSN_CALLS, I960BASE_INSN_CALLS, I960BASE_SFMT_CALLS }, + { I960_INSN_FMARK, I960BASE_INSN_FMARK, I960BASE_SFMT_FMARK }, + { I960_INSN_FLUSHREG, I960BASE_INSN_FLUSHREG, I960BASE_SFMT_FLUSHREG }, }; -static const struct insn_sem i960base_insn_sem_invalid = -{ - VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) +static const struct insn_sem i960base_insn_sem_invalid = { + VIRTUAL_INSN_X_INVALID, I960BASE_INSN_X_INVALID, I960BASE_SFMT_EMPTY }; -#undef FMT -#undef FULL -#undef FAST -#undef IDX -#undef TYPE - /* Initialize an IDESC from the compile-time computable parts. */ static INLINE void @@ -381,6 +351,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; id->num = t->index; + id->sfmt = t->sfmt; if ((int) t->type <= 0) id->idata = & cgen_virtual_insn_table[- (int) t->type]; else @@ -388,12 +359,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) id->attrs = CGEN_INSN_ATTRS (id->idata); /* Oh my god, a magic number. */ id->length = CGEN_INSN_BITSIZE (id->idata) / 8; -#if ! WITH_SEM_SWITCH_FULL - id->sem_full = t->sem_full; -#endif -#if WITH_FAST && ! WITH_SEM_SWITCH_FAST - id->sem_fast = t->sem_fast; -#endif + #if WITH_PROFILE_MODEL_P id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; { @@ -401,6 +367,8 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) SIM_ASSERT (t->index == id->timing->num); } #endif + + /* Semantic pointers are initialized elsewhere. */ } /* Initialize the instruction descriptor table. */ @@ -448,32 +416,32 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 24) & (255 << 0))); switch (val) { - case 8 : itype = I960BASE_INSN_B; goto extract_fmt_b; - case 10 : itype = I960BASE_INSN_RET; goto extract_fmt_ret; - case 16 : itype = I960BASE_INSN_BNO; goto extract_fmt_bno; - case 17 : itype = I960BASE_INSN_BG; goto extract_fmt_bno; - case 18 : itype = I960BASE_INSN_BE; goto extract_fmt_bno; - case 19 : itype = I960BASE_INSN_BGE; goto extract_fmt_bno; - case 20 : itype = I960BASE_INSN_BL; goto extract_fmt_bno; - case 21 : itype = I960BASE_INSN_BNE; goto extract_fmt_bno; - case 22 : itype = I960BASE_INSN_BLE; goto extract_fmt_bno; - case 23 : itype = I960BASE_INSN_BO; goto extract_fmt_bno; - case 32 : itype = I960BASE_INSN_TESTNO_REG; goto extract_fmt_testno_reg; - case 33 : itype = I960BASE_INSN_TESTG_REG; goto extract_fmt_testno_reg; - case 34 : itype = I960BASE_INSN_TESTE_REG; goto extract_fmt_testno_reg; - case 35 : itype = I960BASE_INSN_TESTGE_REG; goto extract_fmt_testno_reg; - case 36 : itype = I960BASE_INSN_TESTL_REG; goto extract_fmt_testno_reg; - case 37 : itype = I960BASE_INSN_TESTNE_REG; goto extract_fmt_testno_reg; - case 38 : itype = I960BASE_INSN_TESTLE_REG; goto extract_fmt_testno_reg; - case 39 : itype = I960BASE_INSN_TESTO_REG; goto extract_fmt_testno_reg; + case 8 : itype = I960BASE_INSN_B; goto extract_sfmt_b; + case 10 : itype = I960BASE_INSN_RET; goto extract_sfmt_ret; + case 16 : itype = I960BASE_INSN_BNO; goto extract_sfmt_bno; + case 17 : itype = I960BASE_INSN_BG; goto extract_sfmt_bno; + case 18 : itype = I960BASE_INSN_BE; goto extract_sfmt_bno; + case 19 : itype = I960BASE_INSN_BGE; goto extract_sfmt_bno; + case 20 : itype = I960BASE_INSN_BL; goto extract_sfmt_bno; + case 21 : itype = I960BASE_INSN_BNE; goto extract_sfmt_bno; + case 22 : itype = I960BASE_INSN_BLE; goto extract_sfmt_bno; + case 23 : itype = I960BASE_INSN_BO; goto extract_sfmt_bno; + case 32 : itype = I960BASE_INSN_TESTNO_REG; goto extract_sfmt_testno_reg; + case 33 : itype = I960BASE_INSN_TESTG_REG; goto extract_sfmt_testno_reg; + case 34 : itype = I960BASE_INSN_TESTE_REG; goto extract_sfmt_testno_reg; + case 35 : itype = I960BASE_INSN_TESTGE_REG; goto extract_sfmt_testno_reg; + case 36 : itype = I960BASE_INSN_TESTL_REG; goto extract_sfmt_testno_reg; + case 37 : itype = I960BASE_INSN_TESTNE_REG; goto extract_sfmt_testno_reg; + case 38 : itype = I960BASE_INSN_TESTLE_REG; goto extract_sfmt_testno_reg; + case 39 : itype = I960BASE_INSN_TESTO_REG; goto extract_sfmt_testno_reg; case 48 : { unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_BBC_REG; goto extract_fmt_bbc_reg; - case 4 : itype = I960BASE_INSN_BBC_LIT; goto extract_fmt_bbc_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_BBC_REG; goto extract_sfmt_bbc_reg; + case 4 : itype = I960BASE_INSN_BBC_LIT; goto extract_sfmt_bbc_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 49 : @@ -481,9 +449,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPOBG_REG; goto extract_fmt_cmpobl_reg; - case 4 : itype = I960BASE_INSN_CMPOBG_LIT; goto extract_fmt_cmpobl_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPOBG_REG; goto extract_sfmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBG_LIT; goto extract_sfmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 50 : @@ -491,9 +459,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPOBE_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPOBE_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPOBE_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPOBE_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 51 : @@ -501,9 +469,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPOBGE_REG; goto extract_fmt_cmpobl_reg; - case 4 : itype = I960BASE_INSN_CMPOBGE_LIT; goto extract_fmt_cmpobl_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPOBGE_REG; goto extract_sfmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBGE_LIT; goto extract_sfmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 52 : @@ -511,9 +479,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPOBL_REG; goto extract_fmt_cmpobl_reg; - case 4 : itype = I960BASE_INSN_CMPOBL_LIT; goto extract_fmt_cmpobl_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPOBL_REG; goto extract_sfmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBL_LIT; goto extract_sfmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 53 : @@ -521,9 +489,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPOBNE_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPOBNE_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPOBNE_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPOBNE_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 54 : @@ -531,9 +499,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPOBLE_REG; goto extract_fmt_cmpobl_reg; - case 4 : itype = I960BASE_INSN_CMPOBLE_LIT; goto extract_fmt_cmpobl_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPOBLE_REG; goto extract_sfmt_cmpobl_reg; + case 4 : itype = I960BASE_INSN_CMPOBLE_LIT; goto extract_sfmt_cmpobl_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 55 : @@ -541,9 +509,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_BBS_REG; goto extract_fmt_bbc_reg; - case 4 : itype = I960BASE_INSN_BBS_LIT; goto extract_fmt_bbc_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_BBS_REG; goto extract_sfmt_bbc_reg; + case 4 : itype = I960BASE_INSN_BBS_LIT; goto extract_sfmt_bbc_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 57 : @@ -551,9 +519,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPIBG_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPIBG_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPIBG_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBG_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 58 : @@ -561,9 +529,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPIBE_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPIBE_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPIBE_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBE_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 59 : @@ -571,9 +539,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPIBGE_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPIBGE_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPIBGE_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBGE_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 60 : @@ -581,9 +549,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPIBL_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPIBL_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPIBL_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBL_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 61 : @@ -591,9 +559,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPIBNE_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPIBNE_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPIBNE_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBNE_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 62 : @@ -601,9 +569,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPIBLE_REG; goto extract_fmt_cmpobe_reg; - case 4 : itype = I960BASE_INSN_CMPIBLE_LIT; goto extract_fmt_cmpobe_lit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPIBLE_REG; goto extract_sfmt_cmpobe_reg; + case 4 : itype = I960BASE_INSN_CMPIBLE_LIT; goto extract_sfmt_cmpobe_lit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 88 : @@ -616,14 +584,14 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOTBIT; goto extract_fmt_notbit; - case 2 : itype = I960BASE_INSN_AND; goto extract_fmt_mulo; - case 4 : itype = I960BASE_INSN_ANDNOT; goto extract_fmt_mulo; - case 6 : itype = I960BASE_INSN_SETBIT; goto extract_fmt_notbit; - case 8 : itype = I960BASE_INSN_NOTAND; goto extract_fmt_mulo; - case 12 : itype = I960BASE_INSN_XOR; goto extract_fmt_mulo; - case 14 : itype = I960BASE_INSN_OR; goto extract_fmt_mulo; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOTBIT; goto extract_sfmt_notbit; + case 2 : itype = I960BASE_INSN_AND; goto extract_sfmt_mulo; + case 4 : itype = I960BASE_INSN_ANDNOT; goto extract_sfmt_mulo; + case 6 : itype = I960BASE_INSN_SETBIT; goto extract_sfmt_notbit; + case 8 : itype = I960BASE_INSN_NOTAND; goto extract_sfmt_mulo; + case 12 : itype = I960BASE_INSN_XOR; goto extract_sfmt_mulo; + case 14 : itype = I960BASE_INSN_OR; goto extract_sfmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 1 : @@ -631,12 +599,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOR; goto extract_fmt_mulo; - case 2 : itype = I960BASE_INSN_XNOR; goto extract_fmt_mulo; - case 4 : itype = I960BASE_INSN_NOT; goto extract_fmt_not; - case 6 : itype = I960BASE_INSN_ORNOT; goto extract_fmt_mulo; - case 8 : itype = I960BASE_INSN_CLRBIT; goto extract_fmt_notbit; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOR; goto extract_sfmt_mulo; + case 2 : itype = I960BASE_INSN_XNOR; goto extract_sfmt_mulo; + case 4 : itype = I960BASE_INSN_NOT; goto extract_sfmt_not; + case 6 : itype = I960BASE_INSN_ORNOT; goto extract_sfmt_mulo; + case 8 : itype = I960BASE_INSN_CLRBIT; goto extract_sfmt_notbit; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 2 : @@ -644,14 +612,14 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOTBIT1; goto extract_fmt_notbit1; - case 2 : itype = I960BASE_INSN_AND1; goto extract_fmt_mulo1; - case 4 : itype = I960BASE_INSN_ANDNOT1; goto extract_fmt_mulo1; - case 6 : itype = I960BASE_INSN_SETBIT1; goto extract_fmt_notbit1; - case 8 : itype = I960BASE_INSN_NOTAND1; goto extract_fmt_mulo1; - case 12 : itype = I960BASE_INSN_XOR1; goto extract_fmt_mulo1; - case 14 : itype = I960BASE_INSN_OR1; goto extract_fmt_mulo1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOTBIT1; goto extract_sfmt_notbit1; + case 2 : itype = I960BASE_INSN_AND1; goto extract_sfmt_mulo1; + case 4 : itype = I960BASE_INSN_ANDNOT1; goto extract_sfmt_mulo1; + case 6 : itype = I960BASE_INSN_SETBIT1; goto extract_sfmt_notbit1; + case 8 : itype = I960BASE_INSN_NOTAND1; goto extract_sfmt_mulo1; + case 12 : itype = I960BASE_INSN_XOR1; goto extract_sfmt_mulo1; + case 14 : itype = I960BASE_INSN_OR1; goto extract_sfmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 3 : @@ -659,12 +627,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOR1; goto extract_fmt_mulo1; - case 2 : itype = I960BASE_INSN_XNOR1; goto extract_fmt_mulo1; - case 4 : itype = I960BASE_INSN_NOT1; goto extract_fmt_not1; - case 6 : itype = I960BASE_INSN_ORNOT1; goto extract_fmt_mulo1; - case 8 : itype = I960BASE_INSN_CLRBIT1; goto extract_fmt_notbit1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOR1; goto extract_sfmt_mulo1; + case 2 : itype = I960BASE_INSN_XNOR1; goto extract_sfmt_mulo1; + case 4 : itype = I960BASE_INSN_NOT1; goto extract_sfmt_not1; + case 6 : itype = I960BASE_INSN_ORNOT1; goto extract_sfmt_mulo1; + case 8 : itype = I960BASE_INSN_CLRBIT1; goto extract_sfmt_notbit1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 4 : @@ -672,14 +640,14 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOTBIT2; goto extract_fmt_notbit2; - case 2 : itype = I960BASE_INSN_AND2; goto extract_fmt_mulo2; - case 4 : itype = I960BASE_INSN_ANDNOT2; goto extract_fmt_mulo2; - case 6 : itype = I960BASE_INSN_SETBIT2; goto extract_fmt_notbit2; - case 8 : itype = I960BASE_INSN_NOTAND2; goto extract_fmt_mulo2; - case 12 : itype = I960BASE_INSN_XOR2; goto extract_fmt_mulo2; - case 14 : itype = I960BASE_INSN_OR2; goto extract_fmt_mulo2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOTBIT2; goto extract_sfmt_notbit2; + case 2 : itype = I960BASE_INSN_AND2; goto extract_sfmt_mulo2; + case 4 : itype = I960BASE_INSN_ANDNOT2; goto extract_sfmt_mulo2; + case 6 : itype = I960BASE_INSN_SETBIT2; goto extract_sfmt_notbit2; + case 8 : itype = I960BASE_INSN_NOTAND2; goto extract_sfmt_mulo2; + case 12 : itype = I960BASE_INSN_XOR2; goto extract_sfmt_mulo2; + case 14 : itype = I960BASE_INSN_OR2; goto extract_sfmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 5 : @@ -687,12 +655,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOR2; goto extract_fmt_mulo2; - case 2 : itype = I960BASE_INSN_XNOR2; goto extract_fmt_mulo2; - case 4 : itype = I960BASE_INSN_NOT2; goto extract_fmt_not2; - case 6 : itype = I960BASE_INSN_ORNOT2; goto extract_fmt_mulo2; - case 8 : itype = I960BASE_INSN_CLRBIT2; goto extract_fmt_notbit2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOR2; goto extract_sfmt_mulo2; + case 2 : itype = I960BASE_INSN_XNOR2; goto extract_sfmt_mulo2; + case 4 : itype = I960BASE_INSN_NOT2; goto extract_sfmt_not; + case 6 : itype = I960BASE_INSN_ORNOT2; goto extract_sfmt_mulo2; + case 8 : itype = I960BASE_INSN_CLRBIT2; goto extract_sfmt_notbit2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 6 : @@ -700,14 +668,14 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOTBIT3; goto extract_fmt_notbit3; - case 2 : itype = I960BASE_INSN_AND3; goto extract_fmt_mulo3; - case 4 : itype = I960BASE_INSN_ANDNOT3; goto extract_fmt_mulo3; - case 6 : itype = I960BASE_INSN_SETBIT3; goto extract_fmt_notbit3; - case 8 : itype = I960BASE_INSN_NOTAND3; goto extract_fmt_mulo3; - case 12 : itype = I960BASE_INSN_XOR3; goto extract_fmt_mulo3; - case 14 : itype = I960BASE_INSN_OR3; goto extract_fmt_mulo3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOTBIT3; goto extract_sfmt_notbit3; + case 2 : itype = I960BASE_INSN_AND3; goto extract_sfmt_mulo3; + case 4 : itype = I960BASE_INSN_ANDNOT3; goto extract_sfmt_mulo3; + case 6 : itype = I960BASE_INSN_SETBIT3; goto extract_sfmt_notbit3; + case 8 : itype = I960BASE_INSN_NOTAND3; goto extract_sfmt_mulo3; + case 12 : itype = I960BASE_INSN_XOR3; goto extract_sfmt_mulo3; + case 14 : itype = I960BASE_INSN_OR3; goto extract_sfmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 7 : @@ -715,15 +683,15 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_NOR3; goto extract_fmt_mulo3; - case 2 : itype = I960BASE_INSN_XNOR3; goto extract_fmt_mulo3; - case 4 : itype = I960BASE_INSN_NOT3; goto extract_fmt_not3; - case 6 : itype = I960BASE_INSN_ORNOT3; goto extract_fmt_mulo3; - case 8 : itype = I960BASE_INSN_CLRBIT3; goto extract_fmt_notbit3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_NOR3; goto extract_sfmt_mulo3; + case 2 : itype = I960BASE_INSN_XNOR3; goto extract_sfmt_mulo3; + case 4 : itype = I960BASE_INSN_NOT3; goto extract_sfmt_not1; + case 6 : itype = I960BASE_INSN_ORNOT3; goto extract_sfmt_mulo3; + case 8 : itype = I960BASE_INSN_CLRBIT3; goto extract_sfmt_notbit3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 89 : @@ -736,9 +704,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_ADDO; goto extract_fmt_mulo; - case 4 : itype = I960BASE_INSN_SUBO; goto extract_fmt_mulo; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_ADDO; goto extract_sfmt_mulo; + case 4 : itype = I960BASE_INSN_SUBO; goto extract_sfmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 1 : @@ -746,11 +714,11 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_SHRO; goto extract_fmt_shlo; - case 6 : itype = I960BASE_INSN_SHRI; goto extract_fmt_shlo; - case 8 : itype = I960BASE_INSN_SHLO; goto extract_fmt_shlo; - case 12 : itype = I960BASE_INSN_SHLI; goto extract_fmt_shlo; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_SHRO; goto extract_sfmt_shlo; + case 6 : itype = I960BASE_INSN_SHRI; goto extract_sfmt_shlo; + case 8 : itype = I960BASE_INSN_SHLO; goto extract_sfmt_shlo; + case 12 : itype = I960BASE_INSN_SHLI; goto extract_sfmt_shlo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 2 : @@ -758,9 +726,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_ADDO1; goto extract_fmt_mulo1; - case 4 : itype = I960BASE_INSN_SUBO1; goto extract_fmt_mulo1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_ADDO1; goto extract_sfmt_mulo1; + case 4 : itype = I960BASE_INSN_SUBO1; goto extract_sfmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 3 : @@ -768,11 +736,11 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_SHRO1; goto extract_fmt_shlo1; - case 6 : itype = I960BASE_INSN_SHRI1; goto extract_fmt_shlo1; - case 8 : itype = I960BASE_INSN_SHLO1; goto extract_fmt_shlo1; - case 12 : itype = I960BASE_INSN_SHLI1; goto extract_fmt_shlo1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_SHRO1; goto extract_sfmt_shlo1; + case 6 : itype = I960BASE_INSN_SHRI1; goto extract_sfmt_shlo1; + case 8 : itype = I960BASE_INSN_SHLO1; goto extract_sfmt_shlo1; + case 12 : itype = I960BASE_INSN_SHLI1; goto extract_sfmt_shlo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 4 : @@ -780,9 +748,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_ADDO2; goto extract_fmt_mulo2; - case 4 : itype = I960BASE_INSN_SUBO2; goto extract_fmt_mulo2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_ADDO2; goto extract_sfmt_mulo2; + case 4 : itype = I960BASE_INSN_SUBO2; goto extract_sfmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 5 : @@ -790,11 +758,11 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_SHRO2; goto extract_fmt_shlo2; - case 6 : itype = I960BASE_INSN_SHRI2; goto extract_fmt_shlo2; - case 8 : itype = I960BASE_INSN_SHLO2; goto extract_fmt_shlo2; - case 12 : itype = I960BASE_INSN_SHLI2; goto extract_fmt_shlo2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_SHRO2; goto extract_sfmt_shlo2; + case 6 : itype = I960BASE_INSN_SHRI2; goto extract_sfmt_shlo2; + case 8 : itype = I960BASE_INSN_SHLO2; goto extract_sfmt_shlo2; + case 12 : itype = I960BASE_INSN_SHLI2; goto extract_sfmt_shlo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 6 : @@ -802,9 +770,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_ADDO3; goto extract_fmt_mulo3; - case 4 : itype = I960BASE_INSN_SUBO3; goto extract_fmt_mulo3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_ADDO3; goto extract_sfmt_mulo3; + case 4 : itype = I960BASE_INSN_SUBO3; goto extract_sfmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 7 : @@ -812,14 +780,14 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_SHRO3; goto extract_fmt_shlo3; - case 6 : itype = I960BASE_INSN_SHRI3; goto extract_fmt_shlo3; - case 8 : itype = I960BASE_INSN_SHLO3; goto extract_fmt_shlo3; - case 12 : itype = I960BASE_INSN_SHLI3; goto extract_fmt_shlo3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_SHRO3; goto extract_sfmt_shlo3; + case 6 : itype = I960BASE_INSN_SHRI3; goto extract_sfmt_shlo3; + case 8 : itype = I960BASE_INSN_SHLO3; goto extract_sfmt_shlo3; + case 12 : itype = I960BASE_INSN_SHLI3; goto extract_sfmt_shlo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 90 : @@ -832,9 +800,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPO; goto extract_fmt_cmpo; - case 2 : itype = I960BASE_INSN_CMPI; goto extract_fmt_cmpi; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPO; goto extract_sfmt_cmpo; + case 2 : itype = I960BASE_INSN_CMPI; goto extract_sfmt_cmpi; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 10 : @@ -842,9 +810,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPO1; goto extract_fmt_cmpo1; - case 2 : itype = I960BASE_INSN_CMPI1; goto extract_fmt_cmpi1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPO1; goto extract_sfmt_cmpo1; + case 2 : itype = I960BASE_INSN_CMPI1; goto extract_sfmt_cmpi1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 12 : @@ -852,9 +820,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPO2; goto extract_fmt_cmpo2; - case 2 : itype = I960BASE_INSN_CMPI2; goto extract_fmt_cmpi2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPO2; goto extract_sfmt_cmpo2; + case 2 : itype = I960BASE_INSN_CMPI2; goto extract_sfmt_cmpi2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 14 : @@ -862,12 +830,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_CMPO3; goto extract_fmt_cmpo3; - case 2 : itype = I960BASE_INSN_CMPI3; goto extract_fmt_cmpi3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_CMPO3; goto extract_sfmt_cmpo3; + case 2 : itype = I960BASE_INSN_CMPI3; goto extract_sfmt_cmpi3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 92 : @@ -875,9 +843,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 5 : itype = I960BASE_INSN_MOV; goto extract_fmt_not2; - case 7 : itype = I960BASE_INSN_MOV1; goto extract_fmt_not3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 5 : itype = I960BASE_INSN_MOV; goto extract_sfmt_not; + case 7 : itype = I960BASE_INSN_MOV1; goto extract_sfmt_not1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 93 : @@ -885,9 +853,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 5 : itype = I960BASE_INSN_MOVL; goto extract_fmt_movl; - case 7 : itype = I960BASE_INSN_MOVL1; goto extract_fmt_movl1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 5 : itype = I960BASE_INSN_MOVL; goto extract_sfmt_movl; + case 7 : itype = I960BASE_INSN_MOVL1; goto extract_sfmt_movl1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 94 : @@ -895,9 +863,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 5 : itype = I960BASE_INSN_MOVT; goto extract_fmt_movt; - case 7 : itype = I960BASE_INSN_MOVT1; goto extract_fmt_movt1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 5 : itype = I960BASE_INSN_MOVT; goto extract_sfmt_movt; + case 7 : itype = I960BASE_INSN_MOVT1; goto extract_sfmt_movt1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 95 : @@ -905,30 +873,30 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 5 : itype = I960BASE_INSN_MOVQ; goto extract_fmt_movq; - case 7 : itype = I960BASE_INSN_MOVQ1; goto extract_fmt_movq1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 5 : itype = I960BASE_INSN_MOVQ; goto extract_sfmt_movq; + case 7 : itype = I960BASE_INSN_MOVQ1; goto extract_sfmt_movq1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 100 : itype = I960BASE_INSN_MODAC; goto extract_fmt_modpc; - case 101 : itype = I960BASE_INSN_MODPC; goto extract_fmt_modpc; + case 100 : itype = I960BASE_INSN_MODAC; goto extract_sfmt_modpc; + case 101 : itype = I960BASE_INSN_MODPC; goto extract_sfmt_modpc; case 102 : { unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 12 : itype = I960BASE_INSN_CALLS; goto extract_fmt_calls; + case 12 : itype = I960BASE_INSN_CALLS; goto extract_sfmt_calls; case 15 : { unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 8 : itype = I960BASE_INSN_FMARK; goto extract_fmt_fmark; - case 10 : itype = I960BASE_INSN_FLUSHREG; goto extract_fmt_flushreg; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 8 : itype = I960BASE_INSN_FMARK; goto extract_sfmt_fmark; + case 10 : itype = I960BASE_INSN_FLUSHREG; goto extract_sfmt_flushreg; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 103 : @@ -936,11 +904,11 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_EMUL; goto extract_fmt_emul; - case 2 : itype = I960BASE_INSN_EMUL1; goto extract_fmt_emul1; - case 4 : itype = I960BASE_INSN_EMUL2; goto extract_fmt_emul2; - case 6 : itype = I960BASE_INSN_EMUL3; goto extract_fmt_emul3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_EMUL; goto extract_sfmt_emul; + case 2 : itype = I960BASE_INSN_EMUL1; goto extract_sfmt_emul1; + case 4 : itype = I960BASE_INSN_EMUL2; goto extract_sfmt_emul2; + case 6 : itype = I960BASE_INSN_EMUL3; goto extract_sfmt_emul3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 112 : @@ -948,51 +916,51 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_MULO; goto extract_fmt_mulo; + case 0 : itype = I960BASE_INSN_MULO; goto extract_sfmt_mulo; case 1 : { unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMO; goto extract_fmt_mulo; - case 6 : itype = I960BASE_INSN_DIVO; goto extract_fmt_mulo; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMO; goto extract_sfmt_mulo; + case 6 : itype = I960BASE_INSN_DIVO; goto extract_sfmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 2 : itype = I960BASE_INSN_MULO1; goto extract_fmt_mulo1; + case 2 : itype = I960BASE_INSN_MULO1; goto extract_sfmt_mulo1; case 3 : { unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMO1; goto extract_fmt_mulo1; - case 6 : itype = I960BASE_INSN_DIVO1; goto extract_fmt_mulo1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMO1; goto extract_sfmt_mulo1; + case 6 : itype = I960BASE_INSN_DIVO1; goto extract_sfmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 4 : itype = I960BASE_INSN_MULO2; goto extract_fmt_mulo2; + case 4 : itype = I960BASE_INSN_MULO2; goto extract_sfmt_mulo2; case 5 : { unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMO2; goto extract_fmt_mulo2; - case 6 : itype = I960BASE_INSN_DIVO2; goto extract_fmt_mulo2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMO2; goto extract_sfmt_mulo2; + case 6 : itype = I960BASE_INSN_DIVO2; goto extract_sfmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 6 : itype = I960BASE_INSN_MULO3; goto extract_fmt_mulo3; + case 6 : itype = I960BASE_INSN_MULO3; goto extract_sfmt_mulo3; case 7 : { unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMO3; goto extract_fmt_mulo3; - case 6 : itype = I960BASE_INSN_DIVO3; goto extract_fmt_mulo3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMO3; goto extract_sfmt_mulo3; + case 6 : itype = I960BASE_INSN_DIVO3; goto extract_sfmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 116 : @@ -1005,9 +973,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMI; goto extract_fmt_mulo; - case 6 : itype = I960BASE_INSN_DIVI; goto extract_fmt_mulo; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMI; goto extract_sfmt_mulo; + case 6 : itype = I960BASE_INSN_DIVI; goto extract_sfmt_mulo; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 3 : @@ -1015,9 +983,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMI1; goto extract_fmt_mulo1; - case 6 : itype = I960BASE_INSN_DIVI1; goto extract_fmt_mulo1; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMI1; goto extract_sfmt_mulo1; + case 6 : itype = I960BASE_INSN_DIVI1; goto extract_sfmt_mulo1; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 5 : @@ -1025,9 +993,9 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMI2; goto extract_fmt_mulo2; - case 6 : itype = I960BASE_INSN_DIVI2; goto extract_fmt_mulo2; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMI2; goto extract_sfmt_mulo2; + case 6 : itype = I960BASE_INSN_DIVI2; goto extract_sfmt_mulo2; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 7 : @@ -1035,12 +1003,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 6) & (15 << 0))); switch (val) { - case 0 : itype = I960BASE_INSN_REMI3; goto extract_fmt_mulo3; - case 6 : itype = I960BASE_INSN_DIVI3; goto extract_fmt_mulo3; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = I960BASE_INSN_REMI3; goto extract_sfmt_mulo3; + case 6 : itype = I960BASE_INSN_DIVI3; goto extract_sfmt_mulo3; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 128 : @@ -1051,18 +1019,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDOB_OFFSET; goto extract_fmt_ldob_offset; - case 4 : itype = I960BASE_INSN_LDOB_INDIRECT; goto extract_fmt_ldob_indirect; - case 7 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX; goto extract_fmt_ldob_indirect_index; + case 3 : itype = I960BASE_INSN_LDOB_OFFSET; goto extract_sfmt_ld_offset; + case 4 : itype = I960BASE_INSN_LDOB_INDIRECT; goto extract_sfmt_ld_indirect; + case 7 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX; goto extract_sfmt_ld_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDOB_INDIRECT_OFFSET; goto extract_fmt_ldob_indirect_offset; - case 12 : itype = I960BASE_INSN_LDOB_DISP; goto extract_fmt_ldob_disp; - case 13 : itype = I960BASE_INSN_LDOB_INDIRECT_DISP; goto extract_fmt_ldob_indirect_disp; - case 14 : itype = I960BASE_INSN_LDOB_INDEX_DISP; goto extract_fmt_ldob_index_disp; - case 15 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP; goto extract_fmt_ldob_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDOB_INDIRECT_OFFSET; goto extract_sfmt_ld_indirect_offset; + case 12 : itype = I960BASE_INSN_LDOB_DISP; goto extract_sfmt_ld_disp; + case 13 : itype = I960BASE_INSN_LDOB_INDIRECT_DISP; goto extract_sfmt_ld_indirect_disp; + case 14 : itype = I960BASE_INSN_LDOB_INDEX_DISP; goto extract_sfmt_ld_index_disp; + case 15 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP; goto extract_sfmt_ld_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 130 : @@ -1073,18 +1041,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_STOB_OFFSET; goto extract_fmt_stob_offset; - case 4 : itype = I960BASE_INSN_STOB_INDIRECT; goto extract_fmt_stob_indirect; - case 7 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX; goto extract_fmt_stob_indirect_index; + case 3 : itype = I960BASE_INSN_STOB_OFFSET; goto extract_sfmt_st_offset; + case 4 : itype = I960BASE_INSN_STOB_INDIRECT; goto extract_sfmt_st_indirect; + case 7 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX; goto extract_sfmt_st_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_STOB_INDIRECT_OFFSET; goto extract_fmt_stob_indirect_offset; - case 12 : itype = I960BASE_INSN_STOB_DISP; goto extract_fmt_stob_disp; - case 13 : itype = I960BASE_INSN_STOB_INDIRECT_DISP; goto extract_fmt_stob_indirect_disp; - case 14 : itype = I960BASE_INSN_STOB_INDEX_DISP; goto extract_fmt_stob_index_disp; - case 15 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX_DISP; goto extract_fmt_stob_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_STOB_INDIRECT_OFFSET; goto extract_sfmt_st_indirect_offset; + case 12 : itype = I960BASE_INSN_STOB_DISP; goto extract_sfmt_st_disp; + case 13 : itype = I960BASE_INSN_STOB_INDIRECT_DISP; goto extract_sfmt_st_indirect_disp; + case 14 : itype = I960BASE_INSN_STOB_INDEX_DISP; goto extract_sfmt_st_index_disp; + case 15 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX_DISP; goto extract_sfmt_st_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 132 : @@ -1092,15 +1060,15 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 4 : itype = I960BASE_INSN_BX_INDIRECT; goto extract_fmt_bx_indirect; - case 7 : itype = I960BASE_INSN_BX_INDIRECT_INDEX; goto extract_fmt_bx_indirect_index; + case 4 : itype = I960BASE_INSN_BX_INDIRECT; goto extract_sfmt_bx_indirect; + case 7 : itype = I960BASE_INSN_BX_INDIRECT_INDEX; goto extract_sfmt_bx_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_BX_INDIRECT_OFFSET; goto extract_fmt_bx_indirect_offset; - case 12 : itype = I960BASE_INSN_BX_DISP; goto extract_fmt_bx_disp; - case 13 : itype = I960BASE_INSN_BX_INDIRECT_DISP; goto extract_fmt_bx_indirect_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_BX_INDIRECT_OFFSET; goto extract_sfmt_bx_indirect_offset; + case 12 : itype = I960BASE_INSN_BX_DISP; goto extract_sfmt_bx_disp; + case 13 : itype = I960BASE_INSN_BX_INDIRECT_DISP; goto extract_sfmt_bx_indirect_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 134 : @@ -1108,13 +1076,13 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 10) & (15 << 0))); switch (val) { - case 4 : itype = I960BASE_INSN_CALLX_INDIRECT; goto extract_fmt_callx_indirect; + case 4 : itype = I960BASE_INSN_CALLX_INDIRECT; goto extract_sfmt_callx_indirect; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_CALLX_INDIRECT_OFFSET; goto extract_fmt_callx_indirect_offset; - case 12 : itype = I960BASE_INSN_CALLX_DISP; goto extract_fmt_callx_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_CALLX_INDIRECT_OFFSET; goto extract_sfmt_callx_indirect_offset; + case 12 : itype = I960BASE_INSN_CALLX_DISP; goto extract_sfmt_callx_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 136 : @@ -1125,18 +1093,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDOS_OFFSET; goto extract_fmt_ldos_offset; - case 4 : itype = I960BASE_INSN_LDOS_INDIRECT; goto extract_fmt_ldos_indirect; - case 7 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX; goto extract_fmt_ldos_indirect_index; + case 3 : itype = I960BASE_INSN_LDOS_OFFSET; goto extract_sfmt_ld_offset; + case 4 : itype = I960BASE_INSN_LDOS_INDIRECT; goto extract_sfmt_ld_indirect; + case 7 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX; goto extract_sfmt_ld_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDOS_INDIRECT_OFFSET; goto extract_fmt_ldos_indirect_offset; - case 12 : itype = I960BASE_INSN_LDOS_DISP; goto extract_fmt_ldos_disp; - case 13 : itype = I960BASE_INSN_LDOS_INDIRECT_DISP; goto extract_fmt_ldos_indirect_disp; - case 14 : itype = I960BASE_INSN_LDOS_INDEX_DISP; goto extract_fmt_ldos_index_disp; - case 15 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP; goto extract_fmt_ldos_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDOS_INDIRECT_OFFSET; goto extract_sfmt_ld_indirect_offset; + case 12 : itype = I960BASE_INSN_LDOS_DISP; goto extract_sfmt_ld_disp; + case 13 : itype = I960BASE_INSN_LDOS_INDIRECT_DISP; goto extract_sfmt_ld_indirect_disp; + case 14 : itype = I960BASE_INSN_LDOS_INDEX_DISP; goto extract_sfmt_ld_index_disp; + case 15 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP; goto extract_sfmt_ld_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 138 : @@ -1147,18 +1115,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_STOS_OFFSET; goto extract_fmt_stos_offset; - case 4 : itype = I960BASE_INSN_STOS_INDIRECT; goto extract_fmt_stos_indirect; - case 7 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX; goto extract_fmt_stos_indirect_index; + case 3 : itype = I960BASE_INSN_STOS_OFFSET; goto extract_sfmt_st_offset; + case 4 : itype = I960BASE_INSN_STOS_INDIRECT; goto extract_sfmt_st_indirect; + case 7 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX; goto extract_sfmt_st_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_STOS_INDIRECT_OFFSET; goto extract_fmt_stos_indirect_offset; - case 12 : itype = I960BASE_INSN_STOS_DISP; goto extract_fmt_stos_disp; - case 13 : itype = I960BASE_INSN_STOS_INDIRECT_DISP; goto extract_fmt_stos_indirect_disp; - case 14 : itype = I960BASE_INSN_STOS_INDEX_DISP; goto extract_fmt_stos_index_disp; - case 15 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX_DISP; goto extract_fmt_stos_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_STOS_INDIRECT_OFFSET; goto extract_sfmt_st_indirect_offset; + case 12 : itype = I960BASE_INSN_STOS_DISP; goto extract_sfmt_st_disp; + case 13 : itype = I960BASE_INSN_STOS_INDIRECT_DISP; goto extract_sfmt_st_indirect_disp; + case 14 : itype = I960BASE_INSN_STOS_INDEX_DISP; goto extract_sfmt_st_index_disp; + case 15 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX_DISP; goto extract_sfmt_st_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 140 : @@ -1169,18 +1137,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDA_OFFSET; goto extract_fmt_lda_offset; - case 4 : itype = I960BASE_INSN_LDA_INDIRECT; goto extract_fmt_lda_indirect; - case 7 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX; goto extract_fmt_lda_indirect_index; + case 3 : itype = I960BASE_INSN_LDA_OFFSET; goto extract_sfmt_lda_offset; + case 4 : itype = I960BASE_INSN_LDA_INDIRECT; goto extract_sfmt_lda_indirect; + case 7 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX; goto extract_sfmt_lda_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDA_INDIRECT_OFFSET; goto extract_fmt_lda_indirect_offset; - case 12 : itype = I960BASE_INSN_LDA_DISP; goto extract_fmt_lda_disp; - case 13 : itype = I960BASE_INSN_LDA_INDIRECT_DISP; goto extract_fmt_lda_indirect_disp; - case 14 : itype = I960BASE_INSN_LDA_INDEX_DISP; goto extract_fmt_lda_index_disp; - case 15 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX_DISP; goto extract_fmt_lda_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDA_INDIRECT_OFFSET; goto extract_sfmt_lda_indirect_offset; + case 12 : itype = I960BASE_INSN_LDA_DISP; goto extract_sfmt_lda_disp; + case 13 : itype = I960BASE_INSN_LDA_INDIRECT_DISP; goto extract_sfmt_lda_indirect_disp; + case 14 : itype = I960BASE_INSN_LDA_INDEX_DISP; goto extract_sfmt_lda_index_disp; + case 15 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX_DISP; goto extract_sfmt_lda_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 144 : @@ -1191,18 +1159,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LD_OFFSET; goto extract_fmt_ld_offset; - case 4 : itype = I960BASE_INSN_LD_INDIRECT; goto extract_fmt_ld_indirect; - case 7 : itype = I960BASE_INSN_LD_INDIRECT_INDEX; goto extract_fmt_ld_indirect_index; + case 3 : itype = I960BASE_INSN_LD_OFFSET; goto extract_sfmt_ld_offset; + case 4 : itype = I960BASE_INSN_LD_INDIRECT; goto extract_sfmt_ld_indirect; + case 7 : itype = I960BASE_INSN_LD_INDIRECT_INDEX; goto extract_sfmt_ld_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LD_INDIRECT_OFFSET; goto extract_fmt_ld_indirect_offset; - case 12 : itype = I960BASE_INSN_LD_DISP; goto extract_fmt_ld_disp; - case 13 : itype = I960BASE_INSN_LD_INDIRECT_DISP; goto extract_fmt_ld_indirect_disp; - case 14 : itype = I960BASE_INSN_LD_INDEX_DISP; goto extract_fmt_ld_index_disp; - case 15 : itype = I960BASE_INSN_LD_INDIRECT_INDEX_DISP; goto extract_fmt_ld_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LD_INDIRECT_OFFSET; goto extract_sfmt_ld_indirect_offset; + case 12 : itype = I960BASE_INSN_LD_DISP; goto extract_sfmt_ld_disp; + case 13 : itype = I960BASE_INSN_LD_INDIRECT_DISP; goto extract_sfmt_ld_indirect_disp; + case 14 : itype = I960BASE_INSN_LD_INDEX_DISP; goto extract_sfmt_ld_index_disp; + case 15 : itype = I960BASE_INSN_LD_INDIRECT_INDEX_DISP; goto extract_sfmt_ld_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 146 : @@ -1213,18 +1181,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_ST_OFFSET; goto extract_fmt_st_offset; - case 4 : itype = I960BASE_INSN_ST_INDIRECT; goto extract_fmt_st_indirect; - case 7 : itype = I960BASE_INSN_ST_INDIRECT_INDEX; goto extract_fmt_st_indirect_index; + case 3 : itype = I960BASE_INSN_ST_OFFSET; goto extract_sfmt_st_offset; + case 4 : itype = I960BASE_INSN_ST_INDIRECT; goto extract_sfmt_st_indirect; + case 7 : itype = I960BASE_INSN_ST_INDIRECT_INDEX; goto extract_sfmt_st_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_ST_INDIRECT_OFFSET; goto extract_fmt_st_indirect_offset; - case 12 : itype = I960BASE_INSN_ST_DISP; goto extract_fmt_st_disp; - case 13 : itype = I960BASE_INSN_ST_INDIRECT_DISP; goto extract_fmt_st_indirect_disp; - case 14 : itype = I960BASE_INSN_ST_INDEX_DISP; goto extract_fmt_st_index_disp; - case 15 : itype = I960BASE_INSN_ST_INDIRECT_INDEX_DISP; goto extract_fmt_st_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_ST_INDIRECT_OFFSET; goto extract_sfmt_st_indirect_offset; + case 12 : itype = I960BASE_INSN_ST_DISP; goto extract_sfmt_st_disp; + case 13 : itype = I960BASE_INSN_ST_INDIRECT_DISP; goto extract_sfmt_st_indirect_disp; + case 14 : itype = I960BASE_INSN_ST_INDEX_DISP; goto extract_sfmt_st_index_disp; + case 15 : itype = I960BASE_INSN_ST_INDIRECT_INDEX_DISP; goto extract_sfmt_st_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 152 : @@ -1235,18 +1203,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDL_OFFSET; goto extract_fmt_ldl_offset; - case 4 : itype = I960BASE_INSN_LDL_INDIRECT; goto extract_fmt_ldl_indirect; - case 7 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX; goto extract_fmt_ldl_indirect_index; + case 3 : itype = I960BASE_INSN_LDL_OFFSET; goto extract_sfmt_ldl_offset; + case 4 : itype = I960BASE_INSN_LDL_INDIRECT; goto extract_sfmt_ldl_indirect; + case 7 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX; goto extract_sfmt_ldl_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDL_INDIRECT_OFFSET; goto extract_fmt_ldl_indirect_offset; - case 12 : itype = I960BASE_INSN_LDL_DISP; goto extract_fmt_ldl_disp; - case 13 : itype = I960BASE_INSN_LDL_INDIRECT_DISP; goto extract_fmt_ldl_indirect_disp; - case 14 : itype = I960BASE_INSN_LDL_INDEX_DISP; goto extract_fmt_ldl_index_disp; - case 15 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX_DISP; goto extract_fmt_ldl_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDL_INDIRECT_OFFSET; goto extract_sfmt_ldl_indirect_offset; + case 12 : itype = I960BASE_INSN_LDL_DISP; goto extract_sfmt_ldl_disp; + case 13 : itype = I960BASE_INSN_LDL_INDIRECT_DISP; goto extract_sfmt_ldl_indirect_disp; + case 14 : itype = I960BASE_INSN_LDL_INDEX_DISP; goto extract_sfmt_ldl_index_disp; + case 15 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX_DISP; goto extract_sfmt_ldl_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 154 : @@ -1257,18 +1225,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_STL_OFFSET; goto extract_fmt_stl_offset; - case 4 : itype = I960BASE_INSN_STL_INDIRECT; goto extract_fmt_stl_indirect; - case 7 : itype = I960BASE_INSN_STL_INDIRECT_INDEX; goto extract_fmt_stl_indirect_index; + case 3 : itype = I960BASE_INSN_STL_OFFSET; goto extract_sfmt_stl_offset; + case 4 : itype = I960BASE_INSN_STL_INDIRECT; goto extract_sfmt_stl_indirect; + case 7 : itype = I960BASE_INSN_STL_INDIRECT_INDEX; goto extract_sfmt_stl_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_STL_INDIRECT_OFFSET; goto extract_fmt_stl_indirect_offset; - case 12 : itype = I960BASE_INSN_STL_DISP; goto extract_fmt_stl_disp; - case 13 : itype = I960BASE_INSN_STL_INDIRECT_DISP; goto extract_fmt_stl_indirect_disp; - case 14 : itype = I960BASE_INSN_STL_INDEX_DISP; goto extract_fmt_stl_index_disp; - case 15 : itype = I960BASE_INSN_STL_INDIRECT_INDEX_DISP; goto extract_fmt_stl_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_STL_INDIRECT_OFFSET; goto extract_sfmt_stl_indirect_offset; + case 12 : itype = I960BASE_INSN_STL_DISP; goto extract_sfmt_stl_disp; + case 13 : itype = I960BASE_INSN_STL_INDIRECT_DISP; goto extract_sfmt_stl_indirect_disp; + case 14 : itype = I960BASE_INSN_STL_INDEX_DISP; goto extract_sfmt_stl_index_disp; + case 15 : itype = I960BASE_INSN_STL_INDIRECT_INDEX_DISP; goto extract_sfmt_stl_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 160 : @@ -1279,18 +1247,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDT_OFFSET; goto extract_fmt_ldt_offset; - case 4 : itype = I960BASE_INSN_LDT_INDIRECT; goto extract_fmt_ldt_indirect; - case 7 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX; goto extract_fmt_ldt_indirect_index; + case 3 : itype = I960BASE_INSN_LDT_OFFSET; goto extract_sfmt_ldt_offset; + case 4 : itype = I960BASE_INSN_LDT_INDIRECT; goto extract_sfmt_ldt_indirect; + case 7 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX; goto extract_sfmt_ldt_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDT_INDIRECT_OFFSET; goto extract_fmt_ldt_indirect_offset; - case 12 : itype = I960BASE_INSN_LDT_DISP; goto extract_fmt_ldt_disp; - case 13 : itype = I960BASE_INSN_LDT_INDIRECT_DISP; goto extract_fmt_ldt_indirect_disp; - case 14 : itype = I960BASE_INSN_LDT_INDEX_DISP; goto extract_fmt_ldt_index_disp; - case 15 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX_DISP; goto extract_fmt_ldt_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDT_INDIRECT_OFFSET; goto extract_sfmt_ldt_indirect_offset; + case 12 : itype = I960BASE_INSN_LDT_DISP; goto extract_sfmt_ldt_disp; + case 13 : itype = I960BASE_INSN_LDT_INDIRECT_DISP; goto extract_sfmt_ldt_indirect_disp; + case 14 : itype = I960BASE_INSN_LDT_INDEX_DISP; goto extract_sfmt_ldt_index_disp; + case 15 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX_DISP; goto extract_sfmt_ldt_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 162 : @@ -1301,18 +1269,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_STT_OFFSET; goto extract_fmt_stt_offset; - case 4 : itype = I960BASE_INSN_STT_INDIRECT; goto extract_fmt_stt_indirect; - case 7 : itype = I960BASE_INSN_STT_INDIRECT_INDEX; goto extract_fmt_stt_indirect_index; + case 3 : itype = I960BASE_INSN_STT_OFFSET; goto extract_sfmt_stt_offset; + case 4 : itype = I960BASE_INSN_STT_INDIRECT; goto extract_sfmt_stt_indirect; + case 7 : itype = I960BASE_INSN_STT_INDIRECT_INDEX; goto extract_sfmt_stt_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_STT_INDIRECT_OFFSET; goto extract_fmt_stt_indirect_offset; - case 12 : itype = I960BASE_INSN_STT_DISP; goto extract_fmt_stt_disp; - case 13 : itype = I960BASE_INSN_STT_INDIRECT_DISP; goto extract_fmt_stt_indirect_disp; - case 14 : itype = I960BASE_INSN_STT_INDEX_DISP; goto extract_fmt_stt_index_disp; - case 15 : itype = I960BASE_INSN_STT_INDIRECT_INDEX_DISP; goto extract_fmt_stt_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_STT_INDIRECT_OFFSET; goto extract_sfmt_stt_indirect_offset; + case 12 : itype = I960BASE_INSN_STT_DISP; goto extract_sfmt_stt_disp; + case 13 : itype = I960BASE_INSN_STT_INDIRECT_DISP; goto extract_sfmt_stt_indirect_disp; + case 14 : itype = I960BASE_INSN_STT_INDEX_DISP; goto extract_sfmt_stt_index_disp; + case 15 : itype = I960BASE_INSN_STT_INDIRECT_INDEX_DISP; goto extract_sfmt_stt_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 176 : @@ -1323,18 +1291,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDQ_OFFSET; goto extract_fmt_ldq_offset; - case 4 : itype = I960BASE_INSN_LDQ_INDIRECT; goto extract_fmt_ldq_indirect; - case 7 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX; goto extract_fmt_ldq_indirect_index; + case 3 : itype = I960BASE_INSN_LDQ_OFFSET; goto extract_sfmt_ldq_offset; + case 4 : itype = I960BASE_INSN_LDQ_INDIRECT; goto extract_sfmt_ldq_indirect; + case 7 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX; goto extract_sfmt_ldq_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDQ_INDIRECT_OFFSET; goto extract_fmt_ldq_indirect_offset; - case 12 : itype = I960BASE_INSN_LDQ_DISP; goto extract_fmt_ldq_disp; - case 13 : itype = I960BASE_INSN_LDQ_INDIRECT_DISP; goto extract_fmt_ldq_indirect_disp; - case 14 : itype = I960BASE_INSN_LDQ_INDEX_DISP; goto extract_fmt_ldq_index_disp; - case 15 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP; goto extract_fmt_ldq_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDQ_INDIRECT_OFFSET; goto extract_sfmt_ldq_indirect_offset; + case 12 : itype = I960BASE_INSN_LDQ_DISP; goto extract_sfmt_ldq_disp; + case 13 : itype = I960BASE_INSN_LDQ_INDIRECT_DISP; goto extract_sfmt_ldq_indirect_disp; + case 14 : itype = I960BASE_INSN_LDQ_INDEX_DISP; goto extract_sfmt_ldq_index_disp; + case 15 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP; goto extract_sfmt_ldq_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 178 : @@ -1345,18 +1313,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_STQ_OFFSET; goto extract_fmt_stq_offset; - case 4 : itype = I960BASE_INSN_STQ_INDIRECT; goto extract_fmt_stq_indirect; - case 7 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX; goto extract_fmt_stq_indirect_index; + case 3 : itype = I960BASE_INSN_STQ_OFFSET; goto extract_sfmt_stq_offset; + case 4 : itype = I960BASE_INSN_STQ_INDIRECT; goto extract_sfmt_stq_indirect; + case 7 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX; goto extract_sfmt_stq_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_STQ_INDIRECT_OFFSET; goto extract_fmt_stq_indirect_offset; - case 12 : itype = I960BASE_INSN_STQ_DISP; goto extract_fmt_stq_disp; - case 13 : itype = I960BASE_INSN_STQ_INDIRECT_DISP; goto extract_fmt_stq_indirect_disp; - case 14 : itype = I960BASE_INSN_STQ_INDEX_DISP; goto extract_fmt_stq_index_disp; - case 15 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX_DISP; goto extract_fmt_stq_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_STQ_INDIRECT_OFFSET; goto extract_sfmt_stq_indirect_offset; + case 12 : itype = I960BASE_INSN_STQ_DISP; goto extract_sfmt_stq_disp; + case 13 : itype = I960BASE_INSN_STQ_INDIRECT_DISP; goto extract_sfmt_stq_indirect_disp; + case 14 : itype = I960BASE_INSN_STQ_INDEX_DISP; goto extract_sfmt_stq_index_disp; + case 15 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX_DISP; goto extract_sfmt_stq_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 192 : @@ -1367,18 +1335,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDIB_OFFSET; goto extract_fmt_ldib_offset; - case 4 : itype = I960BASE_INSN_LDIB_INDIRECT; goto extract_fmt_ldib_indirect; - case 7 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX; goto extract_fmt_ldib_indirect_index; + case 3 : itype = I960BASE_INSN_LDIB_OFFSET; goto extract_sfmt_ld_offset; + case 4 : itype = I960BASE_INSN_LDIB_INDIRECT; goto extract_sfmt_ld_indirect; + case 7 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX; goto extract_sfmt_ld_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDIB_INDIRECT_OFFSET; goto extract_fmt_ldib_indirect_offset; - case 12 : itype = I960BASE_INSN_LDIB_DISP; goto extract_fmt_ldib_disp; - case 13 : itype = I960BASE_INSN_LDIB_INDIRECT_DISP; goto extract_fmt_ldib_indirect_disp; - case 14 : itype = I960BASE_INSN_LDIB_INDEX_DISP; goto extract_fmt_ldib_index_disp; - case 15 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP; goto extract_fmt_ldib_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDIB_INDIRECT_OFFSET; goto extract_sfmt_ld_indirect_offset; + case 12 : itype = I960BASE_INSN_LDIB_DISP; goto extract_sfmt_ld_disp; + case 13 : itype = I960BASE_INSN_LDIB_INDIRECT_DISP; goto extract_sfmt_ld_indirect_disp; + case 14 : itype = I960BASE_INSN_LDIB_INDEX_DISP; goto extract_sfmt_ld_index_disp; + case 15 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP; goto extract_sfmt_ld_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } case 200 : @@ -1389,57 +1357,59 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, case 0 : /* fall through */ case 1 : /* fall through */ case 2 : /* fall through */ - case 3 : itype = I960BASE_INSN_LDIS_OFFSET; goto extract_fmt_ldis_offset; - case 4 : itype = I960BASE_INSN_LDIS_INDIRECT; goto extract_fmt_ldis_indirect; - case 7 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX; goto extract_fmt_ldis_indirect_index; + case 3 : itype = I960BASE_INSN_LDIS_OFFSET; goto extract_sfmt_ld_offset; + case 4 : itype = I960BASE_INSN_LDIS_INDIRECT; goto extract_sfmt_ld_indirect; + case 7 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX; goto extract_sfmt_ld_indirect_index; case 8 : /* fall through */ case 9 : /* fall through */ case 10 : /* fall through */ - case 11 : itype = I960BASE_INSN_LDIS_INDIRECT_OFFSET; goto extract_fmt_ldis_indirect_offset; - case 12 : itype = I960BASE_INSN_LDIS_DISP; goto extract_fmt_ldis_disp; - case 13 : itype = I960BASE_INSN_LDIS_INDIRECT_DISP; goto extract_fmt_ldis_indirect_disp; - case 14 : itype = I960BASE_INSN_LDIS_INDEX_DISP; goto extract_fmt_ldis_index_disp; - case 15 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP; goto extract_fmt_ldis_indirect_index_disp; - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + case 11 : itype = I960BASE_INSN_LDIS_INDIRECT_OFFSET; goto extract_sfmt_ld_indirect_offset; + case 12 : itype = I960BASE_INSN_LDIS_DISP; goto extract_sfmt_ld_disp; + case 13 : itype = I960BASE_INSN_LDIS_INDIRECT_DISP; goto extract_sfmt_ld_indirect_disp; + case 14 : itype = I960BASE_INSN_LDIS_INDEX_DISP; goto extract_sfmt_ld_index_disp; + case 15 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP; goto extract_sfmt_ld_indirect_index_disp; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = I960BASE_INSN_X_INVALID; goto extract_sfmt_empty; } } } /* The instruction has been decoded, now extract the fields. */ - extract_fmt_empty: + extract_sfmt_empty: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); #undef FLD return idesc; } - extract_fmt_mulo: + extract_sfmt_mulo: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mulo.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1454,20 +1424,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mulo1: + extract_sfmt_mulo1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mulo1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO1_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1481,20 +1455,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mulo2: + extract_sfmt_mulo2: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mulo2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src2) = f_src2; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1508,20 +1486,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mulo3: + extract_sfmt_mulo3: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_mulo3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_src2) = f_src2; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1534,20 +1516,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_notbit: + extract_sfmt_notbit: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_notbit.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_notbit", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1562,20 +1548,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_notbit1: + extract_sfmt_notbit1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_notbit1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO1_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_notbit1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1589,20 +1579,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_notbit2: + extract_sfmt_notbit2: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_notbit2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src2) = f_src2; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_notbit2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1616,71 +1610,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_notbit3: + extract_sfmt_notbit3: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_notbit3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_src2) = f_src2; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_notbit3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (out_dst) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_not: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_not.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ - - EXTRACT_IFMT_MULO_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_src1) = & CPU (h_gr)[f_src1]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_src1) = f_src1; - FLD (out_dst) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_not1: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_not1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ - - EXTRACT_IFMT_MULO1_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_src1) = f_src1; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not1", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_notbit3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1693,19 +1640,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_not2: + extract_sfmt_not: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_not2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not2", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not", "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1719,19 +1668,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_not3: + extract_sfmt_not1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_not3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_not3", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_not1", "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1744,20 +1695,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_shlo: + extract_sfmt_shlo: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_shlo.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shlo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1772,20 +1727,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_shlo1: + extract_sfmt_shlo1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_shlo1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO1_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shlo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1799,20 +1758,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_shlo2: + extract_sfmt_shlo2: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_shlo2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src2) = f_src2; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shlo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1826,20 +1789,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_shlo3: + extract_sfmt_shlo3: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_shlo3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_src2) = f_src2; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shlo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1852,21 +1819,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_emul: + extract_sfmt_emul: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_emul.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul", "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_emul", "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1882,21 +1853,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_emul1: + extract_sfmt_emul1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_emul1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO1_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_src1) = f_src1; FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_emul1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1911,21 +1886,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_emul2: + extract_sfmt_emul2: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_emul2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_src2) = f_src2; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul2", "f_srcdst 0x%x", 'x', f_srcdst, "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_emul2", "f_srcdst 0x%x", 'x', f_srcdst, "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1940,21 +1919,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_emul3: + extract_sfmt_emul3: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_emul3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_srcdst; + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_src1) = f_src1; FLD (f_src2) = f_src2; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_emul3", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_emul3", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1968,21 +1951,23 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movl: + extract_sfmt_movl: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movl.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_movq.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_srcdst) = f_srcdst; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movl", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1998,20 +1983,22 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movl1: + extract_sfmt_movl1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movl1.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_src1) = f_src1; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movl1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2025,21 +2012,23 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movt: + extract_sfmt_movt: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movt.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_movq.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_srcdst) = f_srcdst; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movt", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movt", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2057,20 +2046,22 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movt1: + extract_sfmt_movt1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movt1.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_movq.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_src1) = f_src1; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movt1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movt1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2085,21 +2076,23 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movq: + extract_sfmt_movq: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movq.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_movq.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_srcdst) = f_srcdst; FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movq", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movq", "f_src1 0x%x", 'x', f_src1, "f_srcdst 0x%x", 'x', f_srcdst, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2119,20 +2112,22 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_movq1: + extract_sfmt_movq1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_movq1.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_movq.f + UINT f_srcdst; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_src1) = f_src1; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_movq1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movq1", "f_srcdst 0x%x", 'x', f_srcdst, "f_src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2148,19 +2143,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_modpc: + extract_sfmt_modpc: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_modpc.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_srcdst; + UINT f_src2; - EXTRACT_IFMT_MULO_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (i_src2) = & CPU (h_gr)[f_src2]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_modpc", "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_modpc", "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2174,19 +2171,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_offset: + extract_sfmt_lda_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2199,20 +2198,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_indirect_offset: + extract_sfmt_lda_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2226,19 +2229,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_indirect: + extract_sfmt_lda_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2252,21 +2257,27 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_indirect_index: + extract_sfmt_lda_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2281,19 +2292,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_disp: + extract_sfmt_lda_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2306,20 +2322,27 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_indirect_disp: + extract_sfmt_lda_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2333,21 +2356,30 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_index_disp: + extract_sfmt_lda_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2361,14 +2393,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lda_indirect_index_disp: + extract_sfmt_lda_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; @@ -2376,7 +2419,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lda_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lda_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2391,19 +2434,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_offset: + extract_sfmt_ld_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2416,20 +2461,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_indirect_offset: + extract_sfmt_ld_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2443,19 +2492,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_indirect: + extract_sfmt_ld_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2469,21 +2520,27 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_indirect_index: + extract_sfmt_ld_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2498,19 +2555,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_disp: + extract_sfmt_ld_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2523,20 +2585,27 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_indirect_disp: + extract_sfmt_ld_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2550,21 +2619,30 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_index_disp: + extract_sfmt_ld_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2578,14 +2656,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld_indirect_index_disp: + extract_sfmt_ld_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; @@ -2593,7 +2682,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2608,45 +2697,54 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldob_offset: + extract_sfmt_ldl_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_indirect_offset: + extract_sfmt_ldl_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2654,25 +2752,29 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_indirect: + extract_sfmt_ldl_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2680,27 +2782,35 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_indirect_index: + extract_sfmt_ldl_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2709,51 +2819,67 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_disp: + extract_sfmt_ldl_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_indirect_disp: + extract_sfmt_ldl_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2761,27 +2887,38 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_index_disp: + extract_sfmt_ldl_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2789,28 +2926,41 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldob_indirect_index_disp: + extract_sfmt_ldl_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldob_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2819,51 +2969,62 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_offset: + extract_sfmt_ldt_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_indirect_offset: + extract_sfmt_ldt_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2871,25 +3032,30 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_indirect: + extract_sfmt_ldt_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2897,27 +3063,36 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_indirect_index: + extract_sfmt_ldt_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2926,51 +3101,69 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_disp: + extract_sfmt_ldt_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_indirect_disp: + extract_sfmt_ldt_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -2978,27 +3171,39 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_index_disp: + extract_sfmt_ldt_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3006,28 +3211,42 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldos_indirect_index_disp: + extract_sfmt_ldt_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldos_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3036,51 +3255,64 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_offset: + extract_sfmt_ldq_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_indirect_offset: + extract_sfmt_ldq_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3088,25 +3320,31 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_indirect: + extract_sfmt_ldq_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3114,27 +3352,37 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_indirect_index: + extract_sfmt_ldq_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3143,51 +3391,71 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_disp: + extract_sfmt_ldq_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_indirect_disp: + extract_sfmt_ldq_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3195,27 +3463,40 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_index_disp: + extract_sfmt_ldq_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3223,28 +3504,43 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldib_indirect_index_disp: + extract_sfmt_ldq_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ + FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldib_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3253,105 +3549,122 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_abase) = f_abase; FLD (in_index) = f_index; FLD (out_dst) = f_srcdst; + FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); } #endif #undef FLD return idesc; } - extract_fmt_ldis_offset: + extract_sfmt_st_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_offset", "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_indirect_offset: + extract_sfmt_st_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_indirect: + extract_sfmt_st_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect", "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_indirect_index: + extract_sfmt_st_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3359,109 +3672,141 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_disp: + extract_sfmt_st_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_disp", "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_indirect_disp: + extract_sfmt_st_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_index_disp: + extract_sfmt_st_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldis_indirect_index_disp: + extract_sfmt_st_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldis_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -3469,222 +3814,268 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, { FLD (in_abase) = f_abase; FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_offset: + extract_sfmt_stl_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_indirect_offset: + extract_sfmt_stl_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_indirect: + extract_sfmt_stl_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_indirect_index: + extract_sfmt_stl_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_disp: + extract_sfmt_stl_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_indirect_disp: + extract_sfmt_stl_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_index_disp: + extract_sfmt_stl_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldl_indirect_index_disp: + extract_sfmt_stl_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; @@ -3692,1590 +4083,251 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_offset: + extract_sfmt_stt_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_indirect_offset: + extract_sfmt_stt_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_indirect: + extract_sfmt_stt_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_indirect_index: + extract_sfmt_stt_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_disp: + extract_sfmt_stt_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_indirect_disp: + extract_sfmt_stt_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); + FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); + FLD (in_st_src) = f_srcdst; } #endif #undef FLD return idesc; } - extract_fmt_ldt_index_disp: + extract_sfmt_stt_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldt_indirect_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_LDA_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_offset) = f_offset; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_indirect_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_LDA_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_offset) = f_offset; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_indirect: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_indirect_index: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_indirect_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldq_indirect_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_LDA_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_dst) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "dst 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (out_dst) = f_srcdst; - FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1)); - FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2)); - FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3)); - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_offset) = f_offset; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_indirect_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_indirect_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_offset) = f_offset; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_indirect: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_indirect.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_indirect_index: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_indirect_index.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_indirect_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_indirect_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_st_indirect_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_offset) = f_offset; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_indirect_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_offset) = f_offset; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_indirect: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_indirect.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_indirect_index: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_indirect_index.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_indirect_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stob_indirect_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stob_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_offset) = f_offset; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_offset", "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_indirect_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_offset) = f_offset; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_indirect: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_indirect.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect", "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_indirect_index: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_indirect_index.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_disp", "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_indirect_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stos_indirect_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stos_indirect_index_disp", "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_offset) = f_offset; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_indirect_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_offset) = f_offset; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_indirect: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_indirect.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_indirect_index: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_indirect_index.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_indirect_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stl_indirect_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stl_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_offset) = f_offset; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_indirect_offset: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ - - EXTRACT_IFMT_ST_OFFSET_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_offset) = f_offset; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_indirect: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_indirect.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_indirect_index: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_indirect_index.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_INDIRECT_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_scale) = f_scale; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_index) = f_index; - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_indirect_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (i_abase) = & CPU (h_gr)[f_abase]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_abase) = f_abase; - FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1)); - FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2)); - FLD (in_st_src) = f_srcdst; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_stt_index_disp: - { - const IDESC *idesc = &i960base_insn_data[itype]; - CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ - - EXTRACT_IFMT_ST_DISP_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_srcdst) = f_srcdst; - FLD (f_optdisp) = f_optdisp; - FLD (f_scale) = f_scale; - FLD (i_index) = & CPU (h_gr)[f_index]; - FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5291,14 +4343,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stt_indirect_index_disp: + extract_sfmt_stt_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_ST_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; @@ -5307,7 +4370,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stt_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5324,20 +4387,22 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_offset: + extract_sfmt_stq_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_offset; - EXTRACT_IFMT_ST_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5353,21 +4418,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_indirect_offset: + extract_sfmt_stq_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f - EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_ST_OFFSET_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_indirect_offset", "f_srcdst 0x%x", 'x', f_srcdst, "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5384,20 +4453,22 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_indirect: + extract_sfmt_stq_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_indirect.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_srcdst; + UINT f_abase; - EXTRACT_IFMT_ST_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_indirect", "f_srcdst 0x%x", 'x', f_srcdst, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5414,14 +4485,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_indirect_index: + extract_sfmt_stq_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_indirect_index.f - EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_ST_INDIRECT_CODE + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; @@ -5429,7 +4506,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_indirect_index", "f_srcdst 0x%x", 'x', f_srcdst, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5447,20 +4524,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_disp: + extract_sfmt_stq_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_ST_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5476,21 +4558,28 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_indirect_disp: + extract_sfmt_stq_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_ST_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_indirect_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5507,14 +4596,23 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_index_disp: + extract_sfmt_stq_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_ST_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; @@ -5522,7 +4620,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_scale) = f_scale; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5539,14 +4637,25 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stq_indirect_index_disp: + extract_sfmt_stq_indirect_index_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f - EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_srcdst; + UINT f_abase; + UINT f_scale; + UINT f_index; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_ST_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_srcdst) = f_srcdst; @@ -5555,7 +4664,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; FLD (i_st_src) = & CPU (h_gr)[f_srcdst]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq_indirect_index_disp", "f_srcdst 0x%x", 'x', f_srcdst, "f_optdisp 0x%x", 'x', f_optdisp, "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, "st_src 0x%x", 'x', f_srcdst, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5573,21 +4682,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpobe_reg: + extract_sfmt_cmpobe_reg: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f - EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f + UINT f_br_src1; + UINT f_br_src2; + SI f_br_disp; - EXTRACT_IFMT_CMPOBE_REG_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_br_disp) = f_br_disp; FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobe_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpobe_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5601,21 +4713,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpobe_lit: + extract_sfmt_cmpobe_lit: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f - EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f + UINT f_br_src1; + UINT f_br_src2; + SI f_br_disp; - EXTRACT_IFMT_CMPOBE_LIT_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (f_br_src1) = f_br_src1; FLD (i_br_disp) = f_br_disp; FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobe_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpobe_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5628,21 +4743,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpobl_reg: + extract_sfmt_cmpobl_reg: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f - EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f + UINT f_br_src1; + UINT f_br_src2; + SI f_br_disp; - EXTRACT_IFMT_CMPOBE_REG_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_br_disp) = f_br_disp; FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobl_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpobl_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5656,21 +4774,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpobl_lit: + extract_sfmt_cmpobl_lit: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f - EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f + UINT f_br_src1; + UINT f_br_src2; + SI f_br_disp; - EXTRACT_IFMT_CMPOBE_LIT_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (f_br_src1) = f_br_src1; FLD (i_br_disp) = f_br_disp; FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpobl_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpobl_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5683,21 +4804,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bbc_reg: + extract_sfmt_bbc_reg: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f - EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f + UINT f_br_src1; + UINT f_br_src2; + SI f_br_disp; - EXTRACT_IFMT_CMPOBE_REG_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_br_disp) = f_br_disp; FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bbc_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bbc_reg", "br_disp 0x%x", 'x', f_br_disp, "br_src1 0x%x", 'x', f_br_src1, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5711,21 +4835,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bbc_lit: + extract_sfmt_bbc_lit: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f - EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f + UINT f_br_src1; + UINT f_br_src2; + SI f_br_disp; - EXTRACT_IFMT_CMPOBE_LIT_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); + f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (f_br_src1) = f_br_src1; FLD (i_br_disp) = f_br_disp; FLD (i_br_src2) = & CPU (h_gr)[f_br_src2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bbc_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bbc_lit", "f_br_src1 0x%x", 'x', f_br_src1, "br_disp 0x%x", 'x', f_br_disp, "br_src2 0x%x", 'x', f_br_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5738,19 +4865,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpi: + extract_sfmt_cmpi: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpi.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_src2) = & CPU (h_gr)[f_src2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5764,19 +4893,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpi1: + extract_sfmt_cmpi1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpi1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO1_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (i_src2) = & CPU (h_gr)[f_src2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5789,19 +4920,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpi2: + extract_sfmt_cmpi2: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpi2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src2) = f_src2; FLD (i_src1) = & CPU (h_gr)[f_src1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5814,19 +4947,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpi3: + extract_sfmt_cmpi3: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpi3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_src2) = f_src2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5838,19 +4973,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpo: + extract_sfmt_cmpo: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpo.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; FLD (i_src2) = & CPU (h_gr)[f_src2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5864,19 +5001,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpo1: + extract_sfmt_cmpo1: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpo1.f - EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul1.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO1_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (i_src2) = & CPU (h_gr)[f_src2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5889,19 +5028,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpo2: + extract_sfmt_cmpo2: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpo2.f - EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO2_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src2) = f_src2; FLD (i_src1) = & CPU (h_gr)[f_src1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5914,19 +5055,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpo3: + extract_sfmt_cmpo3: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_cmpo3.f - EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul3.f + UINT f_src2; + UINT f_src1; - EXTRACT_IFMT_MULO3_CODE + f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_src1) = f_src1; FLD (f_src2) = f_src2; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5938,18 +5081,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_testno_reg: + extract_sfmt_testno_reg: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_testno_reg.f - EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */ +#define FLD(f) abuf->fields.sfmt_testno_reg.f + UINT f_br_src1; - EXTRACT_IFMT_CMPOBE_REG_CODE + f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); /* Record the fields for the semantic handler. */ FLD (i_br_src1) = & CPU (h_gr)[f_br_src1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_testno_reg", "br_src1 0x%x", 'x', f_br_src1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_testno_reg", "br_src1 0x%x", 'x', f_br_src1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5962,19 +5105,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bno: + extract_sfmt_bno: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f - EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ +#define FLD(f) abuf->fields.sfmt_bno.f + SI f_ctrl_disp; - EXTRACT_IFMT_BNO_CODE + f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_ctrl_disp) = f_ctrl_disp; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bno", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bno", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -5986,19 +5128,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_b: + extract_sfmt_b: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_b.f - EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ +#define FLD(f) abuf->fields.sfmt_bno.f + SI f_ctrl_disp; - EXTRACT_IFMT_BNO_CODE + f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_ctrl_disp) = f_ctrl_disp; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_b", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b", "ctrl_disp 0x%x", 'x', f_ctrl_disp, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6010,20 +5151,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bx_indirect_offset: + extract_sfmt_bx_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6036,19 +5178,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bx_indirect: + extract_sfmt_bx_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (i_abase) = & CPU (h_gr)[f_abase]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6061,21 +5202,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bx_indirect_index: + extract_sfmt_bx_indirect_index: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_abase; + UINT f_scale; + UINT f_index; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); + f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (f_scale) = f_scale; FLD (i_abase) = & CPU (h_gr)[f_abase]; FLD (i_index) = & CPU (h_gr)[f_index]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bx_indirect_index", "f_scale 0x%x", 'x', f_scale, "abase 0x%x", 'x', f_abase, "index 0x%x", 'x', f_index, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6089,19 +5233,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bx_disp: + extract_sfmt_bx_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6113,20 +5259,24 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bx_indirect_disp: + extract_sfmt_bx_indirect_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f + UINT f_optdisp; + UINT f_abase; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; FLD (i_abase) = & CPU (h_gr)[f_abase]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bx_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bx_indirect_disp", "f_optdisp 0x%x", 'x', f_optdisp, "abase 0x%x", 'x', f_abase, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6139,19 +5289,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_callx_disp: + extract_sfmt_callx_disp: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f - EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_callx_disp.f + UINT f_optdisp; + /* Contents of trailing part of insn. */ + UINT word_1; - EXTRACT_IFMT_LDA_DISP_CODE + word_1 = GETIMEMUSI (current_cpu, pc + 4); + f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); /* Record the fields for the semantic handler. */ FLD (f_optdisp) = f_optdisp; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callx_disp", "f_optdisp 0x%x", 'x', f_optdisp, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6197,19 +5349,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_callx_indirect: + extract_sfmt_callx_indirect: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f - EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */ +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f + UINT f_abase; - EXTRACT_IFMT_LDA_INDIRECT_CODE + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); /* Record the fields for the semantic handler. */ FLD (i_abase) = & CPU (h_gr)[f_abase]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callx_indirect", "abase 0x%x", 'x', f_abase, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6256,20 +5407,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_callx_indirect_offset: + extract_sfmt_callx_indirect_offset: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f - EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */ +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f + UINT f_abase; + UINT f_offset; - EXTRACT_IFMT_LDA_OFFSET_CODE + f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); + f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); /* Record the fields for the semantic handler. */ FLD (f_offset) = f_offset; FLD (i_abase) = & CPU (h_gr)[f_abase]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_callx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callx_indirect_offset", "f_offset 0x%x", 'x', f_offset, "abase 0x%x", 'x', f_abase, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6316,18 +5468,15 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ret: + extract_sfmt_ret: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f - EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */ +#define FLD(f) abuf->fields.sfmt_callx_disp.f - EXTRACT_IFMT_BNO_CODE /* Record the fields for the semantic handler. */ - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ret", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ret", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6359,19 +5508,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_calls: + extract_sfmt_calls: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_calls.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.sfmt_emul2.f + UINT f_src1; - EXTRACT_IFMT_MULO_CODE + f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_src1]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_calls", "src1 0x%x", 'x', f_src1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_calls", "src1 0x%x", 'x', f_src1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6384,18 +5532,15 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_fmark: + extract_sfmt_fmark: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_MULO_CODE /* Record the fields for the semantic handler. */ - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_fmark", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmark", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -6407,17 +5552,15 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_flushreg: + extract_sfmt_flushreg: { const IDESC *idesc = &i960base_insn_data[itype]; CGEN_INSN_INT insn = base_insn; -#define FLD(f) abuf->fields.fmt_flushreg.f - EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */ +#define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_MULO_CODE /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_flushreg", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flushreg", (char *) 0)); #undef FLD return idesc; diff --git a/sim/i960/decode.h b/sim/i960/decode.h index 80fbde6..e88e027 100644 --- a/sim/i960/decode.h +++ b/sim/i960/decode.h @@ -29,6 +29,8 @@ extern const IDESC *i960base_decode (SIM_CPU *, IADDR, CGEN_INSN_INT, ARGBUF *); extern void i960base_init_idesc_table (SIM_CPU *); +extern void i960base_sem_init_idesc_table (SIM_CPU *); +extern void i960base_semf_init_idesc_table (SIM_CPU *); /* Enum declaration for instructions in cpu family i960base. */ typedef enum i960base_insn_type { @@ -109,326 +111,41 @@ typedef enum i960base_insn_type { , I960BASE_INSN_FLUSHREG, I960BASE_INSN_MAX } I960BASE_INSN_TYPE; -#if ! WITH_SEM_SWITCH_FULL -#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (i960base,_sem_,fn); -#else -#define SEMFULL(fn) -#endif - -#if ! WITH_SEM_SWITCH_FAST -#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (i960base,_semf_,fn); -#else -#define SEMFAST(fn) -#endif - -#define SEM(fn) SEMFULL (fn) SEMFAST (fn) - -/* The function version of the before/after handlers is always needed, - so we always want the SEMFULL declaration of them. */ -extern SEMANTIC_FN CONCAT3 (i960base,_sem_,x_before); -extern SEMANTIC_FN CONCAT3 (i960base,_sem_,x_after); - -SEM (x_invalid) -SEM (x_after) -SEM (x_before) -SEM (x_cti_chain) -SEM (x_chain) -SEM (x_begin) -SEM (mulo) -SEM (mulo1) -SEM (mulo2) -SEM (mulo3) -SEM (remo) -SEM (remo1) -SEM (remo2) -SEM (remo3) -SEM (divo) -SEM (divo1) -SEM (divo2) -SEM (divo3) -SEM (remi) -SEM (remi1) -SEM (remi2) -SEM (remi3) -SEM (divi) -SEM (divi1) -SEM (divi2) -SEM (divi3) -SEM (addo) -SEM (addo1) -SEM (addo2) -SEM (addo3) -SEM (subo) -SEM (subo1) -SEM (subo2) -SEM (subo3) -SEM (notbit) -SEM (notbit1) -SEM (notbit2) -SEM (notbit3) -SEM (and) -SEM (and1) -SEM (and2) -SEM (and3) -SEM (andnot) -SEM (andnot1) -SEM (andnot2) -SEM (andnot3) -SEM (setbit) -SEM (setbit1) -SEM (setbit2) -SEM (setbit3) -SEM (notand) -SEM (notand1) -SEM (notand2) -SEM (notand3) -SEM (xor) -SEM (xor1) -SEM (xor2) -SEM (xor3) -SEM (or) -SEM (or1) -SEM (or2) -SEM (or3) -SEM (nor) -SEM (nor1) -SEM (nor2) -SEM (nor3) -SEM (xnor) -SEM (xnor1) -SEM (xnor2) -SEM (xnor3) -SEM (not) -SEM (not1) -SEM (not2) -SEM (not3) -SEM (ornot) -SEM (ornot1) -SEM (ornot2) -SEM (ornot3) -SEM (clrbit) -SEM (clrbit1) -SEM (clrbit2) -SEM (clrbit3) -SEM (shlo) -SEM (shlo1) -SEM (shlo2) -SEM (shlo3) -SEM (shro) -SEM (shro1) -SEM (shro2) -SEM (shro3) -SEM (shli) -SEM (shli1) -SEM (shli2) -SEM (shli3) -SEM (shri) -SEM (shri1) -SEM (shri2) -SEM (shri3) -SEM (emul) -SEM (emul1) -SEM (emul2) -SEM (emul3) -SEM (mov) -SEM (mov1) -SEM (movl) -SEM (movl1) -SEM (movt) -SEM (movt1) -SEM (movq) -SEM (movq1) -SEM (modpc) -SEM (modac) -SEM (lda_offset) -SEM (lda_indirect_offset) -SEM (lda_indirect) -SEM (lda_indirect_index) -SEM (lda_disp) -SEM (lda_indirect_disp) -SEM (lda_index_disp) -SEM (lda_indirect_index_disp) -SEM (ld_offset) -SEM (ld_indirect_offset) -SEM (ld_indirect) -SEM (ld_indirect_index) -SEM (ld_disp) -SEM (ld_indirect_disp) -SEM (ld_index_disp) -SEM (ld_indirect_index_disp) -SEM (ldob_offset) -SEM (ldob_indirect_offset) -SEM (ldob_indirect) -SEM (ldob_indirect_index) -SEM (ldob_disp) -SEM (ldob_indirect_disp) -SEM (ldob_index_disp) -SEM (ldob_indirect_index_disp) -SEM (ldos_offset) -SEM (ldos_indirect_offset) -SEM (ldos_indirect) -SEM (ldos_indirect_index) -SEM (ldos_disp) -SEM (ldos_indirect_disp) -SEM (ldos_index_disp) -SEM (ldos_indirect_index_disp) -SEM (ldib_offset) -SEM (ldib_indirect_offset) -SEM (ldib_indirect) -SEM (ldib_indirect_index) -SEM (ldib_disp) -SEM (ldib_indirect_disp) -SEM (ldib_index_disp) -SEM (ldib_indirect_index_disp) -SEM (ldis_offset) -SEM (ldis_indirect_offset) -SEM (ldis_indirect) -SEM (ldis_indirect_index) -SEM (ldis_disp) -SEM (ldis_indirect_disp) -SEM (ldis_index_disp) -SEM (ldis_indirect_index_disp) -SEM (ldl_offset) -SEM (ldl_indirect_offset) -SEM (ldl_indirect) -SEM (ldl_indirect_index) -SEM (ldl_disp) -SEM (ldl_indirect_disp) -SEM (ldl_index_disp) -SEM (ldl_indirect_index_disp) -SEM (ldt_offset) -SEM (ldt_indirect_offset) -SEM (ldt_indirect) -SEM (ldt_indirect_index) -SEM (ldt_disp) -SEM (ldt_indirect_disp) -SEM (ldt_index_disp) -SEM (ldt_indirect_index_disp) -SEM (ldq_offset) -SEM (ldq_indirect_offset) -SEM (ldq_indirect) -SEM (ldq_indirect_index) -SEM (ldq_disp) -SEM (ldq_indirect_disp) -SEM (ldq_index_disp) -SEM (ldq_indirect_index_disp) -SEM (st_offset) -SEM (st_indirect_offset) -SEM (st_indirect) -SEM (st_indirect_index) -SEM (st_disp) -SEM (st_indirect_disp) -SEM (st_index_disp) -SEM (st_indirect_index_disp) -SEM (stob_offset) -SEM (stob_indirect_offset) -SEM (stob_indirect) -SEM (stob_indirect_index) -SEM (stob_disp) -SEM (stob_indirect_disp) -SEM (stob_index_disp) -SEM (stob_indirect_index_disp) -SEM (stos_offset) -SEM (stos_indirect_offset) -SEM (stos_indirect) -SEM (stos_indirect_index) -SEM (stos_disp) -SEM (stos_indirect_disp) -SEM (stos_index_disp) -SEM (stos_indirect_index_disp) -SEM (stl_offset) -SEM (stl_indirect_offset) -SEM (stl_indirect) -SEM (stl_indirect_index) -SEM (stl_disp) -SEM (stl_indirect_disp) -SEM (stl_index_disp) -SEM (stl_indirect_index_disp) -SEM (stt_offset) -SEM (stt_indirect_offset) -SEM (stt_indirect) -SEM (stt_indirect_index) -SEM (stt_disp) -SEM (stt_indirect_disp) -SEM (stt_index_disp) -SEM (stt_indirect_index_disp) -SEM (stq_offset) -SEM (stq_indirect_offset) -SEM (stq_indirect) -SEM (stq_indirect_index) -SEM (stq_disp) -SEM (stq_indirect_disp) -SEM (stq_index_disp) -SEM (stq_indirect_index_disp) -SEM (cmpobe_reg) -SEM (cmpobe_lit) -SEM (cmpobne_reg) -SEM (cmpobne_lit) -SEM (cmpobl_reg) -SEM (cmpobl_lit) -SEM (cmpoble_reg) -SEM (cmpoble_lit) -SEM (cmpobg_reg) -SEM (cmpobg_lit) -SEM (cmpobge_reg) -SEM (cmpobge_lit) -SEM (cmpibe_reg) -SEM (cmpibe_lit) -SEM (cmpibne_reg) -SEM (cmpibne_lit) -SEM (cmpibl_reg) -SEM (cmpibl_lit) -SEM (cmpible_reg) -SEM (cmpible_lit) -SEM (cmpibg_reg) -SEM (cmpibg_lit) -SEM (cmpibge_reg) -SEM (cmpibge_lit) -SEM (bbc_reg) -SEM (bbc_lit) -SEM (bbs_reg) -SEM (bbs_lit) -SEM (cmpi) -SEM (cmpi1) -SEM (cmpi2) -SEM (cmpi3) -SEM (cmpo) -SEM (cmpo1) -SEM (cmpo2) -SEM (cmpo3) -SEM (testno_reg) -SEM (testg_reg) -SEM (teste_reg) -SEM (testge_reg) -SEM (testl_reg) -SEM (testne_reg) -SEM (testle_reg) -SEM (testo_reg) -SEM (bno) -SEM (bg) -SEM (be) -SEM (bge) -SEM (bl) -SEM (bne) -SEM (ble) -SEM (bo) -SEM (b) -SEM (bx_indirect_offset) -SEM (bx_indirect) -SEM (bx_indirect_index) -SEM (bx_disp) -SEM (bx_indirect_disp) -SEM (callx_disp) -SEM (callx_indirect) -SEM (callx_indirect_offset) -SEM (ret) -SEM (calls) -SEM (fmark) -SEM (flushreg) - -#undef SEMFULL -#undef SEMFAST -#undef SEM +/* Enum declaration for semantic formats in cpu family i960base. */ +typedef enum i960base_sfmt_type { + I960BASE_SFMT_EMPTY, I960BASE_SFMT_MULO, I960BASE_SFMT_MULO1, I960BASE_SFMT_MULO2 + , I960BASE_SFMT_MULO3, I960BASE_SFMT_NOTBIT, I960BASE_SFMT_NOTBIT1, I960BASE_SFMT_NOTBIT2 + , I960BASE_SFMT_NOTBIT3, I960BASE_SFMT_NOT, I960BASE_SFMT_NOT1, I960BASE_SFMT_SHLO + , I960BASE_SFMT_SHLO1, I960BASE_SFMT_SHLO2, I960BASE_SFMT_SHLO3, I960BASE_SFMT_EMUL + , I960BASE_SFMT_EMUL1, I960BASE_SFMT_EMUL2, I960BASE_SFMT_EMUL3, I960BASE_SFMT_MOVL + , I960BASE_SFMT_MOVL1, I960BASE_SFMT_MOVT, I960BASE_SFMT_MOVT1, I960BASE_SFMT_MOVQ + , I960BASE_SFMT_MOVQ1, I960BASE_SFMT_MODPC, I960BASE_SFMT_LDA_OFFSET, I960BASE_SFMT_LDA_INDIRECT_OFFSET + , I960BASE_SFMT_LDA_INDIRECT, I960BASE_SFMT_LDA_INDIRECT_INDEX, I960BASE_SFMT_LDA_DISP, I960BASE_SFMT_LDA_INDIRECT_DISP + , I960BASE_SFMT_LDA_INDEX_DISP, I960BASE_SFMT_LDA_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET + , I960BASE_SFMT_LD_INDIRECT, I960BASE_SFMT_LD_INDIRECT_INDEX, I960BASE_SFMT_LD_DISP, I960BASE_SFMT_LD_INDIRECT_DISP + , I960BASE_SFMT_LD_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDL_OFFSET, I960BASE_SFMT_LDL_INDIRECT_OFFSET + , I960BASE_SFMT_LDL_INDIRECT, I960BASE_SFMT_LDL_INDIRECT_INDEX, I960BASE_SFMT_LDL_DISP, I960BASE_SFMT_LDL_INDIRECT_DISP + , I960BASE_SFMT_LDL_INDEX_DISP, I960BASE_SFMT_LDL_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDT_OFFSET, I960BASE_SFMT_LDT_INDIRECT_OFFSET + , I960BASE_SFMT_LDT_INDIRECT, I960BASE_SFMT_LDT_INDIRECT_INDEX, I960BASE_SFMT_LDT_DISP, I960BASE_SFMT_LDT_INDIRECT_DISP + , I960BASE_SFMT_LDT_INDEX_DISP, I960BASE_SFMT_LDT_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDQ_OFFSET, I960BASE_SFMT_LDQ_INDIRECT_OFFSET + , I960BASE_SFMT_LDQ_INDIRECT, I960BASE_SFMT_LDQ_INDIRECT_INDEX, I960BASE_SFMT_LDQ_DISP, I960BASE_SFMT_LDQ_INDIRECT_DISP + , I960BASE_SFMT_LDQ_INDEX_DISP, I960BASE_SFMT_LDQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_ST_OFFSET, I960BASE_SFMT_ST_INDIRECT_OFFSET + , I960BASE_SFMT_ST_INDIRECT, I960BASE_SFMT_ST_INDIRECT_INDEX, I960BASE_SFMT_ST_DISP, I960BASE_SFMT_ST_INDIRECT_DISP + , I960BASE_SFMT_ST_INDEX_DISP, I960BASE_SFMT_ST_INDIRECT_INDEX_DISP, I960BASE_SFMT_STL_OFFSET, I960BASE_SFMT_STL_INDIRECT_OFFSET + , I960BASE_SFMT_STL_INDIRECT, I960BASE_SFMT_STL_INDIRECT_INDEX, I960BASE_SFMT_STL_DISP, I960BASE_SFMT_STL_INDIRECT_DISP + , I960BASE_SFMT_STL_INDEX_DISP, I960BASE_SFMT_STL_INDIRECT_INDEX_DISP, I960BASE_SFMT_STT_OFFSET, I960BASE_SFMT_STT_INDIRECT_OFFSET + , I960BASE_SFMT_STT_INDIRECT, I960BASE_SFMT_STT_INDIRECT_INDEX, I960BASE_SFMT_STT_DISP, I960BASE_SFMT_STT_INDIRECT_DISP + , I960BASE_SFMT_STT_INDEX_DISP, I960BASE_SFMT_STT_INDIRECT_INDEX_DISP, I960BASE_SFMT_STQ_OFFSET, I960BASE_SFMT_STQ_INDIRECT_OFFSET + , I960BASE_SFMT_STQ_INDIRECT, I960BASE_SFMT_STQ_INDIRECT_INDEX, I960BASE_SFMT_STQ_DISP, I960BASE_SFMT_STQ_INDIRECT_DISP + , I960BASE_SFMT_STQ_INDEX_DISP, I960BASE_SFMT_STQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_CMPOBE_REG, I960BASE_SFMT_CMPOBE_LIT + , I960BASE_SFMT_CMPOBL_REG, I960BASE_SFMT_CMPOBL_LIT, I960BASE_SFMT_BBC_REG, I960BASE_SFMT_BBC_LIT + , I960BASE_SFMT_CMPI, I960BASE_SFMT_CMPI1, I960BASE_SFMT_CMPI2, I960BASE_SFMT_CMPI3 + , I960BASE_SFMT_CMPO, I960BASE_SFMT_CMPO1, I960BASE_SFMT_CMPO2, I960BASE_SFMT_CMPO3 + , I960BASE_SFMT_TESTNO_REG, I960BASE_SFMT_BNO, I960BASE_SFMT_B, I960BASE_SFMT_BX_INDIRECT_OFFSET + , I960BASE_SFMT_BX_INDIRECT, I960BASE_SFMT_BX_INDIRECT_INDEX, I960BASE_SFMT_BX_DISP, I960BASE_SFMT_BX_INDIRECT_DISP + , I960BASE_SFMT_CALLX_DISP, I960BASE_SFMT_CALLX_INDIRECT, I960BASE_SFMT_CALLX_INDIRECT_OFFSET, I960BASE_SFMT_RET + , I960BASE_SFMT_CALLS, I960BASE_SFMT_FMARK, I960BASE_SFMT_FLUSHREG +} I960BASE_SFMT_TYPE; /* Function unit handlers (user written). */ diff --git a/sim/i960/i960-desc.h b/sim/i960/i960-desc.h index 75b3d63..40ca227 100644 --- a/sim/i960/i960-desc.h +++ b/sim/i960/i960-desc.h @@ -35,6 +35,9 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INSN_LSB0_P 0 +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + /* Maximum size of any insn (in bytes). */ #define CGEN_MAX_INSN_SIZE 8 diff --git a/sim/i960/model.c b/sim/i960/model.c index 8881f3e..600d9ea 100644 --- a/sim/i960/model.c +++ b/sim/i960/model.c @@ -37,7 +37,7 @@ with this program; if not, write to the Free Software Foundation, Inc., static int model_i960KA_mulo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -53,7 +53,7 @@ model_i960KA_mulo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_mulo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -69,7 +69,7 @@ model_i960KA_mulo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_mulo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -85,7 +85,7 @@ model_i960KA_mulo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_mulo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -101,7 +101,7 @@ model_i960KA_mulo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -117,7 +117,7 @@ model_i960KA_remo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -133,7 +133,7 @@ model_i960KA_remo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -149,7 +149,7 @@ model_i960KA_remo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -165,7 +165,7 @@ model_i960KA_remo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -181,7 +181,7 @@ model_i960KA_divo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -197,7 +197,7 @@ model_i960KA_divo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -213,7 +213,7 @@ model_i960KA_divo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -229,7 +229,7 @@ model_i960KA_divo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -245,7 +245,7 @@ model_i960KA_remi (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remi1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -261,7 +261,7 @@ model_i960KA_remi1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remi2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -277,7 +277,7 @@ model_i960KA_remi2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_remi3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -293,7 +293,7 @@ model_i960KA_remi3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -309,7 +309,7 @@ model_i960KA_divi (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divi1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -325,7 +325,7 @@ model_i960KA_divi1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divi2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -341,7 +341,7 @@ model_i960KA_divi2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_divi3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -357,7 +357,7 @@ model_i960KA_divi3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_addo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -373,7 +373,7 @@ model_i960KA_addo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_addo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -389,7 +389,7 @@ model_i960KA_addo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_addo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -405,7 +405,7 @@ model_i960KA_addo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_addo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -421,7 +421,7 @@ model_i960KA_addo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_subo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -437,7 +437,7 @@ model_i960KA_subo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_subo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -453,7 +453,7 @@ model_i960KA_subo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_subo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -469,7 +469,7 @@ model_i960KA_subo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_subo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -485,7 +485,7 @@ model_i960KA_subo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notbit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -501,7 +501,7 @@ model_i960KA_notbit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notbit1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -517,7 +517,7 @@ model_i960KA_notbit1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notbit2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -533,7 +533,7 @@ model_i960KA_notbit2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notbit3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -549,7 +549,7 @@ model_i960KA_notbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_and (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -565,7 +565,7 @@ model_i960KA_and (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_and1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -581,7 +581,7 @@ model_i960KA_and1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_and2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -597,7 +597,7 @@ model_i960KA_and2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_and3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -613,7 +613,7 @@ model_i960KA_and3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_andnot (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -629,7 +629,7 @@ model_i960KA_andnot (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_andnot1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -645,7 +645,7 @@ model_i960KA_andnot1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_andnot2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -661,7 +661,7 @@ model_i960KA_andnot2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_andnot3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -677,7 +677,7 @@ model_i960KA_andnot3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_setbit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -693,7 +693,7 @@ model_i960KA_setbit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_setbit1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -709,7 +709,7 @@ model_i960KA_setbit1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_setbit2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -725,7 +725,7 @@ model_i960KA_setbit2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_setbit3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -741,7 +741,7 @@ model_i960KA_setbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notand (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -757,7 +757,7 @@ model_i960KA_notand (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notand1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -773,7 +773,7 @@ model_i960KA_notand1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notand2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -789,7 +789,7 @@ model_i960KA_notand2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_notand3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -805,7 +805,7 @@ model_i960KA_notand3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -821,7 +821,7 @@ model_i960KA_xor (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xor1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -837,7 +837,7 @@ model_i960KA_xor1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xor2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -853,7 +853,7 @@ model_i960KA_xor2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -869,7 +869,7 @@ model_i960KA_xor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_or (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -885,7 +885,7 @@ model_i960KA_or (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_or1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -901,7 +901,7 @@ model_i960KA_or1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_or2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -917,7 +917,7 @@ model_i960KA_or2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_or3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -933,7 +933,7 @@ model_i960KA_or3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_nor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -949,7 +949,7 @@ model_i960KA_nor (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_nor1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -965,7 +965,7 @@ model_i960KA_nor1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_nor2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -981,7 +981,7 @@ model_i960KA_nor2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_nor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -997,7 +997,7 @@ model_i960KA_nor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xnor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1013,7 +1013,7 @@ model_i960KA_xnor (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xnor1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1029,7 +1029,7 @@ model_i960KA_xnor1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xnor2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1045,7 +1045,7 @@ model_i960KA_xnor2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_xnor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1061,7 +1061,7 @@ model_i960KA_xnor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_not (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1077,7 +1077,7 @@ model_i960KA_not (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_not1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not1.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1093,7 +1093,7 @@ model_i960KA_not1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_not2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1109,7 +1109,7 @@ model_i960KA_not2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_not3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1125,7 +1125,7 @@ model_i960KA_not3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ornot (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1141,7 +1141,7 @@ model_i960KA_ornot (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ornot1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1157,7 +1157,7 @@ model_i960KA_ornot1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ornot2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1173,7 +1173,7 @@ model_i960KA_ornot2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ornot3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1189,7 +1189,7 @@ model_i960KA_ornot3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_clrbit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1205,7 +1205,7 @@ model_i960KA_clrbit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_clrbit1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1221,7 +1221,7 @@ model_i960KA_clrbit1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_clrbit2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1237,7 +1237,7 @@ model_i960KA_clrbit2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1253,7 +1253,7 @@ model_i960KA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1269,7 +1269,7 @@ model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1285,7 +1285,7 @@ model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1301,7 +1301,7 @@ model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1317,7 +1317,7 @@ model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1333,7 +1333,7 @@ model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1349,7 +1349,7 @@ model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1365,7 +1365,7 @@ model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1381,7 +1381,7 @@ model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1397,7 +1397,7 @@ model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1413,7 +1413,7 @@ model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1429,7 +1429,7 @@ model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1445,7 +1445,7 @@ model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1461,7 +1461,7 @@ model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1477,7 +1477,7 @@ model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1493,7 +1493,7 @@ model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_shri3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1509,7 +1509,7 @@ model_i960KA_shri3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_emul (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1525,7 +1525,7 @@ model_i960KA_emul (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_emul1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1541,7 +1541,7 @@ model_i960KA_emul1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_emul2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1557,7 +1557,7 @@ model_i960KA_emul2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_emul3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1573,7 +1573,7 @@ model_i960KA_emul3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_mov (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1589,7 +1589,7 @@ model_i960KA_mov (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_mov1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1605,7 +1605,7 @@ model_i960KA_mov1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_movl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movl.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1621,7 +1621,7 @@ model_i960KA_movl (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_movl1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movl1.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1637,7 +1637,7 @@ model_i960KA_movl1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_movt (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movt.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1653,7 +1653,7 @@ model_i960KA_movt (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_movt1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movt1.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1669,7 +1669,7 @@ model_i960KA_movt1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_movq (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movq.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1685,7 +1685,7 @@ model_i960KA_movq (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_movq1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movq1.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1701,7 +1701,7 @@ model_i960KA_movq1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_modpc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1717,7 +1717,7 @@ model_i960KA_modpc (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_modac (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1733,7 +1733,7 @@ model_i960KA_modac (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1749,7 +1749,7 @@ model_i960KA_lda_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1765,7 +1765,7 @@ model_i960KA_lda_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1781,7 +1781,7 @@ model_i960KA_lda_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1797,7 +1797,7 @@ model_i960KA_lda_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1813,7 +1813,7 @@ model_i960KA_lda_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1829,7 +1829,7 @@ model_i960KA_lda_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1845,7 +1845,7 @@ model_i960KA_lda_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_lda_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1861,7 +1861,7 @@ model_i960KA_lda_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1877,7 +1877,7 @@ model_i960KA_ld_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1893,7 +1893,7 @@ model_i960KA_ld_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1909,7 +1909,7 @@ model_i960KA_ld_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1925,7 +1925,7 @@ model_i960KA_ld_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1941,7 +1941,7 @@ model_i960KA_ld_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1957,7 +1957,7 @@ model_i960KA_ld_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1973,7 +1973,7 @@ model_i960KA_ld_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ld_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1989,7 +1989,7 @@ model_i960KA_ld_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2005,7 +2005,7 @@ model_i960KA_ldob_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2021,7 +2021,7 @@ model_i960KA_ldob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2037,7 +2037,7 @@ model_i960KA_ldob_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2053,7 +2053,7 @@ model_i960KA_ldob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2069,7 +2069,7 @@ model_i960KA_ldob_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2085,7 +2085,7 @@ model_i960KA_ldob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2101,7 +2101,7 @@ model_i960KA_ldob_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2117,7 +2117,7 @@ model_i960KA_ldob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2133,7 +2133,7 @@ model_i960KA_ldos_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2149,7 +2149,7 @@ model_i960KA_ldos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2165,7 +2165,7 @@ model_i960KA_ldos_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2181,7 +2181,7 @@ model_i960KA_ldos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2197,7 +2197,7 @@ model_i960KA_ldos_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2213,7 +2213,7 @@ model_i960KA_ldos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2229,7 +2229,7 @@ model_i960KA_ldos_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2245,7 +2245,7 @@ model_i960KA_ldos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2261,7 +2261,7 @@ model_i960KA_ldib_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2277,7 +2277,7 @@ model_i960KA_ldib_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2293,7 +2293,7 @@ model_i960KA_ldib_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2309,7 +2309,7 @@ model_i960KA_ldib_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2325,7 +2325,7 @@ model_i960KA_ldib_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2341,7 +2341,7 @@ model_i960KA_ldib_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2357,7 +2357,7 @@ model_i960KA_ldib_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldib_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2373,7 +2373,7 @@ model_i960KA_ldib_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2389,7 +2389,7 @@ model_i960KA_ldis_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2405,7 +2405,7 @@ model_i960KA_ldis_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2421,7 +2421,7 @@ model_i960KA_ldis_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2437,7 +2437,7 @@ model_i960KA_ldis_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2453,7 +2453,7 @@ model_i960KA_ldis_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2469,7 +2469,7 @@ model_i960KA_ldis_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2485,7 +2485,7 @@ model_i960KA_ldis_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldis_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2501,7 +2501,7 @@ model_i960KA_ldis_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2517,7 +2517,7 @@ model_i960KA_ldl_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2533,7 +2533,7 @@ model_i960KA_ldl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2549,7 +2549,7 @@ model_i960KA_ldl_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2565,7 +2565,7 @@ model_i960KA_ldl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2581,7 +2581,7 @@ model_i960KA_ldl_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2597,7 +2597,7 @@ model_i960KA_ldl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2613,7 +2613,7 @@ model_i960KA_ldl_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2629,7 +2629,7 @@ model_i960KA_ldl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2645,7 +2645,7 @@ model_i960KA_ldt_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2661,7 +2661,7 @@ model_i960KA_ldt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2677,7 +2677,7 @@ model_i960KA_ldt_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2693,7 +2693,7 @@ model_i960KA_ldt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2709,7 +2709,7 @@ model_i960KA_ldt_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2725,7 +2725,7 @@ model_i960KA_ldt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2741,7 +2741,7 @@ model_i960KA_ldt_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2757,7 +2757,7 @@ model_i960KA_ldt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2773,7 +2773,7 @@ model_i960KA_ldq_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2789,7 +2789,7 @@ model_i960KA_ldq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2805,7 +2805,7 @@ model_i960KA_ldq_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2821,7 +2821,7 @@ model_i960KA_ldq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2837,7 +2837,7 @@ model_i960KA_ldq_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2853,7 +2853,7 @@ model_i960KA_ldq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2869,7 +2869,7 @@ model_i960KA_ldq_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ldq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2885,7 +2885,7 @@ model_i960KA_ldq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2901,7 +2901,7 @@ model_i960KA_st_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2917,7 +2917,7 @@ model_i960KA_st_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2933,7 +2933,7 @@ model_i960KA_st_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2949,7 +2949,7 @@ model_i960KA_st_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2965,7 +2965,7 @@ model_i960KA_st_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2981,7 +2981,7 @@ model_i960KA_st_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2997,7 +2997,7 @@ model_i960KA_st_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_st_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3013,7 +3013,7 @@ model_i960KA_st_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3029,7 +3029,7 @@ model_i960KA_stob_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3045,7 +3045,7 @@ model_i960KA_stob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3061,7 +3061,7 @@ model_i960KA_stob_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3077,7 +3077,7 @@ model_i960KA_stob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3093,7 +3093,7 @@ model_i960KA_stob_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3109,7 +3109,7 @@ model_i960KA_stob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3125,7 +3125,7 @@ model_i960KA_stob_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3141,7 +3141,7 @@ model_i960KA_stob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3157,7 +3157,7 @@ model_i960KA_stos_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3173,7 +3173,7 @@ model_i960KA_stos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3189,7 +3189,7 @@ model_i960KA_stos_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3205,7 +3205,7 @@ model_i960KA_stos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3221,7 +3221,7 @@ model_i960KA_stos_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3237,7 +3237,7 @@ model_i960KA_stos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3253,7 +3253,7 @@ model_i960KA_stos_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3269,7 +3269,7 @@ model_i960KA_stos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3285,7 +3285,7 @@ model_i960KA_stl_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3301,7 +3301,7 @@ model_i960KA_stl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3317,7 +3317,7 @@ model_i960KA_stl_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3333,7 +3333,7 @@ model_i960KA_stl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3349,7 +3349,7 @@ model_i960KA_stl_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3365,7 +3365,7 @@ model_i960KA_stl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3381,7 +3381,7 @@ model_i960KA_stl_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3397,7 +3397,7 @@ model_i960KA_stl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3413,7 +3413,7 @@ model_i960KA_stt_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3429,7 +3429,7 @@ model_i960KA_stt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3445,7 +3445,7 @@ model_i960KA_stt_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3461,7 +3461,7 @@ model_i960KA_stt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3477,7 +3477,7 @@ model_i960KA_stt_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3493,7 +3493,7 @@ model_i960KA_stt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3509,7 +3509,7 @@ model_i960KA_stt_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3525,7 +3525,7 @@ model_i960KA_stt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3541,7 +3541,7 @@ model_i960KA_stq_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3557,7 +3557,7 @@ model_i960KA_stq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3573,7 +3573,7 @@ model_i960KA_stq_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3589,7 +3589,7 @@ model_i960KA_stq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3605,7 +3605,7 @@ model_i960KA_stq_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3621,7 +3621,7 @@ model_i960KA_stq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3637,7 +3637,7 @@ model_i960KA_stq_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_stq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3653,7 +3653,7 @@ model_i960KA_stq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobe_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3669,7 +3669,7 @@ model_i960KA_cmpobe_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobe_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3685,7 +3685,7 @@ model_i960KA_cmpobe_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobne_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3701,7 +3701,7 @@ model_i960KA_cmpobne_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobne_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3717,7 +3717,7 @@ model_i960KA_cmpobne_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobl_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3733,7 +3733,7 @@ model_i960KA_cmpobl_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobl_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3749,7 +3749,7 @@ model_i960KA_cmpobl_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpoble_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3765,7 +3765,7 @@ model_i960KA_cmpoble_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpoble_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3781,7 +3781,7 @@ model_i960KA_cmpoble_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobg_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3797,7 +3797,7 @@ model_i960KA_cmpobg_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobg_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3813,7 +3813,7 @@ model_i960KA_cmpobg_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobge_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3829,7 +3829,7 @@ model_i960KA_cmpobge_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpobge_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3845,7 +3845,7 @@ model_i960KA_cmpobge_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibe_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3861,7 +3861,7 @@ model_i960KA_cmpibe_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibe_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3877,7 +3877,7 @@ model_i960KA_cmpibe_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibne_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3893,7 +3893,7 @@ model_i960KA_cmpibne_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibne_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3909,7 +3909,7 @@ model_i960KA_cmpibne_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibl_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3925,7 +3925,7 @@ model_i960KA_cmpibl_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibl_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3941,7 +3941,7 @@ model_i960KA_cmpibl_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpible_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3957,7 +3957,7 @@ model_i960KA_cmpible_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpible_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3973,7 +3973,7 @@ model_i960KA_cmpible_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibg_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3989,7 +3989,7 @@ model_i960KA_cmpibg_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibg_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4005,7 +4005,7 @@ model_i960KA_cmpibg_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibge_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4021,7 +4021,7 @@ model_i960KA_cmpibge_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpibge_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4037,7 +4037,7 @@ model_i960KA_cmpibge_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bbc_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4053,7 +4053,7 @@ model_i960KA_bbc_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bbc_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4069,7 +4069,7 @@ model_i960KA_bbc_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bbs_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4085,7 +4085,7 @@ model_i960KA_bbs_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bbs_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4101,7 +4101,7 @@ model_i960KA_bbs_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4117,7 +4117,7 @@ model_i960KA_cmpi (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpi1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4133,7 +4133,7 @@ model_i960KA_cmpi1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpi2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4149,7 +4149,7 @@ model_i960KA_cmpi2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpi3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4165,7 +4165,7 @@ model_i960KA_cmpi3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4181,7 +4181,7 @@ model_i960KA_cmpo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4197,7 +4197,7 @@ model_i960KA_cmpo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4213,7 +4213,7 @@ model_i960KA_cmpo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_cmpo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4229,7 +4229,7 @@ model_i960KA_cmpo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testno_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4245,7 +4245,7 @@ model_i960KA_testno_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testg_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4261,7 +4261,7 @@ model_i960KA_testg_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_teste_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4277,7 +4277,7 @@ model_i960KA_teste_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testge_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4293,7 +4293,7 @@ model_i960KA_testge_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testl_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4309,7 +4309,7 @@ model_i960KA_testl_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testne_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4325,7 +4325,7 @@ model_i960KA_testne_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testle_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4341,7 +4341,7 @@ model_i960KA_testle_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_testo_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4357,7 +4357,7 @@ model_i960KA_testo_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bno (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4373,7 +4373,7 @@ model_i960KA_bno (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4389,7 +4389,7 @@ model_i960KA_bg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_be (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4405,7 +4405,7 @@ model_i960KA_be (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bge (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4421,7 +4421,7 @@ model_i960KA_bge (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4437,7 +4437,7 @@ model_i960KA_bl (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bne (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4453,7 +4453,7 @@ model_i960KA_bne (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ble (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4469,7 +4469,7 @@ model_i960KA_ble (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4485,7 +4485,7 @@ model_i960KA_bo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_b (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_b.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4501,7 +4501,7 @@ model_i960KA_b (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4517,7 +4517,7 @@ model_i960KA_bx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bx_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4533,7 +4533,7 @@ model_i960KA_bx_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bx_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4549,7 +4549,7 @@ model_i960KA_bx_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bx_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4565,7 +4565,7 @@ model_i960KA_bx_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_bx_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4581,7 +4581,7 @@ model_i960KA_bx_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_callx_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4597,7 +4597,7 @@ model_i960KA_callx_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_callx_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4613,7 +4613,7 @@ model_i960KA_callx_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_callx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4629,7 +4629,7 @@ model_i960KA_callx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_ret (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4645,7 +4645,7 @@ model_i960KA_ret (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_calls (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_calls.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4661,7 +4661,7 @@ model_i960KA_calls (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_fmark (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4677,7 +4677,7 @@ model_i960KA_fmark (SIM_CPU *current_cpu, void *sem_arg) static int model_i960KA_flushreg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_flushreg.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4693,7 +4693,7 @@ model_i960KA_flushreg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_mulo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4709,7 +4709,7 @@ model_i960CA_mulo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_mulo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4725,7 +4725,7 @@ model_i960CA_mulo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_mulo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4741,7 +4741,7 @@ model_i960CA_mulo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_mulo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4757,7 +4757,7 @@ model_i960CA_mulo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4773,7 +4773,7 @@ model_i960CA_remo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4789,7 +4789,7 @@ model_i960CA_remo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4805,7 +4805,7 @@ model_i960CA_remo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4821,7 +4821,7 @@ model_i960CA_remo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4837,7 +4837,7 @@ model_i960CA_divo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4853,7 +4853,7 @@ model_i960CA_divo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4869,7 +4869,7 @@ model_i960CA_divo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4885,7 +4885,7 @@ model_i960CA_divo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4901,7 +4901,7 @@ model_i960CA_remi (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remi1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4917,7 +4917,7 @@ model_i960CA_remi1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remi2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4933,7 +4933,7 @@ model_i960CA_remi2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_remi3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4949,7 +4949,7 @@ model_i960CA_remi3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4965,7 +4965,7 @@ model_i960CA_divi (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divi1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4981,7 +4981,7 @@ model_i960CA_divi1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divi2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -4997,7 +4997,7 @@ model_i960CA_divi2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_divi3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5013,7 +5013,7 @@ model_i960CA_divi3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_addo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5029,7 +5029,7 @@ model_i960CA_addo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_addo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5045,7 +5045,7 @@ model_i960CA_addo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_addo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5061,7 +5061,7 @@ model_i960CA_addo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_addo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5077,7 +5077,7 @@ model_i960CA_addo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_subo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5093,7 +5093,7 @@ model_i960CA_subo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_subo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5109,7 +5109,7 @@ model_i960CA_subo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_subo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5125,7 +5125,7 @@ model_i960CA_subo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_subo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5141,7 +5141,7 @@ model_i960CA_subo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notbit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5157,7 +5157,7 @@ model_i960CA_notbit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notbit1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5173,7 +5173,7 @@ model_i960CA_notbit1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notbit2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5189,7 +5189,7 @@ model_i960CA_notbit2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notbit3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5205,7 +5205,7 @@ model_i960CA_notbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_and (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5221,7 +5221,7 @@ model_i960CA_and (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_and1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5237,7 +5237,7 @@ model_i960CA_and1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_and2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5253,7 +5253,7 @@ model_i960CA_and2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_and3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5269,7 +5269,7 @@ model_i960CA_and3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_andnot (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5285,7 +5285,7 @@ model_i960CA_andnot (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_andnot1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5301,7 +5301,7 @@ model_i960CA_andnot1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_andnot2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5317,7 +5317,7 @@ model_i960CA_andnot2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_andnot3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5333,7 +5333,7 @@ model_i960CA_andnot3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_setbit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5349,7 +5349,7 @@ model_i960CA_setbit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_setbit1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5365,7 +5365,7 @@ model_i960CA_setbit1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_setbit2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5381,7 +5381,7 @@ model_i960CA_setbit2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_setbit3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5397,7 +5397,7 @@ model_i960CA_setbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notand (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5413,7 +5413,7 @@ model_i960CA_notand (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notand1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5429,7 +5429,7 @@ model_i960CA_notand1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notand2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5445,7 +5445,7 @@ model_i960CA_notand2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_notand3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5461,7 +5461,7 @@ model_i960CA_notand3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5477,7 +5477,7 @@ model_i960CA_xor (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xor1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5493,7 +5493,7 @@ model_i960CA_xor1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xor2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5509,7 +5509,7 @@ model_i960CA_xor2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5525,7 +5525,7 @@ model_i960CA_xor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_or (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5541,7 +5541,7 @@ model_i960CA_or (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_or1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5557,7 +5557,7 @@ model_i960CA_or1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_or2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5573,7 +5573,7 @@ model_i960CA_or2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_or3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5589,7 +5589,7 @@ model_i960CA_or3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_nor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5605,7 +5605,7 @@ model_i960CA_nor (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_nor1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5621,7 +5621,7 @@ model_i960CA_nor1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_nor2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5637,7 +5637,7 @@ model_i960CA_nor2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_nor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5653,7 +5653,7 @@ model_i960CA_nor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xnor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5669,7 +5669,7 @@ model_i960CA_xnor (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xnor1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5685,7 +5685,7 @@ model_i960CA_xnor1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xnor2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5701,7 +5701,7 @@ model_i960CA_xnor2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_xnor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5717,7 +5717,7 @@ model_i960CA_xnor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_not (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5733,7 +5733,7 @@ model_i960CA_not (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_not1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not1.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5749,7 +5749,7 @@ model_i960CA_not1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_not2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5765,7 +5765,7 @@ model_i960CA_not2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_not3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5781,7 +5781,7 @@ model_i960CA_not3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ornot (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5797,7 +5797,7 @@ model_i960CA_ornot (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ornot1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5813,7 +5813,7 @@ model_i960CA_ornot1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ornot2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5829,7 +5829,7 @@ model_i960CA_ornot2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ornot3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5845,7 +5845,7 @@ model_i960CA_ornot3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_clrbit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5861,7 +5861,7 @@ model_i960CA_clrbit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_clrbit1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5877,7 +5877,7 @@ model_i960CA_clrbit1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_clrbit2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5893,7 +5893,7 @@ model_i960CA_clrbit2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5909,7 +5909,7 @@ model_i960CA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5925,7 +5925,7 @@ model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5941,7 +5941,7 @@ model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5957,7 +5957,7 @@ model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5973,7 +5973,7 @@ model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -5989,7 +5989,7 @@ model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6005,7 +6005,7 @@ model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6021,7 +6021,7 @@ model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6037,7 +6037,7 @@ model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6053,7 +6053,7 @@ model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6069,7 +6069,7 @@ model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6085,7 +6085,7 @@ model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6101,7 +6101,7 @@ model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6117,7 +6117,7 @@ model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6133,7 +6133,7 @@ model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6149,7 +6149,7 @@ model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_shri3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6165,7 +6165,7 @@ model_i960CA_shri3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_emul (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6181,7 +6181,7 @@ model_i960CA_emul (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_emul1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6197,7 +6197,7 @@ model_i960CA_emul1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_emul2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6213,7 +6213,7 @@ model_i960CA_emul2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_emul3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_emul3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6229,7 +6229,7 @@ model_i960CA_emul3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_mov (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6245,7 +6245,7 @@ model_i960CA_mov (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_mov1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6261,7 +6261,7 @@ model_i960CA_mov1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_movl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movl.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6277,7 +6277,7 @@ model_i960CA_movl (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_movl1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movl1.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6293,7 +6293,7 @@ model_i960CA_movl1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_movt (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movt.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6309,7 +6309,7 @@ model_i960CA_movt (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_movt1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movt1.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6325,7 +6325,7 @@ model_i960CA_movt1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_movq (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movq.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6341,7 +6341,7 @@ model_i960CA_movq (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_movq1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_movq1.f +#define FLD(f) abuf->fields.sfmt_movq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6357,7 +6357,7 @@ model_i960CA_movq1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_modpc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6373,7 +6373,7 @@ model_i960CA_modpc (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_modac (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6389,7 +6389,7 @@ model_i960CA_modac (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6405,7 +6405,7 @@ model_i960CA_lda_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6421,7 +6421,7 @@ model_i960CA_lda_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6437,7 +6437,7 @@ model_i960CA_lda_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6453,7 +6453,7 @@ model_i960CA_lda_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6469,7 +6469,7 @@ model_i960CA_lda_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6485,7 +6485,7 @@ model_i960CA_lda_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6501,7 +6501,7 @@ model_i960CA_lda_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_lda_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6517,7 +6517,7 @@ model_i960CA_lda_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6533,7 +6533,7 @@ model_i960CA_ld_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6549,7 +6549,7 @@ model_i960CA_ld_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6565,7 +6565,7 @@ model_i960CA_ld_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6581,7 +6581,7 @@ model_i960CA_ld_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6597,7 +6597,7 @@ model_i960CA_ld_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6613,7 +6613,7 @@ model_i960CA_ld_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6629,7 +6629,7 @@ model_i960CA_ld_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ld_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6645,7 +6645,7 @@ model_i960CA_ld_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6661,7 +6661,7 @@ model_i960CA_ldob_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6677,7 +6677,7 @@ model_i960CA_ldob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6693,7 +6693,7 @@ model_i960CA_ldob_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6709,7 +6709,7 @@ model_i960CA_ldob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6725,7 +6725,7 @@ model_i960CA_ldob_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6741,7 +6741,7 @@ model_i960CA_ldob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6757,7 +6757,7 @@ model_i960CA_ldob_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6773,7 +6773,7 @@ model_i960CA_ldob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6789,7 +6789,7 @@ model_i960CA_ldos_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6805,7 +6805,7 @@ model_i960CA_ldos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6821,7 +6821,7 @@ model_i960CA_ldos_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6837,7 +6837,7 @@ model_i960CA_ldos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6853,7 +6853,7 @@ model_i960CA_ldos_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6869,7 +6869,7 @@ model_i960CA_ldos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6885,7 +6885,7 @@ model_i960CA_ldos_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6901,7 +6901,7 @@ model_i960CA_ldos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6917,7 +6917,7 @@ model_i960CA_ldib_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6933,7 +6933,7 @@ model_i960CA_ldib_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6949,7 +6949,7 @@ model_i960CA_ldib_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6965,7 +6965,7 @@ model_i960CA_ldib_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6981,7 +6981,7 @@ model_i960CA_ldib_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -6997,7 +6997,7 @@ model_i960CA_ldib_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7013,7 +7013,7 @@ model_i960CA_ldib_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldib_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7029,7 +7029,7 @@ model_i960CA_ldib_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7045,7 +7045,7 @@ model_i960CA_ldis_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7061,7 +7061,7 @@ model_i960CA_ldis_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7077,7 +7077,7 @@ model_i960CA_ldis_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7093,7 +7093,7 @@ model_i960CA_ldis_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7109,7 +7109,7 @@ model_i960CA_ldis_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7125,7 +7125,7 @@ model_i960CA_ldis_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7141,7 +7141,7 @@ model_i960CA_ldis_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldis_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7157,7 +7157,7 @@ model_i960CA_ldis_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7173,7 +7173,7 @@ model_i960CA_ldl_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7189,7 +7189,7 @@ model_i960CA_ldl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7205,7 +7205,7 @@ model_i960CA_ldl_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7221,7 +7221,7 @@ model_i960CA_ldl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7237,7 +7237,7 @@ model_i960CA_ldl_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7253,7 +7253,7 @@ model_i960CA_ldl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7269,7 +7269,7 @@ model_i960CA_ldl_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7285,7 +7285,7 @@ model_i960CA_ldl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7301,7 +7301,7 @@ model_i960CA_ldt_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7317,7 +7317,7 @@ model_i960CA_ldt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7333,7 +7333,7 @@ model_i960CA_ldt_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7349,7 +7349,7 @@ model_i960CA_ldt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7365,7 +7365,7 @@ model_i960CA_ldt_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7381,7 +7381,7 @@ model_i960CA_ldt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7397,7 +7397,7 @@ model_i960CA_ldt_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7413,7 +7413,7 @@ model_i960CA_ldt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7429,7 +7429,7 @@ model_i960CA_ldq_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7445,7 +7445,7 @@ model_i960CA_ldq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7461,7 +7461,7 @@ model_i960CA_ldq_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7477,7 +7477,7 @@ model_i960CA_ldq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7493,7 +7493,7 @@ model_i960CA_ldq_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7509,7 +7509,7 @@ model_i960CA_ldq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7525,7 +7525,7 @@ model_i960CA_ldq_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ldq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7541,7 +7541,7 @@ model_i960CA_ldq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7557,7 +7557,7 @@ model_i960CA_st_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7573,7 +7573,7 @@ model_i960CA_st_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7589,7 +7589,7 @@ model_i960CA_st_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7605,7 +7605,7 @@ model_i960CA_st_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7621,7 +7621,7 @@ model_i960CA_st_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7637,7 +7637,7 @@ model_i960CA_st_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7653,7 +7653,7 @@ model_i960CA_st_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_st_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7669,7 +7669,7 @@ model_i960CA_st_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7685,7 +7685,7 @@ model_i960CA_stob_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7701,7 +7701,7 @@ model_i960CA_stob_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7717,7 +7717,7 @@ model_i960CA_stob_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7733,7 +7733,7 @@ model_i960CA_stob_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7749,7 +7749,7 @@ model_i960CA_stob_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7765,7 +7765,7 @@ model_i960CA_stob_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7781,7 +7781,7 @@ model_i960CA_stob_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7797,7 +7797,7 @@ model_i960CA_stob_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7813,7 +7813,7 @@ model_i960CA_stos_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7829,7 +7829,7 @@ model_i960CA_stos_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7845,7 +7845,7 @@ model_i960CA_stos_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7861,7 +7861,7 @@ model_i960CA_stos_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7877,7 +7877,7 @@ model_i960CA_stos_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7893,7 +7893,7 @@ model_i960CA_stos_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7909,7 +7909,7 @@ model_i960CA_stos_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7925,7 +7925,7 @@ model_i960CA_stos_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7941,7 +7941,7 @@ model_i960CA_stl_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7957,7 +7957,7 @@ model_i960CA_stl_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7973,7 +7973,7 @@ model_i960CA_stl_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -7989,7 +7989,7 @@ model_i960CA_stl_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8005,7 +8005,7 @@ model_i960CA_stl_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8021,7 +8021,7 @@ model_i960CA_stl_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8037,7 +8037,7 @@ model_i960CA_stl_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8053,7 +8053,7 @@ model_i960CA_stl_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8069,7 +8069,7 @@ model_i960CA_stt_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8085,7 +8085,7 @@ model_i960CA_stt_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8101,7 +8101,7 @@ model_i960CA_stt_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8117,7 +8117,7 @@ model_i960CA_stt_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8133,7 +8133,7 @@ model_i960CA_stt_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8149,7 +8149,7 @@ model_i960CA_stt_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8165,7 +8165,7 @@ model_i960CA_stt_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8181,7 +8181,7 @@ model_i960CA_stt_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8197,7 +8197,7 @@ model_i960CA_stq_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8213,7 +8213,7 @@ model_i960CA_stq_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8229,7 +8229,7 @@ model_i960CA_stq_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8245,7 +8245,7 @@ model_i960CA_stq_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8261,7 +8261,7 @@ model_i960CA_stq_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8277,7 +8277,7 @@ model_i960CA_stq_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8293,7 +8293,7 @@ model_i960CA_stq_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_stq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8309,7 +8309,7 @@ model_i960CA_stq_indirect_index_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobe_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8325,7 +8325,7 @@ model_i960CA_cmpobe_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobe_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8341,7 +8341,7 @@ model_i960CA_cmpobe_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobne_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8357,7 +8357,7 @@ model_i960CA_cmpobne_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobne_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8373,7 +8373,7 @@ model_i960CA_cmpobne_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobl_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8389,7 +8389,7 @@ model_i960CA_cmpobl_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobl_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8405,7 +8405,7 @@ model_i960CA_cmpobl_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpoble_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8421,7 +8421,7 @@ model_i960CA_cmpoble_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpoble_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8437,7 +8437,7 @@ model_i960CA_cmpoble_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobg_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8453,7 +8453,7 @@ model_i960CA_cmpobg_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobg_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8469,7 +8469,7 @@ model_i960CA_cmpobg_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobge_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8485,7 +8485,7 @@ model_i960CA_cmpobge_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpobge_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8501,7 +8501,7 @@ model_i960CA_cmpobge_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibe_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8517,7 +8517,7 @@ model_i960CA_cmpibe_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibe_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8533,7 +8533,7 @@ model_i960CA_cmpibe_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibne_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8549,7 +8549,7 @@ model_i960CA_cmpibne_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibne_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8565,7 +8565,7 @@ model_i960CA_cmpibne_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibl_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8581,7 +8581,7 @@ model_i960CA_cmpibl_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibl_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8597,7 +8597,7 @@ model_i960CA_cmpibl_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpible_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8613,7 +8613,7 @@ model_i960CA_cmpible_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpible_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8629,7 +8629,7 @@ model_i960CA_cmpible_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibg_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8645,7 +8645,7 @@ model_i960CA_cmpibg_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibg_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8661,7 +8661,7 @@ model_i960CA_cmpibg_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibge_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8677,7 +8677,7 @@ model_i960CA_cmpibge_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpibge_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8693,7 +8693,7 @@ model_i960CA_cmpibge_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bbc_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8709,7 +8709,7 @@ model_i960CA_bbc_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bbc_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8725,7 +8725,7 @@ model_i960CA_bbc_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bbs_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8741,7 +8741,7 @@ model_i960CA_bbs_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bbs_lit (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8757,7 +8757,7 @@ model_i960CA_bbs_lit (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8773,7 +8773,7 @@ model_i960CA_cmpi (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpi1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8789,7 +8789,7 @@ model_i960CA_cmpi1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpi2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8805,7 +8805,7 @@ model_i960CA_cmpi2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpi3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8821,7 +8821,7 @@ model_i960CA_cmpi3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo.f +#define FLD(f) abuf->fields.sfmt_emul.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8837,7 +8837,7 @@ model_i960CA_cmpo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpo1 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8853,7 +8853,7 @@ model_i960CA_cmpo1 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpo2 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8869,7 +8869,7 @@ model_i960CA_cmpo2 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_cmpo3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8885,7 +8885,7 @@ model_i960CA_cmpo3 (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testno_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8901,7 +8901,7 @@ model_i960CA_testno_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testg_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8917,7 +8917,7 @@ model_i960CA_testg_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_teste_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8933,7 +8933,7 @@ model_i960CA_teste_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testge_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8949,7 +8949,7 @@ model_i960CA_testge_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testl_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8965,7 +8965,7 @@ model_i960CA_testl_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testne_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8981,7 +8981,7 @@ model_i960CA_testne_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testle_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -8997,7 +8997,7 @@ model_i960CA_testle_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_testo_reg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9013,7 +9013,7 @@ model_i960CA_testo_reg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bno (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9029,7 +9029,7 @@ model_i960CA_bno (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9045,7 +9045,7 @@ model_i960CA_bg (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_be (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9061,7 +9061,7 @@ model_i960CA_be (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bge (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9077,7 +9077,7 @@ model_i960CA_bge (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9093,7 +9093,7 @@ model_i960CA_bl (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bne (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9109,7 +9109,7 @@ model_i960CA_bne (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ble (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9125,7 +9125,7 @@ model_i960CA_ble (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9141,7 +9141,7 @@ model_i960CA_bo (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_b (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_b.f +#define FLD(f) abuf->fields.sfmt_bno.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9157,7 +9157,7 @@ model_i960CA_b (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9173,7 +9173,7 @@ model_i960CA_bx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bx_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9189,7 +9189,7 @@ model_i960CA_bx_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bx_indirect_index (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9205,7 +9205,7 @@ model_i960CA_bx_indirect_index (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bx_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9221,7 +9221,7 @@ model_i960CA_bx_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_bx_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9237,7 +9237,7 @@ model_i960CA_bx_indirect_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_callx_disp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9253,7 +9253,7 @@ model_i960CA_callx_disp (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_callx_indirect (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9269,7 +9269,7 @@ model_i960CA_callx_indirect (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_callx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9285,7 +9285,7 @@ model_i960CA_callx_indirect_offset (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_ret (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9301,7 +9301,7 @@ model_i960CA_ret (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_calls (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_calls.f +#define FLD(f) abuf->fields.sfmt_emul2.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9317,7 +9317,7 @@ model_i960CA_calls (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_fmark (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -9333,7 +9333,7 @@ model_i960CA_fmark (SIM_CPU *current_cpu, void *sem_arg) static int model_i960CA_flushreg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_flushreg.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; diff --git a/sim/i960/sem-switch.c b/sim/i960/sem-switch.c index b45109f..15f6b70 100644 --- a/sim/i960/sem-switch.c +++ b/sim/i960/sem-switch.c @@ -334,11 +334,13 @@ with this program; if not, write to the Free Software Foundation, Inc., int i; for (i = 0; labels[i].label != 0; ++i) + { #if FAST_P - CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; + CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; #else - CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; + CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; #endif + } #undef DEFINE_LABELS #endif /* DEFINE_LABELS */ @@ -458,12 +460,12 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) #if WITH_SCACHE_PBB_I960BASE #ifdef DEFINE_SWITCH vpc = i960base_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); + pbb_br_type, pbb_br_npc); BREAK (sem); #else /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ vpc = i960base_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_TYPE (current_cpu), CPU_PBB_BR_NPC (current_cpu)); #endif #endif @@ -524,7 +526,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -543,7 +545,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -562,7 +564,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -581,7 +583,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -600,7 +602,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -619,7 +621,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -638,7 +640,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -657,7 +659,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -676,7 +678,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -695,7 +697,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -714,7 +716,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -733,7 +735,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -752,7 +754,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -771,7 +773,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -790,7 +792,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -809,7 +811,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -828,7 +830,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -847,7 +849,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -866,7 +868,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -885,7 +887,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -904,7 +906,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -923,7 +925,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -942,7 +944,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -961,7 +963,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -980,7 +982,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -999,7 +1001,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1018,7 +1020,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1037,7 +1039,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1056,7 +1058,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1075,7 +1077,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1094,7 +1096,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1113,7 +1115,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1132,7 +1134,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1151,7 +1153,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1170,7 +1172,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1189,7 +1191,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1208,7 +1210,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1227,7 +1229,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1246,7 +1248,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1265,7 +1267,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1284,7 +1286,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1303,7 +1305,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1322,7 +1324,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1341,7 +1343,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1360,7 +1362,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1379,7 +1381,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1398,7 +1400,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1417,7 +1419,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1436,7 +1438,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1455,7 +1457,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1474,7 +1476,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1493,7 +1495,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1512,7 +1514,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1531,7 +1533,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1550,7 +1552,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1569,7 +1571,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1588,7 +1590,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1607,7 +1609,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1626,7 +1628,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1645,7 +1647,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1664,7 +1666,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1683,7 +1685,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1702,7 +1704,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1721,7 +1723,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1740,7 +1742,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_not.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1759,7 +1761,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_not1.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1778,7 +1780,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1797,7 +1799,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1816,7 +1818,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1835,7 +1837,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1854,7 +1856,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1873,7 +1875,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1892,7 +1894,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1911,7 +1913,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1930,7 +1932,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1949,7 +1951,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1968,7 +1970,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1987,7 +1989,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2006,7 +2008,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2025,7 +2027,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2044,7 +2046,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2063,7 +2065,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2082,7 +2084,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2101,7 +2103,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2120,7 +2122,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2139,7 +2141,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2158,7 +2160,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2177,7 +2179,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2196,7 +2198,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2215,7 +2217,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2234,7 +2236,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2253,7 +2255,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2272,7 +2274,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_emul.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2302,7 +2304,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_emul1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2332,7 +2334,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_emul2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2362,7 +2364,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_emul3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2392,7 +2394,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2411,7 +2413,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2430,7 +2432,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movl.f +#define FLD(f) abuf->fields.sfmt_movq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2460,7 +2462,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movl1.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2488,7 +2490,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movt.f +#define FLD(f) abuf->fields.sfmt_movq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2523,7 +2525,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movt1.f +#define FLD(f) abuf->fields.sfmt_movq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2556,7 +2558,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movq.f +#define FLD(f) abuf->fields.sfmt_movq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2596,7 +2598,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_movq1.f +#define FLD(f) abuf->fields.sfmt_movq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2634,7 +2636,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2653,7 +2655,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2672,7 +2674,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2691,7 +2693,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2710,7 +2712,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2729,7 +2731,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2748,7 +2750,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2767,7 +2769,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2786,7 +2788,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2805,7 +2807,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2824,7 +2826,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2843,7 +2845,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2862,7 +2864,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2881,7 +2883,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2900,7 +2902,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2919,7 +2921,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2938,7 +2940,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2957,7 +2959,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -2976,7 +2978,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2995,7 +2997,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3014,7 +3016,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3033,7 +3035,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3052,7 +3054,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3071,7 +3073,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3090,7 +3092,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3109,7 +3111,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3128,7 +3130,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3147,7 +3149,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3166,7 +3168,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3185,7 +3187,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3204,7 +3206,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3223,7 +3225,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3242,7 +3244,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3261,7 +3263,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3280,7 +3282,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3299,7 +3301,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3318,7 +3320,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3337,7 +3339,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3356,7 +3358,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3375,7 +3377,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3394,7 +3396,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3413,7 +3415,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3432,7 +3434,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3451,7 +3453,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3470,7 +3472,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3489,7 +3491,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3508,7 +3510,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3527,7 +3529,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3546,7 +3548,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3565,7 +3567,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3584,7 +3586,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3614,7 +3616,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3644,7 +3646,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3674,7 +3676,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3704,7 +3706,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3734,7 +3736,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3764,7 +3766,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3794,7 +3796,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3824,7 +3826,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3859,7 +3861,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3894,7 +3896,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3929,7 +3931,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -3964,7 +3966,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -3999,7 +4001,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4034,7 +4036,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4069,7 +4071,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4104,7 +4106,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4144,7 +4146,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4184,7 +4186,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4224,7 +4226,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4264,7 +4266,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4304,7 +4306,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4344,7 +4346,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4384,7 +4386,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4424,7 +4426,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4443,7 +4445,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4462,7 +4464,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4481,7 +4483,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4500,7 +4502,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4519,7 +4521,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4538,7 +4540,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4557,7 +4559,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4576,7 +4578,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4595,7 +4597,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4614,7 +4616,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4633,7 +4635,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4652,7 +4654,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4671,7 +4673,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4690,7 +4692,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4709,7 +4711,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4728,7 +4730,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4747,7 +4749,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4766,7 +4768,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4785,7 +4787,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4804,7 +4806,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4823,7 +4825,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4842,7 +4844,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4861,7 +4863,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -4880,7 +4882,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4908,7 +4910,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4936,7 +4938,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4964,7 +4966,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4992,7 +4994,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5020,7 +5022,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5048,7 +5050,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5076,7 +5078,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5104,7 +5106,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5137,7 +5139,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5170,7 +5172,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5203,7 +5205,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5236,7 +5238,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5269,7 +5271,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5302,7 +5304,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5335,7 +5337,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5368,7 +5370,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5406,7 +5408,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5444,7 +5446,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5482,7 +5484,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5520,7 +5522,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5558,7 +5560,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5596,7 +5598,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5634,7 +5636,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 8); @@ -5672,7 +5674,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5681,7 +5683,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5697,7 +5699,7 @@ if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5706,7 +5708,7 @@ if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5722,7 +5724,7 @@ if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5731,7 +5733,7 @@ if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5747,7 +5749,7 @@ if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5756,7 +5758,7 @@ if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5772,7 +5774,7 @@ if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5781,7 +5783,7 @@ if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5797,7 +5799,7 @@ if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5806,7 +5808,7 @@ if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5822,7 +5824,7 @@ if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5831,7 +5833,7 @@ if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5847,7 +5849,7 @@ if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5856,7 +5858,7 @@ if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5872,7 +5874,7 @@ if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5881,7 +5883,7 @@ if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5897,7 +5899,7 @@ if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5906,7 +5908,7 @@ if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5922,7 +5924,7 @@ if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5931,7 +5933,7 @@ if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5947,7 +5949,7 @@ if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5956,7 +5958,7 @@ if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5972,7 +5974,7 @@ if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -5981,7 +5983,7 @@ if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5997,7 +5999,7 @@ if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6006,7 +6008,7 @@ if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6022,7 +6024,7 @@ if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6031,7 +6033,7 @@ if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6047,7 +6049,7 @@ if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6056,7 +6058,7 @@ if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6072,7 +6074,7 @@ if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6081,7 +6083,7 @@ if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6097,7 +6099,7 @@ if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6106,7 +6108,7 @@ if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6122,7 +6124,7 @@ if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6131,7 +6133,7 @@ if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6147,7 +6149,7 @@ if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6156,7 +6158,7 @@ if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6172,7 +6174,7 @@ if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6181,7 +6183,7 @@ if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) { if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6197,7 +6199,7 @@ if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6206,7 +6208,7 @@ if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6222,7 +6224,7 @@ if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6231,7 +6233,7 @@ if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) { if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6247,7 +6249,7 @@ if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6256,7 +6258,7 @@ if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) { if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6272,7 +6274,7 @@ if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6281,7 +6283,7 @@ if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) { if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6297,7 +6299,7 @@ if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6306,7 +6308,7 @@ if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6322,7 +6324,7 @@ if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6331,7 +6333,7 @@ if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6347,7 +6349,7 @@ if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6356,7 +6358,7 @@ if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6372,7 +6374,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6391,7 +6393,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6410,7 +6412,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6429,7 +6431,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6448,7 +6450,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpo.f +#define FLD(f) abuf->fields.sfmt_emul.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6467,7 +6469,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6486,7 +6488,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6505,7 +6507,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6524,7 +6526,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6543,7 +6545,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6562,7 +6564,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6581,7 +6583,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6600,7 +6602,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6619,7 +6621,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6638,7 +6640,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6657,7 +6659,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -6676,7 +6678,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6685,7 +6687,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { if (EQSI (CPU (h_cc), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6701,7 +6703,7 @@ if (EQSI (CPU (h_cc), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6710,7 +6712,7 @@ if (EQSI (CPU (h_cc), 0)) { if (NESI (ANDSI (CPU (h_cc), 1), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6726,7 +6728,7 @@ if (NESI (ANDSI (CPU (h_cc), 1), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6735,7 +6737,7 @@ if (NESI (ANDSI (CPU (h_cc), 1), 0)) { if (NESI (ANDSI (CPU (h_cc), 2), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6751,7 +6753,7 @@ if (NESI (ANDSI (CPU (h_cc), 2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6760,7 +6762,7 @@ if (NESI (ANDSI (CPU (h_cc), 2), 0)) { if (NESI (ANDSI (CPU (h_cc), 3), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6776,7 +6778,7 @@ if (NESI (ANDSI (CPU (h_cc), 3), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6785,7 +6787,7 @@ if (NESI (ANDSI (CPU (h_cc), 3), 0)) { if (NESI (ANDSI (CPU (h_cc), 4), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6801,7 +6803,7 @@ if (NESI (ANDSI (CPU (h_cc), 4), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6810,7 +6812,7 @@ if (NESI (ANDSI (CPU (h_cc), 4), 0)) { if (NESI (ANDSI (CPU (h_cc), 5), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6826,7 +6828,7 @@ if (NESI (ANDSI (CPU (h_cc), 5), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6835,7 +6837,7 @@ if (NESI (ANDSI (CPU (h_cc), 5), 0)) { if (NESI (ANDSI (CPU (h_cc), 6), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6851,7 +6853,7 @@ if (NESI (ANDSI (CPU (h_cc), 6), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6860,7 +6862,7 @@ if (NESI (ANDSI (CPU (h_cc), 6), 0)) { if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6876,7 +6878,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_b.f +#define FLD(f) abuf->fields.sfmt_bno.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6884,7 +6886,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6897,7 +6899,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6918,7 +6920,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6939,7 +6941,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6960,7 +6962,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -6968,7 +6970,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { USI opval = FLD (f_optdisp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6981,7 +6983,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7002,7 +7004,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7034,7 +7036,7 @@ SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)])); { USI opval = FLD (f_optdisp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } CPU (h_gr[((UINT) 0)]) = 0xdeadbeef; @@ -7079,7 +7081,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7156,7 +7158,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7233,7 +7235,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7277,7 +7279,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_calls.f +#define FLD(f) abuf->fields.sfmt_emul2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7298,7 +7300,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -7319,7 +7321,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_flushreg.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); diff --git a/sim/i960/sem.c b/sim/i960/sem.c index 45f4f7f..7d5f28b 100644 --- a/sim/i960/sem.c +++ b/sim/i960/sem.c @@ -32,9 +32,20 @@ with this program; if not, write to the Free Software Foundation, Inc., #undef GET_ATTR #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + /* x-invalid: --invalid-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -59,7 +70,7 @@ SEM_FN_NAME (i960base,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-after: --after-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -80,7 +91,7 @@ SEM_FN_NAME (i960base,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-before: --before-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -101,7 +112,7 @@ SEM_FN_NAME (i960base,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-cti-chain: --cti-chain-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -114,12 +125,12 @@ SEM_FN_NAME (i960base,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #if WITH_SCACHE_PBB_I960BASE #ifdef DEFINE_SWITCH vpc = i960base_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); + pbb_br_type, pbb_br_npc); BREAK (sem); #else /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ vpc = i960base_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_TYPE (current_cpu), CPU_PBB_BR_NPC (current_cpu)); #endif #endif @@ -131,7 +142,7 @@ SEM_FN_NAME (i960base,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-chain: --chain-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -155,7 +166,7 @@ SEM_FN_NAME (i960base,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-begin: --begin-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -182,10 +193,10 @@ SEM_FN_NAME (i960base,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulo: mulo $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,mulo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -203,10 +214,10 @@ SEM_FN_NAME (i960base,mulo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulo1: mulo $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,mulo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -224,10 +235,10 @@ SEM_FN_NAME (i960base,mulo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulo2: mulo $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,mulo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -245,10 +256,10 @@ SEM_FN_NAME (i960base,mulo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulo3: mulo $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,mulo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -266,10 +277,10 @@ SEM_FN_NAME (i960base,mulo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remo: remo $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -287,10 +298,10 @@ SEM_FN_NAME (i960base,remo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remo1: remo $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -308,10 +319,10 @@ SEM_FN_NAME (i960base,remo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remo2: remo $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -329,10 +340,10 @@ SEM_FN_NAME (i960base,remo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remo3: remo $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -350,10 +361,10 @@ SEM_FN_NAME (i960base,remo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divo: divo $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -371,10 +382,10 @@ SEM_FN_NAME (i960base,divo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divo1: divo $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -392,10 +403,10 @@ SEM_FN_NAME (i960base,divo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divo2: divo $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -413,10 +424,10 @@ SEM_FN_NAME (i960base,divo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divo3: divo $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -434,10 +445,10 @@ SEM_FN_NAME (i960base,divo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remi: remi $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -455,10 +466,10 @@ SEM_FN_NAME (i960base,remi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remi1: remi $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -476,10 +487,10 @@ SEM_FN_NAME (i960base,remi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remi2: remi $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -497,10 +508,10 @@ SEM_FN_NAME (i960base,remi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* remi3: remi $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,remi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -518,10 +529,10 @@ SEM_FN_NAME (i960base,remi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divi: divi $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -539,10 +550,10 @@ SEM_FN_NAME (i960base,divi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divi1: divi $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -560,10 +571,10 @@ SEM_FN_NAME (i960base,divi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divi2: divi $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -581,10 +592,10 @@ SEM_FN_NAME (i960base,divi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* divi3: divi $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,divi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -602,10 +613,10 @@ SEM_FN_NAME (i960base,divi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addo: addo $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,addo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -623,10 +634,10 @@ SEM_FN_NAME (i960base,addo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addo1: addo $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,addo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -644,10 +655,10 @@ SEM_FN_NAME (i960base,addo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addo2: addo $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,addo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -665,10 +676,10 @@ SEM_FN_NAME (i960base,addo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addo3: addo $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,addo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -686,10 +697,10 @@ SEM_FN_NAME (i960base,addo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subo: subo $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,subo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -707,10 +718,10 @@ SEM_FN_NAME (i960base,subo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subo1: subo $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,subo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -728,10 +739,10 @@ SEM_FN_NAME (i960base,subo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subo2: subo $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,subo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -749,10 +760,10 @@ SEM_FN_NAME (i960base,subo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subo3: subo $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,subo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -770,10 +781,10 @@ SEM_FN_NAME (i960base,subo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notbit: notbit $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -791,10 +802,10 @@ SEM_FN_NAME (i960base,notbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notbit1: notbit $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -812,10 +823,10 @@ SEM_FN_NAME (i960base,notbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notbit2: notbit $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -833,10 +844,10 @@ SEM_FN_NAME (i960base,notbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notbit3: notbit $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -854,10 +865,10 @@ SEM_FN_NAME (i960base,notbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and: and $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -875,10 +886,10 @@ SEM_FN_NAME (i960base,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and1: and $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,and1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -896,10 +907,10 @@ SEM_FN_NAME (i960base,and1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and2: and $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,and2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -917,10 +928,10 @@ SEM_FN_NAME (i960base,and2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and3: and $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -938,10 +949,10 @@ SEM_FN_NAME (i960base,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andnot: andnot $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,andnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -959,10 +970,10 @@ SEM_FN_NAME (i960base,andnot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andnot1: andnot $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,andnot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -980,10 +991,10 @@ SEM_FN_NAME (i960base,andnot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andnot2: andnot $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,andnot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1001,10 +1012,10 @@ SEM_FN_NAME (i960base,andnot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* andnot3: andnot $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,andnot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1022,10 +1033,10 @@ SEM_FN_NAME (i960base,andnot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* setbit: setbit $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,setbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1043,10 +1054,10 @@ SEM_FN_NAME (i960base,setbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* setbit1: setbit $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,setbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1064,10 +1075,10 @@ SEM_FN_NAME (i960base,setbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* setbit2: setbit $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,setbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1085,10 +1096,10 @@ SEM_FN_NAME (i960base,setbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* setbit3: setbit $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,setbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1106,10 +1117,10 @@ SEM_FN_NAME (i960base,setbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notand: notand $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notand) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1127,10 +1138,10 @@ SEM_FN_NAME (i960base,notand) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notand1: notand $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notand1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1148,10 +1159,10 @@ SEM_FN_NAME (i960base,notand1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notand2: notand $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notand2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1169,10 +1180,10 @@ SEM_FN_NAME (i960base,notand2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* notand3: notand $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,notand3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1190,10 +1201,10 @@ SEM_FN_NAME (i960base,notand3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xor: xor $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1211,10 +1222,10 @@ SEM_FN_NAME (i960base,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xor1: xor $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1232,10 +1243,10 @@ SEM_FN_NAME (i960base,xor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xor2: xor $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1253,10 +1264,10 @@ SEM_FN_NAME (i960base,xor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xor3: xor $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1274,10 +1285,10 @@ SEM_FN_NAME (i960base,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or: or $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1295,10 +1306,10 @@ SEM_FN_NAME (i960base,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or1: or $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,or1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1316,10 +1327,10 @@ SEM_FN_NAME (i960base,or1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or2: or $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,or2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1337,10 +1348,10 @@ SEM_FN_NAME (i960base,or2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or3: or $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1358,10 +1369,10 @@ SEM_FN_NAME (i960base,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* nor: nor $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1379,10 +1390,10 @@ SEM_FN_NAME (i960base,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* nor1: nor $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,nor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1400,10 +1411,10 @@ SEM_FN_NAME (i960base,nor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* nor2: nor $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,nor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1421,10 +1432,10 @@ SEM_FN_NAME (i960base,nor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* nor3: nor $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,nor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1442,10 +1453,10 @@ SEM_FN_NAME (i960base,nor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xnor: xnor $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1463,10 +1474,10 @@ SEM_FN_NAME (i960base,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xnor1: xnor $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xnor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1484,10 +1495,10 @@ SEM_FN_NAME (i960base,xnor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xnor2: xnor $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xnor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1505,10 +1516,10 @@ SEM_FN_NAME (i960base,xnor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xnor3: xnor $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,xnor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1526,10 +1537,10 @@ SEM_FN_NAME (i960base,xnor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* not: not $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_not.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1547,10 +1558,10 @@ SEM_FN_NAME (i960base,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* not1: not $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,not1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_not1.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1568,10 +1579,10 @@ SEM_FN_NAME (i960base,not1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* not2: not $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,not2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1589,10 +1600,10 @@ SEM_FN_NAME (i960base,not2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* not3: not $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,not3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1610,10 +1621,10 @@ SEM_FN_NAME (i960base,not3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ornot: ornot $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ornot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1631,10 +1642,10 @@ SEM_FN_NAME (i960base,ornot) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ornot1: ornot $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ornot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1652,10 +1663,10 @@ SEM_FN_NAME (i960base,ornot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ornot2: ornot $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ornot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1673,10 +1684,10 @@ SEM_FN_NAME (i960base,ornot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ornot3: ornot $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ornot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1694,10 +1705,10 @@ SEM_FN_NAME (i960base,ornot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* clrbit: clrbit $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,clrbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1715,10 +1726,10 @@ SEM_FN_NAME (i960base,clrbit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* clrbit1: clrbit $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,clrbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1736,10 +1747,10 @@ SEM_FN_NAME (i960base,clrbit1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* clrbit2: clrbit $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,clrbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1757,10 +1768,10 @@ SEM_FN_NAME (i960base,clrbit2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* clrbit3: clrbit $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,clrbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_notbit3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1778,10 +1789,10 @@ SEM_FN_NAME (i960base,clrbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shlo: shlo $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1799,10 +1810,10 @@ SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shlo1: shlo $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1820,10 +1831,10 @@ SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shlo2: shlo $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1841,10 +1852,10 @@ SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shlo3: shlo $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1862,10 +1873,10 @@ SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shro: shro $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1883,10 +1894,10 @@ SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shro1: shro $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1904,10 +1915,10 @@ SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shro2: shro $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1925,10 +1936,10 @@ SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shro3: shro $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1946,10 +1957,10 @@ SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shli: shli $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1967,10 +1978,10 @@ SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shli1: shli $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1988,10 +1999,10 @@ SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shli2: shli $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2009,10 +2020,10 @@ SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shli3: shli $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2030,10 +2041,10 @@ SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shri: shri $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2051,10 +2062,10 @@ SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shri1: shri $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2072,10 +2083,10 @@ SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shri2: shri $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2093,10 +2104,10 @@ SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* shri3: shri $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,shri3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_shlo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2114,10 +2125,10 @@ SEM_FN_NAME (i960base,shri3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* emul: emul $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,emul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_emul.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2146,10 +2157,10 @@ SEM_FN_NAME (i960base,emul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* emul1: emul $lit1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,emul1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_emul1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2178,10 +2189,10 @@ SEM_FN_NAME (i960base,emul1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* emul2: emul $src1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,emul2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_emul2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2210,10 +2221,10 @@ SEM_FN_NAME (i960base,emul2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* emul3: emul $lit1, $lit2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,emul3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_emul3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2242,10 +2253,10 @@ SEM_FN_NAME (i960base,emul3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mov: mov $src1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,mov) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_not2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2263,10 +2274,10 @@ SEM_FN_NAME (i960base,mov) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mov1: mov $lit1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,mov1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_not3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2284,10 +2295,10 @@ SEM_FN_NAME (i960base,mov1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movl: movl $src1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,movl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movl.f +#define FLD(f) abuf->fields.sfmt_movq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2316,10 +2327,10 @@ SEM_FN_NAME (i960base,movl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movl1: movl $lit1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,movl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movl1.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2346,10 +2357,10 @@ SEM_FN_NAME (i960base,movl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movt: movt $src1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,movt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movt.f +#define FLD(f) abuf->fields.sfmt_movq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2383,10 +2394,10 @@ SEM_FN_NAME (i960base,movt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movt1: movt $lit1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,movt1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movt1.f +#define FLD(f) abuf->fields.sfmt_movq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2418,10 +2429,10 @@ SEM_FN_NAME (i960base,movt1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movq: movq $src1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,movq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movq.f +#define FLD(f) abuf->fields.sfmt_movq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2460,10 +2471,10 @@ SEM_FN_NAME (i960base,movq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* movq1: movq $lit1, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,movq1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_movq1.f +#define FLD(f) abuf->fields.sfmt_movq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2500,10 +2511,10 @@ SEM_FN_NAME (i960base,movq1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* modpc: modpc $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,modpc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2521,10 +2532,10 @@ SEM_FN_NAME (i960base,modpc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* modac: modac $src1, $src2, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,modac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_modpc.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2542,10 +2553,10 @@ SEM_FN_NAME (i960base,modac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lda-offset: lda $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2563,10 +2574,10 @@ SEM_FN_NAME (i960base,lda_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lda-indirect-offset: lda $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2584,10 +2595,10 @@ SEM_FN_NAME (i960base,lda_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* lda-indirect: lda ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2605,10 +2616,10 @@ SEM_FN_NAME (i960base,lda_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lda-indirect-index: lda ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2626,10 +2637,10 @@ SEM_FN_NAME (i960base,lda_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* lda-disp: lda $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2647,10 +2658,10 @@ SEM_FN_NAME (i960base,lda_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lda-indirect-disp: lda $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2668,10 +2679,10 @@ SEM_FN_NAME (i960base,lda_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lda-index-disp: lda $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2689,10 +2700,10 @@ SEM_FN_NAME (i960base,lda_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lda-indirect-index-disp: lda $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,lda_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2710,10 +2721,10 @@ SEM_FN_NAME (i960base,lda_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* ld-offset: ld $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2731,10 +2742,10 @@ SEM_FN_NAME (i960base,ld_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-indirect-offset: ld $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2752,10 +2763,10 @@ SEM_FN_NAME (i960base,ld_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ld-indirect: ld ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2773,10 +2784,10 @@ SEM_FN_NAME (i960base,ld_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-indirect-index: ld ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2794,10 +2805,10 @@ SEM_FN_NAME (i960base,ld_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-disp: ld $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2815,10 +2826,10 @@ SEM_FN_NAME (i960base,ld_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-indirect-disp: ld $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2836,10 +2847,10 @@ SEM_FN_NAME (i960base,ld_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-index-disp: ld $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2857,10 +2868,10 @@ SEM_FN_NAME (i960base,ld_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-indirect-index-disp: ld $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ld_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2878,10 +2889,10 @@ SEM_FN_NAME (i960base,ld_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem /* ldob-offset: ldob $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2899,10 +2910,10 @@ SEM_FN_NAME (i960base,ldob_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldob-indirect-offset: ldob $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2920,10 +2931,10 @@ SEM_FN_NAME (i960base,ldob_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_a /* ldob-indirect: ldob ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2941,10 +2952,10 @@ SEM_FN_NAME (i960base,ldob_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldob-indirect-index: ldob ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2962,10 +2973,10 @@ SEM_FN_NAME (i960base,ldob_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldob-disp: ldob $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2983,10 +2994,10 @@ SEM_FN_NAME (i960base,ldob_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldob-indirect-disp: ldob $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3004,10 +3015,10 @@ SEM_FN_NAME (i960base,ldob_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldob-index-disp: ldob $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3025,10 +3036,10 @@ SEM_FN_NAME (i960base,ldob_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldob-indirect-index-disp: ldob $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldob_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3046,10 +3057,10 @@ SEM_FN_NAME (i960base,ldob_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG s /* ldos-offset: ldos $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3067,10 +3078,10 @@ SEM_FN_NAME (i960base,ldos_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldos-indirect-offset: ldos $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3088,10 +3099,10 @@ SEM_FN_NAME (i960base,ldos_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_a /* ldos-indirect: ldos ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3109,10 +3120,10 @@ SEM_FN_NAME (i960base,ldos_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldos-indirect-index: ldos ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3130,10 +3141,10 @@ SEM_FN_NAME (i960base,ldos_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldos-disp: ldos $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3151,10 +3162,10 @@ SEM_FN_NAME (i960base,ldos_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldos-indirect-disp: ldos $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3172,10 +3183,10 @@ SEM_FN_NAME (i960base,ldos_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldos-index-disp: ldos $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3193,10 +3204,10 @@ SEM_FN_NAME (i960base,ldos_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldos-indirect-index-disp: ldos $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldos_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3214,10 +3225,10 @@ SEM_FN_NAME (i960base,ldos_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG s /* ldib-offset: ldib $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3235,10 +3246,10 @@ SEM_FN_NAME (i960base,ldib_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldib-indirect-offset: ldib $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3256,10 +3267,10 @@ SEM_FN_NAME (i960base,ldib_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_a /* ldib-indirect: ldib ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3277,10 +3288,10 @@ SEM_FN_NAME (i960base,ldib_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldib-indirect-index: ldib ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3298,10 +3309,10 @@ SEM_FN_NAME (i960base,ldib_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldib-disp: ldib $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3319,10 +3330,10 @@ SEM_FN_NAME (i960base,ldib_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldib-indirect-disp: ldib $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3340,10 +3351,10 @@ SEM_FN_NAME (i960base,ldib_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldib-index-disp: ldib $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3361,10 +3372,10 @@ SEM_FN_NAME (i960base,ldib_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldib-indirect-index-disp: ldib $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldib_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3382,10 +3393,10 @@ SEM_FN_NAME (i960base,ldib_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG s /* ldis-offset: ldis $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3403,10 +3414,10 @@ SEM_FN_NAME (i960base,ldis_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldis-indirect-offset: ldis $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3424,10 +3435,10 @@ SEM_FN_NAME (i960base,ldis_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_a /* ldis-indirect: ldis ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3445,10 +3456,10 @@ SEM_FN_NAME (i960base,ldis_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldis-indirect-index: ldis ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3466,10 +3477,10 @@ SEM_FN_NAME (i960base,ldis_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldis-disp: ldis $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3487,10 +3498,10 @@ SEM_FN_NAME (i960base,ldis_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldis-indirect-disp: ldis $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3508,10 +3519,10 @@ SEM_FN_NAME (i960base,ldis_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldis-index-disp: ldis $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3529,10 +3540,10 @@ SEM_FN_NAME (i960base,ldis_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldis-indirect-index-disp: ldis $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldis_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3550,10 +3561,10 @@ SEM_FN_NAME (i960base,ldis_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG s /* ldl-offset: ldl $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3582,10 +3593,10 @@ SEM_FN_NAME (i960base,ldl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldl-indirect-offset: ldl $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3614,10 +3625,10 @@ SEM_FN_NAME (i960base,ldl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldl-indirect: ldl ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3646,10 +3657,10 @@ SEM_FN_NAME (i960base,ldl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldl-indirect-index: ldl ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3678,10 +3689,10 @@ SEM_FN_NAME (i960base,ldl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldl-disp: ldl $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3710,10 +3721,10 @@ SEM_FN_NAME (i960base,ldl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldl-indirect-disp: ldl $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3742,10 +3753,10 @@ SEM_FN_NAME (i960base,ldl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldl-index-disp: ldl $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3774,10 +3785,10 @@ SEM_FN_NAME (i960base,ldl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldl-indirect-index-disp: ldl $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3806,10 +3817,10 @@ SEM_FN_NAME (i960base,ldl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* ldt-offset: ldt $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3843,10 +3854,10 @@ SEM_FN_NAME (i960base,ldt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldt-indirect-offset: ldt $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3880,10 +3891,10 @@ SEM_FN_NAME (i960base,ldt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldt-indirect: ldt ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3917,10 +3928,10 @@ SEM_FN_NAME (i960base,ldt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldt-indirect-index: ldt ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3954,10 +3965,10 @@ SEM_FN_NAME (i960base,ldt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldt-disp: ldt $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3991,10 +4002,10 @@ SEM_FN_NAME (i960base,ldt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldt-indirect-disp: ldt $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4028,10 +4039,10 @@ SEM_FN_NAME (i960base,ldt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldt-index-disp: ldt $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4065,10 +4076,10 @@ SEM_FN_NAME (i960base,ldt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldt-indirect-index-disp: ldt $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4102,10 +4113,10 @@ SEM_FN_NAME (i960base,ldt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* ldq-offset: ldq $offset, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4144,10 +4155,10 @@ SEM_FN_NAME (i960base,ldq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldq-indirect-offset: ldq $offset($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4186,10 +4197,10 @@ SEM_FN_NAME (i960base,ldq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* ldq-indirect: ldq ($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4228,10 +4239,10 @@ SEM_FN_NAME (i960base,ldq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldq-indirect-index: ldq ($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4270,10 +4281,10 @@ SEM_FN_NAME (i960base,ldq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* ldq-disp: ldq $optdisp, $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4312,10 +4323,10 @@ SEM_FN_NAME (i960base,ldq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldq-indirect-disp: ldq $optdisp($abase), $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4354,10 +4365,10 @@ SEM_FN_NAME (i960base,ldq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldq-index-disp: ldq $optdisp[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4396,10 +4407,10 @@ SEM_FN_NAME (i960base,ldq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldq-indirect-index-disp: ldq $optdisp($abase)[$index*S$scale], $dst */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ldq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_ldq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4438,10 +4449,10 @@ SEM_FN_NAME (i960base,ldq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* st-offset: st $st_src, $offset */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4459,10 +4470,10 @@ SEM_FN_NAME (i960base,st_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-indirect-offset: st $st_src, $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4480,10 +4491,10 @@ SEM_FN_NAME (i960base,st_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* st-indirect: st $st_src, ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4501,10 +4512,10 @@ SEM_FN_NAME (i960base,st_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-indirect-index: st $st_src, ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4522,10 +4533,10 @@ SEM_FN_NAME (i960base,st_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-disp: st $st_src, $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4543,10 +4554,10 @@ SEM_FN_NAME (i960base,st_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-indirect-disp: st $st_src, $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4564,10 +4575,10 @@ SEM_FN_NAME (i960base,st_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-index-disp: st $st_src, $optdisp[$index*S$scale */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4585,10 +4596,10 @@ SEM_FN_NAME (i960base,st_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-indirect-index-disp: st $st_src, $optdisp($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,st_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4606,10 +4617,10 @@ SEM_FN_NAME (i960base,st_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem /* stob-offset: stob $st_src, $offset */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4627,10 +4638,10 @@ SEM_FN_NAME (i960base,stob_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stob-indirect-offset: stob $st_src, $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4648,10 +4659,10 @@ SEM_FN_NAME (i960base,stob_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_a /* stob-indirect: stob $st_src, ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4669,10 +4680,10 @@ SEM_FN_NAME (i960base,stob_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stob-indirect-index: stob $st_src, ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4690,10 +4701,10 @@ SEM_FN_NAME (i960base,stob_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* stob-disp: stob $st_src, $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4711,10 +4722,10 @@ SEM_FN_NAME (i960base,stob_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stob-indirect-disp: stob $st_src, $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4732,10 +4743,10 @@ SEM_FN_NAME (i960base,stob_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* stob-index-disp: stob $st_src, $optdisp[$index*S$scale */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4753,10 +4764,10 @@ SEM_FN_NAME (i960base,stob_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stob-indirect-index-disp: stob $st_src, $optdisp($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stob_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4774,10 +4785,10 @@ SEM_FN_NAME (i960base,stob_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG s /* stos-offset: stos $st_src, $offset */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4795,10 +4806,10 @@ SEM_FN_NAME (i960base,stos_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stos-indirect-offset: stos $st_src, $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4816,10 +4827,10 @@ SEM_FN_NAME (i960base,stos_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_a /* stos-indirect: stos $st_src, ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4837,10 +4848,10 @@ SEM_FN_NAME (i960base,stos_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stos-indirect-index: stos $st_src, ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4858,10 +4869,10 @@ SEM_FN_NAME (i960base,stos_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* stos-disp: stos $st_src, $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4879,10 +4890,10 @@ SEM_FN_NAME (i960base,stos_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stos-indirect-disp: stos $st_src, $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4900,10 +4911,10 @@ SEM_FN_NAME (i960base,stos_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* stos-index-disp: stos $st_src, $optdisp[$index*S$scale */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4921,10 +4932,10 @@ SEM_FN_NAME (i960base,stos_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stos-indirect-index-disp: stos $st_src, $optdisp($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stos_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4942,10 +4953,10 @@ SEM_FN_NAME (i960base,stos_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG s /* stl-offset: stl $st_src, $offset */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4972,10 +4983,10 @@ SEM_FN_NAME (i960base,stl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stl-indirect-offset: stl $st_src, $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5002,10 +5013,10 @@ SEM_FN_NAME (i960base,stl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* stl-indirect: stl $st_src, ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5032,10 +5043,10 @@ SEM_FN_NAME (i960base,stl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stl-indirect-index: stl $st_src, ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5062,10 +5073,10 @@ SEM_FN_NAME (i960base,stl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* stl-disp: stl $st_src, $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5092,10 +5103,10 @@ SEM_FN_NAME (i960base,stl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stl-indirect-disp: stl $st_src, $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5122,10 +5133,10 @@ SEM_FN_NAME (i960base,stl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stl-index-disp: stl $st_src, $optdisp[$index*S$scale */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5152,10 +5163,10 @@ SEM_FN_NAME (i960base,stl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stl-indirect-index-disp: stl $st_src, $optdisp($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5182,10 +5193,10 @@ SEM_FN_NAME (i960base,stl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* stt-offset: stt $st_src, $offset */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5217,10 +5228,10 @@ SEM_FN_NAME (i960base,stt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stt-indirect-offset: stt $st_src, $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5252,10 +5263,10 @@ SEM_FN_NAME (i960base,stt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* stt-indirect: stt $st_src, ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5287,10 +5298,10 @@ SEM_FN_NAME (i960base,stt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stt-indirect-index: stt $st_src, ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5322,10 +5333,10 @@ SEM_FN_NAME (i960base,stt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* stt-disp: stt $st_src, $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5357,10 +5368,10 @@ SEM_FN_NAME (i960base,stt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stt-indirect-disp: stt $st_src, $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5392,10 +5403,10 @@ SEM_FN_NAME (i960base,stt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stt-index-disp: stt $st_src, $optdisp[$index*S$scale */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5427,10 +5438,10 @@ SEM_FN_NAME (i960base,stt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stt-indirect-index-disp: stt $st_src, $optdisp($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5462,10 +5473,10 @@ SEM_FN_NAME (i960base,stt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* stq-offset: stq $st_src, $offset */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5502,10 +5513,10 @@ SEM_FN_NAME (i960base,stq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stq-indirect-offset: stq $st_src, $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5542,10 +5553,10 @@ SEM_FN_NAME (i960base,stq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar /* stq-indirect: stq $st_src, ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5582,10 +5593,10 @@ SEM_FN_NAME (i960base,stq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stq-indirect-index: stq $st_src, ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5622,10 +5633,10 @@ SEM_FN_NAME (i960base,stq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* stq-disp: stq $st_src, $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5662,10 +5673,10 @@ SEM_FN_NAME (i960base,stq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stq-indirect-disp: stq $st_src, $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5702,10 +5713,10 @@ SEM_FN_NAME (i960base,stq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stq-index-disp: stq $st_src, $optdisp[$index*S$scale */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5742,10 +5753,10 @@ SEM_FN_NAME (i960base,stq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stq-indirect-index-disp: stq $st_src, $optdisp($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,stq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5782,10 +5793,10 @@ SEM_FN_NAME (i960base,stq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se /* cmpobe-reg: cmpobe $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobe_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5795,7 +5806,7 @@ SEM_FN_NAME (i960base,cmpobe_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5809,10 +5820,10 @@ if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpobe-lit: cmpobe $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobe_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5822,7 +5833,7 @@ SEM_FN_NAME (i960base,cmpobe_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5836,10 +5847,10 @@ if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpobne-reg: cmpobne $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5849,7 +5860,7 @@ SEM_FN_NAME (i960base,cmpobne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5863,10 +5874,10 @@ if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpobne-lit: cmpobne $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobne_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5876,7 +5887,7 @@ SEM_FN_NAME (i960base,cmpobne_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5890,10 +5901,10 @@ if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpobl-reg: cmpobl $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5903,7 +5914,7 @@ SEM_FN_NAME (i960base,cmpobl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5917,10 +5928,10 @@ if (LTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpobl-lit: cmpobl $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobl_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5930,7 +5941,7 @@ SEM_FN_NAME (i960base,cmpobl_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5944,10 +5955,10 @@ if (LTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpoble-reg: cmpoble $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpoble_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5957,7 +5968,7 @@ SEM_FN_NAME (i960base,cmpoble_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5971,10 +5982,10 @@ if (LEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpoble-lit: cmpoble $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpoble_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5984,7 +5995,7 @@ SEM_FN_NAME (i960base,cmpoble_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -5998,10 +6009,10 @@ if (LEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpobg-reg: cmpobg $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6011,7 +6022,7 @@ SEM_FN_NAME (i960base,cmpobg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6025,10 +6036,10 @@ if (GTUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpobg-lit: cmpobg $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobg_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6038,7 +6049,7 @@ SEM_FN_NAME (i960base,cmpobg_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6052,10 +6063,10 @@ if (GTUSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpobge-reg: cmpobge $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6065,7 +6076,7 @@ SEM_FN_NAME (i960base,cmpobge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6079,10 +6090,10 @@ if (GEUSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpobge-lit: cmpobge $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpobge_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6092,7 +6103,7 @@ SEM_FN_NAME (i960base,cmpobge_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6106,10 +6117,10 @@ if (GEUSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpibe-reg: cmpibe $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibe_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6119,7 +6130,7 @@ SEM_FN_NAME (i960base,cmpibe_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6133,10 +6144,10 @@ if (EQSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpibe-lit: cmpibe $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibe_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6146,7 +6157,7 @@ SEM_FN_NAME (i960base,cmpibe_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6160,10 +6171,10 @@ if (EQSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpibne-reg: cmpibne $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6173,7 +6184,7 @@ SEM_FN_NAME (i960base,cmpibne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6187,10 +6198,10 @@ if (NESI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpibne-lit: cmpibne $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibne_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6200,7 +6211,7 @@ SEM_FN_NAME (i960base,cmpibne_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6214,10 +6225,10 @@ if (NESI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpibl-reg: cmpibl $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6227,7 +6238,7 @@ SEM_FN_NAME (i960base,cmpibl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6241,10 +6252,10 @@ if (LTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpibl-lit: cmpibl $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibl_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6254,7 +6265,7 @@ SEM_FN_NAME (i960base,cmpibl_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6268,10 +6279,10 @@ if (LTSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpible-reg: cmpible $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpible_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6281,7 +6292,7 @@ SEM_FN_NAME (i960base,cmpible_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6295,10 +6306,10 @@ if (LESI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpible-lit: cmpible $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpible_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6308,7 +6319,7 @@ SEM_FN_NAME (i960base,cmpible_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6322,10 +6333,10 @@ if (LESI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpibg-reg: cmpibg $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6335,7 +6346,7 @@ SEM_FN_NAME (i960base,cmpibg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6349,10 +6360,10 @@ if (GTSI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpibg-lit: cmpibg $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibg_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6362,7 +6373,7 @@ SEM_FN_NAME (i960base,cmpibg_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6376,10 +6387,10 @@ if (GTSI (FLD (f_br_src1), * FLD (i_br_src2))) { /* cmpibge-reg: cmpibge $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6389,7 +6400,7 @@ SEM_FN_NAME (i960base,cmpibge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6403,10 +6414,10 @@ if (GESI (* FLD (i_br_src1), * FLD (i_br_src2))) { /* cmpibge-lit: cmpibge $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpibge_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6416,7 +6427,7 @@ SEM_FN_NAME (i960base,cmpibge_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6430,10 +6441,10 @@ if (GESI (FLD (f_br_src1), * FLD (i_br_src2))) { /* bbc-reg: bbc $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bbc_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6443,7 +6454,7 @@ SEM_FN_NAME (i960base,bbc_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6457,10 +6468,10 @@ if (EQSI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { /* bbc-lit: bbc $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bbc_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6470,7 +6481,7 @@ SEM_FN_NAME (i960base,bbc_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6484,10 +6495,10 @@ if (EQSI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { /* bbs-reg: bbs $br_src1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bbs_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f +#define FLD(f) abuf->fields.sfmt_cmpobe_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6497,7 +6508,7 @@ SEM_FN_NAME (i960base,bbs_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6511,10 +6522,10 @@ if (NESI (ANDSI (SLLSI (1, * FLD (i_br_src1)), * FLD (i_br_src2)), 0)) { /* bbs-lit: bbs $br_lit1, $br_src2, $br_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bbs_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f +#define FLD(f) abuf->fields.sfmt_cmpobe_lit.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6524,7 +6535,7 @@ SEM_FN_NAME (i960base,bbs_lit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { { USI opval = FLD (i_br_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6538,10 +6549,10 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) { /* cmpi: cmpi $src1, $src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6559,10 +6570,10 @@ SEM_FN_NAME (i960base,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpi1: cmpi $lit1, $src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6580,10 +6591,10 @@ SEM_FN_NAME (i960base,cmpi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpi2: cmpi $src1, $lit2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6601,10 +6612,10 @@ SEM_FN_NAME (i960base,cmpi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpi3: cmpi $lit1, $lit2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6622,10 +6633,10 @@ SEM_FN_NAME (i960base,cmpi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpo: cmpo $src1, $src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo.f +#define FLD(f) abuf->fields.sfmt_emul.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6643,10 +6654,10 @@ SEM_FN_NAME (i960base,cmpo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpo1: cmpo $lit1, $src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo1.f +#define FLD(f) abuf->fields.sfmt_emul1.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6664,10 +6675,10 @@ SEM_FN_NAME (i960base,cmpo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpo2: cmpo $src1, $lit2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo2.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6685,10 +6696,10 @@ SEM_FN_NAME (i960base,cmpo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpo3: cmpo $lit1, $lit2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,cmpo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpo3.f +#define FLD(f) abuf->fields.sfmt_emul3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6706,10 +6717,10 @@ SEM_FN_NAME (i960base,cmpo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testno-reg: testno $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testno_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6727,10 +6738,10 @@ SEM_FN_NAME (i960base,testno_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testg-reg: testg $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6748,10 +6759,10 @@ SEM_FN_NAME (i960base,testg_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* teste-reg: teste $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,teste_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6769,10 +6780,10 @@ SEM_FN_NAME (i960base,teste_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testge-reg: testge $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6790,10 +6801,10 @@ SEM_FN_NAME (i960base,testge_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testl-reg: testl $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6811,10 +6822,10 @@ SEM_FN_NAME (i960base,testl_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testne-reg: testne $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6832,10 +6843,10 @@ SEM_FN_NAME (i960base,testne_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testle-reg: testle $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testle_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6853,10 +6864,10 @@ SEM_FN_NAME (i960base,testle_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* testo-reg: testo $br_src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,testo_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_testno_reg.f +#define FLD(f) abuf->fields.sfmt_testno_reg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6874,10 +6885,10 @@ SEM_FN_NAME (i960base,testo_reg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bno: bno $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6887,7 +6898,7 @@ SEM_FN_NAME (i960base,bno) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (CPU (h_cc), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6901,10 +6912,10 @@ if (EQSI (CPU (h_cc), 0)) { /* bg: bg $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6914,7 +6925,7 @@ SEM_FN_NAME (i960base,bg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 1), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6928,10 +6939,10 @@ if (NESI (ANDSI (CPU (h_cc), 1), 0)) { /* be: be $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6941,7 +6952,7 @@ SEM_FN_NAME (i960base,be) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 2), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6955,10 +6966,10 @@ if (NESI (ANDSI (CPU (h_cc), 2), 0)) { /* bge: bge $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6968,7 +6979,7 @@ SEM_FN_NAME (i960base,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 3), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -6982,10 +6993,10 @@ if (NESI (ANDSI (CPU (h_cc), 3), 0)) { /* bl: bl $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -6995,7 +7006,7 @@ SEM_FN_NAME (i960base,bl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 4), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -7009,10 +7020,10 @@ if (NESI (ANDSI (CPU (h_cc), 4), 0)) { /* bne: bne $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7022,7 +7033,7 @@ SEM_FN_NAME (i960base,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 5), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -7036,10 +7047,10 @@ if (NESI (ANDSI (CPU (h_cc), 5), 0)) { /* ble: ble $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7049,7 +7060,7 @@ SEM_FN_NAME (i960base,ble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 6), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -7063,10 +7074,10 @@ if (NESI (ANDSI (CPU (h_cc), 6), 0)) { /* bo: bo $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bno.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7076,7 +7087,7 @@ SEM_FN_NAME (i960base,bo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (ANDSI (CPU (h_cc), 7), 0)) { { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -7090,10 +7101,10 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) { /* b: b $ctrl_disp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_b.f +#define FLD(f) abuf->fields.sfmt_bno.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7102,7 +7113,7 @@ SEM_FN_NAME (i960base,b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { USI opval = FLD (i_ctrl_disp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -7113,10 +7124,10 @@ SEM_FN_NAME (i960base,b) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bx-indirect-offset: bx $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7136,10 +7147,10 @@ SEM_FN_NAME (i960base,bx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg /* bx-indirect: bx ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7159,10 +7170,10 @@ SEM_FN_NAME (i960base,bx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bx-indirect-index: bx ($abase)[$index*S$scale] */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bx_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7182,10 +7193,10 @@ SEM_FN_NAME (i960base,bx_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bx-disp: bx $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7194,7 +7205,7 @@ SEM_FN_NAME (i960base,bx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { USI opval = FLD (f_optdisp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -7205,10 +7216,10 @@ SEM_FN_NAME (i960base,bx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bx-indirect-disp: bx $optdisp($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,bx_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f +#define FLD(f) abuf->fields.sfmt_stq_indirect_index_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7228,10 +7239,10 @@ SEM_FN_NAME (i960base,bx_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* callx-disp: callx $optdisp */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,callx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7264,7 +7275,7 @@ SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 56), CPU (h_gr[((UINT SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31)]), 60), CPU (h_gr[((UINT) 15)])); { USI opval = FLD (f_optdisp); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } CPU (h_gr[((UINT) 0)]) = 0xdeadbeef; @@ -7307,10 +7318,10 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; /* callx-indirect: callx ($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,callx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7386,10 +7397,10 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; /* callx-indirect-offset: callx $offset($abase) */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,callx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f +#define FLD(f) abuf->fields.sfmt_callx_indirect_offset.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7465,10 +7476,10 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef; /* ret: ret */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_ret.f +#define FLD(f) abuf->fields.sfmt_callx_disp.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7511,10 +7522,10 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31 /* calls: calls $src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,calls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_calls.f +#define FLD(f) abuf->fields.sfmt_emul2.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7534,10 +7545,10 @@ SEM_FN_NAME (i960base,calls) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* fmark: fmark */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,fmark) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7557,10 +7568,10 @@ SEM_FN_NAME (i960base,fmark) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* flushreg: flushreg */ -SEM_PC +static SEM_PC SEM_FN_NAME (i960base,flushreg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_flushreg.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -7572,3 +7583,324 @@ do { } while (0); /*nop*/ #undef FLD } +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { I960BASE_INSN_X_INVALID, SEM_FN_NAME (i960base,x_invalid) }, + { I960BASE_INSN_X_AFTER, SEM_FN_NAME (i960base,x_after) }, + { I960BASE_INSN_X_BEFORE, SEM_FN_NAME (i960base,x_before) }, + { I960BASE_INSN_X_CTI_CHAIN, SEM_FN_NAME (i960base,x_cti_chain) }, + { I960BASE_INSN_X_CHAIN, SEM_FN_NAME (i960base,x_chain) }, + { I960BASE_INSN_X_BEGIN, SEM_FN_NAME (i960base,x_begin) }, + { I960BASE_INSN_MULO, SEM_FN_NAME (i960base,mulo) }, + { I960BASE_INSN_MULO1, SEM_FN_NAME (i960base,mulo1) }, + { I960BASE_INSN_MULO2, SEM_FN_NAME (i960base,mulo2) }, + { I960BASE_INSN_MULO3, SEM_FN_NAME (i960base,mulo3) }, + { I960BASE_INSN_REMO, SEM_FN_NAME (i960base,remo) }, + { I960BASE_INSN_REMO1, SEM_FN_NAME (i960base,remo1) }, + { I960BASE_INSN_REMO2, SEM_FN_NAME (i960base,remo2) }, + { I960BASE_INSN_REMO3, SEM_FN_NAME (i960base,remo3) }, + { I960BASE_INSN_DIVO, SEM_FN_NAME (i960base,divo) }, + { I960BASE_INSN_DIVO1, SEM_FN_NAME (i960base,divo1) }, + { I960BASE_INSN_DIVO2, SEM_FN_NAME (i960base,divo2) }, + { I960BASE_INSN_DIVO3, SEM_FN_NAME (i960base,divo3) }, + { I960BASE_INSN_REMI, SEM_FN_NAME (i960base,remi) }, + { I960BASE_INSN_REMI1, SEM_FN_NAME (i960base,remi1) }, + { I960BASE_INSN_REMI2, SEM_FN_NAME (i960base,remi2) }, + { I960BASE_INSN_REMI3, SEM_FN_NAME (i960base,remi3) }, + { I960BASE_INSN_DIVI, SEM_FN_NAME (i960base,divi) }, + { I960BASE_INSN_DIVI1, SEM_FN_NAME (i960base,divi1) }, + { I960BASE_INSN_DIVI2, SEM_FN_NAME (i960base,divi2) }, + { I960BASE_INSN_DIVI3, SEM_FN_NAME (i960base,divi3) }, + { I960BASE_INSN_ADDO, SEM_FN_NAME (i960base,addo) }, + { I960BASE_INSN_ADDO1, SEM_FN_NAME (i960base,addo1) }, + { I960BASE_INSN_ADDO2, SEM_FN_NAME (i960base,addo2) }, + { I960BASE_INSN_ADDO3, SEM_FN_NAME (i960base,addo3) }, + { I960BASE_INSN_SUBO, SEM_FN_NAME (i960base,subo) }, + { I960BASE_INSN_SUBO1, SEM_FN_NAME (i960base,subo1) }, + { I960BASE_INSN_SUBO2, SEM_FN_NAME (i960base,subo2) }, + { I960BASE_INSN_SUBO3, SEM_FN_NAME (i960base,subo3) }, + { I960BASE_INSN_NOTBIT, SEM_FN_NAME (i960base,notbit) }, + { I960BASE_INSN_NOTBIT1, SEM_FN_NAME (i960base,notbit1) }, + { I960BASE_INSN_NOTBIT2, SEM_FN_NAME (i960base,notbit2) }, + { I960BASE_INSN_NOTBIT3, SEM_FN_NAME (i960base,notbit3) }, + { I960BASE_INSN_AND, SEM_FN_NAME (i960base,and) }, + { I960BASE_INSN_AND1, SEM_FN_NAME (i960base,and1) }, + { I960BASE_INSN_AND2, SEM_FN_NAME (i960base,and2) }, + { I960BASE_INSN_AND3, SEM_FN_NAME (i960base,and3) }, + { I960BASE_INSN_ANDNOT, SEM_FN_NAME (i960base,andnot) }, + { I960BASE_INSN_ANDNOT1, SEM_FN_NAME (i960base,andnot1) }, + { I960BASE_INSN_ANDNOT2, SEM_FN_NAME (i960base,andnot2) }, + { I960BASE_INSN_ANDNOT3, SEM_FN_NAME (i960base,andnot3) }, + { I960BASE_INSN_SETBIT, SEM_FN_NAME (i960base,setbit) }, + { I960BASE_INSN_SETBIT1, SEM_FN_NAME (i960base,setbit1) }, + { I960BASE_INSN_SETBIT2, SEM_FN_NAME (i960base,setbit2) }, + { I960BASE_INSN_SETBIT3, SEM_FN_NAME (i960base,setbit3) }, + { I960BASE_INSN_NOTAND, SEM_FN_NAME (i960base,notand) }, + { I960BASE_INSN_NOTAND1, SEM_FN_NAME (i960base,notand1) }, + { I960BASE_INSN_NOTAND2, SEM_FN_NAME (i960base,notand2) }, + { I960BASE_INSN_NOTAND3, SEM_FN_NAME (i960base,notand3) }, + { I960BASE_INSN_XOR, SEM_FN_NAME (i960base,xor) }, + { I960BASE_INSN_XOR1, SEM_FN_NAME (i960base,xor1) }, + { I960BASE_INSN_XOR2, SEM_FN_NAME (i960base,xor2) }, + { I960BASE_INSN_XOR3, SEM_FN_NAME (i960base,xor3) }, + { I960BASE_INSN_OR, SEM_FN_NAME (i960base,or) }, + { I960BASE_INSN_OR1, SEM_FN_NAME (i960base,or1) }, + { I960BASE_INSN_OR2, SEM_FN_NAME (i960base,or2) }, + { I960BASE_INSN_OR3, SEM_FN_NAME (i960base,or3) }, + { I960BASE_INSN_NOR, SEM_FN_NAME (i960base,nor) }, + { I960BASE_INSN_NOR1, SEM_FN_NAME (i960base,nor1) }, + { I960BASE_INSN_NOR2, SEM_FN_NAME (i960base,nor2) }, + { I960BASE_INSN_NOR3, SEM_FN_NAME (i960base,nor3) }, + { I960BASE_INSN_XNOR, SEM_FN_NAME (i960base,xnor) }, + { I960BASE_INSN_XNOR1, SEM_FN_NAME (i960base,xnor1) }, + { I960BASE_INSN_XNOR2, SEM_FN_NAME (i960base,xnor2) }, + { I960BASE_INSN_XNOR3, SEM_FN_NAME (i960base,xnor3) }, + { I960BASE_INSN_NOT, SEM_FN_NAME (i960base,not) }, + { I960BASE_INSN_NOT1, SEM_FN_NAME (i960base,not1) }, + { I960BASE_INSN_NOT2, SEM_FN_NAME (i960base,not2) }, + { I960BASE_INSN_NOT3, SEM_FN_NAME (i960base,not3) }, + { I960BASE_INSN_ORNOT, SEM_FN_NAME (i960base,ornot) }, + { I960BASE_INSN_ORNOT1, SEM_FN_NAME (i960base,ornot1) }, + { I960BASE_INSN_ORNOT2, SEM_FN_NAME (i960base,ornot2) }, + { I960BASE_INSN_ORNOT3, SEM_FN_NAME (i960base,ornot3) }, + { I960BASE_INSN_CLRBIT, SEM_FN_NAME (i960base,clrbit) }, + { I960BASE_INSN_CLRBIT1, SEM_FN_NAME (i960base,clrbit1) }, + { I960BASE_INSN_CLRBIT2, SEM_FN_NAME (i960base,clrbit2) }, + { I960BASE_INSN_CLRBIT3, SEM_FN_NAME (i960base,clrbit3) }, + { I960BASE_INSN_SHLO, SEM_FN_NAME (i960base,shlo) }, + { I960BASE_INSN_SHLO1, SEM_FN_NAME (i960base,shlo1) }, + { I960BASE_INSN_SHLO2, SEM_FN_NAME (i960base,shlo2) }, + { I960BASE_INSN_SHLO3, SEM_FN_NAME (i960base,shlo3) }, + { I960BASE_INSN_SHRO, SEM_FN_NAME (i960base,shro) }, + { I960BASE_INSN_SHRO1, SEM_FN_NAME (i960base,shro1) }, + { I960BASE_INSN_SHRO2, SEM_FN_NAME (i960base,shro2) }, + { I960BASE_INSN_SHRO3, SEM_FN_NAME (i960base,shro3) }, + { I960BASE_INSN_SHLI, SEM_FN_NAME (i960base,shli) }, + { I960BASE_INSN_SHLI1, SEM_FN_NAME (i960base,shli1) }, + { I960BASE_INSN_SHLI2, SEM_FN_NAME (i960base,shli2) }, + { I960BASE_INSN_SHLI3, SEM_FN_NAME (i960base,shli3) }, + { I960BASE_INSN_SHRI, SEM_FN_NAME (i960base,shri) }, + { I960BASE_INSN_SHRI1, SEM_FN_NAME (i960base,shri1) }, + { I960BASE_INSN_SHRI2, SEM_FN_NAME (i960base,shri2) }, + { I960BASE_INSN_SHRI3, SEM_FN_NAME (i960base,shri3) }, + { I960BASE_INSN_EMUL, SEM_FN_NAME (i960base,emul) }, + { I960BASE_INSN_EMUL1, SEM_FN_NAME (i960base,emul1) }, + { I960BASE_INSN_EMUL2, SEM_FN_NAME (i960base,emul2) }, + { I960BASE_INSN_EMUL3, SEM_FN_NAME (i960base,emul3) }, + { I960BASE_INSN_MOV, SEM_FN_NAME (i960base,mov) }, + { I960BASE_INSN_MOV1, SEM_FN_NAME (i960base,mov1) }, + { I960BASE_INSN_MOVL, SEM_FN_NAME (i960base,movl) }, + { I960BASE_INSN_MOVL1, SEM_FN_NAME (i960base,movl1) }, + { I960BASE_INSN_MOVT, SEM_FN_NAME (i960base,movt) }, + { I960BASE_INSN_MOVT1, SEM_FN_NAME (i960base,movt1) }, + { I960BASE_INSN_MOVQ, SEM_FN_NAME (i960base,movq) }, + { I960BASE_INSN_MOVQ1, SEM_FN_NAME (i960base,movq1) }, + { I960BASE_INSN_MODPC, SEM_FN_NAME (i960base,modpc) }, + { I960BASE_INSN_MODAC, SEM_FN_NAME (i960base,modac) }, + { I960BASE_INSN_LDA_OFFSET, SEM_FN_NAME (i960base,lda_offset) }, + { I960BASE_INSN_LDA_INDIRECT_OFFSET, SEM_FN_NAME (i960base,lda_indirect_offset) }, + { I960BASE_INSN_LDA_INDIRECT, SEM_FN_NAME (i960base,lda_indirect) }, + { I960BASE_INSN_LDA_INDIRECT_INDEX, SEM_FN_NAME (i960base,lda_indirect_index) }, + { I960BASE_INSN_LDA_DISP, SEM_FN_NAME (i960base,lda_disp) }, + { I960BASE_INSN_LDA_INDIRECT_DISP, SEM_FN_NAME (i960base,lda_indirect_disp) }, + { I960BASE_INSN_LDA_INDEX_DISP, SEM_FN_NAME (i960base,lda_index_disp) }, + { I960BASE_INSN_LDA_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,lda_indirect_index_disp) }, + { I960BASE_INSN_LD_OFFSET, SEM_FN_NAME (i960base,ld_offset) }, + { I960BASE_INSN_LD_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ld_indirect_offset) }, + { I960BASE_INSN_LD_INDIRECT, SEM_FN_NAME (i960base,ld_indirect) }, + { I960BASE_INSN_LD_INDIRECT_INDEX, SEM_FN_NAME (i960base,ld_indirect_index) }, + { I960BASE_INSN_LD_DISP, SEM_FN_NAME (i960base,ld_disp) }, + { I960BASE_INSN_LD_INDIRECT_DISP, SEM_FN_NAME (i960base,ld_indirect_disp) }, + { I960BASE_INSN_LD_INDEX_DISP, SEM_FN_NAME (i960base,ld_index_disp) }, + { I960BASE_INSN_LD_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ld_indirect_index_disp) }, + { I960BASE_INSN_LDOB_OFFSET, SEM_FN_NAME (i960base,ldob_offset) }, + { I960BASE_INSN_LDOB_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldob_indirect_offset) }, + { I960BASE_INSN_LDOB_INDIRECT, SEM_FN_NAME (i960base,ldob_indirect) }, + { I960BASE_INSN_LDOB_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldob_indirect_index) }, + { I960BASE_INSN_LDOB_DISP, SEM_FN_NAME (i960base,ldob_disp) }, + { I960BASE_INSN_LDOB_INDIRECT_DISP, SEM_FN_NAME (i960base,ldob_indirect_disp) }, + { I960BASE_INSN_LDOB_INDEX_DISP, SEM_FN_NAME (i960base,ldob_index_disp) }, + { I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldob_indirect_index_disp) }, + { I960BASE_INSN_LDOS_OFFSET, SEM_FN_NAME (i960base,ldos_offset) }, + { I960BASE_INSN_LDOS_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldos_indirect_offset) }, + { I960BASE_INSN_LDOS_INDIRECT, SEM_FN_NAME (i960base,ldos_indirect) }, + { I960BASE_INSN_LDOS_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldos_indirect_index) }, + { I960BASE_INSN_LDOS_DISP, SEM_FN_NAME (i960base,ldos_disp) }, + { I960BASE_INSN_LDOS_INDIRECT_DISP, SEM_FN_NAME (i960base,ldos_indirect_disp) }, + { I960BASE_INSN_LDOS_INDEX_DISP, SEM_FN_NAME (i960base,ldos_index_disp) }, + { I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldos_indirect_index_disp) }, + { I960BASE_INSN_LDIB_OFFSET, SEM_FN_NAME (i960base,ldib_offset) }, + { I960BASE_INSN_LDIB_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldib_indirect_offset) }, + { I960BASE_INSN_LDIB_INDIRECT, SEM_FN_NAME (i960base,ldib_indirect) }, + { I960BASE_INSN_LDIB_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldib_indirect_index) }, + { I960BASE_INSN_LDIB_DISP, SEM_FN_NAME (i960base,ldib_disp) }, + { I960BASE_INSN_LDIB_INDIRECT_DISP, SEM_FN_NAME (i960base,ldib_indirect_disp) }, + { I960BASE_INSN_LDIB_INDEX_DISP, SEM_FN_NAME (i960base,ldib_index_disp) }, + { I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldib_indirect_index_disp) }, + { I960BASE_INSN_LDIS_OFFSET, SEM_FN_NAME (i960base,ldis_offset) }, + { I960BASE_INSN_LDIS_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldis_indirect_offset) }, + { I960BASE_INSN_LDIS_INDIRECT, SEM_FN_NAME (i960base,ldis_indirect) }, + { I960BASE_INSN_LDIS_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldis_indirect_index) }, + { I960BASE_INSN_LDIS_DISP, SEM_FN_NAME (i960base,ldis_disp) }, + { I960BASE_INSN_LDIS_INDIRECT_DISP, SEM_FN_NAME (i960base,ldis_indirect_disp) }, + { I960BASE_INSN_LDIS_INDEX_DISP, SEM_FN_NAME (i960base,ldis_index_disp) }, + { I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldis_indirect_index_disp) }, + { I960BASE_INSN_LDL_OFFSET, SEM_FN_NAME (i960base,ldl_offset) }, + { I960BASE_INSN_LDL_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldl_indirect_offset) }, + { I960BASE_INSN_LDL_INDIRECT, SEM_FN_NAME (i960base,ldl_indirect) }, + { I960BASE_INSN_LDL_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldl_indirect_index) }, + { I960BASE_INSN_LDL_DISP, SEM_FN_NAME (i960base,ldl_disp) }, + { I960BASE_INSN_LDL_INDIRECT_DISP, SEM_FN_NAME (i960base,ldl_indirect_disp) }, + { I960BASE_INSN_LDL_INDEX_DISP, SEM_FN_NAME (i960base,ldl_index_disp) }, + { I960BASE_INSN_LDL_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldl_indirect_index_disp) }, + { I960BASE_INSN_LDT_OFFSET, SEM_FN_NAME (i960base,ldt_offset) }, + { I960BASE_INSN_LDT_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldt_indirect_offset) }, + { I960BASE_INSN_LDT_INDIRECT, SEM_FN_NAME (i960base,ldt_indirect) }, + { I960BASE_INSN_LDT_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldt_indirect_index) }, + { I960BASE_INSN_LDT_DISP, SEM_FN_NAME (i960base,ldt_disp) }, + { I960BASE_INSN_LDT_INDIRECT_DISP, SEM_FN_NAME (i960base,ldt_indirect_disp) }, + { I960BASE_INSN_LDT_INDEX_DISP, SEM_FN_NAME (i960base,ldt_index_disp) }, + { I960BASE_INSN_LDT_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldt_indirect_index_disp) }, + { I960BASE_INSN_LDQ_OFFSET, SEM_FN_NAME (i960base,ldq_offset) }, + { I960BASE_INSN_LDQ_INDIRECT_OFFSET, SEM_FN_NAME (i960base,ldq_indirect_offset) }, + { I960BASE_INSN_LDQ_INDIRECT, SEM_FN_NAME (i960base,ldq_indirect) }, + { I960BASE_INSN_LDQ_INDIRECT_INDEX, SEM_FN_NAME (i960base,ldq_indirect_index) }, + { I960BASE_INSN_LDQ_DISP, SEM_FN_NAME (i960base,ldq_disp) }, + { I960BASE_INSN_LDQ_INDIRECT_DISP, SEM_FN_NAME (i960base,ldq_indirect_disp) }, + { I960BASE_INSN_LDQ_INDEX_DISP, SEM_FN_NAME (i960base,ldq_index_disp) }, + { I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,ldq_indirect_index_disp) }, + { I960BASE_INSN_ST_OFFSET, SEM_FN_NAME (i960base,st_offset) }, + { I960BASE_INSN_ST_INDIRECT_OFFSET, SEM_FN_NAME (i960base,st_indirect_offset) }, + { I960BASE_INSN_ST_INDIRECT, SEM_FN_NAME (i960base,st_indirect) }, + { I960BASE_INSN_ST_INDIRECT_INDEX, SEM_FN_NAME (i960base,st_indirect_index) }, + { I960BASE_INSN_ST_DISP, SEM_FN_NAME (i960base,st_disp) }, + { I960BASE_INSN_ST_INDIRECT_DISP, SEM_FN_NAME (i960base,st_indirect_disp) }, + { I960BASE_INSN_ST_INDEX_DISP, SEM_FN_NAME (i960base,st_index_disp) }, + { I960BASE_INSN_ST_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,st_indirect_index_disp) }, + { I960BASE_INSN_STOB_OFFSET, SEM_FN_NAME (i960base,stob_offset) }, + { I960BASE_INSN_STOB_INDIRECT_OFFSET, SEM_FN_NAME (i960base,stob_indirect_offset) }, + { I960BASE_INSN_STOB_INDIRECT, SEM_FN_NAME (i960base,stob_indirect) }, + { I960BASE_INSN_STOB_INDIRECT_INDEX, SEM_FN_NAME (i960base,stob_indirect_index) }, + { I960BASE_INSN_STOB_DISP, SEM_FN_NAME (i960base,stob_disp) }, + { I960BASE_INSN_STOB_INDIRECT_DISP, SEM_FN_NAME (i960base,stob_indirect_disp) }, + { I960BASE_INSN_STOB_INDEX_DISP, SEM_FN_NAME (i960base,stob_index_disp) }, + { I960BASE_INSN_STOB_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,stob_indirect_index_disp) }, + { I960BASE_INSN_STOS_OFFSET, SEM_FN_NAME (i960base,stos_offset) }, + { I960BASE_INSN_STOS_INDIRECT_OFFSET, SEM_FN_NAME (i960base,stos_indirect_offset) }, + { I960BASE_INSN_STOS_INDIRECT, SEM_FN_NAME (i960base,stos_indirect) }, + { I960BASE_INSN_STOS_INDIRECT_INDEX, SEM_FN_NAME (i960base,stos_indirect_index) }, + { I960BASE_INSN_STOS_DISP, SEM_FN_NAME (i960base,stos_disp) }, + { I960BASE_INSN_STOS_INDIRECT_DISP, SEM_FN_NAME (i960base,stos_indirect_disp) }, + { I960BASE_INSN_STOS_INDEX_DISP, SEM_FN_NAME (i960base,stos_index_disp) }, + { I960BASE_INSN_STOS_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,stos_indirect_index_disp) }, + { I960BASE_INSN_STL_OFFSET, SEM_FN_NAME (i960base,stl_offset) }, + { I960BASE_INSN_STL_INDIRECT_OFFSET, SEM_FN_NAME (i960base,stl_indirect_offset) }, + { I960BASE_INSN_STL_INDIRECT, SEM_FN_NAME (i960base,stl_indirect) }, + { I960BASE_INSN_STL_INDIRECT_INDEX, SEM_FN_NAME (i960base,stl_indirect_index) }, + { I960BASE_INSN_STL_DISP, SEM_FN_NAME (i960base,stl_disp) }, + { I960BASE_INSN_STL_INDIRECT_DISP, SEM_FN_NAME (i960base,stl_indirect_disp) }, + { I960BASE_INSN_STL_INDEX_DISP, SEM_FN_NAME (i960base,stl_index_disp) }, + { I960BASE_INSN_STL_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,stl_indirect_index_disp) }, + { I960BASE_INSN_STT_OFFSET, SEM_FN_NAME (i960base,stt_offset) }, + { I960BASE_INSN_STT_INDIRECT_OFFSET, SEM_FN_NAME (i960base,stt_indirect_offset) }, + { I960BASE_INSN_STT_INDIRECT, SEM_FN_NAME (i960base,stt_indirect) }, + { I960BASE_INSN_STT_INDIRECT_INDEX, SEM_FN_NAME (i960base,stt_indirect_index) }, + { I960BASE_INSN_STT_DISP, SEM_FN_NAME (i960base,stt_disp) }, + { I960BASE_INSN_STT_INDIRECT_DISP, SEM_FN_NAME (i960base,stt_indirect_disp) }, + { I960BASE_INSN_STT_INDEX_DISP, SEM_FN_NAME (i960base,stt_index_disp) }, + { I960BASE_INSN_STT_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,stt_indirect_index_disp) }, + { I960BASE_INSN_STQ_OFFSET, SEM_FN_NAME (i960base,stq_offset) }, + { I960BASE_INSN_STQ_INDIRECT_OFFSET, SEM_FN_NAME (i960base,stq_indirect_offset) }, + { I960BASE_INSN_STQ_INDIRECT, SEM_FN_NAME (i960base,stq_indirect) }, + { I960BASE_INSN_STQ_INDIRECT_INDEX, SEM_FN_NAME (i960base,stq_indirect_index) }, + { I960BASE_INSN_STQ_DISP, SEM_FN_NAME (i960base,stq_disp) }, + { I960BASE_INSN_STQ_INDIRECT_DISP, SEM_FN_NAME (i960base,stq_indirect_disp) }, + { I960BASE_INSN_STQ_INDEX_DISP, SEM_FN_NAME (i960base,stq_index_disp) }, + { I960BASE_INSN_STQ_INDIRECT_INDEX_DISP, SEM_FN_NAME (i960base,stq_indirect_index_disp) }, + { I960BASE_INSN_CMPOBE_REG, SEM_FN_NAME (i960base,cmpobe_reg) }, + { I960BASE_INSN_CMPOBE_LIT, SEM_FN_NAME (i960base,cmpobe_lit) }, + { I960BASE_INSN_CMPOBNE_REG, SEM_FN_NAME (i960base,cmpobne_reg) }, + { I960BASE_INSN_CMPOBNE_LIT, SEM_FN_NAME (i960base,cmpobne_lit) }, + { I960BASE_INSN_CMPOBL_REG, SEM_FN_NAME (i960base,cmpobl_reg) }, + { I960BASE_INSN_CMPOBL_LIT, SEM_FN_NAME (i960base,cmpobl_lit) }, + { I960BASE_INSN_CMPOBLE_REG, SEM_FN_NAME (i960base,cmpoble_reg) }, + { I960BASE_INSN_CMPOBLE_LIT, SEM_FN_NAME (i960base,cmpoble_lit) }, + { I960BASE_INSN_CMPOBG_REG, SEM_FN_NAME (i960base,cmpobg_reg) }, + { I960BASE_INSN_CMPOBG_LIT, SEM_FN_NAME (i960base,cmpobg_lit) }, + { I960BASE_INSN_CMPOBGE_REG, SEM_FN_NAME (i960base,cmpobge_reg) }, + { I960BASE_INSN_CMPOBGE_LIT, SEM_FN_NAME (i960base,cmpobge_lit) }, + { I960BASE_INSN_CMPIBE_REG, SEM_FN_NAME (i960base,cmpibe_reg) }, + { I960BASE_INSN_CMPIBE_LIT, SEM_FN_NAME (i960base,cmpibe_lit) }, + { I960BASE_INSN_CMPIBNE_REG, SEM_FN_NAME (i960base,cmpibne_reg) }, + { I960BASE_INSN_CMPIBNE_LIT, SEM_FN_NAME (i960base,cmpibne_lit) }, + { I960BASE_INSN_CMPIBL_REG, SEM_FN_NAME (i960base,cmpibl_reg) }, + { I960BASE_INSN_CMPIBL_LIT, SEM_FN_NAME (i960base,cmpibl_lit) }, + { I960BASE_INSN_CMPIBLE_REG, SEM_FN_NAME (i960base,cmpible_reg) }, + { I960BASE_INSN_CMPIBLE_LIT, SEM_FN_NAME (i960base,cmpible_lit) }, + { I960BASE_INSN_CMPIBG_REG, SEM_FN_NAME (i960base,cmpibg_reg) }, + { I960BASE_INSN_CMPIBG_LIT, SEM_FN_NAME (i960base,cmpibg_lit) }, + { I960BASE_INSN_CMPIBGE_REG, SEM_FN_NAME (i960base,cmpibge_reg) }, + { I960BASE_INSN_CMPIBGE_LIT, SEM_FN_NAME (i960base,cmpibge_lit) }, + { I960BASE_INSN_BBC_REG, SEM_FN_NAME (i960base,bbc_reg) }, + { I960BASE_INSN_BBC_LIT, SEM_FN_NAME (i960base,bbc_lit) }, + { I960BASE_INSN_BBS_REG, SEM_FN_NAME (i960base,bbs_reg) }, + { I960BASE_INSN_BBS_LIT, SEM_FN_NAME (i960base,bbs_lit) }, + { I960BASE_INSN_CMPI, SEM_FN_NAME (i960base,cmpi) }, + { I960BASE_INSN_CMPI1, SEM_FN_NAME (i960base,cmpi1) }, + { I960BASE_INSN_CMPI2, SEM_FN_NAME (i960base,cmpi2) }, + { I960BASE_INSN_CMPI3, SEM_FN_NAME (i960base,cmpi3) }, + { I960BASE_INSN_CMPO, SEM_FN_NAME (i960base,cmpo) }, + { I960BASE_INSN_CMPO1, SEM_FN_NAME (i960base,cmpo1) }, + { I960BASE_INSN_CMPO2, SEM_FN_NAME (i960base,cmpo2) }, + { I960BASE_INSN_CMPO3, SEM_FN_NAME (i960base,cmpo3) }, + { I960BASE_INSN_TESTNO_REG, SEM_FN_NAME (i960base,testno_reg) }, + { I960BASE_INSN_TESTG_REG, SEM_FN_NAME (i960base,testg_reg) }, + { I960BASE_INSN_TESTE_REG, SEM_FN_NAME (i960base,teste_reg) }, + { I960BASE_INSN_TESTGE_REG, SEM_FN_NAME (i960base,testge_reg) }, + { I960BASE_INSN_TESTL_REG, SEM_FN_NAME (i960base,testl_reg) }, + { I960BASE_INSN_TESTNE_REG, SEM_FN_NAME (i960base,testne_reg) }, + { I960BASE_INSN_TESTLE_REG, SEM_FN_NAME (i960base,testle_reg) }, + { I960BASE_INSN_TESTO_REG, SEM_FN_NAME (i960base,testo_reg) }, + { I960BASE_INSN_BNO, SEM_FN_NAME (i960base,bno) }, + { I960BASE_INSN_BG, SEM_FN_NAME (i960base,bg) }, + { I960BASE_INSN_BE, SEM_FN_NAME (i960base,be) }, + { I960BASE_INSN_BGE, SEM_FN_NAME (i960base,bge) }, + { I960BASE_INSN_BL, SEM_FN_NAME (i960base,bl) }, + { I960BASE_INSN_BNE, SEM_FN_NAME (i960base,bne) }, + { I960BASE_INSN_BLE, SEM_FN_NAME (i960base,ble) }, + { I960BASE_INSN_BO, SEM_FN_NAME (i960base,bo) }, + { I960BASE_INSN_B, SEM_FN_NAME (i960base,b) }, + { I960BASE_INSN_BX_INDIRECT_OFFSET, SEM_FN_NAME (i960base,bx_indirect_offset) }, + { I960BASE_INSN_BX_INDIRECT, SEM_FN_NAME (i960base,bx_indirect) }, + { I960BASE_INSN_BX_INDIRECT_INDEX, SEM_FN_NAME (i960base,bx_indirect_index) }, + { I960BASE_INSN_BX_DISP, SEM_FN_NAME (i960base,bx_disp) }, + { I960BASE_INSN_BX_INDIRECT_DISP, SEM_FN_NAME (i960base,bx_indirect_disp) }, + { I960BASE_INSN_CALLX_DISP, SEM_FN_NAME (i960base,callx_disp) }, + { I960BASE_INSN_CALLX_INDIRECT, SEM_FN_NAME (i960base,callx_indirect) }, + { I960BASE_INSN_CALLX_INDIRECT_OFFSET, SEM_FN_NAME (i960base,callx_indirect_offset) }, + { I960BASE_INSN_RET, SEM_FN_NAME (i960base,ret) }, + { I960BASE_INSN_CALLS, SEM_FN_NAME (i960base,calls) }, + { I960BASE_INSN_FMARK, SEM_FN_NAME (i960base,fmark) }, + { I960BASE_INSN_FLUSHREG, SEM_FN_NAME (i960base,flushreg) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (i960base,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { +#if FAST_P + idesc_table[sf->index].sem_fast = sf->fn; +#else + idesc_table[sf->index].sem_full = sf->fn; +#endif + } +} + diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index 2202b86..1f7f3d4 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,12 @@ +1999-08-09 Doug Evans + + * cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild. + +1999-08-04 Doug Evans + + * m32r-sim.h (SEM_SKIP_INSN): Delete. + * cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild. + 1999-05-08 Felix Lee * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 6ebe199..fa475d5 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -117,317 +117,109 @@ typedef struct { int empty; } MODEL_TEST_DATA; +/* Instruction argument buffer. */ + union sem_fields { - struct { /* empty sformat for unspecified field list */ - int empty; - } fmt_empty; - struct { /* e.g. add $dr,$sr */ - SI * i_dr; - SI * i_sr; - unsigned char in_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_add; - struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ - INT f_simm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_add3; - struct { /* e.g. and3 $dr,$sr,$uimm16 */ - UINT f_uimm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_and3; - struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ - UINT f_uimm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_or3; - struct { /* e.g. addi $dr,$simm8 */ - INT f_simm8; - SI * i_dr; - unsigned char in_dr; - unsigned char out_dr; - } fmt_addi; - struct { /* e.g. addv $dr,$sr */ - SI * i_dr; - SI * i_sr; - unsigned char in_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_addv; - struct { /* e.g. addv3 $dr,$sr,$simm16 */ - INT f_simm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_addv3; - struct { /* e.g. addx $dr,$sr */ - SI * i_dr; - SI * i_sr; - unsigned char in_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_addx; - struct { /* e.g. cmp $src1,$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_cmp; - struct { /* e.g. cmpi $src2,$simm16 */ - INT f_simm16; - SI * i_src2; - unsigned char in_src2; - } fmt_cmpi; - struct { /* e.g. div $dr,$sr */ - SI * i_dr; - SI * i_sr; - unsigned char in_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_div; - struct { /* e.g. ld $dr,@$sr */ - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_ld; - struct { /* e.g. ld $dr,@($slo16,$sr) */ - INT f_simm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_ld_d; - struct { /* e.g. ldb $dr,@$sr */ - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_ldb; - struct { /* e.g. ldb $dr,@($slo16,$sr) */ - INT f_simm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_ldb_d; - struct { /* e.g. ldh $dr,@$sr */ - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_ldh; - struct { /* e.g. ldh $dr,@($slo16,$sr) */ - INT f_simm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_ldh_d; - struct { /* e.g. ld $dr,@$sr+ */ - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - unsigned char out_sr; - } fmt_ld_plus; - struct { /* e.g. ld24 $dr,$uimm24 */ - ADDR i_uimm24; - SI * i_dr; - unsigned char out_dr; - } fmt_ld24; - struct { /* e.g. ldi8 $dr,$simm8 */ - INT f_simm8; - SI * i_dr; - unsigned char out_dr; - } fmt_ldi8; - struct { /* e.g. ldi16 $dr,$hash$slo16 */ - INT f_simm16; - SI * i_dr; - unsigned char out_dr; - } fmt_ldi16; - struct { /* e.g. lock $dr,@$sr */ - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_lock; - struct { /* e.g. machi $src1,$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_machi; - struct { /* e.g. mulhi $src1,$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_mulhi; - struct { /* e.g. mv $dr,$sr */ - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_mv; - struct { /* e.g. mvfachi $dr */ - SI * i_dr; - unsigned char out_dr; - } fmt_mvfachi; - struct { /* e.g. mvfc $dr,$scr */ - UINT f_r2; - SI * i_dr; - unsigned char out_dr; - } fmt_mvfc; - struct { /* e.g. mvtachi $src1 */ - SI * i_src1; - unsigned char in_src1; - } fmt_mvtachi; - struct { /* e.g. mvtc $sr,$dcr */ - UINT f_r1; - SI * i_sr; - unsigned char in_sr; - } fmt_mvtc; - struct { /* e.g. nop */ - int empty; - } fmt_nop; - struct { /* e.g. rac */ - int empty; - } fmt_rac; - struct { /* e.g. seth $dr,$hash$hi16 */ - UINT f_hi16; - SI * i_dr; - unsigned char out_dr; - } fmt_seth; - struct { /* e.g. sll3 $dr,$sr,$simm16 */ - INT f_simm16; - SI * i_sr; - SI * i_dr; - unsigned char in_sr; - unsigned char out_dr; - } fmt_sll3; - struct { /* e.g. slli $dr,$uimm5 */ - UINT f_uimm5; - SI * i_dr; - unsigned char in_dr; - unsigned char out_dr; - } fmt_slli; - struct { /* e.g. st $src1,@$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_st; - struct { /* e.g. st $src1,@($slo16,$src2) */ - INT f_simm16; - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_st_d; - struct { /* e.g. stb $src1,@$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_stb; - struct { /* e.g. stb $src1,@($slo16,$src2) */ - INT f_simm16; - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_stb_d; - struct { /* e.g. sth $src1,@$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_sth; - struct { /* e.g. sth $src1,@($slo16,$src2) */ - INT f_simm16; - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_sth_d; - struct { /* e.g. st $src1,@+$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - unsigned char out_src2; - } fmt_st_plus; - struct { /* e.g. unlock $src1,@$src2 */ - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_unlock; - /* cti insns, kept separately so addr_cache is in fixed place */ - struct { - union { - struct { /* e.g. bc.s $disp8 */ - IADDR i_disp8; - } fmt_bc8; - struct { /* e.g. bc.l $disp24 */ - IADDR i_disp24; - } fmt_bc24; - struct { /* e.g. beq $src1,$src2,$disp16 */ - IADDR i_disp16; - SI * i_src1; - SI * i_src2; - unsigned char in_src1; - unsigned char in_src2; - } fmt_beq; - struct { /* e.g. beqz $src2,$disp16 */ - IADDR i_disp16; - SI * i_src2; - unsigned char in_src2; - } fmt_beqz; - struct { /* e.g. bl.s $disp8 */ - IADDR i_disp8; - unsigned char out_h_gr_14; - } fmt_bl8; - struct { /* e.g. bl.l $disp24 */ - IADDR i_disp24; - unsigned char out_h_gr_14; - } fmt_bl24; - struct { /* e.g. bra.s $disp8 */ - IADDR i_disp8; - } fmt_bra8; - struct { /* e.g. bra.l $disp24 */ - IADDR i_disp24; - } fmt_bra24; - struct { /* e.g. jl $sr */ - SI * i_sr; - unsigned char in_sr; - unsigned char out_h_gr_14; - } fmt_jl; - struct { /* e.g. jmp $sr */ - SI * i_sr; - unsigned char in_sr; - } fmt_jmp; - struct { /* e.g. rte */ - int empty; - } fmt_rte; - struct { /* e.g. trap $uimm4 */ - UINT f_uimm4; - } fmt_trap; - } fields; -#if WITH_SCACHE_PBB - SEM_PC addr_cache; -#endif - } cti; + struct { /* no operands */ + int empty; + } fmt_empty; + struct { /* */ + UINT f_uimm4; + } sfmt_trap; + struct { /* */ + IADDR i_disp24; + unsigned char out_h_gr_14; + } sfmt_bl24; + struct { /* */ + IADDR i_disp8; + unsigned char out_h_gr_14; + } sfmt_bl8; + struct { /* */ + SI* i_dr; + UINT f_hi16; + unsigned char out_dr; + } sfmt_seth; + struct { /* */ + SI* i_sr; + UINT f_r1; + unsigned char in_sr; + } sfmt_mvtc; + struct { /* */ + SI* i_dr; + UINT f_r2; + unsigned char out_dr; + } sfmt_mvfc; + struct { /* */ + ADDR i_uimm24; + SI* i_dr; + unsigned char out_dr; + } sfmt_ld24; + struct { /* */ + SI* i_sr; + unsigned char in_sr; + unsigned char out_h_gr_14; + } sfmt_jl; + struct { /* */ + SI* i_dr; + UINT f_uimm5; + unsigned char in_dr; + unsigned char out_dr; + } sfmt_slli; + struct { /* */ + SI* i_dr; + INT f_simm8; + unsigned char in_dr; + unsigned char out_dr; + } sfmt_addi; + struct { /* */ + SI* i_src1; + SI* i_src2; + unsigned char in_src1; + unsigned char in_src2; + unsigned char out_src2; + } sfmt_st_plus; + struct { /* */ + SI* i_src1; + SI* i_src2; + INT f_simm16; + unsigned char in_src1; + unsigned char in_src2; + } sfmt_st_d; + struct { /* */ + SI* i_dr; + SI* i_sr; + unsigned char in_sr; + unsigned char out_dr; + unsigned char out_sr; + } sfmt_ld_plus; + struct { /* */ + IADDR i_disp16; + SI* i_src1; + SI* i_src2; + unsigned char in_src1; + unsigned char in_src2; + } sfmt_beq; + struct { /* */ + SI* i_dr; + SI* i_sr; + UINT f_uimm16; + unsigned char in_sr; + unsigned char out_dr; + } sfmt_and3; + struct { /* */ + SI* i_dr; + SI* i_sr; + INT f_simm16; + unsigned char in_sr; + unsigned char out_dr; + } sfmt_add3; + struct { /* */ + SI* i_dr; + SI* i_sr; + unsigned char in_dr; + unsigned char in_sr; + unsigned char out_dr; + } sfmt_add; #if WITH_SCACHE_PBB /* Writeback handler. */ struct { @@ -449,6 +241,7 @@ union sem_fields { int insn_count; /* Next pbb to execute. */ SCACHE *next; + SCACHE *branch_target; } chain; #endif }; @@ -460,6 +253,9 @@ struct argbuf { const IDESC *idesc; char trace_p; char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; /* cpu specific data follows */ union sem semantic; int written; @@ -480,13 +276,11 @@ struct scache { These define and assign the local vars that contain the insn's fields. */ #define EXTRACT_IFMT_EMPTY_VARS \ - /* Instruction fields. */ \ unsigned int length; #define EXTRACT_IFMT_EMPTY_CODE \ length = 0; \ #define EXTRACT_IFMT_ADD_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -494,13 +288,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADD_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_ADD3_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -509,14 +302,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADD3_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_AND3_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -525,14 +317,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_AND3_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_OR3_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -541,26 +332,24 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_OR3_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_ADDI_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ INT f_simm8; \ unsigned int length; #define EXTRACT_IFMT_ADDI_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_ADDV3_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -569,38 +358,35 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADDV3_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_BC8_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ SI f_disp8; \ unsigned int length; #define EXTRACT_IFMT_BC8_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ #define EXTRACT_IFMT_BC24_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ SI f_disp24; \ unsigned int length; #define EXTRACT_IFMT_BC24_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ #define EXTRACT_IFMT_BEQ_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -609,14 +395,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BEQ_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ #define EXTRACT_IFMT_BEQZ_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -625,14 +410,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BEQZ_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ #define EXTRACT_IFMT_CMP_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -640,13 +424,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_CMP_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_CMPI_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -655,14 +438,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_CMPI_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_DIV_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -671,14 +453,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_DIV_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_JL_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -686,25 +467,23 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_JL_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_LD24_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_uimm24; \ unsigned int length; #define EXTRACT_IFMT_LD24_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \ #define EXTRACT_IFMT_LDI16_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -713,14 +492,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_LDI16_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_MVFACHI_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -728,13 +506,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MVFACHI_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_MVFC_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -742,13 +519,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MVFC_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_MVTACHI_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -756,13 +532,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MVTACHI_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_MVTC_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -770,13 +545,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MVTC_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_NOP_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -784,13 +558,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_NOP_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_SETH_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -799,14 +572,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_SETH_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_SLLI_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_shift_op2; \ @@ -814,13 +586,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_SLLI_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \ - f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \ + f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \ #define EXTRACT_IFMT_ST_D_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -829,14 +600,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ST_D_CODE \ length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \ #define EXTRACT_IFMT_TRAP_VARS \ - /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ @@ -844,10 +614,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_TRAP_CODE \ length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \ + f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ /* Collection of various things for the trace handler to use. */ diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h index 3563f74..3c91931 100644 --- a/sim/m32r/cpuall.h +++ b/sim/m32r/cpuall.h @@ -51,6 +51,9 @@ struct argbuf { const IDESC *idesc; char trace_p; char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; /* cpu specific data follows */ }; #endif diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index 8bac0ef..2b6b774 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -28,29 +28,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-main.h" #include "sim-assert.h" -/* FIXME: Need to review choices for the following. */ - -#if WITH_SEM_SWITCH_FULL -#define FULL(fn) -#else -#define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) , -#endif - -#if WITH_FAST -#if WITH_SEM_SWITCH_FAST -#define FAST(fn) -#else -#define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */ -#endif -#else -#define FAST(fn) -#endif - -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (M32RBF_,insn) -#define TYPE(insn) CONCAT2 (M32R_,insn) - /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -63,124 +40,117 @@ static IDESC m32rbf_insn_data[M32RBF_INSN_MAX]; static const struct insn_sem m32rbf_insn_sem[] = { - { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }, - { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) }, - { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) }, - { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) }, - { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) }, - { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) }, - { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) }, - { TYPE (INSN_ADD3), IDX (INSN_ADD3), FULL (add3) FAST (add3) }, - { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) }, - { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) }, - { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) }, - { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) }, - { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) }, - { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) }, - { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) }, - { TYPE (INSN_ADDV), IDX (INSN_ADDV), FULL (addv) FAST (addv) }, - { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), FULL (addv3) FAST (addv3) }, - { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) }, - { TYPE (INSN_BC8), IDX (INSN_BC8), FULL (bc8) FAST (bc8) }, - { TYPE (INSN_BC24), IDX (INSN_BC24), FULL (bc24) FAST (bc24) }, - { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) }, - { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) }, - { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) }, - { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) }, - { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) }, - { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) }, - { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) }, - { TYPE (INSN_BL8), IDX (INSN_BL8), FULL (bl8) FAST (bl8) }, - { TYPE (INSN_BL24), IDX (INSN_BL24), FULL (bl24) FAST (bl24) }, - { TYPE (INSN_BNC8), IDX (INSN_BNC8), FULL (bnc8) FAST (bnc8) }, - { TYPE (INSN_BNC24), IDX (INSN_BNC24), FULL (bnc24) FAST (bnc24) }, - { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) }, - { TYPE (INSN_BRA8), IDX (INSN_BRA8), FULL (bra8) FAST (bra8) }, - { TYPE (INSN_BRA24), IDX (INSN_BRA24), FULL (bra24) FAST (bra24) }, - { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) }, - { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) }, - { TYPE (INSN_CMPU), IDX (INSN_CMPU), FULL (cmpu) FAST (cmpu) }, - { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), FULL (cmpui) FAST (cmpui) }, - { TYPE (INSN_DIV), IDX (INSN_DIV), FULL (div) FAST (div) }, - { TYPE (INSN_DIVU), IDX (INSN_DIVU), FULL (divu) FAST (divu) }, - { TYPE (INSN_REM), IDX (INSN_REM), FULL (rem) FAST (rem) }, - { TYPE (INSN_REMU), IDX (INSN_REMU), FULL (remu) FAST (remu) }, - { TYPE (INSN_JL), IDX (INSN_JL), FULL (jl) FAST (jl) }, - { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) }, - { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) }, - { TYPE (INSN_LD_D), IDX (INSN_LD_D), FULL (ld_d) FAST (ld_d) }, - { TYPE (INSN_LDB), IDX (INSN_LDB), FULL (ldb) FAST (ldb) }, - { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), FULL (ldb_d) FAST (ldb_d) }, - { TYPE (INSN_LDH), IDX (INSN_LDH), FULL (ldh) FAST (ldh) }, - { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), FULL (ldh_d) FAST (ldh_d) }, - { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) }, - { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), FULL (ldub_d) FAST (ldub_d) }, - { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) }, - { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), FULL (lduh_d) FAST (lduh_d) }, - { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), FULL (ld_plus) FAST (ld_plus) }, - { TYPE (INSN_LD24), IDX (INSN_LD24), FULL (ld24) FAST (ld24) }, - { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) }, - { TYPE (INSN_LDI16), IDX (INSN_LDI16), FULL (ldi16) FAST (ldi16) }, - { TYPE (INSN_LOCK), IDX (INSN_LOCK), FULL (lock) FAST (lock) }, - { TYPE (INSN_MACHI), IDX (INSN_MACHI), FULL (machi) FAST (machi) }, - { TYPE (INSN_MACLO), IDX (INSN_MACLO), FULL (maclo) FAST (maclo) }, - { TYPE (INSN_MACWHI), IDX (INSN_MACWHI), FULL (macwhi) FAST (macwhi) }, - { TYPE (INSN_MACWLO), IDX (INSN_MACWLO), FULL (macwlo) FAST (macwlo) }, - { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) }, - { TYPE (INSN_MULHI), IDX (INSN_MULHI), FULL (mulhi) FAST (mulhi) }, - { TYPE (INSN_MULLO), IDX (INSN_MULLO), FULL (mullo) FAST (mullo) }, - { TYPE (INSN_MULWHI), IDX (INSN_MULWHI), FULL (mulwhi) FAST (mulwhi) }, - { TYPE (INSN_MULWLO), IDX (INSN_MULWLO), FULL (mulwlo) FAST (mulwlo) }, - { TYPE (INSN_MV), IDX (INSN_MV), FULL (mv) FAST (mv) }, - { TYPE (INSN_MVFACHI), IDX (INSN_MVFACHI), FULL (mvfachi) FAST (mvfachi) }, - { TYPE (INSN_MVFACLO), IDX (INSN_MVFACLO), FULL (mvfaclo) FAST (mvfaclo) }, - { TYPE (INSN_MVFACMI), IDX (INSN_MVFACMI), FULL (mvfacmi) FAST (mvfacmi) }, - { TYPE (INSN_MVFC), IDX (INSN_MVFC), FULL (mvfc) FAST (mvfc) }, - { TYPE (INSN_MVTACHI), IDX (INSN_MVTACHI), FULL (mvtachi) FAST (mvtachi) }, - { TYPE (INSN_MVTACLO), IDX (INSN_MVTACLO), FULL (mvtaclo) FAST (mvtaclo) }, - { TYPE (INSN_MVTC), IDX (INSN_MVTC), FULL (mvtc) FAST (mvtc) }, - { TYPE (INSN_NEG), IDX (INSN_NEG), FULL (neg) FAST (neg) }, - { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) }, - { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) }, - { TYPE (INSN_RAC), IDX (INSN_RAC), FULL (rac) FAST (rac) }, - { TYPE (INSN_RACH), IDX (INSN_RACH), FULL (rach) FAST (rach) }, - { TYPE (INSN_RTE), IDX (INSN_RTE), FULL (rte) FAST (rte) }, - { TYPE (INSN_SETH), IDX (INSN_SETH), FULL (seth) FAST (seth) }, - { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) }, - { TYPE (INSN_SLL3), IDX (INSN_SLL3), FULL (sll3) FAST (sll3) }, - { TYPE (INSN_SLLI), IDX (INSN_SLLI), FULL (slli) FAST (slli) }, - { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) }, - { TYPE (INSN_SRA3), IDX (INSN_SRA3), FULL (sra3) FAST (sra3) }, - { TYPE (INSN_SRAI), IDX (INSN_SRAI), FULL (srai) FAST (srai) }, - { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) }, - { TYPE (INSN_SRL3), IDX (INSN_SRL3), FULL (srl3) FAST (srl3) }, - { TYPE (INSN_SRLI), IDX (INSN_SRLI), FULL (srli) FAST (srli) }, - { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) }, - { TYPE (INSN_ST_D), IDX (INSN_ST_D), FULL (st_d) FAST (st_d) }, - { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) }, - { TYPE (INSN_STB_D), IDX (INSN_STB_D), FULL (stb_d) FAST (stb_d) }, - { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) }, - { TYPE (INSN_STH_D), IDX (INSN_STH_D), FULL (sth_d) FAST (sth_d) }, - { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), FULL (st_plus) FAST (st_plus) }, - { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), FULL (st_minus) FAST (st_minus) }, - { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) }, - { TYPE (INSN_SUBV), IDX (INSN_SUBV), FULL (subv) FAST (subv) }, - { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) }, - { TYPE (INSN_TRAP), IDX (INSN_TRAP), FULL (trap) FAST (trap) }, - { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), FULL (unlock) FAST (unlock) }, + { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY }, + { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD }, + { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 }, + { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD }, + { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 }, + { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD }, + { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 }, + { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD }, + { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 }, + { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI }, + { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV }, + { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 }, + { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX }, + { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 }, + { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 }, + { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ }, + { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ }, + { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 }, + { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 }, + { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 }, + { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 }, + { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ }, + { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 }, + { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 }, + { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP }, + { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI }, + { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP }, + { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI }, + { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV }, + { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV }, + { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV }, + { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV }, + { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL }, + { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP }, + { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD }, + { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D }, + { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LD }, + { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LD_D }, + { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LD }, + { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LD_D }, + { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LD }, + { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LD_D }, + { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LD }, + { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LD_D }, + { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS }, + { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 }, + { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 }, + { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 }, + { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK }, + { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI }, + { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI }, + { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI }, + { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI }, + { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD }, + { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI }, + { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI }, + { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI }, + { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI }, + { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV }, + { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI }, + { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI }, + { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI }, + { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC }, + { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI }, + { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI }, + { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC }, + { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV }, + { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP }, + { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV }, + { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC }, + { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC }, + { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE }, + { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH }, + { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD }, + { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 }, + { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI }, + { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD }, + { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 }, + { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI }, + { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD }, + { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 }, + { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI }, + { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST }, + { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D }, + { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB }, + { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D }, + { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH }, + { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D }, + { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS }, + { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS }, + { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD }, + { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV }, + { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX }, + { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP }, + { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK }, }; -static const struct insn_sem m32rbf_insn_sem_invalid = -{ - VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) +static const struct insn_sem m32rbf_insn_sem_invalid = { + VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY }; -#undef FMT -#undef FULL -#undef FAST -#undef IDX -#undef TYPE - /* Initialize an IDESC from the compile-time computable parts. */ static INLINE void @@ -189,6 +159,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; id->num = t->index; + id->sfmt = t->sfmt; if ((int) t->type <= 0) id->idata = & cgen_virtual_insn_table[- (int) t->type]; else @@ -196,12 +167,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) id->attrs = CGEN_INSN_ATTRS (id->idata); /* Oh my god, a magic number. */ id->length = CGEN_INSN_BITSIZE (id->idata) / 8; -#if ! WITH_SEM_SWITCH_FULL - id->sem_full = t->sem_full; -#endif -#if WITH_FAST && ! WITH_SEM_SWITCH_FAST - id->sem_fast = t->sem_fast; -#endif + #if WITH_PROFILE_MODEL_P id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; { @@ -209,6 +175,8 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) SIM_ASSERT (t->index == id->timing->num); } #endif + + /* Semantic pointers are initialized elsewhere. */ } /* Initialize the instruction descriptor table. */ @@ -256,59 +224,59 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); switch (val) { - case 0 : itype = M32RBF_INSN_SUBV; goto extract_fmt_addv; - case 1 : itype = M32RBF_INSN_SUBX; goto extract_fmt_addx; - case 2 : itype = M32RBF_INSN_SUB; goto extract_fmt_add; - case 3 : itype = M32RBF_INSN_NEG; goto extract_fmt_mv; - case 4 : itype = M32RBF_INSN_CMP; goto extract_fmt_cmp; - case 5 : itype = M32RBF_INSN_CMPU; goto extract_fmt_cmp; - case 8 : itype = M32RBF_INSN_ADDV; goto extract_fmt_addv; - case 9 : itype = M32RBF_INSN_ADDX; goto extract_fmt_addx; - case 10 : itype = M32RBF_INSN_ADD; goto extract_fmt_add; - case 11 : itype = M32RBF_INSN_NOT; goto extract_fmt_mv; - case 12 : itype = M32RBF_INSN_AND; goto extract_fmt_add; - case 13 : itype = M32RBF_INSN_XOR; goto extract_fmt_add; - case 14 : itype = M32RBF_INSN_OR; goto extract_fmt_add; - case 16 : itype = M32RBF_INSN_SRL; goto extract_fmt_add; - case 18 : itype = M32RBF_INSN_SRA; goto extract_fmt_add; - case 20 : itype = M32RBF_INSN_SLL; goto extract_fmt_add; - case 22 : itype = M32RBF_INSN_MUL; goto extract_fmt_add; - case 24 : itype = M32RBF_INSN_MV; goto extract_fmt_mv; - case 25 : itype = M32RBF_INSN_MVFC; goto extract_fmt_mvfc; - case 26 : itype = M32RBF_INSN_MVTC; goto extract_fmt_mvtc; + case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv; + case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx; + case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add; + case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv; + case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp; + case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp; + case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv; + case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx; + case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add; + case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv; + case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add; + case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add; + case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add; + case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add; + case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add; + case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add; + case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add; + case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv; + case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc; + case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc; case 28 : { unsigned int val = (((insn >> 8) & (15 << 0))); switch (val) { - case 14 : itype = M32RBF_INSN_JL; goto extract_fmt_jl; - case 15 : itype = M32RBF_INSN_JMP; goto extract_fmt_jmp; - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + case 14 : itype = M32RBF_INSN_JL; goto extract_sfmt_jl; + case 15 : itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 29 : itype = M32RBF_INSN_RTE; goto extract_fmt_rte; - case 31 : itype = M32RBF_INSN_TRAP; goto extract_fmt_trap; - case 32 : itype = M32RBF_INSN_STB; goto extract_fmt_stb; - case 34 : itype = M32RBF_INSN_STH; goto extract_fmt_sth; - case 36 : itype = M32RBF_INSN_ST; goto extract_fmt_st; - case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_fmt_unlock; - case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_fmt_st_plus; - case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_fmt_st_plus; - case 40 : itype = M32RBF_INSN_LDB; goto extract_fmt_ldb; - case 41 : itype = M32RBF_INSN_LDUB; goto extract_fmt_ldb; - case 42 : itype = M32RBF_INSN_LDH; goto extract_fmt_ldh; - case 43 : itype = M32RBF_INSN_LDUH; goto extract_fmt_ldh; - case 44 : itype = M32RBF_INSN_LD; goto extract_fmt_ld; - case 45 : itype = M32RBF_INSN_LOCK; goto extract_fmt_lock; - case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_fmt_ld_plus; - case 48 : itype = M32RBF_INSN_MULHI; goto extract_fmt_mulhi; - case 49 : itype = M32RBF_INSN_MULLO; goto extract_fmt_mulhi; - case 50 : itype = M32RBF_INSN_MULWHI; goto extract_fmt_mulhi; - case 51 : itype = M32RBF_INSN_MULWLO; goto extract_fmt_mulhi; - case 52 : itype = M32RBF_INSN_MACHI; goto extract_fmt_machi; - case 53 : itype = M32RBF_INSN_MACLO; goto extract_fmt_machi; - case 54 : itype = M32RBF_INSN_MACWHI; goto extract_fmt_machi; - case 55 : itype = M32RBF_INSN_MACWLO; goto extract_fmt_machi; + case 29 : itype = M32RBF_INSN_RTE; goto extract_sfmt_rte; + case 31 : itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap; + case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb; + case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth; + case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st; + case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock; + case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus; + case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus; + case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ld; + case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ld; + case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ld; + case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ld; + case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld; + case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock; + case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus; + case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi; + case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi; + case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi; + case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi; + case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi; + case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi; + case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi; + case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi; case 64 : /* fall through */ case 65 : /* fall through */ case 66 : /* fall through */ @@ -324,34 +292,34 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 76 : /* fall through */ case 77 : /* fall through */ case 78 : /* fall through */ - case 79 : itype = M32RBF_INSN_ADDI; goto extract_fmt_addi; + case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi; case 80 : /* fall through */ - case 81 : itype = M32RBF_INSN_SRLI; goto extract_fmt_slli; + case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli; case 82 : /* fall through */ - case 83 : itype = M32RBF_INSN_SRAI; goto extract_fmt_slli; + case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli; case 84 : /* fall through */ - case 85 : itype = M32RBF_INSN_SLLI; goto extract_fmt_slli; + case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli; case 87 : { unsigned int val = (((insn >> 0) & (15 << 0))); switch (val) { - case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_fmt_mvtachi; - case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_fmt_mvtachi; - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi; + case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 88 : itype = M32RBF_INSN_RACH; goto extract_fmt_rac; - case 89 : itype = M32RBF_INSN_RAC; goto extract_fmt_rac; + case 88 : itype = M32RBF_INSN_RACH; goto extract_sfmt_rac; + case 89 : itype = M32RBF_INSN_RAC; goto extract_sfmt_rac; case 95 : { unsigned int val = (((insn >> 0) & (15 << 0))); switch (val) { - case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_fmt_mvfachi; - case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_fmt_mvfachi; - case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_fmt_mvfachi; - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi; + case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi; + case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } case 96 : /* fall through */ @@ -369,18 +337,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 108 : /* fall through */ case 109 : /* fall through */ case 110 : /* fall through */ - case 111 : itype = M32RBF_INSN_LDI8; goto extract_fmt_ldi8; + case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8; case 112 : { unsigned int val = (((insn >> 8) & (15 << 0))); switch (val) { - case 0 : itype = M32RBF_INSN_NOP; goto extract_fmt_nop; - case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8; - case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8; - case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8; - case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8; - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop; + case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8; + case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8; + case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8; + case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } case 113 : /* fall through */ @@ -402,45 +370,45 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 8) & (15 << 0))); switch (val) { - case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8; - case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8; - case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8; - case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8; - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8; + case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8; + case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8; + case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 132 : itype = M32RBF_INSN_CMPI; goto extract_fmt_cmpi; - case 133 : itype = M32RBF_INSN_CMPUI; goto extract_fmt_cmpi; - case 136 : itype = M32RBF_INSN_ADDV3; goto extract_fmt_addv3; - case 138 : itype = M32RBF_INSN_ADD3; goto extract_fmt_add3; - case 140 : itype = M32RBF_INSN_AND3; goto extract_fmt_and3; - case 141 : itype = M32RBF_INSN_XOR3; goto extract_fmt_and3; - case 142 : itype = M32RBF_INSN_OR3; goto extract_fmt_or3; - case 144 : itype = M32RBF_INSN_DIV; goto extract_fmt_div; - case 145 : itype = M32RBF_INSN_DIVU; goto extract_fmt_div; - case 146 : itype = M32RBF_INSN_REM; goto extract_fmt_div; - case 147 : itype = M32RBF_INSN_REMU; goto extract_fmt_div; - case 152 : itype = M32RBF_INSN_SRL3; goto extract_fmt_sll3; - case 154 : itype = M32RBF_INSN_SRA3; goto extract_fmt_sll3; - case 156 : itype = M32RBF_INSN_SLL3; goto extract_fmt_sll3; - case 159 : itype = M32RBF_INSN_LDI16; goto extract_fmt_ldi16; - case 160 : itype = M32RBF_INSN_STB_D; goto extract_fmt_stb_d; - case 162 : itype = M32RBF_INSN_STH_D; goto extract_fmt_sth_d; - case 164 : itype = M32RBF_INSN_ST_D; goto extract_fmt_st_d; - case 168 : itype = M32RBF_INSN_LDB_D; goto extract_fmt_ldb_d; - case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_fmt_ldb_d; - case 170 : itype = M32RBF_INSN_LDH_D; goto extract_fmt_ldh_d; - case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_fmt_ldh_d; - case 172 : itype = M32RBF_INSN_LD_D; goto extract_fmt_ld_d; - case 176 : itype = M32RBF_INSN_BEQ; goto extract_fmt_beq; - case 177 : itype = M32RBF_INSN_BNE; goto extract_fmt_beq; - case 184 : itype = M32RBF_INSN_BEQZ; goto extract_fmt_beqz; - case 185 : itype = M32RBF_INSN_BNEZ; goto extract_fmt_beqz; - case 186 : itype = M32RBF_INSN_BLTZ; goto extract_fmt_beqz; - case 187 : itype = M32RBF_INSN_BGEZ; goto extract_fmt_beqz; - case 188 : itype = M32RBF_INSN_BLEZ; goto extract_fmt_beqz; - case 189 : itype = M32RBF_INSN_BGTZ; goto extract_fmt_beqz; - case 220 : itype = M32RBF_INSN_SETH; goto extract_fmt_seth; + case 132 : itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi; + case 133 : itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi; + case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3; + case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3; + case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3; + case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3; + case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3; + case 144 : itype = M32RBF_INSN_DIV; goto extract_sfmt_div; + case 145 : itype = M32RBF_INSN_DIVU; goto extract_sfmt_div; + case 146 : itype = M32RBF_INSN_REM; goto extract_sfmt_div; + case 147 : itype = M32RBF_INSN_REMU; goto extract_sfmt_div; + case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3; + case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3; + case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3; + case 159 : itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16; + case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d; + case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d; + case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d; + case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ld_d; + case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ld_d; + case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ld_d; + case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ld_d; + case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d; + case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq; + case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq; + case 184 : itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz; + case 185 : itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz; + case 186 : itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz; + case 187 : itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz; + case 188 : itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz; + case 189 : itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz; + case 220 : itype = M32RBF_INSN_SETH; goto extract_sfmt_seth; case 224 : /* fall through */ case 225 : /* fall through */ case 226 : /* fall through */ @@ -456,7 +424,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 236 : /* fall through */ case 237 : /* fall through */ case 238 : /* fall through */ - case 239 : itype = M32RBF_INSN_LD24; goto extract_fmt_ld24; + case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24; case 240 : /* fall through */ case 241 : /* fall through */ case 242 : /* fall through */ @@ -477,49 +445,49 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 8) & (15 << 0))); switch (val) { - case 12 : itype = M32RBF_INSN_BC24; goto extract_fmt_bc24; - case 13 : itype = M32RBF_INSN_BNC24; goto extract_fmt_bc24; - case 14 : itype = M32RBF_INSN_BL24; goto extract_fmt_bl24; - case 15 : itype = M32RBF_INSN_BRA24; goto extract_fmt_bra24; - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + case 12 : itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24; + case 13 : itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24; + case 14 : itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24; + case 15 : itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } - default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty; + default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; } } } /* The instruction has been decoded, now extract the fields. */ - extract_fmt_empty: + extract_sfmt_empty: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_IFMT_EMPTY_CODE /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); #undef FLD return idesc; } - extract_fmt_add: + extract_sfmt_add: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_add.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_sr) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -534,20 +502,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_add3: + extract_sfmt_add3: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_add3.f - EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ADD3_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -561,20 +533,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_and3: + extract_sfmt_and3: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_and3.f - EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ +#define FLD(f) abuf->fields.sfmt_and3.f + UINT f_r1; + UINT f_r2; + UINT f_uimm16; - EXTRACT_IFMT_AND3_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_uimm16) = f_uimm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -588,20 +564,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_or3: + extract_sfmt_or3: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_or3.f - EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ +#define FLD(f) abuf->fields.sfmt_and3.f + UINT f_r1; + UINT f_r2; + UINT f_uimm16; - EXTRACT_IFMT_OR3_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_uimm16) = f_uimm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -615,19 +595,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addi: + extract_sfmt_addi: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_addi.f - EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_r1; + INT f_simm8; - EXTRACT_IFMT_ADDI_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_simm8) = f_simm8; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -641,19 +623,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addv: + extract_sfmt_addv: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_addv.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_sr) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -668,20 +652,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addv3: + extract_sfmt_addv3: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_addv3.f - EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ADDV3_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -695,19 +683,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_addx: + extract_sfmt_addx: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_addx.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_sr) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -722,19 +712,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bc8: + extract_sfmt_bc8: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f - EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; - EXTRACT_IFMT_BC8_CODE + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -746,19 +735,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bc24: + extract_sfmt_bc24: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f - EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; - EXTRACT_IFMT_BC24_CODE + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -770,21 +758,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_beq: + extract_sfmt_beq: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f - EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_r1; + UINT f_r2; + SI f_disp16; - EXTRACT_IFMT_BEQ_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_disp16) = f_disp16; FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -798,20 +789,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_beqz: + extract_sfmt_beqz: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f - EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ +#define FLD(f) abuf->fields.sfmt_beq.f + UINT f_r2; + SI f_disp16; - EXTRACT_IFMT_BEQZ_CODE + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_disp16) = f_disp16; FLD (i_src2) = & CPU (h_gr)[f_r2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -824,19 +816,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bl8: + extract_sfmt_bl8: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f - EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; - EXTRACT_IFMT_BC8_CODE + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -849,19 +840,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bl24: + extract_sfmt_bl24: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f - EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; - EXTRACT_IFMT_BC24_CODE + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -874,19 +864,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bra8: + extract_sfmt_bra8: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f - EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ +#define FLD(f) abuf->fields.sfmt_bl8.f + SI f_disp8; - EXTRACT_IFMT_BC8_CODE + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -898,19 +887,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_bra24: + extract_sfmt_bra24: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f - EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ +#define FLD(f) abuf->fields.sfmt_bl24.f + SI f_disp24; - EXTRACT_IFMT_BC24_CODE + f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -922,19 +910,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmp: + extract_sfmt_cmp: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_cmp.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -948,19 +938,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_cmpi: + extract_sfmt_cmpi: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_cmpi.f - EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_CMPI_CODE + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -973,19 +965,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_div: + extract_sfmt_div: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_div.f - EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_DIV_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_sr) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1000,19 +994,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_jl: + extract_sfmt_jl: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_jl.f - EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_jl.f + UINT f_r2; - EXTRACT_IFMT_JL_CODE + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1026,97 +1019,45 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_jmp: - { - const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f - EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */ - - EXTRACT_IFMT_JL_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_sr) = & CPU (h_gr)[f_r2]; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_sr) = f_r2; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ld: - { - const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ld.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - - EXTRACT_IFMT_ADD_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_sr) = & CPU (h_gr)[f_r2]; - FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_sr) = f_r2; - FLD (out_dr) = f_r1; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ld_d: + extract_sfmt_jmp: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ld_d.f - EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_mvtc.f + UINT f_r2; - EXTRACT_IFMT_ADD3_CODE + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ - FLD (f_simm16) = f_simm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; - FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { FLD (in_sr) = f_r2; - FLD (out_dr) = f_r1; } #endif #undef FLD return idesc; } - extract_fmt_ldb: + extract_sfmt_ld: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ldb.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1130,20 +1071,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldb_d: + extract_sfmt_ld_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ldb_d.f - EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ADD3_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1157,72 +1102,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldh: + extract_sfmt_ld_plus: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ldh.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_sr) = f_r2; - FLD (out_dr) = f_r1; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ldh_d: - { - const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ldh_d.f - EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - - EXTRACT_IFMT_ADD3_CODE - - /* Record the fields for the semantic handler. */ - FLD (f_simm16) = f_simm16; - FLD (i_sr) = & CPU (h_gr)[f_r2]; - FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_sr) = f_r2; - FLD (out_dr) = f_r1; - } -#endif -#undef FLD - return idesc; - } - - extract_fmt_ld_plus: - { - const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ld_plus.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - - EXTRACT_IFMT_ADD_CODE - - /* Record the fields for the semantic handler. */ - FLD (i_sr) = & CPU (h_gr)[f_r2]; - FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1237,19 +1131,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ld24: + extract_sfmt_ld24: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ld24.f - EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */ +#define FLD(f) abuf->fields.sfmt_ld24.f + UINT f_r1; + UINT f_uimm24; - EXTRACT_IFMT_LD24_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); /* Record the fields for the semantic handler. */ FLD (i_uimm24) = f_uimm24; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1262,19 +1158,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldi8: + extract_sfmt_ldi8: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ldi8.f - EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ +#define FLD(f) abuf->fields.sfmt_addi.f + UINT f_r1; + INT f_simm8; - EXTRACT_IFMT_ADDI_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_simm8) = f_simm8; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1287,19 +1185,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_ldi16: + extract_sfmt_ldi16: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_ldi16.f - EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + INT f_simm16; - EXTRACT_IFMT_LDI16_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1312,19 +1212,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_lock: + extract_sfmt_lock: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_lock.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1338,19 +1240,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_machi: + extract_sfmt_machi: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_machi.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1364,19 +1268,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mulhi: + extract_sfmt_mulhi: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_mulhi.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1390,19 +1296,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mv: + extract_sfmt_mv: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_mv.f - EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_ld_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_ADD_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1416,18 +1324,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mvfachi: + extract_sfmt_mvfachi: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_mvfachi.f - EXTRACT_IFMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_seth.f + UINT f_r1; - EXTRACT_IFMT_MVFACHI_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1440,19 +1348,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mvfc: + extract_sfmt_mvfc: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_mvfc.f - EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_mvfc.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_MVFC_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_r2) = f_r2; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1465,18 +1375,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mvtachi: + extract_sfmt_mvtachi: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_mvtachi.f - EXTRACT_IFMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; - EXTRACT_IFMT_MVTACHI_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1489,19 +1399,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_mvtc: + extract_sfmt_mvtc: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_mvtc.f - EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_mvtc.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_MVTC_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_r1) = f_r1; FLD (i_sr) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1514,50 +1426,43 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_nop: + extract_sfmt_nop: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_nop.f - EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); #undef FLD return idesc; } - extract_fmt_rac: + extract_sfmt_rac: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_rac.f - EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0)); #undef FLD return idesc; } - extract_fmt_rte: + extract_sfmt_rte: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_rte.f - EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1569,19 +1474,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_seth: + extract_sfmt_seth: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_seth.f - EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ +#define FLD(f) abuf->fields.sfmt_seth.f + UINT f_r1; + UINT f_hi16; - EXTRACT_IFMT_SETH_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_hi16) = f_hi16; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1594,20 +1501,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_sll3: + extract_sfmt_sll3: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_sll3.f - EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_add3.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ADDV3_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1621,19 +1532,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_slli: + extract_sfmt_slli: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_slli.f - EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ +#define FLD(f) abuf->fields.sfmt_slli.f + UINT f_r1; + UINT f_uimm5; - EXTRACT_IFMT_SLLI_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); /* Record the fields for the semantic handler. */ FLD (f_uimm5) = f_uimm5; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1647,19 +1560,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_st: + extract_sfmt_st: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_st.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1673,20 +1588,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_st_d: + extract_sfmt_st_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_st_d.f - EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ST_D_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1700,19 +1619,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stb: + extract_sfmt_stb: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_stb.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1726,20 +1647,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_stb_d: + extract_sfmt_stb_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_stb_d.f - EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ST_D_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1753,19 +1678,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_sth: + extract_sfmt_sth: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_sth.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1779,20 +1706,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_sth_d: + extract_sfmt_sth_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_sth_d.f - EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ +#define FLD(f) abuf->fields.sfmt_st_d.f + UINT f_r1; + UINT f_r2; + INT f_simm16; - EXTRACT_IFMT_ST_D_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); + f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1806,19 +1737,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_st_plus: + extract_sfmt_st_plus: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_st_plus.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1833,19 +1766,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_trap: + extract_sfmt_trap: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.cti.fields.fmt_trap.f - EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ +#define FLD(f) abuf->fields.sfmt_trap.f + UINT f_uimm4; - EXTRACT_IFMT_TRAP_CODE + f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_uimm4) = f_uimm4; - SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1857,19 +1789,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_fmt_unlock: + extract_sfmt_unlock: { const IDESC *idesc = &m32rbf_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.fmt_unlock.f - EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ +#define FLD(f) abuf->fields.sfmt_st_plus.f + UINT f_r1; + UINT f_r2; - EXTRACT_IFMT_CMP_CODE + f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h index 91471e8..9649acc 100644 --- a/sim/m32r/decode.h +++ b/sim/m32r/decode.h @@ -29,6 +29,8 @@ extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR, CGEN_INSN_INT, CGEN_INSN_INT, ARGBUF *); extern void m32rbf_init_idesc_table (SIM_CPU *); +extern void m32rbf_sem_init_idesc_table (SIM_CPU *); +extern void m32rbf_semf_init_idesc_table (SIM_CPU *); /* Enum declaration for instructions in cpu family m32rbf. */ typedef enum m32rbf_insn_type { @@ -61,134 +63,22 @@ typedef enum m32rbf_insn_type { , M32RBF_INSN_UNLOCK, M32RBF_INSN_MAX } M32RBF_INSN_TYPE; -#if ! WITH_SEM_SWITCH_FULL -#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,fn); -#else -#define SEMFULL(fn) -#endif - -#if ! WITH_SEM_SWITCH_FAST -#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_semf_,fn); -#else -#define SEMFAST(fn) -#endif - -#define SEM(fn) SEMFULL (fn) SEMFAST (fn) - -/* The function version of the before/after handlers is always needed, - so we always want the SEMFULL declaration of them. */ -extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_before); -extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_after); - -SEM (x_invalid) -SEM (x_after) -SEM (x_before) -SEM (x_cti_chain) -SEM (x_chain) -SEM (x_begin) -SEM (add) -SEM (add3) -SEM (and) -SEM (and3) -SEM (or) -SEM (or3) -SEM (xor) -SEM (xor3) -SEM (addi) -SEM (addv) -SEM (addv3) -SEM (addx) -SEM (bc8) -SEM (bc24) -SEM (beq) -SEM (beqz) -SEM (bgez) -SEM (bgtz) -SEM (blez) -SEM (bltz) -SEM (bnez) -SEM (bl8) -SEM (bl24) -SEM (bnc8) -SEM (bnc24) -SEM (bne) -SEM (bra8) -SEM (bra24) -SEM (cmp) -SEM (cmpi) -SEM (cmpu) -SEM (cmpui) -SEM (div) -SEM (divu) -SEM (rem) -SEM (remu) -SEM (jl) -SEM (jmp) -SEM (ld) -SEM (ld_d) -SEM (ldb) -SEM (ldb_d) -SEM (ldh) -SEM (ldh_d) -SEM (ldub) -SEM (ldub_d) -SEM (lduh) -SEM (lduh_d) -SEM (ld_plus) -SEM (ld24) -SEM (ldi8) -SEM (ldi16) -SEM (lock) -SEM (machi) -SEM (maclo) -SEM (macwhi) -SEM (macwlo) -SEM (mul) -SEM (mulhi) -SEM (mullo) -SEM (mulwhi) -SEM (mulwlo) -SEM (mv) -SEM (mvfachi) -SEM (mvfaclo) -SEM (mvfacmi) -SEM (mvfc) -SEM (mvtachi) -SEM (mvtaclo) -SEM (mvtc) -SEM (neg) -SEM (nop) -SEM (not) -SEM (rac) -SEM (rach) -SEM (rte) -SEM (seth) -SEM (sll) -SEM (sll3) -SEM (slli) -SEM (sra) -SEM (sra3) -SEM (srai) -SEM (srl) -SEM (srl3) -SEM (srli) -SEM (st) -SEM (st_d) -SEM (stb) -SEM (stb_d) -SEM (sth) -SEM (sth_d) -SEM (st_plus) -SEM (st_minus) -SEM (sub) -SEM (subv) -SEM (subx) -SEM (trap) -SEM (unlock) - -#undef SEMFULL -#undef SEMFAST -#undef SEM +/* Enum declaration for semantic formats in cpu family m32rbf. */ +typedef enum m32rbf_sfmt_type { + M32RBF_SFMT_EMPTY, M32RBF_SFMT_ADD, M32RBF_SFMT_ADD3, M32RBF_SFMT_AND3 + , M32RBF_SFMT_OR3, M32RBF_SFMT_ADDI, M32RBF_SFMT_ADDV, M32RBF_SFMT_ADDV3 + , M32RBF_SFMT_ADDX, M32RBF_SFMT_BC8, M32RBF_SFMT_BC24, M32RBF_SFMT_BEQ + , M32RBF_SFMT_BEQZ, M32RBF_SFMT_BL8, M32RBF_SFMT_BL24, M32RBF_SFMT_BRA8 + , M32RBF_SFMT_BRA24, M32RBF_SFMT_CMP, M32RBF_SFMT_CMPI, M32RBF_SFMT_DIV + , M32RBF_SFMT_JL, M32RBF_SFMT_JMP, M32RBF_SFMT_LD, M32RBF_SFMT_LD_D + , M32RBF_SFMT_LD_PLUS, M32RBF_SFMT_LD24, M32RBF_SFMT_LDI8, M32RBF_SFMT_LDI16 + , M32RBF_SFMT_LOCK, M32RBF_SFMT_MACHI, M32RBF_SFMT_MULHI, M32RBF_SFMT_MV + , M32RBF_SFMT_MVFACHI, M32RBF_SFMT_MVFC, M32RBF_SFMT_MVTACHI, M32RBF_SFMT_MVTC + , M32RBF_SFMT_NOP, M32RBF_SFMT_RAC, M32RBF_SFMT_RTE, M32RBF_SFMT_SETH + , M32RBF_SFMT_SLL3, M32RBF_SFMT_SLLI, M32RBF_SFMT_ST, M32RBF_SFMT_ST_D + , M32RBF_SFMT_STB, M32RBF_SFMT_STB_D, M32RBF_SFMT_STH, M32RBF_SFMT_STH_D + , M32RBF_SFMT_ST_PLUS, M32RBF_SFMT_TRAP, M32RBF_SFMT_UNLOCK +} M32RBF_SFMT_TYPE; /* Function unit handlers (user written). */ diff --git a/sim/m32r/model.c b/sim/m32r/model.c index e82881e..99ca3cd 100644 --- a/sim/m32r/model.c +++ b/sim/m32r/model.c @@ -37,7 +37,7 @@ with this program; if not, write to the Free Software Foundation, Inc., static int model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -62,7 +62,7 @@ model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -85,7 +85,7 @@ model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -110,7 +110,7 @@ model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -133,7 +133,7 @@ model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -158,7 +158,7 @@ model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_or3.f +#define FLD(f) abuf->fields.sfmt_and3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -181,7 +181,7 @@ model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -206,7 +206,7 @@ model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -229,7 +229,7 @@ model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -252,7 +252,7 @@ model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -277,7 +277,7 @@ model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addv3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -300,7 +300,7 @@ model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -325,7 +325,7 @@ model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -343,7 +343,7 @@ model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -361,7 +361,7 @@ model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -390,7 +390,7 @@ model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -417,7 +417,7 @@ model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -444,7 +444,7 @@ model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -471,7 +471,7 @@ model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -498,7 +498,7 @@ model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -525,7 +525,7 @@ model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -552,7 +552,7 @@ model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -570,7 +570,7 @@ model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -588,7 +588,7 @@ model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -606,7 +606,7 @@ model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -624,7 +624,7 @@ model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -653,7 +653,7 @@ model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -671,7 +671,7 @@ model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -689,7 +689,7 @@ model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -711,7 +711,7 @@ model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -731,7 +731,7 @@ model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -753,7 +753,7 @@ model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -773,7 +773,7 @@ model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -798,7 +798,7 @@ model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -823,7 +823,7 @@ model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -848,7 +848,7 @@ model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -873,7 +873,7 @@ model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jl.f +#define FLD(f) abuf->fields.sfmt_jl.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -893,7 +893,7 @@ model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mvtc.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -913,7 +913,7 @@ model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -935,7 +935,7 @@ model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -957,7 +957,7 @@ model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -979,7 +979,7 @@ model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1001,7 +1001,7 @@ model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1023,7 +1023,7 @@ model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1045,7 +1045,7 @@ model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1067,7 +1067,7 @@ model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1089,7 +1089,7 @@ model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1111,7 +1111,7 @@ model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1133,7 +1133,7 @@ model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_plus.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1167,7 +1167,7 @@ model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld24.f +#define FLD(f) abuf->fields.sfmt_ld24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1188,7 +1188,7 @@ model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1209,7 +1209,7 @@ model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi16.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1230,7 +1230,7 @@ model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lock.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1252,7 +1252,7 @@ model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1274,7 +1274,7 @@ model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1296,7 +1296,7 @@ model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1318,7 +1318,7 @@ model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1340,7 +1340,7 @@ model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1365,7 +1365,7 @@ model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1387,7 +1387,7 @@ model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1409,7 +1409,7 @@ model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1431,7 +1431,7 @@ model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1453,7 +1453,7 @@ model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1476,7 +1476,7 @@ model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1497,7 +1497,7 @@ model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1518,7 +1518,7 @@ model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1539,7 +1539,7 @@ model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfc.f +#define FLD(f) abuf->fields.sfmt_mvfc.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1560,7 +1560,7 @@ model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1580,7 +1580,7 @@ model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1600,7 +1600,7 @@ model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtc.f +#define FLD(f) abuf->fields.sfmt_mvtc.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1621,7 +1621,7 @@ model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1644,7 +1644,7 @@ model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_nop.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1663,7 +1663,7 @@ model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1686,7 +1686,7 @@ model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1704,7 +1704,7 @@ model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1722,7 +1722,7 @@ model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_rte.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1741,7 +1741,7 @@ model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_seth.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1762,7 +1762,7 @@ model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1787,7 +1787,7 @@ model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1810,7 +1810,7 @@ model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1833,7 +1833,7 @@ model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1858,7 +1858,7 @@ model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1881,7 +1881,7 @@ model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1904,7 +1904,7 @@ model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1929,7 +1929,7 @@ model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1952,7 +1952,7 @@ model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1975,7 +1975,7 @@ model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -1997,7 +1997,7 @@ model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2019,7 +2019,7 @@ model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stb.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2041,7 +2041,7 @@ model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stb_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2063,7 +2063,7 @@ model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sth.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2085,7 +2085,7 @@ model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sth_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2107,7 +2107,7 @@ model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2139,7 +2139,7 @@ model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2171,7 +2171,7 @@ model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2196,7 +2196,7 @@ model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2221,7 +2221,7 @@ model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2246,7 +2246,7 @@ model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_trap.f +#define FLD(f) abuf->fields.sfmt_trap.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2265,7 +2265,7 @@ model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg) static int model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_unlock.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2283,7 +2283,7 @@ model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg) static int model_test_add (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2299,7 +2299,7 @@ model_test_add (SIM_CPU *current_cpu, void *sem_arg) static int model_test_add3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2315,7 +2315,7 @@ model_test_add3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_and (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2331,7 +2331,7 @@ model_test_and (SIM_CPU *current_cpu, void *sem_arg) static int model_test_and3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2347,7 +2347,7 @@ model_test_and3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_or (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2363,7 +2363,7 @@ model_test_or (SIM_CPU *current_cpu, void *sem_arg) static int model_test_or3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_or3.f +#define FLD(f) abuf->fields.sfmt_and3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2379,7 +2379,7 @@ model_test_or3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_xor (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2395,7 +2395,7 @@ model_test_xor (SIM_CPU *current_cpu, void *sem_arg) static int model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2411,7 +2411,7 @@ model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_addi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2427,7 +2427,7 @@ model_test_addi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_addv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2443,7 +2443,7 @@ model_test_addv (SIM_CPU *current_cpu, void *sem_arg) static int model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addv3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2459,7 +2459,7 @@ model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_addx (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2475,7 +2475,7 @@ model_test_addx (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2491,7 +2491,7 @@ model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2507,7 +2507,7 @@ model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_beq (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2523,7 +2523,7 @@ model_test_beq (SIM_CPU *current_cpu, void *sem_arg) static int model_test_beqz (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2539,7 +2539,7 @@ model_test_beqz (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bgez (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2555,7 +2555,7 @@ model_test_bgez (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2571,7 +2571,7 @@ model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg) static int model_test_blez (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2587,7 +2587,7 @@ model_test_blez (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bltz (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2603,7 +2603,7 @@ model_test_bltz (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bnez (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2619,7 +2619,7 @@ model_test_bnez (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2635,7 +2635,7 @@ model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2651,7 +2651,7 @@ model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2667,7 +2667,7 @@ model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2683,7 +2683,7 @@ model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bne (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2699,7 +2699,7 @@ model_test_bne (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f +#define FLD(f) abuf->fields.sfmt_bl8.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2715,7 +2715,7 @@ model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f +#define FLD(f) abuf->fields.sfmt_bl24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2731,7 +2731,7 @@ model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_cmp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2747,7 +2747,7 @@ model_test_cmp (SIM_CPU *current_cpu, void *sem_arg) static int model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2763,7 +2763,7 @@ model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2779,7 +2779,7 @@ model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg) static int model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2795,7 +2795,7 @@ model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg) static int model_test_div (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2811,7 +2811,7 @@ model_test_div (SIM_CPU *current_cpu, void *sem_arg) static int model_test_divu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2827,7 +2827,7 @@ model_test_divu (SIM_CPU *current_cpu, void *sem_arg) static int model_test_rem (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2843,7 +2843,7 @@ model_test_rem (SIM_CPU *current_cpu, void *sem_arg) static int model_test_remu (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2859,7 +2859,7 @@ model_test_remu (SIM_CPU *current_cpu, void *sem_arg) static int model_test_jl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jl.f +#define FLD(f) abuf->fields.sfmt_jl.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2875,7 +2875,7 @@ model_test_jl (SIM_CPU *current_cpu, void *sem_arg) static int model_test_jmp (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mvtc.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2891,7 +2891,7 @@ model_test_jmp (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ld (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2907,7 +2907,7 @@ model_test_ld (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2923,7 +2923,7 @@ model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2939,7 +2939,7 @@ model_test_ldb (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2955,7 +2955,7 @@ model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2971,7 +2971,7 @@ model_test_ldh (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -2987,7 +2987,7 @@ model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3003,7 +3003,7 @@ model_test_ldub (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3019,7 +3019,7 @@ model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_lduh (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3035,7 +3035,7 @@ model_test_lduh (SIM_CPU *current_cpu, void *sem_arg) static int model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3051,7 +3051,7 @@ model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_plus.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3067,7 +3067,7 @@ model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ld24.f +#define FLD(f) abuf->fields.sfmt_ld24.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3083,7 +3083,7 @@ model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_addi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3099,7 +3099,7 @@ model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi16.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3115,7 +3115,7 @@ model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_lock (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_lock.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3131,7 +3131,7 @@ model_test_lock (SIM_CPU *current_cpu, void *sem_arg) static int model_test_machi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3147,7 +3147,7 @@ model_test_machi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_maclo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3163,7 +3163,7 @@ model_test_maclo (SIM_CPU *current_cpu, void *sem_arg) static int model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3179,7 +3179,7 @@ model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3195,7 +3195,7 @@ model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mul (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3211,7 +3211,7 @@ model_test_mul (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3227,7 +3227,7 @@ model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mullo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3243,7 +3243,7 @@ model_test_mullo (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3259,7 +3259,7 @@ model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3275,7 +3275,7 @@ model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3291,7 +3291,7 @@ model_test_mv (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3307,7 +3307,7 @@ model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3323,7 +3323,7 @@ model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3339,7 +3339,7 @@ model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfc.f +#define FLD(f) abuf->fields.sfmt_mvfc.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3355,7 +3355,7 @@ model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3371,7 +3371,7 @@ model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3387,7 +3387,7 @@ model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg) static int model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtc.f +#define FLD(f) abuf->fields.sfmt_mvtc.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3403,7 +3403,7 @@ model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg) static int model_test_neg (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3419,7 +3419,7 @@ model_test_neg (SIM_CPU *current_cpu, void *sem_arg) static int model_test_nop (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_nop.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3435,7 +3435,7 @@ model_test_nop (SIM_CPU *current_cpu, void *sem_arg) static int model_test_not (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3451,7 +3451,7 @@ model_test_not (SIM_CPU *current_cpu, void *sem_arg) static int model_test_rac (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3467,7 +3467,7 @@ model_test_rac (SIM_CPU *current_cpu, void *sem_arg) static int model_test_rach (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3483,7 +3483,7 @@ model_test_rach (SIM_CPU *current_cpu, void *sem_arg) static int model_test_rte (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_rte.f +#define FLD(f) abuf->fields.fmt_empty.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3499,7 +3499,7 @@ model_test_rte (SIM_CPU *current_cpu, void *sem_arg) static int model_test_seth (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_seth.f +#define FLD(f) abuf->fields.sfmt_seth.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3515,7 +3515,7 @@ model_test_seth (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sll (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3531,7 +3531,7 @@ model_test_sll (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3547,7 +3547,7 @@ model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_slli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3563,7 +3563,7 @@ model_test_slli (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sra (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3579,7 +3579,7 @@ model_test_sra (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3595,7 +3595,7 @@ model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_srai (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3611,7 +3611,7 @@ model_test_srai (SIM_CPU *current_cpu, void *sem_arg) static int model_test_srl (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3627,7 +3627,7 @@ model_test_srl (SIM_CPU *current_cpu, void *sem_arg) static int model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3643,7 +3643,7 @@ model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg) static int model_test_srli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3659,7 +3659,7 @@ model_test_srli (SIM_CPU *current_cpu, void *sem_arg) static int model_test_st (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3675,7 +3675,7 @@ model_test_st (SIM_CPU *current_cpu, void *sem_arg) static int model_test_st_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3691,7 +3691,7 @@ model_test_st_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_stb (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stb.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3707,7 +3707,7 @@ model_test_stb (SIM_CPU *current_cpu, void *sem_arg) static int model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_stb_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3723,7 +3723,7 @@ model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sth (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sth.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3739,7 +3739,7 @@ model_test_sth (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_sth_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3755,7 +3755,7 @@ model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg) static int model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3771,7 +3771,7 @@ model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg) static int model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3787,7 +3787,7 @@ model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg) static int model_test_sub (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3803,7 +3803,7 @@ model_test_sub (SIM_CPU *current_cpu, void *sem_arg) static int model_test_subv (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3819,7 +3819,7 @@ model_test_subv (SIM_CPU *current_cpu, void *sem_arg) static int model_test_subx (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3835,7 +3835,7 @@ model_test_subx (SIM_CPU *current_cpu, void *sem_arg) static int model_test_trap (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_trap.f +#define FLD(f) abuf->fields.sfmt_trap.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -3851,7 +3851,7 @@ model_test_trap (SIM_CPU *current_cpu, void *sem_arg) static int model_test_unlock (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.fmt_unlock.f +#define FLD(f) abuf->fields.sfmt_st_plus.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c index 673b836..cd7e8da 100644 --- a/sim/m32r/sem-switch.c +++ b/sim/m32r/sem-switch.c @@ -142,11 +142,13 @@ with this program; if not, write to the Free Software Foundation, Inc., int i; for (i = 0; labels[i].label != 0; ++i) + { #if FAST_P - CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; + CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; #else - CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; + CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; #endif + } #undef DEFINE_LABELS #endif /* DEFINE_LABELS */ @@ -266,12 +268,12 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) #if WITH_SCACHE_PBB_M32RBF #ifdef DEFINE_SWITCH vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); + pbb_br_type, pbb_br_npc); BREAK (sem); #else /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_TYPE (current_cpu), CPU_PBB_BR_NPC (current_cpu)); #endif #endif @@ -332,7 +334,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -351,7 +353,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add3.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -370,7 +372,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -389,7 +391,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -408,7 +410,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -427,7 +429,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_or3.f +#define FLD(f) abuf->fields.sfmt_and3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -446,7 +448,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -465,7 +467,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -484,7 +486,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -503,7 +505,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -532,7 +534,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addv3.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -561,7 +563,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -590,7 +592,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -599,7 +601,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) if (CPU (h_cond)) { { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -615,7 +617,7 @@ if (CPU (h_cond)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -624,7 +626,7 @@ if (CPU (h_cond)) { if (CPU (h_cond)) { { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -640,7 +642,7 @@ if (CPU (h_cond)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -649,7 +651,7 @@ if (CPU (h_cond)) { if (EQSI (* FLD (i_src1), * FLD (i_src2))) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -665,7 +667,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -674,7 +676,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) { if (EQSI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -690,7 +692,7 @@ if (EQSI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -699,7 +701,7 @@ if (EQSI (* FLD (i_src2), 0)) { if (GESI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -715,7 +717,7 @@ if (GESI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -724,7 +726,7 @@ if (GESI (* FLD (i_src2), 0)) { if (GTSI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -740,7 +742,7 @@ if (GTSI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -749,7 +751,7 @@ if (GTSI (* FLD (i_src2), 0)) { if (LESI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -765,7 +767,7 @@ if (LESI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -774,7 +776,7 @@ if (LESI (* FLD (i_src2), 0)) { if (LTSI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -790,7 +792,7 @@ if (LTSI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -799,7 +801,7 @@ if (LTSI (* FLD (i_src2), 0)) { if (NESI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -815,7 +817,7 @@ if (NESI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f +#define FLD(f) abuf->fields.sfmt_bl8.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -829,7 +831,7 @@ if (NESI (* FLD (i_src2), 0)) { } { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -843,7 +845,7 @@ if (NESI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f +#define FLD(f) abuf->fields.sfmt_bl24.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -857,7 +859,7 @@ if (NESI (* FLD (i_src2), 0)) { } { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -871,7 +873,7 @@ if (NESI (* FLD (i_src2), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -880,7 +882,7 @@ if (NESI (* FLD (i_src2), 0)) { if (NOTBI (CPU (h_cond))) { { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -896,7 +898,7 @@ if (NOTBI (CPU (h_cond))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -905,7 +907,7 @@ if (NOTBI (CPU (h_cond))) { if (NOTBI (CPU (h_cond))) { { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -921,7 +923,7 @@ if (NOTBI (CPU (h_cond))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -930,7 +932,7 @@ if (NOTBI (CPU (h_cond))) { if (NESI (* FLD (i_src1), * FLD (i_src2))) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -946,7 +948,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f +#define FLD(f) abuf->fields.sfmt_bl8.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -954,7 +956,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -967,7 +969,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f +#define FLD(f) abuf->fields.sfmt_bl24.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -975,7 +977,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -988,7 +990,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1007,7 +1009,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1026,7 +1028,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1045,7 +1047,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1064,7 +1066,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1087,7 +1089,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1110,7 +1112,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1133,7 +1135,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1156,7 +1158,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_jl.f +#define FLD(f) abuf->fields.sfmt_jl.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -1187,7 +1189,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mvtc.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -1208,7 +1210,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1227,7 +1229,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_d.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1246,7 +1248,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1265,7 +1267,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1284,7 +1286,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1303,7 +1305,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1322,7 +1324,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1341,7 +1343,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1360,7 +1362,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1379,7 +1381,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1398,7 +1400,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld_plus.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1427,7 +1429,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ld24.f +#define FLD(f) abuf->fields.sfmt_ld24.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1446,7 +1448,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_addi.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1465,7 +1467,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_ldi16.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1484,7 +1486,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_lock.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1510,7 +1512,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1529,7 +1531,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1548,7 +1550,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1567,7 +1569,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1586,7 +1588,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1605,7 +1607,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1624,7 +1626,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1643,7 +1645,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1662,7 +1664,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1681,7 +1683,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1700,7 +1702,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1719,7 +1721,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1738,7 +1740,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1757,7 +1759,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvfc.f +#define FLD(f) abuf->fields.sfmt_mvfc.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1776,7 +1778,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1795,7 +1797,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1814,7 +1816,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mvtc.f +#define FLD(f) abuf->fields.sfmt_mvtc.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1833,7 +1835,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1852,7 +1854,7 @@ if (NESI (* FLD (i_sr), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_nop.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1867,7 +1869,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1886,7 +1888,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1910,7 +1912,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1943,7 +1945,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_rte.f +#define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -1981,7 +1983,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_seth.f +#define FLD(f) abuf->fields.sfmt_seth.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2000,7 +2002,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2019,7 +2021,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2038,7 +2040,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2057,7 +2059,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2076,7 +2078,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2095,7 +2097,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2114,7 +2116,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2133,7 +2135,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2152,7 +2154,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2171,7 +2173,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2190,7 +2192,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2209,7 +2211,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stb.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2228,7 +2230,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_stb_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2247,7 +2249,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_sth.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2266,7 +2268,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_sth_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2285,7 +2287,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2313,7 +2315,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2341,7 +2343,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2360,7 +2362,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2389,7 +2391,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2418,7 +2420,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.cti.fields.fmt_trap.f +#define FLD(f) abuf->fields.sfmt_trap.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -2466,7 +2468,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_unlock.f +#define FLD(f) abuf->fields.sfmt_st_plus.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c index 03b0a6f..b337bb8 100644 --- a/sim/m32r/sem.c +++ b/sim/m32r/sem.c @@ -32,9 +32,20 @@ with this program; if not, write to the Free Software Foundation, Inc., #undef GET_ATTR #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef TRACE_RESULT +#define TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + /* x-invalid: --invalid-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -59,7 +70,7 @@ SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-after: --after-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -80,7 +91,7 @@ SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-before: --before-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -101,7 +112,7 @@ SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-cti-chain: --cti-chain-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -114,12 +125,12 @@ SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #if WITH_SCACHE_PBB_M32RBF #ifdef DEFINE_SWITCH vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, - pbb_br_npc_ptr, pbb_br_npc); + pbb_br_type, pbb_br_npc); BREAK (sem); #else /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, - CPU_PBB_BR_NPC_PTR (current_cpu), + CPU_PBB_BR_TYPE (current_cpu), CPU_PBB_BR_NPC (current_cpu)); #endif #endif @@ -131,7 +142,7 @@ SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-chain: --chain-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -155,7 +166,7 @@ SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* x-begin: --begin-- */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.fmt_empty.f @@ -182,10 +193,10 @@ SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* add: add $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -203,10 +214,10 @@ SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* add3: add3 $dr,$sr,$hash$slo16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add3.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -224,10 +235,10 @@ SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and: and $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -245,10 +256,10 @@ SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* and3: and3 $dr,$sr,$uimm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -266,10 +277,10 @@ SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or: or $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -287,10 +298,10 @@ SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* or3: or3 $dr,$sr,$hash$ulo16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_or3.f +#define FLD(f) abuf->fields.sfmt_and3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -308,10 +319,10 @@ SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xor: xor $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -329,10 +340,10 @@ SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* xor3: xor3 $dr,$sr,$uimm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_and3.f +#define FLD(f) abuf->fields.sfmt_and3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -350,10 +361,10 @@ SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addi: addi $dr,$simm8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addi.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -371,10 +382,10 @@ SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addv: addv $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -402,10 +413,10 @@ SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addv3: addv3 $dr,$sr,$simm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addv3.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -433,10 +444,10 @@ SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* addx: addx $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -464,10 +475,10 @@ SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bc8: bc.s $disp8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -477,7 +488,7 @@ SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_cond)) { { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -491,10 +502,10 @@ if (CPU (h_cond)) { /* bc24: bc.l $disp24 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -504,7 +515,7 @@ SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (CPU (h_cond)) { { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -518,10 +529,10 @@ if (CPU (h_cond)) { /* beq: beq $src1,$src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -531,7 +542,7 @@ SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (* FLD (i_src1), * FLD (i_src2))) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -545,10 +556,10 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) { /* beqz: beqz $src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -558,7 +569,7 @@ SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQSI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -572,10 +583,10 @@ if (EQSI (* FLD (i_src2), 0)) { /* bgez: bgez $src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -585,7 +596,7 @@ SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GESI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -599,10 +610,10 @@ if (GESI (* FLD (i_src2), 0)) { /* bgtz: bgtz $src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -612,7 +623,7 @@ SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GTSI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -626,10 +637,10 @@ if (GTSI (* FLD (i_src2), 0)) { /* blez: blez $src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -639,7 +650,7 @@ SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LESI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -653,10 +664,10 @@ if (LESI (* FLD (i_src2), 0)) { /* bltz: bltz $src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -666,7 +677,7 @@ SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (LTSI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -680,10 +691,10 @@ if (LTSI (* FLD (i_src2), 0)) { /* bnez: bnez $src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -693,7 +704,7 @@ SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (* FLD (i_src2), 0)) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -707,10 +718,10 @@ if (NESI (* FLD (i_src2), 0)) { /* bl8: bl.s $disp8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f +#define FLD(f) abuf->fields.sfmt_bl8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -725,7 +736,7 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) } { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -737,10 +748,10 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bl24: bl.l $disp24 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f +#define FLD(f) abuf->fields.sfmt_bl24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -755,7 +766,7 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) } { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } @@ -767,10 +778,10 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bnc8: bnc.s $disp8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f +#define FLD(f) abuf->fields.sfmt_bl8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -780,7 +791,7 @@ SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_cond))) { { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -794,10 +805,10 @@ if (NOTBI (CPU (h_cond))) { /* bnc24: bnc.l $disp24 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f +#define FLD(f) abuf->fields.sfmt_bl24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -807,7 +818,7 @@ SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (CPU (h_cond))) { { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -821,10 +832,10 @@ if (NOTBI (CPU (h_cond))) { /* bne: bne $src1,$src2,$disp16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_beq.f +#define FLD(f) abuf->fields.sfmt_beq.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -834,7 +845,7 @@ SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NESI (* FLD (i_src1), * FLD (i_src2))) { { USI opval = FLD (i_disp16); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -848,10 +859,10 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { /* bra8: bra.s $disp8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f +#define FLD(f) abuf->fields.sfmt_bl8.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -860,7 +871,7 @@ SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { USI opval = FLD (i_disp8); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -871,10 +882,10 @@ SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* bra24: bra.l $disp24 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f +#define FLD(f) abuf->fields.sfmt_bl24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -883,7 +894,7 @@ SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { USI opval = FLD (i_disp24); - SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); + SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } @@ -894,10 +905,10 @@ SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmp: cmp $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -915,10 +926,10 @@ SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpi: cmpi $src2,$simm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -936,10 +947,10 @@ SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpu: cmpu $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmp.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -957,10 +968,10 @@ SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* cmpui: cmpui $src2,$simm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_cmpi.f +#define FLD(f) abuf->fields.sfmt_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -978,10 +989,10 @@ SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* div: div $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1003,10 +1014,10 @@ if (NESI (* FLD (i_sr), 0)) { /* divu: divu $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1028,10 +1039,10 @@ if (NESI (* FLD (i_sr), 0)) { /* rem: rem $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1053,10 +1064,10 @@ if (NESI (* FLD (i_sr), 0)) { /* remu: remu $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_div.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1078,10 +1089,10 @@ if (NESI (* FLD (i_sr), 0)) { /* jl: jl $sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jl.f +#define FLD(f) abuf->fields.sfmt_jl.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1111,10 +1122,10 @@ SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* jmp: jmp $sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f +#define FLD(f) abuf->fields.sfmt_mvtc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1134,10 +1145,10 @@ SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld: ld $dr,@$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1155,10 +1166,10 @@ SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-d: ld $dr,@($slo16,$sr) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_d.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1176,10 +1187,10 @@ SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldb: ldb $dr,@$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1197,10 +1208,10 @@ SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldb-d: ldb $dr,@($slo16,$sr) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1218,10 +1229,10 @@ SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldh: ldh $dr,@$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1239,10 +1250,10 @@ SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldh-d: ldh $dr,@($slo16,$sr) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1260,10 +1271,10 @@ SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldub: ldub $dr,@$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1281,10 +1292,10 @@ SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldub-d: ldub $dr,@($slo16,$sr) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldb_d.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1302,10 +1313,10 @@ SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lduh: lduh $dr,@$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1323,10 +1334,10 @@ SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lduh-d: lduh $dr,@($slo16,$sr) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldh_d.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1344,10 +1355,10 @@ SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld-plus: ld $dr,@$sr+ */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld_plus.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1375,10 +1386,10 @@ SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ld24: ld24 $dr,$uimm24 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ld24.f +#define FLD(f) abuf->fields.sfmt_ld24.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1396,10 +1407,10 @@ SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldi8: ldi8 $dr,$simm8 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi8.f +#define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1417,10 +1428,10 @@ SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* ldi16: ldi16 $dr,$hash$slo16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_ldi16.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1438,10 +1449,10 @@ SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* lock: lock $dr,@$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_lock.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1466,10 +1477,10 @@ SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* machi: machi $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1487,10 +1498,10 @@ SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* maclo: maclo $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1508,10 +1519,10 @@ SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* macwhi: macwhi $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1529,10 +1540,10 @@ SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* macwlo: macwlo $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_machi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1550,10 +1561,10 @@ SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mul: mul $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1571,10 +1582,10 @@ SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulhi: mulhi $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1592,10 +1603,10 @@ SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mullo: mullo $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1613,10 +1624,10 @@ SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulwhi: mulwhi $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1634,10 +1645,10 @@ SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mulwlo: mulwlo $src1,$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mulhi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1655,10 +1666,10 @@ SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mv: mv $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1676,10 +1687,10 @@ SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvfachi: mvfachi $dr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1697,10 +1708,10 @@ SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvfaclo: mvfaclo $dr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1718,10 +1729,10 @@ SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvfacmi: mvfacmi $dr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfachi.f +#define FLD(f) abuf->fields.sfmt_seth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1739,10 +1750,10 @@ SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvfc: mvfc $dr,$scr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvfc.f +#define FLD(f) abuf->fields.sfmt_mvfc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1760,10 +1771,10 @@ SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvtachi: mvtachi $src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1781,10 +1792,10 @@ SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvtaclo: mvtaclo $src1 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtachi.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1802,10 +1813,10 @@ SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* mvtc: mvtc $sr,$dcr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mvtc.f +#define FLD(f) abuf->fields.sfmt_mvtc.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1823,10 +1834,10 @@ SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* neg: neg $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1844,10 +1855,10 @@ SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* nop: nop */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_nop.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1861,10 +1872,10 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); /* not: not $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_mv.f +#define FLD(f) abuf->fields.sfmt_ld_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1882,10 +1893,10 @@ SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* rac: rac */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1908,10 +1919,10 @@ SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* rach: rach */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_rac.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1943,10 +1954,10 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083 /* rte: rte */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_rte.f +#define FLD(f) abuf->fields.fmt_empty.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1983,10 +1994,10 @@ SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* seth: seth $dr,$hash$hi16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_seth.f +#define FLD(f) abuf->fields.sfmt_seth.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2004,10 +2015,10 @@ SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sll: sll $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2025,10 +2036,10 @@ SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sll3: sll3 $dr,$sr,$simm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2046,10 +2057,10 @@ SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* slli: slli $dr,$uimm5 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2067,10 +2078,10 @@ SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sra: sra $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2088,10 +2099,10 @@ SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sra3: sra3 $dr,$sr,$simm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2109,10 +2120,10 @@ SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* srai: srai $dr,$uimm5 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2130,10 +2141,10 @@ SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* srl: srl $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2151,10 +2162,10 @@ SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* srl3: srl3 $dr,$sr,$simm16 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_sll3.f +#define FLD(f) abuf->fields.sfmt_add3.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2172,10 +2183,10 @@ SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* srli: srli $dr,$uimm5 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_slli.f +#define FLD(f) abuf->fields.sfmt_slli.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2193,10 +2204,10 @@ SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st: st $src1,@$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2214,10 +2225,10 @@ SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-d: st $src1,@($slo16,$src2) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2235,10 +2246,10 @@ SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stb: stb $src1,@$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stb.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2256,10 +2267,10 @@ SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* stb-d: stb $src1,@($slo16,$src2) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_stb_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2277,10 +2288,10 @@ SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sth: sth $src1,@$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_sth.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2298,10 +2309,10 @@ SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sth-d: sth $src1,@($slo16,$src2) */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_sth_d.f +#define FLD(f) abuf->fields.sfmt_st_d.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2319,10 +2330,10 @@ SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-plus: st $src1,@+$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2349,10 +2360,10 @@ SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* st-minus: st $src1,@-$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_st_plus.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2379,10 +2390,10 @@ SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* sub: sub $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_add.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2400,10 +2411,10 @@ SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subv: subv $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addv.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2431,10 +2442,10 @@ SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* subx: subx $dr,$sr */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_addx.f +#define FLD(f) abuf->fields.sfmt_add.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2462,10 +2473,10 @@ SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* trap: trap $uimm4 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.cti.fields.fmt_trap.f +#define FLD(f) abuf->fields.sfmt_trap.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2512,10 +2523,10 @@ SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg) /* unlock: unlock $src1,@$src2 */ -SEM_PC +static SEM_PC SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_unlock.f +#define FLD(f) abuf->fields.sfmt_st_plus.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2542,3 +2553,132 @@ if (CPU (h_lock)) { #undef FLD } +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { M32RBF_INSN_X_INVALID, SEM_FN_NAME (m32rbf,x_invalid) }, + { M32RBF_INSN_X_AFTER, SEM_FN_NAME (m32rbf,x_after) }, + { M32RBF_INSN_X_BEFORE, SEM_FN_NAME (m32rbf,x_before) }, + { M32RBF_INSN_X_CTI_CHAIN, SEM_FN_NAME (m32rbf,x_cti_chain) }, + { M32RBF_INSN_X_CHAIN, SEM_FN_NAME (m32rbf,x_chain) }, + { M32RBF_INSN_X_BEGIN, SEM_FN_NAME (m32rbf,x_begin) }, + { M32RBF_INSN_ADD, SEM_FN_NAME (m32rbf,add) }, + { M32RBF_INSN_ADD3, SEM_FN_NAME (m32rbf,add3) }, + { M32RBF_INSN_AND, SEM_FN_NAME (m32rbf,and) }, + { M32RBF_INSN_AND3, SEM_FN_NAME (m32rbf,and3) }, + { M32RBF_INSN_OR, SEM_FN_NAME (m32rbf,or) }, + { M32RBF_INSN_OR3, SEM_FN_NAME (m32rbf,or3) }, + { M32RBF_INSN_XOR, SEM_FN_NAME (m32rbf,xor) }, + { M32RBF_INSN_XOR3, SEM_FN_NAME (m32rbf,xor3) }, + { M32RBF_INSN_ADDI, SEM_FN_NAME (m32rbf,addi) }, + { M32RBF_INSN_ADDV, SEM_FN_NAME (m32rbf,addv) }, + { M32RBF_INSN_ADDV3, SEM_FN_NAME (m32rbf,addv3) }, + { M32RBF_INSN_ADDX, SEM_FN_NAME (m32rbf,addx) }, + { M32RBF_INSN_BC8, SEM_FN_NAME (m32rbf,bc8) }, + { M32RBF_INSN_BC24, SEM_FN_NAME (m32rbf,bc24) }, + { M32RBF_INSN_BEQ, SEM_FN_NAME (m32rbf,beq) }, + { M32RBF_INSN_BEQZ, SEM_FN_NAME (m32rbf,beqz) }, + { M32RBF_INSN_BGEZ, SEM_FN_NAME (m32rbf,bgez) }, + { M32RBF_INSN_BGTZ, SEM_FN_NAME (m32rbf,bgtz) }, + { M32RBF_INSN_BLEZ, SEM_FN_NAME (m32rbf,blez) }, + { M32RBF_INSN_BLTZ, SEM_FN_NAME (m32rbf,bltz) }, + { M32RBF_INSN_BNEZ, SEM_FN_NAME (m32rbf,bnez) }, + { M32RBF_INSN_BL8, SEM_FN_NAME (m32rbf,bl8) }, + { M32RBF_INSN_BL24, SEM_FN_NAME (m32rbf,bl24) }, + { M32RBF_INSN_BNC8, SEM_FN_NAME (m32rbf,bnc8) }, + { M32RBF_INSN_BNC24, SEM_FN_NAME (m32rbf,bnc24) }, + { M32RBF_INSN_BNE, SEM_FN_NAME (m32rbf,bne) }, + { M32RBF_INSN_BRA8, SEM_FN_NAME (m32rbf,bra8) }, + { M32RBF_INSN_BRA24, SEM_FN_NAME (m32rbf,bra24) }, + { M32RBF_INSN_CMP, SEM_FN_NAME (m32rbf,cmp) }, + { M32RBF_INSN_CMPI, SEM_FN_NAME (m32rbf,cmpi) }, + { M32RBF_INSN_CMPU, SEM_FN_NAME (m32rbf,cmpu) }, + { M32RBF_INSN_CMPUI, SEM_FN_NAME (m32rbf,cmpui) }, + { M32RBF_INSN_DIV, SEM_FN_NAME (m32rbf,div) }, + { M32RBF_INSN_DIVU, SEM_FN_NAME (m32rbf,divu) }, + { M32RBF_INSN_REM, SEM_FN_NAME (m32rbf,rem) }, + { M32RBF_INSN_REMU, SEM_FN_NAME (m32rbf,remu) }, + { M32RBF_INSN_JL, SEM_FN_NAME (m32rbf,jl) }, + { M32RBF_INSN_JMP, SEM_FN_NAME (m32rbf,jmp) }, + { M32RBF_INSN_LD, SEM_FN_NAME (m32rbf,ld) }, + { M32RBF_INSN_LD_D, SEM_FN_NAME (m32rbf,ld_d) }, + { M32RBF_INSN_LDB, SEM_FN_NAME (m32rbf,ldb) }, + { M32RBF_INSN_LDB_D, SEM_FN_NAME (m32rbf,ldb_d) }, + { M32RBF_INSN_LDH, SEM_FN_NAME (m32rbf,ldh) }, + { M32RBF_INSN_LDH_D, SEM_FN_NAME (m32rbf,ldh_d) }, + { M32RBF_INSN_LDUB, SEM_FN_NAME (m32rbf,ldub) }, + { M32RBF_INSN_LDUB_D, SEM_FN_NAME (m32rbf,ldub_d) }, + { M32RBF_INSN_LDUH, SEM_FN_NAME (m32rbf,lduh) }, + { M32RBF_INSN_LDUH_D, SEM_FN_NAME (m32rbf,lduh_d) }, + { M32RBF_INSN_LD_PLUS, SEM_FN_NAME (m32rbf,ld_plus) }, + { M32RBF_INSN_LD24, SEM_FN_NAME (m32rbf,ld24) }, + { M32RBF_INSN_LDI8, SEM_FN_NAME (m32rbf,ldi8) }, + { M32RBF_INSN_LDI16, SEM_FN_NAME (m32rbf,ldi16) }, + { M32RBF_INSN_LOCK, SEM_FN_NAME (m32rbf,lock) }, + { M32RBF_INSN_MACHI, SEM_FN_NAME (m32rbf,machi) }, + { M32RBF_INSN_MACLO, SEM_FN_NAME (m32rbf,maclo) }, + { M32RBF_INSN_MACWHI, SEM_FN_NAME (m32rbf,macwhi) }, + { M32RBF_INSN_MACWLO, SEM_FN_NAME (m32rbf,macwlo) }, + { M32RBF_INSN_MUL, SEM_FN_NAME (m32rbf,mul) }, + { M32RBF_INSN_MULHI, SEM_FN_NAME (m32rbf,mulhi) }, + { M32RBF_INSN_MULLO, SEM_FN_NAME (m32rbf,mullo) }, + { M32RBF_INSN_MULWHI, SEM_FN_NAME (m32rbf,mulwhi) }, + { M32RBF_INSN_MULWLO, SEM_FN_NAME (m32rbf,mulwlo) }, + { M32RBF_INSN_MV, SEM_FN_NAME (m32rbf,mv) }, + { M32RBF_INSN_MVFACHI, SEM_FN_NAME (m32rbf,mvfachi) }, + { M32RBF_INSN_MVFACLO, SEM_FN_NAME (m32rbf,mvfaclo) }, + { M32RBF_INSN_MVFACMI, SEM_FN_NAME (m32rbf,mvfacmi) }, + { M32RBF_INSN_MVFC, SEM_FN_NAME (m32rbf,mvfc) }, + { M32RBF_INSN_MVTACHI, SEM_FN_NAME (m32rbf,mvtachi) }, + { M32RBF_INSN_MVTACLO, SEM_FN_NAME (m32rbf,mvtaclo) }, + { M32RBF_INSN_MVTC, SEM_FN_NAME (m32rbf,mvtc) }, + { M32RBF_INSN_NEG, SEM_FN_NAME (m32rbf,neg) }, + { M32RBF_INSN_NOP, SEM_FN_NAME (m32rbf,nop) }, + { M32RBF_INSN_NOT, SEM_FN_NAME (m32rbf,not) }, + { M32RBF_INSN_RAC, SEM_FN_NAME (m32rbf,rac) }, + { M32RBF_INSN_RACH, SEM_FN_NAME (m32rbf,rach) }, + { M32RBF_INSN_RTE, SEM_FN_NAME (m32rbf,rte) }, + { M32RBF_INSN_SETH, SEM_FN_NAME (m32rbf,seth) }, + { M32RBF_INSN_SLL, SEM_FN_NAME (m32rbf,sll) }, + { M32RBF_INSN_SLL3, SEM_FN_NAME (m32rbf,sll3) }, + { M32RBF_INSN_SLLI, SEM_FN_NAME (m32rbf,slli) }, + { M32RBF_INSN_SRA, SEM_FN_NAME (m32rbf,sra) }, + { M32RBF_INSN_SRA3, SEM_FN_NAME (m32rbf,sra3) }, + { M32RBF_INSN_SRAI, SEM_FN_NAME (m32rbf,srai) }, + { M32RBF_INSN_SRL, SEM_FN_NAME (m32rbf,srl) }, + { M32RBF_INSN_SRL3, SEM_FN_NAME (m32rbf,srl3) }, + { M32RBF_INSN_SRLI, SEM_FN_NAME (m32rbf,srli) }, + { M32RBF_INSN_ST, SEM_FN_NAME (m32rbf,st) }, + { M32RBF_INSN_ST_D, SEM_FN_NAME (m32rbf,st_d) }, + { M32RBF_INSN_STB, SEM_FN_NAME (m32rbf,stb) }, + { M32RBF_INSN_STB_D, SEM_FN_NAME (m32rbf,stb_d) }, + { M32RBF_INSN_STH, SEM_FN_NAME (m32rbf,sth) }, + { M32RBF_INSN_STH_D, SEM_FN_NAME (m32rbf,sth_d) }, + { M32RBF_INSN_ST_PLUS, SEM_FN_NAME (m32rbf,st_plus) }, + { M32RBF_INSN_ST_MINUS, SEM_FN_NAME (m32rbf,st_minus) }, + { M32RBF_INSN_SUB, SEM_FN_NAME (m32rbf,sub) }, + { M32RBF_INSN_SUBV, SEM_FN_NAME (m32rbf,subv) }, + { M32RBF_INSN_SUBX, SEM_FN_NAME (m32rbf,subx) }, + { M32RBF_INSN_TRAP, SEM_FN_NAME (m32rbf,trap) }, + { M32RBF_INSN_UNLOCK, SEM_FN_NAME (m32rbf,unlock) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (m32rbf,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { +#if FAST_P + idesc_table[sf->index].sem_fast = sf->fn; +#else + idesc_table[sf->index].sem_full = sf->fn; +#endif + } +} + -- cgit v1.1