From 3fbeef0be80152e38e0b6966805f1dfc5c26df74 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Sun, 14 Jul 2002 00:15:20 +0000 Subject: Obsolete the d30v. --- sim/ChangeLog | 5 + sim/common/ChangeLog | 5 + sim/common/gennltvals.sh | 6 +- sim/common/nltvals.def | 24 - sim/configure | 10 +- sim/configure.in | 10 +- sim/d30v/ChangeLog | 6 + sim/d30v/Makefile.in | 434 ++--- sim/d30v/alu.h | 212 +- sim/d30v/cpu.c | 344 ++-- sim/d30v/cpu.h | 498 ++--- sim/d30v/d30v-insns | 4845 +++++++++++++++++++++++----------------------- sim/d30v/dc-short | 44 +- sim/d30v/engine.c | 992 +++++----- sim/d30v/ic-d30v | 160 +- sim/d30v/sim-calls.c | 728 +++---- sim/d30v/sim-main.h | 164 +- 17 files changed, 4238 insertions(+), 4249 deletions(-) (limited to 'sim') diff --git a/sim/ChangeLog b/sim/ChangeLog index a9f73ae..2a01ae9 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,8 @@ +2002-07-13 Andrew Cagney + + * configure.in (extra_subdirs): Mark d30v-*-* as obsolete. + * configure: Re-generate. + 2002-06-16 Andrew Cagney * Makefile.in (autoconf-changelog autoheader-changelog): Let name, diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index 84db793..d8a597d 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,8 @@ +2002-07-13 Andrew Cagney + + * gennltvals.sh (dir): Mark d30v as obsolete. + * nltvals.def: Remove d30v. + 2002-06-17 Andrew Cagney * hw-events.c (hw_event_queue_schedule): Initialize `dummy'. diff --git a/sim/common/gennltvals.sh b/sim/common/gennltvals.sh index 40ca5c7..fefd880 100644 --- a/sim/common/gennltvals.sh +++ b/sim/common/gennltvals.sh @@ -33,9 +33,9 @@ dir=newlib/libc/sys/d10v/sys target=d10v $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" -dir=libgloss target=d30v -$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ - "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" +# OBSOLETE dir=libgloss target=d30v +# OBSOLETE $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ +# OBSOLETE "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" dir=libgloss target=fr30 $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ diff --git a/sim/common/nltvals.def b/sim/common/nltvals.def index b5e82fc..14093ae 100644 --- a/sim/common/nltvals.def +++ b/sim/common/nltvals.def @@ -214,30 +214,6 @@ /* end d10v sys target macros */ #endif #endif -#ifdef NL_TARGET_d30v -#ifdef sys_defs -/* from syscall.h */ -/* begin d30v sys target macros */ - { "SYS_argv", 13 }, - { "SYS_argvlen", 12 }, - { "SYS_chdir", 14 }, - { "SYS_chmod", 16 }, - { "SYS_close", 3 }, - { "SYS_exit", 1 }, - { "SYS_fstat", 10 }, - { "SYS_getpid", 8 }, - { "SYS_kill", 9 }, - { "SYS_lseek", 6 }, - { "SYS_open", 2 }, - { "SYS_read", 4 }, - { "SYS_stat", 15 }, - { "SYS_time", 18 }, - { "SYS_unlink", 7 }, - { "SYS_utime", 17 }, - { "SYS_write", 5 }, -/* end d30v sys target macros */ -#endif -#endif #ifdef NL_TARGET_fr30 #ifdef sys_defs /* from syscall.h */ diff --git a/sim/configure b/sim/configure index b8029dd..f26af8b 100755 --- a/sim/configure +++ b/sim/configure @@ -1420,11 +1420,11 @@ case "${target}" in extra_subdirs="${extra_subdirs} testsuite" ;; d10v-*-*) sim_target=d10v ;; - d30v-*-*) - sim_target=d30v - only_if_gcc=yes - extra_subdirs="${extra_subdirs} igen" - ;; +# OBSOLETE d30v-*-*) +# OBSOLETE sim_target=d30v +# OBSOLETE only_if_gcc=yes +# OBSOLETE extra_subdirs="${extra_subdirs} igen" +# OBSOLETE ;; fr30-*-*) sim_target=fr30 ;; h8300*-*-*) sim_target=h8300 ;; h8500-*-*) sim_target=h8500 ;; diff --git a/sim/configure.in b/sim/configure.in index e48ae36..854ee63 100644 --- a/sim/configure.in +++ b/sim/configure.in @@ -59,11 +59,11 @@ case "${target}" in extra_subdirs="${extra_subdirs} testsuite" ;; d10v-*-*) sim_target=d10v ;; - d30v-*-*) - sim_target=d30v - only_if_gcc=yes - extra_subdirs="${extra_subdirs} igen" - ;; +# OBSOLETE d30v-*-*) +# OBSOLETE sim_target=d30v +# OBSOLETE only_if_gcc=yes +# OBSOLETE extra_subdirs="${extra_subdirs} igen" +# OBSOLETE ;; fr30-*-*) sim_target=fr30 ;; h8300*-*-*) sim_target=h8300 ;; h8500-*-*) sim_target=h8500 ;; diff --git a/sim/d30v/ChangeLog b/sim/d30v/ChangeLog index 2c3e1c4..d1c1df5 100644 --- a/sim/d30v/ChangeLog +++ b/sim/d30v/ChangeLog @@ -1,3 +1,9 @@ +2002-07-13 Andrew Cagney + + * cpu.h: Mark file obsolete. + * sim-main.h, sim-calls.c, engine.c, cpu.c, alu.h: Ditto. + * dc-short, ic-d30v, d30v-insns, Makefile.in: Ditto. + 2002-06-16 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/d30v/Makefile.in b/sim/d30v/Makefile.in index d563be8..76afe20 100644 --- a/sim/d30v/Makefile.in +++ b/sim/d30v/Makefile.in @@ -1,217 +1,217 @@ -# Mitsubishi Electric Corp. D30V Simulator. -# Copyright (C) 1997, Free Software Foundation, Inc. -# Contributed by Cygnus Support. -# -# This file is part of GDB, the GNU debugger. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -M4= @M4@ - - -## COMMON_PRE_CONFIG_FRAG - -# These variables are given default values in COMMON_PRE_CONFIG_FRAG. -# We override the ones we need to here. -# Not all of these need to be mentioned, only the necessary ones. - -# List of object files, less common parts. -SIM_OBJS = \ - $(SIM_NEW_COMMON_OBJS) \ - engine.o cpu.o \ - s_support.o l_support.o \ - s_idecode.o l_idecode.o \ - s_semantics.o l_semantics.o \ - sim-calls.o itable.o \ - sim-hload.o \ - sim-hrw.o \ - sim-engine.o \ - sim-stop.o \ - sim-reason.o \ - sim-resume.o - -# List of extra dependencies. -# Generally this consists of simulator specific files included by sim-main.h. -SIM_EXTRA_DEPS = itable.h s_idecode.h l_idecode.h cpu.h alu.h - -# List of generators -SIM_GEN=tmp-igen - -# List of extra flags to always pass to $(CC). -SIM_EXTRA_CFLAGS = @sim_trapdump@ - -# List of main object files for `run'. -SIM_RUN_OBJS = nrun.o - -# Dependency of `clean' to clean any extra files. -SIM_EXTRA_CLEAN = clean-igen - -# This selects the d30v newlib/libgloss syscall definitions. -NL_TARGET=-DNL_TARGET_d30v - -## COMMON_POST_CONFIG_FRAG - -MAIN_INCLUDE_DEPS = tconfig.h -INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) - -# Rules need to build $(SIM_OBJS), plus whatever else the target wants. - -# ... target specific rules ... - -# Filter to eliminate known warnings -FILTER = 2>&1 | egrep -v "Discarding instruction|instruction field of type \`compute\' changed to \`cache\'|Instruction format is not 64 bits wide" - -BUILT_SRC_FROM_IGEN = \ - s_icache.h \ - s_icache.c \ - s_idecode.h \ - s_idecode.c \ - s_semantics.h \ - s_semantics.c \ - s_model.h \ - s_model.c \ - s_support.h \ - s_support.c \ - l_icache.h \ - l_icache.c \ - l_idecode.h \ - l_idecode.c \ - l_semantics.h \ - l_semantics.c \ - l_model.h \ - l_model.c \ - l_support.h \ - l_support.c \ - itable.h itable.c -$(BUILT_SRC_FROM_IGEN): tmp-igen -# - -.PHONY: clean-igen -clean-igen: - rm -f $(BUILT_SRC_FROM_IGEN) - rm -f tmp-igen tmp-insns - -../igen/igen: - cd ../igen && $(MAKE) - -tmp-igen: $(srcdir)/dc-short $(srcdir)/d30v-insns $(srcdir)/ic-d30v ../igen/igen - cd ../igen && $(MAKE) - echo "# 1 \"$(srcdir)/d30v-insns\"" > tmp-insns - $(M4) < $(srcdir)/d30v-insns >> tmp-insns - @echo "Generating short version ..." - ../igen/igen \ - -G gen-zero-r0 \ - -G direct-access \ - -G default-nia-minus-one \ - -G conditional-issue \ - -G verify-slot \ - -G field-widths \ - -F short,emul \ - -B 32 \ - -P "s_" \ - -o $(srcdir)/dc-short \ - -k $(srcdir)/ic-d30v \ - -n $(srcdir)/d30v-insns -i tmp-insns \ - -n s_icache.h -hc tmp-icache.h \ - -n s_icache.c -c tmp-icache.c \ - -n s_semantics.h -hs tmp-semantics.h \ - -n s_semantics.c -s tmp-semantics.c \ - -n s_idecode.h -hd tmp-idecode.h \ - -n s_idecode.c -d tmp-idecode.c \ - -n s_model.h -hm tmp-model.h \ - -n s_model.c -m tmp-model.c \ - -n s_support.h -hf tmp-support.h \ - -n s_support.c -f tmp-support.c $(FILTER) - $(srcdir)/../../move-if-change tmp-icache.h s_icache.h - $(srcdir)/../../move-if-change tmp-icache.c s_icache.c - $(srcdir)/../../move-if-change tmp-idecode.h s_idecode.h - $(srcdir)/../../move-if-change tmp-idecode.c s_idecode.c - $(srcdir)/../../move-if-change tmp-semantics.h s_semantics.h - $(srcdir)/../../move-if-change tmp-semantics.c s_semantics.c - $(srcdir)/../../move-if-change tmp-model.h s_model.h - $(srcdir)/../../move-if-change tmp-model.c s_model.c - $(srcdir)/../../move-if-change tmp-support.h s_support.h - $(srcdir)/../../move-if-change tmp-support.c s_support.c - @echo "Generating long version ..." - ../igen/igen \ - -G gen-zero-r0 \ - -G direct-access \ - -G default-nia-minus-one \ - -G conditional-issue \ - -G field-widths \ - -F long,emul \ - -B 64 \ - -P "l_" \ - -o $(srcdir)/dc-short \ - -k $(srcdir)/ic-d30v \ - -i tmp-insns \ - -n l_icache.h -hc tmp-icache.h \ - -n l_icache.c -c tmp-icache.c \ - -n l_semantics.h -hs tmp-semantics.h \ - -n l_semantics.c -s tmp-semantics.c \ - -n l_idecode.h -hd tmp-idecode.h \ - -n l_idecode.c -d tmp-idecode.c \ - -n l_model.h -hm tmp-model.h \ - -n l_model.c -m tmp-model.c \ - -n l_support.h -hf tmp-support.h \ - -n l_support.c -f tmp-support.c $(FILTER) - $(srcdir)/../../move-if-change tmp-icache.h l_icache.h - $(srcdir)/../../move-if-change tmp-icache.c l_icache.c - $(srcdir)/../../move-if-change tmp-idecode.h l_idecode.h - $(srcdir)/../../move-if-change tmp-idecode.c l_idecode.c - $(srcdir)/../../move-if-change tmp-semantics.h l_semantics.h - $(srcdir)/../../move-if-change tmp-semantics.c l_semantics.c - $(srcdir)/../../move-if-change tmp-model.h l_model.h - $(srcdir)/../../move-if-change tmp-model.c l_model.c - $(srcdir)/../../move-if-change tmp-support.h l_support.h - $(srcdir)/../../move-if-change tmp-support.c l_support.c - @echo "Generating instruction database ..." - ../igen/igen \ - -G field-widths \ - -F short,long,emul \ - -B 64 \ - -o $(srcdir)/dc-short \ - -k $(srcdir)/ic-d30v \ - -i tmp-insns \ - -n itable.h -ht tmp-itable.h \ - -n itable.c -t tmp-itable.c $(FILTER) - $(srcdir)/../../move-if-change tmp-itable.h itable.h - $(srcdir)/../../move-if-change tmp-itable.c itable.c - touch tmp-igen - -ENGINE_H = \ - sim-main.h \ - $(srcdir)/../common/sim-basics.h \ - config.h \ - $(srcdir)/../common/sim-config.h \ - $(srcdir)/../common/sim-inline.h \ - $(srcdir)/../common/sim-types.h \ - $(srcdir)/../common/sim-bits.h \ - $(srcdir)/../common/sim-endian.h \ - itable.h \ - l_idecode.h s_idecode.h \ - cpu.h \ - alu.h \ - $(srcdir)/../common/sim-alu.h \ - $(srcdir)/../common/sim-core.h \ - $(srcdir)/../common/sim-events.h \ - -engine.o: engine.c $(ENGINE_H) -sim-calls.o: sim-calls.c $(ENGINE_H) $(srcdir)/../common/sim-utils.h $(srcdir)/../common/sim-options.h -cpu.o: cpu.c $(ENGINE_H) -s_support.o: s_support.c $(ENGINE_H) -l_support.o: l_support.c $(ENGINE_H) -s_semantics.o: s_semantics.c $(ENGINE_H) -l_semantics.o: l_semantics.c $(ENGINE_H) +# OBSOLETE # Mitsubishi Electric Corp. D30V Simulator. +# OBSOLETE # Copyright (C) 1997, Free Software Foundation, Inc. +# OBSOLETE # Contributed by Cygnus Support. +# OBSOLETE # +# OBSOLETE # This file is part of GDB, the GNU debugger. +# OBSOLETE # +# OBSOLETE # This program is free software; you can redistribute it and/or modify +# OBSOLETE # it under the terms of the GNU General Public License as published by +# OBSOLETE # the Free Software Foundation; either version 2, or (at your option) +# OBSOLETE # any later version. +# OBSOLETE # +# OBSOLETE # This program is distributed in the hope that it will be useful, +# OBSOLETE # but WITHOUT ANY WARRANTY; without even the implied warranty of +# OBSOLETE # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# OBSOLETE # GNU General Public License for more details. +# OBSOLETE # +# OBSOLETE # You should have received a copy of the GNU General Public License along +# OBSOLETE # with this program; if not, write to the Free Software Foundation, Inc., +# OBSOLETE # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +# OBSOLETE +# OBSOLETE M4= @M4@ +# OBSOLETE +# OBSOLETE +# OBSOLETE ## COMMON_PRE_CONFIG_FRAG +# OBSOLETE +# OBSOLETE # These variables are given default values in COMMON_PRE_CONFIG_FRAG. +# OBSOLETE # We override the ones we need to here. +# OBSOLETE # Not all of these need to be mentioned, only the necessary ones. +# OBSOLETE +# OBSOLETE # List of object files, less common parts. +# OBSOLETE SIM_OBJS = \ +# OBSOLETE $(SIM_NEW_COMMON_OBJS) \ +# OBSOLETE engine.o cpu.o \ +# OBSOLETE s_support.o l_support.o \ +# OBSOLETE s_idecode.o l_idecode.o \ +# OBSOLETE s_semantics.o l_semantics.o \ +# OBSOLETE sim-calls.o itable.o \ +# OBSOLETE sim-hload.o \ +# OBSOLETE sim-hrw.o \ +# OBSOLETE sim-engine.o \ +# OBSOLETE sim-stop.o \ +# OBSOLETE sim-reason.o \ +# OBSOLETE sim-resume.o +# OBSOLETE +# OBSOLETE # List of extra dependencies. +# OBSOLETE # Generally this consists of simulator specific files included by sim-main.h. +# OBSOLETE SIM_EXTRA_DEPS = itable.h s_idecode.h l_idecode.h cpu.h alu.h +# OBSOLETE +# OBSOLETE # List of generators +# OBSOLETE SIM_GEN=tmp-igen +# OBSOLETE +# OBSOLETE # List of extra flags to always pass to $(CC). +# OBSOLETE SIM_EXTRA_CFLAGS = @sim_trapdump@ +# OBSOLETE +# OBSOLETE # List of main object files for `run'. +# OBSOLETE SIM_RUN_OBJS = nrun.o +# OBSOLETE +# OBSOLETE # Dependency of `clean' to clean any extra files. +# OBSOLETE SIM_EXTRA_CLEAN = clean-igen +# OBSOLETE +# OBSOLETE # This selects the d30v newlib/libgloss syscall definitions. +# OBSOLETE NL_TARGET=-DNL_TARGET_d30v +# OBSOLETE +# OBSOLETE ## COMMON_POST_CONFIG_FRAG +# OBSOLETE +# OBSOLETE MAIN_INCLUDE_DEPS = tconfig.h +# OBSOLETE INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) +# OBSOLETE +# OBSOLETE # Rules need to build $(SIM_OBJS), plus whatever else the target wants. +# OBSOLETE +# OBSOLETE # ... target specific rules ... +# OBSOLETE +# OBSOLETE # Filter to eliminate known warnings +# OBSOLETE FILTER = 2>&1 | egrep -v "Discarding instruction|instruction field of type \`compute\' changed to \`cache\'|Instruction format is not 64 bits wide" +# OBSOLETE +# OBSOLETE BUILT_SRC_FROM_IGEN = \ +# OBSOLETE s_icache.h \ +# OBSOLETE s_icache.c \ +# OBSOLETE s_idecode.h \ +# OBSOLETE s_idecode.c \ +# OBSOLETE s_semantics.h \ +# OBSOLETE s_semantics.c \ +# OBSOLETE s_model.h \ +# OBSOLETE s_model.c \ +# OBSOLETE s_support.h \ +# OBSOLETE s_support.c \ +# OBSOLETE l_icache.h \ +# OBSOLETE l_icache.c \ +# OBSOLETE l_idecode.h \ +# OBSOLETE l_idecode.c \ +# OBSOLETE l_semantics.h \ +# OBSOLETE l_semantics.c \ +# OBSOLETE l_model.h \ +# OBSOLETE l_model.c \ +# OBSOLETE l_support.h \ +# OBSOLETE l_support.c \ +# OBSOLETE itable.h itable.c +# OBSOLETE $(BUILT_SRC_FROM_IGEN): tmp-igen +# OBSOLETE # +# OBSOLETE +# OBSOLETE .PHONY: clean-igen +# OBSOLETE clean-igen: +# OBSOLETE rm -f $(BUILT_SRC_FROM_IGEN) +# OBSOLETE rm -f tmp-igen tmp-insns +# OBSOLETE +# OBSOLETE ../igen/igen: +# OBSOLETE cd ../igen && $(MAKE) +# OBSOLETE +# OBSOLETE tmp-igen: $(srcdir)/dc-short $(srcdir)/d30v-insns $(srcdir)/ic-d30v ../igen/igen +# OBSOLETE cd ../igen && $(MAKE) +# OBSOLETE echo "# 1 \"$(srcdir)/d30v-insns\"" > tmp-insns +# OBSOLETE $(M4) < $(srcdir)/d30v-insns >> tmp-insns +# OBSOLETE @echo "Generating short version ..." +# OBSOLETE ../igen/igen \ +# OBSOLETE -G gen-zero-r0 \ +# OBSOLETE -G direct-access \ +# OBSOLETE -G default-nia-minus-one \ +# OBSOLETE -G conditional-issue \ +# OBSOLETE -G verify-slot \ +# OBSOLETE -G field-widths \ +# OBSOLETE -F short,emul \ +# OBSOLETE -B 32 \ +# OBSOLETE -P "s_" \ +# OBSOLETE -o $(srcdir)/dc-short \ +# OBSOLETE -k $(srcdir)/ic-d30v \ +# OBSOLETE -n $(srcdir)/d30v-insns -i tmp-insns \ +# OBSOLETE -n s_icache.h -hc tmp-icache.h \ +# OBSOLETE -n s_icache.c -c tmp-icache.c \ +# OBSOLETE -n s_semantics.h -hs tmp-semantics.h \ +# OBSOLETE -n s_semantics.c -s tmp-semantics.c \ +# OBSOLETE -n s_idecode.h -hd tmp-idecode.h \ +# OBSOLETE -n s_idecode.c -d tmp-idecode.c \ +# OBSOLETE -n s_model.h -hm tmp-model.h \ +# OBSOLETE -n s_model.c -m tmp-model.c \ +# OBSOLETE -n s_support.h -hf tmp-support.h \ +# OBSOLETE -n s_support.c -f tmp-support.c $(FILTER) +# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.h s_icache.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.c s_icache.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.h s_idecode.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.c s_idecode.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.h s_semantics.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.c s_semantics.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-model.h s_model.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-model.c s_model.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-support.h s_support.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-support.c s_support.c +# OBSOLETE @echo "Generating long version ..." +# OBSOLETE ../igen/igen \ +# OBSOLETE -G gen-zero-r0 \ +# OBSOLETE -G direct-access \ +# OBSOLETE -G default-nia-minus-one \ +# OBSOLETE -G conditional-issue \ +# OBSOLETE -G field-widths \ +# OBSOLETE -F long,emul \ +# OBSOLETE -B 64 \ +# OBSOLETE -P "l_" \ +# OBSOLETE -o $(srcdir)/dc-short \ +# OBSOLETE -k $(srcdir)/ic-d30v \ +# OBSOLETE -i tmp-insns \ +# OBSOLETE -n l_icache.h -hc tmp-icache.h \ +# OBSOLETE -n l_icache.c -c tmp-icache.c \ +# OBSOLETE -n l_semantics.h -hs tmp-semantics.h \ +# OBSOLETE -n l_semantics.c -s tmp-semantics.c \ +# OBSOLETE -n l_idecode.h -hd tmp-idecode.h \ +# OBSOLETE -n l_idecode.c -d tmp-idecode.c \ +# OBSOLETE -n l_model.h -hm tmp-model.h \ +# OBSOLETE -n l_model.c -m tmp-model.c \ +# OBSOLETE -n l_support.h -hf tmp-support.h \ +# OBSOLETE -n l_support.c -f tmp-support.c $(FILTER) +# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.h l_icache.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.c l_icache.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.h l_idecode.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.c l_idecode.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.h l_semantics.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.c l_semantics.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-model.h l_model.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-model.c l_model.c +# OBSOLETE $(srcdir)/../../move-if-change tmp-support.h l_support.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-support.c l_support.c +# OBSOLETE @echo "Generating instruction database ..." +# OBSOLETE ../igen/igen \ +# OBSOLETE -G field-widths \ +# OBSOLETE -F short,long,emul \ +# OBSOLETE -B 64 \ +# OBSOLETE -o $(srcdir)/dc-short \ +# OBSOLETE -k $(srcdir)/ic-d30v \ +# OBSOLETE -i tmp-insns \ +# OBSOLETE -n itable.h -ht tmp-itable.h \ +# OBSOLETE -n itable.c -t tmp-itable.c $(FILTER) +# OBSOLETE $(srcdir)/../../move-if-change tmp-itable.h itable.h +# OBSOLETE $(srcdir)/../../move-if-change tmp-itable.c itable.c +# OBSOLETE touch tmp-igen +# OBSOLETE +# OBSOLETE ENGINE_H = \ +# OBSOLETE sim-main.h \ +# OBSOLETE $(srcdir)/../common/sim-basics.h \ +# OBSOLETE config.h \ +# OBSOLETE $(srcdir)/../common/sim-config.h \ +# OBSOLETE $(srcdir)/../common/sim-inline.h \ +# OBSOLETE $(srcdir)/../common/sim-types.h \ +# OBSOLETE $(srcdir)/../common/sim-bits.h \ +# OBSOLETE $(srcdir)/../common/sim-endian.h \ +# OBSOLETE itable.h \ +# OBSOLETE l_idecode.h s_idecode.h \ +# OBSOLETE cpu.h \ +# OBSOLETE alu.h \ +# OBSOLETE $(srcdir)/../common/sim-alu.h \ +# OBSOLETE $(srcdir)/../common/sim-core.h \ +# OBSOLETE $(srcdir)/../common/sim-events.h \ +# OBSOLETE +# OBSOLETE engine.o: engine.c $(ENGINE_H) +# OBSOLETE sim-calls.o: sim-calls.c $(ENGINE_H) $(srcdir)/../common/sim-utils.h $(srcdir)/../common/sim-options.h +# OBSOLETE cpu.o: cpu.c $(ENGINE_H) +# OBSOLETE s_support.o: s_support.c $(ENGINE_H) +# OBSOLETE l_support.o: l_support.c $(ENGINE_H) +# OBSOLETE s_semantics.o: s_semantics.c $(ENGINE_H) +# OBSOLETE l_semantics.o: l_semantics.c $(ENGINE_H) diff --git a/sim/d30v/alu.h b/sim/d30v/alu.h index d39ee3f..5605ce2 100644 --- a/sim/d30v/alu.h +++ b/sim/d30v/alu.h @@ -1,106 +1,106 @@ -/* Mitsubishi Electric Corp. D30V Simulator. - Copyright (C) 1997, Free Software Foundation, Inc. - Contributed by Cygnus Support. - -This file is part of GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#ifndef _D30V_ALU_H_ -#define _D30V_ALU_H_ - -#define ALU_CARRY (PSW_VAL(PSW_C) != 0) - -#include "sim-alu.h" - -#define ALU16_END(TARG, HIGH) \ -{ \ - unsigned32 mask, value; \ - if (ALU16_HAD_OVERFLOW) { \ - mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \ - value = BIT32 (PSW_V) | BIT32 (PSW_VA); \ - } \ - else { \ - mask = BIT32 (PSW_V) | BIT32 (PSW_C); \ - value = 0; \ - } \ - if (ALU16_HAD_CARRY_BORROW) \ - value |= BIT32 (PSW_C); \ - if (HIGH) \ - WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT<<16, 0xffff0000); \ - else \ - WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT, 0x0000ffff); \ - WRITE32_QUEUE_MASK (&PSW, value, mask); \ -} - -#define ALU32_END(TARG) \ -{ \ - unsigned32 mask, value; \ - if (ALU32_HAD_OVERFLOW) { \ - mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \ - value = BIT32 (PSW_V) | BIT32 (PSW_VA); \ - } \ - else { \ - mask = BIT32 (PSW_V) | BIT32 (PSW_C); \ - value = 0; \ - } \ - if (ALU32_HAD_CARRY_BORROW) \ - value |= BIT32 (PSW_C); \ - WRITE32_QUEUE (TARG, ALU32_OVERFLOW_RESULT); \ - WRITE32_QUEUE_MASK (&PSW, value, mask); \ -} - -#define ALU_END(TARG) ALU32_END(TARG) - - -/* PSW & Flag manipulation */ - -#define PSW_SET(BIT,VAL) BLIT32(PSW, (BIT), (VAL)) -#define PSW_VAL(BIT) EXTRACTED32(PSW, (BIT), (BIT)) - -#define PSW_F(FLAG) (17 + ((FLAG) % 8) * 2) -#define PSW_FLAG_SET(FLAG,VAL) PSW_SET(PSW_F(FLAG), VAL) -#define PSW_FLAG_VAL(FLAG) PSW_VAL(PSW_F(FLAG)) - -#define PSW_SET_QUEUE(BIT,VAL) \ -do { \ - unsigned32 mask = BIT32 (BIT); \ - unsigned32 bitval = (VAL) ? mask : 0; \ - WRITE32_QUEUE_MASK (&PSW, bitval, mask); \ -} while (0) - -#define PSW_FLAG_SET_QUEUE(FLAG,VAL) \ -do { \ - unsigned32 mask = BIT32 (PSW_F (FLAG)); \ - unsigned32 bitval = (VAL) ? mask : 0; \ - WRITE32_QUEUE_MASK (&PSW, bitval, mask); \ -} while (0) - -/* Bring data in from the cold */ - -#define IMEM(EA) \ -(sim_core_read_8(STATE_CPU (sd, 0), cia, exec_map, (EA))) - -#define MEM(SIGN, EA, NR_BYTES) \ -((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, read_map, (EA))) - -#define STORE(EA, NR_BYTES, VAL) \ -do { \ - sim_core_write_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, write_map, (EA), (VAL)); \ -} while (0) - - -#endif +/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */ +/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */ +/* OBSOLETE Contributed by Cygnus Support. */ +/* OBSOLETE */ +/* OBSOLETE This file is part of GDB, the GNU debugger. */ +/* OBSOLETE */ +/* OBSOLETE This program is free software; you can redistribute it and/or modify */ +/* OBSOLETE it under the terms of the GNU General Public License as published by */ +/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */ +/* OBSOLETE any later version. */ +/* OBSOLETE */ +/* OBSOLETE This program is distributed in the hope that it will be useful, */ +/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* OBSOLETE GNU General Public License for more details. */ +/* OBSOLETE */ +/* OBSOLETE You should have received a copy of the GNU General Public License along */ +/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */ +/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #ifndef _D30V_ALU_H_ */ +/* OBSOLETE #define _D30V_ALU_H_ */ +/* OBSOLETE */ +/* OBSOLETE #define ALU_CARRY (PSW_VAL(PSW_C) != 0) */ +/* OBSOLETE */ +/* OBSOLETE #include "sim-alu.h" */ +/* OBSOLETE */ +/* OBSOLETE #define ALU16_END(TARG, HIGH) \ */ +/* OBSOLETE { \ */ +/* OBSOLETE unsigned32 mask, value; \ */ +/* OBSOLETE if (ALU16_HAD_OVERFLOW) { \ */ +/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \ */ +/* OBSOLETE value = BIT32 (PSW_V) | BIT32 (PSW_VA); \ */ +/* OBSOLETE } \ */ +/* OBSOLETE else { \ */ +/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_C); \ */ +/* OBSOLETE value = 0; \ */ +/* OBSOLETE } \ */ +/* OBSOLETE if (ALU16_HAD_CARRY_BORROW) \ */ +/* OBSOLETE value |= BIT32 (PSW_C); \ */ +/* OBSOLETE if (HIGH) \ */ +/* OBSOLETE WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT<<16, 0xffff0000); \ */ +/* OBSOLETE else \ */ +/* OBSOLETE WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT, 0x0000ffff); \ */ +/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, value, mask); \ */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE #define ALU32_END(TARG) \ */ +/* OBSOLETE { \ */ +/* OBSOLETE unsigned32 mask, value; \ */ +/* OBSOLETE if (ALU32_HAD_OVERFLOW) { \ */ +/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \ */ +/* OBSOLETE value = BIT32 (PSW_V) | BIT32 (PSW_VA); \ */ +/* OBSOLETE } \ */ +/* OBSOLETE else { \ */ +/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_C); \ */ +/* OBSOLETE value = 0; \ */ +/* OBSOLETE } \ */ +/* OBSOLETE if (ALU32_HAD_CARRY_BORROW) \ */ +/* OBSOLETE value |= BIT32 (PSW_C); \ */ +/* OBSOLETE WRITE32_QUEUE (TARG, ALU32_OVERFLOW_RESULT); \ */ +/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, value, mask); \ */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE #define ALU_END(TARG) ALU32_END(TARG) */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE /* PSW & Flag manipulation */ */ +/* OBSOLETE */ +/* OBSOLETE #define PSW_SET(BIT,VAL) BLIT32(PSW, (BIT), (VAL)) */ +/* OBSOLETE #define PSW_VAL(BIT) EXTRACTED32(PSW, (BIT), (BIT)) */ +/* OBSOLETE */ +/* OBSOLETE #define PSW_F(FLAG) (17 + ((FLAG) % 8) * 2) */ +/* OBSOLETE #define PSW_FLAG_SET(FLAG,VAL) PSW_SET(PSW_F(FLAG), VAL) */ +/* OBSOLETE #define PSW_FLAG_VAL(FLAG) PSW_VAL(PSW_F(FLAG)) */ +/* OBSOLETE */ +/* OBSOLETE #define PSW_SET_QUEUE(BIT,VAL) \ */ +/* OBSOLETE do { \ */ +/* OBSOLETE unsigned32 mask = BIT32 (BIT); \ */ +/* OBSOLETE unsigned32 bitval = (VAL) ? mask : 0; \ */ +/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, bitval, mask); \ */ +/* OBSOLETE } while (0) */ +/* OBSOLETE */ +/* OBSOLETE #define PSW_FLAG_SET_QUEUE(FLAG,VAL) \ */ +/* OBSOLETE do { \ */ +/* OBSOLETE unsigned32 mask = BIT32 (PSW_F (FLAG)); \ */ +/* OBSOLETE unsigned32 bitval = (VAL) ? mask : 0; \ */ +/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, bitval, mask); \ */ +/* OBSOLETE } while (0) */ +/* OBSOLETE */ +/* OBSOLETE /* Bring data in from the cold */ */ +/* OBSOLETE */ +/* OBSOLETE #define IMEM(EA) \ */ +/* OBSOLETE (sim_core_read_8(STATE_CPU (sd, 0), cia, exec_map, (EA))) */ +/* OBSOLETE */ +/* OBSOLETE #define MEM(SIGN, EA, NR_BYTES) \ */ +/* OBSOLETE ((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, read_map, (EA))) */ +/* OBSOLETE */ +/* OBSOLETE #define STORE(EA, NR_BYTES, VAL) \ */ +/* OBSOLETE do { \ */ +/* OBSOLETE sim_core_write_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, write_map, (EA), (VAL)); \ */ +/* OBSOLETE } while (0) */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #endif */ diff --git a/sim/d30v/cpu.c b/sim/d30v/cpu.c index c14a951..32d8829 100644 --- a/sim/d30v/cpu.c +++ b/sim/d30v/cpu.c @@ -1,172 +1,172 @@ -/* Mitsubishi Electric Corp. D30V Simulator. - Copyright (C) 1997, Free Software Foundation, Inc. - Contributed by Cygnus Support. - -This file is part of GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#ifndef _CPU_C_ -#define _CPU_C_ - -#include "sim-main.h" - - -int -is_wrong_slot (SIM_DESC sd, - address_word cia, - itable_index index) -{ - switch (STATE_CPU (sd, 0)->unit) - { - case memory_unit: - return !itable[index].option[itable_option_mu]; - case integer_unit: - return !itable[index].option[itable_option_iu]; - case any_unit: - return 0; - default: - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, - "internal error - is_wrong_slot - bad switch"); - return -1; - } -} - -int -is_condition_ok (SIM_DESC sd, - address_word cia, - int cond) -{ - switch (cond) - { - case 0x0: - return 1; - case 0x1: - return PSW_VAL(PSW_F0); - case 0x2: - return !PSW_VAL(PSW_F0); - case 0x3: - return PSW_VAL(PSW_F1); - case 0x4: - return !PSW_VAL(PSW_F1); - case 0x5: - return PSW_VAL(PSW_F0) && PSW_VAL(PSW_F1); - case 0x6: - return PSW_VAL(PSW_F0) && !PSW_VAL(PSW_F1); - case 0x7: - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, - "is_condition_ok - bad instruction condition bits"); - return 0; - default: - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, - "internal error - is_condition_ok - bad switch"); - return -1; - } -} - -/* If --trace-call, trace calls, remembering the current state of - registers. */ - -typedef struct _call_stack { - struct _call_stack *prev; - registers regs; -} call_stack; - -static call_stack *call_stack_head = (call_stack *)0; -static int call_depth = 0; - -void call_occurred (SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - address_word nia) -{ - call_stack *ptr = ZALLOC (call_stack); - ptr->regs = cpu->regs; - ptr->prev = call_stack_head; - call_stack_head = ptr; - - trace_one_insn (sd, cpu, nia, 1, "", 0, "call", - "Depth %3d, Return 0x%.8lx, Args 0x%.8lx 0x%.8lx", - ++call_depth, (unsigned long)cia+8, (unsigned long)GPR[2], - (unsigned long)GPR[3]); -} - -/* If --trace-call, trace returns, checking if any saved register was changed. */ - -void return_occurred (SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - address_word nia) -{ - char buffer[1024]; - char *buf_ptr = buffer; - call_stack *ptr = call_stack_head; - int regno; - char *prefix = ", Registers that differ: "; - - *buf_ptr = '\0'; - for (regno = 34; regno <= 63; regno++) { - if (cpu->regs.general_purpose[regno] != ptr->regs.general_purpose[regno]) { - sprintf (buf_ptr, "%sr%d", prefix, regno); - buf_ptr += strlen (buf_ptr); - prefix = " "; - } - } - - if (cpu->regs.accumulator[1] != ptr->regs.accumulator[1]) { - sprintf (buf_ptr, "%sa1", prefix); - buf_ptr += strlen (buf_ptr); - prefix = " "; - } - - trace_one_insn (sd, cpu, cia, 1, "", 0, "return", - "Depth %3d, Return 0x%.8lx, Ret. 0x%.8lx 0x%.8lx%s", - call_depth--, (unsigned long)nia, (unsigned long)GPR[2], - (unsigned long)GPR[3], buffer); - - call_stack_head = ptr->prev; - zfree (ptr); -} - - -/* Read/write functions for system call interface. */ -int -d30v_read_mem (host_callback *cb, - struct cb_syscall *sc, - unsigned long taddr, - char *buf, - int bytes) -{ - SIM_DESC sd = (SIM_DESC) sc->p1; - sim_cpu *cpu = STATE_CPU (sd, 0); - - return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); -} - -int -d30v_write_mem (host_callback *cb, - struct cb_syscall *sc, - unsigned long taddr, - const char *buf, - int bytes) -{ - SIM_DESC sd = (SIM_DESC) sc->p1; - sim_cpu *cpu = STATE_CPU (sd, 0); - - return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); -} - -#endif /* _CPU_C_ */ +/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */ +/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */ +/* OBSOLETE Contributed by Cygnus Support. */ +/* OBSOLETE */ +/* OBSOLETE This file is part of GDB, the GNU debugger. */ +/* OBSOLETE */ +/* OBSOLETE This program is free software; you can redistribute it and/or modify */ +/* OBSOLETE it under the terms of the GNU General Public License as published by */ +/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */ +/* OBSOLETE any later version. */ +/* OBSOLETE */ +/* OBSOLETE This program is distributed in the hope that it will be useful, */ +/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* OBSOLETE GNU General Public License for more details. */ +/* OBSOLETE */ +/* OBSOLETE You should have received a copy of the GNU General Public License along */ +/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */ +/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #ifndef _CPU_C_ */ +/* OBSOLETE #define _CPU_C_ */ +/* OBSOLETE */ +/* OBSOLETE #include "sim-main.h" */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE int */ +/* OBSOLETE is_wrong_slot (SIM_DESC sd, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE itable_index index) */ +/* OBSOLETE { */ +/* OBSOLETE switch (STATE_CPU (sd, 0)->unit) */ +/* OBSOLETE { */ +/* OBSOLETE case memory_unit: */ +/* OBSOLETE return !itable[index].option[itable_option_mu]; */ +/* OBSOLETE case integer_unit: */ +/* OBSOLETE return !itable[index].option[itable_option_iu]; */ +/* OBSOLETE case any_unit: */ +/* OBSOLETE return 0; */ +/* OBSOLETE default: */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */ +/* OBSOLETE "internal error - is_wrong_slot - bad switch"); */ +/* OBSOLETE return -1; */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE int */ +/* OBSOLETE is_condition_ok (SIM_DESC sd, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE int cond) */ +/* OBSOLETE { */ +/* OBSOLETE switch (cond) */ +/* OBSOLETE { */ +/* OBSOLETE case 0x0: */ +/* OBSOLETE return 1; */ +/* OBSOLETE case 0x1: */ +/* OBSOLETE return PSW_VAL(PSW_F0); */ +/* OBSOLETE case 0x2: */ +/* OBSOLETE return !PSW_VAL(PSW_F0); */ +/* OBSOLETE case 0x3: */ +/* OBSOLETE return PSW_VAL(PSW_F1); */ +/* OBSOLETE case 0x4: */ +/* OBSOLETE return !PSW_VAL(PSW_F1); */ +/* OBSOLETE case 0x5: */ +/* OBSOLETE return PSW_VAL(PSW_F0) && PSW_VAL(PSW_F1); */ +/* OBSOLETE case 0x6: */ +/* OBSOLETE return PSW_VAL(PSW_F0) && !PSW_VAL(PSW_F1); */ +/* OBSOLETE case 0x7: */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */ +/* OBSOLETE "is_condition_ok - bad instruction condition bits"); */ +/* OBSOLETE return 0; */ +/* OBSOLETE default: */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */ +/* OBSOLETE "internal error - is_condition_ok - bad switch"); */ +/* OBSOLETE return -1; */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* If --trace-call, trace calls, remembering the current state of */ +/* OBSOLETE registers. */ */ +/* OBSOLETE */ +/* OBSOLETE typedef struct _call_stack { */ +/* OBSOLETE struct _call_stack *prev; */ +/* OBSOLETE registers regs; */ +/* OBSOLETE } call_stack; */ +/* OBSOLETE */ +/* OBSOLETE static call_stack *call_stack_head = (call_stack *)0; */ +/* OBSOLETE static int call_depth = 0; */ +/* OBSOLETE */ +/* OBSOLETE void call_occurred (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE address_word nia) */ +/* OBSOLETE { */ +/* OBSOLETE call_stack *ptr = ZALLOC (call_stack); */ +/* OBSOLETE ptr->regs = cpu->regs; */ +/* OBSOLETE ptr->prev = call_stack_head; */ +/* OBSOLETE call_stack_head = ptr; */ +/* OBSOLETE */ +/* OBSOLETE trace_one_insn (sd, cpu, nia, 1, "", 0, "call", */ +/* OBSOLETE "Depth %3d, Return 0x%.8lx, Args 0x%.8lx 0x%.8lx", */ +/* OBSOLETE ++call_depth, (unsigned long)cia+8, (unsigned long)GPR[2], */ +/* OBSOLETE (unsigned long)GPR[3]); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* If --trace-call, trace returns, checking if any saved register was changed. */ */ +/* OBSOLETE */ +/* OBSOLETE void return_occurred (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE address_word nia) */ +/* OBSOLETE { */ +/* OBSOLETE char buffer[1024]; */ +/* OBSOLETE char *buf_ptr = buffer; */ +/* OBSOLETE call_stack *ptr = call_stack_head; */ +/* OBSOLETE int regno; */ +/* OBSOLETE char *prefix = ", Registers that differ: "; */ +/* OBSOLETE */ +/* OBSOLETE *buf_ptr = '\0'; */ +/* OBSOLETE for (regno = 34; regno <= 63; regno++) { */ +/* OBSOLETE if (cpu->regs.general_purpose[regno] != ptr->regs.general_purpose[regno]) { */ +/* OBSOLETE sprintf (buf_ptr, "%sr%d", prefix, regno); */ +/* OBSOLETE buf_ptr += strlen (buf_ptr); */ +/* OBSOLETE prefix = " "; */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE if (cpu->regs.accumulator[1] != ptr->regs.accumulator[1]) { */ +/* OBSOLETE sprintf (buf_ptr, "%sa1", prefix); */ +/* OBSOLETE buf_ptr += strlen (buf_ptr); */ +/* OBSOLETE prefix = " "; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "", 0, "return", */ +/* OBSOLETE "Depth %3d, Return 0x%.8lx, Ret. 0x%.8lx 0x%.8lx%s", */ +/* OBSOLETE call_depth--, (unsigned long)nia, (unsigned long)GPR[2], */ +/* OBSOLETE (unsigned long)GPR[3], buffer); */ +/* OBSOLETE */ +/* OBSOLETE call_stack_head = ptr->prev; */ +/* OBSOLETE zfree (ptr); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE /* Read/write functions for system call interface. */ */ +/* OBSOLETE int */ +/* OBSOLETE d30v_read_mem (host_callback *cb, */ +/* OBSOLETE struct cb_syscall *sc, */ +/* OBSOLETE unsigned long taddr, */ +/* OBSOLETE char *buf, */ +/* OBSOLETE int bytes) */ +/* OBSOLETE { */ +/* OBSOLETE SIM_DESC sd = (SIM_DESC) sc->p1; */ +/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */ +/* OBSOLETE */ +/* OBSOLETE return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE int */ +/* OBSOLETE d30v_write_mem (host_callback *cb, */ +/* OBSOLETE struct cb_syscall *sc, */ +/* OBSOLETE unsigned long taddr, */ +/* OBSOLETE const char *buf, */ +/* OBSOLETE int bytes) */ +/* OBSOLETE { */ +/* OBSOLETE SIM_DESC sd = (SIM_DESC) sc->p1; */ +/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */ +/* OBSOLETE */ +/* OBSOLETE return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE #endif /* _CPU_C_ */ */ diff --git a/sim/d30v/cpu.h b/sim/d30v/cpu.h index 56f749c..1e9f3d8 100644 --- a/sim/d30v/cpu.h +++ b/sim/d30v/cpu.h @@ -1,249 +1,249 @@ -/* Mitsubishi Electric Corp. D30V Simulator. - Copyright (C) 1997, Free Software Foundation, Inc. - Contributed by Cygnus Support. - -This file is part of GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#ifndef _CPU_H_ -#define _CPU_H_ - -enum { - NR_GENERAL_PURPOSE_REGISTERS = 64, - NR_CONTROL_REGISTERS = 64, - NR_ACCUMULATORS = 2, - STACK_POINTER_GPR = 63, - NR_STACK_POINTERS = 2, -}; - -enum { - processor_status_word_cr = 0, - backup_processor_status_word_cr = 1, - program_counter_cr = 2, - backup_program_counter_cr = 3, - debug_backup_processor_status_word_cr = 4, - debug_backup_program_counter_cr = 5, - reserved_6_cr = 6, - repeat_count_cr = 7, - repeat_start_address_cr = 8, - repeat_end_address_cr = 9, - modulo_start_address_cr = 10, - modulo_end_address_cr = 11, - instruction_break_address_cr = 14, - eit_vector_base_cr = 15, -}; - - -enum { - PSW_SM = 0, - PSW_EA = 2, - PSW_DB = 3, - PSW_DS = 4, - PSW_IE = 5, - PSW_RP = 6, - PSW_MD = 7, - PSW_F0 = 17, - PSW_F1 = 19, - PSW_F2 = 21, - PSW_F3 = 23, - PSW_S = 25, - PSW_V = 27, - PSW_VA = 29, - PSW_C = 31, -}; - -/* aliases for PSW flag numbers (F0..F7) */ -enum -{ - PSW_S_FLAG = 4, -}; - -typedef struct _registers { - unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS]; - /* keep track of the stack pointer */ - unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */ - unsigned32 current_sp; - unsigned32 control[NR_CONTROL_REGISTERS]; - unsigned64 accumulator[NR_ACCUMULATORS]; -} registers; - -typedef enum _cpu_units { - memory_unit, - integer_unit, - any_unit, -} cpu_units; - -/* In order to support parallel instructions, which one instruction can be - writing to a register that is used as input to another, queue up the - writes to the end of the instruction boundaries. */ - -#define MAX_WRITE32 16 -#define MAX_WRITE64 2 - -struct _write32 { - int num; /* # of 32-bit writes queued up */ - unsigned32 value[MAX_WRITE32]; /* value to write */ - unsigned32 mask[MAX_WRITE32]; /* mask to use */ - unsigned32 *ptr[MAX_WRITE32]; /* address to write to */ -}; - -struct _write64 { - int num; /* # of 64-bit writes queued up */ - unsigned64 value[MAX_WRITE64]; /* value to write */ - unsigned64 *ptr[MAX_WRITE64]; /* address to write to */ -}; - -struct _sim_cpu { - cpu_units unit; - registers regs; - sim_cpu_base base; - int trace_call_p; /* Whether to do call tracing. */ - int trace_trap_p; /* If unknown traps dump out the regs */ - int trace_action; /* trace bits at end of instructions */ - int left_kills_right_p; /* left insn kills insn in right slot of -> */ - int mvtsys_left_p; /* left insn was mvtsys */ - int did_trap; /* we did a trap & need to finish it */ - struct _write32 write32; /* queued up 32-bit writes */ - struct _write64 write64; /* queued up 64-bit writes */ -}; - -#define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr]) -#define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr]) -#define PSWL (*AL2_4(&PSW)) -#define PSWH (*AH2_4(&PSW)) -#define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr]) -#define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr]) -#define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr]) -#define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr]) -#define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr]) -#define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr]) -#define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr]) -#define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr]) -#define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr]) -#define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr]) -#define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr]) -#define GPR (STATE_CPU (sd, 0)->regs.general_purpose) -#define GPR_CLEAR(N) (GPR[(N)] = 0) -#define ACC (STATE_CPU (sd, 0)->regs.accumulator) -#define CREG (STATE_CPU (sd, 0)->regs.control) -#define SP (GPR[STACK_POINTER_GPR]) -#define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p) -#define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p) -#define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action) -#define TRACE_ACTION_CALL 0x00000001 /* call occurred */ -#define TRACE_ACTION_RETURN 0x00000002 /* return occurred */ - -#define WRITE32 (STATE_CPU (sd, 0)->write32) -#define WRITE32_NUM (WRITE32.num) -#define WRITE32_PTR(N) (WRITE32.ptr[N]) -#define WRITE32_MASK(N) (WRITE32.mask[N]) -#define WRITE32_VALUE(N) (WRITE32.value[N]) -#define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff) - -#define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \ -do { \ - int _num = WRITE32_NUM; \ - if (_num >= MAX_WRITE32) \ - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ - "Too many queued 32-bit writes"); \ - WRITE32_PTR(_num) = PTR; \ - WRITE32_VALUE(_num) = VALUE; \ - WRITE32_MASK(_num) = MASK; \ - WRITE32_NUM = _num+1; \ -} while (0) - -#define DID_TRAP (STATE_CPU (sd, 0)->did_trap) - -#define WRITE64 (STATE_CPU (sd, 0)->write64) -#define WRITE64_NUM (WRITE64.num) -#define WRITE64_PTR(N) (WRITE64.ptr[N]) -#define WRITE64_VALUE(N) (WRITE64.value[N]) -#define WRITE64_QUEUE(PTR, VALUE) \ -do { \ - int _num = WRITE64_NUM; \ - if (_num >= MAX_WRITE64) \ - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ - "Too many queued 64-bit writes"); \ - WRITE64_PTR(_num) = PTR; \ - WRITE64_VALUE(_num) = VALUE; \ - WRITE64_NUM = _num+1; \ -} while (0) - -#define DPSW_VALID 0xbf005555 -#define PSW_VALID 0xb7005555 -#define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */ -#define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */ - -/* Verify that the instruction is in the correct slot */ - -#define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX) -extern int is_wrong_slot -(SIM_DESC sd, - address_word cia, - itable_index index); - -#define IS_CONDITION_OK is_condition_ok(sd, cia, CCC) -extern int is_condition_ok -(SIM_DESC sd, - address_word cia, - int cond); - -#define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */ - -/* Internal breakpoint instruction is syscall 5 */ -#define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05} -#define SIM_BREAKPOINT_SIZE (4) - -/* Call occurred */ -extern void call_occurred -(SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - address_word nia); - -/* Return occurred */ -extern void return_occurred -(SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - address_word nia); - -/* Whether to do call tracing. */ -extern int d30v_call_trace_p; - -/* Read/write functions for system call interface. */ -extern int d30v_read_mem -(host_callback *cb, - struct cb_syscall *sc, - unsigned long taddr, - char *buf, - int bytes); - -extern int d30v_write_mem -(host_callback *cb, - struct cb_syscall *sc, - unsigned long taddr, - const char *buf, - int bytes); - -/* Process all of the queued up writes in order now */ -void unqueue_writes -(SIM_DESC sd, - sim_cpu *cpu, - address_word cia); - -#endif /* _CPU_H_ */ +/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */ +/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */ +/* OBSOLETE Contributed by Cygnus Support. */ +/* OBSOLETE */ +/* OBSOLETE This file is part of GDB, the GNU debugger. */ +/* OBSOLETE */ +/* OBSOLETE This program is free software; you can redistribute it and/or modify */ +/* OBSOLETE it under the terms of the GNU General Public License as published by */ +/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */ +/* OBSOLETE any later version. */ +/* OBSOLETE */ +/* OBSOLETE This program is distributed in the hope that it will be useful, */ +/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* OBSOLETE GNU General Public License for more details. */ +/* OBSOLETE */ +/* OBSOLETE You should have received a copy of the GNU General Public License along */ +/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */ +/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #ifndef _CPU_H_ */ +/* OBSOLETE #define _CPU_H_ */ +/* OBSOLETE */ +/* OBSOLETE enum { */ +/* OBSOLETE NR_GENERAL_PURPOSE_REGISTERS = 64, */ +/* OBSOLETE NR_CONTROL_REGISTERS = 64, */ +/* OBSOLETE NR_ACCUMULATORS = 2, */ +/* OBSOLETE STACK_POINTER_GPR = 63, */ +/* OBSOLETE NR_STACK_POINTERS = 2, */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE enum { */ +/* OBSOLETE processor_status_word_cr = 0, */ +/* OBSOLETE backup_processor_status_word_cr = 1, */ +/* OBSOLETE program_counter_cr = 2, */ +/* OBSOLETE backup_program_counter_cr = 3, */ +/* OBSOLETE debug_backup_processor_status_word_cr = 4, */ +/* OBSOLETE debug_backup_program_counter_cr = 5, */ +/* OBSOLETE reserved_6_cr = 6, */ +/* OBSOLETE repeat_count_cr = 7, */ +/* OBSOLETE repeat_start_address_cr = 8, */ +/* OBSOLETE repeat_end_address_cr = 9, */ +/* OBSOLETE modulo_start_address_cr = 10, */ +/* OBSOLETE modulo_end_address_cr = 11, */ +/* OBSOLETE instruction_break_address_cr = 14, */ +/* OBSOLETE eit_vector_base_cr = 15, */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE enum { */ +/* OBSOLETE PSW_SM = 0, */ +/* OBSOLETE PSW_EA = 2, */ +/* OBSOLETE PSW_DB = 3, */ +/* OBSOLETE PSW_DS = 4, */ +/* OBSOLETE PSW_IE = 5, */ +/* OBSOLETE PSW_RP = 6, */ +/* OBSOLETE PSW_MD = 7, */ +/* OBSOLETE PSW_F0 = 17, */ +/* OBSOLETE PSW_F1 = 19, */ +/* OBSOLETE PSW_F2 = 21, */ +/* OBSOLETE PSW_F3 = 23, */ +/* OBSOLETE PSW_S = 25, */ +/* OBSOLETE PSW_V = 27, */ +/* OBSOLETE PSW_VA = 29, */ +/* OBSOLETE PSW_C = 31, */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE /* aliases for PSW flag numbers (F0..F7) */ */ +/* OBSOLETE enum */ +/* OBSOLETE { */ +/* OBSOLETE PSW_S_FLAG = 4, */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE typedef struct _registers { */ +/* OBSOLETE unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS]; */ +/* OBSOLETE /* keep track of the stack pointer */ */ +/* OBSOLETE unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */ */ +/* OBSOLETE unsigned32 current_sp; */ +/* OBSOLETE unsigned32 control[NR_CONTROL_REGISTERS]; */ +/* OBSOLETE unsigned64 accumulator[NR_ACCUMULATORS]; */ +/* OBSOLETE } registers; */ +/* OBSOLETE */ +/* OBSOLETE typedef enum _cpu_units { */ +/* OBSOLETE memory_unit, */ +/* OBSOLETE integer_unit, */ +/* OBSOLETE any_unit, */ +/* OBSOLETE } cpu_units; */ +/* OBSOLETE */ +/* OBSOLETE /* In order to support parallel instructions, which one instruction can be */ +/* OBSOLETE writing to a register that is used as input to another, queue up the */ +/* OBSOLETE writes to the end of the instruction boundaries. */ */ +/* OBSOLETE */ +/* OBSOLETE #define MAX_WRITE32 16 */ +/* OBSOLETE #define MAX_WRITE64 2 */ +/* OBSOLETE */ +/* OBSOLETE struct _write32 { */ +/* OBSOLETE int num; /* # of 32-bit writes queued up */ */ +/* OBSOLETE unsigned32 value[MAX_WRITE32]; /* value to write */ */ +/* OBSOLETE unsigned32 mask[MAX_WRITE32]; /* mask to use */ */ +/* OBSOLETE unsigned32 *ptr[MAX_WRITE32]; /* address to write to */ */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE struct _write64 { */ +/* OBSOLETE int num; /* # of 64-bit writes queued up */ */ +/* OBSOLETE unsigned64 value[MAX_WRITE64]; /* value to write */ */ +/* OBSOLETE unsigned64 *ptr[MAX_WRITE64]; /* address to write to */ */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE struct _sim_cpu { */ +/* OBSOLETE cpu_units unit; */ +/* OBSOLETE registers regs; */ +/* OBSOLETE sim_cpu_base base; */ +/* OBSOLETE int trace_call_p; /* Whether to do call tracing. */ */ +/* OBSOLETE int trace_trap_p; /* If unknown traps dump out the regs */ */ +/* OBSOLETE int trace_action; /* trace bits at end of instructions */ */ +/* OBSOLETE int left_kills_right_p; /* left insn kills insn in right slot of -> */ */ +/* OBSOLETE int mvtsys_left_p; /* left insn was mvtsys */ */ +/* OBSOLETE int did_trap; /* we did a trap & need to finish it */ */ +/* OBSOLETE struct _write32 write32; /* queued up 32-bit writes */ */ +/* OBSOLETE struct _write64 write64; /* queued up 64-bit writes */ */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE #define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr]) */ +/* OBSOLETE #define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr]) */ +/* OBSOLETE #define PSWL (*AL2_4(&PSW)) */ +/* OBSOLETE #define PSWH (*AH2_4(&PSW)) */ +/* OBSOLETE #define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr]) */ +/* OBSOLETE #define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr]) */ +/* OBSOLETE #define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr]) */ +/* OBSOLETE #define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr]) */ +/* OBSOLETE #define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr]) */ +/* OBSOLETE #define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr]) */ +/* OBSOLETE #define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr]) */ +/* OBSOLETE #define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr]) */ +/* OBSOLETE #define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr]) */ +/* OBSOLETE #define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr]) */ +/* OBSOLETE #define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr]) */ +/* OBSOLETE #define GPR (STATE_CPU (sd, 0)->regs.general_purpose) */ +/* OBSOLETE #define GPR_CLEAR(N) (GPR[(N)] = 0) */ +/* OBSOLETE #define ACC (STATE_CPU (sd, 0)->regs.accumulator) */ +/* OBSOLETE #define CREG (STATE_CPU (sd, 0)->regs.control) */ +/* OBSOLETE #define SP (GPR[STACK_POINTER_GPR]) */ +/* OBSOLETE #define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p) */ +/* OBSOLETE #define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p) */ +/* OBSOLETE #define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action) */ +/* OBSOLETE #define TRACE_ACTION_CALL 0x00000001 /* call occurred */ */ +/* OBSOLETE #define TRACE_ACTION_RETURN 0x00000002 /* return occurred */ */ +/* OBSOLETE */ +/* OBSOLETE #define WRITE32 (STATE_CPU (sd, 0)->write32) */ +/* OBSOLETE #define WRITE32_NUM (WRITE32.num) */ +/* OBSOLETE #define WRITE32_PTR(N) (WRITE32.ptr[N]) */ +/* OBSOLETE #define WRITE32_MASK(N) (WRITE32.mask[N]) */ +/* OBSOLETE #define WRITE32_VALUE(N) (WRITE32.value[N]) */ +/* OBSOLETE #define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff) */ +/* OBSOLETE */ +/* OBSOLETE #define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \ */ +/* OBSOLETE do { \ */ +/* OBSOLETE int _num = WRITE32_NUM; \ */ +/* OBSOLETE if (_num >= MAX_WRITE32) \ */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */ +/* OBSOLETE "Too many queued 32-bit writes"); \ */ +/* OBSOLETE WRITE32_PTR(_num) = PTR; \ */ +/* OBSOLETE WRITE32_VALUE(_num) = VALUE; \ */ +/* OBSOLETE WRITE32_MASK(_num) = MASK; \ */ +/* OBSOLETE WRITE32_NUM = _num+1; \ */ +/* OBSOLETE } while (0) */ +/* OBSOLETE */ +/* OBSOLETE #define DID_TRAP (STATE_CPU (sd, 0)->did_trap) */ +/* OBSOLETE */ +/* OBSOLETE #define WRITE64 (STATE_CPU (sd, 0)->write64) */ +/* OBSOLETE #define WRITE64_NUM (WRITE64.num) */ +/* OBSOLETE #define WRITE64_PTR(N) (WRITE64.ptr[N]) */ +/* OBSOLETE #define WRITE64_VALUE(N) (WRITE64.value[N]) */ +/* OBSOLETE #define WRITE64_QUEUE(PTR, VALUE) \ */ +/* OBSOLETE do { \ */ +/* OBSOLETE int _num = WRITE64_NUM; \ */ +/* OBSOLETE if (_num >= MAX_WRITE64) \ */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */ +/* OBSOLETE "Too many queued 64-bit writes"); \ */ +/* OBSOLETE WRITE64_PTR(_num) = PTR; \ */ +/* OBSOLETE WRITE64_VALUE(_num) = VALUE; \ */ +/* OBSOLETE WRITE64_NUM = _num+1; \ */ +/* OBSOLETE } while (0) */ +/* OBSOLETE */ +/* OBSOLETE #define DPSW_VALID 0xbf005555 */ +/* OBSOLETE #define PSW_VALID 0xb7005555 */ +/* OBSOLETE #define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */ */ +/* OBSOLETE #define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */ */ +/* OBSOLETE */ +/* OBSOLETE /* Verify that the instruction is in the correct slot */ */ +/* OBSOLETE */ +/* OBSOLETE #define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX) */ +/* OBSOLETE extern int is_wrong_slot */ +/* OBSOLETE (SIM_DESC sd, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE itable_index index); */ +/* OBSOLETE */ +/* OBSOLETE #define IS_CONDITION_OK is_condition_ok(sd, cia, CCC) */ +/* OBSOLETE extern int is_condition_ok */ +/* OBSOLETE (SIM_DESC sd, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE int cond); */ +/* OBSOLETE */ +/* OBSOLETE #define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */ */ +/* OBSOLETE */ +/* OBSOLETE /* Internal breakpoint instruction is syscall 5 */ */ +/* OBSOLETE #define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05} */ +/* OBSOLETE #define SIM_BREAKPOINT_SIZE (4) */ +/* OBSOLETE */ +/* OBSOLETE /* Call occurred */ */ +/* OBSOLETE extern void call_occurred */ +/* OBSOLETE (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE address_word nia); */ +/* OBSOLETE */ +/* OBSOLETE /* Return occurred */ */ +/* OBSOLETE extern void return_occurred */ +/* OBSOLETE (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE address_word nia); */ +/* OBSOLETE */ +/* OBSOLETE /* Whether to do call tracing. */ */ +/* OBSOLETE extern int d30v_call_trace_p; */ +/* OBSOLETE */ +/* OBSOLETE /* Read/write functions for system call interface. */ */ +/* OBSOLETE extern int d30v_read_mem */ +/* OBSOLETE (host_callback *cb, */ +/* OBSOLETE struct cb_syscall *sc, */ +/* OBSOLETE unsigned long taddr, */ +/* OBSOLETE char *buf, */ +/* OBSOLETE int bytes); */ +/* OBSOLETE */ +/* OBSOLETE extern int d30v_write_mem */ +/* OBSOLETE (host_callback *cb, */ +/* OBSOLETE struct cb_syscall *sc, */ +/* OBSOLETE unsigned long taddr, */ +/* OBSOLETE const char *buf, */ +/* OBSOLETE int bytes); */ +/* OBSOLETE */ +/* OBSOLETE /* Process all of the queued up writes in order now */ */ +/* OBSOLETE void unqueue_writes */ +/* OBSOLETE (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia); */ +/* OBSOLETE */ +/* OBSOLETE #endif /* _CPU_H_ */ */ diff --git a/sim/d30v/d30v-insns b/sim/d30v/d30v-insns index 7b7c3c8..10ce868 100644 --- a/sim/d30v/d30v-insns +++ b/sim/d30v/d30v-insns @@ -1,2424 +1,2421 @@ -// -*- C -*- -// Mitsubishi Electric Corp. D30V Simulator. -// Copyright (C) 1997, Free Software Foundation, Inc. -// Contributed by Cygnus Solutions Inc. -// -// This file is part of GDB, the GNU debugger. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -// - - -define( _BRA, `1.*,CCC,000') -define( _LOGIC, `1.*,CCC,001') -define( _IMEM, `1.*,CCC,010') -define( _IALU1, `1.*,CCC,100') -define(_IALU2, `1.*,CCC,101') - - - -define(_IMM6, `6.IMM_6S') -define(_IMM12, `12.IMM_12S') -define(_IMM18, `18.IMM_18S') -define(_IMM32, `6.IMM_6L,*,000,8.IMM_8L,00,18.IMM_18L') - - - -// The following is called when ever an illegal instruction is -// encountered -::internal::illegal - sim_io_eprintf (sd, "illegal instruction at 0x%lx\n", (long) cia); - sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); - -// The following is called when ever an instruction in the wrong -// slot is encountered. -::internal::wrong_slot - sim_io_eprintf (sd, "wrong slot at 0x%lx\n", (long) cia); - sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); - - - -// Something illegal that can be used to contact the simulator emul -// library. -define(_EMUL, `1.*,CCC,111') - -void::function::do_emul:int imm - /* temp hack - later replace with real interface */ - enum { - param1 = 2, param2, param3, param4 - }; - switch (imm) { - case 0: - { - sim_engine_abort (SD, CPU, cia, "UNIX call emulation unsupported"); - break; - } - case 1: - /* Trap 1 - prints a string */ - { - address_word str = GPR[param1]; - char chr; - while (1) { - chr = MEM (unsigned, str, 1); - if (chr == '\0') break; - sim_io_write_stdout (sd, &chr, sizeof chr); - str++; - } - break; - } - case 3: - /* Trap 3 - writes a character */ - { - char chr = GPR[param1]; - sim_io_write_stdout (sd, &chr, sizeof chr); - break; - } - case 4: - /* Trap 4 exits with status in [param1] */ - { - sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR[param1]); - break; - } - case 5: - /* Trap 5 breakpoints. If the breakpoint system knows about this, it - won't return. Otherwise, we fall through to treat this as an - unknown instruction. */ - { - sim_handle_breakpoint (SD, CPU, cia); - /* Fall through to default case.*/ - } - default: - sim_engine_abort (SD, CPU, cia, "Unknown monitor call %d", imm); - } - -_EMUL,00000,00,6.*,6.*,IMM_6S:EMUL:short,emul:iu,mu:EMUL -"syscall " - do_emul (_SD, imm); -_BRA,00000,00,6.**,6.**,_IMM32:BRA:long:iu,mu:EMUL long -"syscall " - do_emul (_SD, imm); - -// ABS - -_IALU1,01000,00,6.RA,6.RB,6.**:IALU1:short:iu,mu:ABS -"abs r, r" - WRITE32_QUEUE (Ra, abs(Rb)); - - - -// ADD - -void::function::do_add:unsigned32 *ra, unsigned32 rb, unsigned32 imm - ALU_BEGIN(rb); - ALU_ADDC(imm); - ALU_END(ra); - -_IALU1,00000,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD -"add r, r, r" - do_add (_SD, Ra, Rb, Rc); -_IALU1,00000,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD imm -"add r, r, " - do_add (_SD, Ra, Rb, imm); -_IALU1,00000,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD imm long -"add r, r, " - do_add (_SD, Ra, Rb, imm); - - - -// ADD2H - -void::function::do_add2h:signed32 *ra, signed32 rb, signed32 imm - unsigned16 ah2 = VH2_4(rb) + VH2_4(imm); - unsigned16 al2 = VL2_4(rb) + VL2_4(imm); - WRITE32_QUEUE (ra, (ah2 << 16) | al2); - -_IALU1,00001,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD2H -"add2h r, r, r" - do_add2h (_SD, Ra, Rb, Rc); -_IALU1,00001,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD2H imm -"add2h r, r, " - do_add2h (_SD, Ra, Rb, immHL); -_IALU1,00001,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD2H imm long -"add2h r, r, " - do_add2h (_SD, Ra, Rb, imm); - - - -// ADDC - -void::function::do_addc:unsigned32 *ra, unsigned32 rb, unsigned32 imm - ALU_BEGIN(rb); - ALU_ADDC_C(imm, ALU_CARRY); - ALU_END(ra); - -_IALU1,00100,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDC -"addc r, r, r" - do_addc (_SD, Ra, Rb, Rc); -_IALU1,00100,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDC imm -"addc r, r, " - do_addc (_SD, Ra, Rb, imm); -_IALU1,00100,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDC imm long -"addc r, r, " - do_addc (_SD, Ra, Rb, imm); - - - -// ADDHppp - -void::function::do_addh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src - switch (ppp) { - case 0x0: /* LLL */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_ADDC(VL2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x1: /* LLH */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_ADDC(VH2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x2: /* LHL */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_ADDC(VL2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x3: /* LHH */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_ADDC(VH2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x4: /* HLL */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_ADDC(VL2_4(src)); - ALU16_END(ra, 1); - } - break; - case 0x5: /* HLH */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_ADDC(VH2_4(src)); - ALU16_END(ra, 1); - } - break; - case 0x6: /* HHL */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_ADDC(VL2_4(src)); - ALU16_END(ra, 1); - } - break; - case 0x7: /* HHH */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_ADDC(VH2_4(src)); - ALU16_END(ra, 1); - } - break; - default: - sim_engine_abort (SD, CPU, cia, "do_addh_ppp - internal error - bad switch"); - } -::%s::ppp:int ppp - switch (ppp) - { - case 0x0: return "lll"; - case 0x1: return "llh"; - case 0x2: return "lhl"; - case 0x3: return "lhh"; - case 0x4: return "hll"; - case 0x5: return "hlh"; - case 0x6: return "hhl"; - case 0x7: return "hhh"; - default: return "?"; - } - -_IALU1,10,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDHppp -"addh%s r, r, r" - do_addh_ppp(_SD, ppp, Ra, Rb, Rc); -_IALU1,10,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDHppp imm -"addh%s r, r, " - do_addh_ppp(_SD, ppp, Ra, Rb, immHL); -_IALU1,10,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDHppp imm long -"addh%s r, r, " - do_addh_ppp(_SD, ppp, Ra, Rb, imm); - - - -// ADDS - -void::function::do_adds:unsigned32 *ra, unsigned32 rb, unsigned32 imm - ALU_BEGIN(rb); - ALU_ADDC(EXTRACTED32(imm, 0, 0)); - ALU_END(ra); - -_IALU1,00110,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS -"adds r, r, r" - do_adds (_SD, Ra, Rb, Rc); -_IALU1,00110,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS imm -"adds r, r, " - do_adds (_SD, Ra, Rb, imm); -_IALU1,00110,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS imm long -"adds r, r, " - do_adds (_SD, Ra, Rb, imm); - - - -// ADDS2H - -void::function::do_adds2h:unsigned32 *ra, unsigned32 rb, unsigned32 immHL - unsigned16 high = VH2_4(rb) + EXTRACTED32(immHL, 0, 0); - unsigned16 low = VL2_4(rb) + EXTRACTED32(immHL, 16, 16); - WRITE32_QUEUE (ra, (high << 16) | low); - -_IALU1,00111,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS2H -"adds2h r, r, r" - do_adds2h (_SD, Ra, Rb, Rc); -_IALU1,00111,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS2H imm -"adds2h r, r, " - do_adds2h (_SD, Ra, Rb, immHL); -_IALU1,00111,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS2H imm long -"adds2h r, r, " - do_adds2h (_SD, Ra, Rb, imm); - - - -// AND - -_LOGIC,11000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:AND -"and r, r, r" - WRITE32_QUEUE (Ra, Rb & Rc); -_LOGIC,11000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:AND imm -"and r, r, " - WRITE32_QUEUE (Ra, Rb & imm); -_LOGIC,11000,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:AND imm long -"and r, r, " - WRITE32_QUEUE (Ra, Rb & imm); - - -// ANDFG - -_LOGIC,01000,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:Logical AND Flags -"andfg f, f, f" - PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & PSW_FLAG_VAL(FC)); -_LOGIC,01000,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:Logical AND Flags imm -"andfg f, f, " - PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & (imm_6 & 1)); - - - -// AVG - -void::function::do_avg:unsigned32 *ra, unsigned32 rb, unsigned32 imm - WRITE32_QUEUE (ra, ((signed64)(signed32)rb + (signed64)(signed32)imm + 1) >> 1); - -_IALU1,01010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG -"avg r, r, r" - do_avg (_SD, Ra, Rb, Rc); -_IALU1,01010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG imm -"avg r, r, " - do_avg (_SD, Ra, Rb, imm); -_IALU1,01010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG imm long -"avg r, r, " - do_avg (_SD, Ra, Rb, imm); - - - -// AVG2H - -void::function::do_avg2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm - unsigned16 high = ((signed32)(signed16)VH2_4(rb) + (signed32)(signed16)VH2_4(imm) + 1) >> 1; - unsigned16 low = ((signed32)(signed16)VL2_4(rb) + (signed32)(signed16)VL2_4(imm) + 1) >> 1; - WRITE32_QUEUE (ra, (high << 16) | low); - -_IALU1,01011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG2H -"avg2h r, r, r" - do_avg2h (_SD, Ra, Rb, Rc); -_IALU1,01011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG2H imm -"avg2h r, r, " - do_avg2h (_SD, Ra, Rb, immHL); -_IALU1,01011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG2H imm long -"avg2h r, r, " - do_avg2h (_SD, Ra, Rb, imm); - - - -// BCLR - -_LOGIC,00011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BCLR -"bclr r, r, r" - WRITE32_QUEUE(Ra, Rb & ~BIT32((Rc) % 32)); -_LOGIC,00011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BCLR imm -"bclr r, r, " - WRITE32_QUEUE(Ra, Rb & ~BIT32((imm) % 32)); - - - -// BNOT - -_LOGIC,00001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BNOT -"bnot r, r, r" - WRITE32_QUEUE (Ra, Rb ^ BIT32((Rc) % 32)); -_LOGIC,00001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BNOT imm -"bnot r, r, " - WRITE32_QUEUE (Ra, Rb ^ BIT32((imm) % 32)); - - - -// BRA - -_BRA,00000,00,6.**,6.**,6.RC:BRA:short:mu:BRA -"bra r" - nia = cia + pcdisp; -_BRA,00000,10,_IMM18:BRA:short:mu:BRA imm -"bra " - nia = cia + pcdisp; -_BRA,00000,10,6.**,6.**,_IMM32:BRA:long:mu:BRA imm long -"bra " - nia = cia + pcdisp; - - - -// BRATNZ - -_BRA,00100,01,6.RA,6.**,6.RC:BRA:short:mu:BRATNZ -"bratnz r" - if (*Ra != 0) - nia = cia + pcdisp; -_BRA,00100,11,6.RA,_IMM12:BRA:short:mu:BRATNZ imm -"bratnz " - if (*Ra != 0) - nia = cia + pcdisp; -_BRA,00100,11,6.RA,6.**,_IMM32:BRA:long:mu:BRATNZ imm long -"bratnz " - if (*Ra != 0) - nia = cia + pcdisp; - - - -// BRATZR - -_BRA,00100,00,6.RA,6.**,6.RC:BRA:short:mu:BRATZR -"bratzr r" - if (val_Ra == 0) - nia = cia + pcdisp; -_BRA,00100,10,6.RA,_IMM12:BRA:short:mu:BRATZR imm -"bratzr " - if (val_Ra == 0) - nia = cia + pcdisp; -_BRA,00100,10,6.RA,6.**,_IMM32:BRA:long:mu:BRATZR imm long -"bratzr " - if (val_Ra == 0) - nia = cia + pcdisp; - - - -// BSET - -_LOGIC,00010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BSET -"bset r, r, r" - WRITE32_QUEUE (Ra, Rb | BIT32((Rc) % 32)); -_LOGIC,00010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BSET imm -"bset r, r, " - WRITE32_QUEUE (Ra, Rb | BIT32((imm) % 32)); - - - -// BSR - -_BRA,00010,00,6.**,6.**,6.RC:BRA:short:mu:BSR -"bsr r" - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; -_BRA,00010,10,_IMM18:BRA:short:mu:BSR imm -"bsr " - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; -_BRA,00010,10,6.**,6.**,_IMM32:BRA:long:mu:BSR imm long -"bsr " - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - - -// BSRTNZ - -_BRA,00110,01,6.RA,6.**,6.RC:BRA:short:mu:BSRTNZ -"bsrtnz r" - if (val_Ra != 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - -_BRA,00110,11,6.RA,_IMM12:BRA:short:mu:BSRTNZ imm -"bsrtnz " - if (val_Ra != 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - -_BRA,00110,11,6.RA,6.**,_IMM32:BRA:long:mu:BSRTNZ imm long -"bsrtnz " - if (val_Ra != 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - - -// BSRTZR - -_BRA,00110,00,6.RA,6.**,6.RC:BRA:short:mu:BSRTZR -"bsrtzr r" - if (val_Ra == 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - -_BRA,00110,10,6.RA,_IMM12:BRA:short:mu:BSRTZR imm -"bsrtzr " - if (val_Ra == 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - -_BRA,00110,10,6.RA,6.**,_IMM32:BRA:long:mu:BSRTZR imm long -"bsrtzr " - if (val_Ra == 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = cia + pcdisp; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - - -// BTST - -_LOGIC,00000,00,***,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:BTST -"btst f, r, r" - int bit = (Rc) % 32; - PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit)); -_LOGIC,00000,10,***,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:BTST imm -"btst f, r, " - int bit = imm % 32; - PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit)); - - - -// CMPcc - -void::function::do_cmp_cc:int cc, int fa, signed32 rb, signed32 rc - int value = 0; - switch (cc) { - case 0: /* EQ */ - value = (rb == rc); - break; - case 1: /* NE */ - value = (rb != rc); - break; - case 2: /* GT */ - value = (rb > rc); - break; - case 3: /* GE */ - value = (rb >= rc); - break; - case 4: /* LT */ - value = (rb < rc); - break; - case 5: /* LE */ - value = (rb <= rc); - break; - case 6: /* PS */ - value = ((rb >= 0) && (rc >= 0)); - break; - case 7: /* NG */ - value = ((rb < 0) && (rc < 0)); - break; - default: - sim_engine_abort (SD, CPU, cia, "do_cmp_cc - internal error - bad switch (%d)", cc); - } - PSW_FLAG_SET_QUEUE(fa, value); - -::%s::ccc:int ccc - switch (ccc) - { - case 0: return "eq"; - case 1: return "ne"; - case 2: return "gt"; - case 3: return "ge"; - case 4: return "lt"; - case 5: return "le"; - case 6: return "ps"; - case 7: return "ng"; - default: return "?"; - } - -_LOGIC,01100,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPcc -"cmp%s f, r, r" - do_cmp_cc(_SD, ccc, FA, Rb, Rc); -_LOGIC,01100,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPcc imm -"cmp%s f, r, " - do_cmp_cc(_SD, ccc, FA, Rb, imm); -_LOGIC,01100,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPcc imm long -"cmp%s f, r, " - do_cmp_cc(_SD, ccc, FA, Rb, imm); - - - -// CMPUcc - -void::function::do_cmpu_cc:int cc, int fa, unsigned32 rb, unsigned32 rc - int value = 0; - switch (cc) { - case 2: /* GT */ - value = (rb > rc); - break; - case 3: /* GE */ - value = (rb >= rc); - break; - case 4: /* LT */ - value = (rb < rc); - break; - case 5: /* LE */ - value = (rb <= rc); - break; - default: - sim_engine_abort (SD, CPU, cia, "do_cmpu_cc - internal error - bad switch (%d)", cc); - } - PSW_FLAG_SET_QUEUE(fa, value); - -_LOGIC,01101,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPUcc -"cmpu%s f, r, r" - do_cmpu_cc(_SD, ccc, FA, Rb, Rc); -_LOGIC,01101,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPUcc imm -"cmpu%s f, r, " - do_cmpu_cc(_SD, ccc, FA, Rb, imm_6u); -_LOGIC,01101,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPUcc imm long -"cmpu%s f, r, " - do_cmpu_cc(_SD, ccc, FA, Rb, imm); - - - -// DBRA - -void::function::do_dbra:address_word pcdisp, unsigned32 ra - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, cia + pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7)); - -_BRA,10000,00,6.RA,6.**,6.RC:BRA:short:mu:DBRA -"dbra r, r" - do_dbra(_SD, pcdisp, val_Ra); -_BRA,10000,10,6.RA,_IMM12:BRA:short:mu:DBRA imm -"dbra r, " - do_dbra(_SD, pcdisp, val_Ra); -_BRA,10000,10,6.RA,6.**,_IMM32:BRA:long:mu:DBRA imm long -"dbra r, " - do_dbra(_SD, pcdisp, val_Ra); - - - -// DBRAI - -void::function::do_dbrai:address_word pcdisp, unsigned32 imm - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, cia + pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); - -_BRA,10100,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBRAI -"dbrai , r" - do_dbrai(_SD, pcdisp, IMM_6); -_BRA,10100,10,6.IMM_6,_IMM12:BRA:short:mu:DBRAI imm -"dbrai , " - do_dbrai(_SD, pcdisp, IMM_6); -_BRA,10100,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBRAI imm long -"dbrai , " - do_dbrai(_SD, pcdisp, IMM_6); - - - -// DBSR - -void::function::do_dbsr:address_word pcdisp, unsigned32 ra - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, cia + pcdisp); - WRITE32_QUEUE (&RPT_E, cia + ra); - WRITE32_QUEUE (&GPR[62], cia + ra + 8); - -_BRA,10010,00,6.RA,6.**,6.RC:BRA:short:mu:DBSR -"dbsr r, r" - do_dbsr(_SD, pcdisp, val_Ra); -_BRA,10010,10,6.RA,_IMM12:BRA:short:mu:DBSR imm -"dbsr r, " - do_dbsr(_SD, pcdisp, val_Ra); -_BRA,10010,10,6.RA,6.**,_IMM32:BRA:long:mu:DBSR imm long -"dbsr r, " - do_dbsr(_SD, pcdisp, val_Ra); - - - -// DBSRI - -void::function::do_dbsri:address_word pcdisp, unsigned32 imm - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, cia + pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); - WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8); - -_BRA,10110,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBSRI -"dbsri , r" - do_dbsri(_SD, pcdisp, IMM_6); -_BRA,10110,10,6.IMM_6,_IMM12:BRA:short:mu:DBSRI imm -"dbsri , " - do_dbsri(_SD, pcdisp, IMM_6); -_BRA,10110,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBSRI imm long -"dbsri , " - do_dbsri(_SD, pcdisp, IMM_6); - - - -// DBT - - -_BRA,01011,00,6.**,6.**,6.**:BRA:short:mu:DBT -"dbt" - if (cia == RPT_E && PSW_VAL (PSW_RP)) - { - WRITE32_QUEUE (&DPC, RPT_S); - if (RPT_C == 0) - PSW_SET (PSW_RP, 0); - } - else - WRITE32_QUEUE (&DPC, cia + 8); - DID_TRAP = 2; - nia = 0xfffff120; /* debug_trap_address */ - -// DJMP - -void::function::do_djmp:address_word pcdisp, unsigned32 ra - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7)); - -_BRA,10001,00,6.RA,6.**,6.RC:BRA:short:mu:DJMP -"djmp r, r" - do_djmp(_SD, pcdisp, val_Ra); -_BRA,10001,10,6.RA,_IMM12:BRA:short:mu:DJMP imm -"djmp r, " - do_djmp(_SD, pcdisp, val_Ra); -_BRA,10001,10,6.RA,6.**,_IMM32:BRA:long:mu:DJMP imm long -"djmp r, " - do_djmp(_SD, pcdisp, val_Ra); - - - -// DJMPI - -void::function::do_djmpi:address_word pcdisp, unsigned32 imm - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); - -_BRA,10101,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJMPI -"djmpi , r" - do_djmpi(_SD, pcdisp, IMM_6); -_BRA,10101,10,6.IMM_6,_IMM12:BRA:short:mu:DJMPI imm -"djmpi , " - do_djmpi(_SD, pcdisp, IMM_6); -_BRA,10101,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJMPI imm long -"djmpi , " - do_djmpi(_SD, pcdisp, IMM_6); - - - -// DJSR - -void::function::do_djsr:address_word pcdisp, unsigned32 ra - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7)); - WRITE32_QUEUE (&GPR[62], cia + (ra & ~0x7) + 8); - -_BRA,10011,00,6.RA,6.**,6.RC:BRA:short:mu:DJSR -"djsr r, r" - do_djsr(_SD, pcdisp, val_Ra); -_BRA,10011,10,6.RA,_IMM12:BRA:short:mu:DJSR imm -"djsr r, " - do_djsr(_SD, pcdisp, val_Ra); -_BRA,10011,10,6.RA,6.**,_IMM32:BRA:long:mu:DJSR imm long -"djsr r, " - do_djsr(_SD, pcdisp, val_Ra); - - - -// DJSRI - -void::function::do_djsri:address_word pcdisp, unsigned32 imm - PSW_SET_QUEUE (PSW_RP, 1); - WRITE32_QUEUE (&RPT_C, 1); - WRITE32_QUEUE (&RPT_S, pcdisp); - WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); - WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8); - -_BRA,10111,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJSRI -"djsri , r" - do_djsri(_SD, pcdisp, IMM_6); -_BRA,10111,10,6.IMM_6,_IMM12:BRA:short:mu:DJSRI imm -"djsri , " - do_djsri(_SD, pcdisp, IMM_6); -_BRA,10111,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJSRI imm long -"djsri , " - do_djsri(_SD, pcdisp, IMM_6); - - - -// JMP - -_BRA,00001,00,6.**,6.**,6.RC:BRA:short:mu:JMP -"jmp r" - nia = pcaddr; - if (RC == 62 && TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_RETURN; -_BRA,00001,10,_IMM18:BRA:short:mu:JMP imm -"jmp " - nia = pcaddr; -_BRA,00001,10,6.**,6.**,_IMM32:BRA:long:mu:JMP imm long -"jmp " - nia = pcaddr; - - - -// JMPTNZ - -_BRA,00101,01,6.RA,6.**,6.RC:BRA:short:mu:JMPTNZ -"jmptnz r" - if (val_Ra != 0) - nia = pcaddr; -_BRA,00101,11,6.RA,_IMM12:BRA:short:mu:JMPTNZ imm -"jmptnz " - if (val_Ra != 0) - nia = pcaddr; -_BRA,00101,11,6.RA,6.**,_IMM32:BRA:long:mu:JMPTNZ imm long -"jmptnz " - if (val_Ra != 0) - nia = pcaddr; - - - -// JMPTZR - -_BRA,00101,00,6.RA,6.**,6.RC:BRA:short:mu:JMPTZR -"jmptzr r" - if (val_Ra == 0) - nia = pcaddr; -_BRA,00101,10,6.RA,_IMM12:BRA:short:mu:JMPTZR imm -"jmptzr " - if (val_Ra == 0) - nia = pcaddr; -_BRA,00101,10,6.RA,6.**,_IMM32:BRA:long:mu:JMPTZR imm long -"jmptzr " - if (val_Ra == 0) - nia = pcaddr; - - - -// JOINpp - -void::function::do_join_pp:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src - switch (pp) { - case 0x0: /* LL */ - WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VL2_4(src)); - break; - case 0x1: /* LH */ - WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VH2_4(src)); - break; - case 0x2: /* HL */ - WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VL2_4(src)); - break; - case 0x3: /* HH */ - WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VH2_4(src)); - break; - } - -::%s::pp:int pp - switch (pp) - { - case 0x0: return "ll"; - case 0x1: return "lh"; - case 0x2: return "hl"; - case 0x3: return "hh"; - default: return "?"; - } - -_IALU1,011,pp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:JOINpp -"join%s r, r, r" - do_join_pp(_SD, pp, Ra, Rb, Rc); -_IALU1,011,pp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:JOINpp imm -"join%s r, r, " - do_join_pp(_SD, pp, Ra, Rb, immHL); -_IALU1,011,pp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:JOINpp imm long -"join%s r, r, " - do_join_pp(_SD, pp, Ra, Rb, immHL); - - - -// JSR - -_BRA,00011,00,6.**,6.**,6.RC:BRA:short:mu:JSR -"jsr r" - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - return pcaddr; -_BRA,00011,10,_IMM18:BRA:short:mu:JSR imm -"jsr " - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - return pcaddr; -_BRA,00011,10,6.**,6.**,_IMM32:BRA:long:mu:JSR imm long -"jsr " - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - return pcaddr; - - -// JSRTNZ - -_BRA,00111,01,6.RA,6.**,6.RC:BRA:short:mu:JSRTNZ -"jsrtnz r" - if (val_Ra != 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = pcaddr; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } -_BRA,00111,11,6.RA,_IMM12:BRA:short:mu:JSRTNZ imm -"jsrtnz " - if (val_Ra != 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = pcaddr; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } -_BRA,00111,11,6.RA,6.**,_IMM32:BRA:long:mu:JSRTNZ imm long -"jsrtnz " - if (val_Ra != 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = pcaddr; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - - - -// JSRTZR - -_BRA,00111,00,6.RA,6.**,6.RC:BRA:short:mu:JSRTZR -"jsrtzr r" - if (val_Ra == 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = pcaddr; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } -_BRA,00111,10,6.RA,_IMM12:BRA:short:mu:JSRTZR imm -"jsrtzr " - if (val_Ra == 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = pcaddr; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } -_BRA,00111,10,6.RA,6.**,_IMM32:BRA:long:mu:JSRTZR imm long -"jsrtzr " - if (val_Ra == 0) { - if (cia == RPT_E && PSW_VAL (PSW_RP)) - WRITE32_QUEUE (&GPR[62], RPT_S); - else - WRITE32_QUEUE (&GPR[62], cia + 8); - nia = pcaddr; - if (TRACE_CALL_P) - TRACE_ACTION |= TRACE_ACTION_CALL; - } - - - -// Post increment - -void::function::do_incr:int x, unsigned32 *rb, int delta - unsigned32 next_rb; - if (x == 1) - next_rb = *rb + delta; - else if (x == 3) - next_rb = *rb - delta; - else - next_rb = *rb; /* value not used */ - /* HW erratum: check value after incrementing */ - if (next_rb == MOD_E - && (x == 1 || x == 3) - && (PSW_VAL(PSW_MD))) { - WRITE32_QUEUE (rb, MOD_S); - } - else if (x == 1 || x == 3) - WRITE32_QUEUE (rb, next_rb); - -// LD2H - -int::function::make_even_reg:int reg, const char *name - if (reg & 1) - sim_engine_abort (SD, CPU, cia, - "0x%lx:%s odd register (r%d) used in multi-word load/mulx2h", - (long) cia, name, reg); - return reg; - -void::function::do_ld2h:int ra, unsigned32 rb, unsigned32 src - signed32 mem; - ra = make_even_reg(_SD, ra, "LD2H"); - mem = MEM(signed, rb + src, 4); - if (ra != 0) - { - WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16)); - WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16)); - } - -::%s::XX:int XX - switch (XX) - { - case 0: return ""; - case 1: return "+"; - case 3: return "-"; - default: return "?"; - } - -_IMEM,00011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD2H -"ld2h r, @(r, )":XX == 0 -"ld2h r, @(r%s, r)" - do_ld2h(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,00011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD2H long -"ld2h r, @(r, )" - do_ld2h(_SD, RA, Rb, imm); - - - -// LD2W - -void::function::do_ld2w:int ra, unsigned32 rb, unsigned32 src - unsigned64 mem; - ra = make_even_reg(_SD, ra, "LD2W"); - mem = MEM(unsigned, rb + src, 8); - if (ra != 0) - { - WRITE32_QUEUE (&GPR[ra + 0], EXTRACTED64 (mem, 0, 31)); - WRITE32_QUEUE (&GPR[ra + 1], EXTRACTED64 (mem, 32, 63)); - } - -_IMEM,00110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:L2W -"ld2w r, @(r, )":XX == 0 -"ld2w r, @(r%s, r)" - do_ld2w(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 8); -_IMEM,00110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:L2W long -"ld2w r, @(r, )" - do_ld2w(_SD, RA, Rb, imm); - - - -// LD4BH - -void::function::do_ld4bh:unsigned32 ra, unsigned32 rb, unsigned32 src - unsigned16 l1, l2, h1, h2; - unsigned32 mem; - ra = make_even_reg(_SD, ra, "LD4BH"); - mem = MEM(unsigned, rb + src, 4); - h1 = SEXT16(EXTRACTED32(mem, 0, 7), 8); - l1 = SEXT16(EXTRACTED32(mem, 8, 15), 8); - h2 = SEXT16(EXTRACTED32(mem, 16, 23), 8); - l2 = SEXT16(EXTRACTED32(mem, 24, 31), 8); - if (ra != 0) - { - WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1); - WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2); - } - -_IMEM,00101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BH -"ld4bh r, @(r, )":XX == 0 -"ld4bh r, @(r%s, r)" - do_ld4bh(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,00101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BH long -"ld4bh r, @(r, )" - do_ld4bh(_SD, RA, Rb, imm); - - - -// LD4BHU - -void::function::do_ld4bhu:unsigned32 ra, unsigned32 rb, unsigned32 src - unsigned16 l1, l2, h1, h2; - unsigned32 mem; - ra = make_even_reg(_SD, ra, "LD4BH"); - mem = MEM(signed, rb + src, 4); - h1 = EXTRACTED32(mem, 0, 7); - l1 = EXTRACTED32(mem, 8, 15); - h2 = EXTRACTED32(mem, 16, 23); - l2 = EXTRACTED32(mem, 24, 31); - if (ra != 0) - { - WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1); - WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2); - } - -_IMEM,01101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BHU -"ld4hbu r, @(r, )":XX == 0 -"ld4hbu r, @(r%s, r)" - do_ld4bhu(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,01101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BHU long -"ld4hbu r, @(r, )" - do_ld4bhu(_SD, RA, Rb, imm); - - - -// LDB - -void::function::do_ldb:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, MEM(signed, rb + src, 1)); - -_IMEM,00000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDB -"ldb r, @(r, )":XX == 0 -"ldb r, @(r%s, r)" - do_ldb(_SD, Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 1); -_IMEM,00000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDB long -"ldb r, @(r, )" - do_ldb(_SD, Ra, Rb, imm); - - - -// LDBU - -void::function::do_ldbu:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 1)); - -_IMEM,01001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDBU -"ldbu r, @(r, )":XX == 0 -"ldbu r, @(r%s, r)" - do_ldbu(_SD, Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 1); -_IMEM,01001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDBU long -"ldbu r, @(r, )" - do_ldbu(_SD, Ra, Rb, imm); - - - -// LDH - -void::function::do_ldh:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, MEM(signed, rb + src, 2)); - -_IMEM,00010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDH -"ldh r, @(r, )":XX == 0 -"ldh r, @(r%s, r)" - do_ldh(_SD, Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 2); -_IMEM,00010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDH long -"ldh r, @(r, )" - do_ldh(_SD, Ra, Rb, imm); - - - -// LDHH - -void::function::do_ldhh:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, MEM(signed, rb + src, 2) << 16); - -_IMEM,00001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHH -"ldhh r, @(r, )":XX == 0 -"ldhh r, @(r%s, r)" - do_ldhh(_SD, Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 2); -_IMEM,00001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHH long -"ldhh r, @(r, )" - do_ldhh(_SD, Ra, Rb, imm); - - - -// LDHU - -void::function::do_ldhu:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 2)); - -_IMEM,01010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHU -"ldhu r, @(r, )":XX == 0 -"ldhu r, @(r%s, r)" - do_ldhu(_SD, Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 2); -_IMEM,01010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHU long -"ldhu r, @(r, )" - do_ldhu(_SD, Ra, Rb, imm); - - - -// LDW - -void::function::do_ldw:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, MEM(signed, rb + src, 4)); - -_IMEM,00100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDW -"ldw r, @(r, )":XX == 0 -"ldw r, @(r%s, r)" - do_ldw(_SD, Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,00100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDW long -"ldw r, @(r, )" - do_ldw(_SD, Ra, Rb, imm); - - - -// MACa - -void::function::do_mac:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src - unsigned64 accum = *aa; - accum += (signed64) (rb) * (signed64) (src); - WRITE64_QUEUE (aa, accum); - WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63)); - -_IALU2,10100,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACa -"mac r, r, r" - do_mac(_SD, Aa, Ra, Rb, Rc); -_IALU2,10100,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACa imm -"mac r, r, " - do_mac(_SD, Aa, Ra, Rb, imm); - - - -// MACSa - -void::function::do_macs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src - unsigned64 accum = *aa; - accum += ((signed64) (rb) * (signed64) (src)) << 1; - WRITE64_QUEUE (aa, accum); - WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31)); - -_IALU2,10101,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACSa -"macs r, r, r" - do_macs(_SD, Aa, Ra, Rb, Rc); -_IALU2,10101,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACSa imm -"macs r, r, " - do_macs(_SD, Aa, Ra, Rb, imm); - - - -// MODDEC | MODINC - -_IMEM,00111,11,6.**,6.RB,_IMM6:IMEM:short:mu:MODDEC -"moddec r, " - do_incr(_SD, 3/*0b11*/, &GPR[RB], imm_5); -_IMEM,00111,01,6.**,6.RB,_IMM6:IMEM:short:mu:MODINC -"modinc r, " - do_incr(_SD, 1/*0b01*/, &GPR[RB], imm_5); - - - -// MSUBa - -void::function::do_msub:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src - unsigned64 accum = *aa; - accum -= (signed64) (rb) * (signed64) (src); - WRITE64_QUEUE (aa, accum); - WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63)); - -_IALU2,10110,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBa -"msub r, r, r" - do_msub(_SD, Aa, Ra, Rb, Rc); -_IALU2,10110,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBa imm -"msub r, r, " - do_msub(_SD, Aa, Ra, Rb, imm); - - - -// MSUBSa - -void::function::do_msubs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src - unsigned64 accum = *aa; - accum -= ((signed64) (rb) * (signed64) (src)) << 1; - WRITE64_QUEUE (aa, accum); - WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31)); - -_IALU2,10111,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBSa -"msubs r, r, r" - do_msubs(_SD, Aa, Ra, Rb, Rc); -_IALU2,10111,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBSa imm -"msubs r, r, " - do_msubs(_SD, Aa, Ra, Rb, imm); - - - -// MUL - -void::function::do_mul:unsigned32 *ra, unsigned32 rb, unsigned32 src - WRITE32_QUEUE (ra, rb * src); - -_IALU2,10000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL -"mul r, r, r" - do_mul(_SD, Ra, Rb, Rc); -_IALU2,10000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL imm -"mul r, r, " - do_mul(_SD, Ra, Rb, imm); - - - -// MUL2H - -void::function::do_mul2h:unsigned32 *ra, unsigned32 rb, unsigned32 src - unsigned16 high = VH2_4(rb) * VH2_4(src); - unsigned16 low = VL2_4(rb) * VL2_4(src); - WRITE32_QUEUE (ra, (high << 16) | low); - -_IALU2,00000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL2H -"mul2h r, r, r" - do_mul2h(_SD, Ra, Rb, Rc); -_IALU2,00000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL2H imm -"mul2h r, r, " - do_mul2h(_SD, Ra, Rb, immHL); - - - -// MULX - -void::function::do_mulx:unsigned64 *aa, signed32 rb, signed32 src - WRITE64_QUEUE (aa, (signed64) (rb) * (signed64) (src)); - -_IALU2,11000,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULX -"mulx a, r, r" - do_mulx(_SD, Aa, Rb, Rc); -_IALU2,11000,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULX imm -"mulx a, r, " - do_mulx(_SD, Aa, Rb, imm); - - -// MULX2H - -void::function::do_mulx2h:int ra, signed32 rb, signed32 src, int high - signed32 result = rb * src; - if (!high) - { - ra = make_even_reg(_SD, ra, "MULX2H"); - if (ra != 0) - WRITE32_QUEUE (&GPR[ra+1], result); - } - else if (ra != 0) - { - WRITE32_QUEUE (&GPR[ra+0], result); - } - -_IALU2,00001,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULX2H -"mul2h r, r, r" - do_mulx2h(_SD, RA, RbH, RcH, 1); - do_mulx2h(_SD, RA, RbL, RcL, 0); -_IALU2,00001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULX2H imm -"mul2h r, r, " - do_mulx2h(_SD, RA, RbH, imm, 1); - do_mulx2h(_SD, RA, RbL, imm, 0); - -// MULHXpp - -void::function::do_mulhx:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src - signed32 value = 0; - switch (pp) { - case 0: /* LL */ - value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16); - break; - case 1: /* LH */ - value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16); - break; - case 2: /* HL */ - value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16); - break; - case 3: /* HH */ - value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16); - break; - default: - sim_engine_abort (SD, CPU, cia, "do_mulhx - internal error - bad switch"); - } - WRITE32_QUEUE (ra, value); - -_IALU2,001,pp,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULHXpp -"mulhx%s r, r, r" - do_mulhx(_SD, pp, Ra, Rb, Rc); -_IALU2,001,pp,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULHXpp imm -"mulhx%s r, r, " - do_mulhx(_SD, pp, Ra, Rb, immHL); - - - -// MULXS - -void::function::do_mulxs:unsigned64 *aa, signed32 rb, signed32 src - WRITE64_QUEUE (aa, ((signed64) (rb) * (signed64) (src)) << 1); - -_IALU2,11001,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULXS -"mulxs a, r, r" - do_mulxs(_SD, Aa, Rb, Rc); -_IALU2,11001,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULXS imm -"mulxs a, r, " - do_mulxs(_SD, Aa, Rb, imm); - - - -// MVFACC - -void::function::do_mvfacc:unsigned32 *ra, unsigned64 ab, unsigned32 src - while (src > 63) src -= 64; - WRITE32_QUEUE (ra, ((signed64)ab) >> src); - -_IALU2,11111,00,6.RA,5.*,1.AB,6.RC:IALU2:short:iu:MVFACC -"mvfacc r, a, r" - do_mvfacc(_SD, Ra, *Ab, Rc); -_IALU2,11111,10,6.RA,5.*,1.AB,_IMM6:IALU2:short:iu:MVFACC imm -"mvfacc r, a, " - do_mvfacc(_SD, Ra, *Ab, imm_6u); - - - -// MVFSYS - -_BRA,11110,00,6.RA,6.CR,6.ID:BRA:short:mu:MVFSYS -"mvfsys r, cr" - switch (ID) { - case 0: - if (CR >= NR_CONTROL_REGISTERS) - sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR"); - else - WRITE32_QUEUE (Ra, (CPU)->regs.control[CR]); - break; - case 1: - WRITE32_QUEUE (Ra, PSWL); - break; - case 2: - WRITE32_QUEUE (Ra, EXTRACTED32(PSWH, 16, 31)); - break; - case 3: - WRITE32_QUEUE (Ra, PSW_FLAG_VAL(CR)); - break; - default: - sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID"); - } - - - -// MVTACC - -_IALU2,01111,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MVTACC -"mvtacc a, r, r" - WRITE64_QUEUE (Aa, INSERTED64(RbU, 0, 31) | (RcU)); - - - -// MVTSYS - -_BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS -"mvtsys cr, r" - switch (ID) { - case 0: /* control register */ - if (CR >= NR_CONTROL_REGISTERS) - sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR"); - else - { - unsigned32 value = Rb; - CPU->mvtsys_left_p = 1; - if (CR == processor_status_word_cr) - { - unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */ - value = ds | (value & PSW_VALID); - } - else if (CR == backup_processor_status_word_cr - || CR == debug_backup_processor_status_word_cr) - value &= DPSW_VALID; - else if (CR == eit_vector_base_cr) - value &= EIT_VALID; - WRITE32_QUEUE (&(CPU)->regs.control[CR], value); - } - break; - case 1: /* PSWL */ - WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31), - PSW_VALID & 0x0000ffff); - break; - case 2: /* PSWH */ - { - unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */ - WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds, - (PSW_VALID | ds) & 0xffff0000); - } - break; - case 3: /* FLAG */ - PSW_FLAG_SET_QUEUE(CR, Rb & 1); - break; - default: - sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID"); - } - - - -// NOP - -_BRA,01111,00,6.**,6.**,6.**:BRA:short:iu,mu:NOP -"nop" - /* NOP */; - - -// NOT - -_LOGIC,11001,00,6.RA,6.RB,6.*:LOGIC:short:iu,mu:NOT -"not r, r" - WRITE32_QUEUE (Ra, ~Rb); - - - -// NOTFG - -_LOGIC,01001,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:NOTFG -"notfg f, f" - PSW_FLAG_SET_QUEUE(FA, !PSW_FLAG_VAL(FB)); - - -// OR - -_LOGIC,11010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:OR -"or r, r, r" - WRITE32_QUEUE (Ra, Rb | Rc); -_LOGIC,11010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:OR imm -"or r, r, " - WRITE32_QUEUE (Ra, Rb | imm); -_LOGIC,11010,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:OR imm long -"or r, r, " - WRITE32_QUEUE (Ra, Rb | imm); - - - -// ORFG - -_LOGIC,01010,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:ORFG -"orfg f, f, f" - PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | PSW_FLAG_VAL(FC)); -_LOGIC,01010,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:ORFG imm -"orfg f, f, " - PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | (imm_6 & 1)); - - - -// REIT - -_BRA,01000,00,6.**,6.**,6.**:BRA:short:mu:REIT -"reit" - WRITE32_QUEUE (&PSW, bPSW); - nia = bPC; - - - - -// REPEAT - -void::function::do_repeat:unsigned32 count, address_word pcaddr - address_word rpt_s = cia + 8; - address_word rpt_e = cia + pcaddr; - - if (count == 0) - sim_engine_abort (SD, CPU, cia, "REPEAT with ra=0 and REPEATI with imm = 0 is forbidden."); - if (count > 1) - PSW_SET_QUEUE (PSW_RP, 1); - if (rpt_e < rpt_s + 0x10) - sim_io_eprintf (sd, "warning: 0x%lx: REPEAT or REPEATI loop is too small\n", (long) cia); - WRITE32_QUEUE (&RPT_C, count - 1); - WRITE32_QUEUE (&RPT_S, rpt_s); - WRITE32_QUEUE (&RPT_E, rpt_e); - -_BRA,11000,00,6.RA,6.**,6.RC:BRA:short:mu:REPEAT -"repeat r, r" - do_repeat(_SD, val_Ra, pcaddr); -_BRA,11000,10,6.RA,_IMM12:BRA:short:mu:REPEAT imm -"repeat r, " - do_repeat(_SD, val_Ra, pcaddr); -_BRA,11000,10,6.RA,6.**,_IMM32:BRA:long:mu:REPEAT imm long -"repeat r, " - do_repeat(_SD, val_Ra, pcaddr); - - - - -// REPEATI - -_BRA,11010,00,6.IMM_6,6.**,6.RC:BRA:short:mu:REPEATI -"repeati , r" - do_repeat(_SD, IMM_6, pcaddr); -_BRA,11010,10,6.IMM_6,_IMM12:BRA:short:mu:REPEATI imm -"repeati , " - do_repeat(_SD, IMM_6, pcaddr); -_BRA,11010,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:REPEATI imm long -"repeati , " - do_repeat(_SD, IMM_6, pcaddr); - - - - -// RTD - -_BRA,01010,00,6.*,6.*,6.*:BRA:short:mu:RTD -"rtd" - WRITE32_QUEUE (&PSW, DPSW); - nia = DPC; - - - - -// ROT - -_LOGIC,10100,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT -"rot r, r, r" - WRITE32_QUEUE (Ra, ROT32(Rb, Rc & 0x1f)); -_LOGIC,10100,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT imm -"rot r, r, " - WRITE32_QUEUE (Ra, ROT32(Rb, imm & 0x1f)); - - - - -// ROT2H - -void::function::do_rot2h:unsigned32 *ra, unsigned32 rb, signed32 src - unsigned16 high = ROTR16(VH2_4(rb), VH2_4(src) & 0xf); - unsigned16 low = ROTR16(VL2_4(rb), VL2_4(src) & 0xf); - WRITE32_QUEUE (ra, (high << 16) | low); - -_LOGIC,10101,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT2H -"rot2h r, r, r" - do_rot2h(_SD, Ra, Rb, Rc); -_LOGIC,10101,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT2H imm -"rot2h r, r, " - do_rot2h(_SD, Ra, Rb, immHL); - - - - -// SAT - -void::function::do_sat:signed32 *ra, signed32 rb, signed32 src - int bits = LSMASKED32(src, 4, 0); /* 5 */ - signed32 sat = LSMASK32(bits, 0) >> 2; - signed32 nsat = ~sat; - signed32 value; - if (bits != src) - sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia); - if (bits == 0) - value = rb; - else if (rb >= sat) - value = sat; - else if (rb <= nsat) - value = nsat; - else - value = rb; - WRITE32_QUEUE (ra, value); - -_IALU2,01000,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT -"sat r, r, r" - do_sat(_SD, Ra, Rb, Rc); -_IALU2,01000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT imm -"sat r, r, " - do_sat(_SD, Ra, Rb, imm_5); - - - - -// SAT2H - -void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int updates_f4 - int bits = LSMASKED32(src, 4, 0); /* 5 */ - signed32 sat = LSMASK32(bits, 0) >> 2; - signed32 nsat = ~sat; - signed32 value; - if (bits != src) - sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia); - if (bits == 0) - value = rb; - else if (rb >= sat) - value = sat; - else if (rb <= nsat) - value = nsat; - else - value = rb; - if (high) - WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); - else - WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); - if (updates_f4) - { - /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */ - if(STATE_CPU (sd, 0)->mvtsys_left_p) - unqueue_writes (sd, STATE_CPU (sd, 0), cia); - PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1)); - } - -_IALU2,01001,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT2H -"sat2h r, r, r" - do_sath(_SD, Ra, RbH, RcH, 1, 0); - do_sath(_SD, Ra, RbL, RcL, 0, 0); -_IALU2,01001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT2H imm -"sat2h r, r, " - do_sath(_SD, Ra, RbH, imm_5, 1, 0); - do_sath(_SD, Ra, RbL, imm_5, 0, 0); - - - - -// SATHp - -::%s::p:int p - switch (p) - { - case 0: return "l"; - case 1: return "h"; - default: return "?"; - } - -_IALU2,1110,p,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATHP -"sath%s

r, r, r" - do_sath(_SD, Ra, Rb, Rc, p, 1); -_IALU2,1110,p,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATHP imm -"sath%s

r, r, " - do_sath(_SD, Ra, Rb, imm_5, p, 1); - - - -// SATZ - -void::function::do_satz:signed32 *ra, signed32 rb, signed32 src - if (rb < 0) - WRITE32_QUEUE (ra, 0); - else - do_sat (_SD, ra, rb, src); - -_IALU2,01010,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ -"satz r, r, r" - do_satz(_SD, Ra, Rb, Rc); -_IALU2,01010,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ imm -"satz r, r, " - do_satz(_SD, Ra, Rb, imm_5); - - - - -// SATZ2H - -void::function::do_satzh:signed32 *ra, signed16 rb, signed32 src, int high - int bits = LSMASKED32(src, 3, 0); /*4*/ - signed16 sat = LSMASK16(bits, 0) >> 2; - signed16 nsat = 0; - signed16 value; - if (bits != src) - sim_io_eprintf (sd, "warning: 0x%lx:SATZ2H bit overflow\n", (long) cia); - if (bits == 0 && rb > sat) - value = rb; - else if (rb > sat) - value = sat; - else if (rb < nsat) - value = nsat; - else - value = rb; - if (high) - WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); - else - WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); - - -_IALU2,01011,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ2H -"satz2h r, r, r" - do_satzh(_SD, Ra, RbH, RcH, 1); - do_satzh(_SD, Ra, RbL, RcL, 0); -_IALU2,01011,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ2H imm -"satz2h r, r, " - do_satzh(_SD, Ra, RbH, imm, 1); - do_satzh(_SD, Ra, RbL, imm, 0); - - - - -// SRA - -void::function::do_sra:unsigned32 *ra, unsigned32 rb, signed32 src - unsigned32 value; - while (src > 31) src -= 32; - while (src < -32) src += 32; - if (src >= 0) - value = (signed32)rb >> src; - else if (src == -32) - value = 0; - else - value = rb << -src; - WRITE32_QUEUE (ra, value); - -_LOGIC,10000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA -"sra r, r, r" - do_sra(_SD, Ra, Rb, Rc); -_LOGIC,10000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA imm -"sra r, r, " - do_sra(_SD, Ra, Rb, imm); - - - - -// SRAHp - -void::function::do_srah:unsigned32 *ra, unsigned32 rb, int src, int high - unsigned32 value; - while (src > 31) src -= 32; - while (src < -32) src += 32; - if (src >= 0) - value = (signed32)rb >> src; - else if (src == -32) - value = 0; - else - value = rb << -src; - if (high) - WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); - else - WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); - -_LOGIC,0010,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRAHP -"srah%s

r, r, r" - do_srah(_SD, Ra, Rb, Rc, p); -_LOGIC,0010,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRAHP imm -"srah%s

r, r, " - do_srah(_SD, Ra, Rb, imm, p); - - - - -// SRA2H - -_LOGIC,10001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA2H -"sra2h r, r, r" - signed32 srcH = RcH; - signed32 srcL = RcL; - while (srcH > 15) srcH -= 16; - while (srcH < -16) srcH += 16; - while (srcL > 15) srcL -= 16; - while (srcL < -16) srcL += 16; - do_srah(_SD, Ra, RbH, srcH, 1); - do_srah(_SD, Ra, RbL, srcL, 0); -_LOGIC,10001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA2H imm -"sra2h r, r, " - signed32 src = imm; - while (src > 15) src -= 16; - while (src < -16) src += 16; - do_srah(_SD, Ra, RbH, src, 1); - do_srah(_SD, Ra, RbL, src, 0); - - - - -// SRC - -void::function::do_src:unsigned32 *ra, unsigned32 rb, int src - unsigned32 value; - unsigned64 operand; - unsigned64 shifted; - while (src > 31) src -= 32; - while (src < -32) src += 32; - if (src >= 0) - { - operand = (INSERTED64(rb, 0, 31) | INSERTED64(*ra, 32, 63)); - shifted = operand >> src; - value = EXTRACTED64(shifted, 32, 63); - } - else - { - operand = (INSERTED64(*ra, 0, 31) | INSERTED64(rb, 32, 63)); - shifted = operand << -src; - value = EXTRACTED64(shifted, 0, 31); - } - WRITE32_QUEUE (ra, value); - -_LOGIC,10110,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRC -"src r, r, r" - do_src(_SD, Ra, Rb, Rc); -_LOGIC,10110,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRC imm -"src r, r, " - do_src(_SD, Ra, Rb, imm); - - - - -// SRL - -void::function::do_srl:unsigned32 *ra, unsigned32 rb, int src - unsigned32 value; - while (src > 31) src -= 32; - while (src < -32) src += 32; - if (src >= 0) - value = (unsigned32)rb >> src; - else if (src == -32) - value = 0; - else - value = (unsigned32)rb << -src; - WRITE32_QUEUE (ra, value); - -_LOGIC,10010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL -"srl r, r, r" - do_srl(_SD, Ra, Rb, Rc); -_LOGIC,10010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL imm -"srl r, r, " - do_srl(_SD, Ra, Rb, imm); - - - - -// SRLHp - -void::function::do_srlh:unsigned32 *ra, unsigned32 rb, int src, int high - unsigned32 value; - while (src > 31) src -= 32; - while (src < -32) src += 32; - if (src >= 0) - value = rb >> src; - else if (src == -32) - value = 0; - else - value = rb << -src; - if (high) - WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); - else - WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); - -_LOGIC,0011,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRLHP -"srlh%s

r, r, r" - do_srlh(_SD, Ra, Rb, Rc, p); -_LOGIC,0011,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRLHP imm -"srlh%s

r, r, " - do_srlh(_SD, Ra, Rb, imm, p); - - -// SRL2H - -_LOGIC,10011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL2H -"srl2h r, r, r" - signed32 srcH = RcH; - signed32 srcL = RcL; - while (srcH > 15) srcH -= 16; - while (srcH < -16) srcH += 16; - while (srcL > 15) srcL -= 16; - while (srcL < -16) srcL += 16; - do_srlh(_SD, Ra, RbHU, srcH, 1); - do_srlh(_SD, Ra, RbLU, srcL, 0); -_LOGIC,10011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL2H imm -"srl2h r, r, " - signed32 src = imm; - while (src > 15) src -= 16; - while (src < -16) src += 16; - do_srlh(_SD, Ra, RbHU, src, 1); - do_srlh(_SD, Ra, RbLU, src, 0); - - - - -// ST2H - -void::function::get_even_reg:int *reg, unsigned32 *r0, const char *name - if (*reg & 1) - sim_engine_abort (SD, CPU, cia, - "0x%lx:%s odd register (r%d) used in multi-word store", - (long) cia, name, *reg); - if (*reg == 0) - *r0 = 0; - else - *r0 = GPR[*reg]; - -void::function::do_st2h:int ra, unsigned32 rb, unsigned32 src - unsigned32 val_ra; - unsigned32 mem; - get_even_reg(_SD, &ra, &val_ra, "ST2H"); - mem = INSERTED32(val_ra, 0, 15) | - INSERTED32(GPR[ra + 1], 16, 31); - STORE(rb + src, 4, mem); - -_IMEM,10011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2H -"st2h r, @(r, )":XX == 0 -"st2h r, @(r%s, r)" - do_st2h(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,10011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2H long -"st2h r, @(r, )" - do_st2h(_SD, RA, Rb, imm); - - - -// ST2W - -void::function::do_st2w:int ra, unsigned32 rb, unsigned32 src - unsigned32 val_ra; - unsigned64 mem; - get_even_reg(_SD, &ra, &val_ra, "ST2W"); - mem = INSERTED64(val_ra, 0, 31) | INSERTED64(GPR[ra + 1], 32, 63); - STORE(rb + src, 8, mem); - -_IMEM,10110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2W -"st2w r, @(r, )":XX == 0 -"st2w r, @(r%s, r)" - do_st2w(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 8); -_IMEM,10110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2W long -"st2w r, @(r, )" - do_st2w(_SD, RA, Rb, imm); - - - -// ST4HB - -void::function::do_st4hb:int ra, unsigned32 rb, unsigned32 src - unsigned32 val_ra; - unsigned32 mem; - get_even_reg(_SD, &ra, &val_ra, "ST4HB"); - mem = INSERTED32(EXTRACTED32(val_ra, 8, 15), 0, 7) | - INSERTED32(EXTRACTED32(val_ra, 24, 31), 8, 15) | - INSERTED32(EXTRACTED32(GPR[ra + 1], 8, 15), 16, 23) | - INSERTED32(EXTRACTED32(GPR[ra + 1], 24, 31), 24, 31); - STORE(rb + src, 4, mem); - -_IMEM,10101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST4HB -"st4hb r, @(r, )":XX == 0 -"st4hb r, @(r%s, r)" - do_st4hb(_SD, RA, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,10101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST4HB long -"st4hb r, @(r, )" - do_st4hb(_SD, RA, Rb, imm); - - - -// STB - -void::function::do_stb:unsigned32 ra, unsigned32 rb, unsigned32 src - STORE(rb + src, 1, EXTRACTED32(ra, 24, 31)); - -_IMEM,10000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STB -"stb r, @(r, )":XX == 0 -"stb r, @(r%s, r)" - do_stb(_SD, val_Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 1); -_IMEM,10000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STB long -"stb r, @(r, )" - do_stb(_SD, val_Ra, Rb, imm); - - - -// STH - -void::function::do_sth:unsigned32 ra, unsigned32 rb, unsigned32 src - STORE(rb + src, 2, EXTRACTED32(ra, 16, 31)); - -_IMEM,10010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STH -"sth r, @(r, )":XX == 0 -"sth r, @(r%s, r)" - do_sth(_SD, val_Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 2); -_IMEM,10010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STH long -"sth r, @(r, )" - do_sth(_SD, val_Ra, Rb, imm); - - - -// STHH - -void::function::do_sthh:unsigned32 ra, unsigned32 rb, unsigned32 src - STORE(rb + src, 2, EXTRACTED32(ra, 0, 15)); - -_IMEM,10001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STHH -"sthh r, @(r, )":XX == 0 -"sthh r, @(r%s, r)" - do_sthh(_SD, val_Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 2); -_IMEM,10001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STHH long -"sthh r, @(r, )" - do_sthh(_SD, val_Ra, Rb, imm); - - - -// STW - -void::function::do_stw:unsigned32 ra, unsigned32 rb, unsigned32 src - STORE(rb + src, 4, ra); - -_IMEM,10100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STW -"stw r, @(r, )":XX == 0 -"stw r, @(r%s, r)" - do_stw(_SD, val_Ra, Rb, src); - do_incr(_SD, XX, &GPR[RB], 4); -_IMEM,10100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STW long -"stw r, @(r, )" - do_stw(_SD, val_Ra, Rb, imm); - - - -// SUB - -void::function::do_sub:unsigned32 *ra, unsigned32 rb, unsigned32 imm - ALU_BEGIN(rb); - ALU_SUBB(imm); - ALU_END(ra); - -_IALU1,00010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB -"sub r, r, r" - do_sub (_SD, Ra, Rb, Rc); -_IALU1,00010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB imm -"sub r, r, " - do_sub (_SD, Ra, Rb, imm); -_IALU1,00010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB imm long -"sub r, r, " - do_sub (_SD, Ra, Rb, imm); - - - -// SUB2H - -void::function::do_sub2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm - unsigned16 high = VH2_4(rb) - VH2_4(imm); - unsigned16 low = VL2_4(rb) - VL2_4(imm); - WRITE32_QUEUE (ra, (high << 16) | low); - -_IALU1,00011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB2H -"sub2h r, r, r" - do_sub2h (_SD, Ra, Rb, Rc); -_IALU1,00011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB2H imm -"sub2h r, r, " - do_sub2h (_SD, Ra, Rb, immHL); -_IALU1,00011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB2H imm long -"sub2h r, r, " - do_sub2h (_SD, Ra, Rb, imm); - - - -// SUBB - -void::function::do_subb:unsigned32 *ra, unsigned32 rb, unsigned32 imm - ALU_BEGIN(rb); - ALU_SUBB_B(imm, ALU_CARRY); - ALU_END(ra); - -_IALU1,00101,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBB -"subb r, r, r" - do_subb (_SD, Ra, Rb, Rc); -_IALU1,00101,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBB imm -"subb r, r, " - do_subb (_SD, Ra, Rb, imm); -_IALU1,00101,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBB imm long -"subb r, r, " - do_subb (_SD, Ra, Rb, imm); - - - -// SUBHppp - -void::function::do_subh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src - switch (ppp) { - case 0x0: /* LLL */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_SUBB(VL2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x1: /* LLH */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_SUBB(VH2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x2: /* LHL */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_SUBB(VL2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x3: /* LHH */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_SUBB(VH2_4(src)); - ALU16_END(ra, 0); - } - break; - case 0x4: /* HLL */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_SUBB(VL2_4(src)); - ALU16_END(ra, 1); - } - break; - case 0x5: /* HLH */ - { - ALU16_BEGIN(VL2_4(rb)); - ALU16_SUBB(VH2_4(src)); - ALU16_END(ra, 1); - } - break; - case 0x6: /* HHL */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_SUBB(VL2_4(src)); - ALU16_END(ra, 1); - } - break; - case 0x7: /* HHH */ - { - ALU16_BEGIN(VH2_4(rb)); - ALU16_SUBB(VH2_4(src)); - ALU16_END(ra, 1); - } - break; - default: - sim_engine_abort (SD, CPU, cia, "do_subh_ppp - internal error - bad switch"); - } - -_IALU1,11,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBHppp -"subh%s r, r, r" - do_subh_ppp(_SD, ppp, Ra, Rb, Rc); -_IALU1,11,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBHppp imm -"subh%s r, r, " - do_subh_ppp(_SD, ppp, Ra, Rb, immHL); -_IALU1,11,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBHppp imm long -"subh%s r, r, " - do_subh_ppp(_SD, ppp, Ra, Rb, imm); - - - -// TRAP - -address_word::function::do_trap:address_word trap_vector, address_word nia - /* Steal trap 31 for doing system calls */ - /* System calls are defined in libgloss/d30v/syscall.h. */ - if (trap_vector == EIT_VB + 0x20 + (31 << 3)) - { - enum { PARM1 = 2, PARM2, PARM3, PARM4, FUNC }; - if (GPR[FUNC] == 1) /* exit */ - { - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, sim_exited, - GPR[PARM1]); - return -1; /* dummy */ - } - else - { - CB_SYSCALL syscall; - - CB_SYSCALL_INIT (&syscall); - syscall.arg1 = GPR[PARM1]; - syscall.arg2 = GPR[PARM2]; - syscall.arg3 = GPR[PARM3]; - syscall.arg4 = GPR[PARM4]; - syscall.func = GPR[FUNC]; - syscall.p1 = (PTR) SD; - syscall.read_mem = d30v_read_mem; - syscall.write_mem = d30v_write_mem; - - WRITE32_QUEUE (&GPR[PARM1], - ((cb_syscall (STATE_CALLBACK (SD), &syscall) - == CB_RC_OK) - ? syscall.result - : -syscall.errcode)); - return nia; - } - } - else if (TRACE_TRAP_P) - { - int reg, i; - sim_io_eprintf (sd, "\nTrap %ld:\n", (long) ((trap_vector - (EIT_VB + 0x20)) >> 3)); - for (reg = 0; reg < NR_GENERAL_PURPOSE_REGISTERS; reg += 8) - { - sim_io_eprintf (sd, "r%.2d - r%.2d: ", reg, reg+7); - for (i = 0; i < 8; i++) - sim_io_eprintf (sd, " 0x%.8lx", (long) GPR[reg+i]); - sim_io_eprintf (sd, "\n"); - } - - for (reg = 0; reg < 16; reg += 8) - { - sim_io_eprintf (sd, "cr%.2d - cr%.2d:", reg, reg+7); - for (i = 0; i < 8; i++) - sim_io_eprintf (sd, " 0x%.8lx", (long) CREG[reg+i]); - sim_io_eprintf (sd, "\n"); - } - - sim_io_eprintf (sd, "a0 - a1: "); - for (reg = 0; reg < NR_ACCUMULATORS; reg++) - sim_io_eprintf (sd, " 0x%.8lx 0x%.8lx", - (long)EXTRACTED64(ACC[reg], 0, 31), - (long)EXTRACTED64(ACC[reg], 32, 63)); - sim_io_eprintf (sd, "\n"); - - sim_io_eprintf (sd, "f0 - f7: "); - sim_io_eprintf (sd, " (f0) %d", (int) PSW_VAL(PSW_F0)); - sim_io_eprintf (sd, " (f1) %d", (int) PSW_VAL(PSW_F1)); - sim_io_eprintf (sd, " (f2) %d", (int) PSW_VAL(PSW_F2)); - sim_io_eprintf (sd, " (f3) %d", (int) PSW_VAL(PSW_F3)); - sim_io_eprintf (sd, " (s) %d", (int) PSW_VAL(PSW_S)); - sim_io_eprintf (sd, " (v) %d", (int) PSW_VAL(PSW_V)); - sim_io_eprintf (sd, " (va) %d", (int) PSW_VAL(PSW_VA)); - sim_io_eprintf (sd, " (c) %d\n", (int) PSW_VAL(PSW_C)); - - sim_io_eprintf (sd, "pswh: "); - sim_io_eprintf (sd, " (sm) %d", (int) PSW_VAL(PSW_SM)); - sim_io_eprintf (sd, " (ea) %d", (int) PSW_VAL(PSW_EA)); - sim_io_eprintf (sd, " (ie) %d", (int) PSW_VAL(PSW_IE)); - sim_io_eprintf (sd, " (rp) %d", (int) PSW_VAL(PSW_RP)); - sim_io_eprintf (sd, " (md) %d", (int) PSW_VAL(PSW_MD)); - - if (PSW_VAL(PSW_DB)) - sim_io_eprintf (sd, " (db) %d", (int) PSW_VAL(PSW_DB)); - - if (PSW_VAL(PSW_DS)) - sim_io_eprintf (sd, " (ds) %d", (int) PSW_VAL(PSW_DS)); - - sim_io_eprintf (sd, "\n"); - return nia; - } - else - { - if(PSW_VAL(PSW_RP) && RPT_E == cia) - { - WRITE32_QUEUE (&bPC, RPT_S); - if (RPT_C == 0) - PSW_SET (PSW_RP, 0); - } - else - WRITE32_QUEUE (&bPC, cia + 8); - DID_TRAP = 1; - return trap_vector; - } - -_BRA,01001,00,6.**,6.**,6.RC:BRA:short:mu:TRAP -"trap r" - nia = do_trap (_SD, EIT_VB + 0x20 + MASKED32(Rc, 24, 28), nia); -_BRA,01001,10,6.**,6.**,_IMM6:BRA:short:mu:TRAP imm -"trap " - nia = do_trap (_SD, EIT_VB + 0x20 + (imm_5 << 3), nia); - - - -// XOR - -_LOGIC,11011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:XOR -"xor r, r, r" - WRITE32_QUEUE (Ra, Rb ^ Rc); -_LOGIC,11011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:XOR imm -"xor r, r, " - WRITE32_QUEUE (Ra, Rb ^ imm); -_LOGIC,11011,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:XOR imm long -"xor r, r, " - WRITE32_QUEUE (Ra, Rb ^ imm); - - - -// XORFG - -_LOGIC,01011,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:XORFG -"xorfg f, f, f" - PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ PSW_FLAG_VAL(FC)); -_LOGIC,01011,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:XORFG imm -"xorfg f, f, " - PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ (imm_6 & 1)); - - - +# OBSOLETE // -*- C -*- +# OBSOLETE // Mitsubishi Electric Corp. D30V Simulator. +# OBSOLETE // Copyright (C) 1997, Free Software Foundation, Inc. +# OBSOLETE // Contributed by Cygnus Solutions Inc. +# OBSOLETE // +# OBSOLETE // This file is part of GDB, the GNU debugger. +# OBSOLETE // +# OBSOLETE // This program is free software; you can redistribute it and/or modify +# OBSOLETE // it under the terms of the GNU General Public License as published by +# OBSOLETE // the Free Software Foundation; either version 2 of the License, or +# OBSOLETE // (at your option) any later version. +# OBSOLETE // +# OBSOLETE // This program is distributed in the hope that it will be useful, +# OBSOLETE // but WITHOUT ANY WARRANTY; without even the implied warranty of +# OBSOLETE // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# OBSOLETE // GNU General Public License for more details. +# OBSOLETE // +# OBSOLETE // You should have received a copy of the GNU General Public License +# OBSOLETE // along with this program; if not, write to the Free Software +# OBSOLETE // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# OBSOLETE // +# OBSOLETE +# OBSOLETE +# OBSOLETE define( _BRA, `1.*,CCC,000') +# OBSOLETE define( _LOGIC, `1.*,CCC,001') +# OBSOLETE define( _IMEM, `1.*,CCC,010') +# OBSOLETE define( _IALU1, `1.*,CCC,100') +# OBSOLETE define(_IALU2, `1.*,CCC,101') +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE define(_IMM6, `6.IMM_6S') +# OBSOLETE define(_IMM12, `12.IMM_12S') +# OBSOLETE define(_IMM18, `18.IMM_18S') +# OBSOLETE define(_IMM32, `6.IMM_6L,*,000,8.IMM_8L,00,18.IMM_18L') +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // The following is called when ever an illegal instruction is +# OBSOLETE // encountered +# OBSOLETE ::internal::illegal +# OBSOLETE sim_io_eprintf (sd, "illegal instruction at 0x%lx\n", (long) cia); +# OBSOLETE sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); +# OBSOLETE +# OBSOLETE // The following is called when ever an instruction in the wrong +# OBSOLETE // slot is encountered. +# OBSOLETE ::internal::wrong_slot +# OBSOLETE sim_io_eprintf (sd, "wrong slot at 0x%lx\n", (long) cia); +# OBSOLETE sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // Something illegal that can be used to contact the simulator emul +# OBSOLETE // library. +# OBSOLETE define(_EMUL, `1.*,CCC,111') +# OBSOLETE +# OBSOLETE void::function::do_emul:int imm +# OBSOLETE /* temp hack - later replace with real interface */ +# OBSOLETE enum { +# OBSOLETE param1 = 2, param2, param3, param4 +# OBSOLETE }; +# OBSOLETE switch (imm) { +# OBSOLETE case 0: +# OBSOLETE { +# OBSOLETE sim_engine_abort (SD, CPU, cia, "UNIX call emulation unsupported"); +# OBSOLETE break; +# OBSOLETE } +# OBSOLETE case 1: +# OBSOLETE /* Trap 1 - prints a string */ +# OBSOLETE { +# OBSOLETE address_word str = GPR[param1]; +# OBSOLETE char chr; +# OBSOLETE while (1) { +# OBSOLETE chr = MEM (unsigned, str, 1); +# OBSOLETE if (chr == '\0') break; +# OBSOLETE sim_io_write_stdout (sd, &chr, sizeof chr); +# OBSOLETE str++; +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE } +# OBSOLETE case 3: +# OBSOLETE /* Trap 3 - writes a character */ +# OBSOLETE { +# OBSOLETE char chr = GPR[param1]; +# OBSOLETE sim_io_write_stdout (sd, &chr, sizeof chr); +# OBSOLETE break; +# OBSOLETE } +# OBSOLETE case 4: +# OBSOLETE /* Trap 4 exits with status in [param1] */ +# OBSOLETE { +# OBSOLETE sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR[param1]); +# OBSOLETE break; +# OBSOLETE } +# OBSOLETE case 5: +# OBSOLETE /* Trap 5 breakpoints. If the breakpoint system knows about this, it +# OBSOLETE won't return. Otherwise, we fall through to treat this as an +# OBSOLETE unknown instruction. */ +# OBSOLETE { +# OBSOLETE sim_handle_breakpoint (SD, CPU, cia); +# OBSOLETE /* Fall through to default case.*/ +# OBSOLETE } +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "Unknown monitor call %d", imm); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _EMUL,00000,00,6.*,6.*,IMM_6S:EMUL:short,emul:iu,mu:EMUL +# OBSOLETE "syscall " +# OBSOLETE do_emul (_SD, imm); +# OBSOLETE _BRA,00000,00,6.**,6.**,_IMM32:BRA:long:iu,mu:EMUL long +# OBSOLETE "syscall " +# OBSOLETE do_emul (_SD, imm); +# OBSOLETE +# OBSOLETE // ABS +# OBSOLETE +# OBSOLETE _IALU1,01000,00,6.RA,6.RB,6.**:IALU1:short:iu,mu:ABS +# OBSOLETE "abs r, r" +# OBSOLETE WRITE32_QUEUE (Ra, abs(Rb)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ADD +# OBSOLETE +# OBSOLETE void::function::do_add:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE ALU_BEGIN(rb); +# OBSOLETE ALU_ADDC(imm); +# OBSOLETE ALU_END(ra); +# OBSOLETE +# OBSOLETE _IALU1,00000,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD +# OBSOLETE "add r, r, r" +# OBSOLETE do_add (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00000,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD imm +# OBSOLETE "add r, r, " +# OBSOLETE do_add (_SD, Ra, Rb, imm); +# OBSOLETE _IALU1,00000,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD imm long +# OBSOLETE "add r, r, " +# OBSOLETE do_add (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ADD2H +# OBSOLETE +# OBSOLETE void::function::do_add2h:signed32 *ra, signed32 rb, signed32 imm +# OBSOLETE unsigned16 ah2 = VH2_4(rb) + VH2_4(imm); +# OBSOLETE unsigned16 al2 = VL2_4(rb) + VL2_4(imm); +# OBSOLETE WRITE32_QUEUE (ra, (ah2 << 16) | al2); +# OBSOLETE +# OBSOLETE _IALU1,00001,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADD2H +# OBSOLETE "add2h r, r, r" +# OBSOLETE do_add2h (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00001,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADD2H imm +# OBSOLETE "add2h r, r, " +# OBSOLETE do_add2h (_SD, Ra, Rb, immHL); +# OBSOLETE _IALU1,00001,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADD2H imm long +# OBSOLETE "add2h r, r, " +# OBSOLETE do_add2h (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ADDC +# OBSOLETE +# OBSOLETE void::function::do_addc:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE ALU_BEGIN(rb); +# OBSOLETE ALU_ADDC_C(imm, ALU_CARRY); +# OBSOLETE ALU_END(ra); +# OBSOLETE +# OBSOLETE _IALU1,00100,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDC +# OBSOLETE "addc r, r, r" +# OBSOLETE do_addc (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00100,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDC imm +# OBSOLETE "addc r, r, " +# OBSOLETE do_addc (_SD, Ra, Rb, imm); +# OBSOLETE _IALU1,00100,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDC imm long +# OBSOLETE "addc r, r, " +# OBSOLETE do_addc (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ADDHppp +# OBSOLETE +# OBSOLETE void::function::do_addh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE switch (ppp) { +# OBSOLETE case 0x0: /* LLL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_ADDC(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x1: /* LLH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_ADDC(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x2: /* LHL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_ADDC(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x3: /* LHH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_ADDC(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x4: /* HLL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_ADDC(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x5: /* HLH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_ADDC(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x6: /* HHL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_ADDC(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x7: /* HHH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_ADDC(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "do_addh_ppp - internal error - bad switch"); +# OBSOLETE } +# OBSOLETE ::%s::ppp:int ppp +# OBSOLETE switch (ppp) +# OBSOLETE { +# OBSOLETE case 0x0: return "lll"; +# OBSOLETE case 0x1: return "llh"; +# OBSOLETE case 0x2: return "lhl"; +# OBSOLETE case 0x3: return "lhh"; +# OBSOLETE case 0x4: return "hll"; +# OBSOLETE case 0x5: return "hlh"; +# OBSOLETE case 0x6: return "hhl"; +# OBSOLETE case 0x7: return "hhh"; +# OBSOLETE default: return "?"; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IALU1,10,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDHppp +# OBSOLETE "addh%s r, r, r" +# OBSOLETE do_addh_ppp(_SD, ppp, Ra, Rb, Rc); +# OBSOLETE _IALU1,10,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDHppp imm +# OBSOLETE "addh%s r, r, " +# OBSOLETE do_addh_ppp(_SD, ppp, Ra, Rb, immHL); +# OBSOLETE _IALU1,10,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDHppp imm long +# OBSOLETE "addh%s r, r, " +# OBSOLETE do_addh_ppp(_SD, ppp, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ADDS +# OBSOLETE +# OBSOLETE void::function::do_adds:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE ALU_BEGIN(rb); +# OBSOLETE ALU_ADDC(EXTRACTED32(imm, 0, 0)); +# OBSOLETE ALU_END(ra); +# OBSOLETE +# OBSOLETE _IALU1,00110,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS +# OBSOLETE "adds r, r, r" +# OBSOLETE do_adds (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00110,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS imm +# OBSOLETE "adds r, r, " +# OBSOLETE do_adds (_SD, Ra, Rb, imm); +# OBSOLETE _IALU1,00110,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS imm long +# OBSOLETE "adds r, r, " +# OBSOLETE do_adds (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ADDS2H +# OBSOLETE +# OBSOLETE void::function::do_adds2h:unsigned32 *ra, unsigned32 rb, unsigned32 immHL +# OBSOLETE unsigned16 high = VH2_4(rb) + EXTRACTED32(immHL, 0, 0); +# OBSOLETE unsigned16 low = VL2_4(rb) + EXTRACTED32(immHL, 16, 16); +# OBSOLETE WRITE32_QUEUE (ra, (high << 16) | low); +# OBSOLETE +# OBSOLETE _IALU1,00111,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:ADDS2H +# OBSOLETE "adds2h r, r, r" +# OBSOLETE do_adds2h (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00111,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:ADDS2H imm +# OBSOLETE "adds2h r, r, " +# OBSOLETE do_adds2h (_SD, Ra, Rb, immHL); +# OBSOLETE _IALU1,00111,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:ADDS2H imm long +# OBSOLETE "adds2h r, r, " +# OBSOLETE do_adds2h (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // AND +# OBSOLETE +# OBSOLETE _LOGIC,11000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:AND +# OBSOLETE "and r, r, r" +# OBSOLETE WRITE32_QUEUE (Ra, Rb & Rc); +# OBSOLETE _LOGIC,11000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:AND imm +# OBSOLETE "and r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb & imm); +# OBSOLETE _LOGIC,11000,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:AND imm long +# OBSOLETE "and r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb & imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE // ANDFG +# OBSOLETE +# OBSOLETE _LOGIC,01000,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:Logical AND Flags +# OBSOLETE "andfg f, f, f" +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & PSW_FLAG_VAL(FC)); +# OBSOLETE _LOGIC,01000,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:Logical AND Flags imm +# OBSOLETE "andfg f, f, " +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) & (imm_6 & 1)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // AVG +# OBSOLETE +# OBSOLETE void::function::do_avg:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE WRITE32_QUEUE (ra, ((signed64)(signed32)rb + (signed64)(signed32)imm + 1) >> 1); +# OBSOLETE +# OBSOLETE _IALU1,01010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG +# OBSOLETE "avg r, r, r" +# OBSOLETE do_avg (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,01010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG imm +# OBSOLETE "avg r, r, " +# OBSOLETE do_avg (_SD, Ra, Rb, imm); +# OBSOLETE _IALU1,01010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG imm long +# OBSOLETE "avg r, r, " +# OBSOLETE do_avg (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // AVG2H +# OBSOLETE +# OBSOLETE void::function::do_avg2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE unsigned16 high = ((signed32)(signed16)VH2_4(rb) + (signed32)(signed16)VH2_4(imm) + 1) >> 1; +# OBSOLETE unsigned16 low = ((signed32)(signed16)VL2_4(rb) + (signed32)(signed16)VL2_4(imm) + 1) >> 1; +# OBSOLETE WRITE32_QUEUE (ra, (high << 16) | low); +# OBSOLETE +# OBSOLETE _IALU1,01011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:AVG2H +# OBSOLETE "avg2h r, r, r" +# OBSOLETE do_avg2h (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,01011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:AVG2H imm +# OBSOLETE "avg2h r, r, " +# OBSOLETE do_avg2h (_SD, Ra, Rb, immHL); +# OBSOLETE _IALU1,01011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:AVG2H imm long +# OBSOLETE "avg2h r, r, " +# OBSOLETE do_avg2h (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BCLR +# OBSOLETE +# OBSOLETE _LOGIC,00011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BCLR +# OBSOLETE "bclr r, r, r" +# OBSOLETE WRITE32_QUEUE(Ra, Rb & ~BIT32((Rc) % 32)); +# OBSOLETE _LOGIC,00011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BCLR imm +# OBSOLETE "bclr r, r, " +# OBSOLETE WRITE32_QUEUE(Ra, Rb & ~BIT32((imm) % 32)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BNOT +# OBSOLETE +# OBSOLETE _LOGIC,00001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BNOT +# OBSOLETE "bnot r, r, r" +# OBSOLETE WRITE32_QUEUE (Ra, Rb ^ BIT32((Rc) % 32)); +# OBSOLETE _LOGIC,00001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BNOT imm +# OBSOLETE "bnot r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb ^ BIT32((imm) % 32)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BRA +# OBSOLETE +# OBSOLETE _BRA,00000,00,6.**,6.**,6.RC:BRA:short:mu:BRA +# OBSOLETE "bra r" +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE _BRA,00000,10,_IMM18:BRA:short:mu:BRA imm +# OBSOLETE "bra " +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE _BRA,00000,10,6.**,6.**,_IMM32:BRA:long:mu:BRA imm long +# OBSOLETE "bra " +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BRATNZ +# OBSOLETE +# OBSOLETE _BRA,00100,01,6.RA,6.**,6.RC:BRA:short:mu:BRATNZ +# OBSOLETE "bratnz r" +# OBSOLETE if (*Ra != 0) +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE _BRA,00100,11,6.RA,_IMM12:BRA:short:mu:BRATNZ imm +# OBSOLETE "bratnz " +# OBSOLETE if (*Ra != 0) +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE _BRA,00100,11,6.RA,6.**,_IMM32:BRA:long:mu:BRATNZ imm long +# OBSOLETE "bratnz " +# OBSOLETE if (*Ra != 0) +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BRATZR +# OBSOLETE +# OBSOLETE _BRA,00100,00,6.RA,6.**,6.RC:BRA:short:mu:BRATZR +# OBSOLETE "bratzr r" +# OBSOLETE if (val_Ra == 0) +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE _BRA,00100,10,6.RA,_IMM12:BRA:short:mu:BRATZR imm +# OBSOLETE "bratzr " +# OBSOLETE if (val_Ra == 0) +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE _BRA,00100,10,6.RA,6.**,_IMM32:BRA:long:mu:BRATZR imm long +# OBSOLETE "bratzr " +# OBSOLETE if (val_Ra == 0) +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BSET +# OBSOLETE +# OBSOLETE _LOGIC,00010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:BSET +# OBSOLETE "bset r, r, r" +# OBSOLETE WRITE32_QUEUE (Ra, Rb | BIT32((Rc) % 32)); +# OBSOLETE _LOGIC,00010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:BSET imm +# OBSOLETE "bset r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb | BIT32((imm) % 32)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // BSR +# OBSOLETE +# OBSOLETE _BRA,00010,00,6.**,6.**,6.RC:BRA:short:mu:BSR +# OBSOLETE "bsr r" +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE _BRA,00010,10,_IMM18:BRA:short:mu:BSR imm +# OBSOLETE "bsr " +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE _BRA,00010,10,6.**,6.**,_IMM32:BRA:long:mu:BSR imm long +# OBSOLETE "bsr " +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE +# OBSOLETE +# OBSOLETE // BSRTNZ +# OBSOLETE +# OBSOLETE _BRA,00110,01,6.RA,6.**,6.RC:BRA:short:mu:BSRTNZ +# OBSOLETE "bsrtnz r" +# OBSOLETE if (val_Ra != 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _BRA,00110,11,6.RA,_IMM12:BRA:short:mu:BSRTNZ imm +# OBSOLETE "bsrtnz " +# OBSOLETE if (val_Ra != 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _BRA,00110,11,6.RA,6.**,_IMM32:BRA:long:mu:BSRTNZ imm long +# OBSOLETE "bsrtnz " +# OBSOLETE if (val_Ra != 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE +# OBSOLETE // BSRTZR +# OBSOLETE +# OBSOLETE _BRA,00110,00,6.RA,6.**,6.RC:BRA:short:mu:BSRTZR +# OBSOLETE "bsrtzr r" +# OBSOLETE if (val_Ra == 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _BRA,00110,10,6.RA,_IMM12:BRA:short:mu:BSRTZR imm +# OBSOLETE "bsrtzr " +# OBSOLETE if (val_Ra == 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _BRA,00110,10,6.RA,6.**,_IMM32:BRA:long:mu:BSRTZR imm long +# OBSOLETE "bsrtzr " +# OBSOLETE if (val_Ra == 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = cia + pcdisp; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE +# OBSOLETE // BTST +# OBSOLETE +# OBSOLETE _LOGIC,00000,00,***,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:BTST +# OBSOLETE "btst f, r, r" +# OBSOLETE int bit = (Rc) % 32; +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit)); +# OBSOLETE _LOGIC,00000,10,***,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:BTST imm +# OBSOLETE "btst f, r, " +# OBSOLETE int bit = imm % 32; +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, MASKED32(Rb, bit, bit)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // CMPcc +# OBSOLETE +# OBSOLETE void::function::do_cmp_cc:int cc, int fa, signed32 rb, signed32 rc +# OBSOLETE int value = 0; +# OBSOLETE switch (cc) { +# OBSOLETE case 0: /* EQ */ +# OBSOLETE value = (rb == rc); +# OBSOLETE break; +# OBSOLETE case 1: /* NE */ +# OBSOLETE value = (rb != rc); +# OBSOLETE break; +# OBSOLETE case 2: /* GT */ +# OBSOLETE value = (rb > rc); +# OBSOLETE break; +# OBSOLETE case 3: /* GE */ +# OBSOLETE value = (rb >= rc); +# OBSOLETE break; +# OBSOLETE case 4: /* LT */ +# OBSOLETE value = (rb < rc); +# OBSOLETE break; +# OBSOLETE case 5: /* LE */ +# OBSOLETE value = (rb <= rc); +# OBSOLETE break; +# OBSOLETE case 6: /* PS */ +# OBSOLETE value = ((rb >= 0) && (rc >= 0)); +# OBSOLETE break; +# OBSOLETE case 7: /* NG */ +# OBSOLETE value = ((rb < 0) && (rc < 0)); +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "do_cmp_cc - internal error - bad switch (%d)", cc); +# OBSOLETE } +# OBSOLETE PSW_FLAG_SET_QUEUE(fa, value); +# OBSOLETE +# OBSOLETE ::%s::ccc:int ccc +# OBSOLETE switch (ccc) +# OBSOLETE { +# OBSOLETE case 0: return "eq"; +# OBSOLETE case 1: return "ne"; +# OBSOLETE case 2: return "gt"; +# OBSOLETE case 3: return "ge"; +# OBSOLETE case 4: return "lt"; +# OBSOLETE case 5: return "le"; +# OBSOLETE case 6: return "ps"; +# OBSOLETE case 7: return "ng"; +# OBSOLETE default: return "?"; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _LOGIC,01100,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPcc +# OBSOLETE "cmp%s f, r, r" +# OBSOLETE do_cmp_cc(_SD, ccc, FA, Rb, Rc); +# OBSOLETE _LOGIC,01100,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPcc imm +# OBSOLETE "cmp%s f, r, " +# OBSOLETE do_cmp_cc(_SD, ccc, FA, Rb, imm); +# OBSOLETE _LOGIC,01100,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPcc imm long +# OBSOLETE "cmp%s f, r, " +# OBSOLETE do_cmp_cc(_SD, ccc, FA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // CMPUcc +# OBSOLETE +# OBSOLETE void::function::do_cmpu_cc:int cc, int fa, unsigned32 rb, unsigned32 rc +# OBSOLETE int value = 0; +# OBSOLETE switch (cc) { +# OBSOLETE case 2: /* GT */ +# OBSOLETE value = (rb > rc); +# OBSOLETE break; +# OBSOLETE case 3: /* GE */ +# OBSOLETE value = (rb >= rc); +# OBSOLETE break; +# OBSOLETE case 4: /* LT */ +# OBSOLETE value = (rb < rc); +# OBSOLETE break; +# OBSOLETE case 5: /* LE */ +# OBSOLETE value = (rb <= rc); +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "do_cmpu_cc - internal error - bad switch (%d)", cc); +# OBSOLETE } +# OBSOLETE PSW_FLAG_SET_QUEUE(fa, value); +# OBSOLETE +# OBSOLETE _LOGIC,01101,00,ccc,3.FA,6.RB,6.RC:LOGIC:short:iu,mu:CMPUcc +# OBSOLETE "cmpu%s f, r, r" +# OBSOLETE do_cmpu_cc(_SD, ccc, FA, Rb, Rc); +# OBSOLETE _LOGIC,01101,10,ccc,3.FA,6.RB,_IMM6:LOGIC:short:iu,mu:CMPUcc imm +# OBSOLETE "cmpu%s f, r, " +# OBSOLETE do_cmpu_cc(_SD, ccc, FA, Rb, imm_6u); +# OBSOLETE _LOGIC,01101,10,ccc,3.FA,6.RB,_IMM32:LOGIC:long:iu,mu:CMPUcc imm long +# OBSOLETE "cmpu%s f, r, " +# OBSOLETE do_cmpu_cc(_SD, ccc, FA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DBRA +# OBSOLETE +# OBSOLETE void::function::do_dbra:address_word pcdisp, unsigned32 ra +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, cia + pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7)); +# OBSOLETE +# OBSOLETE _BRA,10000,00,6.RA,6.**,6.RC:BRA:short:mu:DBRA +# OBSOLETE "dbra r, r" +# OBSOLETE do_dbra(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10000,10,6.RA,_IMM12:BRA:short:mu:DBRA imm +# OBSOLETE "dbra r, " +# OBSOLETE do_dbra(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10000,10,6.RA,6.**,_IMM32:BRA:long:mu:DBRA imm long +# OBSOLETE "dbra r, " +# OBSOLETE do_dbra(_SD, pcdisp, val_Ra); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DBRAI +# OBSOLETE +# OBSOLETE void::function::do_dbrai:address_word pcdisp, unsigned32 imm +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, cia + pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); +# OBSOLETE +# OBSOLETE _BRA,10100,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBRAI +# OBSOLETE "dbrai , r" +# OBSOLETE do_dbrai(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10100,10,6.IMM_6,_IMM12:BRA:short:mu:DBRAI imm +# OBSOLETE "dbrai , " +# OBSOLETE do_dbrai(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10100,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBRAI imm long +# OBSOLETE "dbrai , " +# OBSOLETE do_dbrai(_SD, pcdisp, IMM_6); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DBSR +# OBSOLETE +# OBSOLETE void::function::do_dbsr:address_word pcdisp, unsigned32 ra +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, cia + pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + ra); +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + ra + 8); +# OBSOLETE +# OBSOLETE _BRA,10010,00,6.RA,6.**,6.RC:BRA:short:mu:DBSR +# OBSOLETE "dbsr r, r" +# OBSOLETE do_dbsr(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10010,10,6.RA,_IMM12:BRA:short:mu:DBSR imm +# OBSOLETE "dbsr r, " +# OBSOLETE do_dbsr(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10010,10,6.RA,6.**,_IMM32:BRA:long:mu:DBSR imm long +# OBSOLETE "dbsr r, " +# OBSOLETE do_dbsr(_SD, pcdisp, val_Ra); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DBSRI +# OBSOLETE +# OBSOLETE void::function::do_dbsri:address_word pcdisp, unsigned32 imm +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, cia + pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8); +# OBSOLETE +# OBSOLETE _BRA,10110,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DBSRI +# OBSOLETE "dbsri , r" +# OBSOLETE do_dbsri(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10110,10,6.IMM_6,_IMM12:BRA:short:mu:DBSRI imm +# OBSOLETE "dbsri , " +# OBSOLETE do_dbsri(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10110,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DBSRI imm long +# OBSOLETE "dbsri , " +# OBSOLETE do_dbsri(_SD, pcdisp, IMM_6); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DBT +# OBSOLETE +# OBSOLETE +# OBSOLETE _BRA,01011,00,6.**,6.**,6.**:BRA:short:mu:DBT +# OBSOLETE "dbt" +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&DPC, RPT_S); +# OBSOLETE if (RPT_C == 0) +# OBSOLETE PSW_SET (PSW_RP, 0); +# OBSOLETE } +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&DPC, cia + 8); +# OBSOLETE DID_TRAP = 2; +# OBSOLETE nia = 0xfffff120; /* debug_trap_address */ +# OBSOLETE +# OBSOLETE // DJMP +# OBSOLETE +# OBSOLETE void::function::do_djmp:address_word pcdisp, unsigned32 ra +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7)); +# OBSOLETE +# OBSOLETE _BRA,10001,00,6.RA,6.**,6.RC:BRA:short:mu:DJMP +# OBSOLETE "djmp r, r" +# OBSOLETE do_djmp(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10001,10,6.RA,_IMM12:BRA:short:mu:DJMP imm +# OBSOLETE "djmp r, " +# OBSOLETE do_djmp(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10001,10,6.RA,6.**,_IMM32:BRA:long:mu:DJMP imm long +# OBSOLETE "djmp r, " +# OBSOLETE do_djmp(_SD, pcdisp, val_Ra); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DJMPI +# OBSOLETE +# OBSOLETE void::function::do_djmpi:address_word pcdisp, unsigned32 imm +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); +# OBSOLETE +# OBSOLETE _BRA,10101,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJMPI +# OBSOLETE "djmpi , r" +# OBSOLETE do_djmpi(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10101,10,6.IMM_6,_IMM12:BRA:short:mu:DJMPI imm +# OBSOLETE "djmpi , " +# OBSOLETE do_djmpi(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10101,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJMPI imm long +# OBSOLETE "djmpi , " +# OBSOLETE do_djmpi(_SD, pcdisp, IMM_6); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DJSR +# OBSOLETE +# OBSOLETE void::function::do_djsr:address_word pcdisp, unsigned32 ra +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (ra & ~0x7)); +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + (ra & ~0x7) + 8); +# OBSOLETE +# OBSOLETE _BRA,10011,00,6.RA,6.**,6.RC:BRA:short:mu:DJSR +# OBSOLETE "djsr r, r" +# OBSOLETE do_djsr(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10011,10,6.RA,_IMM12:BRA:short:mu:DJSR imm +# OBSOLETE "djsr r, " +# OBSOLETE do_djsr(_SD, pcdisp, val_Ra); +# OBSOLETE _BRA,10011,10,6.RA,6.**,_IMM32:BRA:long:mu:DJSR imm long +# OBSOLETE "djsr r, " +# OBSOLETE do_djsr(_SD, pcdisp, val_Ra); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // DJSRI +# OBSOLETE +# OBSOLETE void::function::do_djsri:address_word pcdisp, unsigned32 imm +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_C, 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, pcdisp); +# OBSOLETE WRITE32_QUEUE (&RPT_E, cia + (imm << 3)); +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + (imm << 3) + 8); +# OBSOLETE +# OBSOLETE _BRA,10111,00,6.IMM_6,6.**,6.RC:BRA:short:mu:DJSRI +# OBSOLETE "djsri , r" +# OBSOLETE do_djsri(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10111,10,6.IMM_6,_IMM12:BRA:short:mu:DJSRI imm +# OBSOLETE "djsri , " +# OBSOLETE do_djsri(_SD, pcdisp, IMM_6); +# OBSOLETE _BRA,10111,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:DJSRI imm long +# OBSOLETE "djsri , " +# OBSOLETE do_djsri(_SD, pcdisp, IMM_6); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // JMP +# OBSOLETE +# OBSOLETE _BRA,00001,00,6.**,6.**,6.RC:BRA:short:mu:JMP +# OBSOLETE "jmp r" +# OBSOLETE nia = pcaddr; +# OBSOLETE if (RC == 62 && TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_RETURN; +# OBSOLETE _BRA,00001,10,_IMM18:BRA:short:mu:JMP imm +# OBSOLETE "jmp " +# OBSOLETE nia = pcaddr; +# OBSOLETE _BRA,00001,10,6.**,6.**,_IMM32:BRA:long:mu:JMP imm long +# OBSOLETE "jmp " +# OBSOLETE nia = pcaddr; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // JMPTNZ +# OBSOLETE +# OBSOLETE _BRA,00101,01,6.RA,6.**,6.RC:BRA:short:mu:JMPTNZ +# OBSOLETE "jmptnz r" +# OBSOLETE if (val_Ra != 0) +# OBSOLETE nia = pcaddr; +# OBSOLETE _BRA,00101,11,6.RA,_IMM12:BRA:short:mu:JMPTNZ imm +# OBSOLETE "jmptnz " +# OBSOLETE if (val_Ra != 0) +# OBSOLETE nia = pcaddr; +# OBSOLETE _BRA,00101,11,6.RA,6.**,_IMM32:BRA:long:mu:JMPTNZ imm long +# OBSOLETE "jmptnz " +# OBSOLETE if (val_Ra != 0) +# OBSOLETE nia = pcaddr; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // JMPTZR +# OBSOLETE +# OBSOLETE _BRA,00101,00,6.RA,6.**,6.RC:BRA:short:mu:JMPTZR +# OBSOLETE "jmptzr r" +# OBSOLETE if (val_Ra == 0) +# OBSOLETE nia = pcaddr; +# OBSOLETE _BRA,00101,10,6.RA,_IMM12:BRA:short:mu:JMPTZR imm +# OBSOLETE "jmptzr " +# OBSOLETE if (val_Ra == 0) +# OBSOLETE nia = pcaddr; +# OBSOLETE _BRA,00101,10,6.RA,6.**,_IMM32:BRA:long:mu:JMPTZR imm long +# OBSOLETE "jmptzr " +# OBSOLETE if (val_Ra == 0) +# OBSOLETE nia = pcaddr; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // JOINpp +# OBSOLETE +# OBSOLETE void::function::do_join_pp:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE switch (pp) { +# OBSOLETE case 0x0: /* LL */ +# OBSOLETE WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VL2_4(src)); +# OBSOLETE break; +# OBSOLETE case 0x1: /* LH */ +# OBSOLETE WRITE32_QUEUE (ra, ((unsigned32)VL2_4(rb) << 16) | VH2_4(src)); +# OBSOLETE break; +# OBSOLETE case 0x2: /* HL */ +# OBSOLETE WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VL2_4(src)); +# OBSOLETE break; +# OBSOLETE case 0x3: /* HH */ +# OBSOLETE WRITE32_QUEUE (ra, ((unsigned32)VH2_4(rb) << 16) | VH2_4(src)); +# OBSOLETE break; +# OBSOLETE } +# OBSOLETE +# OBSOLETE ::%s::pp:int pp +# OBSOLETE switch (pp) +# OBSOLETE { +# OBSOLETE case 0x0: return "ll"; +# OBSOLETE case 0x1: return "lh"; +# OBSOLETE case 0x2: return "hl"; +# OBSOLETE case 0x3: return "hh"; +# OBSOLETE default: return "?"; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IALU1,011,pp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:JOINpp +# OBSOLETE "join%s r, r, r" +# OBSOLETE do_join_pp(_SD, pp, Ra, Rb, Rc); +# OBSOLETE _IALU1,011,pp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:JOINpp imm +# OBSOLETE "join%s r, r, " +# OBSOLETE do_join_pp(_SD, pp, Ra, Rb, immHL); +# OBSOLETE _IALU1,011,pp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:JOINpp imm long +# OBSOLETE "join%s r, r, " +# OBSOLETE do_join_pp(_SD, pp, Ra, Rb, immHL); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // JSR +# OBSOLETE +# OBSOLETE _BRA,00011,00,6.**,6.**,6.RC:BRA:short:mu:JSR +# OBSOLETE "jsr r" +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE return pcaddr; +# OBSOLETE _BRA,00011,10,_IMM18:BRA:short:mu:JSR imm +# OBSOLETE "jsr " +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE return pcaddr; +# OBSOLETE _BRA,00011,10,6.**,6.**,_IMM32:BRA:long:mu:JSR imm long +# OBSOLETE "jsr " +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE return pcaddr; +# OBSOLETE +# OBSOLETE +# OBSOLETE // JSRTNZ +# OBSOLETE +# OBSOLETE _BRA,00111,01,6.RA,6.**,6.RC:BRA:short:mu:JSRTNZ +# OBSOLETE "jsrtnz r" +# OBSOLETE if (val_Ra != 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = pcaddr; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE _BRA,00111,11,6.RA,_IMM12:BRA:short:mu:JSRTNZ imm +# OBSOLETE "jsrtnz " +# OBSOLETE if (val_Ra != 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = pcaddr; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE _BRA,00111,11,6.RA,6.**,_IMM32:BRA:long:mu:JSRTNZ imm long +# OBSOLETE "jsrtnz " +# OBSOLETE if (val_Ra != 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = pcaddr; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // JSRTZR +# OBSOLETE +# OBSOLETE _BRA,00111,00,6.RA,6.**,6.RC:BRA:short:mu:JSRTZR +# OBSOLETE "jsrtzr r" +# OBSOLETE if (val_Ra == 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = pcaddr; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE _BRA,00111,10,6.RA,_IMM12:BRA:short:mu:JSRTZR imm +# OBSOLETE "jsrtzr " +# OBSOLETE if (val_Ra == 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = pcaddr; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE _BRA,00111,10,6.RA,6.**,_IMM32:BRA:long:mu:JSRTZR imm long +# OBSOLETE "jsrtzr " +# OBSOLETE if (val_Ra == 0) { +# OBSOLETE if (cia == RPT_E && PSW_VAL (PSW_RP)) +# OBSOLETE WRITE32_QUEUE (&GPR[62], RPT_S); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&GPR[62], cia + 8); +# OBSOLETE nia = pcaddr; +# OBSOLETE if (TRACE_CALL_P) +# OBSOLETE TRACE_ACTION |= TRACE_ACTION_CALL; +# OBSOLETE } +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // Post increment +# OBSOLETE +# OBSOLETE void::function::do_incr:int x, unsigned32 *rb, int delta +# OBSOLETE unsigned32 next_rb; +# OBSOLETE if (x == 1) +# OBSOLETE next_rb = *rb + delta; +# OBSOLETE else if (x == 3) +# OBSOLETE next_rb = *rb - delta; +# OBSOLETE else +# OBSOLETE next_rb = *rb; /* value not used */ +# OBSOLETE /* HW erratum: check value after incrementing */ +# OBSOLETE if (next_rb == MOD_E +# OBSOLETE && (x == 1 || x == 3) +# OBSOLETE && (PSW_VAL(PSW_MD))) { +# OBSOLETE WRITE32_QUEUE (rb, MOD_S); +# OBSOLETE } +# OBSOLETE else if (x == 1 || x == 3) +# OBSOLETE WRITE32_QUEUE (rb, next_rb); +# OBSOLETE +# OBSOLETE // LD2H +# OBSOLETE +# OBSOLETE int::function::make_even_reg:int reg, const char *name +# OBSOLETE if (reg & 1) +# OBSOLETE sim_engine_abort (SD, CPU, cia, +# OBSOLETE "0x%lx:%s odd register (r%d) used in multi-word load/mulx2h", +# OBSOLETE (long) cia, name, reg); +# OBSOLETE return reg; +# OBSOLETE +# OBSOLETE void::function::do_ld2h:int ra, unsigned32 rb, unsigned32 src +# OBSOLETE signed32 mem; +# OBSOLETE ra = make_even_reg(_SD, ra, "LD2H"); +# OBSOLETE mem = MEM(signed, rb + src, 4); +# OBSOLETE if (ra != 0) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 0], SEXT32(EXTRACTED32(mem, 0, 15), 16)); +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 1], SEXT32(EXTRACTED32(mem, 16, 31), 16)); +# OBSOLETE } +# OBSOLETE +# OBSOLETE ::%s::XX:int XX +# OBSOLETE switch (XX) +# OBSOLETE { +# OBSOLETE case 0: return ""; +# OBSOLETE case 1: return "+"; +# OBSOLETE case 3: return "-"; +# OBSOLETE default: return "?"; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IMEM,00011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD2H +# OBSOLETE "ld2h r, @(r, )":XX == 0 +# OBSOLETE "ld2h r, @(r%s, r)" +# OBSOLETE do_ld2h(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,00011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD2H long +# OBSOLETE "ld2h r, @(r, )" +# OBSOLETE do_ld2h(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LD2W +# OBSOLETE +# OBSOLETE void::function::do_ld2w:int ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned64 mem; +# OBSOLETE ra = make_even_reg(_SD, ra, "LD2W"); +# OBSOLETE mem = MEM(unsigned, rb + src, 8); +# OBSOLETE if (ra != 0) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 0], EXTRACTED64 (mem, 0, 31)); +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 1], EXTRACTED64 (mem, 32, 63)); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IMEM,00110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:L2W +# OBSOLETE "ld2w r, @(r, )":XX == 0 +# OBSOLETE "ld2w r, @(r%s, r)" +# OBSOLETE do_ld2w(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 8); +# OBSOLETE _IMEM,00110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:L2W long +# OBSOLETE "ld2w r, @(r, )" +# OBSOLETE do_ld2w(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LD4BH +# OBSOLETE +# OBSOLETE void::function::do_ld4bh:unsigned32 ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned16 l1, l2, h1, h2; +# OBSOLETE unsigned32 mem; +# OBSOLETE ra = make_even_reg(_SD, ra, "LD4BH"); +# OBSOLETE mem = MEM(unsigned, rb + src, 4); +# OBSOLETE h1 = SEXT16(EXTRACTED32(mem, 0, 7), 8); +# OBSOLETE l1 = SEXT16(EXTRACTED32(mem, 8, 15), 8); +# OBSOLETE h2 = SEXT16(EXTRACTED32(mem, 16, 23), 8); +# OBSOLETE l2 = SEXT16(EXTRACTED32(mem, 24, 31), 8); +# OBSOLETE if (ra != 0) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1); +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IMEM,00101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BH +# OBSOLETE "ld4bh r, @(r, )":XX == 0 +# OBSOLETE "ld4bh r, @(r%s, r)" +# OBSOLETE do_ld4bh(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,00101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BH long +# OBSOLETE "ld4bh r, @(r, )" +# OBSOLETE do_ld4bh(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LD4BHU +# OBSOLETE +# OBSOLETE void::function::do_ld4bhu:unsigned32 ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned16 l1, l2, h1, h2; +# OBSOLETE unsigned32 mem; +# OBSOLETE ra = make_even_reg(_SD, ra, "LD4BH"); +# OBSOLETE mem = MEM(signed, rb + src, 4); +# OBSOLETE h1 = EXTRACTED32(mem, 0, 7); +# OBSOLETE l1 = EXTRACTED32(mem, 8, 15); +# OBSOLETE h2 = EXTRACTED32(mem, 16, 23); +# OBSOLETE l2 = EXTRACTED32(mem, 24, 31); +# OBSOLETE if (ra != 0) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 0], (h1 << 16) | l1); +# OBSOLETE WRITE32_QUEUE (&GPR[ra + 1], (h2 << 16) | l2); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IMEM,01101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LD4BHU +# OBSOLETE "ld4hbu r, @(r, )":XX == 0 +# OBSOLETE "ld4hbu r, @(r%s, r)" +# OBSOLETE do_ld4bhu(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,01101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LD4BHU long +# OBSOLETE "ld4hbu r, @(r, )" +# OBSOLETE do_ld4bhu(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LDB +# OBSOLETE +# OBSOLETE void::function::do_ldb:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, MEM(signed, rb + src, 1)); +# OBSOLETE +# OBSOLETE _IMEM,00000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDB +# OBSOLETE "ldb r, @(r, )":XX == 0 +# OBSOLETE "ldb r, @(r%s, r)" +# OBSOLETE do_ldb(_SD, Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 1); +# OBSOLETE _IMEM,00000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDB long +# OBSOLETE "ldb r, @(r, )" +# OBSOLETE do_ldb(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LDBU +# OBSOLETE +# OBSOLETE void::function::do_ldbu:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 1)); +# OBSOLETE +# OBSOLETE _IMEM,01001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDBU +# OBSOLETE "ldbu r, @(r, )":XX == 0 +# OBSOLETE "ldbu r, @(r%s, r)" +# OBSOLETE do_ldbu(_SD, Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 1); +# OBSOLETE _IMEM,01001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDBU long +# OBSOLETE "ldbu r, @(r, )" +# OBSOLETE do_ldbu(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LDH +# OBSOLETE +# OBSOLETE void::function::do_ldh:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, MEM(signed, rb + src, 2)); +# OBSOLETE +# OBSOLETE _IMEM,00010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDH +# OBSOLETE "ldh r, @(r, )":XX == 0 +# OBSOLETE "ldh r, @(r%s, r)" +# OBSOLETE do_ldh(_SD, Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 2); +# OBSOLETE _IMEM,00010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDH long +# OBSOLETE "ldh r, @(r, )" +# OBSOLETE do_ldh(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LDHH +# OBSOLETE +# OBSOLETE void::function::do_ldhh:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, MEM(signed, rb + src, 2) << 16); +# OBSOLETE +# OBSOLETE _IMEM,00001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHH +# OBSOLETE "ldhh r, @(r, )":XX == 0 +# OBSOLETE "ldhh r, @(r%s, r)" +# OBSOLETE do_ldhh(_SD, Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 2); +# OBSOLETE _IMEM,00001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHH long +# OBSOLETE "ldhh r, @(r, )" +# OBSOLETE do_ldhh(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LDHU +# OBSOLETE +# OBSOLETE void::function::do_ldhu:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, MEM(unsigned, rb + src, 2)); +# OBSOLETE +# OBSOLETE _IMEM,01010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDHU +# OBSOLETE "ldhu r, @(r, )":XX == 0 +# OBSOLETE "ldhu r, @(r%s, r)" +# OBSOLETE do_ldhu(_SD, Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 2); +# OBSOLETE _IMEM,01010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDHU long +# OBSOLETE "ldhu r, @(r, )" +# OBSOLETE do_ldhu(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // LDW +# OBSOLETE +# OBSOLETE void::function::do_ldw:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, MEM(signed, rb + src, 4)); +# OBSOLETE +# OBSOLETE _IMEM,00100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:LDW +# OBSOLETE "ldw r, @(r, )":XX == 0 +# OBSOLETE "ldw r, @(r%s, r)" +# OBSOLETE do_ldw(_SD, Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,00100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:LDW long +# OBSOLETE "ldw r, @(r, )" +# OBSOLETE do_ldw(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MACa +# OBSOLETE +# OBSOLETE void::function::do_mac:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src +# OBSOLETE unsigned64 accum = *aa; +# OBSOLETE accum += (signed64) (rb) * (signed64) (src); +# OBSOLETE WRITE64_QUEUE (aa, accum); +# OBSOLETE WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63)); +# OBSOLETE +# OBSOLETE _IALU2,10100,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACa +# OBSOLETE "mac r, r, r" +# OBSOLETE do_mac(_SD, Aa, Ra, Rb, Rc); +# OBSOLETE _IALU2,10100,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACa imm +# OBSOLETE "mac r, r, " +# OBSOLETE do_mac(_SD, Aa, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MACSa +# OBSOLETE +# OBSOLETE void::function::do_macs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src +# OBSOLETE unsigned64 accum = *aa; +# OBSOLETE accum += ((signed64) (rb) * (signed64) (src)) << 1; +# OBSOLETE WRITE64_QUEUE (aa, accum); +# OBSOLETE WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31)); +# OBSOLETE +# OBSOLETE _IALU2,10101,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MACSa +# OBSOLETE "macs r, r, r" +# OBSOLETE do_macs(_SD, Aa, Ra, Rb, Rc); +# OBSOLETE _IALU2,10101,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MACSa imm +# OBSOLETE "macs r, r, " +# OBSOLETE do_macs(_SD, Aa, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MODDEC | MODINC +# OBSOLETE +# OBSOLETE _IMEM,00111,11,6.**,6.RB,_IMM6:IMEM:short:mu:MODDEC +# OBSOLETE "moddec r, " +# OBSOLETE do_incr(_SD, 3/*0b11*/, &GPR[RB], imm_5); +# OBSOLETE _IMEM,00111,01,6.**,6.RB,_IMM6:IMEM:short:mu:MODINC +# OBSOLETE "modinc r, " +# OBSOLETE do_incr(_SD, 1/*0b01*/, &GPR[RB], imm_5); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MSUBa +# OBSOLETE +# OBSOLETE void::function::do_msub:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src +# OBSOLETE unsigned64 accum = *aa; +# OBSOLETE accum -= (signed64) (rb) * (signed64) (src); +# OBSOLETE WRITE64_QUEUE (aa, accum); +# OBSOLETE WRITE32_QUEUE (ra, EXTRACTED64(accum, 32, 63)); +# OBSOLETE +# OBSOLETE _IALU2,10110,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBa +# OBSOLETE "msub r, r, r" +# OBSOLETE do_msub(_SD, Aa, Ra, Rb, Rc); +# OBSOLETE _IALU2,10110,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBa imm +# OBSOLETE "msub r, r, " +# OBSOLETE do_msub(_SD, Aa, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MSUBSa +# OBSOLETE +# OBSOLETE void::function::do_msubs:unsigned64 *aa, unsigned32 *ra, signed32 rb, signed32 src +# OBSOLETE unsigned64 accum = *aa; +# OBSOLETE accum -= ((signed64) (rb) * (signed64) (src)) << 1; +# OBSOLETE WRITE64_QUEUE (aa, accum); +# OBSOLETE WRITE32_QUEUE (ra, EXTRACTED64(accum, 0, 31)); +# OBSOLETE +# OBSOLETE _IALU2,10111,0,1.AA,6.RA,6.RB,6.RC:IALU2:short:iu:MSUBSa +# OBSOLETE "msubs r, r, r" +# OBSOLETE do_msubs(_SD, Aa, Ra, Rb, Rc); +# OBSOLETE _IALU2,10111,1,1.AA,6.RA,6.RB,_IMM6:IALU2:short:iu:MSUBSa imm +# OBSOLETE "msubs r, r, " +# OBSOLETE do_msubs(_SD, Aa, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MUL +# OBSOLETE +# OBSOLETE void::function::do_mul:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE WRITE32_QUEUE (ra, rb * src); +# OBSOLETE +# OBSOLETE _IALU2,10000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL +# OBSOLETE "mul r, r, r" +# OBSOLETE do_mul(_SD, Ra, Rb, Rc); +# OBSOLETE _IALU2,10000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL imm +# OBSOLETE "mul r, r, " +# OBSOLETE do_mul(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MUL2H +# OBSOLETE +# OBSOLETE void::function::do_mul2h:unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned16 high = VH2_4(rb) * VH2_4(src); +# OBSOLETE unsigned16 low = VL2_4(rb) * VL2_4(src); +# OBSOLETE WRITE32_QUEUE (ra, (high << 16) | low); +# OBSOLETE +# OBSOLETE _IALU2,00000,00,6.RA,6.RB,6.RC:IALU2:short:iu:MUL2H +# OBSOLETE "mul2h r, r, r" +# OBSOLETE do_mul2h(_SD, Ra, Rb, Rc); +# OBSOLETE _IALU2,00000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MUL2H imm +# OBSOLETE "mul2h r, r, " +# OBSOLETE do_mul2h(_SD, Ra, Rb, immHL); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MULX +# OBSOLETE +# OBSOLETE void::function::do_mulx:unsigned64 *aa, signed32 rb, signed32 src +# OBSOLETE WRITE64_QUEUE (aa, (signed64) (rb) * (signed64) (src)); +# OBSOLETE +# OBSOLETE _IALU2,11000,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULX +# OBSOLETE "mulx a, r, r" +# OBSOLETE do_mulx(_SD, Aa, Rb, Rc); +# OBSOLETE _IALU2,11000,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULX imm +# OBSOLETE "mulx a, r, " +# OBSOLETE do_mulx(_SD, Aa, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE // MULX2H +# OBSOLETE +# OBSOLETE void::function::do_mulx2h:int ra, signed32 rb, signed32 src, int high +# OBSOLETE signed32 result = rb * src; +# OBSOLETE if (!high) +# OBSOLETE { +# OBSOLETE ra = make_even_reg(_SD, ra, "MULX2H"); +# OBSOLETE if (ra != 0) +# OBSOLETE WRITE32_QUEUE (&GPR[ra+1], result); +# OBSOLETE } +# OBSOLETE else if (ra != 0) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&GPR[ra+0], result); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IALU2,00001,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULX2H +# OBSOLETE "mul2h r, r, r" +# OBSOLETE do_mulx2h(_SD, RA, RbH, RcH, 1); +# OBSOLETE do_mulx2h(_SD, RA, RbL, RcL, 0); +# OBSOLETE _IALU2,00001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULX2H imm +# OBSOLETE "mul2h r, r, " +# OBSOLETE do_mulx2h(_SD, RA, RbH, imm, 1); +# OBSOLETE do_mulx2h(_SD, RA, RbL, imm, 0); +# OBSOLETE +# OBSOLETE // MULHXpp +# OBSOLETE +# OBSOLETE void::function::do_mulhx:int pp, unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE signed32 value = 0; +# OBSOLETE switch (pp) { +# OBSOLETE case 0: /* LL */ +# OBSOLETE value = SEXT32(VL2_4(rb), 16) * SEXT32(VL2_4(src), 16); +# OBSOLETE break; +# OBSOLETE case 1: /* LH */ +# OBSOLETE value = SEXT32(VL2_4(rb), 16) * SEXT32(VH2_4(src), 16); +# OBSOLETE break; +# OBSOLETE case 2: /* HL */ +# OBSOLETE value = SEXT32(VH2_4(rb), 16) * SEXT32(VL2_4(src), 16); +# OBSOLETE break; +# OBSOLETE case 3: /* HH */ +# OBSOLETE value = SEXT32(VH2_4(rb), 16) * SEXT32(VH2_4(src), 16); +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "do_mulhx - internal error - bad switch"); +# OBSOLETE } +# OBSOLETE WRITE32_QUEUE (ra, value); +# OBSOLETE +# OBSOLETE _IALU2,001,pp,00,6.RA,6.RB,6.RC:IALU2:short:iu:MULHXpp +# OBSOLETE "mulhx%s r, r, r" +# OBSOLETE do_mulhx(_SD, pp, Ra, Rb, Rc); +# OBSOLETE _IALU2,001,pp,10,6.RA,6.RB,_IMM6:IALU2:short:iu:MULHXpp imm +# OBSOLETE "mulhx%s r, r, " +# OBSOLETE do_mulhx(_SD, pp, Ra, Rb, immHL); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MULXS +# OBSOLETE +# OBSOLETE void::function::do_mulxs:unsigned64 *aa, signed32 rb, signed32 src +# OBSOLETE WRITE64_QUEUE (aa, ((signed64) (rb) * (signed64) (src)) << 1); +# OBSOLETE +# OBSOLETE _IALU2,11001,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MULXS +# OBSOLETE "mulxs a, r, r" +# OBSOLETE do_mulxs(_SD, Aa, Rb, Rc); +# OBSOLETE _IALU2,11001,10,5.*,1.AA,6.RB,_IMM6:IALU2:short:iu:MULXS imm +# OBSOLETE "mulxs a, r, " +# OBSOLETE do_mulxs(_SD, Aa, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MVFACC +# OBSOLETE +# OBSOLETE void::function::do_mvfacc:unsigned32 *ra, unsigned64 ab, unsigned32 src +# OBSOLETE while (src > 63) src -= 64; +# OBSOLETE WRITE32_QUEUE (ra, ((signed64)ab) >> src); +# OBSOLETE +# OBSOLETE _IALU2,11111,00,6.RA,5.*,1.AB,6.RC:IALU2:short:iu:MVFACC +# OBSOLETE "mvfacc r, a, r" +# OBSOLETE do_mvfacc(_SD, Ra, *Ab, Rc); +# OBSOLETE _IALU2,11111,10,6.RA,5.*,1.AB,_IMM6:IALU2:short:iu:MVFACC imm +# OBSOLETE "mvfacc r, a, " +# OBSOLETE do_mvfacc(_SD, Ra, *Ab, imm_6u); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MVFSYS +# OBSOLETE +# OBSOLETE _BRA,11110,00,6.RA,6.CR,6.ID:BRA:short:mu:MVFSYS +# OBSOLETE "mvfsys r, cr" +# OBSOLETE switch (ID) { +# OBSOLETE case 0: +# OBSOLETE if (CR >= NR_CONTROL_REGISTERS) +# OBSOLETE sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR"); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (Ra, (CPU)->regs.control[CR]); +# OBSOLETE break; +# OBSOLETE case 1: +# OBSOLETE WRITE32_QUEUE (Ra, PSWL); +# OBSOLETE break; +# OBSOLETE case 2: +# OBSOLETE WRITE32_QUEUE (Ra, EXTRACTED32(PSWH, 16, 31)); +# OBSOLETE break; +# OBSOLETE case 3: +# OBSOLETE WRITE32_QUEUE (Ra, PSW_FLAG_VAL(CR)); +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID"); +# OBSOLETE } +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MVTACC +# OBSOLETE +# OBSOLETE _IALU2,01111,00,5.*,1.AA,6.RB,6.RC:IALU2:short:iu:MVTACC +# OBSOLETE "mvtacc a, r, r" +# OBSOLETE WRITE64_QUEUE (Aa, INSERTED64(RbU, 0, 31) | (RcU)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // MVTSYS +# OBSOLETE +# OBSOLETE _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS +# OBSOLETE "mvtsys cr, r" +# OBSOLETE switch (ID) { +# OBSOLETE case 0: /* control register */ +# OBSOLETE if (CR >= NR_CONTROL_REGISTERS) +# OBSOLETE sim_engine_abort (SD, CPU, cia, "FIXME - illegal CR"); +# OBSOLETE else +# OBSOLETE { +# OBSOLETE unsigned32 value = Rb; +# OBSOLETE CPU->mvtsys_left_p = 1; +# OBSOLETE if (CR == processor_status_word_cr) +# OBSOLETE { +# OBSOLETE unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */ +# OBSOLETE value = ds | (value & PSW_VALID); +# OBSOLETE } +# OBSOLETE else if (CR == backup_processor_status_word_cr +# OBSOLETE || CR == debug_backup_processor_status_word_cr) +# OBSOLETE value &= DPSW_VALID; +# OBSOLETE else if (CR == eit_vector_base_cr) +# OBSOLETE value &= EIT_VALID; +# OBSOLETE WRITE32_QUEUE (&(CPU)->regs.control[CR], value); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 1: /* PSWL */ +# OBSOLETE WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31), +# OBSOLETE PSW_VALID & 0x0000ffff); +# OBSOLETE break; +# OBSOLETE case 2: /* PSWH */ +# OBSOLETE { +# OBSOLETE unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */ +# OBSOLETE WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds, +# OBSOLETE (PSW_VALID | ds) & 0xffff0000); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 3: /* FLAG */ +# OBSOLETE PSW_FLAG_SET_QUEUE(CR, Rb & 1); +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID"); +# OBSOLETE } +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // NOP +# OBSOLETE +# OBSOLETE _BRA,01111,00,6.**,6.**,6.**:BRA:short:iu,mu:NOP +# OBSOLETE "nop" +# OBSOLETE /* NOP */; +# OBSOLETE +# OBSOLETE +# OBSOLETE // NOT +# OBSOLETE +# OBSOLETE _LOGIC,11001,00,6.RA,6.RB,6.*:LOGIC:short:iu,mu:NOT +# OBSOLETE "not r, r" +# OBSOLETE WRITE32_QUEUE (Ra, ~Rb); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // NOTFG +# OBSOLETE +# OBSOLETE _LOGIC,01001,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:NOTFG +# OBSOLETE "notfg f, f" +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, !PSW_FLAG_VAL(FB)); +# OBSOLETE +# OBSOLETE +# OBSOLETE // OR +# OBSOLETE +# OBSOLETE _LOGIC,11010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:OR +# OBSOLETE "or r, r, r" +# OBSOLETE WRITE32_QUEUE (Ra, Rb | Rc); +# OBSOLETE _LOGIC,11010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:OR imm +# OBSOLETE "or r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb | imm); +# OBSOLETE _LOGIC,11010,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:OR imm long +# OBSOLETE "or r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb | imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ORFG +# OBSOLETE +# OBSOLETE _LOGIC,01010,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:ORFG +# OBSOLETE "orfg f, f, f" +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | PSW_FLAG_VAL(FC)); +# OBSOLETE _LOGIC,01010,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:ORFG imm +# OBSOLETE "orfg f, f, " +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) | (imm_6 & 1)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // REIT +# OBSOLETE +# OBSOLETE _BRA,01000,00,6.**,6.**,6.**:BRA:short:mu:REIT +# OBSOLETE "reit" +# OBSOLETE WRITE32_QUEUE (&PSW, bPSW); +# OBSOLETE nia = bPC; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // REPEAT +# OBSOLETE +# OBSOLETE void::function::do_repeat:unsigned32 count, address_word pcaddr +# OBSOLETE address_word rpt_s = cia + 8; +# OBSOLETE address_word rpt_e = cia + pcaddr; +# OBSOLETE +# OBSOLETE if (count == 0) +# OBSOLETE sim_engine_abort (SD, CPU, cia, "REPEAT with ra=0 and REPEATI with imm = 0 is forbidden."); +# OBSOLETE if (count > 1) +# OBSOLETE PSW_SET_QUEUE (PSW_RP, 1); +# OBSOLETE if (rpt_e < rpt_s + 0x10) +# OBSOLETE sim_io_eprintf (sd, "warning: 0x%lx: REPEAT or REPEATI loop is too small\n", (long) cia); +# OBSOLETE WRITE32_QUEUE (&RPT_C, count - 1); +# OBSOLETE WRITE32_QUEUE (&RPT_S, rpt_s); +# OBSOLETE WRITE32_QUEUE (&RPT_E, rpt_e); +# OBSOLETE +# OBSOLETE _BRA,11000,00,6.RA,6.**,6.RC:BRA:short:mu:REPEAT +# OBSOLETE "repeat r, r" +# OBSOLETE do_repeat(_SD, val_Ra, pcaddr); +# OBSOLETE _BRA,11000,10,6.RA,_IMM12:BRA:short:mu:REPEAT imm +# OBSOLETE "repeat r, " +# OBSOLETE do_repeat(_SD, val_Ra, pcaddr); +# OBSOLETE _BRA,11000,10,6.RA,6.**,_IMM32:BRA:long:mu:REPEAT imm long +# OBSOLETE "repeat r, " +# OBSOLETE do_repeat(_SD, val_Ra, pcaddr); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // REPEATI +# OBSOLETE +# OBSOLETE _BRA,11010,00,6.IMM_6,6.**,6.RC:BRA:short:mu:REPEATI +# OBSOLETE "repeati , r" +# OBSOLETE do_repeat(_SD, IMM_6, pcaddr); +# OBSOLETE _BRA,11010,10,6.IMM_6,_IMM12:BRA:short:mu:REPEATI imm +# OBSOLETE "repeati , " +# OBSOLETE do_repeat(_SD, IMM_6, pcaddr); +# OBSOLETE _BRA,11010,10,6.IMM_6,6.**,_IMM32:BRA:long:mu:REPEATI imm long +# OBSOLETE "repeati , " +# OBSOLETE do_repeat(_SD, IMM_6, pcaddr); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // RTD +# OBSOLETE +# OBSOLETE _BRA,01010,00,6.*,6.*,6.*:BRA:short:mu:RTD +# OBSOLETE "rtd" +# OBSOLETE WRITE32_QUEUE (&PSW, DPSW); +# OBSOLETE nia = DPC; +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ROT +# OBSOLETE +# OBSOLETE _LOGIC,10100,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT +# OBSOLETE "rot r, r, r" +# OBSOLETE WRITE32_QUEUE (Ra, ROT32(Rb, Rc & 0x1f)); +# OBSOLETE _LOGIC,10100,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT imm +# OBSOLETE "rot r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, ROT32(Rb, imm & 0x1f)); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ROT2H +# OBSOLETE +# OBSOLETE void::function::do_rot2h:unsigned32 *ra, unsigned32 rb, signed32 src +# OBSOLETE unsigned16 high = ROTR16(VH2_4(rb), VH2_4(src) & 0xf); +# OBSOLETE unsigned16 low = ROTR16(VL2_4(rb), VL2_4(src) & 0xf); +# OBSOLETE WRITE32_QUEUE (ra, (high << 16) | low); +# OBSOLETE +# OBSOLETE _LOGIC,10101,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:ROT2H +# OBSOLETE "rot2h r, r, r" +# OBSOLETE do_rot2h(_SD, Ra, Rb, Rc); +# OBSOLETE _LOGIC,10101,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:ROT2H imm +# OBSOLETE "rot2h r, r, " +# OBSOLETE do_rot2h(_SD, Ra, Rb, immHL); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SAT +# OBSOLETE +# OBSOLETE void::function::do_sat:signed32 *ra, signed32 rb, signed32 src +# OBSOLETE int bits = LSMASKED32(src, 4, 0); /* 5 */ +# OBSOLETE signed32 sat = LSMASK32(bits, 0) >> 2; +# OBSOLETE signed32 nsat = ~sat; +# OBSOLETE signed32 value; +# OBSOLETE if (bits != src) +# OBSOLETE sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia); +# OBSOLETE if (bits == 0) +# OBSOLETE value = rb; +# OBSOLETE else if (rb >= sat) +# OBSOLETE value = sat; +# OBSOLETE else if (rb <= nsat) +# OBSOLETE value = nsat; +# OBSOLETE else +# OBSOLETE value = rb; +# OBSOLETE WRITE32_QUEUE (ra, value); +# OBSOLETE +# OBSOLETE _IALU2,01000,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT +# OBSOLETE "sat r, r, r" +# OBSOLETE do_sat(_SD, Ra, Rb, Rc); +# OBSOLETE _IALU2,01000,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT imm +# OBSOLETE "sat r, r, " +# OBSOLETE do_sat(_SD, Ra, Rb, imm_5); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SAT2H +# OBSOLETE +# OBSOLETE void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int updates_f4 +# OBSOLETE int bits = LSMASKED32(src, 4, 0); /* 5 */ +# OBSOLETE signed32 sat = LSMASK32(bits, 0) >> 2; +# OBSOLETE signed32 nsat = ~sat; +# OBSOLETE signed32 value; +# OBSOLETE if (bits != src) +# OBSOLETE sim_io_eprintf (sd, "warning: 0x%lx:SAT bit overflow\n", (long) cia); +# OBSOLETE if (bits == 0) +# OBSOLETE value = rb; +# OBSOLETE else if (rb >= sat) +# OBSOLETE value = sat; +# OBSOLETE else if (rb <= nsat) +# OBSOLETE value = nsat; +# OBSOLETE else +# OBSOLETE value = rb; +# OBSOLETE if (high) +# OBSOLETE WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); +# OBSOLETE if (updates_f4) +# OBSOLETE { +# OBSOLETE /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */ +# OBSOLETE if(STATE_CPU (sd, 0)->mvtsys_left_p) +# OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); +# OBSOLETE PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1)); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IALU2,01001,00,6.RA,6.RB,6.RC:IALU2:short:iu:SAT2H +# OBSOLETE "sat2h r, r, r" +# OBSOLETE do_sath(_SD, Ra, RbH, RcH, 1, 0); +# OBSOLETE do_sath(_SD, Ra, RbL, RcL, 0, 0); +# OBSOLETE _IALU2,01001,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SAT2H imm +# OBSOLETE "sat2h r, r, " +# OBSOLETE do_sath(_SD, Ra, RbH, imm_5, 1, 0); +# OBSOLETE do_sath(_SD, Ra, RbL, imm_5, 0, 0); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SATHp +# OBSOLETE +# OBSOLETE ::%s::p:int p +# OBSOLETE switch (p) +# OBSOLETE { +# OBSOLETE case 0: return "l"; +# OBSOLETE case 1: return "h"; +# OBSOLETE default: return "?"; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IALU2,1110,p,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATHP +# OBSOLETE "sath%s

r, r, r" +# OBSOLETE do_sath(_SD, Ra, Rb, Rc, p, 1); +# OBSOLETE _IALU2,1110,p,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATHP imm +# OBSOLETE "sath%s

r, r, " +# OBSOLETE do_sath(_SD, Ra, Rb, imm_5, p, 1); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SATZ +# OBSOLETE +# OBSOLETE void::function::do_satz:signed32 *ra, signed32 rb, signed32 src +# OBSOLETE if (rb < 0) +# OBSOLETE WRITE32_QUEUE (ra, 0); +# OBSOLETE else +# OBSOLETE do_sat (_SD, ra, rb, src); +# OBSOLETE +# OBSOLETE _IALU2,01010,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ +# OBSOLETE "satz r, r, r" +# OBSOLETE do_satz(_SD, Ra, Rb, Rc); +# OBSOLETE _IALU2,01010,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ imm +# OBSOLETE "satz r, r, " +# OBSOLETE do_satz(_SD, Ra, Rb, imm_5); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SATZ2H +# OBSOLETE +# OBSOLETE void::function::do_satzh:signed32 *ra, signed16 rb, signed32 src, int high +# OBSOLETE int bits = LSMASKED32(src, 3, 0); /*4*/ +# OBSOLETE signed16 sat = LSMASK16(bits, 0) >> 2; +# OBSOLETE signed16 nsat = 0; +# OBSOLETE signed16 value; +# OBSOLETE if (bits != src) +# OBSOLETE sim_io_eprintf (sd, "warning: 0x%lx:SATZ2H bit overflow\n", (long) cia); +# OBSOLETE if (bits == 0 && rb > sat) +# OBSOLETE value = rb; +# OBSOLETE else if (rb > sat) +# OBSOLETE value = sat; +# OBSOLETE else if (rb < nsat) +# OBSOLETE value = nsat; +# OBSOLETE else +# OBSOLETE value = rb; +# OBSOLETE if (high) +# OBSOLETE WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); +# OBSOLETE +# OBSOLETE +# OBSOLETE _IALU2,01011,00,6.RA,6.RB,6.RC:IALU2:short:iu:SATZ2H +# OBSOLETE "satz2h r, r, r" +# OBSOLETE do_satzh(_SD, Ra, RbH, RcH, 1); +# OBSOLETE do_satzh(_SD, Ra, RbL, RcL, 0); +# OBSOLETE _IALU2,01011,10,6.RA,6.RB,_IMM6:IALU2:short:iu:SATZ2H imm +# OBSOLETE "satz2h r, r, " +# OBSOLETE do_satzh(_SD, Ra, RbH, imm, 1); +# OBSOLETE do_satzh(_SD, Ra, RbL, imm, 0); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRA +# OBSOLETE +# OBSOLETE void::function::do_sra:unsigned32 *ra, unsigned32 rb, signed32 src +# OBSOLETE unsigned32 value; +# OBSOLETE while (src > 31) src -= 32; +# OBSOLETE while (src < -32) src += 32; +# OBSOLETE if (src >= 0) +# OBSOLETE value = (signed32)rb >> src; +# OBSOLETE else if (src == -32) +# OBSOLETE value = 0; +# OBSOLETE else +# OBSOLETE value = rb << -src; +# OBSOLETE WRITE32_QUEUE (ra, value); +# OBSOLETE +# OBSOLETE _LOGIC,10000,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA +# OBSOLETE "sra r, r, r" +# OBSOLETE do_sra(_SD, Ra, Rb, Rc); +# OBSOLETE _LOGIC,10000,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA imm +# OBSOLETE "sra r, r, " +# OBSOLETE do_sra(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRAHp +# OBSOLETE +# OBSOLETE void::function::do_srah:unsigned32 *ra, unsigned32 rb, int src, int high +# OBSOLETE unsigned32 value; +# OBSOLETE while (src > 31) src -= 32; +# OBSOLETE while (src < -32) src += 32; +# OBSOLETE if (src >= 0) +# OBSOLETE value = (signed32)rb >> src; +# OBSOLETE else if (src == -32) +# OBSOLETE value = 0; +# OBSOLETE else +# OBSOLETE value = rb << -src; +# OBSOLETE if (high) +# OBSOLETE WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); +# OBSOLETE +# OBSOLETE _LOGIC,0010,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRAHP +# OBSOLETE "srah%s

r, r, r" +# OBSOLETE do_srah(_SD, Ra, Rb, Rc, p); +# OBSOLETE _LOGIC,0010,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRAHP imm +# OBSOLETE "srah%s

r, r, " +# OBSOLETE do_srah(_SD, Ra, Rb, imm, p); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRA2H +# OBSOLETE +# OBSOLETE _LOGIC,10001,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRA2H +# OBSOLETE "sra2h r, r, r" +# OBSOLETE signed32 srcH = RcH; +# OBSOLETE signed32 srcL = RcL; +# OBSOLETE while (srcH > 15) srcH -= 16; +# OBSOLETE while (srcH < -16) srcH += 16; +# OBSOLETE while (srcL > 15) srcL -= 16; +# OBSOLETE while (srcL < -16) srcL += 16; +# OBSOLETE do_srah(_SD, Ra, RbH, srcH, 1); +# OBSOLETE do_srah(_SD, Ra, RbL, srcL, 0); +# OBSOLETE _LOGIC,10001,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRA2H imm +# OBSOLETE "sra2h r, r, " +# OBSOLETE signed32 src = imm; +# OBSOLETE while (src > 15) src -= 16; +# OBSOLETE while (src < -16) src += 16; +# OBSOLETE do_srah(_SD, Ra, RbH, src, 1); +# OBSOLETE do_srah(_SD, Ra, RbL, src, 0); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRC +# OBSOLETE +# OBSOLETE void::function::do_src:unsigned32 *ra, unsigned32 rb, int src +# OBSOLETE unsigned32 value; +# OBSOLETE unsigned64 operand; +# OBSOLETE unsigned64 shifted; +# OBSOLETE while (src > 31) src -= 32; +# OBSOLETE while (src < -32) src += 32; +# OBSOLETE if (src >= 0) +# OBSOLETE { +# OBSOLETE operand = (INSERTED64(rb, 0, 31) | INSERTED64(*ra, 32, 63)); +# OBSOLETE shifted = operand >> src; +# OBSOLETE value = EXTRACTED64(shifted, 32, 63); +# OBSOLETE } +# OBSOLETE else +# OBSOLETE { +# OBSOLETE operand = (INSERTED64(*ra, 0, 31) | INSERTED64(rb, 32, 63)); +# OBSOLETE shifted = operand << -src; +# OBSOLETE value = EXTRACTED64(shifted, 0, 31); +# OBSOLETE } +# OBSOLETE WRITE32_QUEUE (ra, value); +# OBSOLETE +# OBSOLETE _LOGIC,10110,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRC +# OBSOLETE "src r, r, r" +# OBSOLETE do_src(_SD, Ra, Rb, Rc); +# OBSOLETE _LOGIC,10110,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRC imm +# OBSOLETE "src r, r, " +# OBSOLETE do_src(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRL +# OBSOLETE +# OBSOLETE void::function::do_srl:unsigned32 *ra, unsigned32 rb, int src +# OBSOLETE unsigned32 value; +# OBSOLETE while (src > 31) src -= 32; +# OBSOLETE while (src < -32) src += 32; +# OBSOLETE if (src >= 0) +# OBSOLETE value = (unsigned32)rb >> src; +# OBSOLETE else if (src == -32) +# OBSOLETE value = 0; +# OBSOLETE else +# OBSOLETE value = (unsigned32)rb << -src; +# OBSOLETE WRITE32_QUEUE (ra, value); +# OBSOLETE +# OBSOLETE _LOGIC,10010,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL +# OBSOLETE "srl r, r, r" +# OBSOLETE do_srl(_SD, Ra, Rb, Rc); +# OBSOLETE _LOGIC,10010,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL imm +# OBSOLETE "srl r, r, " +# OBSOLETE do_srl(_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRLHp +# OBSOLETE +# OBSOLETE void::function::do_srlh:unsigned32 *ra, unsigned32 rb, int src, int high +# OBSOLETE unsigned32 value; +# OBSOLETE while (src > 31) src -= 32; +# OBSOLETE while (src < -32) src += 32; +# OBSOLETE if (src >= 0) +# OBSOLETE value = rb >> src; +# OBSOLETE else if (src == -32) +# OBSOLETE value = 0; +# OBSOLETE else +# OBSOLETE value = rb << -src; +# OBSOLETE if (high) +# OBSOLETE WRITE32_QUEUE_MASK (ra, value << 16, 0xffff0000); +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE_MASK (ra, value, 0x0000ffff); +# OBSOLETE +# OBSOLETE _LOGIC,0011,p,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRLHP +# OBSOLETE "srlh%s

r, r, r" +# OBSOLETE do_srlh(_SD, Ra, Rb, Rc, p); +# OBSOLETE _LOGIC,0011,p,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRLHP imm +# OBSOLETE "srlh%s

r, r, " +# OBSOLETE do_srlh(_SD, Ra, Rb, imm, p); +# OBSOLETE +# OBSOLETE +# OBSOLETE // SRL2H +# OBSOLETE +# OBSOLETE _LOGIC,10011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:SRL2H +# OBSOLETE "srl2h r, r, r" +# OBSOLETE signed32 srcH = RcH; +# OBSOLETE signed32 srcL = RcL; +# OBSOLETE while (srcH > 15) srcH -= 16; +# OBSOLETE while (srcH < -16) srcH += 16; +# OBSOLETE while (srcL > 15) srcL -= 16; +# OBSOLETE while (srcL < -16) srcL += 16; +# OBSOLETE do_srlh(_SD, Ra, RbHU, srcH, 1); +# OBSOLETE do_srlh(_SD, Ra, RbLU, srcL, 0); +# OBSOLETE _LOGIC,10011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:SRL2H imm +# OBSOLETE "srl2h r, r, " +# OBSOLETE signed32 src = imm; +# OBSOLETE while (src > 15) src -= 16; +# OBSOLETE while (src < -16) src += 16; +# OBSOLETE do_srlh(_SD, Ra, RbHU, src, 1); +# OBSOLETE do_srlh(_SD, Ra, RbLU, src, 0); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ST2H +# OBSOLETE +# OBSOLETE void::function::get_even_reg:int *reg, unsigned32 *r0, const char *name +# OBSOLETE if (*reg & 1) +# OBSOLETE sim_engine_abort (SD, CPU, cia, +# OBSOLETE "0x%lx:%s odd register (r%d) used in multi-word store", +# OBSOLETE (long) cia, name, *reg); +# OBSOLETE if (*reg == 0) +# OBSOLETE *r0 = 0; +# OBSOLETE else +# OBSOLETE *r0 = GPR[*reg]; +# OBSOLETE +# OBSOLETE void::function::do_st2h:int ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned32 val_ra; +# OBSOLETE unsigned32 mem; +# OBSOLETE get_even_reg(_SD, &ra, &val_ra, "ST2H"); +# OBSOLETE mem = INSERTED32(val_ra, 0, 15) | +# OBSOLETE INSERTED32(GPR[ra + 1], 16, 31); +# OBSOLETE STORE(rb + src, 4, mem); +# OBSOLETE +# OBSOLETE _IMEM,10011,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2H +# OBSOLETE "st2h r, @(r, )":XX == 0 +# OBSOLETE "st2h r, @(r%s, r)" +# OBSOLETE do_st2h(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,10011,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2H long +# OBSOLETE "st2h r, @(r, )" +# OBSOLETE do_st2h(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ST2W +# OBSOLETE +# OBSOLETE void::function::do_st2w:int ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned32 val_ra; +# OBSOLETE unsigned64 mem; +# OBSOLETE get_even_reg(_SD, &ra, &val_ra, "ST2W"); +# OBSOLETE mem = INSERTED64(val_ra, 0, 31) | INSERTED64(GPR[ra + 1], 32, 63); +# OBSOLETE STORE(rb + src, 8, mem); +# OBSOLETE +# OBSOLETE _IMEM,10110,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST2W +# OBSOLETE "st2w r, @(r, )":XX == 0 +# OBSOLETE "st2w r, @(r%s, r)" +# OBSOLETE do_st2w(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 8); +# OBSOLETE _IMEM,10110,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST2W long +# OBSOLETE "st2w r, @(r, )" +# OBSOLETE do_st2w(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // ST4HB +# OBSOLETE +# OBSOLETE void::function::do_st4hb:int ra, unsigned32 rb, unsigned32 src +# OBSOLETE unsigned32 val_ra; +# OBSOLETE unsigned32 mem; +# OBSOLETE get_even_reg(_SD, &ra, &val_ra, "ST4HB"); +# OBSOLETE mem = INSERTED32(EXTRACTED32(val_ra, 8, 15), 0, 7) | +# OBSOLETE INSERTED32(EXTRACTED32(val_ra, 24, 31), 8, 15) | +# OBSOLETE INSERTED32(EXTRACTED32(GPR[ra + 1], 8, 15), 16, 23) | +# OBSOLETE INSERTED32(EXTRACTED32(GPR[ra + 1], 24, 31), 24, 31); +# OBSOLETE STORE(rb + src, 4, mem); +# OBSOLETE +# OBSOLETE _IMEM,10101,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:ST4HB +# OBSOLETE "st4hb r, @(r, )":XX == 0 +# OBSOLETE "st4hb r, @(r%s, r)" +# OBSOLETE do_st4hb(_SD, RA, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,10101,10,6.RA,6.RB,_IMM32:IMEM:long:mu:ST4HB long +# OBSOLETE "st4hb r, @(r, )" +# OBSOLETE do_st4hb(_SD, RA, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // STB +# OBSOLETE +# OBSOLETE void::function::do_stb:unsigned32 ra, unsigned32 rb, unsigned32 src +# OBSOLETE STORE(rb + src, 1, EXTRACTED32(ra, 24, 31)); +# OBSOLETE +# OBSOLETE _IMEM,10000,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STB +# OBSOLETE "stb r, @(r, )":XX == 0 +# OBSOLETE "stb r, @(r%s, r)" +# OBSOLETE do_stb(_SD, val_Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 1); +# OBSOLETE _IMEM,10000,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STB long +# OBSOLETE "stb r, @(r, )" +# OBSOLETE do_stb(_SD, val_Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // STH +# OBSOLETE +# OBSOLETE void::function::do_sth:unsigned32 ra, unsigned32 rb, unsigned32 src +# OBSOLETE STORE(rb + src, 2, EXTRACTED32(ra, 16, 31)); +# OBSOLETE +# OBSOLETE _IMEM,10010,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STH +# OBSOLETE "sth r, @(r, )":XX == 0 +# OBSOLETE "sth r, @(r%s, r)" +# OBSOLETE do_sth(_SD, val_Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 2); +# OBSOLETE _IMEM,10010,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STH long +# OBSOLETE "sth r, @(r, )" +# OBSOLETE do_sth(_SD, val_Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // STHH +# OBSOLETE +# OBSOLETE void::function::do_sthh:unsigned32 ra, unsigned32 rb, unsigned32 src +# OBSOLETE STORE(rb + src, 2, EXTRACTED32(ra, 0, 15)); +# OBSOLETE +# OBSOLETE _IMEM,10001,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STHH +# OBSOLETE "sthh r, @(r, )":XX == 0 +# OBSOLETE "sthh r, @(r%s, r)" +# OBSOLETE do_sthh(_SD, val_Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 2); +# OBSOLETE _IMEM,10001,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STHH long +# OBSOLETE "sthh r, @(r, )" +# OBSOLETE do_sthh(_SD, val_Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // STW +# OBSOLETE +# OBSOLETE void::function::do_stw:unsigned32 ra, unsigned32 rb, unsigned32 src +# OBSOLETE STORE(rb + src, 4, ra); +# OBSOLETE +# OBSOLETE _IMEM,10100,XX,6.RA,6.RB,6.SRC_6:IMEM:short:mu:STW +# OBSOLETE "stw r, @(r, )":XX == 0 +# OBSOLETE "stw r, @(r%s, r)" +# OBSOLETE do_stw(_SD, val_Ra, Rb, src); +# OBSOLETE do_incr(_SD, XX, &GPR[RB], 4); +# OBSOLETE _IMEM,10100,10,6.RA,6.RB,_IMM32:IMEM:long:mu:STW long +# OBSOLETE "stw r, @(r, )" +# OBSOLETE do_stw(_SD, val_Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SUB +# OBSOLETE +# OBSOLETE void::function::do_sub:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE ALU_BEGIN(rb); +# OBSOLETE ALU_SUBB(imm); +# OBSOLETE ALU_END(ra); +# OBSOLETE +# OBSOLETE _IALU1,00010,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB +# OBSOLETE "sub r, r, r" +# OBSOLETE do_sub (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00010,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB imm +# OBSOLETE "sub r, r, " +# OBSOLETE do_sub (_SD, Ra, Rb, imm); +# OBSOLETE _IALU1,00010,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB imm long +# OBSOLETE "sub r, r, " +# OBSOLETE do_sub (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SUB2H +# OBSOLETE +# OBSOLETE void::function::do_sub2h:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE unsigned16 high = VH2_4(rb) - VH2_4(imm); +# OBSOLETE unsigned16 low = VL2_4(rb) - VL2_4(imm); +# OBSOLETE WRITE32_QUEUE (ra, (high << 16) | low); +# OBSOLETE +# OBSOLETE _IALU1,00011,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUB2H +# OBSOLETE "sub2h r, r, r" +# OBSOLETE do_sub2h (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00011,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUB2H imm +# OBSOLETE "sub2h r, r, " +# OBSOLETE do_sub2h (_SD, Ra, Rb, immHL); +# OBSOLETE _IALU1,00011,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUB2H imm long +# OBSOLETE "sub2h r, r, " +# OBSOLETE do_sub2h (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SUBB +# OBSOLETE +# OBSOLETE void::function::do_subb:unsigned32 *ra, unsigned32 rb, unsigned32 imm +# OBSOLETE ALU_BEGIN(rb); +# OBSOLETE ALU_SUBB_B(imm, ALU_CARRY); +# OBSOLETE ALU_END(ra); +# OBSOLETE +# OBSOLETE _IALU1,00101,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBB +# OBSOLETE "subb r, r, r" +# OBSOLETE do_subb (_SD, Ra, Rb, Rc); +# OBSOLETE _IALU1,00101,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBB imm +# OBSOLETE "subb r, r, " +# OBSOLETE do_subb (_SD, Ra, Rb, imm); +# OBSOLETE _IALU1,00101,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBB imm long +# OBSOLETE "subb r, r, " +# OBSOLETE do_subb (_SD, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // SUBHppp +# OBSOLETE +# OBSOLETE void::function::do_subh_ppp:int ppp, unsigned32 *ra, unsigned32 rb, unsigned32 src +# OBSOLETE switch (ppp) { +# OBSOLETE case 0x0: /* LLL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_SUBB(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x1: /* LLH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_SUBB(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x2: /* LHL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_SUBB(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x3: /* LHH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_SUBB(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 0); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x4: /* HLL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_SUBB(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x5: /* HLH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VL2_4(rb)); +# OBSOLETE ALU16_SUBB(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x6: /* HHL */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_SUBB(VL2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE case 0x7: /* HHH */ +# OBSOLETE { +# OBSOLETE ALU16_BEGIN(VH2_4(rb)); +# OBSOLETE ALU16_SUBB(VH2_4(src)); +# OBSOLETE ALU16_END(ra, 1); +# OBSOLETE } +# OBSOLETE break; +# OBSOLETE default: +# OBSOLETE sim_engine_abort (SD, CPU, cia, "do_subh_ppp - internal error - bad switch"); +# OBSOLETE } +# OBSOLETE +# OBSOLETE _IALU1,11,ppp,00,6.RA,6.RB,6.RC:IALU1:short:iu,mu:SUBHppp +# OBSOLETE "subh%s r, r, r" +# OBSOLETE do_subh_ppp(_SD, ppp, Ra, Rb, Rc); +# OBSOLETE _IALU1,11,ppp,10,6.RA,6.RB,_IMM6:IALU1:short:iu,mu:SUBHppp imm +# OBSOLETE "subh%s r, r, " +# OBSOLETE do_subh_ppp(_SD, ppp, Ra, Rb, immHL); +# OBSOLETE _IALU1,11,ppp,10,6.RA,6.RB,_IMM32:IALU1:long:iu,mu:SUBHppp imm long +# OBSOLETE "subh%s r, r, " +# OBSOLETE do_subh_ppp(_SD, ppp, Ra, Rb, imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // TRAP +# OBSOLETE +# OBSOLETE address_word::function::do_trap:address_word trap_vector, address_word nia +# OBSOLETE /* Steal trap 31 for doing system calls */ +# OBSOLETE /* System calls are defined in libgloss/d30v/syscall.h. */ +# OBSOLETE if (trap_vector == EIT_VB + 0x20 + (31 << 3)) +# OBSOLETE { +# OBSOLETE enum { PARM1 = 2, PARM2, PARM3, PARM4, FUNC }; +# OBSOLETE if (GPR[FUNC] == 1) /* exit */ +# OBSOLETE { +# OBSOLETE sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, sim_exited, +# OBSOLETE GPR[PARM1]); +# OBSOLETE return -1; /* dummy */ +# OBSOLETE } +# OBSOLETE else +# OBSOLETE { +# OBSOLETE CB_SYSCALL syscall; +# OBSOLETE +# OBSOLETE CB_SYSCALL_INIT (&syscall); +# OBSOLETE syscall.arg1 = GPR[PARM1]; +# OBSOLETE syscall.arg2 = GPR[PARM2]; +# OBSOLETE syscall.arg3 = GPR[PARM3]; +# OBSOLETE syscall.arg4 = GPR[PARM4]; +# OBSOLETE syscall.func = GPR[FUNC]; +# OBSOLETE syscall.p1 = (PTR) SD; +# OBSOLETE syscall.read_mem = d30v_read_mem; +# OBSOLETE syscall.write_mem = d30v_write_mem; +# OBSOLETE +# OBSOLETE WRITE32_QUEUE (&GPR[PARM1], +# OBSOLETE ((cb_syscall (STATE_CALLBACK (SD), &syscall) +# OBSOLETE == CB_RC_OK) +# OBSOLETE ? syscall.result +# OBSOLETE : -syscall.errcode)); +# OBSOLETE return nia; +# OBSOLETE } +# OBSOLETE } +# OBSOLETE else if (TRACE_TRAP_P) +# OBSOLETE { +# OBSOLETE int reg, i; +# OBSOLETE sim_io_eprintf (sd, "\nTrap %ld:\n", (long) ((trap_vector - (EIT_VB + 0x20)) >> 3)); +# OBSOLETE for (reg = 0; reg < NR_GENERAL_PURPOSE_REGISTERS; reg += 8) +# OBSOLETE { +# OBSOLETE sim_io_eprintf (sd, "r%.2d - r%.2d: ", reg, reg+7); +# OBSOLETE for (i = 0; i < 8; i++) +# OBSOLETE sim_io_eprintf (sd, " 0x%.8lx", (long) GPR[reg+i]); +# OBSOLETE sim_io_eprintf (sd, "\n"); +# OBSOLETE } +# OBSOLETE +# OBSOLETE for (reg = 0; reg < 16; reg += 8) +# OBSOLETE { +# OBSOLETE sim_io_eprintf (sd, "cr%.2d - cr%.2d:", reg, reg+7); +# OBSOLETE for (i = 0; i < 8; i++) +# OBSOLETE sim_io_eprintf (sd, " 0x%.8lx", (long) CREG[reg+i]); +# OBSOLETE sim_io_eprintf (sd, "\n"); +# OBSOLETE } +# OBSOLETE +# OBSOLETE sim_io_eprintf (sd, "a0 - a1: "); +# OBSOLETE for (reg = 0; reg < NR_ACCUMULATORS; reg++) +# OBSOLETE sim_io_eprintf (sd, " 0x%.8lx 0x%.8lx", +# OBSOLETE (long)EXTRACTED64(ACC[reg], 0, 31), +# OBSOLETE (long)EXTRACTED64(ACC[reg], 32, 63)); +# OBSOLETE sim_io_eprintf (sd, "\n"); +# OBSOLETE +# OBSOLETE sim_io_eprintf (sd, "f0 - f7: "); +# OBSOLETE sim_io_eprintf (sd, " (f0) %d", (int) PSW_VAL(PSW_F0)); +# OBSOLETE sim_io_eprintf (sd, " (f1) %d", (int) PSW_VAL(PSW_F1)); +# OBSOLETE sim_io_eprintf (sd, " (f2) %d", (int) PSW_VAL(PSW_F2)); +# OBSOLETE sim_io_eprintf (sd, " (f3) %d", (int) PSW_VAL(PSW_F3)); +# OBSOLETE sim_io_eprintf (sd, " (s) %d", (int) PSW_VAL(PSW_S)); +# OBSOLETE sim_io_eprintf (sd, " (v) %d", (int) PSW_VAL(PSW_V)); +# OBSOLETE sim_io_eprintf (sd, " (va) %d", (int) PSW_VAL(PSW_VA)); +# OBSOLETE sim_io_eprintf (sd, " (c) %d\n", (int) PSW_VAL(PSW_C)); +# OBSOLETE +# OBSOLETE sim_io_eprintf (sd, "pswh: "); +# OBSOLETE sim_io_eprintf (sd, " (sm) %d", (int) PSW_VAL(PSW_SM)); +# OBSOLETE sim_io_eprintf (sd, " (ea) %d", (int) PSW_VAL(PSW_EA)); +# OBSOLETE sim_io_eprintf (sd, " (ie) %d", (int) PSW_VAL(PSW_IE)); +# OBSOLETE sim_io_eprintf (sd, " (rp) %d", (int) PSW_VAL(PSW_RP)); +# OBSOLETE sim_io_eprintf (sd, " (md) %d", (int) PSW_VAL(PSW_MD)); +# OBSOLETE +# OBSOLETE if (PSW_VAL(PSW_DB)) +# OBSOLETE sim_io_eprintf (sd, " (db) %d", (int) PSW_VAL(PSW_DB)); +# OBSOLETE +# OBSOLETE if (PSW_VAL(PSW_DS)) +# OBSOLETE sim_io_eprintf (sd, " (ds) %d", (int) PSW_VAL(PSW_DS)); +# OBSOLETE +# OBSOLETE sim_io_eprintf (sd, "\n"); +# OBSOLETE return nia; +# OBSOLETE } +# OBSOLETE else +# OBSOLETE { +# OBSOLETE if(PSW_VAL(PSW_RP) && RPT_E == cia) +# OBSOLETE { +# OBSOLETE WRITE32_QUEUE (&bPC, RPT_S); +# OBSOLETE if (RPT_C == 0) +# OBSOLETE PSW_SET (PSW_RP, 0); +# OBSOLETE } +# OBSOLETE else +# OBSOLETE WRITE32_QUEUE (&bPC, cia + 8); +# OBSOLETE DID_TRAP = 1; +# OBSOLETE return trap_vector; +# OBSOLETE } +# OBSOLETE +# OBSOLETE _BRA,01001,00,6.**,6.**,6.RC:BRA:short:mu:TRAP +# OBSOLETE "trap r" +# OBSOLETE nia = do_trap (_SD, EIT_VB + 0x20 + MASKED32(Rc, 24, 28), nia); +# OBSOLETE _BRA,01001,10,6.**,6.**,_IMM6:BRA:short:mu:TRAP imm +# OBSOLETE "trap " +# OBSOLETE nia = do_trap (_SD, EIT_VB + 0x20 + (imm_5 << 3), nia); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // XOR +# OBSOLETE +# OBSOLETE _LOGIC,11011,00,6.RA,6.RB,6.RC:LOGIC:short:iu,mu:XOR +# OBSOLETE "xor r, r, r" +# OBSOLETE WRITE32_QUEUE (Ra, Rb ^ Rc); +# OBSOLETE _LOGIC,11011,10,6.RA,6.RB,_IMM6:LOGIC:short:iu,mu:XOR imm +# OBSOLETE "xor r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb ^ imm); +# OBSOLETE _LOGIC,11011,10,6.RA,6.RB,_IMM32:LOGIC:long:iu,mu:XOR imm long +# OBSOLETE "xor r, r, " +# OBSOLETE WRITE32_QUEUE (Ra, Rb ^ imm); +# OBSOLETE +# OBSOLETE +# OBSOLETE +# OBSOLETE // XORFG +# OBSOLETE +# OBSOLETE _LOGIC,01011,00,***,3.FA,***,3.FB,***,3.FC:LOGIC:short:iu,mu:XORFG +# OBSOLETE "xorfg f, f, f" +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ PSW_FLAG_VAL(FC)); +# OBSOLETE _LOGIC,01011,10,***,3.FA,***,3.FB,_IMM6:LOGIC:short:iu,mu:XORFG imm +# OBSOLETE "xorfg f, f, " +# OBSOLETE PSW_FLAG_SET_QUEUE(FA, PSW_FLAG_VAL(FB) ^ (imm_6 & 1)); diff --git a/sim/d30v/dc-short b/sim/d30v/dc-short index 1451dfa..95887ec 100644 --- a/sim/d30v/dc-short +++ b/sim/d30v/dc-short @@ -1,22 +1,22 @@ -// -// Mitsubishi Electric Corp. D30V Simulator. -// Copyright (C) 1997, Free Software Foundation, Inc. -// Contributed by Cygnus Solutions Inc. -// -// This file is part of GDB, the GNU debugger. -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -// -switch: 4: 13: 4: 13 +# OBSOLETE // +# OBSOLETE // Mitsubishi Electric Corp. D30V Simulator. +# OBSOLETE // Copyright (C) 1997, Free Software Foundation, Inc. +# OBSOLETE // Contributed by Cygnus Solutions Inc. +# OBSOLETE // +# OBSOLETE // This file is part of GDB, the GNU debugger. +# OBSOLETE // +# OBSOLETE // This program is free software; you can redistribute it and/or modify +# OBSOLETE // it under the terms of the GNU General Public License as published by +# OBSOLETE // the Free Software Foundation; either version 2 of the License, or +# OBSOLETE // (at your option) any later version. +# OBSOLETE // +# OBSOLETE // This program is distributed in the hope that it will be useful, +# OBSOLETE // but WITHOUT ANY WARRANTY; without even the implied warranty of +# OBSOLETE // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# OBSOLETE // GNU General Public License for more details. +# OBSOLETE // +# OBSOLETE // You should have received a copy of the GNU General Public License +# OBSOLETE // along with this program; if not, write to the Free Software +# OBSOLETE // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# OBSOLETE // +# OBSOLETE switch: 4: 13: 4: 13 diff --git a/sim/d30v/engine.c b/sim/d30v/engine.c index 2bbaad1..0f4a025 100644 --- a/sim/d30v/engine.c +++ b/sim/d30v/engine.c @@ -1,496 +1,496 @@ -/* This file is part of the program psim. - - Copyright (C) 1994-1997, Andrew Cagney - Copyright (C) 1996, 1997, Free Software Foundation - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - - */ - - -#ifndef ENGINE_C -#define ENGINE_C - -#include "sim-main.h" - -#include -#include - -#ifdef HAVE_STDLIB_H -#include -#endif - -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif - -static void -do_stack_swap (SIM_DESC sd) -{ - sim_cpu *cpu = STATE_CPU (sd, 0); - unsigned new_sp = (PSW_VAL(PSW_SM) != 0); - if (cpu->regs.current_sp != new_sp) - { - cpu->regs.sp[cpu->regs.current_sp] = SP; - cpu->regs.current_sp = new_sp; - SP = cpu->regs.sp[cpu->regs.current_sp]; - } -} - -#if WITH_TRACE -/* Implement ALU tracing of 32-bit registers. */ -static void -trace_alu32 (SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - unsigned32 *ptr) -{ - unsigned32 value = *ptr; - - if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS]) - trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", - "Set register r%-2d = 0x%.8lx (%ld)", - ptr - &GPR[0], (long)value, (long)value); - - else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW) - trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", - "Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", - (ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"), - (long)value, - (value & (0x80000000 >> PSW_SM)) ? ", sm" : "", - (value & (0x80000000 >> PSW_EA)) ? ", ea" : "", - (value & (0x80000000 >> PSW_DB)) ? ", db" : "", - (value & (0x80000000 >> PSW_DS)) ? ", ds" : "", - (value & (0x80000000 >> PSW_IE)) ? ", ie" : "", - (value & (0x80000000 >> PSW_RP)) ? ", rp" : "", - (value & (0x80000000 >> PSW_MD)) ? ", md" : "", - (value & (0x80000000 >> PSW_F0)) ? ", f0" : "", - (value & (0x80000000 >> PSW_F1)) ? ", f1" : "", - (value & (0x80000000 >> PSW_F2)) ? ", f2" : "", - (value & (0x80000000 >> PSW_F3)) ? ", f3" : "", - (value & (0x80000000 >> PSW_S)) ? ", s" : "", - (value & (0x80000000 >> PSW_V)) ? ", v" : "", - (value & (0x80000000 >> PSW_VA)) ? ", va" : "", - (value & (0x80000000 >> PSW_C)) ? ", c" : ""); - - else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS]) - trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", - "Set register cr%d = 0x%.8lx (%ld)", - ptr - &CREG[0], (long)value, (long)value); -} - -/* Implement ALU tracing of 32-bit registers. */ -static void -trace_alu64 (SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - unsigned64 *ptr) -{ - unsigned64 value = *ptr; - - if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS]) - trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", - "Set register a%-2d = 0x%.8lx 0x%.8lx", - ptr - &ACC[0], - (unsigned long)(unsigned32)(value >> 32), - (unsigned long)(unsigned32)value); - -} -#endif - -/* Process all of the queued up writes in order now */ -void -unqueue_writes (SIM_DESC sd, - sim_cpu *cpu, - address_word cia) -{ - int i, num; - int did_psw = 0; - unsigned32 *psw_addr = &PSW; - - num = WRITE32_NUM; - for (i = 0; i < num; i++) - { - unsigned32 mask = WRITE32_MASK (i); - unsigned32 *ptr = WRITE32_PTR (i); - unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask); - int j; - - if (ptr == psw_addr) - { - /* If MU instruction was not a MVTSYS, resolve PSW - contention in favour of IU. */ - if(! STATE_CPU (sd, 0)->mvtsys_left_p) - { - /* Detect contention in parallel writes to the same PSW flags. - The hardware allows the updates from IU to prevail over - those from MU. */ - - unsigned32 flag_bits = - BIT32 (PSW_F0) | BIT32 (PSW_F1) | - BIT32 (PSW_F2) | BIT32 (PSW_F3) | - BIT32 (PSW_S) | BIT32 (PSW_V) | - BIT32 (PSW_VA) | BIT32 (PSW_C); - unsigned32 my_flag_bits = mask & flag_bits; - - for (j = i + 1; j < num; j++) - if (WRITE32_PTR (j) == psw_addr && /* write to PSW */ - WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */ - { - /* Recompute local mask & value, to suppress this - earlier write to the same flag bits. */ - - unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits); - - /* There is a special case for the VA (accumulated - overflow) flag, in that it is only included in the - second instruction's mask if the overflow - occurred. Yet the hardware still suppresses the - first instruction's update to VA. So we kludge - this by inferring PSW_V -> PSW_VA for the second - instruction. */ - - if (WRITE32_MASK (j) & BIT32 (PSW_V)) - { - new_mask &= ~BIT32 (PSW_VA); - } - - value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask); - } - } - - did_psw = 1; - } - - *ptr = value; - -#if WITH_TRACE - if (TRACE_ALU_P (cpu)) - trace_alu32 (sd, cpu, cia, ptr); -#endif - } - - num = WRITE64_NUM; - for (i = 0; i < num; i++) - { - unsigned64 *ptr = WRITE64_PTR (i); - *ptr = WRITE64_VALUE (i); - -#if WITH_TRACE - if (TRACE_ALU_P (cpu)) - trace_alu64 (sd, cpu, cia, ptr); -#endif - } - - WRITE32_NUM = 0; - WRITE64_NUM = 0; - - if (DID_TRAP == 1) /* ordinary trap */ - { - bPSW = PSW; - PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM)); - did_psw = 1; - } - else if (DID_TRAP == 2) /* debug trap */ - { - DPSW = PSW; - PSW &= BIT32 (PSW_DS); - PSW |= BIT32 (PSW_DS); - did_psw = 1; - } - DID_TRAP = 0; - - if (did_psw) - do_stack_swap (sd); -} - - -/* SIMULATE INSTRUCTIONS, various different ways of achieving the same - thing */ - -static address_word -do_long (SIM_DESC sd, - l_instruction_word instruction, - address_word cia) -{ - address_word nia = l_idecode_issue(sd, - instruction, - cia); - - unqueue_writes (sd, STATE_CPU (sd, 0), cia); - return nia; -} - -static address_word -do_2_short (SIM_DESC sd, - s_instruction_word insn1, - s_instruction_word insn2, - cpu_units unit, - address_word cia) -{ - address_word nia; - - /* run the first instruction */ - STATE_CPU (sd, 0)->unit = unit; - STATE_CPU (sd, 0)->left_kills_right_p = 0; - STATE_CPU (sd, 0)->mvtsys_left_p = 0; - nia = s_idecode_issue(sd, - insn1, - cia); - - unqueue_writes (sd, STATE_CPU (sd, 0), cia); - - /* Only do the second instruction if the PC has not changed */ - if ((nia == INVALID_INSTRUCTION_ADDRESS) && - (! STATE_CPU (sd, 0)->left_kills_right_p)) { - STATE_CPU (sd, 0)->unit = any_unit; - nia = s_idecode_issue (sd, - insn2, - cia); - - unqueue_writes (sd, STATE_CPU (sd, 0), cia); - } - - STATE_CPU (sd, 0)->left_kills_right_p = 0; - STATE_CPU (sd, 0)->mvtsys_left_p = 0; - return nia; -} - -static address_word -do_parallel (SIM_DESC sd, - s_instruction_word left_insn, - s_instruction_word right_insn, - address_word cia) -{ - address_word nia_left; - address_word nia_right; - address_word nia; - - /* run the first instruction */ - STATE_CPU (sd, 0)->unit = memory_unit; - STATE_CPU (sd, 0)->left_kills_right_p = 0; - STATE_CPU (sd, 0)->mvtsys_left_p = 0; - nia_left = s_idecode_issue(sd, - left_insn, - cia); - - /* run the second instruction */ - STATE_CPU (sd, 0)->unit = integer_unit; - nia_right = s_idecode_issue(sd, - right_insn, - cia); - - /* merge the PC's */ - if (nia_left == INVALID_INSTRUCTION_ADDRESS) { - if (nia_right == INVALID_INSTRUCTION_ADDRESS) - nia = INVALID_INSTRUCTION_ADDRESS; - else - nia = nia_right; - } - else { - if (nia_right == INVALID_INSTRUCTION_ADDRESS) - nia = nia_left; - else { - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps"); - nia = INVALID_INSTRUCTION_ADDRESS; - } - } - - unqueue_writes (sd, STATE_CPU (sd, 0), cia); - return nia; -} - - -typedef enum { - p_insn = 0, - long_insn = 3, - l_r_insn = 1, - r_l_insn = 2, -} instruction_types; - -STATIC_INLINE instruction_types -instruction_type(l_instruction_word insn) -{ - int fm0 = MASKED64(insn, 0, 0) != 0; - int fm1 = MASKED64(insn, 32, 32) != 0; - return ((fm0 << 1) | fm1); -} - - - -void -sim_engine_run (SIM_DESC sd, - int last_cpu_nr, - int nr_cpus, - int siggnal) -{ - while (1) - { - address_word cia = PC; - address_word nia; - l_instruction_word insn = IMEM(cia); - int rp_was_set; - int rpt_c_was_nonzero; - - /* Before executing the instruction, we need to test whether or - not RPT_C is greater than zero, and save that state for use - after executing the instruction. In particular, we need to - not care whether the instruction changes RPT_C itself. */ - - rpt_c_was_nonzero = (RPT_C > 0); - - /* Before executing the instruction, we need to check to see if - we have to decrement RPT_C, the repeat count register. Do this - if PC == RPT_E, but only if we are in an active repeat block. */ - - if (PC == RPT_E && - (RPT_C > 0 || PSW_VAL (PSW_RP) != 0)) - { - RPT_C --; - } - - /* Now execute the instruction at PC */ - - switch (instruction_type (insn)) - { - case long_insn: - nia = do_long (sd, insn, cia); - break; - case r_l_insn: - /* L <- R */ - nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia); - break; - case l_r_insn: - /* L -> R */ - nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia); - break; - case p_insn: - nia = do_parallel (sd, insn >> 32, insn, cia); - break; - default: - sim_engine_abort (sd, STATE_CPU (sd, 0), cia, - "internal error - engine_run_until_stop - bad switch"); - nia = -1; - } - - if (TRACE_ACTION) - { - if (TRACE_ACTION & TRACE_ACTION_CALL) - call_occurred (sd, STATE_CPU (sd, 0), cia, nia); - - if (TRACE_ACTION & TRACE_ACTION_RETURN) - return_occurred (sd, STATE_CPU (sd, 0), cia, nia); - - TRACE_ACTION = 0; - } - - /* Check now to see if we need to reset the RP bit in the PSW. - There are three conditions for this, the RP bit is already - set (just a speed optimization), the instruction we just - executed is the last instruction in the loop, and the repeat - count is currently zero. */ - - rp_was_set = PSW_VAL (PSW_RP); - if (rp_was_set && (PC == RPT_E) && RPT_C == 0) - { - PSW_SET (PSW_RP, 0); - } - - /* Now update the PC. If we just executed a jump instruction, - that takes precedence over everything else. Next comes - branching back to RPT_S as a result of a loop. Finally, the - default is to simply advance to the next inline - instruction. */ - - if (nia != INVALID_INSTRUCTION_ADDRESS) - { - PC = nia; - } - else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E)) - { - PC = RPT_S; - } - else - { - PC = cia + 8; - } - - /* Check for DDBT (debugger debug trap) condition. Do this after - the repeat block checks so the excursion to the trap handler does - not alter looping state. */ - - if (cia == IBA && PSW_VAL (PSW_DB)) - { - DPC = PC; - PSW_SET (PSW_EA, 1); - DPSW = PSW; - /* clear all bits in PSW except SM */ - PSW &= BIT32 (PSW_SM); - /* add DS bit */ - PSW |= BIT32 (PSW_DS); - /* dispatch to DDBT handler */ - PC = 0xfffff128; /* debugger_debug_trap_address */ - } - - /* process any events */ - /* FIXME - should L->R or L<-R insns count as two cycles? */ - if (sim_events_tick (sd)) - { - sim_events_process (sd); - } - } -} - - -/* d30v external interrupt handler. - - Note: This should be replaced by a proper interrupt delivery - mechanism. This interrupt mechanism discards later interrupts if - an earlier interrupt hasn't been delivered. - - Note: This interrupt mechanism does not reset its self when the - simulator is re-opened. */ - -void -d30v_interrupt_event (SIM_DESC sd, - void *data) -{ - if (PSW_VAL (PSW_IE)) - /* interrupts not masked */ - { - /* scrub any pending interrupt */ - if (sd->pending_interrupt != NULL) - sim_events_deschedule (sd, sd->pending_interrupt); - /* deliver */ - bPSW = PSW; - bPC = PC; - PSW = 0; - PC = 0xfffff138; /* external interrupt */ - do_stack_swap (sd); - } - else if (sd->pending_interrupt == NULL) - /* interrupts masked and no interrupt pending */ - { - sd->pending_interrupt = sim_events_schedule (sd, 1, - d30v_interrupt_event, - data); - } -} - -#endif +/* OBSOLETE /* This file is part of the program psim. */ +/* OBSOLETE */ +/* OBSOLETE Copyright (C) 1994-1997, Andrew Cagney */ +/* OBSOLETE Copyright (C) 1996, 1997, Free Software Foundation */ +/* OBSOLETE */ +/* OBSOLETE This program is free software; you can redistribute it and/or modify */ +/* OBSOLETE it under the terms of the GNU General Public License as published by */ +/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */ +/* OBSOLETE (at your option) any later version. */ +/* OBSOLETE */ +/* OBSOLETE This program is distributed in the hope that it will be useful, */ +/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* OBSOLETE GNU General Public License for more details. */ +/* OBSOLETE */ +/* OBSOLETE You should have received a copy of the GNU General Public License */ +/* OBSOLETE along with this program; if not, write to the Free Software */ +/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* OBSOLETE */ +/* OBSOLETE */ */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #ifndef ENGINE_C */ +/* OBSOLETE #define ENGINE_C */ +/* OBSOLETE */ +/* OBSOLETE #include "sim-main.h" */ +/* OBSOLETE */ +/* OBSOLETE #include */ +/* OBSOLETE #include */ +/* OBSOLETE */ +/* OBSOLETE #ifdef HAVE_STDLIB_H */ +/* OBSOLETE #include */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE #ifdef HAVE_STRING_H */ +/* OBSOLETE #include */ +/* OBSOLETE #else */ +/* OBSOLETE #ifdef HAVE_STRINGS_H */ +/* OBSOLETE #include */ +/* OBSOLETE #endif */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE static void */ +/* OBSOLETE do_stack_swap (SIM_DESC sd) */ +/* OBSOLETE { */ +/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */ +/* OBSOLETE unsigned new_sp = (PSW_VAL(PSW_SM) != 0); */ +/* OBSOLETE if (cpu->regs.current_sp != new_sp) */ +/* OBSOLETE { */ +/* OBSOLETE cpu->regs.sp[cpu->regs.current_sp] = SP; */ +/* OBSOLETE cpu->regs.current_sp = new_sp; */ +/* OBSOLETE SP = cpu->regs.sp[cpu->regs.current_sp]; */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE #if WITH_TRACE */ +/* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */ +/* OBSOLETE static void */ +/* OBSOLETE trace_alu32 (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE unsigned32 *ptr) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned32 value = *ptr; */ +/* OBSOLETE */ +/* OBSOLETE if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS]) */ +/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ +/* OBSOLETE "Set register r%-2d = 0x%.8lx (%ld)", */ +/* OBSOLETE ptr - &GPR[0], (long)value, (long)value); */ +/* OBSOLETE */ +/* OBSOLETE else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW) */ +/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ +/* OBSOLETE "Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", */ +/* OBSOLETE (ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"), */ +/* OBSOLETE (long)value, */ +/* OBSOLETE (value & (0x80000000 >> PSW_SM)) ? ", sm" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_EA)) ? ", ea" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_DB)) ? ", db" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_DS)) ? ", ds" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_IE)) ? ", ie" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_RP)) ? ", rp" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_MD)) ? ", md" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_F0)) ? ", f0" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_F1)) ? ", f1" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_F2)) ? ", f2" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_F3)) ? ", f3" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_S)) ? ", s" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_V)) ? ", v" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_VA)) ? ", va" : "", */ +/* OBSOLETE (value & (0x80000000 >> PSW_C)) ? ", c" : ""); */ +/* OBSOLETE */ +/* OBSOLETE else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS]) */ +/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ +/* OBSOLETE "Set register cr%d = 0x%.8lx (%ld)", */ +/* OBSOLETE ptr - &CREG[0], (long)value, (long)value); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */ +/* OBSOLETE static void */ +/* OBSOLETE trace_alu64 (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia, */ +/* OBSOLETE unsigned64 *ptr) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned64 value = *ptr; */ +/* OBSOLETE */ +/* OBSOLETE if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS]) */ +/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */ +/* OBSOLETE "Set register a%-2d = 0x%.8lx 0x%.8lx", */ +/* OBSOLETE ptr - &ACC[0], */ +/* OBSOLETE (unsigned long)(unsigned32)(value >> 32), */ +/* OBSOLETE (unsigned long)(unsigned32)value); */ +/* OBSOLETE */ +/* OBSOLETE } */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE /* Process all of the queued up writes in order now */ */ +/* OBSOLETE void */ +/* OBSOLETE unqueue_writes (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE address_word cia) */ +/* OBSOLETE { */ +/* OBSOLETE int i, num; */ +/* OBSOLETE int did_psw = 0; */ +/* OBSOLETE unsigned32 *psw_addr = &PSW; */ +/* OBSOLETE */ +/* OBSOLETE num = WRITE32_NUM; */ +/* OBSOLETE for (i = 0; i < num; i++) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned32 mask = WRITE32_MASK (i); */ +/* OBSOLETE unsigned32 *ptr = WRITE32_PTR (i); */ +/* OBSOLETE unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask); */ +/* OBSOLETE int j; */ +/* OBSOLETE */ +/* OBSOLETE if (ptr == psw_addr) */ +/* OBSOLETE { */ +/* OBSOLETE /* If MU instruction was not a MVTSYS, resolve PSW */ +/* OBSOLETE contention in favour of IU. */ */ +/* OBSOLETE if(! STATE_CPU (sd, 0)->mvtsys_left_p) */ +/* OBSOLETE { */ +/* OBSOLETE /* Detect contention in parallel writes to the same PSW flags. */ +/* OBSOLETE The hardware allows the updates from IU to prevail over */ +/* OBSOLETE those from MU. */ */ +/* OBSOLETE */ +/* OBSOLETE unsigned32 flag_bits = */ +/* OBSOLETE BIT32 (PSW_F0) | BIT32 (PSW_F1) | */ +/* OBSOLETE BIT32 (PSW_F2) | BIT32 (PSW_F3) | */ +/* OBSOLETE BIT32 (PSW_S) | BIT32 (PSW_V) | */ +/* OBSOLETE BIT32 (PSW_VA) | BIT32 (PSW_C); */ +/* OBSOLETE unsigned32 my_flag_bits = mask & flag_bits; */ +/* OBSOLETE */ +/* OBSOLETE for (j = i + 1; j < num; j++) */ +/* OBSOLETE if (WRITE32_PTR (j) == psw_addr && /* write to PSW */ */ +/* OBSOLETE WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */ */ +/* OBSOLETE { */ +/* OBSOLETE /* Recompute local mask & value, to suppress this */ +/* OBSOLETE earlier write to the same flag bits. */ */ +/* OBSOLETE */ +/* OBSOLETE unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits); */ +/* OBSOLETE */ +/* OBSOLETE /* There is a special case for the VA (accumulated */ +/* OBSOLETE overflow) flag, in that it is only included in the */ +/* OBSOLETE second instruction's mask if the overflow */ +/* OBSOLETE occurred. Yet the hardware still suppresses the */ +/* OBSOLETE first instruction's update to VA. So we kludge */ +/* OBSOLETE this by inferring PSW_V -> PSW_VA for the second */ +/* OBSOLETE instruction. */ */ +/* OBSOLETE */ +/* OBSOLETE if (WRITE32_MASK (j) & BIT32 (PSW_V)) */ +/* OBSOLETE { */ +/* OBSOLETE new_mask &= ~BIT32 (PSW_VA); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask); */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE did_psw = 1; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE *ptr = value; */ +/* OBSOLETE */ +/* OBSOLETE #if WITH_TRACE */ +/* OBSOLETE if (TRACE_ALU_P (cpu)) */ +/* OBSOLETE trace_alu32 (sd, cpu, cia, ptr); */ +/* OBSOLETE #endif */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE num = WRITE64_NUM; */ +/* OBSOLETE for (i = 0; i < num; i++) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned64 *ptr = WRITE64_PTR (i); */ +/* OBSOLETE *ptr = WRITE64_VALUE (i); */ +/* OBSOLETE */ +/* OBSOLETE #if WITH_TRACE */ +/* OBSOLETE if (TRACE_ALU_P (cpu)) */ +/* OBSOLETE trace_alu64 (sd, cpu, cia, ptr); */ +/* OBSOLETE #endif */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE WRITE32_NUM = 0; */ +/* OBSOLETE WRITE64_NUM = 0; */ +/* OBSOLETE */ +/* OBSOLETE if (DID_TRAP == 1) /* ordinary trap */ */ +/* OBSOLETE { */ +/* OBSOLETE bPSW = PSW; */ +/* OBSOLETE PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM)); */ +/* OBSOLETE did_psw = 1; */ +/* OBSOLETE } */ +/* OBSOLETE else if (DID_TRAP == 2) /* debug trap */ */ +/* OBSOLETE { */ +/* OBSOLETE DPSW = PSW; */ +/* OBSOLETE PSW &= BIT32 (PSW_DS); */ +/* OBSOLETE PSW |= BIT32 (PSW_DS); */ +/* OBSOLETE did_psw = 1; */ +/* OBSOLETE } */ +/* OBSOLETE DID_TRAP = 0; */ +/* OBSOLETE */ +/* OBSOLETE if (did_psw) */ +/* OBSOLETE do_stack_swap (sd); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE /* SIMULATE INSTRUCTIONS, various different ways of achieving the same */ +/* OBSOLETE thing */ */ +/* OBSOLETE */ +/* OBSOLETE static address_word */ +/* OBSOLETE do_long (SIM_DESC sd, */ +/* OBSOLETE l_instruction_word instruction, */ +/* OBSOLETE address_word cia) */ +/* OBSOLETE { */ +/* OBSOLETE address_word nia = l_idecode_issue(sd, */ +/* OBSOLETE instruction, */ +/* OBSOLETE cia); */ +/* OBSOLETE */ +/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ +/* OBSOLETE return nia; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE static address_word */ +/* OBSOLETE do_2_short (SIM_DESC sd, */ +/* OBSOLETE s_instruction_word insn1, */ +/* OBSOLETE s_instruction_word insn2, */ +/* OBSOLETE cpu_units unit, */ +/* OBSOLETE address_word cia) */ +/* OBSOLETE { */ +/* OBSOLETE address_word nia; */ +/* OBSOLETE */ +/* OBSOLETE /* run the first instruction */ */ +/* OBSOLETE STATE_CPU (sd, 0)->unit = unit; */ +/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */ +/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */ +/* OBSOLETE nia = s_idecode_issue(sd, */ +/* OBSOLETE insn1, */ +/* OBSOLETE cia); */ +/* OBSOLETE */ +/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ +/* OBSOLETE */ +/* OBSOLETE /* Only do the second instruction if the PC has not changed */ */ +/* OBSOLETE if ((nia == INVALID_INSTRUCTION_ADDRESS) && */ +/* OBSOLETE (! STATE_CPU (sd, 0)->left_kills_right_p)) { */ +/* OBSOLETE STATE_CPU (sd, 0)->unit = any_unit; */ +/* OBSOLETE nia = s_idecode_issue (sd, */ +/* OBSOLETE insn2, */ +/* OBSOLETE cia); */ +/* OBSOLETE */ +/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */ +/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */ +/* OBSOLETE return nia; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE static address_word */ +/* OBSOLETE do_parallel (SIM_DESC sd, */ +/* OBSOLETE s_instruction_word left_insn, */ +/* OBSOLETE s_instruction_word right_insn, */ +/* OBSOLETE address_word cia) */ +/* OBSOLETE { */ +/* OBSOLETE address_word nia_left; */ +/* OBSOLETE address_word nia_right; */ +/* OBSOLETE address_word nia; */ +/* OBSOLETE */ +/* OBSOLETE /* run the first instruction */ */ +/* OBSOLETE STATE_CPU (sd, 0)->unit = memory_unit; */ +/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */ +/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */ +/* OBSOLETE nia_left = s_idecode_issue(sd, */ +/* OBSOLETE left_insn, */ +/* OBSOLETE cia); */ +/* OBSOLETE */ +/* OBSOLETE /* run the second instruction */ */ +/* OBSOLETE STATE_CPU (sd, 0)->unit = integer_unit; */ +/* OBSOLETE nia_right = s_idecode_issue(sd, */ +/* OBSOLETE right_insn, */ +/* OBSOLETE cia); */ +/* OBSOLETE */ +/* OBSOLETE /* merge the PC's */ */ +/* OBSOLETE if (nia_left == INVALID_INSTRUCTION_ADDRESS) { */ +/* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */ +/* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */ +/* OBSOLETE else */ +/* OBSOLETE nia = nia_right; */ +/* OBSOLETE } */ +/* OBSOLETE else { */ +/* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */ +/* OBSOLETE nia = nia_left; */ +/* OBSOLETE else { */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps"); */ +/* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */ +/* OBSOLETE return nia; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE typedef enum { */ +/* OBSOLETE p_insn = 0, */ +/* OBSOLETE long_insn = 3, */ +/* OBSOLETE l_r_insn = 1, */ +/* OBSOLETE r_l_insn = 2, */ +/* OBSOLETE } instruction_types; */ +/* OBSOLETE */ +/* OBSOLETE STATIC_INLINE instruction_types */ +/* OBSOLETE instruction_type(l_instruction_word insn) */ +/* OBSOLETE { */ +/* OBSOLETE int fm0 = MASKED64(insn, 0, 0) != 0; */ +/* OBSOLETE int fm1 = MASKED64(insn, 32, 32) != 0; */ +/* OBSOLETE return ((fm0 << 1) | fm1); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE void */ +/* OBSOLETE sim_engine_run (SIM_DESC sd, */ +/* OBSOLETE int last_cpu_nr, */ +/* OBSOLETE int nr_cpus, */ +/* OBSOLETE int siggnal) */ +/* OBSOLETE { */ +/* OBSOLETE while (1) */ +/* OBSOLETE { */ +/* OBSOLETE address_word cia = PC; */ +/* OBSOLETE address_word nia; */ +/* OBSOLETE l_instruction_word insn = IMEM(cia); */ +/* OBSOLETE int rp_was_set; */ +/* OBSOLETE int rpt_c_was_nonzero; */ +/* OBSOLETE */ +/* OBSOLETE /* Before executing the instruction, we need to test whether or */ +/* OBSOLETE not RPT_C is greater than zero, and save that state for use */ +/* OBSOLETE after executing the instruction. In particular, we need to */ +/* OBSOLETE not care whether the instruction changes RPT_C itself. */ */ +/* OBSOLETE */ +/* OBSOLETE rpt_c_was_nonzero = (RPT_C > 0); */ +/* OBSOLETE */ +/* OBSOLETE /* Before executing the instruction, we need to check to see if */ +/* OBSOLETE we have to decrement RPT_C, the repeat count register. Do this */ +/* OBSOLETE if PC == RPT_E, but only if we are in an active repeat block. */ */ +/* OBSOLETE */ +/* OBSOLETE if (PC == RPT_E && */ +/* OBSOLETE (RPT_C > 0 || PSW_VAL (PSW_RP) != 0)) */ +/* OBSOLETE { */ +/* OBSOLETE RPT_C --; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* Now execute the instruction at PC */ */ +/* OBSOLETE */ +/* OBSOLETE switch (instruction_type (insn)) */ +/* OBSOLETE { */ +/* OBSOLETE case long_insn: */ +/* OBSOLETE nia = do_long (sd, insn, cia); */ +/* OBSOLETE break; */ +/* OBSOLETE case r_l_insn: */ +/* OBSOLETE /* L <- R */ */ +/* OBSOLETE nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia); */ +/* OBSOLETE break; */ +/* OBSOLETE case l_r_insn: */ +/* OBSOLETE /* L -> R */ */ +/* OBSOLETE nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia); */ +/* OBSOLETE break; */ +/* OBSOLETE case p_insn: */ +/* OBSOLETE nia = do_parallel (sd, insn >> 32, insn, cia); */ +/* OBSOLETE break; */ +/* OBSOLETE default: */ +/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */ +/* OBSOLETE "internal error - engine_run_until_stop - bad switch"); */ +/* OBSOLETE nia = -1; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE if (TRACE_ACTION) */ +/* OBSOLETE { */ +/* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_CALL) */ +/* OBSOLETE call_occurred (sd, STATE_CPU (sd, 0), cia, nia); */ +/* OBSOLETE */ +/* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_RETURN) */ +/* OBSOLETE return_occurred (sd, STATE_CPU (sd, 0), cia, nia); */ +/* OBSOLETE */ +/* OBSOLETE TRACE_ACTION = 0; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* Check now to see if we need to reset the RP bit in the PSW. */ +/* OBSOLETE There are three conditions for this, the RP bit is already */ +/* OBSOLETE set (just a speed optimization), the instruction we just */ +/* OBSOLETE executed is the last instruction in the loop, and the repeat */ +/* OBSOLETE count is currently zero. */ */ +/* OBSOLETE */ +/* OBSOLETE rp_was_set = PSW_VAL (PSW_RP); */ +/* OBSOLETE if (rp_was_set && (PC == RPT_E) && RPT_C == 0) */ +/* OBSOLETE { */ +/* OBSOLETE PSW_SET (PSW_RP, 0); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* Now update the PC. If we just executed a jump instruction, */ +/* OBSOLETE that takes precedence over everything else. Next comes */ +/* OBSOLETE branching back to RPT_S as a result of a loop. Finally, the */ +/* OBSOLETE default is to simply advance to the next inline */ +/* OBSOLETE instruction. */ */ +/* OBSOLETE */ +/* OBSOLETE if (nia != INVALID_INSTRUCTION_ADDRESS) */ +/* OBSOLETE { */ +/* OBSOLETE PC = nia; */ +/* OBSOLETE } */ +/* OBSOLETE else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E)) */ +/* OBSOLETE { */ +/* OBSOLETE PC = RPT_S; */ +/* OBSOLETE } */ +/* OBSOLETE else */ +/* OBSOLETE { */ +/* OBSOLETE PC = cia + 8; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* Check for DDBT (debugger debug trap) condition. Do this after */ +/* OBSOLETE the repeat block checks so the excursion to the trap handler does */ +/* OBSOLETE not alter looping state. */ */ +/* OBSOLETE */ +/* OBSOLETE if (cia == IBA && PSW_VAL (PSW_DB)) */ +/* OBSOLETE { */ +/* OBSOLETE DPC = PC; */ +/* OBSOLETE PSW_SET (PSW_EA, 1); */ +/* OBSOLETE DPSW = PSW; */ +/* OBSOLETE /* clear all bits in PSW except SM */ */ +/* OBSOLETE PSW &= BIT32 (PSW_SM); */ +/* OBSOLETE /* add DS bit */ */ +/* OBSOLETE PSW |= BIT32 (PSW_DS); */ +/* OBSOLETE /* dispatch to DDBT handler */ */ +/* OBSOLETE PC = 0xfffff128; /* debugger_debug_trap_address */ */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* process any events */ */ +/* OBSOLETE /* FIXME - should L->R or L<-R insns count as two cycles? */ */ +/* OBSOLETE if (sim_events_tick (sd)) */ +/* OBSOLETE { */ +/* OBSOLETE sim_events_process (sd); */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE /* d30v external interrupt handler. */ +/* OBSOLETE */ +/* OBSOLETE Note: This should be replaced by a proper interrupt delivery */ +/* OBSOLETE mechanism. This interrupt mechanism discards later interrupts if */ +/* OBSOLETE an earlier interrupt hasn't been delivered. */ +/* OBSOLETE */ +/* OBSOLETE Note: This interrupt mechanism does not reset its self when the */ +/* OBSOLETE simulator is re-opened. */ */ +/* OBSOLETE */ +/* OBSOLETE void */ +/* OBSOLETE d30v_interrupt_event (SIM_DESC sd, */ +/* OBSOLETE void *data) */ +/* OBSOLETE { */ +/* OBSOLETE if (PSW_VAL (PSW_IE)) */ +/* OBSOLETE /* interrupts not masked */ */ +/* OBSOLETE { */ +/* OBSOLETE /* scrub any pending interrupt */ */ +/* OBSOLETE if (sd->pending_interrupt != NULL) */ +/* OBSOLETE sim_events_deschedule (sd, sd->pending_interrupt); */ +/* OBSOLETE /* deliver */ */ +/* OBSOLETE bPSW = PSW; */ +/* OBSOLETE bPC = PC; */ +/* OBSOLETE PSW = 0; */ +/* OBSOLETE PC = 0xfffff138; /* external interrupt */ */ +/* OBSOLETE do_stack_swap (sd); */ +/* OBSOLETE } */ +/* OBSOLETE else if (sd->pending_interrupt == NULL) */ +/* OBSOLETE /* interrupts masked and no interrupt pending */ */ +/* OBSOLETE { */ +/* OBSOLETE sd->pending_interrupt = sim_events_schedule (sd, 1, */ +/* OBSOLETE d30v_interrupt_event, */ +/* OBSOLETE data); */ +/* OBSOLETE } */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE #endif */ diff --git a/sim/d30v/ic-d30v b/sim/d30v/ic-d30v index 50a184f..bdf7ea2 100644 --- a/sim/d30v/ic-d30v +++ b/sim/d30v/ic-d30v @@ -1,80 +1,80 @@ -# Instruction cache rules -# -# This file is part of the program psim. -# -# Copyright (C) 1994-1995, Andrew Cagney -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -# -compute:RA:RA:: -compute:RA:Ra:signed32 *:(&GPR[RA]) -compute:RA:RaH:signed16 *:AH2_4(Ra) -compute:RA:RaL:signed16 *:AL2_4(Ra) -compute:RA:val_Ra:signed32:(RA == 0 ? 0 : GPR[RA]) -# -compute:RB:RB:: -compute:RB:Rb:signed32:(RB == 0 ? 0 : GPR[RB]) -compute:RB:RbU:unsigned32:(RB == 0 ? 0 : GPR[RB]) -compute:RB:RbH:signed16:VH2_4(Rb) -compute:RB:RbL:signed16:VL2_4(Rb) -compute:RB:RbHU:unsigned16:VH2_4(Rb) -compute:RB:RbLU:unsigned16:VL2_4(Rb) -# -compute:RC:RC:: -compute:RC:Rc:signed32:(RC == 0 ? 0 : GPR[RC]) -compute:RC:RcU:unsigned32:(RC == 0 ? 0 : GPR[RC]) -compute:RC:RcH:signed16:VH2_4(Rc) -compute:RC:RcL:signed16:VL2_4(Rc) -# -# -compute:IMM_6S:IMM_6S:: -compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6) -# NB - for short imm[HL] are the same value -compute:IMM_6S:immHL:signed32:((imm << 16) | MASKED32(imm, 16, 31)) -compute:IMM_6S:immH:signed32:imm -compute:IMM_6S:immL:signed32:imm -compute:IMM_6S:imm_6:signed32:IMM_6S -compute:IMM_6S:imm_5:signed32:LSMASKED32(IMM_6S, 4, 0) -compute:IMM_6S:imm_6u:unsigned32:(IMM_6S & 0x3f) -# -compute:RC:pcdisp:signed32:(Rc & ~0x7) -compute:RC:pcaddr:signed32:pcdisp -# -compute:IMM_18S:IMM_18S:: -compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3) -compute:IMM_18S:pcaddr:signed32:pcdisp -compute:IMM_12S:IMM_12S:: -compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3) -compute:IMM_12S:pcaddr:signed32:pcdisp -# -compute:IMM_8L:IMM_8L:: -compute:IMM_18L:IMM_18L:: -compute:IMM_6L:IMM_6L:: -compute:IMM_6L:imm:signed32:((((IMM_6L << 8) | IMM_8L) << 18) | IMM_18L) -compute:IMM_6L:immHL:signed32:imm -compute:IMM_6L:immH:signed32:EXTRACTED32(imm, 0, 15) -compute:IMM_6L:immL:signed32:EXTRACTED32(imm, 16, 31) -compute:IMM_6L:pcdisp:signed32:(imm & ~0x7) -compute:IMM_6L:pcaddr:signed32:pcdisp -# -# -compute:SRC_6:SRC_6:: -compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6]) -# -# -compute:AA:AA:: -compute:AA:Aa:unsigned64*:((CPU)->regs.accumulator + AA) -compute:AB:AB:: -compute:AB:Ab:unsigned64*:((CPU)->regs.accumulator + AB) +# OBSOLETE # Instruction cache rules +# OBSOLETE # +# OBSOLETE # This file is part of the program psim. +# OBSOLETE # +# OBSOLETE # Copyright (C) 1994-1995, Andrew Cagney +# OBSOLETE # +# OBSOLETE # This program is free software; you can redistribute it and/or modify +# OBSOLETE # it under the terms of the GNU General Public License as published by +# OBSOLETE # the Free Software Foundation; either version 2 of the License, or +# OBSOLETE # (at your option) any later version. +# OBSOLETE # +# OBSOLETE # This program is distributed in the hope that it will be useful, +# OBSOLETE # but WITHOUT ANY WARRANTY; without even the implied warranty of +# OBSOLETE # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# OBSOLETE # GNU General Public License for more details. +# OBSOLETE # +# OBSOLETE # You should have received a copy of the GNU General Public License +# OBSOLETE # along with this program; if not, write to the Free Software +# OBSOLETE # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# OBSOLETE # +# OBSOLETE compute:RA:RA:: +# OBSOLETE compute:RA:Ra:signed32 *:(&GPR[RA]) +# OBSOLETE compute:RA:RaH:signed16 *:AH2_4(Ra) +# OBSOLETE compute:RA:RaL:signed16 *:AL2_4(Ra) +# OBSOLETE compute:RA:val_Ra:signed32:(RA == 0 ? 0 : GPR[RA]) +# OBSOLETE # +# OBSOLETE compute:RB:RB:: +# OBSOLETE compute:RB:Rb:signed32:(RB == 0 ? 0 : GPR[RB]) +# OBSOLETE compute:RB:RbU:unsigned32:(RB == 0 ? 0 : GPR[RB]) +# OBSOLETE compute:RB:RbH:signed16:VH2_4(Rb) +# OBSOLETE compute:RB:RbL:signed16:VL2_4(Rb) +# OBSOLETE compute:RB:RbHU:unsigned16:VH2_4(Rb) +# OBSOLETE compute:RB:RbLU:unsigned16:VL2_4(Rb) +# OBSOLETE # +# OBSOLETE compute:RC:RC:: +# OBSOLETE compute:RC:Rc:signed32:(RC == 0 ? 0 : GPR[RC]) +# OBSOLETE compute:RC:RcU:unsigned32:(RC == 0 ? 0 : GPR[RC]) +# OBSOLETE compute:RC:RcH:signed16:VH2_4(Rc) +# OBSOLETE compute:RC:RcL:signed16:VL2_4(Rc) +# OBSOLETE # +# OBSOLETE # +# OBSOLETE compute:IMM_6S:IMM_6S:: +# OBSOLETE compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6) +# OBSOLETE # NB - for short imm[HL] are the same value +# OBSOLETE compute:IMM_6S:immHL:signed32:((imm << 16) | MASKED32(imm, 16, 31)) +# OBSOLETE compute:IMM_6S:immH:signed32:imm +# OBSOLETE compute:IMM_6S:immL:signed32:imm +# OBSOLETE compute:IMM_6S:imm_6:signed32:IMM_6S +# OBSOLETE compute:IMM_6S:imm_5:signed32:LSMASKED32(IMM_6S, 4, 0) +# OBSOLETE compute:IMM_6S:imm_6u:unsigned32:(IMM_6S & 0x3f) +# OBSOLETE # +# OBSOLETE compute:RC:pcdisp:signed32:(Rc & ~0x7) +# OBSOLETE compute:RC:pcaddr:signed32:pcdisp +# OBSOLETE # +# OBSOLETE compute:IMM_18S:IMM_18S:: +# OBSOLETE compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3) +# OBSOLETE compute:IMM_18S:pcaddr:signed32:pcdisp +# OBSOLETE compute:IMM_12S:IMM_12S:: +# OBSOLETE compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3) +# OBSOLETE compute:IMM_12S:pcaddr:signed32:pcdisp +# OBSOLETE # +# OBSOLETE compute:IMM_8L:IMM_8L:: +# OBSOLETE compute:IMM_18L:IMM_18L:: +# OBSOLETE compute:IMM_6L:IMM_6L:: +# OBSOLETE compute:IMM_6L:imm:signed32:((((IMM_6L << 8) | IMM_8L) << 18) | IMM_18L) +# OBSOLETE compute:IMM_6L:immHL:signed32:imm +# OBSOLETE compute:IMM_6L:immH:signed32:EXTRACTED32(imm, 0, 15) +# OBSOLETE compute:IMM_6L:immL:signed32:EXTRACTED32(imm, 16, 31) +# OBSOLETE compute:IMM_6L:pcdisp:signed32:(imm & ~0x7) +# OBSOLETE compute:IMM_6L:pcaddr:signed32:pcdisp +# OBSOLETE # +# OBSOLETE # +# OBSOLETE compute:SRC_6:SRC_6:: +# OBSOLETE compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6]) +# OBSOLETE # +# OBSOLETE # +# OBSOLETE compute:AA:AA:: +# OBSOLETE compute:AA:Aa:unsigned64*:((CPU)->regs.accumulator + AA) +# OBSOLETE compute:AB:AB:: +# OBSOLETE compute:AB:Ab:unsigned64*:((CPU)->regs.accumulator + AB) diff --git a/sim/d30v/sim-calls.c b/sim/d30v/sim-calls.c index d319529..9384376 100644 --- a/sim/d30v/sim-calls.c +++ b/sim/d30v/sim-calls.c @@ -1,364 +1,364 @@ -/* This file is part of the program psim. - - Copyright (C) 1994-1996, Andrew Cagney - Copyright (C) 1997, Free Software Foundation - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - - */ - - -#include -#include - -#include "sim-main.h" -#include "sim-options.h" - -#include "bfd.h" -#include "sim-utils.h" - -#ifdef HAVE_STDLIB_H -#include -#endif - -static unsigned long extmem_size = 1024*1024*8; /* 8 meg is the maximum listed in the arch. manual */ - -static const char * get_insn_name (sim_cpu *, int); - -#define SIM_ADDR unsigned - - -#define OPTION_TRACE_CALL 200 -#define OPTION_TRACE_TRAPDUMP 201 -#define OPTION_EXTMEM_SIZE 202 - -static SIM_RC -d30v_option_handler (SIM_DESC sd, - sim_cpu *cpu, - int opt, - char *arg, - int command_p) -{ - char *suffix; - - switch (opt) - { - default: - break; - - case OPTION_TRACE_CALL: - if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0) - TRACE_CALL_P = 1; - else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0) - TRACE_CALL_P = 0; - else - { - sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg); - return SIM_RC_FAIL; - } - return SIM_RC_OK; - - case OPTION_TRACE_TRAPDUMP: - if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0) - TRACE_TRAP_P = 1; - else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0) - TRACE_TRAP_P = 0; - else - { - sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg); - return SIM_RC_FAIL; - } - return SIM_RC_OK; - - case OPTION_EXTMEM_SIZE: - if (arg == NULL || !isdigit (*arg)) - { - sim_io_eprintf (sd, "Invalid memory size `%s'", arg); - return SIM_RC_FAIL; - } - - suffix = arg; - extmem_size = strtol (arg, &suffix, 0); - if (*suffix == 'm' || *suffix == 'M') - extmem_size <<= 20; - else if (*suffix == 'k' || *suffix == 'K') - extmem_size <<= 10; - sim_do_commandf (sd, "memory delete 0x80000000"); - sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size); - - return SIM_RC_OK; - } - - sim_io_eprintf (sd, "Unknown option (%d)\n", opt); - return SIM_RC_FAIL; -} - -static const OPTION d30v_options[] = -{ - { {"trace-call", optional_argument, NULL, OPTION_TRACE_CALL}, - '\0', "on|off", "Enable tracing of calls and returns, checking saved registers", - d30v_option_handler }, - { {"trace-trapdump", optional_argument, NULL, OPTION_TRACE_TRAPDUMP}, - '\0', "on|off", -#if TRAPDUMP - "Traps 0..30 dump out all of the registers (defaults on)", -#else - "Traps 0..30 dump out all of the registers", -#endif - d30v_option_handler }, - { {"extmem-size", required_argument, NULL, OPTION_EXTMEM_SIZE}, - '\0', "size", "Change size of external memory, default 8 meg", - d30v_option_handler }, - { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } -}; - -/* Return name of an insn, used by insn profiling. */ - -static const char * -get_insn_name (sim_cpu *cpu, int i) -{ - return itable[i].name; -} - -/* Structures used by the simulator, for gdb just have static structures */ - -SIM_DESC -sim_open (SIM_OPEN_KIND kind, - host_callback *callback, - struct _bfd *abfd, - char **argv) -{ - SIM_DESC sd = sim_state_alloc (kind, callback); - - /* FIXME: watchpoints code shouldn't need this */ - STATE_WATCHPOINTS (sd)->pc = &(PC); - STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); - STATE_WATCHPOINTS (sd)->interrupt_handler = d30v_interrupt_event; - - /* Initialize the mechanism for doing insn profiling. */ - CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name; - CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries; - -#ifdef TRAPDUMP - TRACE_TRAP_P = TRAPDUMP; -#endif - - if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) - return 0; - sim_add_option_table (sd, NULL, d30v_options); - - /* Memory and EEPROM */ - /* internal instruction RAM - fixed */ - sim_do_commandf (sd, "memory region 0,0x10000"); - /* internal data RAM - fixed */ - sim_do_commandf (sd, "memory region 0x20000000,0x8000"); - /* control register dummy area */ - sim_do_commandf (sd, "memory region 0x40000000,0x10000"); - /* external RAM */ - sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size); - /* EIT RAM */ - sim_do_commandf (sd, "memory region 0xfffff000,0x1000"); - - /* getopt will print the error message so we just have to exit if this fails. - FIXME: Hmmm... in the case of gdb we need getopt to call - print_filtered. */ - if (sim_parse_args (sd, argv) != SIM_RC_OK) - { - /* Uninstall the modules to avoid memory leaks, - file descriptor leaks, etc. */ - sim_module_uninstall (sd); - return 0; - } - - /* check for/establish the a reference program image */ - if (sim_analyze_program (sd, - (STATE_PROG_ARGV (sd) != NULL - ? *STATE_PROG_ARGV (sd) - : NULL), - abfd) != SIM_RC_OK) - { - sim_module_uninstall (sd); - return 0; - } - - /* establish any remaining configuration options */ - if (sim_config (sd) != SIM_RC_OK) - { - sim_module_uninstall (sd); - return 0; - } - - if (sim_post_argv_init (sd) != SIM_RC_OK) - { - /* Uninstall the modules to avoid memory leaks, - file descriptor leaks, etc. */ - sim_module_uninstall (sd); - return 0; - } - - return sd; -} - - -void -sim_close (SIM_DESC sd, int quitting) -{ - /* Uninstall the modules to avoid memory leaks, - file descriptor leaks, etc. */ - sim_module_uninstall (sd); -} - - -SIM_RC -sim_create_inferior (SIM_DESC sd, - struct _bfd *abfd, - char **argv, - char **envp) -{ - /* clear all registers */ - memset (&STATE_CPU (sd, 0)->regs, 0, sizeof (STATE_CPU (sd, 0)->regs)); - EIT_VB = EIT_VB_DEFAULT; - STATE_CPU (sd, 0)->unit = any_unit; - sim_module_init (sd); - if (abfd != NULL) - PC = bfd_get_start_address (abfd); - else - PC = 0xfffff000; /* reset value */ - return SIM_RC_OK; -} - -void -sim_do_command (SIM_DESC sd, char *cmd) -{ - if (sim_args_command (sd, cmd) != SIM_RC_OK) - sim_io_printf (sd, "Unknown command `%s'\n", cmd); -} - -/* The following register definitions were ripped off from - gdb/config/tm-d30v.h. If any of those defs changes, this table needs to - be updated. */ - -#define NUM_REGS 86 - -#define R0_REGNUM 0 -#define FP_REGNUM 11 -#define LR_REGNUM 62 -#define SP_REGNUM 63 -#define SPI_REGNUM 64 /* Interrupt stack pointer */ -#define SPU_REGNUM 65 /* User stack pointer */ -#define CREGS_START 66 - -#define PSW_REGNUM (CREGS_START + 0) /* psw, bpsw, or dpsw??? */ -#define PSW_SM 0x80000000 /* Stack mode: 0 == interrupt (SPI), - 1 == user (SPU) */ -#define BPSW_REGNUM (CREGS_START + 1) /* Backup PSW (on interrupt) */ -#define PC_REGNUM (CREGS_START + 2) /* pc, bpc, or dpc??? */ -#define BPC_REGNUM (CREGS_START + 3) /* Backup PC (on interrupt) */ -#define DPSW_REGNUM (CREGS_START + 4) /* Backup PSW (on debug trap) */ -#define DPC_REGNUM (CREGS_START + 5) /* Backup PC (on debug trap) */ -#define RPT_C_REGNUM (CREGS_START + 7) /* Loop count */ -#define RPT_S_REGNUM (CREGS_START + 8) /* Loop start address*/ -#define RPT_E_REGNUM (CREGS_START + 9) /* Loop end address */ -#define MOD_S_REGNUM (CREGS_START + 10) -#define MOD_E_REGNUM (CREGS_START + 11) -#define IBA_REGNUM (CREGS_START + 14) /* Instruction break address */ -#define EIT_VB_REGNUM (CREGS_START + 15) /* Vector base address */ -#define INT_S_REGNUM (CREGS_START + 16) /* Interrupt status */ -#define INT_M_REGNUM (CREGS_START + 17) /* Interrupt mask */ -#define A0_REGNUM 84 -#define A1_REGNUM 85 - -int -sim_fetch_register (sd, regno, buf, length) - SIM_DESC sd; - int regno; - unsigned char *buf; - int length; -{ - if (regno < A0_REGNUM) - { - unsigned32 reg; - - if (regno <= R0_REGNUM + 63) - reg = sd->cpu[0].regs.general_purpose[regno]; - else if (regno <= SPU_REGNUM) - reg = sd->cpu[0].regs.sp[regno - SPI_REGNUM]; - else - reg = sd->cpu[0].regs.control[regno - CREGS_START]; - - buf[0] = reg >> 24; - buf[1] = reg >> 16; - buf[2] = reg >> 8; - buf[3] = reg; - } - else if (regno < NUM_REGS) - { - unsigned32 reg; - - reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM] >> 32; - - buf[0] = reg >> 24; - buf[1] = reg >> 16; - buf[2] = reg >> 8; - buf[3] = reg; - - reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM]; - - buf[4] = reg >> 24; - buf[5] = reg >> 16; - buf[6] = reg >> 8; - buf[7] = reg; - } - else - abort (); - return -1; -} - -int -sim_store_register (sd, regno, buf, length) - SIM_DESC sd; - int regno; - unsigned char *buf; - int length; -{ - if (regno < A0_REGNUM) - { - unsigned32 reg; - - reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; - - if (regno <= R0_REGNUM + 63) - sd->cpu[0].regs.general_purpose[regno] = reg; - else if (regno <= SPU_REGNUM) - sd->cpu[0].regs.sp[regno - SPI_REGNUM] = reg; - else - sd->cpu[0].regs.control[regno - CREGS_START] = reg; - } - else if (regno < NUM_REGS) - { - unsigned32 reg; - - reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; - - sd->cpu[0].regs.accumulator[regno - A0_REGNUM] = (unsigned64)reg << 32; - - reg = (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7]; - - sd->cpu[0].regs.accumulator[regno - A0_REGNUM] |= reg; - } - else - abort (); - return -1; -} +/* OBSOLETE /* This file is part of the program psim. */ +/* OBSOLETE */ +/* OBSOLETE Copyright (C) 1994-1996, Andrew Cagney */ +/* OBSOLETE Copyright (C) 1997, Free Software Foundation */ +/* OBSOLETE */ +/* OBSOLETE This program is free software; you can redistribute it and/or modify */ +/* OBSOLETE it under the terms of the GNU General Public License as published by */ +/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */ +/* OBSOLETE (at your option) any later version. */ +/* OBSOLETE */ +/* OBSOLETE This program is distributed in the hope that it will be useful, */ +/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* OBSOLETE GNU General Public License for more details. */ +/* OBSOLETE */ +/* OBSOLETE You should have received a copy of the GNU General Public License */ +/* OBSOLETE along with this program; if not, write to the Free Software */ +/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* OBSOLETE */ +/* OBSOLETE */ */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #include */ +/* OBSOLETE #include */ +/* OBSOLETE */ +/* OBSOLETE #include "sim-main.h" */ +/* OBSOLETE #include "sim-options.h" */ +/* OBSOLETE */ +/* OBSOLETE #include "bfd.h" */ +/* OBSOLETE #include "sim-utils.h" */ +/* OBSOLETE */ +/* OBSOLETE #ifdef HAVE_STDLIB_H */ +/* OBSOLETE #include */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE static unsigned long extmem_size = 1024*1024*8; /* 8 meg is the maximum listed in the arch. manual */ */ +/* OBSOLETE */ +/* OBSOLETE static const char * get_insn_name (sim_cpu *, int); */ +/* OBSOLETE */ +/* OBSOLETE #define SIM_ADDR unsigned */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #define OPTION_TRACE_CALL 200 */ +/* OBSOLETE #define OPTION_TRACE_TRAPDUMP 201 */ +/* OBSOLETE #define OPTION_EXTMEM_SIZE 202 */ +/* OBSOLETE */ +/* OBSOLETE static SIM_RC */ +/* OBSOLETE d30v_option_handler (SIM_DESC sd, */ +/* OBSOLETE sim_cpu *cpu, */ +/* OBSOLETE int opt, */ +/* OBSOLETE char *arg, */ +/* OBSOLETE int command_p) */ +/* OBSOLETE { */ +/* OBSOLETE char *suffix; */ +/* OBSOLETE */ +/* OBSOLETE switch (opt) */ +/* OBSOLETE { */ +/* OBSOLETE default: */ +/* OBSOLETE break; */ +/* OBSOLETE */ +/* OBSOLETE case OPTION_TRACE_CALL: */ +/* OBSOLETE if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0) */ +/* OBSOLETE TRACE_CALL_P = 1; */ +/* OBSOLETE else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0) */ +/* OBSOLETE TRACE_CALL_P = 0; */ +/* OBSOLETE else */ +/* OBSOLETE { */ +/* OBSOLETE sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg); */ +/* OBSOLETE return SIM_RC_FAIL; */ +/* OBSOLETE } */ +/* OBSOLETE return SIM_RC_OK; */ +/* OBSOLETE */ +/* OBSOLETE case OPTION_TRACE_TRAPDUMP: */ +/* OBSOLETE if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0) */ +/* OBSOLETE TRACE_TRAP_P = 1; */ +/* OBSOLETE else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0) */ +/* OBSOLETE TRACE_TRAP_P = 0; */ +/* OBSOLETE else */ +/* OBSOLETE { */ +/* OBSOLETE sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg); */ +/* OBSOLETE return SIM_RC_FAIL; */ +/* OBSOLETE } */ +/* OBSOLETE return SIM_RC_OK; */ +/* OBSOLETE */ +/* OBSOLETE case OPTION_EXTMEM_SIZE: */ +/* OBSOLETE if (arg == NULL || !isdigit (*arg)) */ +/* OBSOLETE { */ +/* OBSOLETE sim_io_eprintf (sd, "Invalid memory size `%s'", arg); */ +/* OBSOLETE return SIM_RC_FAIL; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE suffix = arg; */ +/* OBSOLETE extmem_size = strtol (arg, &suffix, 0); */ +/* OBSOLETE if (*suffix == 'm' || *suffix == 'M') */ +/* OBSOLETE extmem_size <<= 20; */ +/* OBSOLETE else if (*suffix == 'k' || *suffix == 'K') */ +/* OBSOLETE extmem_size <<= 10; */ +/* OBSOLETE sim_do_commandf (sd, "memory delete 0x80000000"); */ +/* OBSOLETE sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size); */ +/* OBSOLETE */ +/* OBSOLETE return SIM_RC_OK; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE sim_io_eprintf (sd, "Unknown option (%d)\n", opt); */ +/* OBSOLETE return SIM_RC_FAIL; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE static const OPTION d30v_options[] = */ +/* OBSOLETE { */ +/* OBSOLETE { {"trace-call", optional_argument, NULL, OPTION_TRACE_CALL}, */ +/* OBSOLETE '\0', "on|off", "Enable tracing of calls and returns, checking saved registers", */ +/* OBSOLETE d30v_option_handler }, */ +/* OBSOLETE { {"trace-trapdump", optional_argument, NULL, OPTION_TRACE_TRAPDUMP}, */ +/* OBSOLETE '\0', "on|off", */ +/* OBSOLETE #if TRAPDUMP */ +/* OBSOLETE "Traps 0..30 dump out all of the registers (defaults on)", */ +/* OBSOLETE #else */ +/* OBSOLETE "Traps 0..30 dump out all of the registers", */ +/* OBSOLETE #endif */ +/* OBSOLETE d30v_option_handler }, */ +/* OBSOLETE { {"extmem-size", required_argument, NULL, OPTION_EXTMEM_SIZE}, */ +/* OBSOLETE '\0', "size", "Change size of external memory, default 8 meg", */ +/* OBSOLETE d30v_option_handler }, */ +/* OBSOLETE { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE /* Return name of an insn, used by insn profiling. */ */ +/* OBSOLETE */ +/* OBSOLETE static const char * */ +/* OBSOLETE get_insn_name (sim_cpu *cpu, int i) */ +/* OBSOLETE { */ +/* OBSOLETE return itable[i].name; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* Structures used by the simulator, for gdb just have static structures */ */ +/* OBSOLETE */ +/* OBSOLETE SIM_DESC */ +/* OBSOLETE sim_open (SIM_OPEN_KIND kind, */ +/* OBSOLETE host_callback *callback, */ +/* OBSOLETE struct _bfd *abfd, */ +/* OBSOLETE char **argv) */ +/* OBSOLETE { */ +/* OBSOLETE SIM_DESC sd = sim_state_alloc (kind, callback); */ +/* OBSOLETE */ +/* OBSOLETE /* FIXME: watchpoints code shouldn't need this */ */ +/* OBSOLETE STATE_WATCHPOINTS (sd)->pc = &(PC); */ +/* OBSOLETE STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); */ +/* OBSOLETE STATE_WATCHPOINTS (sd)->interrupt_handler = d30v_interrupt_event; */ +/* OBSOLETE */ +/* OBSOLETE /* Initialize the mechanism for doing insn profiling. */ */ +/* OBSOLETE CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name; */ +/* OBSOLETE CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries; */ +/* OBSOLETE */ +/* OBSOLETE #ifdef TRAPDUMP */ +/* OBSOLETE TRACE_TRAP_P = TRAPDUMP; */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) */ +/* OBSOLETE return 0; */ +/* OBSOLETE sim_add_option_table (sd, NULL, d30v_options); */ +/* OBSOLETE */ +/* OBSOLETE /* Memory and EEPROM */ */ +/* OBSOLETE /* internal instruction RAM - fixed */ */ +/* OBSOLETE sim_do_commandf (sd, "memory region 0,0x10000"); */ +/* OBSOLETE /* internal data RAM - fixed */ */ +/* OBSOLETE sim_do_commandf (sd, "memory region 0x20000000,0x8000"); */ +/* OBSOLETE /* control register dummy area */ */ +/* OBSOLETE sim_do_commandf (sd, "memory region 0x40000000,0x10000"); */ +/* OBSOLETE /* external RAM */ */ +/* OBSOLETE sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size); */ +/* OBSOLETE /* EIT RAM */ */ +/* OBSOLETE sim_do_commandf (sd, "memory region 0xfffff000,0x1000"); */ +/* OBSOLETE */ +/* OBSOLETE /* getopt will print the error message so we just have to exit if this fails. */ +/* OBSOLETE FIXME: Hmmm... in the case of gdb we need getopt to call */ +/* OBSOLETE print_filtered. */ */ +/* OBSOLETE if (sim_parse_args (sd, argv) != SIM_RC_OK) */ +/* OBSOLETE { */ +/* OBSOLETE /* Uninstall the modules to avoid memory leaks, */ +/* OBSOLETE file descriptor leaks, etc. */ */ +/* OBSOLETE sim_module_uninstall (sd); */ +/* OBSOLETE return 0; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* check for/establish the a reference program image */ */ +/* OBSOLETE if (sim_analyze_program (sd, */ +/* OBSOLETE (STATE_PROG_ARGV (sd) != NULL */ +/* OBSOLETE ? *STATE_PROG_ARGV (sd) */ +/* OBSOLETE : NULL), */ +/* OBSOLETE abfd) != SIM_RC_OK) */ +/* OBSOLETE { */ +/* OBSOLETE sim_module_uninstall (sd); */ +/* OBSOLETE return 0; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* establish any remaining configuration options */ */ +/* OBSOLETE if (sim_config (sd) != SIM_RC_OK) */ +/* OBSOLETE { */ +/* OBSOLETE sim_module_uninstall (sd); */ +/* OBSOLETE return 0; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE if (sim_post_argv_init (sd) != SIM_RC_OK) */ +/* OBSOLETE { */ +/* OBSOLETE /* Uninstall the modules to avoid memory leaks, */ +/* OBSOLETE file descriptor leaks, etc. */ */ +/* OBSOLETE sim_module_uninstall (sd); */ +/* OBSOLETE return 0; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE return sd; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE void */ +/* OBSOLETE sim_close (SIM_DESC sd, int quitting) */ +/* OBSOLETE { */ +/* OBSOLETE /* Uninstall the modules to avoid memory leaks, */ +/* OBSOLETE file descriptor leaks, etc. */ */ +/* OBSOLETE sim_module_uninstall (sd); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE SIM_RC */ +/* OBSOLETE sim_create_inferior (SIM_DESC sd, */ +/* OBSOLETE struct _bfd *abfd, */ +/* OBSOLETE char **argv, */ +/* OBSOLETE char **envp) */ +/* OBSOLETE { */ +/* OBSOLETE /* clear all registers */ */ +/* OBSOLETE memset (&STATE_CPU (sd, 0)->regs, 0, sizeof (STATE_CPU (sd, 0)->regs)); */ +/* OBSOLETE EIT_VB = EIT_VB_DEFAULT; */ +/* OBSOLETE STATE_CPU (sd, 0)->unit = any_unit; */ +/* OBSOLETE sim_module_init (sd); */ +/* OBSOLETE if (abfd != NULL) */ +/* OBSOLETE PC = bfd_get_start_address (abfd); */ +/* OBSOLETE else */ +/* OBSOLETE PC = 0xfffff000; /* reset value */ */ +/* OBSOLETE return SIM_RC_OK; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE void */ +/* OBSOLETE sim_do_command (SIM_DESC sd, char *cmd) */ +/* OBSOLETE { */ +/* OBSOLETE if (sim_args_command (sd, cmd) != SIM_RC_OK) */ +/* OBSOLETE sim_io_printf (sd, "Unknown command `%s'\n", cmd); */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE /* The following register definitions were ripped off from */ +/* OBSOLETE gdb/config/tm-d30v.h. If any of those defs changes, this table needs to */ +/* OBSOLETE be updated. */ */ +/* OBSOLETE */ +/* OBSOLETE #define NUM_REGS 86 */ +/* OBSOLETE */ +/* OBSOLETE #define R0_REGNUM 0 */ +/* OBSOLETE #define FP_REGNUM 11 */ +/* OBSOLETE #define LR_REGNUM 62 */ +/* OBSOLETE #define SP_REGNUM 63 */ +/* OBSOLETE #define SPI_REGNUM 64 /* Interrupt stack pointer */ */ +/* OBSOLETE #define SPU_REGNUM 65 /* User stack pointer */ */ +/* OBSOLETE #define CREGS_START 66 */ +/* OBSOLETE */ +/* OBSOLETE #define PSW_REGNUM (CREGS_START + 0) /* psw, bpsw, or dpsw??? */ */ +/* OBSOLETE #define PSW_SM 0x80000000 /* Stack mode: 0 == interrupt (SPI), */ +/* OBSOLETE 1 == user (SPU) */ */ +/* OBSOLETE #define BPSW_REGNUM (CREGS_START + 1) /* Backup PSW (on interrupt) */ */ +/* OBSOLETE #define PC_REGNUM (CREGS_START + 2) /* pc, bpc, or dpc??? */ */ +/* OBSOLETE #define BPC_REGNUM (CREGS_START + 3) /* Backup PC (on interrupt) */ */ +/* OBSOLETE #define DPSW_REGNUM (CREGS_START + 4) /* Backup PSW (on debug trap) */ */ +/* OBSOLETE #define DPC_REGNUM (CREGS_START + 5) /* Backup PC (on debug trap) */ */ +/* OBSOLETE #define RPT_C_REGNUM (CREGS_START + 7) /* Loop count */ */ +/* OBSOLETE #define RPT_S_REGNUM (CREGS_START + 8) /* Loop start address*/ */ +/* OBSOLETE #define RPT_E_REGNUM (CREGS_START + 9) /* Loop end address */ */ +/* OBSOLETE #define MOD_S_REGNUM (CREGS_START + 10) */ +/* OBSOLETE #define MOD_E_REGNUM (CREGS_START + 11) */ +/* OBSOLETE #define IBA_REGNUM (CREGS_START + 14) /* Instruction break address */ */ +/* OBSOLETE #define EIT_VB_REGNUM (CREGS_START + 15) /* Vector base address */ */ +/* OBSOLETE #define INT_S_REGNUM (CREGS_START + 16) /* Interrupt status */ */ +/* OBSOLETE #define INT_M_REGNUM (CREGS_START + 17) /* Interrupt mask */ */ +/* OBSOLETE #define A0_REGNUM 84 */ +/* OBSOLETE #define A1_REGNUM 85 */ +/* OBSOLETE */ +/* OBSOLETE int */ +/* OBSOLETE sim_fetch_register (sd, regno, buf, length) */ +/* OBSOLETE SIM_DESC sd; */ +/* OBSOLETE int regno; */ +/* OBSOLETE unsigned char *buf; */ +/* OBSOLETE int length; */ +/* OBSOLETE { */ +/* OBSOLETE if (regno < A0_REGNUM) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned32 reg; */ +/* OBSOLETE */ +/* OBSOLETE if (regno <= R0_REGNUM + 63) */ +/* OBSOLETE reg = sd->cpu[0].regs.general_purpose[regno]; */ +/* OBSOLETE else if (regno <= SPU_REGNUM) */ +/* OBSOLETE reg = sd->cpu[0].regs.sp[regno - SPI_REGNUM]; */ +/* OBSOLETE else */ +/* OBSOLETE reg = sd->cpu[0].regs.control[regno - CREGS_START]; */ +/* OBSOLETE */ +/* OBSOLETE buf[0] = reg >> 24; */ +/* OBSOLETE buf[1] = reg >> 16; */ +/* OBSOLETE buf[2] = reg >> 8; */ +/* OBSOLETE buf[3] = reg; */ +/* OBSOLETE } */ +/* OBSOLETE else if (regno < NUM_REGS) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned32 reg; */ +/* OBSOLETE */ +/* OBSOLETE reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM] >> 32; */ +/* OBSOLETE */ +/* OBSOLETE buf[0] = reg >> 24; */ +/* OBSOLETE buf[1] = reg >> 16; */ +/* OBSOLETE buf[2] = reg >> 8; */ +/* OBSOLETE buf[3] = reg; */ +/* OBSOLETE */ +/* OBSOLETE reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM]; */ +/* OBSOLETE */ +/* OBSOLETE buf[4] = reg >> 24; */ +/* OBSOLETE buf[5] = reg >> 16; */ +/* OBSOLETE buf[6] = reg >> 8; */ +/* OBSOLETE buf[7] = reg; */ +/* OBSOLETE } */ +/* OBSOLETE else */ +/* OBSOLETE abort (); */ +/* OBSOLETE return -1; */ +/* OBSOLETE } */ +/* OBSOLETE */ +/* OBSOLETE int */ +/* OBSOLETE sim_store_register (sd, regno, buf, length) */ +/* OBSOLETE SIM_DESC sd; */ +/* OBSOLETE int regno; */ +/* OBSOLETE unsigned char *buf; */ +/* OBSOLETE int length; */ +/* OBSOLETE { */ +/* OBSOLETE if (regno < A0_REGNUM) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned32 reg; */ +/* OBSOLETE */ +/* OBSOLETE reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; */ +/* OBSOLETE */ +/* OBSOLETE if (regno <= R0_REGNUM + 63) */ +/* OBSOLETE sd->cpu[0].regs.general_purpose[regno] = reg; */ +/* OBSOLETE else if (regno <= SPU_REGNUM) */ +/* OBSOLETE sd->cpu[0].regs.sp[regno - SPI_REGNUM] = reg; */ +/* OBSOLETE else */ +/* OBSOLETE sd->cpu[0].regs.control[regno - CREGS_START] = reg; */ +/* OBSOLETE } */ +/* OBSOLETE else if (regno < NUM_REGS) */ +/* OBSOLETE { */ +/* OBSOLETE unsigned32 reg; */ +/* OBSOLETE */ +/* OBSOLETE reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; */ +/* OBSOLETE */ +/* OBSOLETE sd->cpu[0].regs.accumulator[regno - A0_REGNUM] = (unsigned64)reg << 32; */ +/* OBSOLETE */ +/* OBSOLETE reg = (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7]; */ +/* OBSOLETE */ +/* OBSOLETE sd->cpu[0].regs.accumulator[regno - A0_REGNUM] |= reg; */ +/* OBSOLETE } */ +/* OBSOLETE else */ +/* OBSOLETE abort (); */ +/* OBSOLETE return -1; */ +/* OBSOLETE } */ diff --git a/sim/d30v/sim-main.h b/sim/d30v/sim-main.h index 4db8aa0..d1764da 100644 --- a/sim/d30v/sim-main.h +++ b/sim/d30v/sim-main.h @@ -1,82 +1,82 @@ -/* This file is part of the program psim. - - Copyright (C) 1994-1997, Andrew Cagney - Copyright (C) 1997, 1998, Free Software Foundation - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - - */ - - -#ifndef _SIM_MAIN_H_ -#define _SIM_MAIN_H_ - -/* This simulator suports watchpoints */ -#define WITH_WATCHPOINTS 1 - -#include "sim-basics.h" -#include "sim-signal.h" - -/* needed */ -typedef address_word sim_cia; -#define INVALID_INSTRUCTION_ADDRESS ((address_word) 0 - 1) - -/* This simulator doesn't cache anything so no saving of context is - needed during either of a halt or restart */ -#define SIM_ENGINE_HALT_HOOK(SD,CPU,CIA) while (0) -#define SIM_ENGINE_RESTART_HOOK(SD,CPU,CIA) while (0) - -#include "sim-base.h" - -/* These are generated files. */ -#include "itable.h" -#include "s_idecode.h" -#include "l_idecode.h" - -#include "cpu.h" -#include "alu.h" - - -struct sim_state { - - sim_event *pending_interrupt; - - /* the processors proper */ - sim_cpu cpu[MAX_NR_PROCESSORS]; -#if (WITH_SMP) -#define STATE_CPU(sd, n) (&(sd)->cpu[n]) -#else -#define STATE_CPU(sd, n) (&(sd)->cpu[0]) -#endif - - /* The base class. */ - sim_state_base base; - -}; - - -/* deliver an interrupt */ -sim_event_handler d30v_interrupt_event; - - -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif - -#endif /* _SIM_MAIN_H_ */ +/* OBSOLETE /* This file is part of the program psim. */ +/* OBSOLETE */ +/* OBSOLETE Copyright (C) 1994-1997, Andrew Cagney */ +/* OBSOLETE Copyright (C) 1997, 1998, Free Software Foundation */ +/* OBSOLETE */ +/* OBSOLETE This program is free software; you can redistribute it and/or modify */ +/* OBSOLETE it under the terms of the GNU General Public License as published by */ +/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */ +/* OBSOLETE (at your option) any later version. */ +/* OBSOLETE */ +/* OBSOLETE This program is distributed in the hope that it will be useful, */ +/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* OBSOLETE GNU General Public License for more details. */ +/* OBSOLETE */ +/* OBSOLETE You should have received a copy of the GNU General Public License */ +/* OBSOLETE along with this program; if not, write to the Free Software */ +/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* OBSOLETE */ +/* OBSOLETE */ */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #ifndef _SIM_MAIN_H_ */ +/* OBSOLETE #define _SIM_MAIN_H_ */ +/* OBSOLETE */ +/* OBSOLETE /* This simulator suports watchpoints */ */ +/* OBSOLETE #define WITH_WATCHPOINTS 1 */ +/* OBSOLETE */ +/* OBSOLETE #include "sim-basics.h" */ +/* OBSOLETE #include "sim-signal.h" */ +/* OBSOLETE */ +/* OBSOLETE /* needed */ */ +/* OBSOLETE typedef address_word sim_cia; */ +/* OBSOLETE #define INVALID_INSTRUCTION_ADDRESS ((address_word) 0 - 1) */ +/* OBSOLETE */ +/* OBSOLETE /* This simulator doesn't cache anything so no saving of context is */ +/* OBSOLETE needed during either of a halt or restart */ */ +/* OBSOLETE #define SIM_ENGINE_HALT_HOOK(SD,CPU,CIA) while (0) */ +/* OBSOLETE #define SIM_ENGINE_RESTART_HOOK(SD,CPU,CIA) while (0) */ +/* OBSOLETE */ +/* OBSOLETE #include "sim-base.h" */ +/* OBSOLETE */ +/* OBSOLETE /* These are generated files. */ */ +/* OBSOLETE #include "itable.h" */ +/* OBSOLETE #include "s_idecode.h" */ +/* OBSOLETE #include "l_idecode.h" */ +/* OBSOLETE */ +/* OBSOLETE #include "cpu.h" */ +/* OBSOLETE #include "alu.h" */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE struct sim_state { */ +/* OBSOLETE */ +/* OBSOLETE sim_event *pending_interrupt; */ +/* OBSOLETE */ +/* OBSOLETE /* the processors proper */ */ +/* OBSOLETE sim_cpu cpu[MAX_NR_PROCESSORS]; */ +/* OBSOLETE #if (WITH_SMP) */ +/* OBSOLETE #define STATE_CPU(sd, n) (&(sd)->cpu[n]) */ +/* OBSOLETE #else */ +/* OBSOLETE #define STATE_CPU(sd, n) (&(sd)->cpu[0]) */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE /* The base class. */ */ +/* OBSOLETE sim_state_base base; */ +/* OBSOLETE */ +/* OBSOLETE }; */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE /* deliver an interrupt */ */ +/* OBSOLETE sim_event_handler d30v_interrupt_event; */ +/* OBSOLETE */ +/* OBSOLETE */ +/* OBSOLETE #ifdef HAVE_STRING_H */ +/* OBSOLETE #include */ +/* OBSOLETE #else */ +/* OBSOLETE #ifdef HAVE_STRINGS_H */ +/* OBSOLETE #include */ +/* OBSOLETE #endif */ +/* OBSOLETE #endif */ +/* OBSOLETE */ +/* OBSOLETE #endif /* _SIM_MAIN_H_ */ */ -- cgit v1.1