From 1d18e9892e9d7a2243636676f05efc2fc29b88e7 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 1 Apr 2012 04:31:46 +0000 Subject: sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slots Parallel insns can only do one 32bit, then two 16bits. So if we see a 2nd 32bit insn after the first 32bit in a parallel insn, abort. Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 5 +++++ sim/bfin/bfin-sim.c | 3 +++ 2 files changed, 8 insertions(+) (limited to 'sim') diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 899d0ca..f442224 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,5 +1,10 @@ 2012-04-01 Mike Frysinger + * bfin-sim.c (_interp_insn_bfin): Call illegal_instruction_combination + when INSN_LEN is non-zero before 32bit decode. + +2012-04-01 Mike Frysinger + * bfin-dis.c (fmtconst): Replace decimal handling with a single sprintf call and the '*' field width. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 54d6bca..a8c7794 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -6187,6 +6187,9 @@ _interp_insn_bfin (SIM_CPU *cpu, bu32 pc) /* Only cache on first run through (in case of parallel insns). */ if (INSN_LEN == 0) INSN_LEN = insn_len; + else + /* Once you're past the first slot, only 16bit insns are valid. */ + illegal_instruction_combination (cpu); if ((iw0 & 0xf7ff) == 0xc003 && (iw1 & 0xfe00) == 0x1800) { -- cgit v1.1