From c906108c21474dfb4ed285bcc0ac6fe02cd400cc Mon Sep 17 00:00:00 2001 From: Stan Shebs Date: Fri, 16 Apr 1999 01:35:26 +0000 Subject: Initial creation of sourceware repository --- sim/v850/ChangeLog | 1055 ++++++++++++ sim/v850/Makefile.in | 142 ++ sim/v850/acconfig.h | 15 + sim/v850/config.in | 183 +++ sim/v850/configure | 4267 +++++++++++++++++++++++++++++++++++++++++++++++++ sim/v850/configure.in | 18 + sim/v850/gencode.c | 149 ++ sim/v850/interp.c | 360 +++++ sim/v850/sim-main.h | 388 +++++ sim/v850/simops.c | 2733 +++++++++++++++++++++++++++++++ sim/v850/v850-dc | 30 + sim/v850/v850.igen | 1407 ++++++++++++++++ sim/v850/v850_sim.h | 8 + 13 files changed, 10755 insertions(+) create mode 100644 sim/v850/ChangeLog create mode 100644 sim/v850/Makefile.in create mode 100644 sim/v850/acconfig.h create mode 100644 sim/v850/config.in create mode 100755 sim/v850/configure create mode 100644 sim/v850/configure.in create mode 100644 sim/v850/gencode.c create mode 100644 sim/v850/interp.c create mode 100644 sim/v850/sim-main.h create mode 100644 sim/v850/simops.c create mode 100644 sim/v850/v850-dc create mode 100644 sim/v850/v850.igen create mode 100644 sim/v850/v850_sim.h (limited to 'sim/v850') diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog new file mode 100644 index 0000000..ee0df4f --- /dev/null +++ b/sim/v850/ChangeLog @@ -0,0 +1,1055 @@ +Tue Dec 1 17:25:16 1998 Andrew Cagney + + * Makefile.in (NL_TARGET): Define as -DNL_TARGET_v850. + +Wed Nov 25 17:52:58 1998 Andrew Cagney + + * Makefile.in (simops.o): Depends on targ-vals.h + * simops.c: Include targ-vals.h instead of + libgloss/.../syscall.h. Replace SYS_* with TARGET_SYS_*. + (divn, divun, OP_1C007E0, OP_18207E0, OP_1C207E0,OP_18007E0): + Replace signed long int with signed32. + +Fri Oct 9 18:02:25 1998 Doug Evans + + * interp.c: #include "itable.h". + (get_insn_name): New function. + (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. + * sim-main.h (MAX_INSNS,INSN_NAME): Delete. + +Wed May 6 19:43:27 1998 Doug Evans + + * sim-main.h (INSN_NAME): New arg `cpu'. + +Tue Apr 28 18:33:31 1998 Geoffrey Noer + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Apr 26 15:31:55 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:19:14 1998 Tom Tromey + + * acconfig.h: New file. + * configure.in: Reverted change of Apr 24; use sinclude again. + +Fri Apr 24 14:16:40 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:18:08 1998 Tom Tromey + + * configure.in: Don't call sinclude. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * sim-main.h (SIM_MAIN_H): Wrap header. + +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Mar 10 15:54:50 1998 Andrew Cagney + + * interp.c (sim_stop): Delete, second attempt. + +Thu Feb 26 19:09:47 1998 Andrew Cagney + + * interp.c (sim_info): Delete. + +Wed Feb 18 10:47:32 1998 Andrew Cagney + + * sim-main.h (TRACE_ALU_INPUT*): Delete. Moved to sim-trace.[hc]. + + * simops.c (trace_result): Call trace_generic instead of + trace_one_insn. + (trace_module): Change variable type to integer. + (trace_input): Initialize trace_module with TRACE_ALU_IDX. + + * sim-main.h (trace_module): Change variable decl to integer type. + (TRACE_BRANCH*, TRACE_LD, TRACE_ST): Update. + +Tue Feb 17 12:51:18 1998 Andrew Cagney + + * interp.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Tue Feb 3 16:24:42 1998 Andrew Cagney + + * sim-main.h (IMEM16, IMEM16_IMMED): Rename IMEM and + IMEM_IMMED. To match recent igen change. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Jan 30 09:51:27 1998 Andrew Cagney + + * sim-main.h (CPU_CIA): Delete, replaced by. + (CIA_SET, CIA_SET): Define. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Dec 5 09:26:08 1997 Nick Clifton + + * v850.igen: Revert break value back to its old value. + +Thu Dec 4 09:21:05 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Dec 3 17:27:19 1997 Nick Clifton + + * v850.igen: Make break have a zero first field, since otherwise + it clashes with the DIVH instruction. + +Sat Nov 22 21:32:07 1997 Andrew Cagney + + * simops.c (OP_10007E0): Rename SIGABRT -> SIM_SIGABRT. Give + sim_stopped instead of sim_signalled. + + * v850.igen (BREAK), simops.c (OP_12007E0): Rename SIGTRAP to + SIM_SIGTRAP. + (illegal): Rename SIGILL to SIM_SIGILL. + + * sim-main.h, simops.c, interp.c: Do not include signal.h. + + * sim-main.h: Include sim-signal.h instead of signal.h. + (SIGTRAP, SIGQUIT): Delete definition. + (SIG_V850_EXIT): Delete definition. + +Tue Nov 18 15:33:48 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). + +Fri Oct 31 10:33:40 1997 Andrew Cagney + + * interp.c (sim_open): Check state magic number. + (sim-assert.h): Include. + +Tue Oct 28 11:06:47 1997 Andrew Cagney + + * v850.igen: Add model filter field to records. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 26 11:56:02 1997 Felix Lee + + * sim-main.h: delete null override of SIM_ENGINE_HALT_HOOK and + SIM_ENGINE_RESTART_HOOK. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:28:26 1997 Andrew Cagney + + * sim-main.h (WITH_TARGET_WORD_MSB): Delete. + + * configure.in (SIM_AC_OPTION_BITSIZE): Specify 32 bit + architecture with MSB == 31. + +Wed Sep 24 14:04:20 1997 Andrew Cagney + + * v850.igen: Make divh insn with RRRRR==0 breakpoint. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 10:19:51 1997 Andrew Cagney + + * Makefile.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN, + SIM_HOSTENDIAN, SIM_RESERVED_BITS): Delete, moved to common. + (SIM_EXTRA_CFLAGS): Update. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * configure.in: Really specify NONSTRICT_ALIGNMENT as the default. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure.in: Specify NONSTRICT_ALIGNMENT as the default. + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 10:37:20 1997 Andrew Cagney + + * v850.igen (disp16): Use EXTEND16 to sign extend disp. + (disp22): Only shift left by 1, not 2. + ("jmp"): Ensure PC is 2 byte aligned. + + * simops.c, v850.igen: Move "Bcond", "jr", "jarl" code to + v850.igen. Fix tracing. + + * simops.c (OP_300, OP_400, OP_500): Move "sdl.b", "sld.h", + "sld.w" insns to v850.igen. Fix tracing. + (OP_70): Ditto for "sld.hu". + + * v850.igen: Clarify tracing of "sld.b", "sld.h" et.al. + + * simops.c (condition_met): Make global. + + * sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0, TRACE_LD, + TRACE_ST): Define. + (TRACE_LD_NAME): Define. + + * simops.c: Move "cmov", "cmov imm" to v850.igen, fix. + +Wed Sep 17 16:21:08 1997 Andrew Cagney + + * simops.c: Move "mov", "reti", to v850.igen, fix tracing. + + * interp.c (hash): Delete. + + * v850.igen (nop): Really do nothing. + + * interp.c (do_interrupt): Mask interrupts after PSW is saved, not + before. + * v850.igen (reti): Return to current PC not previous. + +Wed Sep 17 14:02:10 1997 Andrew Cagney + + * simops.c: Move "ctret", "bsw", "hsw" to v850.igen, fix tracing. + (trace_module): Global, save component/module name across insn. + + * simops.c: Move "bsh" to v850.igen, fix. + + * v850.igen (callt): Load correct number of bytes. Fix tracing. + (stsr, ldsr): Correct src, dest fields. Fix tracing. + (ctret): Force alignment. Fix tracing. + +Tue Sep 16 22:14:01 1997 Andrew Cagney + + * simops.c (trace_output): Add result argument. + (trace_result): New function. Simpler version of trace_output, + assumes trace needed. + (trace_output): Call trace_result. + (trace_output): For IMM_REG_REG, trace correct register. + (trace_input): Add case for 16bit immediates. + (OP_600, OP_640, OP_680, OP_6C0, OP_6A0): Use. + + * sim-main.h (TRACE_ALU_INPUT, TRACE_ALU_RESULT): Define. + (trace_values, trace_name, trace_pc, trace_num_values): Make + global. + (GR, SR): Define. + + v850.insn (movea, stsr): Use. + (sxb, sxh, zxb, zxh): Ditto. + +Tue Sep 16 21:14:01 1997 Andrew Cagney + + * simops.c: Move "movea" from here. + * v850.igen: To here. + + * v850.igen (simm16): Define, sign extend imm16. + (uimm16): Define, no sign extension. + (addi, andi, movea, movhi, mulhi, ori, satsubi, xori): Use. + + * simops.c: Move "sxh", "switch", "sxb", "callt", "dispose", + "mov32" from here. + * v850.igen: To here. + (switch): Fix off by two error in NIA calc. + +Tue Sep 16 15:14:01 1997 Andrew Cagney + + * simops.c (trace_pc, trace_name, trace_values, trace_num_values): + New static globals. + (trace_input): Just save pc, name and values for trace_output. + (trace_output): Write trace values to a buffer. Use + trace_one_insn to print trace info and buffer. + (SIZE_OPERANDS, SIZE_LOCATION): Delete. + +Tue Sep 16 09:02:00 1997 Andrew Cagney + + * sim-main.h (struct _sim_cpu): Add psw_mask so that reserved bits + can be masked out. + + * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr" + instructions from here. + * v850.igen (ldsr, stsr): To here. Mask out reserved bits when + setting PSW. + + * interp.c (sim_open): Set psw_mask if machine known. + +Tue Sep 16 10:20:00 1997 Andrew Cagney + + * v850-dc: Add rule to diferentiate between breakpoint and divh. + * v850.igen (break): New instruction, breakpoint simulator. + * v850.igen (breakpoint): Enable. Change to a 32bit instruction. + +Mon Sep 15 18:44:05 1997 Jim Wilson + + * simops.c (Multiply64): Don't store into register zero. + +Tue Sep 16 09:02:00 1997 Andrew Cagney + + * Makefile.in (semantics.o): Add dependency. + + * sim-main.h (SAVE_1, SAVE_2): Perform backward compatible save, + do not adjust CIA/NIA. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * simops.c (OP_300, OP_400, OP_70): Make behavour depend on PSW[US]. + + * simops.c: Move "divun", "sld.bu", "divhn", "divhun", "divn", + "divun", "pushml" code from here to v850.igen. + (divun): Make global. + (type3_regs): Make global + + * v850.igen: Move simops.c code to here. + + * interp.c (sim_create_inferior): For v850eq set US bit by + default. + + * interp.c (sim_open): Don't set arch, now set by + sim_analyze_program. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 15 14:39:34 1997 Andrew Cagney + + * simops.c (op_types): Move from here. + sim-main.h: To here. + + * sim-main.h (trace_input, trace_output), simops.c: Make global. + + * simops.c (OP_60): Move "jmp" code from here. + * v850.igen (jmp): To here. + + * simops.c (OP_60): Move "sld.bu" code from here. + * v850.igen (sld.bu): To here. + +Fri Sep 12 15:11:03 1997 Andrew Cagney + + * v850.igen (prepare, ...): Add to v850eq architecture. + + * interp.c (sim_open): Default to v850eq. + + * interp.c (sim_open): Default to v850e. + * sim-main.h (signal.h): Include. + + * v850.igen (illegal): Report/halt illegal instructions. + + * Makefile.in (SIM_EXTRA_CFLAGS): Add SIM_RESERVED_BITS. + + * configure.in: Add reserved bits option. + * configure: Regenerate. + +Thu Sep 11 08:40:03 1997 Andrew Cagney + + * interp.c (sim_open): Use sim_do_commandf instead of asprintf. + + * sim-main.h (INSN_NAME): + + * Makefile.in (INCLUDE): Add SIM_EXTRA_DEPS. + (SIM_EXTRA_DEPS): Add itable.h + (tmp-gencode): Does not depend on simops.h + + * sim-main.h (itable.h): Include. + (MAX_INSNS, INSN_NAME): Define. + + * interp.c: Compute inttype from the interrupt_names index that + was passed in. + +Wed Sep 10 10:25:40 1997 Andrew Cagney + + * simops.c (trace_input): Use trace_printf instead of + sim_io_printf. + (trace_output): Ditto. + (trace_input): Only trace when TRACE_ALU_P. Delete code + disasembling instruction. + (trace_output): Only trace when TRACE_ALU_P. + +Tue Sep 9 01:29:50 1997 Andrew Cagney + + * simops.c (trace_input, trace_output): Use sim_io_printf. + (OP_620): Pass correct argument to trace. + (OP_E607E0): Ditto. + (trace_input): Obtain prog_bfd, text_start et.al from simulator + struct. + +Mon Sep 8 21:03:52 1997 Andrew Cagney + + * v850.igen: New file. + * v850-dc: New file. + +Mon Sep 8 18:33:04 1997 Andrew Cagney + + + * sim-main.h (SEXT16): Delete, use EXTEND16. + (SEXT8): Delete, use EXTEND8. + (SEXT32): Delete, used? + (SEXT40, SEXT44, SEXT64): Use UNSIGNED64 for constants, not ...LL. + (WITH_TARGET_WORD_MSB): Define as 31. v850 little bit endian. + + * simops.c: Use EXTEND15 from sim-bits instead of SEXT16. + + * sim-main.h (DEBUG_TRACE, DEBUG_VALUES, v850_debug): Delete, + replace with TRACE_INSN_P and TRACE_ALU_P. + + * simops.c (trace_input, trace_output): Update. + + * interp.c (sim_engine_run): Delete. + (lookup_hash): Delete. + (sim_open): Do not fill hash table. + (sim_trace): Delete. + +Fri Sep 5 17:04:48 1997 Andrew Cagney + + * simops.c (OP_FFFF): Use sim_engine_halt. + (OP_12007E0): Ditto. + (OP_10007E0): Ditto. + + * sim-main.h (struct sim_cpu): Delete member exception. Using + sim-engine et.al. + + * interp.c (sim_info): Do not do anything in sim-info. + (sim_stop): Delete, replace with sim-stop. + (sim_stop_reason): Delete, replace with sim-reason. + + * sim-main.h (WITH_WATCHPOINTS): Define. + (WITH_MODULO_MEMORY): Define + + * Makefile.in (SIM_OBJS): Add sim-resume, sim-watch, sim-stop, + sim-reason. + + * interp.c (enum interrupt_cond_type): Delete. + (struct interrupt_generator): Delete. + (enum interrupt_type): Drop int_none. + (sim_open): Initialize WATCHPOINT module. + (sim_resume, sim_run): Rename sim_resume to sim_run. + (sim_engine_run): Replace interrupt code with call to sim-events. + (sim_set_interrupt): Delete. + (sim_parse_number): Delete. + +Thu Sep 4 17:21:23 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Sep 4 18:11:37 1997 Andrew Cagney + + * simops.c (fetch_argv): New function, fetch a arg vector from + simulator memory. + + * configure.in: Check for fork, execve, execv. + * configure: Regenerate. + + * interp.c (sim_store_register, sim_fetch_register): Use H2T_4 and + T2H_4 for byte swapping. + + * sim-main.h, interp.c (get_word, get_half, get_byte, put_word, + put_half, put_byte): Delete. + + * Makefile.in (SIM_OBJS): Add sim-memopt.o module. + + * sim-main.h (load_mem, store_mem): Redefine as macros. + (IMEM, IMEM_IMMED): New macros - fetch instructions. + + * simops.c (OP_10007E0): For SYS_read, SYS_write, SYS_open + transfer data via a buffer. + (fetch_str): New function, fetch string from memory. + + * Makefile.in (SIM_OBJS): Add sim-hrw.o module. + + * interp.c (sim_open): Establish memory maps using sim-memopt.c + via sim_do_command. + (sim_do_command): Print error if memory-map command is used. Call + sim_args_command. + (map): Delete, replaced by sim-core. + (sim_memory_init): Delete, replaced by sim-core. + (sim_set_memory_map): Delete, replaced by sim-memopt. + (load_mem): Delete, replaced by sim-core. + (store_mem): Delete, replaced by sim-core. + (sim_write): Delete, replaced by sim-hrw. + (sim_read): Delete, replaced by sim-hrw. + + * sim-main.h (struct sim_state): Remove memory members, using + sim-core.c + +Wed Sep 3 10:18:55 1997 Andrew Cagney + + * sim-main.h: Replace SIM_HAVE_FLATMEM with mem ptr. + * interp.c (map): Do not add to a void pointer. + + * Makefile.in (INCLUDE): Add sim-main.h + + * configure.in: Check for time.h + * configure: Re-generate. + + * interp.c (struct interrupt_generator): Make time unsigned long, + address SIM_ADDR. + (sim_resume): Make oldpc SIM_ADDR. + (struct hash_entry): Make mask/opcode unsigned. + + * v850_sim.h (struct simops ): Make opcode and mask unsigned. + + * simops.c (utime.h): Include if available. + (OP_10007E0): Check for UTIME function. + (divun): Put parentheses around shift argument. + (OP_640): Put parentheses around shift argument, was wrong. + (OP_107F0): Return something. + + * interp.c (sim_parse_number): Use strtoul not strtol. + (sim_resume): Use sim_elapsed_time_get to keep track of the time. + + * configure.in (SIM_AC_OPTION_WARNINGS): Add. + (SIM_AC_OPTION_ENDIAN): Set to hardwired big. + (SIM_AC_OPTION_HOST_ENDIAN): Add. + (AC_CHECK_FUNCS): Add utime. + (AC_CHECK_HEADERS): Add stdlib.h, string.h, strings.h, utime.h + configure: Regenerate. + + + * Makefile.in (SIM_RUN_OBJS): Use nrun.o. + (SIM_OBJS): Add sim-io.o, sim-hload.o, sim-utils.o, sim-options.o, + sim-config.o, sim-module.o, sim-events.o, sim-core.o, + sim-endian.o, sim-engine.o, sim-trace.o, sim-profile.o + (SIM_ENDIAN, SIM_WARNGINS): Define. + + * simops.c (OP_10007E0): Use sim_io_* for transfers. + + * interp.c (sim_resume): Pass sd around. + + * simops.c (sim-main.h): Include. + + * gencode.c (write_template): Generate #include sim-main.h. + (write_opcodes): Ditto. + + * interp.c (prog_bfd, prog_bfd_was_opened_p): Delete. + (v850_callback): Ditto. + (sim_kind, myname): Ditto. + (lookup_hash): Pass SD. Use sim_io_error. + (sim_set_memory_map): Pass in SD, use. + (init_system): Pass in SD, use. + (sim_open): Update. + (sim_set_profile): Delete. + (sim_set_profile_size): Delete. + (do_interrupt): Pass in SD, use. + (sim_info): Use sim_io_printf. + (sim_create_inferior): Reset registers. Set PC from prog_bfd + argument. + (sim_load): Delete, use common/sim-hload.c + (sim_size): Rename to sim_memory_init. + (sim_write): Remove call to init_system. + (init_system): Delete. + (sim_set_callbacks): Delete. + (sim_set_interrupt): Pass in SD, use. + (start_time): Delete. + + * v850_sim.h: Remove everything except `struct simops' from here. + * sim-main.h: Move most to here. + * gencode.c: Move #includes to here. + + * sim-main.h(struct _sim_cpu): Rename struct _state. + (#define PC, et.al.): Update + (v850_callback): Delete. Replaced with SIM_DESC arg. + (int8, uint8, int16, uint16, int32, uint32): Define types using + unsigned8 et.al from common/sim-types.h. + * sim-main.h (State): Define as STATE_CPU. + +Mon Sep 1 12:07:55 1997 Andrew Cagney + + * configure.in: Check for time, chmod. + * configure: Regenerate. + * simops.c (SYS_time, SYS_chmod): Use HAVE_TIME, HAVE_CHMOD. + + * simops.c (../../libgloss/v850/sys/syscall.h): Include instead of + sys/syscall.h. + (OP_10007E0): Check the existance each SYS_* macro independantly. + + * v850_sim.h (SIGQUIT, SIGTRAP): Only define if missing. + +Wed Aug 27 18:13:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Tue Aug 26 10:42:38 1997 Andrew Cagney + + * interp.c (sim_kill): Delete. + (sim_create_inferior): Add ABFD argument. + (sim_load): Move setting of PC from here. + (sim_create_inferior): To here. + +Mon Aug 25 17:50:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 11:31:23 1997 Andrew Cagney + + * interp.c (sim_open): Add ABFD argument. + +Fri Aug 22 10:39:28 1997 Nick Clifton + + * simops.c (bsh): Only set CY flag if either of the bottom + bytes is zero. + + * simops.c (prepare, dispose): Lower numbered + registers go to higher numbered address. + + * simops.c (unsigned divide instructions): S bit set if result has + top bit set. + + * simops.c (pushml, pushmh, popml, popmh): Lower numbered + registers go to higher numbered address. + +Wed Aug 20 13:56:35 1997 Nick Clifton + + * simops.c (OP_107E0, OP_107F0, OP_307E0, OP_307F0): Use correct + interpretation of SR bit in list18 structure. + (divn, divun): New functions to perform N step divide functions. + +Mon Aug 18 10:59:02 1997 Nick Clifton + + * simops.c (OP_300, OP_400, OP_60, OP_70): Support variant opcodes + with US bit set in the PSW. + +Wed Aug 13 19:06:55 1997 Nick Clifton + + * interp.c (sim_resume): Opcode functions return amount to be + added to PC and all opcodes take a standard format in the OP[] + array. + + (do_format_*): Functions removed. + + * v850_sim.h (SP, EP): New register mnemonics. + + * gencode.c (write_header): Functions prototypes return an + integer. + + * simops.c: Opcode functions return amount to be added to PC. + + * v850_sim.h (CTPC, CTPSW, CTBP): New register mnemonics. + + * simops.c: Add support for v850e instructions. + + * simops.c: Add support for v850eq instructions. + +Tue May 20 10:24:14 1997 Andrew Cagney + + * interp.c (sim_open): Add callback argument. + (sim_set_callbacks): Delete SIM_DESC argument. + +Thu Apr 24 00:39:51 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 23 17:20:16 1997 Doug Evans + + * interp.c (prog_bfd_was_opened_p): New static local. + (prog_bfd): New global variable. + (sim_open): Undo patch to add -E support. + (sim_close): Close prog_bfd if sim_load opened it. + (sim_load): Record bfd of loaded file in prog_bfd. + * simops.c (prog_bfd): Renamed from exec_bfd. + +Fri Apr 18 14:17:12 1997 Andrew Cagney + + * interp.c (sim_stop): Stub function. + +Thu Apr 17 03:53:18 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Add sim-load.o. + * interp.c (sim_kind, myname): New static locals. + (sim_open): Set sim_kind, myname. Ignore -E arg. + (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to + load file into simulator. Set start address from bfd. + (sim_create_inferior): Return SIM_RC. Delete arg start_address. + +Wed Apr 16 19:53:55 1997 Andrew Cagney + + * simops.c (OP_10007E0): Only provide system calls SYS_execv, + SYS_wait, SYS_wait, SYS_utime, SYS_time if defined by the host. + +Mon Apr 7 15:45:02 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Apr 2 15:06:28 1997 Doug Evans + + * interp.c (sim_open): New arg `kind'. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:34:19 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 19 01:14:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 17 15:10:07 1997 Andrew Cagney + + * configure: Re-generate. + +Fri Mar 14 10:34:11 1997 Michael Meissner + + * configure: Regenerate to track ../common/aclocal.m4 changes. + +Thu Mar 13 13:00:54 1997 Doug Evans + + * interp.c (sim_open): New SIM_DESC result. Argument is now + in argv form. + (other sim_*): New SIM_DESC argument. + +Tue Feb 4 13:33:30 1997 Doug Evans + + * Makefile.in (@COMMON_MAKEFILE_FRAG): Use + COMMON_{PRE,POST}_CONFIG_FRAG instead. + * configure.in: sinclude ../common/aclocal.m4. + * configure: Regenerated. + +Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) + + * configure configure.in Makefile.in: Update to new configure + scheme which is more compatible with WinGDB builds. + * configure.in: Improve comment on how to run autoconf. + * configure: Re-run autoconf to get new ../common/aclocal.m4. + * Makefile.in: Use autoconf substitution to install common + makefile fragment. + +Mon Jan 20 16:05:34 1997 Michael Meissner + + * simops.c (OP_{E0,2E0,6E0}): The multiply operations sign extend, + not zero extend. + +Tue Jan 14 17:06:03 1997 Stu Grossman (grossman@critters.cygnus.com) + + * simops.c: Put ifdefs around things to make MSVC happy. Get rid + of unistd.h. Disable SYS_stat, SYS_chown, SYS_time, SYS_times, + SYS_gettimeofday and SYS_utime from MSVC. + +Tue Dec 31 18:11:13 1996 Michael Meissner + + * simops.c (OP_10007E0): Know that kill encodes the signal number + via: 0xdead0000 | signal and turn it back into a signal. + +Fri Dec 27 14:44:06 1996 Michael Meissner + + * v850_sim.h (SIG_V850_EXIT): Define as -1. + + * interp.c (sim_open): Cast calloc function. + (sim_stop_reason): If signal is SIG_V850_EXIT, inform gdb the + program exited with the appropriate exit code. + (sim_set_interrupt): Declare buildargv. + + * simops.c (OP_10007E0): Make exit signal normal exit. Make time + type correct and work on big endian systems. + +Wed Nov 20 02:18:44 1996 Doug Evans + + * Makefile.in: Delete stuff moved to ../common/Make-common.in. + (SIM_OBJS,SIM_EXTRA_CFLAGS,SIM_EXTRA_CLEAN): Define. + * configure.in: Simplify using macros in ../common/aclocal.m4. + Call AC_CHECK_HEADERS(unistd.h). + * configure: Regenerated. + * config.in: New file. + * simops.c: #include "config.h". #include if present. + +Sun Nov 3 23:02:54 1996 Stan Shebs + + * v850_sim.h (State): New slots dummy_mem, pending_nmi. + (EIPC, etc): New macros for system registers. + * simops.c, interp.c: Use everywhere. + + * interp.c: Add support for interrupts issued by interrupt + generators, either PC- or time-based. Controlled by simulator + command "sim interrupt". + + * interp.c: Add support for variable-size allocation of memory, + via simulator command "sim memory-map". + (map): Issue SIGSEGV for references to invalid memory regions. + +Thu Oct 31 14:44:10 1996 Gavin Koch + + * simops.c: Include for struct timeval and + struct timezone. + +Wed Oct 30 08:49:10 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c (OP_10007E0): Handle SYS_times and SYS_gettimeofday. + + * simops.c (OP_10007E0): Handle SYS_time. + +Tue Oct 29 14:22:55 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Include . + (OP_10007E0): Handle SYS_stat. + +Thu Oct 24 12:26:35 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c (OP_10007E0): Don't declare errno. + + * simops.c (OP_500): Mask off low bit in displacement + for sld.w. + (OP_501): Similarly. + + * simops.c (OP_500): Fix displacement handling for sld.w. + (OP_501): Similarly for sst.w. + + * simops.c (trace_input): Remove all references to SEXT7. + (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement + is zero extended for sst/sld instructions. + * v850_sim.h (SEX7): Delete. It's no longer needed (and it + was incorrect anyway). + +Thu Oct 24 10:33:33 1996 Stu Grossman (grossman@critters.cygnus.com) + + * Makefile.in: Get rid of srcroot. Set all INSTALL macros via + autoconf. + * gencode.c (write_opcodes): Pad operands field to account for + MSVC braindamage. + * simops.c: Include errno.h. Exclude SYS_chown, since MSVC + doesn't support it. (Why is this here in the first place?!?) + * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's. + Change number of operands in struct simops from 9 to 6. Define + SIGTRAP and SIGQUIT for MSVC. + +Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com) + + * interp.c (MEM_SIZE): It's now bytes, not a power of 2. + * (map): Add support for external mem in the 1->2 meg range. + Also, abort() when memory access is way out of bounds. (Better to + die than to give wrong result. (This will be fixed later.)) + * (sim_size): MEM_SIZE is now bytes, not shift factor. + +Tue Oct 1 15:53:24 1996 Gavin Koch + + * simops.c (trace_input): Swapped order of operands for output + output of OP_IMM_REG. Changed the fetching of the operands for + OP_LOAD32, and OP_STORE32 to work like op-function. + +Mon Sep 30 15:46:33 1996 Stu Grossman (grossman@critters.cygnus.com) + + * interp.c: Move includes of remote-sim.h and callback.h to + v850-sim.h. + * (lookup_hash): Add PC to report of hash failure. + * (map load_mem store_mem): New memory subsystem. Models V851 + memory system. + * (sim_write sim_read): Use new memory subsystem. + * (sim_resume): Don't load and save PC into EIPC anymore. Needed + to make user-defined traps work right. + * simops.c (OP_*): Use new memory subsystem. + * (OP_14007E0 (reti)): Implement reti. + * (OP_14996E0 (trap)): Implement user-defined traps. Move I/O to + trap 31. Use new memory subsystem. + * v850_sim.h: Prototypes for load_mem, store_mem and map. Use + load_mem in RLW macro. + +Fri Sep 27 18:34:09 1996 Stu Grossman (grossman@critters.cygnus.com) + + * gencode.c (write_opcodes): Output hex values for opcode mask + and patterns. + * interp.c (sim_resume): Save and restore PC from the appropriate + register. + * (sim_fetch_register sim_store_register): Fix byte-order problem + with reading and writing registers. + * simops.c (OP_FFFF): Implement pseudo-breakpoint insn. + +Fri Sep 27 17:42:37 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c (trace_input): Fix thinko. + +Wed Sep 18 09:54:12 1996 Michael Meissner + + * simops.c (exec_bfd): Rename from sim_bfd. + (trace_input): Ditto. + +Thu Sep 12 12:03:05 1996 Michael Meissner + + * simops.c (trace_input): Use find_nearest_line to print line + number, function name or file name of PC. + +Wed Sep 11 16:44:37 1996 Michael Meissner + + * simops.c: Add tracing support. Use SEXTxx macros instead of + doing hardwired shifts. + + * configure.in (--enable-sim-cflags): Add switch to add additional + flags to simulator buld. If --enable-sim-cflags=trace, turn on + tracing. + * configure: Regenerate. + + * Makefile.in: Don't require a VPATH capable make if configuring + in the same directory. Don't use CFLAGS for configuration flags. + Add flags from --enable-sim-cflags. Support canadian cross + builds. Rebuild whole simulator if include files change. + + * interp.c (v850_debug): New global for debugging. + (lookup_hash,sim_size,sim_set_profile): Use + printf_filtered callback, instead of calling printf directly. + (sim_{open,trace}): Enable tracing if -t and compiled for tracing. + + * v850_sim.h: Use limits.h to set the various sized types. + (SEXT{5,7,16,22}): New macros. + +Mon Sep 9 20:50:46 1996 Jeffrey A Law (law@cygnus.com) + + * interp.c (hash): Make this an inline function + when compiling with GCC. Simplify. + * simpos.c: Explicitly include "sys/syscall.h". Remove + some #if 0'd code. Enable more emulated syscalls. + +Wed Sep 4 01:48:55 1996 Jeffrey A Law (law@cygnus.com) + + * interp.c: Fix sign bit handling for add and sub instructions. + +Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com) + + * gencode.c: Fix various indention & style problems. + Remove test code. Remove #if 0 code. + * interp.c: Provide prototypes for all static functions. + Fix minor indention problems. + (sim_open, sim_resume): Remove unused variables. + (sim_read): Return type is "int". + * simops.c: Remove unused variables. + (divh): Make result of divide-by-zero zero. + (setf): Initialize result to keep compiler quiet. + (sar instructions): These just clear the overflow bit. + * v850_sim.h: Provide prototypes for put_byte, put_half + and put_word. + + * interp.c: OP should be an array of 32bit operands! + (v850_callback): Declare. + (do_format_5): Fix extraction of OP[0]. + (sim_size): Remove debugging printf. + (sim_set_callbacks): Do something useful. + (sim_stop_reason): Gross hacks to get c-torture running. + * simops.c: Simplify code for computing targets of bCC + insns. Invert 's' bit if 'ov' bit is set for some + instructions. Fix 'cy' bit handling for numerous + instructions. Make the simulator stop when a halt + instruction is encountered. Very crude support for + emulated syscalls (trap 0). + * v850_sim.h: Include "callback.h" and declare + v850_callback. Items in the operand array are 32bits. + +Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com) + + * interp.c (sim_resume): Fix code to check for a format 3 + opcode. + * simops.c: bCC insns only argument is a constant, not a + register value (duh...) + +Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix "not1" and "set1". + + * simops.c: Don't forget to initialize temp for + "ld.h" and "ld.w" + + * interp.c: Remove various debugging printfs. + + * simops.c: Fix satadd, satsub boundary case handling. + + * interp.c (hash): Fix. + * interp.c (do_format_8): Get operands correctly and + call the target function. + * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1". + +Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com) + + * interp.c (do_format_4): Get operands correctly and + call the target function. + * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b", + "sst.h", and "sst.w". + + * v850_sim.h: The V850 doesn't have split I&D spaces. Change + accordingly. Remove many unused definitions. + * interp.c: The V850 doesn't have split I&D spaces. Change + accordingly. + (get_longlong, get_longword, get_word): Deleted. + (write_longlong, write_longword, write_word): Deleted. + (get_operands): Deleted. + (get_byte, get_half, get_word): New functions. + (put_byte, put_half, put_word): New functions. + * simops.c: Remove unused functions. Rough cut at + "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns. + + * v850_sim.h (struct _state): Remove "psw" field. Add + "sregs" field. + (PSW): Remove bogus definition. + * simops.c: Change condition code handling to use the psw + register within the sregs array. Handle "ldsr" and "stsr". + + * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr". + + * interp.c (do_format_5): Get operands correctly and + call the target function. + (sim_resume): Don't do a PC update for format 5 instructions. + * simops.c: Handle "jarl" and "jmp" instructions. + + * simops.c: Fix minor typos. Handle "cmp", "setf", "tst" + "di", and "ei" instructions correctly. + + * interp.c (do_format_3): Get operands correctly and call + the target function. + * simops.c: Handle bCC instructions. + + * simops.c: Add condition code handling to shift insns. + Fix minor typos in condition code handling for other insns. + + * Makefile.in: Fix typo. + * simops.c: Add condition code handling to "sub" "subr" and + "divh" instructions. + + * interp.c (hash): Update to be more accurate. + (lookup_hash): Call hash rather than computing the hash + code here. + (do_format_1_2): Handle format 1 and format 2 instructions. + Get operands correctly and call the target function. + (do_format_6): Get operands correctly and call the target + function. + (do_formats_9_10): Rough cut so shift ops will work. + (sim_resume): Tweak to deal with format 1 and format 2 + handling in a single funtion. Don't update the PC + for format 3 insns. Fix typos. + * simops.c: Slightly reorganize. Add condition code handling + to "add", "addi", "and", "andi", "or", "ori", "xor", "xori" + and "not" instructions. + * v850_sim.h (reg_t): Registers are 32bits. + (_state): The V850 has 32 general registers. Add a 32bit + psw and pc register too. Add accessor macros + + * Makefile.in, interp.c, v850_sim.h: Bring over endianness + changes from the d10v simulator. + + * simops.c: Add shift support. + + * simops.c: Add multiply & divide support. Abort for system + instructions. + + * simops.c: Add logicals, mov, movhi, movea, add, addi, sub + and subr. No condition codes yet. + +Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com) + + * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h, + gencode.c, interp.c, simops.c: Created. + diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in new file mode 100644 index 0000000..7f65230 --- /dev/null +++ b/sim/v850/Makefile.in @@ -0,0 +1,142 @@ +# Makefile template for Configure for the V850 sim library. +# Copyright (C) 1996, 1997 Free Software Foundation, Inc. +# Written by Cygnus Support. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +## COMMON_PRE_CONFIG_FRAG + +SIM_OBJS = \ + $(SIM_NEW_COMMON_OBJS) \ + simops.o interp.o \ + itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \ + sim-engine.o \ + sim-hload.o \ + sim-hrw.o \ + sim-resume.o \ + sim-reason.o \ + sim-stop.o + +SIM_RUN_OBJS = nrun.o + +# List of extra dependencies. +# Generally this consists of simulator specific files included by sim-main.h. +SIM_EXTRA_DEPS = v850_sim.h sim-main.h simops.h itable.h + +# List of flags to always pass to $(CC) +SIM_EXTRA_CFLAGS = \ + -DDEBUG \ + -I$(srcdir)/../../newlib/libc/sys/sysnecv850 +SIM_EXTRA_CLEAN = clean-extra + +INCLUDE = $(sim_main_headers) $(SIM_EXTRA_DEPS) + +NL_TARGET = -DNL_TARGET_v850 + +## COMMON_POST_CONFIG_FRAG + +simops.h table.c: tmp-gencode +tmp-gencode: gencode + ./gencode >tmp-table.c + mv tmp-table.c table.c + ./gencode -h >tmp-simops.h + mv tmp-simops.h simops.h + touch tmp-gencode +gencode.o: gencode.c + $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gencode.c +v850-opc.o: $(srcdir)/../../opcodes/v850-opc.c + $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $< +gencode: gencode.o v850-opc.o + $(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.o v850-opc.o + + + +BUILT_SRC_FROM_IGEN = \ + icache.h \ + icache.c \ + idecode.h \ + idecode.c \ + semantics.h \ + semantics.c \ + model.h \ + model.c \ + support.h \ + support.c \ + itable.h \ + itable.c \ + engine.h \ + engine.c \ + irun.c +$(BUILT_SRC_FROM_IGEN): tmp-igen simops.h +# + +.PHONY: clean-igen +clean-igen: + rm -f $(BUILT_SRC_FROM_IGEN) + rm -f tmp-igen tmp-insns + +../igen/igen: + cd ../igen && $(MAKE) + +IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries +IGEN_INSN=$(srcdir)/v850.igen +IGEN_DC=$(srcdir)/v850-dc +tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen + cd ../igen && $(MAKE) + ../igen/igen \ + $(IGEN_TRACE) \ + -G gen-direct-access \ + -i $(IGEN_INSN) \ + -o $(IGEN_DC) \ + -x \ + -n icache.h -hc tmp-icache.h \ + -n icache.c -c tmp-icache.c \ + -n semantics.h -hs tmp-semantics.h \ + -n semantics.c -s tmp-semantics.c \ + -n idecode.h -hd tmp-idecode.h \ + -n idecode.c -d tmp-idecode.c \ + -n model.h -hm tmp-model.h \ + -n model.c -m tmp-model.c \ + -n support.h -hf tmp-support.h \ + -n support.c -f tmp-support.c \ + -n itable.h -ht tmp-itable.h \ + -n itable.c -t tmp-itable.c \ + -n engine.h -he tmp-engine.h \ + -n engine.c -e tmp-engine.c \ + -n irun.c -r tmp-irun.c + $(srcdir)/../../move-if-change tmp-icache.h icache.h + $(srcdir)/../../move-if-change tmp-icache.c icache.c + $(srcdir)/../../move-if-change tmp-idecode.h idecode.h + $(srcdir)/../../move-if-change tmp-idecode.c idecode.c + $(srcdir)/../../move-if-change tmp-semantics.h semantics.h + $(srcdir)/../../move-if-change tmp-semantics.c semantics.c + $(srcdir)/../../move-if-change tmp-model.h model.h + $(srcdir)/../../move-if-change tmp-model.c model.c + $(srcdir)/../../move-if-change tmp-support.h support.h + $(srcdir)/../../move-if-change tmp-support.c support.c + $(srcdir)/../../move-if-change tmp-itable.h itable.h + $(srcdir)/../../move-if-change tmp-itable.c itable.c + $(srcdir)/../../move-if-change tmp-engine.h engine.h + $(srcdir)/../../move-if-change tmp-engine.c engine.c + $(srcdir)/../../move-if-change tmp-irun.c irun.c + touch tmp-igen + +clean-extra: clean-igen + rm -f table.c simops.h gencode + +#interp.o: interp.c table.c $(INCLUDE) +simops.o: simops.c $(INCLUDE) targ-vals.h +#table.o: table.c +semantics.o: $(INCLUDE) diff --git a/sim/v850/acconfig.h b/sim/v850/acconfig.h new file mode 100644 index 0000000..f9b87a1 --- /dev/null +++ b/sim/v850/acconfig.h @@ -0,0 +1,15 @@ + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have catgets and don't want to use GNU gettext. */ +#undef HAVE_CATGETS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES diff --git a/sim/v850/config.in b/sim/v850/config.in new file mode 100644 index 0000000..a49ca9c --- /dev/null +++ b/sim/v850/config.in @@ -0,0 +1,183 @@ +/* config.in. Generated automatically from configure.in by autoheader. */ + +/* Define if using alloca.c. */ +#undef C_ALLOCA + +/* Define to empty if the keyword does not work. */ +#undef const + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define if you have alloca, as a function or macro. */ +#undef HAVE_ALLOCA + +/* Define if you have and it should be used (not on Ultrix). */ +#undef HAVE_ALLOCA_H + +/* Define if you have a working `mmap' system call. */ +#undef HAVE_MMAP + +/* Define as __inline if that's what the C compiler calls it. */ +#undef inline + +/* Define to `long' if doesn't define. */ +#undef off_t + +/* Define if you need to in order for stat and other things to work. */ +#undef _POSIX_SOURCE + +/* Define as the return type of signal handlers (int or void). */ +#undef RETSIGTYPE + +/* Define to `unsigned' if doesn't define. */ +#undef size_t + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown + */ +#undef STACK_DIRECTION + +/* Define if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define if your processor stores words with the most significant + byte first (like Motorola and SPARC, unlike Intel and VAX). */ +#undef WORDS_BIGENDIAN + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES + +/* Define if you have the __argz_count function. */ +#undef HAVE___ARGZ_COUNT + +/* Define if you have the __argz_next function. */ +#undef HAVE___ARGZ_NEXT + +/* Define if you have the __argz_stringify function. */ +#undef HAVE___ARGZ_STRINGIFY + +/* Define if you have the __setfpucw function. */ +#undef HAVE___SETFPUCW + +/* Define if you have the chmod function. */ +#undef HAVE_CHMOD + +/* Define if you have the chown function. */ +#undef HAVE_CHOWN + +/* Define if you have the dcgettext function. */ +#undef HAVE_DCGETTEXT + +/* Define if you have the execv function. */ +#undef HAVE_EXECV + +/* Define if you have the execve function. */ +#undef HAVE_EXECVE + +/* Define if you have the fork function. */ +#undef HAVE_FORK + +/* Define if you have the getcwd function. */ +#undef HAVE_GETCWD + +/* Define if you have the getpagesize function. */ +#undef HAVE_GETPAGESIZE + +/* Define if you have the getrusage function. */ +#undef HAVE_GETRUSAGE + +/* Define if you have the munmap function. */ +#undef HAVE_MUNMAP + +/* Define if you have the putenv function. */ +#undef HAVE_PUTENV + +/* Define if you have the setenv function. */ +#undef HAVE_SETENV + +/* Define if you have the setlocale function. */ +#undef HAVE_SETLOCALE + +/* Define if you have the sigaction function. */ +#undef HAVE_SIGACTION + +/* Define if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if you have the strcasecmp function. */ +#undef HAVE_STRCASECMP + +/* Define if you have the strchr function. */ +#undef HAVE_STRCHR + +/* Define if you have the time function. */ +#undef HAVE_TIME + +/* Define if you have the utime function. */ +#undef HAVE_UTIME + +/* Define if you have the header file. */ +#undef HAVE_ARGZ_H + +/* Define if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define if you have the header file. */ +#undef HAVE_LOCALE_H + +/* Define if you have the header file. */ +#undef HAVE_MALLOC_H + +/* Define if you have the header file. */ +#undef HAVE_NL_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PARAM_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_UTIME_H + +/* Define if you have the header file. */ +#undef HAVE_VALUES_H diff --git a/sim/v850/configure b/sim/v850/configure new file mode 100755 index 0000000..06efdb2 --- /dev/null +++ b/sim/v850/configure @@ -0,0 +1,4267 @@ +#! /bin/sh + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +sim_inline="-DDEFAULT_INLINE=0" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# This file is derived from `gettext.m4'. The difference is that the +# included macros assume Cygnus-style source and build trees. + +# Macro to add for using GNU gettext. +# Ulrich Drepper , 1995. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 3 + + + + + +# Search path for a program which passes the given test. +# Ulrich Drepper , 1996. +# +# This file file be copied and used freely without restrictions. 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"$ac_site_file" + fi +done + +if test -r "$cache_file"; then + echo "loading cache $cache_file" + . $cache_file +else + echo "creating cache $cache_file" + > $cache_file +fi + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +ac_exeext= +ac_objext=o +if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then + # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu. + if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then + ac_n= ac_c=' +' ac_t=' ' + else + ac_n=-n ac_c= ac_t= + fi +else + ac_n= ac_c='\c' ac_t= +fi + + + +echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 +echo "configure:689: checking how to run the C preprocessor" >&5 +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then +if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + # This must be in double quotes, not single quotes, because CPP may get + # substituted into the Makefile and "${CC-cc}" will confuse make. + CPP="${CC-cc} -E" + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:710: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -E -traditional-cpp" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:727: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -nologo -E" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:744: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP=/lib/cpp +fi +rm -f conftest* +fi +rm -f conftest* +fi +rm -f conftest* + ac_cv_prog_CPP="$CPP" +fi + CPP="$ac_cv_prog_CPP" +else + ac_cv_prog_CPP="$CPP" +fi +echo "$ac_t""$CPP" 1>&6 + +echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 +echo "configure:769: checking whether ${MAKE-make} sets \${MAKE}" >&5 +set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftestmake <<\EOF +all: + @echo 'ac_maketemp="${MAKE}"' +EOF +# GNU make sometimes prints "make[1]: Entering...", which would confuse us. +eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=` +if test -n "$ac_maketemp"; then + eval ac_cv_prog_make_${ac_make}_set=yes +else + eval ac_cv_prog_make_${ac_make}_set=no +fi +rm -f conftestmake +fi +if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then + echo "$ac_t""yes" 1>&6 + SET_MAKE= +else + echo "$ac_t""no" 1>&6 + SET_MAKE="MAKE=${MAKE-make}" +fi + +echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 +echo "configure:796: checking for POSIXized ISC" >&5 +if test -d /etc/conf/kconfig.d && + grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 +then + echo "$ac_t""yes" 1>&6 + ISC=yes # If later tests want to check for ISC. + cat >> confdefs.h <<\EOF +#define _POSIX_SOURCE 1 +EOF + + if test "$GCC" = yes; then + CC="$CC -posix" + else + CC="$CC -Xp" + fi +else + echo "$ac_t""no" 1>&6 + ISC= +fi + +echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 +echo "configure:817: checking for ANSI C header files" >&5 +if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#include +#include +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:830: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + ac_cv_header_stdc=yes +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "memchr" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "free" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. +if test "$cross_compiling" = yes; then + : +else + cat > conftest.$ac_ext < +#define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int main () { int i; for (i = 0; i < 256; i++) +if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); +exit (0); } + +EOF +if { (eval echo configure:897: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + : +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_header_stdc=no +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_header_stdc" 1>&6 +if test $ac_cv_header_stdc = yes; then + cat >> confdefs.h <<\EOF +#define STDC_HEADERS 1 +EOF + +fi + +echo $ac_n "checking for working const""... $ac_c" 1>&6 +echo "configure:921: checking for working const" >&5 +if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <j = 5; +} +{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; +} + +; return 0; } +EOF +if { (eval echo configure:975: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_const=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_const=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_c_const" 1>&6 +if test $ac_cv_c_const = no; then + cat >> confdefs.h <<\EOF +#define const +EOF + +fi + +echo $ac_n "checking for inline""... $ac_c" 1>&6 +echo "configure:996: checking for inline" >&5 +if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_inline=no +for ac_kw in inline __inline__ __inline; do + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_inline=$ac_kw; break +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +done + +fi + +echo "$ac_t""$ac_cv_c_inline" 1>&6 +case "$ac_cv_c_inline" in + inline | yes) ;; + no) cat >> confdefs.h <<\EOF +#define inline +EOF + ;; + *) cat >> confdefs.h <&6 +echo "configure:1036: checking for off_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_off_t=yes +else + rm -rf conftest* + ac_cv_type_off_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_off_t" 1>&6 +if test $ac_cv_type_off_t = no; then + cat >> confdefs.h <<\EOF +#define off_t long +EOF + +fi + +echo $ac_n "checking for size_t""... $ac_c" 1>&6 +echo "configure:1069: checking for size_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_size_t=yes +else + rm -rf conftest* + ac_cv_type_size_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_size_t" 1>&6 +if test $ac_cv_type_size_t = no; then + cat >> confdefs.h <<\EOF +#define size_t unsigned +EOF + +fi + +# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works +# for constant arguments. Useless! +echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 +echo "configure:1104: checking for working alloca.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +char *p = alloca(2 * sizeof(int)); +; return 0; } +EOF +if { (eval echo configure:1116: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_header_alloca_h=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_alloca_h=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_header_alloca_h" 1>&6 +if test $ac_cv_header_alloca_h = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA_H 1 +EOF + +fi + +echo $ac_n "checking for alloca""... $ac_c" 1>&6 +echo "configure:1137: checking for alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +# define alloca _alloca +# else +# if HAVE_ALLOCA_H +# include +# else +# ifdef _AIX + #pragma alloca +# else +# ifndef alloca /* predefined by HP cc +Olibcalls */ +char *alloca (); +# endif +# endif +# endif +# endif +#endif + +int main() { +char *p = (char *) alloca(1); +; return 0; } +EOF +if { (eval echo configure:1170: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_func_alloca_works=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_func_alloca_works=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_func_alloca_works" 1>&6 +if test $ac_cv_func_alloca_works = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA 1 +EOF + +fi + +if test $ac_cv_func_alloca_works = no; then + # The SVR3 libPW and SVR4 libucb both contain incompatible functions + # that cause trouble. Some versions do not even contain alloca or + # contain a buggy version. If you still want to use their alloca, + # use ar to extract alloca.o from them instead of compiling alloca.c. + ALLOCA=alloca.${ac_objext} + cat >> confdefs.h <<\EOF +#define C_ALLOCA 1 +EOF + + +echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 +echo "configure:1202: checking whether alloca needs Cray hooks" >&5 +if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5 | + egrep "webecray" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_os_cray=yes +else + rm -rf conftest* + ac_cv_os_cray=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_os_cray" 1>&6 +if test $ac_cv_os_cray = yes; then +for ac_func in _getb67 GETB67 getb67; do + echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:1232: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:1260: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + cat >> confdefs.h <&6 +fi + +done +fi + +echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 +echo "configure:1287: checking stack direction for C alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_c_stack_direction=0 +else + cat > conftest.$ac_ext < addr) ? 1 : -1; +} +main () +{ + exit (find_stack_direction() < 0); +} +EOF +if { (eval echo configure:1314: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_stack_direction=1 +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_stack_direction=-1 +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_c_stack_direction" 1>&6 +cat >> confdefs.h <&6 +echo "configure:1339: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:1349: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getpagesize +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:1378: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:1406: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + +echo $ac_n "checking for working mmap""... $ac_c" 1>&6 +echo "configure:1431: checking for working mmap" >&5 +if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_func_mmap_fixed_mapped=no +else + cat > conftest.$ac_ext < +#include +#include + +/* This mess was copied from the GNU getpagesize.h. */ +#ifndef HAVE_GETPAGESIZE +# ifdef HAVE_UNISTD_H +# include +# endif + +/* Assume that all systems that can run configure have sys/param.h. */ +# ifndef HAVE_SYS_PARAM_H +# define HAVE_SYS_PARAM_H 1 +# endif + +# ifdef _SC_PAGESIZE +# define getpagesize() sysconf(_SC_PAGESIZE) +# else /* no _SC_PAGESIZE */ +# ifdef HAVE_SYS_PARAM_H +# include +# ifdef EXEC_PAGESIZE +# define getpagesize() EXEC_PAGESIZE +# else /* no EXEC_PAGESIZE */ +# ifdef NBPG +# define getpagesize() NBPG * CLSIZE +# ifndef CLSIZE +# define CLSIZE 1 +# endif /* no CLSIZE */ +# else /* no NBPG */ +# ifdef NBPC +# define getpagesize() NBPC +# else /* no NBPC */ +# ifdef PAGESIZE +# define getpagesize() PAGESIZE +# endif /* PAGESIZE */ +# endif /* no NBPC */ +# endif /* no NBPG */ +# endif /* no EXEC_PAGESIZE */ +# else /* no HAVE_SYS_PARAM_H */ +# define getpagesize() 8192 /* punt totally */ +# endif /* no HAVE_SYS_PARAM_H */ +# endif /* no _SC_PAGESIZE */ + +#endif /* no HAVE_GETPAGESIZE */ + +#ifdef __cplusplus +extern "C" { void *malloc(unsigned); } +#else +char *malloc(); +#endif + +int +main() +{ + char *data, *data2, *data3; + int i, pagesize; + int fd; + + pagesize = getpagesize(); + + /* + * First, make a file with some known garbage in it. + */ + data = malloc(pagesize); + if (!data) + exit(1); + for (i = 0; i < pagesize; ++i) + *(data + i) = rand(); + umask(0); + fd = creat("conftestmmap", 0600); + if (fd < 0) + exit(1); + if (write(fd, data, pagesize) != pagesize) + exit(1); + close(fd); + + /* + * Next, try to mmap the file at a fixed address which + * already has something else allocated at it. If we can, + * also make sure that we see the same garbage. + */ + fd = open("conftestmmap", O_RDWR); + if (fd < 0) + exit(1); + data2 = malloc(2 * pagesize); + if (!data2) + exit(1); + data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1); + if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_FIXED, fd, 0L)) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data2 + i)) + exit(1); + + /* + * Finally, make sure that changes to the mapped area + * do not percolate back to the file as seen by read(). + * (This is a bug on some variants of i386 svr4.0.) + */ + for (i = 0; i < pagesize; ++i) + *(data2 + i) = *(data2 + i) + 1; + data3 = malloc(pagesize); + if (!data3) + exit(1); + if (read(fd, data3, pagesize) != pagesize) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data3 + i)) + exit(1); + close(fd); + unlink("conftestmmap"); + exit(0); +} + +EOF +if { (eval echo configure:1579: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_func_mmap_fixed_mapped=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_func_mmap_fixed_mapped=no +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6 +if test $ac_cv_func_mmap_fixed_mapped = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_MMAP 1 +EOF + +fi + + +# autoconf.info says this should be called right after AC_INIT. + + +ac_aux_dir= +for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do + if test -f $ac_dir/install-sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f $ac_dir/install.sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; } +fi +ac_config_guess=$ac_aux_dir/config.guess +ac_config_sub=$ac_aux_dir/config.sub +ac_configure=$ac_aux_dir/configure # This should be Cygnus configure. + + +# Do some error checking and defaulting for the host and target type. +# The inputs are: +# configure --host=HOST --target=TARGET --build=BUILD NONOPT +# +# The rules are: +# 1. You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:1652: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:1673: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:1691: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +if test "$program_transform_name" = s,x,x,; then + program_transform_name= +else + # Double any \ or $. echo might interpret backslashes. + cat <<\EOF_SED > conftestsed +s,\\,\\\\,g; s,\$,$$,g +EOF_SED + program_transform_name="`echo $program_transform_name|sed -f conftestsed`" + rm -f conftestsed +fi +test "$program_prefix" != NONE && + program_transform_name="s,^,${program_prefix},; $program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s,\$\$,${program_suffix},; $program_transform_name" + +# sed with no file args requires a program. +test "$program_transform_name" = "" && program_transform_name="s,x,x," + +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1735: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1764: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1814: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:1845: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:1879: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:1884: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:1912: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# ./install, which can be erroneously created by make from ./install.sh. +echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 +echo "configure:1955: checking for a BSD compatible install" >&5 +if test -z "$INSTALL"; then +if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS=":" + for ac_dir in $PATH; do + # Account for people who put trailing slashes in PATH elements. + case "$ac_dir/" in + /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + if test -f $ac_dir/$ac_prog; then + if test $ac_prog = install && + grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + else + ac_cv_path_install="$ac_dir/$ac_prog -c" + break 2 + fi + fi + done + ;; + esac + done + IFS="$ac_save_IFS" + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL="$ac_cv_path_install" + else + # As a last resort, use the slow shell script. We don't cache a + # path for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the path is relative. + INSTALL="$ac_install_sh" + fi +fi +echo "$ac_t""$INSTALL" 1>&6 + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +# Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2021: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="ranlib" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + +ALL_LINGUAS= + + for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \ +unistd.h values.h sys/param.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2055: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2065: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \ +__argz_count __argz_stringify __argz_next +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2095: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2123: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + + if test "${ac_cv_func_stpcpy+set}" != "set"; then + for ac_func in stpcpy +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2152: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2180: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + fi + if test "${ac_cv_func_stpcpy}" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_STPCPY 1 +EOF + + fi + + if test $ac_cv_header_locale_h = yes; then + echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 +echo "configure:2214: checking for LC_MESSAGES" >&5 +if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return LC_MESSAGES +; return 0; } +EOF +if { (eval echo configure:2226: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + am_cv_val_LC_MESSAGES=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + am_cv_val_LC_MESSAGES=no +fi +rm -f conftest* +fi + +echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6 + if test $am_cv_val_LC_MESSAGES = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_LC_MESSAGES 1 +EOF + + fi + fi + echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 +echo "configure:2247: checking whether NLS is requested" >&5 + # Check whether --enable-nls or --disable-nls was given. +if test "${enable_nls+set}" = set; then + enableval="$enable_nls" + USE_NLS=$enableval +else + USE_NLS=yes +fi + + echo "$ac_t""$USE_NLS" 1>&6 + + + USE_INCLUDED_LIBINTL=no + + if test "$USE_NLS" = "yes"; then + cat >> confdefs.h <<\EOF +#define ENABLE_NLS 1 +EOF + + echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 +echo "configure:2267: checking whether included gettext is requested" >&5 + # Check whether --with-included-gettext or --without-included-gettext was given. +if test "${with_included_gettext+set}" = set; then + withval="$with_included_gettext" + nls_cv_force_use_gnu_gettext=$withval +else + nls_cv_force_use_gnu_gettext=no +fi + + echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6 + + nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext" + if test "$nls_cv_force_use_gnu_gettext" != "yes"; then + nls_cv_header_intl= + nls_cv_header_libgt= + CATOBJEXT=NONE + + ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 +echo "configure:2286: checking for libintl.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2296: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 +echo "configure:2313: checking for gettext in libc" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return (int) gettext ("") +; return 0; } +EOF +if { (eval echo configure:2325: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libc=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libc=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 + + if test "$gt_cv_func_gettext_libc" != "yes"; then + echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 +echo "configure:2341: checking for bindtextdomain in -lintl" >&5 +ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lintl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 +echo "configure:2376: checking for gettext in libintl" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libintl=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libintl=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + fi + + if test "$gt_cv_func_gettext_libc" = "yes" \ + || test "$gt_cv_func_gettext_libintl" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_GETTEXT 1 +EOF + + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2416: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + if test "$MSGFMT" != "no"; then + for ac_func in dcgettext +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2450: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2478: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2505: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2540: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + CATOBJEXT=.gmo + DATADIRNAME=share +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CATOBJEXT=.mo + DATADIRNAME=lib +fi +rm -f conftest* + INSTOBJEXT=.mo + fi + fi + +else + echo "$ac_t""no" 1>&6 +fi + + + + if test "$CATOBJEXT" = "NONE"; then + nls_cv_use_gnu_gettext=yes + fi + fi + + if test "$nls_cv_use_gnu_gettext" = "yes"; then + INTLOBJS="\$(GETTOBJS)" + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2612: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2646: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2681: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + + USE_INCLUDED_LIBINTL=yes + CATOBJEXT=.gmo + INSTOBJEXT=.mo + DATADIRNAME=share + INTLDEPS='$(top_builddir)/../intl/libintl.a' + INTLLIBS=$INTLDEPS + LIBS=`echo $LIBS | sed -e 's/-lintl//'` + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + if test "$XGETTEXT" != ":"; then + if $XGETTEXT --omit-header /dev/null 2> /dev/null; then + : ; + else + echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6 + XGETTEXT=":" + fi + fi + + # We need to process the po/ directory. + POSUB=po + else + DATADIRNAME=share + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + # If this is used in GNU gettext we have to set USE_NLS to `yes' + # because some of the sources are only built for this goal. + if test "$PACKAGE" = gettext; then + USE_NLS=yes + USE_INCLUDED_LIBINTL=yes + fi + + for lang in $ALL_LINGUAS; do + GMOFILES="$GMOFILES $lang.gmo" + POFILES="$POFILES $lang.po" + done + + + + + + + + + + + + + + + if test "x$CATOBJEXT" != "x"; then + if test "x$ALL_LINGUAS" = "x"; then + LINGUAS= + else + echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 +echo "configure:2771: checking for catalogs to be installed" >&5 + NEW_LINGUAS= + for lang in ${LINGUAS=$ALL_LINGUAS}; do + case "$ALL_LINGUAS" in + *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;; + esac + done + LINGUAS=$NEW_LINGUAS + echo "$ac_t""$LINGUAS" 1>&6 + fi + + if test -n "$LINGUAS"; then + for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done + fi + fi + + if test $ac_cv_header_locale_h = yes; then + INCLUDE_LOCALE_H="#include " + else + INCLUDE_LOCALE_H="\ +/* The system does not provide the header . Take care yourself. */" + fi + + + if test -f $srcdir/po2tbl.sed.in; then + if test "$CATOBJEXT" = ".cat"; then + ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 +echo "configure:2799: checking for linux/version.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2809: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + msgformat=linux +else + echo "$ac_t""no" 1>&6 +msgformat=xopen +fi + + + sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed + fi + sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \ + $srcdir/po2tbl.sed.in > po2tbl.sed + fi + + if test "$PACKAGE" = "gettext"; then + GT_NO="#NO#" + GT_YES= + else + GT_NO= + GT_YES="#YES#" + fi + + + + MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs" + + + l= + + + if test -d $srcdir/po; then + test -d po || mkdir po + if test "x$srcdir" != "x."; then + if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then + posrcprefix="$srcdir/" + else + posrcprefix="../$srcdir/" + fi + else + posrcprefix="../" + fi + rm -f po/POTFILES + sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \ + < $srcdir/po/POTFILES.in > po/POTFILES + fi + + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. +for ac_hdr in stdlib.h string.h strings.h unistd.h time.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2878: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2888: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in sys/time.h sys/resource.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2918: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2928: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in fcntl.h fpu_control.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2958: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2968: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getrusage time sigaction __setfpucw +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2997: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3025: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + +# Check for socket libraries +echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6 +echo "configure:3052: checking for bind in -lsocket" >&5 +ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lsocket $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \ + -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'` + cat >> confdefs.h <&6 +fi + +echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6 +echo "configure:3099: checking for gethostbyname in -lnsl" >&5 +ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lnsl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \ + -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'` + cat >> confdefs.h <&6 +fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then + enableval="$enable_maintainer_mode" + case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) { echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap or --disable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then + enableval="$enable_sim_bswap" + case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) { echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags or --disable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then + enableval="$enable_sim_cflags" + case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug or --disable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then + enableval="$enable_sim_debug" + case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio or --disable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then + enableval="$enable_sim_stdio" + case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace or --disable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then + enableval="$enable_sim_trace" + case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile or --disable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then + enableval="$enable_sim_profile" + case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="" +fi + + + +echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 +echo "configure:3294: checking return type of signal handlers" >&5 +if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#ifdef signal +#undef signal +#endif +#ifdef __cplusplus +extern "C" void (*signal (int, void (*)(int)))(int); +#else +void (*signal ()) (); +#endif + +int main() { +int i; +; return 0; } +EOF +if { (eval echo configure:3316: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_type_signal=void +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_type_signal=int +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_type_signal" 1>&6 +cat >> confdefs.h <&6 +echo "configure:3336: checking for executable suffix" >&5 +if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$CYGWIN32" = yes; then +am_cv_exeext=.exe +else +cat > am_c_test.c << 'EOF' +int main() { +/* Nothing needed here */ +} +EOF +${CC-cc} -o am_c_test $CFLAGS $CPPFLAGS $LDFLAGS am_c_test.c $LIBS 1>&5 +am_cv_exeext=`ls am_c_test.* | grep -v am_c_test.c | sed -e s/am_c_test//` +rm -f am_c_test* +fi + +test x"${am_cv_exeext}" = x && am_cv_exeext=no +fi +EXEEXT="" +test x"${am_cv_exeext}" != xno && EXEEXT=${am_cv_exeext} +echo "$ac_t""${am_cv_exeext}" 1>&6 + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + + + +wire_endian="LITTLE_ENDIAN" +default_endian="" +# Check whether --enable-sim-endian or --disable-sim-endian was given. +if test "${enable_sim_endian+set}" = set; then + enableval="$enable_sim_endian" + case "${enableval}" in + b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";; + yes) if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + if test x"$default_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}" + else + echo "No hard-wired endian for target $target" 1>&6 + sim_endian="-DWITH_TARGET_BYTE_ORDER=0" + fi + fi;; + no) if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" + else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}" + else + echo "No default endian for target $target" 1>&6 + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0" + fi + fi;; + *) { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then + echo "Setting endian flags = $sim_endian" 6>&1 +fi +else + if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" +else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + sim_endian= + fi +fi +fi + +wire_alignment="" +default_alignment="NONSTRICT_ALIGNMENT" + +# Check whether --enable-sim-alignment or --disable-sim-alignment was given. +if test "${enable_sim_alignment+set}" = set; then + enableval="$enable_sim_alignment" + case "${enableval}" in + strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";; + nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";; + forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";; + yes) if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${default_alignment}" + else + echo "No hard-wired alignment for target $target" 1>&6 + sim_alignment="-DWITH_ALIGNMENT=0" + fi + fi;; + no) if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" + else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}" + else + echo "No default alignment for target $target" 1>&6 + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0" + fi + fi;; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then + echo "Setting alignment flags = $sim_alignment" 6>&1 +fi +else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" +else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + sim_alignment= + fi +fi +fi + + +# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given. +if test "${enable_sim_hostendian+set}" = set; then + enableval="$enable_sim_hostendian" + case "${enableval}" in + no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";; + b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";; + *) { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then + echo "Setting hostendian flags = $sim_hostendian" 6>&1 +fi +else + +if test "x$cross_compiling" = "xno"; then + echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6 +echo "configure:3490: checking whether byte ordering is bigendian" >&5 +if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_bigendian=unknown +# See if sys/param.h defines the BYTE_ORDER macro. +cat > conftest.$ac_ext < +#include +int main() { + +#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN + bogus endian macros +#endif +; return 0; } +EOF +if { (eval echo configure:3508: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + # It does; now see whether it defined to BIG_ENDIAN or not. +cat > conftest.$ac_ext < +#include +int main() { + +#if BYTE_ORDER != BIG_ENDIAN + not big endian +#endif +; return 0; } +EOF +if { (eval echo configure:3523: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_bigendian=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_bigendian=no +fi +rm -f conftest* +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +if test $ac_cv_c_bigendian = unknown; then +if test "$cross_compiling" = yes; then + { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; } +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_bigendian=no +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_bigendian=yes +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_c_bigendian" 1>&6 +if test $ac_cv_c_bigendian = yes; then + cat >> confdefs.h <<\EOF +#define WORDS_BIGENDIAN 1 +EOF + +fi + + if test $ac_cv_c_bigendian = yes; then + sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN" + else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN" + fi +else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=0" +fi +fi + + +# Check whether --enable-build-warnings or --disable-build-warnings was given. +if test "${enable_build_warnings+set}" = set; then + enableval="$enable_build_warnings" + build_warnings="-Wall -Wpointer-arith -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations" +case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting warning flags = $build_warnings" 6>&1 +fi +else + build_warnings="" +fi + + +default_sim_reserved_bits="1" +# Check whether --enable-sim-reserved-bits or --disable-sim-reserved-bits was given. +if test "${enable_sim_reserved_bits+set}" = set; then + enableval="$enable_sim_reserved_bits" + case "${enableval}" in + yes) sim_reserved_bits="-DWITH_RESERVED_BITS=1";; + no) sim_reserved_bits="-DWITH_RESERVED_BITS=0";; + *) { echo "configure: error: "--enable-sim-reserved-bits does not take a value"" 1>&2; exit 1; }; sim_reserved_bits="";; +esac +if test x"$silent" != x"yes" && test x"$sim_reserved_bits" != x""; then + echo "Setting reserved flags = $sim_reserved_bits" 6>&1 +fi +else + sim_reserved_bits="-DWITH_RESERVED_BITS=${default_sim_reserved_bits}" +fi + +wire_word_bitsize="32" +wire_word_msb="31" +wire_address_bitsize="" +wire_cell_bitsize="" +# Check whether --enable-sim-bitsize or --disable-sim-bitsize was given. +if test "${enable_sim_bitsize+set}" = set; then + enableval="$enable_sim_bitsize" + sim_bitsize= +case "${enableval}" in + 64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";; + 32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";; + 64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";; + 32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";; + 32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31" + else + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0" + fi ;; + 64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63" + else + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0" + fi ;; + *) { echo "configure: error: "--enable-sim-bitsize was given $enableval. Expected 32 or 64"" 1>&2; exit 1; } ;; +esac +# address bitsize +tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9]*,*//"` +case x"${tmp}" in + x ) ;; + x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;; + x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;; + * ) { echo "configure: error: "--enable-sim-bitsize was given address size $enableval. Expected 32 or 64"" 1>&2; exit 1; } ;; +esac +# cell bitsize +tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9*]*,*[0-9]*,*//"` +case x"${tmp}" in + x ) ;; + x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;; + x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;; + * ) { echo "configure: error: "--enable-sim-bitsize was given cell size $enableval. Expected 32 or 64"" 1>&2; exit 1; } ;; +esac +if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then + echo "Setting bitsize flags = $sim_bitsize" 6>&1 +fi +else + sim_bitsize="" +if test x"$wire_word_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize" +fi +if test x"$wire_word_msb" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb" +fi +if test x"$wire_address_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize" +fi +if test x"$wire_cell_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize" +fi +fi + + +for ac_func in time chmod utime fork execve execv chown +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3691: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3719: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in unistd.h stdlib.h string.h strings.h utime.h time.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3747: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3757: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set) 2>&1 | grep ac_space` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +DEFS=-DHAVE_CONFIG_H + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS </dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.12.2" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir +ac_given_INSTALL="$INSTALL" + +trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS < conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@sim_environment@%$sim_environment%g +s%@sim_alignment@%$sim_alignment%g +s%@sim_assert@%$sim_assert%g +s%@sim_bitsize@%$sim_bitsize%g +s%@sim_endian@%$sim_endian%g +s%@sim_hostendian@%$sim_hostendian%g +s%@sim_float@%$sim_float%g +s%@sim_scache@%$sim_scache%g +s%@sim_default_model@%$sim_default_model%g +s%@sim_hw_cflags@%$sim_hw_cflags%g +s%@sim_hw_objs@%$sim_hw_objs%g +s%@sim_hw@%$sim_hw%g +s%@sim_inline@%$sim_inline%g +s%@sim_packages@%$sim_packages%g +s%@sim_regparm@%$sim_regparm%g +s%@sim_reserved_bits@%$sim_reserved_bits%g +s%@sim_smp@%$sim_smp%g +s%@sim_stdcall@%$sim_stdcall%g +s%@sim_xor_endian@%$sim_xor_endian%g +s%@build_warnings@%$build_warnings%g +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g +s%@CC@%$CC%g +s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g +s%@INSTALL_DATA@%$INSTALL_DATA%g +s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g +s%@HDEFINES@%$HDEFINES%g +s%@AR@%$AR%g +s%@RANLIB@%$RANLIB%g +s%@SET_MAKE@%$SET_MAKE%g +s%@CPP@%$CPP%g +s%@ALLOCA@%$ALLOCA%g +s%@USE_NLS@%$USE_NLS%g +s%@MSGFMT@%$MSGFMT%g +s%@GMSGFMT@%$GMSGFMT%g +s%@XGETTEXT@%$XGETTEXT%g +s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g +s%@CATALOGS@%$CATALOGS%g +s%@CATOBJEXT@%$CATOBJEXT%g +s%@DATADIRNAME@%$DATADIRNAME%g +s%@GMOFILES@%$GMOFILES%g +s%@INSTOBJEXT@%$INSTOBJEXT%g +s%@INTLDEPS@%$INTLDEPS%g +s%@INTLLIBS@%$INTLLIBS%g +s%@INTLOBJS@%$INTLOBJS%g +s%@POFILES@%$POFILES%g +s%@POSUB@%$POSUB%g +s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g +s%@GT_NO@%$GT_NO%g +s%@GT_YES@%$GT_YES%g +s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g +s%@l@%$l%g +s%@MAINT@%$MAINT%g +s%@sim_bswap@%$sim_bswap%g +s%@sim_cflags@%$sim_cflags%g +s%@sim_debug@%$sim_debug%g +s%@sim_stdio@%$sim_stdio%g +s%@sim_trace@%$sim_trace%g +s%@sim_profile@%$sim_profile%g +s%@EXEEXT@%$EXEEXT%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + case "$ac_given_INSTALL" in + [/$]*) INSTALL="$ac_given_INSTALL" ;; + *) INSTALL="$ac_dots$ac_given_INSTALL" ;; + esac + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +s%@INSTALL@%$INSTALL%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where +# NAME is the cpp macro being defined and VALUE is the value it is being given. +# +# ac_d sets the value in "#define NAME VALUE" lines. +ac_dA='s%^\([ ]*\)#\([ ]*define[ ][ ]*\)' +ac_dB='\([ ][ ]*\)[^ ]*%\1#\2' +ac_dC='\3' +ac_dD='%g' +# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE". +ac_uA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_uB='\([ ]\)%\1#\2define\3' +ac_uC=' ' +ac_uD='\4%g' +# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE". +ac_eA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_eB='$%\1#\2define\3' +ac_eC=' ' +ac_eD='%g' + +if test "${CONFIG_HEADERS+set}" != set; then +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +fi +for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + echo creating $ac_file + + rm -f conftest.frag conftest.in conftest.out + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + cat $ac_file_inputs > conftest.in + +EOF + +# Transform confdefs.h into a sed script conftest.vals that substitutes +# the proper values into config.h.in to produce config.h. And first: +# Protect against being on the right side of a sed subst in config.status. +# Protect against being in an unquoted here document in config.status. +rm -f conftest.vals +cat > conftest.hdr <<\EOF +s/[\\&%]/\\&/g +s%[\\$`]%\\&%g +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp +s%ac_d%ac_u%gp +s%ac_u%ac_e%gp +EOF +sed -n -f conftest.hdr confdefs.h > conftest.vals +rm -f conftest.hdr + +# This sed command replaces #undef with comments. This is necessary, for +# example, in the case of _POSIX_SOURCE, which is predefined and required +# on some systems where configure will not decide to define it. +cat >> conftest.vals <<\EOF +s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */% +EOF + +# Break up conftest.vals because some shells have a limit on +# the size of here documents, and old seds have small limits too. + +rm -f conftest.tail +while : +do + ac_lines=`grep -c . conftest.vals` + # grep -c gives empty output for an empty file on some AIX systems. + if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi + # Write a limited-size here document to conftest.frag. + echo ' cat > conftest.frag <> $CONFIG_STATUS + sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS + echo 'CEOF + sed -f conftest.frag conftest.in > conftest.out + rm -f conftest.in + mv conftest.out conftest.in +' >> $CONFIG_STATUS + sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail + rm -f conftest.vals + mv conftest.tail conftest.vals +done +rm -f conftest.vals + +cat >> $CONFIG_STATUS <<\EOF + rm -f conftest.frag conftest.h + echo "/* $ac_file. Generated automatically by configure. */" > conftest.h + cat conftest.in >> conftest.h + rm -f conftest.in + if cmp -s $ac_file conftest.h 2>/dev/null; then + echo "$ac_file is unchanged" + rm -f conftest.h + else + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + fi + rm -f $ac_file + mv conftest.h $ac_file + fi +fi; done + +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +srcdir=$ac_given_srcdir +while test -n "$ac_sources"; do + set $ac_dests; ac_dest=$1; shift; ac_dests=$* + set $ac_sources; ac_source=$1; shift; ac_sources=$* + + echo "linking $srcdir/$ac_source to $ac_dest" + + if test ! -r $srcdir/$ac_source; then + { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; } + fi + rm -f $ac_dest + + # Make relative symlinks. + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'` + if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then + # The dest file is in a subdirectory. + test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir" + ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dest_dir_suffix. + ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dest_dir_suffix= ac_dots= + fi + + case "$srcdir" in + [/$]*) ac_rel_source="$srcdir/$ac_source" ;; + *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;; + esac + + # Make a symlink if possible; otherwise try a hard link. + if ln -s $ac_rel_source $ac_dest 2>/dev/null || + ln $srcdir/$ac_source $ac_dest; then : + else + { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; } + fi +done +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +case "x$CONFIG_FILES" in + xMakefile*) + echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp + ;; + esac + case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + + diff --git a/sim/v850/configure.in b/sim/v850/configure.in new file mode 100644 index 0000000..03e892d --- /dev/null +++ b/sim/v850/configure.in @@ -0,0 +1,18 @@ +dnl Process this file with autoconf to produce a configure script. +sinclude(../common/aclocal.m4) +AC_PREREQ(2.5)dnl +AC_INIT(Makefile.in) + +SIM_AC_COMMON + +SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN) +SIM_AC_OPTION_ALIGNMENT(,NONSTRICT_ALIGNMENT) +SIM_AC_OPTION_HOSTENDIAN +SIM_AC_OPTION_WARNINGS +SIM_AC_OPTION_RESERVED_BITS +SIM_AC_OPTION_BITSIZE(32,31) + +AC_CHECK_FUNCS(time chmod utime fork execve execv chown) +AC_CHECK_HEADERS(unistd.h stdlib.h string.h strings.h utime.h time.h) + +SIM_AC_OUTPUT diff --git a/sim/v850/gencode.c b/sim/v850/gencode.c new file mode 100644 index 0000000..05ce866 --- /dev/null +++ b/sim/v850/gencode.c @@ -0,0 +1,149 @@ +#include +#include +#include "ansidecl.h" +#include "opcode/v850.h" +#include + +static void write_header PARAMS ((void)); +static void write_opcodes PARAMS ((void)); +static void write_template PARAMS ((void)); + +long Opcodes[512]; +static int curop=0; + +int +main (argc, argv) + int argc; + char *argv[]; +{ + if ((argc > 1) && (strcmp (argv[1], "-h") == 0)) + write_header(); + else if ((argc > 1) && (strcmp (argv[1], "-t") == 0)) + write_template (); + else + write_opcodes(); + return 0; +} + + +static void +write_header () +{ + struct v850_opcode *opcode; + + for (opcode = (struct v850_opcode *)v850_opcodes; opcode->name; opcode++) + printf("int OP_%X PARAMS ((void));\t\t/* %s */\n", + opcode->opcode, opcode->name); +} + + +/* write_template creates a file all required functions, ready */ +/* to be filled out */ + +static void +write_template () +{ + struct v850_opcode *opcode; + int i,j; + + printf ("#include \"sim-main.h\"\n"); + printf ("#include \"v850_sim.h\"\n"); + printf ("#include \"simops.h\"\n"); + + for (opcode = (struct v850_opcode *)v850_opcodes; opcode->name; opcode++) + { + printf("/* %s */\nvoid\nOP_%X (void)\n{\n", opcode->name, opcode->opcode); + + /* count operands */ + j = 0; + for (i = 0; i < 6; i++) + { + int flags = v850_operands[opcode->operands[i]].flags; + + if (flags & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_CC)) + j++; + } + switch (j) + { + case 0: + printf ("printf(\" %s\\n\");\n", opcode->name); + break; + case 1: + printf ("printf(\" %s\\t%%x\\n\", OP[0]);\n", opcode->name); + break; + case 2: + printf ("printf(\" %s\\t%%x,%%x\\n\",OP[0],OP[1]);\n", + opcode->name); + break; + case 3: + printf ("printf(\" %s\\t%%x,%%x,%%x\\n\",OP[0],OP[1],OP[2]);\n", + opcode->name); + break; + default: + fprintf (stderr,"Too many operands: %d\n", j); + } + printf ("}\n\n"); + } +} + +static void +write_opcodes () +{ + struct v850_opcode *opcode; + int i, j; + int numops; + + /* write out opcode table */ + printf ("#include \"sim-main.h\"\n"); + printf ("#include \"v850_sim.h\"\n"); + printf ("#include \"simops.h\"\n\n"); + printf ("struct simops Simops[] = {\n"); + + for (opcode = (struct v850_opcode *)v850_opcodes; opcode->name; opcode++) + { + printf (" { 0x%x,0x%x,OP_%X,", + opcode->opcode, opcode->mask, opcode->opcode); + + Opcodes[curop++] = opcode->opcode; + + /* count operands */ + j = 0; + for (i = 0; i < 6; i++) + { + int flags = v850_operands[opcode->operands[i]].flags; + + if (flags & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_CC)) + j++; + } + printf ("%d,{",j); + + j = 0; + numops = 0; + for (i = 0; i < 6; i++) + { + int flags = v850_operands[opcode->operands[i]].flags; + int shift = v850_operands[opcode->operands[i]].shift; + + if (flags & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_CC)) + { + if (j) + printf (", "); + printf ("%d,%d,%d", shift, + v850_operands[opcode->operands[i]].bits,flags); + j = 1; + numops++; + } + } + + switch (numops) + { + case 0: + printf ("0,0,0"); + case 1: + printf (",0,0,0"); + } + + printf ("}},\n"); + } + printf ("{ 0,0,NULL,0,{0,0,0,0,0,0}},\n};\n"); +} diff --git a/sim/v850/interp.c b/sim/v850/interp.c new file mode 100644 index 0000000..0ce5e3a --- /dev/null +++ b/sim/v850/interp.c @@ -0,0 +1,360 @@ +#include "sim-main.h" +#include "sim-options.h" +#include "v850_sim.h" +#include "sim-assert.h" +#include "itable.h" + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif + +#include "bfd.h" + +#ifndef INLINE +#ifdef __GNUC__ +#define INLINE inline +#else +#define INLINE +#endif +#endif + +static const char * get_insn_name (sim_cpu *, int); + +/* For compatibility */ +SIM_DESC simulator; + + + +/* v850 interrupt model */ + +enum interrupt_type +{ + int_reset, + int_nmi, + int_intov1, + int_intp10, + int_intp11, + int_intp12, + int_intp13, + int_intcm4, + num_int_types +}; + +char *interrupt_names[] = { + "reset", + "nmi", + "intov1", + "intp10", + "intp11", + "intp12", + "intp13", + "intcm4", + NULL +}; + +static void +do_interrupt (sd, data) + SIM_DESC sd; + void *data; +{ + char **interrupt_name = (char**)data; + enum interrupt_type inttype; + inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names); + + /* For a hardware reset, drop everything and jump to the start + address */ + if (inttype == int_reset) + { + PC = 0; + PSW = 0x20; + ECR = 0; + sim_engine_restart (sd, NULL, NULL, NULL_CIA); + } + + /* Deliver an NMI when allowed */ + if (inttype == int_nmi) + { + if (PSW & PSW_NP) + { + /* We're already working on an NMI, so this one must wait + around until the previous one is done. The processor + ignores subsequent NMIs, so we don't need to count them. + Just keep re-scheduling a single NMI until it manages to + be delivered */ + if (STATE_CPU (sd, 0)->pending_nmi != NULL) + sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi); + STATE_CPU (sd, 0)->pending_nmi = + sim_events_schedule (sd, 1, do_interrupt, data); + return; + } + else + { + /* NMI can be delivered. Do not deschedule pending_nmi as + that, if still in the event queue, is a second NMI that + needs to be delivered later. */ + FEPC = PC; + FEPSW = PSW; + /* Set the FECC part of the ECR. */ + ECR &= 0x0000ffff; + ECR |= 0x10; + PSW |= PSW_NP; + PSW &= ~PSW_EP; + PSW |= PSW_ID; + PC = 0x10; + sim_engine_restart (sd, NULL, NULL, NULL_CIA); + } + } + + /* deliver maskable interrupt when allowed */ + if (inttype > int_nmi && inttype < num_int_types) + { + if ((PSW & PSW_NP) || (PSW & PSW_ID)) + { + /* Can't deliver this interrupt, reschedule it for later */ + sim_events_schedule (sd, 1, do_interrupt, data); + return; + } + else + { + /* save context */ + EIPC = PC; + EIPSW = PSW; + /* Disable further interrupts. */ + PSW |= PSW_ID; + /* Indicate that we're doing interrupt not exception processing. */ + PSW &= ~PSW_EP; + /* Clear the EICC part of the ECR, will set below. */ + ECR &= 0xffff0000; + switch (inttype) + { + case int_intov1: + PC = 0x80; + ECR |= 0x80; + break; + case int_intp10: + PC = 0x90; + ECR |= 0x90; + break; + case int_intp11: + PC = 0xa0; + ECR |= 0xa0; + break; + case int_intp12: + PC = 0xb0; + ECR |= 0xb0; + break; + case int_intp13: + PC = 0xc0; + ECR |= 0xc0; + break; + case int_intcm4: + PC = 0xd0; + ECR |= 0xd0; + break; + default: + /* Should never be possible. */ + sim_engine_abort (sd, NULL, NULL_CIA, + "do_interrupt - internal error - bad switch"); + break; + } + } + sim_engine_restart (sd, NULL, NULL, NULL_CIA); + } + + /* some other interrupt? */ + sim_engine_abort (sd, NULL, NULL_CIA, + "do_interrupt - internal error - interrupt %d unknown", + inttype); +} + +/* Return name of an insn, used by insn profiling. */ + +static const char * +get_insn_name (sim_cpu *cpu, int i) +{ + return itable[i].name; +} + +/* These default values correspond to expected usage for the chip. */ + +uint32 OP[4]; + + +SIM_DESC +sim_open (kind, cb, abfd, argv) + SIM_OPEN_KIND kind; + host_callback *cb; + struct _bfd *abfd; + char **argv; +{ + SIM_DESC sd = sim_state_alloc (kind, cb); + int mach; + + SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); + + /* for compatibility */ + simulator = sd; + + /* FIXME: should be better way of setting up interrupts */ + STATE_WATCHPOINTS (sd)->pc = &(PC); + STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); + STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt; + STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names; + + /* Initialize the mechanism for doing insn profiling. */ + CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name; + CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries; + + if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) + return 0; + + /* Allocate core managed memory */ + + /* "Mirror" the ROM addresses below 1MB. */ + sim_do_commandf (sd, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE); + /* Chunk of ram adjacent to rom */ + sim_do_commandf (sd, "memory region 0x100000,0x%lx", V850_LOW_END-0x100000); + /* peripheral I/O region - mirror 1K across 4k (0x1000) */ + sim_do_command (sd, "memory region 0xfff000,0x1000,1024"); + /* similarly if in the internal RAM region */ + sim_do_command (sd, "memory region 0xffe000,0x1000,1024"); + + /* getopt will print the error message so we just have to exit if this fails. + FIXME: Hmmm... in the case of gdb we need getopt to call + print_filtered. */ + if (sim_parse_args (sd, argv) != SIM_RC_OK) + { + /* Uninstall the modules to avoid memory leaks, + file descriptor leaks, etc. */ + sim_module_uninstall (sd); + return 0; + } + + /* check for/establish the a reference program image */ + if (sim_analyze_program (sd, + (STATE_PROG_ARGV (sd) != NULL + ? *STATE_PROG_ARGV (sd) + : NULL), + abfd) != SIM_RC_OK) + { + sim_module_uninstall (sd); + return 0; + } + + /* establish any remaining configuration options */ + if (sim_config (sd) != SIM_RC_OK) + { + sim_module_uninstall (sd); + return 0; + } + + if (sim_post_argv_init (sd) != SIM_RC_OK) + { + /* Uninstall the modules to avoid memory leaks, + file descriptor leaks, etc. */ + sim_module_uninstall (sd); + return 0; + } + + + /* determine the machine type */ + if (STATE_ARCHITECTURE (sd) != NULL + && STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850) + mach = STATE_ARCHITECTURE (sd)->mach; + else + mach = bfd_mach_v850; /* default */ + + /* set machine specific configuration */ + switch (mach) + { + case bfd_mach_v850: + case bfd_mach_v850e: + STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT + | PSW_CY | PSW_OV | PSW_S | PSW_Z); + break; + case bfd_mach_v850ea: + PSW |= PSW_US; + STATE_CPU (sd, 0)->psw_mask = (PSW_US + | PSW_NP | PSW_EP | PSW_ID | PSW_SAT + | PSW_CY | PSW_OV | PSW_S | PSW_Z); + break; + } + + return sd; +} + + +void +sim_close (sd, quitting) + SIM_DESC sd; + int quitting; +{ + sim_module_uninstall (sd); +} + +SIM_RC +sim_create_inferior (sd, prog_bfd, argv, env) + SIM_DESC sd; + struct _bfd *prog_bfd; + char **argv; + char **env; +{ + memset (&State, 0, sizeof (State)); + if (prog_bfd != NULL) + PC = bfd_get_start_address (prog_bfd); + /* For v850ea, set PSW[US] by default */ + if (STATE_ARCHITECTURE (sd) != NULL + && STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850 + && STATE_ARCHITECTURE (sd)->mach == bfd_mach_v850ea) + PSW |= PSW_US; + return SIM_RC_OK; +} + +int +sim_fetch_register (sd, rn, memory, length) + SIM_DESC sd; + int rn; + unsigned char *memory; + int length; +{ + *(unsigned32*)memory = H2T_4 (State.regs[rn]); + return -1; +} + +int +sim_store_register (sd, rn, memory, length) + SIM_DESC sd; + int rn; + unsigned char *memory; + int length; +{ + State.regs[rn] = T2H_4 (*(unsigned32*)memory); + return -1; +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd; + char *cmd; +{ + char *mm_cmd = "memory-map"; + char *int_cmd = "interrupt"; + + if (sim_args_command (sd, cmd) != SIM_RC_OK) + { + if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) + sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); + else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) + sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); + else + sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); + } +} diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h new file mode 100644 index 0000000..37ea31f --- /dev/null +++ b/sim/v850/sim-main.h @@ -0,0 +1,388 @@ +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +/* General config options */ + +#define WITH_CORE +#define WITH_MODULO_MEMORY 1 +#define WITH_WATCHPOINTS 1 + + +/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ + +#define WITH_TARGET_WORD_MSB 31 + + +#include "sim-basics.h" +#include "sim-signal.h" + +typedef address_word sim_cia; + +#include "sim-base.h" + +#include "simops.h" +#include "bfd.h" + + +typedef signed8 int8; +typedef unsigned8 uint8; +typedef signed16 int16; +typedef unsigned16 uint16; +typedef signed32 int32; +typedef unsigned32 uint32; +typedef unsigned32 reg_t; + + +/* The current state of the processor; registers, memory, etc. */ + +typedef struct _v850_regs { + reg_t regs[32]; /* general-purpose registers */ + reg_t sregs[32]; /* system registers, including psw */ + reg_t pc; + int dummy_mem; /* where invalid accesses go */ +} v850_regs; + +struct _sim_cpu +{ + /* ... simulator specific members ... */ + v850_regs reg; + reg_t psw_mask; /* only allow non-reserved bits to be set */ + sim_event *pending_nmi; + /* ... base type ... */ + sim_cpu_base base; +}; + +#define CIA_GET(CPU) ((CPU)->reg.pc + 0) +#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL)) + +struct sim_state { + sim_cpu cpu[MAX_NR_PROCESSORS]; +#if (WITH_SMP) +#define STATE_CPU(sd,n) (&(sd)->cpu[n]) +#else +#define STATE_CPU(sd,n) (&(sd)->cpu[0]) +#endif +#if 0 + SIM_ADDR rom_size; + SIM_ADDR low_end; + SIM_ADDR high_start; + SIM_ADDR high_base; + void *mem; +#endif + sim_state_base base; +}; + +/* For compatibility, until all functions converted to passing + SIM_DESC as an argument */ +extern SIM_DESC simulator; + + +#define V850_ROM_SIZE 0x8000 +#define V850_LOW_END 0x200000 +#define V850_HIGH_START 0xffe000 + + +/* Because we are still using the old semantic table, provide compat + macro's that store the instruction where the old simops expects + it. */ + +extern uint32 OP[4]; +#if 0 +OP[0] = inst & 0x1f; /* RRRRR -> reg1 */ +OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */ +OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */ +OP[3] = inst; +#endif + +#define SAVE_1 \ +PC = cia; \ +OP[0] = instruction_0 & 0x1f; \ +OP[1] = (instruction_0 >> 11) & 0x1f; \ +OP[2] = 0; \ +OP[3] = instruction_0 + +#define COMPAT_1(CALL) \ +SAVE_1; \ +PC += (CALL); \ +nia = PC + +#define SAVE_2 \ +PC = cia; \ +OP[0] = instruction_0 & 0x1f; \ +OP[1] = (instruction_0 >> 11) & 0x1f; \ +OP[2] = instruction_1; \ +OP[3] = (instruction_1 << 16) | instruction_0 + +#define COMPAT_2(CALL) \ +SAVE_2; \ +PC += (CALL); \ +nia = PC + + +/* new */ +#define GR ((CPU)->reg.regs) +#define SR ((CPU)->reg.sregs) + +/* old */ +#define State (STATE_CPU (simulator, 0)->reg) +#define PC (State.pc) +#define SP (State.regs[3]) +#define EP (State.regs[30]) + +#define EIPC (State.sregs[0]) +#define EIPSW (State.sregs[1]) +#define FEPC (State.sregs[2]) +#define FEPSW (State.sregs[3]) +#define ECR (State.sregs[4]) +#define PSW (State.sregs[5]) +#define CTPC (SR[16]) +#define CTPSW (SR[17]) +#define DBPC (State.sregs[18]) +#define DBPSW (State.sregs[19]) +#define CTBP (State.sregs[20]) + +#define PSW_US BIT32 (8) +#define PSW_NP 0x80 +#define PSW_EP 0x40 +#define PSW_ID 0x20 +#define PSW_SAT 0x10 +#define PSW_CY 0x8 +#define PSW_OV 0x4 +#define PSW_S 0x2 +#define PSW_Z 0x1 + +#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) + +/* sign-extend a 4-bit number */ +#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) + +/* sign-extend a 5-bit number */ +#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) + +/* sign-extend a 9-bit number */ +#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) + +/* sign-extend a 22-bit number */ +#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) + +/* sign extend a 40 bit number */ +#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \ + ^ (~UNSIGNED64 (0x7fffffffff))) \ + + UNSIGNED64 (0x8000000000)) + +/* sign extend a 44 bit number */ +#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \ + ^ (~ UNSIGNED64 (0x7ffffffffff))) \ + + UNSIGNED64 (0x80000000000)) + +/* sign extend a 60 bit number */ +#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \ + ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \ + + UNSIGNED64 (0x800000000000000)) + +/* No sign extension */ +#define NOP(x) (x) + +#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i)) + +#define RLW(x) load_mem (x, 4) + +/* Function declarations. */ + +#define IMEM16(EA) \ +sim_core_read_aligned_2 (CPU, PC, exec_map, (EA)) + +#define IMEM16_IMMED(EA,N) \ +sim_core_read_aligned_2 (STATE_CPU (sd, 0), \ + PC, exec_map, (EA) + (N) * 2) + +#define load_mem(ADDR,LEN) \ +sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \ + PC, read_map, (ADDR)) + +#define store_mem(ADDR,LEN,DATA) \ +sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ + PC, write_map, (ADDR), (DATA)) + + +/* compare cccc field against PSW */ +int condition_met (unsigned code); + + +/* Debug/tracing calls */ + +enum op_types +{ + OP_UNKNOWN, + OP_NONE, + OP_TRAP, + OP_REG, + OP_REG_REG, + OP_REG_REG_CMP, + OP_REG_REG_MOVE, + OP_IMM_REG, + OP_IMM_REG_CMP, + OP_IMM_REG_MOVE, + OP_COND_BR, + OP_LOAD16, + OP_STORE16, + OP_LOAD32, + OP_STORE32, + OP_JUMP, + OP_IMM_REG_REG, + OP_UIMM_REG_REG, + OP_IMM16_REG_REG, + OP_UIMM16_REG_REG, + OP_BIT, + OP_EX1, + OP_EX2, + OP_LDSR, + OP_STSR, + OP_BIT_CHANGE, + OP_REG_REG_REG, + OP_REG_REG3, + OP_IMM_REG_REG_REG, + OP_PUSHPOP1, + OP_PUSHPOP2, + OP_PUSHPOP3, +}; + +#ifdef DEBUG +void trace_input PARAMS ((char *name, enum op_types type, int size)); +void trace_output PARAMS ((enum op_types result)); +void trace_result PARAMS ((int has_result, unsigned32 result)); + +extern int trace_num_values; +extern unsigned32 trace_values[]; +extern unsigned32 trace_pc; +extern const char *trace_name; +extern int trace_module; + +#define TRACE_BRANCH0() \ +do { \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_num_values = 0; \ + trace_result (1, (nia)); \ + } \ +} while (0) + +#define TRACE_BRANCH1(IN1) \ +do { \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (IN1); \ + trace_num_values = 1; \ + trace_result (1, (nia)); \ + } \ +} while (0) + +#define TRACE_BRANCH2(IN1, IN2) \ +do { \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (IN1); \ + trace_values[1] = (IN2); \ + trace_num_values = 2; \ + trace_result (1, (nia)); \ + } \ +} while (0) + +#define TRACE_BRANCH3(IN1, IN2, IN3) \ +do { \ + if (TRACE_BRANCH_P (CPU)) { \ + trace_module = TRACE_BRANCH_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (IN1); \ + trace_values[1] = (IN2); \ + trace_values[2] = (IN3); \ + trace_num_values = 3; \ + trace_result (1, (nia)); \ + } \ +} while (0) + +#define TRACE_LD(ADDR,RESULT) \ +do { \ + if (TRACE_MEMORY_P (CPU)) { \ + trace_module = TRACE_MEMORY_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (ADDR); \ + trace_num_values = 1; \ + trace_result (1, (RESULT)); \ + } \ +} while (0) + +#define TRACE_LD_NAME(NAME, ADDR,RESULT) \ +do { \ + if (TRACE_MEMORY_P (CPU)) { \ + trace_module = TRACE_MEMORY_IDX; \ + trace_pc = cia; \ + trace_name = (NAME); \ + trace_values[0] = (ADDR); \ + trace_num_values = 1; \ + trace_result (1, (RESULT)); \ + } \ +} while (0) + +#define TRACE_ST(ADDR,RESULT) \ +do { \ + if (TRACE_MEMORY_P (CPU)) { \ + trace_module = TRACE_MEMORY_IDX; \ + trace_pc = cia; \ + trace_name = itable[MY_INDEX].name; \ + trace_values[0] = (ADDR); \ + trace_num_values = 1; \ + trace_result (1, (RESULT)); \ + } \ +} while (0) + +#else +#define trace_input(NAME, IN1, IN2) +#define trace_output(RESULT) +#define trace_result(HAS_RESULT, RESULT) + +#define TRACE_ALU_INPUT0() +#define TRACE_ALU_INPUT1(IN0) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1) +#define TRACE_ALU_INPUT2(IN0, IN1 INS2) +#define TRACE_ALU_RESULT(RESULT) + +#define TRACE_BRANCH0() +#define TRACE_BRANCH1(IN1) +#define TRACE_BRANCH2(IN1, IN2) +#define TRACE_BRANCH2(IN1, IN2, IN3) + +#define TRACE_LD(ADDR,RESULT) +#define TRACE_ST(ADDR,RESULT) + +#endif + + +extern void divun ( unsigned int N, + unsigned long int als, + unsigned long int sfi, + unsigned32 /*unsigned long int*/ * quotient_ptr, + unsigned32 /*unsigned long int*/ * remainder_ptr, + boolean * overflow_ptr + ); +extern void divn ( unsigned int N, + unsigned long int als, + unsigned long int sfi, + signed32 /*signed long int*/ * quotient_ptr, + signed32 /*signed long int*/ * remainder_ptr, + boolean * overflow_ptr + ); +extern int type1_regs[]; +extern int type2_regs[]; +extern int type3_regs[]; + +#endif diff --git a/sim/v850/simops.c b/sim/v850/simops.c new file mode 100644 index 0000000..f6f43ee --- /dev/null +++ b/sim/v850/simops.c @@ -0,0 +1,2733 @@ +#include "sim-main.h" +#include "v850_sim.h" +#include "simops.h" + +#ifdef HAVE_UTIME_H +#include +#endif + +#ifdef HAVE_TIME_H +#include +#endif + +#ifdef HAVE_UNISTD_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif + +#include "targ-vals.h" + +#include "libiberty.h" + +#include +#if !defined(__GO32__) && !defined(_WIN32) +#include +#include +#include +#endif + +/* This is an array of the bit positions of registers r20 .. r31 in + that order in a prepare/dispose instruction. */ +int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 }; +/* This is an array of the bit positions of registers r16 .. r31 in + that order in a push/pop instruction. */ +int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; +/* This is an array of the bit positions of registers r1 .. r15 in + that order in a push/pop instruction. */ +int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21}; + +#ifdef DEBUG +#ifndef SIZE_INSTRUCTION +#define SIZE_INSTRUCTION 18 +#endif + +#ifndef SIZE_VALUES +#define SIZE_VALUES 11 +#endif + + +unsigned32 trace_values[3]; +int trace_num_values; +unsigned32 trace_pc; +const char *trace_name; +int trace_module; + + +void +trace_input (name, type, size) + char *name; + enum op_types type; + int size; +{ + + if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) + return; + + trace_pc = PC; + trace_name = name; + trace_module = TRACE_ALU_IDX; + + switch (type) + { + default: + case OP_UNKNOWN: + case OP_NONE: + case OP_TRAP: + trace_num_values = 0; + break; + + case OP_REG: + case OP_REG_REG_MOVE: + trace_values[0] = State.regs[OP[0]]; + trace_num_values = 1; + break; + + case OP_BIT_CHANGE: + case OP_REG_REG: + case OP_REG_REG_CMP: + trace_values[0] = State.regs[OP[1]]; + trace_values[1] = State.regs[OP[0]]; + trace_num_values = 2; + break; + + case OP_IMM_REG: + case OP_IMM_REG_CMP: + trace_values[0] = SEXT5 (OP[0]); + trace_values[1] = OP[1]; + trace_num_values = 2; + break; + + case OP_IMM_REG_MOVE: + trace_values[0] = SEXT5 (OP[0]); + trace_num_values = 1; + break; + + case OP_COND_BR: + trace_values[0] = State.pc; + trace_values[1] = SEXT9 (OP[0]); + trace_values[2] = PSW; + trace_num_values = 3; + break; + + case OP_LOAD16: + trace_values[0] = OP[1] * size; + trace_values[1] = State.regs[30]; + trace_num_values = 2; + break; + + case OP_STORE16: + trace_values[0] = State.regs[OP[0]]; + trace_values[1] = OP[1] * size; + trace_values[2] = State.regs[30]; + trace_num_values = 3; + break; + + case OP_LOAD32: + trace_values[0] = EXTEND16 (OP[2]); + trace_values[1] = State.regs[OP[0]]; + trace_num_values = 2; + break; + + case OP_STORE32: + trace_values[0] = State.regs[OP[1]]; + trace_values[1] = EXTEND16 (OP[2]); + trace_values[2] = State.regs[OP[0]]; + trace_num_values = 3; + break; + + case OP_JUMP: + trace_values[0] = SEXT22 (OP[0]); + trace_values[1] = State.pc; + trace_num_values = 2; + break; + + case OP_IMM_REG_REG: + trace_values[0] = EXTEND16 (OP[0]) << size; + trace_values[1] = State.regs[OP[1]]; + trace_num_values = 2; + break; + + case OP_IMM16_REG_REG: + trace_values[0] = EXTEND16 (OP[2]) << size; + trace_values[1] = State.regs[OP[1]]; + trace_num_values = 2; + break; + + case OP_UIMM_REG_REG: + trace_values[0] = (OP[0] & 0xffff) << size; + trace_values[1] = State.regs[OP[1]]; + trace_num_values = 2; + break; + + case OP_UIMM16_REG_REG: + trace_values[0] = (OP[2]) << size; + trace_values[1] = State.regs[OP[1]]; + trace_num_values = 2; + break; + + case OP_BIT: + trace_num_values = 0; + break; + + case OP_EX1: + trace_values[0] = PSW; + trace_num_values = 1; + break; + + case OP_EX2: + trace_num_values = 0; + break; + + case OP_LDSR: + trace_values[0] = State.regs[OP[0]]; + trace_num_values = 1; + break; + + case OP_STSR: + trace_values[0] = State.sregs[OP[1]]; + trace_num_values = 1; + } + +} + +void +trace_result (int has_result, unsigned32 result) +{ + char buf[1000]; + char *chp; + + buf[0] = '\0'; + chp = buf; + + /* write out the values saved during the trace_input call */ + { + int i; + for (i = 0; i < trace_num_values; i++) + { + sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", trace_values[i]); + chp = strchr (chp, '\0'); + } + while (i++ < 3) + { + sprintf (chp, "%*s", SIZE_VALUES, ""); + chp = strchr (chp, '\0'); + } + } + + /* append any result to the end of the buffer */ + if (has_result) + sprintf (chp, " :: 0x%.8lx", (unsigned long)result); + + trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf); +} + +void +trace_output (result) + enum op_types result; +{ + if (!TRACE_ALU_P (STATE_CPU (simulator, 0))) + return; + + switch (result) + { + default: + case OP_UNKNOWN: + case OP_NONE: + case OP_TRAP: + case OP_REG: + case OP_REG_REG_CMP: + case OP_IMM_REG_CMP: + case OP_COND_BR: + case OP_STORE16: + case OP_STORE32: + case OP_BIT: + case OP_EX2: + trace_result (0, 0); + break; + + case OP_LOAD16: + case OP_STSR: + trace_result (1, State.regs[OP[0]]); + break; + + case OP_REG_REG: + case OP_REG_REG_MOVE: + case OP_IMM_REG: + case OP_IMM_REG_MOVE: + case OP_LOAD32: + case OP_EX1: + trace_result (1, State.regs[OP[1]]); + break; + + case OP_IMM_REG_REG: + case OP_UIMM_REG_REG: + case OP_IMM16_REG_REG: + case OP_UIMM16_REG_REG: + trace_result (1, State.regs[OP[1]]); + break; + + case OP_JUMP: + if (OP[1] != 0) + trace_result (1, State.regs[OP[1]]); + else + trace_result (0, 0); + break; + + case OP_LDSR: + trace_result (1, State.sregs[OP[1]]); + break; + } +} +#endif + + +/* Returns 1 if the specific condition is met, returns 0 otherwise. */ +int +condition_met (unsigned code) +{ + unsigned int psw = PSW; + + switch (code & 0xf) + { + case 0x0: return ((psw & PSW_OV) != 0); + case 0x1: return ((psw & PSW_CY) != 0); + case 0x2: return ((psw & PSW_Z) != 0); + case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0); + case 0x4: return ((psw & PSW_S) != 0); + /*case 0x5: return 1;*/ + case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0); + case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0); + case 0x8: return ((psw & PSW_OV) == 0); + case 0x9: return ((psw & PSW_CY) == 0); + case 0xa: return ((psw & PSW_Z) == 0); + case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0); + case 0xc: return ((psw & PSW_S) == 0); + case 0xd: return ((psw & PSW_SAT) != 0); + case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0); + case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0); + } + + return 1; +} + +static unsigned long +Add32 (unsigned long a1, unsigned long a2, int * carry) +{ + unsigned long result = (a1 + a2); + + * carry = (result < a1); + + return result; +} + +static void +Multiply64 (boolean sign, unsigned long op0) +{ + unsigned long op1; + unsigned long lo; + unsigned long mid1; + unsigned long mid2; + unsigned long hi; + unsigned long RdLo; + unsigned long RdHi; + int carry; + + op1 = State.regs[ OP[1] ]; + + if (sign) + { + /* Compute sign of result and adjust operands if necessary. */ + + sign = (op0 ^ op1) & 0x80000000; + + if (((signed long) op0) < 0) + op0 = - op0; + + if (((signed long) op1) < 0) + op1 = - op1; + } + + /* We can split the 32x32 into four 16x16 operations. This ensures + that we do not lose precision on 32bit only hosts: */ + lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF)); + mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); + mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF)); + hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); + + /* We now need to add all of these results together, taking care + to propogate the carries from the additions: */ + RdLo = Add32 (lo, (mid1 << 16), & carry); + RdHi = carry; + RdLo = Add32 (RdLo, (mid2 << 16), & carry); + RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); + + if (sign) + { + /* Negate result if necessary. */ + + RdLo = ~ RdLo; + RdHi = ~ RdHi; + if (RdLo == 0xFFFFFFFF) + { + RdLo = 0; + RdHi += 1; + } + else + RdLo += 1; + } + + /* Don't store into register 0. */ + if (OP[1]) + State.regs[ OP[1] ] = RdLo; + if (OP[2] >> 11) + State.regs[ OP[2] >> 11 ] = RdHi; + + return; +} + + +/* Read a null terminated string from memory, return in a buffer */ +static char * +fetch_str (sd, addr) + SIM_DESC sd; + address_word addr; +{ + char *buf; + int nr = 0; + while (sim_core_read_1 (STATE_CPU (sd, 0), + PC, read_map, addr + nr) != 0) + nr++; + buf = NZALLOC (char, nr + 1); + sim_read (simulator, addr, buf, nr); + return buf; +} + +/* Read a null terminated argument vector from memory, return in a + buffer */ +static char ** +fetch_argv (sd, addr) + SIM_DESC sd; + address_word addr; +{ + int max_nr = 64; + int nr = 0; + char **buf = xmalloc (max_nr * sizeof (char*)); + while (1) + { + unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0), + PC, read_map, addr + nr * 4); + if (a == 0) break; + buf[nr] = fetch_str (sd, a); + nr ++; + if (nr == max_nr - 1) + { + max_nr += 50; + buf = xrealloc (buf, max_nr * sizeof (char*)); + } + } + buf[nr] = 0; + return buf; +} + + +/* sst.b */ +int +OP_380 () +{ + trace_input ("sst.b", OP_STORE16, 1); + + store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]); + + trace_output (OP_STORE16); + + return 2; +} + +/* sst.h */ +int +OP_480 () +{ + trace_input ("sst.h", OP_STORE16, 2); + + store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]); + + trace_output (OP_STORE16); + + return 2; +} + +/* sst.w */ +int +OP_501 () +{ + trace_input ("sst.w", OP_STORE16, 4); + + store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]); + + trace_output (OP_STORE16); + + return 2; +} + +/* ld.b */ +int +OP_700 () +{ + int adr; + + trace_input ("ld.b", OP_LOAD32, 1); + + adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); + + State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1)); + + trace_output (OP_LOAD32); + + return 4; +} + +/* ld.h */ +int +OP_720 () +{ + int adr; + + trace_input ("ld.h", OP_LOAD32, 2); + + adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); + adr &= ~0x1; + + State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2)); + + trace_output (OP_LOAD32); + + return 4; +} + +/* ld.w */ +int +OP_10720 () +{ + int adr; + + trace_input ("ld.w", OP_LOAD32, 4); + + adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); + adr &= ~0x3; + + State.regs[ OP[1] ] = load_mem (adr, 4); + + trace_output (OP_LOAD32); + + return 4; +} + +/* st.b */ +int +OP_740 () +{ + trace_input ("st.b", OP_STORE32, 1); + + store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]); + + trace_output (OP_STORE32); + + return 4; +} + +/* st.h */ +int +OP_760 () +{ + int adr; + + trace_input ("st.h", OP_STORE32, 2); + + adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]); + adr &= ~1; + + store_mem (adr, 2, State.regs[ OP[1] ]); + + trace_output (OP_STORE32); + + return 4; +} + +/* st.w */ +int +OP_10760 () +{ + int adr; + + trace_input ("st.w", OP_STORE32, 4); + + adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); + adr &= ~3; + + store_mem (adr, 4, State.regs[ OP[1] ]); + + trace_output (OP_STORE32); + + return 4; +} + +/* add reg, reg */ +int +OP_1C0 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + + trace_input ("add", OP_REG_REG, 0); + + /* Compute the result. */ + + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + + result = op0 + op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (result < op0 || result < op1); + ov = ((op0 & 0x80000000) == (op1 & 0x80000000) + && (op0 & 0x80000000) != (result & 0x80000000)); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* add sign_extend(imm5), reg */ +int +OP_240 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + int temp; + + trace_input ("add", OP_IMM_REG, 0); + + /* Compute the result. */ + temp = SEXT5 (OP[0]); + op0 = temp; + op1 = State.regs[OP[1]]; + result = op0 + op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (result < op0 || result < op1); + ov = ((op0 & 0x80000000) == (op1 & 0x80000000) + && (op0 & 0x80000000) != (result & 0x80000000)); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_IMM_REG); + + return 2; +} + +/* addi sign_extend(imm16), reg, reg */ +int +OP_600 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + + trace_input ("addi", OP_IMM16_REG_REG, 0); + + /* Compute the result. */ + + op0 = EXTEND16 (OP[2]); + op1 = State.regs[ OP[0] ]; + result = op0 + op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (result < op0 || result < op1); + ov = ((op0 & 0x80000000) == (op1 & 0x80000000) + && (op0 & 0x80000000) != (result & 0x80000000)); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_IMM16_REG_REG); + + return 4; +} + +/* sub reg1, reg2 */ +int +OP_1A0 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + + trace_input ("sub", OP_REG_REG, 0); + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op1 - op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 < op0); + ov = ((op1 & 0x80000000) != (op0 & 0x80000000) + && (op1 & 0x80000000) != (result & 0x80000000)); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* subr reg1, reg2 */ +int +OP_180 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + + trace_input ("subr", OP_REG_REG, 0); + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 - op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op0 < op1); + ov = ((op0 & 0x80000000) != (op1 & 0x80000000) + && (op0 & 0x80000000) != (result & 0x80000000)); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* sxh reg1 */ +int +OP_E0 () +{ + trace_input ("mulh", OP_REG_REG, 0); + + State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ])); + + trace_output (OP_REG_REG); + + return 2; +} + +/* mulh sign_extend(imm5), reg2 */ +int +OP_2E0 () +{ + trace_input ("mulh", OP_IMM_REG, 0); + + State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]); + + trace_output (OP_IMM_REG); + + return 2; +} + +/* mulhi imm16, reg1, reg2 */ +int +OP_6E0 () +{ + trace_input ("mulhi", OP_IMM16_REG_REG, 0); + + State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]); + + trace_output (OP_IMM16_REG_REG); + + return 4; +} + +/* divh reg1, reg2 */ +int +OP_40 () +{ + unsigned int op0, op1, result, ov, s, z; + int temp; + + trace_input ("divh", OP_REG_REG, 0); + + /* Compute the result. */ + temp = EXTEND16 (State.regs[ OP[0] ]); + op0 = temp; + op1 = State.regs[OP[1]]; + + if (op0 == 0xffffffff && op1 == 0x80000000) + { + result = 0x80000000; + ov = 1; + } + else if (op0 != 0) + { + result = op1 / op0; + ov = 0; + } + else + { + result = 0x0; + ov = 1; + } + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* cmp reg, reg */ +int +OP_1E0 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + + trace_input ("cmp", OP_REG_REG_CMP, 0); + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op1 - op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 < op0); + ov = ((op1 & 0x80000000) != (op0 & 0x80000000) + && (op1 & 0x80000000) != (result & 0x80000000)); + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG_CMP); + + return 2; +} + +/* cmp sign_extend(imm5), reg */ +int +OP_260 () +{ + unsigned int op0, op1, result, z, s, cy, ov; + int temp; + + /* Compute the result. */ + trace_input ("cmp", OP_IMM_REG_CMP, 0); + temp = SEXT5 (OP[0]); + op0 = temp; + op1 = State.regs[OP[1]]; + result = op1 - op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 < op0); + ov = ((op1 & 0x80000000) != (op0 & 0x80000000) + && (op1 & 0x80000000) != (result & 0x80000000)); + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_IMM_REG_CMP); + + return 2; +} + +/* setf cccc,reg2 */ +int +OP_7E0 () +{ + trace_input ("setf", OP_EX1, 0); + + State.regs[ OP[1] ] = condition_met (OP[0]); + + trace_output (OP_EX1); + + return 4; +} + +/* satadd reg,reg */ +int +OP_C0 () +{ + unsigned int op0, op1, result, z, s, cy, ov, sat; + + trace_input ("satadd", OP_REG_REG, 0); + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 + op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (result < op0 || result < op1); + ov = ((op0 & 0x80000000) == (op1 & 0x80000000) + && (op0 & 0x80000000) != (result & 0x80000000)); + sat = ov; + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) + | (sat ? PSW_SAT : 0)); + + /* Handle saturated results. */ + if (sat && s) + State.regs[OP[1]] = 0x80000000; + else if (sat) + State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_REG_REG); + + return 2; +} + +/* satadd sign_extend(imm5), reg */ +int +OP_220 () +{ + unsigned int op0, op1, result, z, s, cy, ov, sat; + + int temp; + + trace_input ("satadd", OP_IMM_REG, 0); + + /* Compute the result. */ + temp = SEXT5 (OP[0]); + op0 = temp; + op1 = State.regs[OP[1]]; + result = op0 + op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (result < op0 || result < op1); + ov = ((op0 & 0x80000000) == (op1 & 0x80000000) + && (op0 & 0x80000000) != (result & 0x80000000)); + sat = ov; + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) + | (sat ? PSW_SAT : 0)); + + /* Handle saturated results. */ + if (sat && s) + State.regs[OP[1]] = 0x80000000; + else if (sat) + State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_IMM_REG); + + return 2; +} + +/* satsub reg1, reg2 */ +int +OP_A0 () +{ + unsigned int op0, op1, result, z, s, cy, ov, sat; + + trace_input ("satsub", OP_REG_REG, 0); + + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op1 - op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 < op0); + ov = ((op1 & 0x80000000) != (op0 & 0x80000000) + && (op1 & 0x80000000) != (result & 0x80000000)); + sat = ov; + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) + | (sat ? PSW_SAT : 0)); + + /* Handle saturated results. */ + if (sat && s) + State.regs[OP[1]] = 0x80000000; + else if (sat) + State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_REG_REG); + return 2; +} + +/* satsubi sign_extend(imm16), reg */ +int +OP_660 () +{ + unsigned int op0, op1, result, z, s, cy, ov, sat; + int temp; + + trace_input ("satsubi", OP_IMM_REG, 0); + + /* Compute the result. */ + temp = EXTEND16 (OP[2]); + op0 = temp; + op1 = State.regs[ OP[0] ]; + result = op1 - op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 < op0); + ov = ((op1 & 0x80000000) != (op0 & 0x80000000) + && (op1 & 0x80000000) != (result & 0x80000000)); + sat = ov; + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) + | (sat ? PSW_SAT : 0)); + + /* Handle saturated results. */ + if (sat && s) + State.regs[OP[1]] = 0x80000000; + else if (sat) + State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_IMM_REG); + + return 4; +} + +/* satsubr reg,reg */ +int +OP_80 () +{ + unsigned int op0, op1, result, z, s, cy, ov, sat; + + trace_input ("satsubr", OP_REG_REG, 0); + + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 - op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (result < op0); + ov = ((op1 & 0x80000000) != (op0 & 0x80000000) + && (op1 & 0x80000000) != (result & 0x80000000)); + sat = ov; + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0) + | (sat ? PSW_SAT : 0)); + + /* Handle saturated results. */ + if (sat && s) + State.regs[OP[1]] = 0x80000000; + else if (sat) + State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_REG_REG); + + return 2; +} + +/* tst reg,reg */ +int +OP_160 () +{ + unsigned int op0, op1, result, z, s; + + trace_input ("tst", OP_REG_REG_CMP, 0); + + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 & op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG_CMP); + + return 2; +} + +/* mov sign_extend(imm5), reg */ +int +OP_200 () +{ + int value = SEXT5 (OP[0]); + + trace_input ("mov", OP_IMM_REG_MOVE, 0); + + State.regs[ OP[1] ] = value; + + trace_output (OP_IMM_REG_MOVE); + + return 2; +} + +/* movhi imm16, reg, reg */ +int +OP_640 () +{ + trace_input ("movhi", OP_UIMM16_REG_REG, 16); + + State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16); + + trace_output (OP_UIMM16_REG_REG); + + return 4; +} + +/* sar zero_extend(imm5),reg1 */ +int +OP_2A0 () +{ + unsigned int op0, op1, result, z, s, cy; + + trace_input ("sar", OP_IMM_REG, 0); + op0 = OP[0]; + op1 = State.regs[ OP[1] ]; + result = (signed)op1 >> op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 & (1 << (op0 - 1))); + + /* Store the result and condition codes. */ + State.regs[ OP[1] ] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0)); + trace_output (OP_IMM_REG); + + return 2; +} + +/* sar reg1, reg2 */ +int +OP_A007E0 () +{ + unsigned int op0, op1, result, z, s, cy; + + trace_input ("sar", OP_REG_REG, 0); + + op0 = State.regs[ OP[0] ] & 0x1f; + op1 = State.regs[ OP[1] ]; + result = (signed)op1 >> op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 & (1 << (op0 - 1))); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0)); + trace_output (OP_REG_REG); + + return 4; +} + +/* shl zero_extend(imm5),reg1 */ +int +OP_2C0 () +{ + unsigned int op0, op1, result, z, s, cy; + + trace_input ("shl", OP_IMM_REG, 0); + op0 = OP[0]; + op1 = State.regs[ OP[1] ]; + result = op1 << op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 & (1 << (32 - op0))); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0)); + trace_output (OP_IMM_REG); + + return 2; +} + +/* shl reg1, reg2 */ +int +OP_C007E0 () +{ + unsigned int op0, op1, result, z, s, cy; + + trace_input ("shl", OP_REG_REG, 0); + op0 = State.regs[ OP[0] ] & 0x1f; + op1 = State.regs[ OP[1] ]; + result = op1 << op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 & (1 << (32 - op0))); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0)); + trace_output (OP_REG_REG); + + return 4; +} + +/* shr zero_extend(imm5),reg1 */ +int +OP_280 () +{ + unsigned int op0, op1, result, z, s, cy; + + trace_input ("shr", OP_IMM_REG, 0); + op0 = OP[0]; + op1 = State.regs[ OP[1] ]; + result = op1 >> op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 & (1 << (op0 - 1))); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0)); + trace_output (OP_IMM_REG); + + return 2; +} + +/* shr reg1, reg2 */ +int +OP_8007E0 () +{ + unsigned int op0, op1, result, z, s, cy; + + trace_input ("shr", OP_REG_REG, 0); + op0 = State.regs[ OP[0] ] & 0x1f; + op1 = State.regs[ OP[1] ]; + result = op1 >> op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + cy = (op1 & (1 << (op0 - 1))); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) + | (cy ? PSW_CY : 0)); + trace_output (OP_REG_REG); + + return 4; +} + +/* or reg, reg */ +int +OP_100 () +{ + unsigned int op0, op1, result, z, s; + + trace_input ("or", OP_REG_REG, 0); + + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 | op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* ori zero_extend(imm16), reg, reg */ +int +OP_680 () +{ + unsigned int op0, op1, result, z, s; + + trace_input ("ori", OP_UIMM16_REG_REG, 0); + op0 = OP[2]; + op1 = State.regs[ OP[0] ]; + result = op0 | op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_UIMM16_REG_REG); + + return 4; +} + +/* and reg, reg */ +int +OP_140 () +{ + unsigned int op0, op1, result, z, s; + + trace_input ("and", OP_REG_REG, 0); + + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 & op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* andi zero_extend(imm16), reg, reg */ +int +OP_6C0 () +{ + unsigned int result, z; + + trace_input ("andi", OP_UIMM16_REG_REG, 0); + + result = OP[2] & State.regs[ OP[0] ]; + + /* Compute the condition codes. */ + z = (result == 0); + + /* Store the result and condition codes. */ + State.regs[ OP[1] ] = result; + + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= (z ? PSW_Z : 0); + + trace_output (OP_UIMM16_REG_REG); + + return 4; +} + +/* xor reg, reg */ +int +OP_120 () +{ + unsigned int op0, op1, result, z, s; + + trace_input ("xor", OP_REG_REG, 0); + + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + op1 = State.regs[ OP[1] ]; + result = op0 ^ op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG); + + return 2; +} + +/* xori zero_extend(imm16), reg, reg */ +int +OP_6A0 () +{ + unsigned int op0, op1, result, z, s; + + trace_input ("xori", OP_UIMM16_REG_REG, 0); + op0 = OP[2]; + op1 = State.regs[ OP[0] ]; + result = op0 ^ op1; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_UIMM16_REG_REG); + + return 4; +} + +/* not reg1, reg2 */ +int +OP_20 () +{ + unsigned int op0, result, z, s; + + trace_input ("not", OP_REG_REG_MOVE, 0); + /* Compute the result. */ + op0 = State.regs[ OP[0] ]; + result = ~op0; + + /* Compute the condition codes. */ + z = (result == 0); + s = (result & 0x80000000); + + /* Store the result and condition codes. */ + State.regs[OP[1]] = result; + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG_MOVE); + + return 2; +} + +/* set1 */ +int +OP_7C0 () +{ + unsigned int op0, op1, op2; + int temp; + + trace_input ("set1", OP_BIT, 0); + op0 = State.regs[ OP[0] ]; + op1 = OP[1] & 0x7; + temp = EXTEND16 (OP[2]); + op2 = temp; + temp = load_mem (op0 + op2, 1); + PSW &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + PSW |= PSW_Z; + temp |= (1 << op1); + store_mem (op0 + op2, 1, temp); + trace_output (OP_BIT); + + return 4; +} + +/* not1 */ +int +OP_47C0 () +{ + unsigned int op0, op1, op2; + int temp; + + trace_input ("not1", OP_BIT, 0); + op0 = State.regs[ OP[0] ]; + op1 = OP[1] & 0x7; + temp = EXTEND16 (OP[2]); + op2 = temp; + temp = load_mem (op0 + op2, 1); + PSW &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + PSW |= PSW_Z; + temp ^= (1 << op1); + store_mem (op0 + op2, 1, temp); + trace_output (OP_BIT); + + return 4; +} + +/* clr1 */ +int +OP_87C0 () +{ + unsigned int op0, op1, op2; + int temp; + + trace_input ("clr1", OP_BIT, 0); + op0 = State.regs[ OP[0] ]; + op1 = OP[1] & 0x7; + temp = EXTEND16 (OP[2]); + op2 = temp; + temp = load_mem (op0 + op2, 1); + PSW &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + PSW |= PSW_Z; + temp &= ~(1 << op1); + store_mem (op0 + op2, 1, temp); + trace_output (OP_BIT); + + return 4; +} + +/* tst1 */ +int +OP_C7C0 () +{ + unsigned int op0, op1, op2; + int temp; + + trace_input ("tst1", OP_BIT, 0); + op0 = State.regs[ OP[0] ]; + op1 = OP[1] & 0x7; + temp = EXTEND16 (OP[2]); + op2 = temp; + temp = load_mem (op0 + op2, 1); + PSW &= ~PSW_Z; + if ((temp & (1 << op1)) == 0) + PSW |= PSW_Z; + trace_output (OP_BIT); + + return 4; +} + +/* di */ +int +OP_16007E0 () +{ + trace_input ("di", OP_NONE, 0); + PSW |= PSW_ID; + trace_output (OP_NONE); + + return 4; +} + +/* ei */ +int +OP_16087E0 () +{ + trace_input ("ei", OP_NONE, 0); + PSW &= ~PSW_ID; + trace_output (OP_NONE); + + return 4; +} + +/* halt */ +int +OP_12007E0 () +{ + trace_input ("halt", OP_NONE, 0); + /* FIXME this should put processor into a mode where NMI still handled */ + trace_output (OP_NONE); + sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, + sim_stopped, SIM_SIGTRAP); + return 0; +} + +/* trap */ +int +OP_10007E0 () +{ + trace_input ("trap", OP_TRAP, 0); + trace_output (OP_TRAP); + + /* Trap 31 is used for simulating OS I/O functions */ + + if (OP[0] == 31) + { + int save_errno = errno; + errno = 0; + +/* Registers passed to trap 0 */ + +#define FUNC State.regs[6] /* function number, return value */ +#define PARM1 State.regs[7] /* optional parm 1 */ +#define PARM2 State.regs[8] /* optional parm 2 */ +#define PARM3 State.regs[9] /* optional parm 3 */ + +/* Registers set by trap 0 */ + +#define RETVAL State.regs[10] /* return value */ +#define RETERR State.regs[11] /* return error code */ + +/* Turn a pointer in a register into a pointer into real memory. */ + +#define MEMPTR(x) (map (x)) + + switch (FUNC) + { + +#ifdef HAVE_FORK +#ifdef TARGET_SYS_fork + case TARGET_SYS_fork: + RETVAL = fork (); + break; +#endif +#endif + +#ifdef HAVE_EXECVE +#ifdef TARGET_SYS_execv + case TARGET_SYS_execve: + { + char *path = fetch_str (simulator, PARM1); + char **argv = fetch_argv (simulator, PARM2); + char **envp = fetch_argv (simulator, PARM3); + RETVAL = execve (path, argv, envp); + zfree (path); + freeargv (argv); + freeargv (envp); + break; + } +#endif +#endif + +#if HAVE_EXECV +#ifdef TARGET_SYS_execv + case TARGET_SYS_execv: + { + char *path = fetch_str (simulator, PARM1); + char **argv = fetch_argv (simulator, PARM2); + RETVAL = execv (path, argv); + zfree (path); + freeargv (argv); + break; + } +#endif +#endif + +#if 0 +#ifdef TARGET_SYS_pipe + case TARGET_SYS_pipe: + { + reg_t buf; + int host_fd[2]; + + buf = PARM1; + RETVAL = pipe (host_fd); + SW (buf, host_fd[0]); + buf += sizeof(uint16); + SW (buf, host_fd[1]); + } + break; +#endif +#endif + +#if 0 +#ifdef TARGET_SYS_wait + case TARGET_SYS_wait: + { + int status; + + RETVAL = wait (&status); + SW (PARM1, status); + } + break; +#endif +#endif + +#ifdef TARGET_SYS_read + case TARGET_SYS_read: + { + char *buf = zalloc (PARM3); + RETVAL = sim_io_read (simulator, PARM1, buf, PARM3); + sim_write (simulator, PARM2, buf, PARM3); + zfree (buf); + break; + } +#endif + +#ifdef TARGET_SYS_write + case TARGET_SYS_write: + { + char *buf = zalloc (PARM3); + sim_read (simulator, PARM2, buf, PARM3); + if (PARM1 == 1) + RETVAL = sim_io_write_stdout (simulator, buf, PARM3); + else + RETVAL = sim_io_write (simulator, PARM1, buf, PARM3); + zfree (buf); + break; + } +#endif + +#ifdef TARGET_SYS_lseek + case TARGET_SYS_lseek: + RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3); + break; +#endif + +#ifdef TARGET_SYS_close + case TARGET_SYS_close: + RETVAL = sim_io_close (simulator, PARM1); + break; +#endif + +#ifdef TARGET_SYS_open + case TARGET_SYS_open: + { + char *buf = fetch_str (simulator, PARM1); + RETVAL = sim_io_open (simulator, buf, PARM2); + zfree (buf); + break; + } +#endif + +#ifdef TARGET_SYS_exit + case TARGET_SYS_exit: + if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0) + /* get signal encoded by kill */ + sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, + sim_signalled, PARM1 & 0xffff); + else if (PARM1 == 0xdead) + /* old libraries */ + sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, + sim_stopped, SIM_SIGABRT); + else + /* PARM1 has exit status */ + sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, + sim_exited, PARM1); + break; +#endif + +#if !defined(__GO32__) && !defined(_WIN32) +#ifdef TARGET_SYS_stat + case TARGET_SYS_stat: /* added at hmsi */ + /* stat system call */ + { + struct stat host_stat; + reg_t buf; + char *path = fetch_str (simulator, PARM1); + + RETVAL = stat (path, &host_stat); + + zfree (path); + buf = PARM2; + + /* Just wild-assed guesses. */ + store_mem (buf, 2, host_stat.st_dev); + store_mem (buf + 2, 2, host_stat.st_ino); + store_mem (buf + 4, 4, host_stat.st_mode); + store_mem (buf + 8, 2, host_stat.st_nlink); + store_mem (buf + 10, 2, host_stat.st_uid); + store_mem (buf + 12, 2, host_stat.st_gid); + store_mem (buf + 14, 2, host_stat.st_rdev); + store_mem (buf + 16, 4, host_stat.st_size); + store_mem (buf + 20, 4, host_stat.st_atime); + store_mem (buf + 28, 4, host_stat.st_mtime); + store_mem (buf + 36, 4, host_stat.st_ctime); + } + break; +#endif +#endif + +#ifdef HAVE_CHOWN +#ifdef TARGET_SYS_chown + case TARGET_SYS_chown: + { + char *path = fetch_str (simulator, PARM1); + RETVAL = chown (path, PARM2, PARM3); + zfree (path); + } + break; +#endif +#endif + +#if HAVE_CHMOD +#ifdef TARGET_SYS_chmod + case TARGET_SYS_chmod: + { + char *path = fetch_str (simulator, PARM1); + RETVAL = chmod (path, PARM2); + zfree (path); + } + break; +#endif +#endif + +#ifdef TARGET_SYS_time +#if HAVE_TIME + case TARGET_SYS_time: + { + time_t now; + RETVAL = time (&now); + store_mem (PARM1, 4, now); + } + break; +#endif +#endif + +#if !defined(__GO32__) && !defined(_WIN32) +#ifdef TARGET_SYS_times + case TARGET_SYS_times: + { + struct tms tms; + RETVAL = times (&tms); + store_mem (PARM1, 4, tms.tms_utime); + store_mem (PARM1 + 4, 4, tms.tms_stime); + store_mem (PARM1 + 8, 4, tms.tms_cutime); + store_mem (PARM1 + 12, 4, tms.tms_cstime); + break; + } +#endif +#endif + +#ifdef TARGET_SYS_gettimeofday +#if !defined(__GO32__) && !defined(_WIN32) + case TARGET_SYS_gettimeofday: + { + struct timeval t; + struct timezone tz; + RETVAL = gettimeofday (&t, &tz); + store_mem (PARM1, 4, t.tv_sec); + store_mem (PARM1 + 4, 4, t.tv_usec); + store_mem (PARM2, 4, tz.tz_minuteswest); + store_mem (PARM2 + 4, 4, tz.tz_dsttime); + break; + } +#endif +#endif + +#ifdef TARGET_SYS_utime +#if HAVE_UTIME + case TARGET_SYS_utime: + { + /* Cast the second argument to void *, to avoid type mismatch + if a prototype is present. */ + sim_io_error (simulator, "Utime not supported"); + /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */ + } + break; +#endif +#endif + + default: + abort (); + } + RETERR = errno; + errno = save_errno; + + return 4; + } + else + { /* Trap 0 -> 30 */ + EIPC = PC + 4; + EIPSW = PSW; + /* Mask out EICC */ + ECR &= 0xffff0000; + ECR |= 0x40 + OP[0]; + /* Flag that we are now doing exception processing. */ + PSW |= PSW_EP | PSW_ID; + PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4; + + return 0; + } +} + +/* tst1 reg2, [reg1] */ +int +OP_E607E0 (void) +{ + int temp; + + trace_input ("tst1", OP_BIT, 1); + + temp = load_mem (State.regs[ OP[0] ], 1); + + PSW &= ~PSW_Z; + if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0) + PSW |= PSW_Z; + + trace_output (OP_BIT); + + return 4; +} + +/* mulu reg1, reg2, reg3 */ +int +OP_22207E0 (void) +{ + trace_input ("mulu", OP_REG_REG_REG, 0); + + Multiply64 (false, State.regs[ OP[0] ]); + + trace_output (OP_REG_REG_REG); + + return 4; +} + +#define BIT_CHANGE_OP( name, binop ) \ + unsigned int bit; \ + unsigned int temp; \ + \ + trace_input (name, OP_BIT_CHANGE, 0); \ + \ + bit = 1 << State.regs[ OP[1] & 0x7 ]; \ + temp = load_mem (State.regs[ OP[0] ], 1); \ + \ + PSW &= ~PSW_Z; \ + if ((temp & bit) == 0) \ + PSW |= PSW_Z; \ + temp binop bit; \ + \ + store_mem (State.regs[ OP[0] ], 1, temp); \ + \ + trace_output (OP_BIT_CHANGE); \ + \ + return 4; + +/* clr1 reg2, [reg1] */ +int +OP_E407E0 (void) +{ + BIT_CHANGE_OP ("clr1", &= ~ ); +} + +/* not1 reg2, [reg1] */ +int +OP_E207E0 (void) +{ + BIT_CHANGE_OP ("not1", ^= ); +} + +/* set1 */ +int +OP_E007E0 (void) +{ + BIT_CHANGE_OP ("set1", |= ); +} + +/* sasf */ +int +OP_20007E0 (void) +{ + trace_input ("sasf", OP_EX1, 0); + + State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]); + + trace_output (OP_EX1); + + return 4; +} + +/* This function is courtesy of Sugimoto at NEC, via Seow Tan + (Soew_Tan@el.nec.com) */ +void +divun +( + unsigned int N, + unsigned long int als, + unsigned long int sfi, + unsigned32 /*unsigned long int*/ * quotient_ptr, + unsigned32 /*unsigned long int*/ * remainder_ptr, + boolean * overflow_ptr +) +{ + unsigned long ald = sfi >> (N - 1); + unsigned long alo = als; + unsigned int Q = 1; + unsigned int C; + unsigned int S = 0; + unsigned int i; + unsigned int R1 = 1; + unsigned int DBZ = (als == 0) ? 1 : 0; + unsigned long alt = Q ? ~als : als; + + /* 1st Loop */ + alo = ald + alt + Q; + C = (((alt >> 31) & (ald >> 31)) + | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); + C = C ^ Q; + Q = ~(C ^ S) & 1; + R1 = (alo == 0) ? 0 : (R1 & Q); + if ((S ^ (alo>>31)) && !C) + { + DBZ = 1; + } + S = alo >> 31; + sfi = (sfi << (32-N+1)) | Q; + ald = (alo << 1) | (sfi >> 31); + + /* 2nd - N-1th Loop */ + for (i = 2; i < N; i++) + { + alt = Q ? ~als : als; + alo = ald + alt + Q; + C = (((alt >> 31) & (ald >> 31)) + | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); + C = C ^ Q; + Q = ~(C ^ S) & 1; + R1 = (alo == 0) ? 0 : (R1 & Q); + if ((S ^ (alo>>31)) && !C && !DBZ) + { + DBZ = 1; + } + S = alo >> 31; + sfi = (sfi << 1) | Q; + ald = (alo << 1) | (sfi >> 31); + } + + /* Nth Loop */ + alt = Q ? ~als : als; + alo = ald + alt + Q; + C = (((alt >> 31) & (ald >> 31)) + | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); + C = C ^ Q; + Q = ~(C ^ S) & 1; + R1 = (alo == 0) ? 0 : (R1 & Q); + if ((S ^ (alo>>31)) && !C) + { + DBZ = 1; + } + + * quotient_ptr = (sfi << 1) | Q; + * remainder_ptr = Q ? alo : (alo + als); + * overflow_ptr = DBZ | R1; +} + +/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */ +void +divn +( + unsigned int N, + unsigned long int als, + unsigned long int sfi, + signed32 /*signed long int*/ * quotient_ptr, + signed32 /*signed long int*/ * remainder_ptr, + boolean * overflow_ptr +) +{ + unsigned long ald = (signed long) sfi >> (N - 1); + unsigned long alo = als; + unsigned int SS = als >> 31; + unsigned int SD = sfi >> 31; + unsigned int R1 = 1; + unsigned int OV; + unsigned int DBZ = als == 0 ? 1 : 0; + unsigned int Q = ~(SS ^ SD) & 1; + unsigned int C; + unsigned int S; + unsigned int i; + unsigned long alt = Q ? ~als : als; + + + /* 1st Loop */ + + alo = ald + alt + Q; + C = (((alt >> 31) & (ald >> 31)) + | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); + Q = C ^ SS; + R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); + S = alo >> 31; + sfi = (sfi << (32-N+1)) | Q; + ald = (alo << 1) | (sfi >> 31); + if ((alo >> 31) ^ (ald >> 31)) + { + DBZ = 1; + } + + /* 2nd - N-1th Loop */ + + for (i = 2; i < N; i++) + { + alt = Q ? ~als : als; + alo = ald + alt + Q; + C = (((alt >> 31) & (ald >> 31)) + | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); + Q = C ^ SS; + R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); + S = alo >> 31; + sfi = (sfi << 1) | Q; + ald = (alo << 1) | (sfi >> 31); + if ((alo >> 31) ^ (ald >> 31)) + { + DBZ = 1; + } + } + + /* Nth Loop */ + alt = Q ? ~als : als; + alo = ald + alt + Q; + C = (((alt >> 31) & (ald >> 31)) + | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31))); + Q = C ^ SS; + R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD))); + sfi = (sfi << (32-N+1)); + ald = alo; + + /* End */ + if (alo != 0) + { + alt = Q ? ~als : als; + alo = ald + alt + Q; + } + R1 = R1 & ((~alo >> 31) ^ SD); + if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald; + if (N != 32) + ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q; + else + ald = sfi = sfi | Q; + + OV = DBZ | ((alo == 0) ? 0 : R1); + + * remainder_ptr = alo; + + /* Adj */ + if (((alo != 0) && ((SS ^ SD) ^ R1)) + || ((alo == 0) && (SS ^ R1))) + alo = ald + 1; + else + alo = ald; + + OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31)); + + * quotient_ptr = alo; + * overflow_ptr = OV; +} + +/* sdivun imm5, reg1, reg2, reg3 */ +int +OP_1C207E0 (void) +{ + unsigned32 /*unsigned long int*/ quotient; + unsigned32 /*unsigned long int*/ remainder; + unsigned long int divide_by; + unsigned long int divide_this; + boolean overflow = false; + unsigned int imm5; + + trace_input ("sdivun", OP_IMM_REG_REG_REG, 0); + + imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); + + divide_by = State.regs[ OP[0] ]; + divide_this = State.regs[ OP[1] ] << imm5; + + divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ OP[1] ] = quotient; + State.regs[ OP[2] >> 11 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient & 0x80000000) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); + + return 4; +} + +/* sdivn imm5, reg1, reg2, reg3 */ +int +OP_1C007E0 (void) +{ + signed32 /*signed long int*/ quotient; + signed32 /*signed long int*/ remainder; + signed long int divide_by; + signed long int divide_this; + boolean overflow = false; + unsigned int imm5; + + trace_input ("sdivn", OP_IMM_REG_REG_REG, 0); + + imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); + + divide_by = State.regs[ OP[0] ]; + divide_this = State.regs[ OP[1] ] << imm5; + + divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ OP[1] ] = quotient; + State.regs[ OP[2] >> 11 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient < 0) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); + + return 4; +} + +/* sdivhun imm5, reg1, reg2, reg3 */ +int +OP_18207E0 (void) +{ + unsigned32 /*unsigned long int*/ quotient; + unsigned32 /*unsigned long int*/ remainder; + unsigned long int divide_by; + unsigned long int divide_this; + boolean overflow = false; + unsigned int imm5; + + trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0); + + imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); + + divide_by = State.regs[ OP[0] ] & 0xffff; + divide_this = State.regs[ OP[1] ] << imm5; + + divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ OP[1] ] = quotient; + State.regs[ OP[2] >> 11 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient & 0x80000000) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); + + return 4; +} + +/* sdivhn imm5, reg1, reg2, reg3 */ +int +OP_18007E0 (void) +{ + signed32 /*signed long int*/ quotient; + signed32 /*signed long int*/ remainder; + signed long int divide_by; + signed long int divide_this; + boolean overflow = false; + unsigned int imm5; + + trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0); + + imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); + + divide_by = EXTEND16 (State.regs[ OP[0] ]); + divide_this = State.regs[ OP[1] ] << imm5; + + divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ OP[1] ] = quotient; + State.regs[ OP[2] >> 11 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient < 0) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); + + return 4; +} + +/* divu reg1, reg2, reg3 */ +int +OP_2C207E0 (void) +{ + unsigned long int quotient; + unsigned long int remainder; + unsigned long int divide_by; + unsigned long int divide_this; + boolean overflow = false; + + trace_input ("divu", OP_REG_REG_REG, 0); + + /* Compute the result. */ + + divide_by = State.regs[ OP[0] ]; + divide_this = State.regs[ OP[1] ]; + + if (divide_by == 0) + { + overflow = true; + divide_by = 1; + } + + State.regs[ OP[1] ] = quotient = divide_this / divide_by; + State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient & 0x80000000) PSW |= PSW_S; + + trace_output (OP_REG_REG_REG); + + return 4; +} + +/* div reg1, reg2, reg3 */ +int +OP_2C007E0 (void) +{ + signed long int quotient; + signed long int remainder; + signed long int divide_by; + signed long int divide_this; + boolean overflow = false; + + trace_input ("div", OP_REG_REG_REG, 0); + + /* Compute the result. */ + + divide_by = State.regs[ OP[0] ]; + divide_this = State.regs[ OP[1] ]; + + if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) + { + overflow = true; + divide_by = 1; + } + + State.regs[ OP[1] ] = quotient = divide_this / divide_by; + State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient < 0) PSW |= PSW_S; + + trace_output (OP_REG_REG_REG); + + return 4; +} + +/* divhu reg1, reg2, reg3 */ +int +OP_28207E0 (void) +{ + unsigned long int quotient; + unsigned long int remainder; + unsigned long int divide_by; + unsigned long int divide_this; + boolean overflow = false; + + trace_input ("divhu", OP_REG_REG_REG, 0); + + /* Compute the result. */ + + divide_by = State.regs[ OP[0] ] & 0xffff; + divide_this = State.regs[ OP[1] ]; + + if (divide_by == 0) + { + overflow = true; + divide_by = 1; + } + + State.regs[ OP[1] ] = quotient = divide_this / divide_by; + State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient & 0x80000000) PSW |= PSW_S; + + trace_output (OP_REG_REG_REG); + + return 4; +} + +/* divh reg1, reg2, reg3 */ +int +OP_28007E0 (void) +{ + signed long int quotient; + signed long int remainder; + signed long int divide_by; + signed long int divide_this; + boolean overflow = false; + + trace_input ("divh", OP_REG_REG_REG, 0); + + /* Compute the result. */ + + divide_by = State.regs[ OP[0] ]; + divide_this = EXTEND16 (State.regs[ OP[1] ]); + + if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) + { + overflow = true; + divide_by = 1; + } + + State.regs[ OP[1] ] = quotient = divide_this / divide_by; + State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient < 0) PSW |= PSW_S; + + trace_output (OP_REG_REG_REG); + + return 4; +} + +/* mulu imm9, reg2, reg3 */ +int +OP_24207E0 (void) +{ + trace_input ("mulu", OP_IMM_REG_REG, 0); + + Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)); + + trace_output (OP_IMM_REG_REG); + + return 4; +} + +/* mul imm9, reg2, reg3 */ +int +OP_24007E0 (void) +{ + trace_input ("mul", OP_IMM_REG_REG, 0); + + Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)); + + trace_output (OP_IMM_REG_REG); + + return 4; +} + +/* ld.hu */ +int +OP_107E0 (void) +{ + int adr; + + trace_input ("ld.hu", OP_LOAD32, 2); + + adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1); + adr &= ~0x1; + + State.regs[ OP[1] ] = load_mem (adr, 2); + + trace_output (OP_LOAD32); + + return 4; +} + + +/* ld.bu */ +int +OP_10780 (void) +{ + int adr; + + trace_input ("ld.bu", OP_LOAD32, 1); + + adr = (State.regs[ OP[0] ] + + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1))); + + State.regs[ OP[1] ] = load_mem (adr, 1); + + trace_output (OP_LOAD32); + + return 4; +} + +/* prepare list12, imm5, imm32 */ +int +OP_1B0780 (void) +{ + int i; + + trace_input ("prepare", OP_PUSHPOP1, 0); + + /* Store the registers with lower number registers being placed at higher addresses. */ + for (i = 0; i < 12; i++) + if ((OP[3] & (1 << type1_regs[ i ]))) + { + SP -= 4; + store_mem (SP, 4, State.regs[ 20 + i ]); + } + + SP -= (OP[3] & 0x3e) << 1; + + EP = load_mem (PC + 4, 4); + + trace_output (OP_PUSHPOP1); + + return 8; +} + +/* prepare list12, imm5, imm16-32 */ +int +OP_130780 (void) +{ + int i; + + trace_input ("prepare", OP_PUSHPOP1, 0); + + /* Store the registers with lower number registers being placed at higher addresses. */ + for (i = 0; i < 12; i++) + if ((OP[3] & (1 << type1_regs[ i ]))) + { + SP -= 4; + store_mem (SP, 4, State.regs[ 20 + i ]); + } + + SP -= (OP[3] & 0x3e) << 1; + + EP = load_mem (PC + 4, 2) << 16; + + trace_output (OP_PUSHPOP1); + + return 6; +} + +/* prepare list12, imm5, imm16 */ +int +OP_B0780 (void) +{ + int i; + + trace_input ("prepare", OP_PUSHPOP1, 0); + + /* Store the registers with lower number registers being placed at higher addresses. */ + for (i = 0; i < 12; i++) + if ((OP[3] & (1 << type1_regs[ i ]))) + { + SP -= 4; + store_mem (SP, 4, State.regs[ 20 + i ]); + } + + SP -= (OP[3] & 0x3e) << 1; + + EP = EXTEND16 (load_mem (PC + 4, 2)); + + trace_output (OP_PUSHPOP1); + + return 6; +} + +/* prepare list12, imm5, sp */ +int +OP_30780 (void) +{ + int i; + + trace_input ("prepare", OP_PUSHPOP1, 0); + + /* Store the registers with lower number registers being placed at higher addresses. */ + for (i = 0; i < 12; i++) + if ((OP[3] & (1 << type1_regs[ i ]))) + { + SP -= 4; + store_mem (SP, 4, State.regs[ 20 + i ]); + } + + SP -= (OP[3] & 0x3e) << 1; + + EP = SP; + + trace_output (OP_PUSHPOP1); + + return 4; +} + +/* mul reg1, reg2, reg3 */ +int +OP_22007E0 (void) +{ + trace_input ("mul", OP_REG_REG_REG, 0); + + Multiply64 (true, State.regs[ OP[0] ]); + + trace_output (OP_REG_REG_REG); + + return 4; +} + +/* popmh list18 */ +int +OP_307F0 (void) +{ + int i; + + trace_input ("popmh", OP_PUSHPOP2, 0); + + if (OP[3] & (1 << 19)) + { + if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) + { + FEPSW = load_mem ( SP & ~ 3, 4); + FEPC = load_mem ((SP + 4) & ~ 3, 4); + } + else + { + EIPSW = load_mem ( SP & ~ 3, 4); + EIPC = load_mem ((SP + 4) & ~ 3, 4); + } + + SP += 8; + } + + /* Load the registers with lower number registers being retrieved from higher addresses. */ + for (i = 16; i--;) + if ((OP[3] & (1 << type2_regs[ i ]))) + { + State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4); + SP += 4; + } + + trace_output (OP_PUSHPOP2); + + return 4; +} + +/* popml lsit18 */ +int +OP_107F0 (void) +{ + int i; + + trace_input ("popml", OP_PUSHPOP3, 0); + + if (OP[3] & (1 << 19)) + { + if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) + { + FEPSW = load_mem ( SP & ~ 3, 4); + FEPC = load_mem ((SP + 4) & ~ 3, 4); + } + else + { + EIPSW = load_mem ( SP & ~ 3, 4); + EIPC = load_mem ((SP + 4) & ~ 3, 4); + } + + SP += 8; + } + + if (OP[3] & (1 << 3)) + { + PSW = load_mem (SP & ~ 3, 4); + SP += 4; + } + + /* Load the registers with lower number registers being retrieved from higher addresses. */ + for (i = 15; i--;) + if ((OP[3] & (1 << type3_regs[ i ]))) + { + State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4); + SP += 4; + } + + trace_output (OP_PUSHPOP2); + + return 4; +} + +/* pushmh list18 */ +int +OP_307E0 (void) +{ + int i; + + trace_input ("pushmh", OP_PUSHPOP2, 0); + + /* Store the registers with lower number registers being placed at higher addresses. */ + for (i = 0; i < 16; i++) + if ((OP[3] & (1 << type2_regs[ i ]))) + { + SP -= 4; + store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]); + } + + if (OP[3] & (1 << 19)) + { + SP -= 8; + + if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) + { + store_mem ((SP + 4) & ~ 3, 4, FEPC); + store_mem ( SP & ~ 3, 4, FEPSW); + } + else + { + store_mem ((SP + 4) & ~ 3, 4, EIPC); + store_mem ( SP & ~ 3, 4, EIPSW); + } + } + + trace_output (OP_PUSHPOP2); + + return 4; +} + diff --git a/sim/v850/v850-dc b/sim/v850/v850-dc new file mode 100644 index 0000000..997a375 --- /dev/null +++ b/sim/v850/v850-dc @@ -0,0 +1,30 @@ +# most instructions +# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ... +# { : mask : value : word } + +# Top level - create a very big switch statement. + + padded-switch,combine : 15 : 5 : : : : 0 : : + + +# for opcode 60,124 + + switch,combine : 4 : 0 : : : : 1 : V,VII : + switch,combine : 4 : 0 : : : : 1 : V,XIII : v850e + switch,combine : 4 : 0 : : : : 1 : V,XIII : v850ea + + +# for opcode 63, 127, 1087 et.al. + + switch,combine : 9 : 5 : : : : 1 : : + switch,combine : 4 : 0 : : : : 1 : : + + +# for opcode 40 et.al. + + switch,combine : 4 : 0 : : : : 0 : III,IV : + switch,combine : 4 : 0 : : : : 0 : III,IV,XIV : v850ea + +# for opcode 66 - divh/break + + switch,combine : 4 : 0 : : : : 0 : I : diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen new file mode 100644 index 0000000..724b0be --- /dev/null +++ b/sim/v850/v850.igen @@ -0,0 +1,1407 @@ +:option:::insn-bit-size:16 +:option:::hi-bit-nr:15 + + +:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X +:option:::format-names:XI,XII,XIII +:option:::format-names:XIV,XV +:option:::format-names:Z + + +:model:::v850:v850: + +:option:::multi-sim:true +:model:::v850e:v850e: + +:option:::multi-sim:true +:model:::v850ea:v850ea: + + + +// Cache macros + +:cache:::unsigned:reg1:RRRRR:(RRRRR) +:cache:::unsigned:reg2:rrrrr:(rrrrr) +:cache:::unsigned:reg3:wwwww:(wwwww) + +:cache:::unsigned:disp4:dddd:(dddd) +:cache:::unsigned:disp5:dddd:(dddd << 1) +:cache:::unsigned:disp7:ddddddd:ddddddd +:cache:::unsigned:disp8:ddddddd:(ddddddd << 1) +:cache:::unsigned:disp8:dddddd:(dddddd << 2) +:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1) +:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd) +:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1) +:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1) + +:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4) +:cache:::unsigned:imm6:iiiiii:iiiiii +:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1) +:cache:::unsigned:imm5:iiii:(32 - (iiii << 1)) +:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii) +:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii +:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII) +:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd) + +:cache:::unsigned:vector:iiiii:iiiii + +:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL) +:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL) + +:cache:::unsigned:bit3:bbb:bbb + + +// What do we do with an illegal instruction? +:internal::::illegal: +{ + sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n", + (unsigned long) cia); + sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL); +} + + + +// Add + +rrrrr,001110,RRRRR:I:::add +"add r, r" +{ + COMPAT_1 (OP_1C0 ()); +} + +rrrrr,010010,iiiii:II:::add +"add ,r" +{ + COMPAT_1 (OP_240 ()); +} + + + +// ADDI +rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi +"addi , r, r" +{ + COMPAT_2 (OP_600 ()); +} + + + +// AND +rrrrr,001010,RRRRR:I:::and +"and r, r" +{ + COMPAT_1 (OP_140 ()); +} + + + +// ANDI +rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi +"andi , r, r" +{ + COMPAT_2 (OP_6C0 ()); +} + + + +// Map condition code to a string +:%s::::cccc:int cccc +{ + switch (cccc) + { + case 0xf: return "gt"; + case 0xe: return "ge"; + case 0x6: return "lt"; + + case 0x7: return "le"; + + case 0xb: return "h"; + case 0x9: return "nl"; + case 0x1: return "l"; + + case 0x3: return "nh"; + + case 0x2: return "e"; + + case 0xa: return "ne"; + + case 0x0: return "v"; + case 0x8: return "nv"; + case 0x4: return "n"; + case 0xc: return "p"; + /* case 0x1: return "c"; */ + /* case 0x9: return "nc"; */ + /* case 0x2: return "z"; */ + /* case 0xa: return "nz"; */ + case 0x5: return "r"; /* always */ + case 0xd: return "sa"; + } + return "(null)"; +} + + +// Bcond +ddddd,1011,ddd,cccc:III:::Bcond +"b%s " +{ + int cond = condition_met (cccc); + if (cond) + nia = cia + disp9; + TRACE_BRANCH1 (cond); +} + + + +// BSH +rrrrr,11111100000 + wwwww,01101000010:XII:::bsh +*v850e +*v850ea +"bsh r, r" +{ + unsigned32 value; + TRACE_ALU_INPUT1 (GR[reg2]); + + value = (MOVED32 (GR[reg2], 23, 16, 31, 24) + | MOVED32 (GR[reg2], 31, 24, 23, 16) + | MOVED32 (GR[reg2], 7, 0, 15, 8) + | MOVED32 (GR[reg2], 15, 8, 7, 0)); + + GR[reg3] = value; + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + if (value == 0) PSW |= PSW_Z; + if (value & 0x80000000) PSW |= PSW_S; + if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY; + + TRACE_ALU_RESULT (GR[reg3]); +} + +// BSW +rrrrr,11111100000 + wwwww,01101000000:XII:::bsw +*v850e +*v850ea +"bsw r, r" +{ +#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080) + unsigned32 value; + TRACE_ALU_INPUT1 (GR[reg2]); + + value = GR[reg2]; + value >>= 24; + value |= (GR[reg2] << 24); + value |= ((GR[reg2] << 8) & 0x00ff0000); + value |= ((GR[reg2] >> 8) & 0x0000ff00); + GR[reg3] = value; + + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + + if (value == 0) PSW |= PSW_Z; + if (value & 0x80000000) PSW |= PSW_S; + if (WORDHASNULLBYTE (value)) PSW |= PSW_CY; + + TRACE_ALU_RESULT (GR[reg3]); +} + +// CALLT +0000001000,iiiiii:II:::callt +*v850e +*v850ea +"callt " +{ + unsigned32 adr; + unsigned32 off; + CTPC = cia + 2; + CTPSW = PSW; + adr = (CTBP & ~1) + (imm6 << 1); + off = load_mem (adr, 2) & ~1; /* Force alignment */ + nia = (CTBP & ~1) + off; + TRACE_BRANCH3 (adr, CTBP, off); +} + + +// CLR1 +10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1 +"clr1 , [r]" +{ + COMPAT_2 (OP_87C0 ()); +} + +rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 +*v850e +*v850ea +"clr1 r, [r]" +{ + COMPAT_2 (OP_E407E0 ()); +} + + +// CTRET +0000011111100000 + 0000000101000100:X:::ctret +*v850e +*v850ea +"ctret" +{ + nia = (CTPC & ~1); + PSW = (CTPSW & (CPU)->psw_mask); + TRACE_BRANCH1 (PSW); +} + +// CMOV +rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov +*v850e +*v850ea +"cmov %s, r, r, r" +{ + int cond = condition_met (cccc); + TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]); + GR[reg3] = cond ? GR[reg1] : GR[reg2]; + TRACE_ALU_RESULT (GR[reg3]); +} + +rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov +*v850e +*v850ea +"cmov %s, , r, r" +{ + int cond = condition_met (cccc); + TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]); + GR[reg3] = cond ? imm5 : GR[reg2]; + TRACE_ALU_RESULT (GR[reg3]); +} + +// CMP +rrrrr,001111,RRRRR:I:::cmp +"cmp r, r" +{ + COMPAT_1 (OP_1E0 ()); +} + +rrrrr,010011,iiiii:II:::cmp +"cmp , r" +{ + COMPAT_1 (OP_260 ()); +} + + + +// DI +0000011111100000 + 0000000101100000:X:::di +"di" +{ + COMPAT_2 (OP_16007E0 ()); +} + + + +// DISPOSE +// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose +// "dispose , " +0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose +*v850e +*v850ea +"dispose , ":RRRRR == 0 +"dispose , , [reg1]" +{ + int i; + SAVE_2; + + trace_input ("dispose", OP_PUSHPOP1, 0); + + SP += (OP[3] & 0x3e) << 1; + + /* Load the registers with lower number registers being retrieved + from higher addresses. */ + for (i = 12; i--;) + if ((OP[3] & (1 << type1_regs[ i ]))) + { + State.regs[ 20 + i ] = load_mem (SP, 4); + SP += 4; + } + + if ((OP[3] & 0x1f0000) != 0) + { + nia = State.regs[ (OP[3] >> 16) & 0x1f]; + } + + trace_output (OP_PUSHPOP1); +} + + +// DIV +rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div +*v850e +"div r, r, r" +{ + COMPAT_2 (OP_2C007E0 ()); +} + + +// DIVH +rrrrr!0,000010,RRRRR!0:I:::divh +"divh r, r" +{ + COMPAT_1 (OP_40 ()); +} + +rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh +*v850e +"divh r, r, r" +{ + COMPAT_2 (OP_28007E0 ()); +} + + +// DIVHU +rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu +*v850e +"divhu r, r, r" +{ + COMPAT_2 (OP_28207E0 ()); +} + + +// DIVU +rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu +*v850e +"divu r, r, r" +{ + COMPAT_2 (OP_2C207E0 ()); +} + + +// EI +1000011111100000 + 0000000101100000:X:::ei +"ei" +{ + COMPAT_2 (OP_16087E0 ()); +} + + + +// HALT +0000011111100000 + 0000000100100000:X:::halt +"halt" +{ + COMPAT_2 (OP_12007E0 ()); +} + + + +// HSW +rrrrr,11111100000 + wwwww,01101000100:XII:::hsw +*v850e +*v850ea +"hsw r, r" +{ + unsigned32 value; + TRACE_ALU_INPUT1 (GR[reg2]); + + value = GR[reg2]; + value >>= 16; + value |= (GR[reg2] << 16); + + GR[reg3] = value; + + PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); + + if (value == 0) PSW |= PSW_Z; + if (value & 0x80000000) PSW |= PSW_S; + if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY; + + TRACE_ALU_RESULT (GR[reg3]); +} + + + +// JARL +rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl +"jarl , r" +{ + GR[reg2] = nia; + nia = cia + disp22; + TRACE_BRANCH1 (GR[reg2]); +} + + + +// JMP +00000000011,RRRRR:I:::jmp +"jmp [r]" +{ + nia = GR[reg1] & ~1; + TRACE_BRANCH0 (); +} + + + +// JR +0000011110,dddddd + ddddddddddddddd,0:V:::jr +"jr " +{ + nia = cia + disp22; + TRACE_BRANCH0 (); +} + + + +// LD +rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b +"ld.b [r], r" +{ + COMPAT_2 (OP_700 ()); +} + +rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h +"ld.h [r], r" +{ + COMPAT_2 (OP_720 ()); +} + +rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w +"ld.w [r], r" +{ + COMPAT_2 (OP_10720 ()); +} + +rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu +*v850e +*v850ea +"ld.bu [r], r" +{ + COMPAT_2 (OP_10780 ()); +} + +rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu +*v850e +*v850ea +"ld.hu [r], r" +{ + COMPAT_2 (OP_107E0 ()); +} + + +// LDSR +regID,111111,RRRRR + 0000000000100000:IX:::ldsr +"ldsr r, s" +{ + TRACE_ALU_INPUT1 (GR[reg1]); + + if (&PSW == &SR[regID]) + PSW = (GR[reg1] & (CPU)->psw_mask); + else + SR[regID] = GR[reg1]; + + TRACE_ALU_RESULT (SR[regID]); +} + + + +// MOV +rrrrr!0,000000,RRRRR:I:::mov +"mov r, r" +{ + TRACE_ALU_INPUT0 (); + GR[reg2] = GR[reg1]; + TRACE_ALU_RESULT (GR[reg2]); +} + + +rrrrr!0,010000,iiiii:II:::mov +"mov , r" +{ + COMPAT_1 (OP_200 ()); +} + +00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov +*v850e +*v850ea +"mov , r" +{ + SAVE_2; + trace_input ("mov", OP_IMM_REG, 4); + State.regs[ OP[0] ] = load_mem (PC + 2, 4); + trace_output (OP_IMM_REG); +} + + + +// MOVEA +rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea +"movea , r, r" +{ + TRACE_ALU_INPUT2 (GR[reg1], simm16); + GR[reg2] = GR[reg1] + simm16; + TRACE_ALU_RESULT (GR[reg2]); +} + + + +// MOVHI +rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi +"movhi , r, r" +{ + COMPAT_2 (OP_640 ()); +} + + + +// MUL +rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul +*v850e +*v850ea +"mul r, r, r" +{ + COMPAT_2 (OP_22007E0 ()); +} + +rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul +*v850e +*v850ea +"mul , r, r" +{ + COMPAT_2 (OP_24007E0 ()); +} + + +// MULH +rrrrr!0,000111,RRRRR:I:::mulh +"mulh r, r" +{ + COMPAT_1 (OP_E0 ()); +} + +rrrrr!0,010111,iiiii:II:::mulh +"mulh , r" +{ + COMPAT_1 (OP_2E0 ()); +} + + + +// MULHI +rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi +"mulhi , r, r" +{ + COMPAT_2 (OP_6E0 ()); +} + + + +// MULU +rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu +*v850e +*v850ea +"mulu r, r, r" +{ + COMPAT_2 (OP_22207E0 ()); +} + +rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu +*v850e +*v850ea +"mulu , r, r" +{ + COMPAT_2 (OP_24207E0 ()); +} + + + +// NOP +0000000000000000:I:::nop +"nop" +{ + /* do nothing, trace nothing */ +} + + + +// NOT +rrrrr,000001,RRRRR:I:::not +"not r, r" +{ + COMPAT_1 (OP_20 ()); +} + + + +// NOT1 +01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1 +"not1 , [r]" +{ + COMPAT_2 (OP_47C0 ()); +} + +rrrrr,111111,RRRRR + 0000000011100010:IX:::not1 +*v850e +*v850ea +"not1 r, r" +{ + COMPAT_2 (OP_E207E0 ()); +} + + + +// OR +rrrrr,001000,RRRRR:I:::or +"or r, r" +{ + COMPAT_1 (OP_100 ()); +} + + + +// ORI +rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori +"ori , r, r" +{ + COMPAT_2 (OP_680 ()); +} + + + +// PREPARE +0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare +*v850e +*v850ea +"prepare , " +{ + int i; + SAVE_2; + + trace_input ("prepare", OP_PUSHPOP1, 0); + + /* Store the registers with lower number registers being placed at + higher addresses. */ + for (i = 0; i < 12; i++) + if ((OP[3] & (1 << type1_regs[ i ]))) + { + SP -= 4; + store_mem (SP, 4, State.regs[ 20 + i ]); + } + + SP -= (OP[3] & 0x3e) << 1; + + trace_output (OP_PUSHPOP1); +} + + +0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00 +*v850e +*v850ea +"prepare , , sp" +{ + COMPAT_2 (OP_30780 ()); +} + +0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01 +*v850e +*v850ea +"prepare , , " +{ + COMPAT_2 (OP_B0780 ()); +} + +0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10 +*v850e +*v850ea +"prepare , , " +{ + COMPAT_2 (OP_130780 ()); +} + +0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11 +*v850e +*v850ea +"prepare , , " +{ + COMPAT_2 (OP_1B0780 ()); +} + + + +// RETI +0000011111100000 + 0000000101000000:X:::reti +"reti" +{ + if ((PSW & PSW_EP)) + { + nia = (EIPC & ~1); + PSW = EIPSW; + } + else if ((PSW & PSW_NP)) + { + nia = (FEPC & ~1); + PSW = FEPSW; + } + else + { + nia = (EIPC & ~1); + PSW = EIPSW; + } + TRACE_BRANCH1 (PSW); +} + + + +// SAR +rrrrr,111111,RRRRR + 0000000010100000:IX:::sar +"sar r, r" +{ + COMPAT_2 (OP_A007E0 ()); +} + +rrrrr,010101,iiiii:II:::sar +"sar , r" +{ + COMPAT_1 (OP_2A0 ()); +} + + + +// SASF +rrrrr,1111110,cccc + 0000001000000000:IX:::sasf +*v850e +*v850ea +"sasf %s, r" +{ + COMPAT_2 (OP_20007E0 ()); +} + + + + +// SATADD +rrrrr!0,000110,RRRRR:I:::satadd +"satadd r, r" +{ + COMPAT_1 (OP_C0 ()); +} + +rrrrr!0,010001,iiiii:II:::satadd +"satadd , r" +{ + COMPAT_1 (OP_220 ()); +} + + + +// SATSUB +rrrrr!0,000101,RRRRR:I:::satsub +"satsub r, r" +{ + COMPAT_1 (OP_A0 ()); +} + + + +// SATSUBI +rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi +"satsubi , r, r" +{ + COMPAT_2 (OP_660 ()); +} + + + +// SATSUBR +rrrrr!0,000100,RRRRR:I:::satsubr +"satsubr r, r" +{ + COMPAT_1 (OP_80 ()); +} + + + +// SETF +rrrrr,1111110,cccc + 0000000000000000:IX:::setf +"setf %s, r" +{ + COMPAT_2 (OP_7E0 ()); +} + + + +// SET1 +00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1 +"set1 , [r]" +{ + COMPAT_2 (OP_7C0 ()); +} + +rrrrr,111111,RRRRR + 0000000011100000:IX:::set1 +*v850e +*v850ea +"set1 r, [r]" +{ + COMPAT_2 (OP_E007E0 ()); +} + + + +// SHL +rrrrr,111111,RRRRR + 0000000011000000:IX:::shl +"shl r, r" +{ + COMPAT_2 (OP_C007E0 ()); +} + +rrrrr,010110,iiiii:II:::shl +"shl , r" +{ + COMPAT_1 (OP_2C0 ()); +} + + + +// SHR +rrrrr,111111,RRRRR + 0000000010000000:IX:::shr +"shr r, r" +{ + COMPAT_2 (OP_8007E0 ()); +} + +rrrrr,010100,iiiii:II:::shr +"shr , r" +{ + COMPAT_1 (OP_280 ()); +} + + + +// SLD +rrrrr,0110,ddddddd:IV:::sld.b +"sld.bu [ep], r":(PSW & PSW_US) +"sld.b [ep], r" +{ + unsigned32 addr = EP + disp7; + unsigned32 result = load_mem (addr, 1); + if (PSW & PSW_US) + { + GR[reg2] = result; + TRACE_LD_NAME ("sld.bu", addr, result); + } + else + { + result = EXTEND8 (result); + GR[reg2] = result; + TRACE_LD (addr, result); + } +} + +rrrrr,1000,ddddddd:IV:::sld.h +"sld.hu [ep], r":(PSW & PSW_US) +"sld.h [ep], r" +{ + unsigned32 addr = EP + disp8; + unsigned32 result = load_mem (addr, 2); + if (PSW & PSW_US) + { + GR[reg2] = result; + TRACE_LD_NAME ("sld.hu", addr, result); + } + else + { + result = EXTEND16 (result); + GR[reg2] = result; + TRACE_LD (addr, result); + } +} + +rrrrr,1010,dddddd,0:IV:::sld.w +"sld.w [ep], r" +{ + unsigned32 addr = EP + disp8; + unsigned32 result = load_mem (addr, 4); + GR[reg2] = result; + TRACE_LD (addr, result); +} + +rrrrr!0,0000110,dddd:IV:::sld.bu +*v850e +*v850ea +"sld.b [ep], r":(PSW & PSW_US) +"sld.bu [ep], r" +{ + unsigned32 addr = EP + disp4; + unsigned32 result = load_mem (addr, 1); + if (PSW & PSW_US) + { + result = EXTEND8 (result); + GR[reg2] = result; + TRACE_LD_NAME ("sld.b", addr, result); + } + else + { + GR[reg2] = result; + TRACE_LD (addr, result); + } +} + +rrrrr!0,0000111,dddd:IV:::sld.hu +*v850e +*v850ea +"sld.h [ep], r":(PSW & PSW_US) +"sld.hu [ep], r" +{ + unsigned32 addr = EP + disp5; + unsigned32 result = load_mem (addr, 2); + if (PSW & PSW_US) + { + result = EXTEND16 (result); + GR[reg2] = result; + TRACE_LD_NAME ("sld.h", addr, result); + } + else + { + GR[reg2] = result; + TRACE_LD (addr, result); + } +} + + +// SST +rrrrr,0111,ddddddd:IV:::sst.b +"sst.b r, [ep]" +{ + COMPAT_1 (OP_380 ()); +} + +rrrrr,1001,ddddddd:IV:::sst.h +"sst.h r, [ep]" +{ + COMPAT_1 (OP_480 ()); +} + +rrrrr,1010,dddddd,1:IV:::sst.w +"sst.w r, [ep]" +{ + COMPAT_1 (OP_501 ()); +} + + + +// ST +rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b +"st.b r, [r]" +{ + COMPAT_2 (OP_740 ()); +} + +rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h +"st.h r, [r]" +{ + COMPAT_2 (OP_760 ()); +} + +rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w +"st.w r, [r]" +{ + COMPAT_2 (OP_10760 ()); +} + + + +// STSR +rrrrr,111111,regID + 0000000001000000:IX:::stsr +"stsr s, r" +{ + TRACE_ALU_INPUT1 (SR[regID]); + GR[reg2] = SR[regID]; + TRACE_ALU_RESULT (GR[reg2]); +} + + + +// SUB +rrrrr,001101,RRRRR:I:::sub +"sub r, r" +{ + COMPAT_1 (OP_1A0 ()); +} + + + +// SUBR +rrrrr,001100,RRRRR:I:::subr +"subr r, r" +{ + COMPAT_1 (OP_180 ()); +} + + + +// SWITCH +00000000010,RRRRR:I:::switch +*v850e +*v850ea +"switch r" +{ + unsigned long adr; + SAVE_1; + trace_input ("switch", OP_REG, 0); + adr = (cia + 2) + (State.regs[ reg1 ] << 1); + nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1); + trace_output (OP_REG); +} + + +// SXB +00000000101,RRRRR:I:::sxb +*v850e +*v850ea +"sxb r" +{ + TRACE_ALU_INPUT1 (GR[reg1]); + GR[reg1] = EXTEND8 (GR[reg1]); + TRACE_ALU_RESULT (GR[reg1]); +} + +// SXH +00000000111,RRRRR:I:::sxh +*v850e +*v850ea +"sxh r" +{ + TRACE_ALU_INPUT1 (GR[reg1]); + GR[reg1] = EXTEND16 (GR[reg1]); + TRACE_ALU_RESULT (GR[reg1]); +} + + + +// TRAP +00000111111,iiiii + 0000000100000000:X:::trap +"trap " +{ + COMPAT_2 (OP_10007E0 ()); +} + + + +// TST +rrrrr,001011,RRRRR:I:::tst +"tst r, r" +{ + COMPAT_1 (OP_160 ()); +} + + + +// TST1 +11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1 +"tst1 , [r]" +{ + COMPAT_2 (OP_C7C0 ()); +} + +rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1 +*v850e +*v850ea +"tst1 r, [r]" +{ + COMPAT_2 (OP_E607E0 ()); +} + + + +// XOR +rrrrr,001001,RRRRR:I:::xor +"xor r, r" +{ + COMPAT_1 (OP_120 ()); +} + + + +// XORI +rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori +"xori , r, r" +{ + COMPAT_2 (OP_6A0 ()); +} + + + +// ZXB +00000000100,RRRRR:I:::zxb +*v850e +*v850ea +"zxb r" +{ + TRACE_ALU_INPUT1 (GR[reg1]); + GR[reg1] = GR[reg1] & 0xff; + TRACE_ALU_RESULT (GR[reg1]); +} + +// ZXH +00000000110,RRRRR:I:::zxh +*v850e +*v850ea +"zxh r" +{ + TRACE_ALU_INPUT1 (GR[reg1]); + GR[reg1] = GR[reg1] & 0xffff; + TRACE_ALU_RESULT (GR[reg1]); +} + + +// Right field must be zero so that it doesn't clash with DIVH +// Left field must be non-zero so that it doesn't clash with SWITCH +11111,000010,00000:I:::break +{ + sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); +} + + + +// DIVHN +rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn +*v850ea +"divhn , r, r, r" +{ + signed32 quotient; + signed32 remainder; + signed32 divide_by; + signed32 divide_this; + boolean overflow = false; + SAVE_2; + + trace_input ("divhn", OP_IMM_REG_REG_REG, 0); + + divide_by = EXTEND16 (State.regs[ reg1 ]); + divide_this = State.regs[ reg2 ]; + + divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ reg2 ] = quotient; + State.regs[ reg3 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient < 0) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); +} + + + +// DIVHUN +rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun +*v850ea +"divhun , r, r, r" +{ + signed32 quotient; + signed32 remainder; + signed32 divide_by; + signed32 divide_this; + boolean overflow = false; + SAVE_2; + + trace_input ("divhun", OP_IMM_REG_REG_REG, 0); + + divide_by = State.regs[ reg1 ] & 0xffff; + divide_this = State.regs[ reg2 ]; + + divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ reg2 ] = quotient; + State.regs[ reg3 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient & 0x80000000) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); +} + + + +// DIVN +rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn +*v850ea +"divn , r, r, r" +{ + signed32 quotient; + signed32 remainder; + signed32 divide_by; + signed32 divide_this; + boolean overflow = false; + SAVE_2; + + trace_input ("divn", OP_IMM_REG_REG_REG, 0); + + divide_by = State.regs[ reg1 ]; + divide_this = State.regs[ reg2 ]; + + divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ reg2 ] = quotient; + State.regs[ reg3 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient < 0) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); +} + + + +// DIVUN +rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun +*v850ea +"divun , r, r, r" +{ + signed32 quotient; + signed32 remainder; + signed32 divide_by; + signed32 divide_this; + boolean overflow = false; + SAVE_2; + + trace_input ("divun", OP_IMM_REG_REG_REG, 0); + + divide_by = State.regs[ reg1 ]; + divide_this = State.regs[ reg2 ]; + + divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); + + State.regs[ reg2 ] = quotient; + State.regs[ reg3 ] = remainder; + + /* Set condition codes. */ + PSW &= ~(PSW_Z | PSW_S | PSW_OV); + + if (overflow) PSW |= PSW_OV; + if (quotient == 0) PSW |= PSW_Z; + if (quotient & 0x80000000) PSW |= PSW_S; + + trace_output (OP_IMM_REG_REG_REG); +} + + + +// SDIVHN +rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn +*v850ea +"sdivhn , r, r, r" +{ + COMPAT_2 (OP_18007E0 ()); +} + + + +// SDIVHUN +rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun +*v850ea +"sdivhun , r, r, r" +{ + COMPAT_2 (OP_18207E0 ()); +} + + + +// SDIVN +rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn +*v850ea +"sdivn , r, r, r" +{ + COMPAT_2 (OP_1C007E0 ()); +} + + + +// SDIVUN +rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun +*v850ea +"sdivun , r, r, r" +{ + COMPAT_2 (OP_1C207E0 ()); +} + + + +// PUSHML +000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml +*v850ea +"pushml " +{ + int i; + SAVE_2; + + trace_input ("pushml", OP_PUSHPOP3, 0); + + /* Store the registers with lower number registers being placed at + higher addresses. */ + + for (i = 0; i < 15; i++) + if ((OP[3] & (1 << type3_regs[ i ]))) + { + SP -= 4; + store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]); + } + + if (OP[3] & (1 << 3)) + { + SP -= 4; + + store_mem (SP & ~ 3, 4, PSW); + } + + if (OP[3] & (1 << 19)) + { + SP -= 8; + + if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0)) + { + store_mem ((SP + 4) & ~ 3, 4, FEPC); + store_mem ( SP & ~ 3, 4, FEPSW); + } + else + { + store_mem ((SP + 4) & ~ 3, 4, EIPC); + store_mem ( SP & ~ 3, 4, EIPSW); + } + } + + trace_output (OP_PUSHPOP2); +} + + + +// PUSHHML +000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh +*v850ea +"pushhml " +{ + COMPAT_2 (OP_307E0 ()); +} + + + +// POPML +000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml +*v850ea +"popml " +{ + COMPAT_2 (OP_107F0 ()); +} + + + +// POPMH +000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh +*v850ea +"popmh " +{ + COMPAT_2 (OP_307F0 ()); +} + diff --git a/sim/v850/v850_sim.h b/sim/v850/v850_sim.h new file mode 100644 index 0000000..bf59727 --- /dev/null +++ b/sim/v850/v850_sim.h @@ -0,0 +1,8 @@ +struct simops +{ + unsigned long opcode; + unsigned long mask; + int (* func) PARAMS ((void)); + int numops; + int operands[12]; +}; -- cgit v1.1