From 477904ca751c50d243ee3cba3f12cf75e8ba12b3 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Wed, 6 Apr 2022 11:10:40 -0400 Subject: Fix for v850e divq instruction This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch. --- sim/v850/simops.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sim/v850') diff --git a/sim/v850/simops.c b/sim/v850/simops.c index e9a5d48..f90a0f7 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -3135,8 +3135,8 @@ v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, u bfd_boolean overflow = FALSE; /* Compute the result. */ - divide_by = op0; - divide_this = op1; + divide_by = (int32_t)op0; + divide_this = (int32_t)op1; if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31))) { -- cgit v1.1