From 676a64f422161303f6d57fca0d244400a1cdd576 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 1 Mar 2004 10:11:46 +0000 Subject: Add fr450 support. --- sim/testsuite/ChangeLog | 18 ++++++ sim/testsuite/sim/frv/allinsn.exp | 2 +- sim/testsuite/sim/frv/fr400/addss.cgs | 2 +- sim/testsuite/sim/frv/fr400/allinsn.exp | 2 +- sim/testsuite/sim/frv/fr400/scutss.cgs | 2 +- sim/testsuite/sim/frv/fr400/slass.cgs | 2 +- sim/testsuite/sim/frv/fr400/smass.cgs | 2 +- sim/testsuite/sim/frv/fr400/smsss.cgs | 2 +- sim/testsuite/sim/frv/fr400/smu.cgs | 2 +- sim/testsuite/sim/frv/fr400/subss.cgs | 2 +- .../sim/frv/interrupts/fp_exception-fr550.cgs | 2 +- sim/testsuite/sim/frv/interrupts/fp_exception.cgs | 2 +- sim/testsuite/sim/frv/mqlclrhs.cgs | 74 ++++++++++++++++++++++ sim/testsuite/sim/frv/mqlmths.cgs | 74 ++++++++++++++++++++++ sim/testsuite/sim/frv/mqsllhi.cgs | 40 ++++++++++++ sim/testsuite/sim/frv/mqsrahi.cgs | 40 ++++++++++++ 16 files changed, 257 insertions(+), 11 deletions(-) create mode 100644 sim/testsuite/sim/frv/mqlclrhs.cgs create mode 100644 sim/testsuite/sim/frv/mqlmths.cgs create mode 100644 sim/testsuite/sim/frv/mqsllhi.cgs create mode 100644 sim/testsuite/sim/frv/mqsrahi.cgs (limited to 'sim/testsuite') diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index e1d6069..a344a6d 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,5 +1,23 @@ 2004-03-01 Richard Sandiford + * sim/frv/allinsn.exp (all_machs): Add fr405 and fr450. + * sim/fr400/allinsn.exp (all_machs): Likewise. + * sim/fr400/addss.cgs (mach): Change to "fr405 fr450". + * sim/fr400/scutss.cgs (mach): Likewise. + * sim/fr400/slass.cgs (mach): Likewise. + * sim/fr400/smass.cgs (mach): Likewise. + * sim/fr400/smsss.cgs (mach): Likewise. + * sim/fr400/smu.cgs (mach): Likewise. + * sim/fr400/subss.cgs (mach): Likewise. + * sim/interrupts/fp_exception.cgs: Replace fmadds with .word. + * sim/interrupts/fp_exception-fr550.cgs: Likewise. + * sim/frv/mqlclrhs.cgs: New test. + * sim/frv/mqlmths.cgs: New test. + * sim/frv/mqsllhi.cgs: New test. + * sim/frv/mqsrahi.cgs: New test. + +2004-03-01 Richard Sandiford + * sim/frv/fr400/scutss.cgs: Fix tests to account for rounding. Add some new ones. diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp index 220550d..b7f9fe2 100644 --- a/sim/testsuite/sim/frv/allinsn.exp +++ b/sim/testsuite/sim/frv/allinsn.exp @@ -4,7 +4,7 @@ if [istarget frv*-*] { # load support procs (none yet) # load_lib cgen.exp # all machines - set all_machs "frv fr500 fr550 fr400" + set all_machs "frv fr500 fr550 fr400 fr405 fr450" set cpu_option -mcpu # The .cgs suffix is for "cgen .s". diff --git a/sim/testsuite/sim/frv/fr400/addss.cgs b/sim/testsuite/sim/frv/fr400/addss.cgs index 631d574..b108f50 100644 --- a/sim/testsuite/sim/frv/fr400/addss.cgs +++ b/sim/testsuite/sim/frv/fr400/addss.cgs @@ -1,5 +1,5 @@ # frv testcase for addss $GRi,$GRj,$GRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp index 53394ec..b169761 100644 --- a/sim/testsuite/sim/frv/fr400/allinsn.exp +++ b/sim/testsuite/sim/frv/fr400/allinsn.exp @@ -4,7 +4,7 @@ if [istarget frv*-*] { # load support procs (none yet) # load_lib cgen.exp # all machines - set all_machs "fr400 fr550" + set all_machs "fr400 fr405 fr450 fr550" set cpu_option -mcpu # The .cgs suffix is for "cgen .s". diff --git a/sim/testsuite/sim/frv/fr400/scutss.cgs b/sim/testsuite/sim/frv/fr400/scutss.cgs index f77a982..f958de6 100644 --- a/sim/testsuite/sim/frv/fr400/scutss.cgs +++ b/sim/testsuite/sim/frv/fr400/scutss.cgs @@ -1,5 +1,5 @@ # frv testcase for scutss $FRj,$FRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/slass.cgs b/sim/testsuite/sim/frv/fr400/slass.cgs index 0100052..3e8bcac 100644 --- a/sim/testsuite/sim/frv/fr400/slass.cgs +++ b/sim/testsuite/sim/frv/fr400/slass.cgs @@ -1,5 +1,5 @@ # frv testcase for slass $GRi,$GRj,$GRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/smass.cgs b/sim/testsuite/sim/frv/fr400/smass.cgs index 3df0fa5..4594ecd 100644 --- a/sim/testsuite/sim/frv/fr400/smass.cgs +++ b/sim/testsuite/sim/frv/fr400/smass.cgs @@ -1,5 +1,5 @@ # frv testcase for smass $GRi,$GRj -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/smsss.cgs b/sim/testsuite/sim/frv/fr400/smsss.cgs index 56efa56..50876d8 100644 --- a/sim/testsuite/sim/frv/fr400/smsss.cgs +++ b/sim/testsuite/sim/frv/fr400/smsss.cgs @@ -1,5 +1,5 @@ # frv testcase for smsss $GRi,$GRj -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/smu.cgs b/sim/testsuite/sim/frv/fr400/smu.cgs index d0087df..eae788e 100644 --- a/sim/testsuite/sim/frv/fr400/smu.cgs +++ b/sim/testsuite/sim/frv/fr400/smu.cgs @@ -1,5 +1,5 @@ # frv testcase for smu $GRi,$GRj -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/fr400/subss.cgs b/sim/testsuite/sim/frv/fr400/subss.cgs index cbaafb5..fcda589 100644 --- a/sim/testsuite/sim/frv/fr400/subss.cgs +++ b/sim/testsuite/sim/frv/fr400/subss.cgs @@ -1,5 +1,5 @@ # frv testcase for subss $GRi,$GRj,$GRk -# mach: fr400 +# mach: fr405 fr450 .include "../testutils.inc" diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs index 0bb98d8..5d1c3f5 100644 --- a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs +++ b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs @@ -70,7 +70,7 @@ pack: fnegs fr10,fr12 set_spr_addr ok1,lr set_gr_immed 4,gr20 ; PC increment -bad: fmadds fr16,fr4,fr1 ; unimplemented +bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) test_gr_immed 4,gr15 and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs index ad5f7e4..0109b53 100644 --- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs +++ b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs @@ -65,7 +65,7 @@ pack: fnegs fr10,fr10 set_spr_addr ok1,lr set_gr_immed 4,gr20 ; PC increment -bad: fmadds fr16,fr4,fr1 ; unimplemented +bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) test_gr_immed 4,gr15 and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception diff --git a/sim/testsuite/sim/frv/mqlclrhs.cgs b/sim/testsuite/sim/frv/mqlclrhs.cgs new file mode 100644 index 0000000..5e090b0 --- /dev/null +++ b/sim/testsuite/sim/frv/mqlclrhs.cgs @@ -0,0 +1,74 @@ +# frv testcase for mqlclrhs $FRi,$FRj,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqlclrhs +mqlclrhs: + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0x0800,0x0800,fr6 + set_fr_iimmed 0x0800,0x0800,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x1000,0x2000,fr8 + test_fr_limmed 0xe800,0xd800,fr9 + + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0xf800,0xf800,fr6 + set_fr_iimmed 0xf800,0xf800,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0xf000,0xe000,fr8 + test_fr_limmed 0x1800,0x2800,fr9 + + set_fr_iimmed 0x1000,0x1000,fr4 + set_fr_iimmed 0x1000,0x1000,fr5 + set_fr_iimmed 0xf000,0xf800,fr6 + set_fr_iimmed 0x0800,0x1000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0xf000,fr8 + test_fr_limmed 0x1000,0x0000,fr9 + + set_fr_iimmed 0xf000,0xf000,fr4 + set_fr_iimmed 0xf000,0xf000,fr5 + set_fr_iimmed 0xf000,0xf800,fr6 + set_fr_iimmed 0x0800,0x1000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x1000,fr8 + test_fr_limmed 0xf000,0x0000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x8000,0x8000,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x8000,fr8 + test_fr_limmed 0x7fff,0x8000,fr9 + + set_fr_iimmed 0x7fff,0x7fff,fr4 + set_fr_iimmed 0x7fff,0x7fff,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_fr_limmed 0x0000,0x7fff,fr9 + + set_fr_iimmed 0x8001,0x8001,fr4 + set_fr_iimmed 0x8001,0x8001,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x0000,0x0000,fr8 + test_fr_limmed 0x0000,0x8001,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x0001,0xffff,fr5 + set_fr_iimmed 0x0001,0xffff,fr6 + set_fr_iimmed 0x8000,0x8000,fr7 + mqlclrhs fr4,fr6,fr8 + test_fr_limmed 0x8000,0x7fff,fr8 + test_fr_limmed 0x0000,0x0000,fr9 + + pass diff --git a/sim/testsuite/sim/frv/mqlmths.cgs b/sim/testsuite/sim/frv/mqlmths.cgs new file mode 100644 index 0000000..d416d65 --- /dev/null +++ b/sim/testsuite/sim/frv/mqlmths.cgs @@ -0,0 +1,74 @@ +# frv testcase for mqlmths $FRi,$FRj,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqlmths +mqlmths: + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0x0800,0x0800,fr6 + set_fr_iimmed 0x0800,0x0800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x0800,0x0800,fr8 + test_fr_limmed 0xf800,0xf800,fr9 + + set_fr_iimmed 0x1000,0x2000,fr4 + set_fr_iimmed 0xe800,0xd800,fr5 + set_fr_iimmed 0xf800,0xf800,fr6 + set_fr_iimmed 0xf800,0xf800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xf800,0xf800,fr8 + test_fr_limmed 0x0800,0x0800,fr9 + + set_fr_iimmed 0x1000,0x1000,fr4 + set_fr_iimmed 0x1000,0x1000,fr5 + set_fr_iimmed 0xe800,0xf800,fr6 + set_fr_iimmed 0x0800,0x1800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x1000,0xf800,fr8 + test_fr_limmed 0x0800,0x1000,fr9 + + set_fr_iimmed 0xf000,0xf000,fr4 + set_fr_iimmed 0xf000,0xf000,fr5 + set_fr_iimmed 0xe800,0xf800,fr6 + set_fr_iimmed 0x0800,0x1800,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xf000,0x0800,fr8 + test_fr_limmed 0xf800,0xf000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x8000,0x8000,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x7fff,0x8001,fr8 + test_fr_limmed 0x7fff,0x0000,fr9 + + set_fr_iimmed 0x7fff,0x7fff,fr4 + set_fr_iimmed 0x7fff,0x7fff,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x7fff,0x7fff,fr8 + test_fr_limmed 0x8001,0x0000,fr9 + + set_fr_iimmed 0x8001,0x8001,fr4 + set_fr_iimmed 0x8001,0x8001,fr5 + set_fr_iimmed 0x8000,0x7fff,fr6 + set_fr_iimmed 0x8001,0x0000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0x8001,0x8001,fr8 + test_fr_limmed 0x7fff,0x0000,fr9 + + set_fr_iimmed 0x8000,0x8000,fr4 + set_fr_iimmed 0x0001,0xffff,fr5 + set_fr_iimmed 0x0001,0xffff,fr6 + set_fr_iimmed 0x8000,0x8000,fr7 + mqlmths fr4,fr6,fr8 + test_fr_limmed 0xffff,0x0001,fr8 + test_fr_limmed 0x0001,0xffff,fr9 + + pass diff --git a/sim/testsuite/sim/frv/mqsllhi.cgs b/sim/testsuite/sim/frv/mqsllhi.cgs new file mode 100644 index 0000000..21379f2 --- /dev/null +++ b/sim/testsuite/sim/frv/mqsllhi.cgs @@ -0,0 +1,40 @@ +# frv testcase for mqsllhi $FRi,#u6,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqsllhi +mqsllhi: + set_fr_iimmed 0x0001,0x0002,fr4 + set_fr_iimmed 0x0003,0x0004,fr5 + mqsllhi fr4,#1,fr6 + test_fr_limmed 0x0002,0x0004,fr6 + test_fr_limmed 0x0006,0x0008,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsllhi fr4,#1,fr6 + test_fr_limmed 0xfffe,0xfffc,fr6 + test_fr_limmed 0xfff8,0xfff0,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsllhi fr4,#12,fr6 + test_fr_limmed 0xf000,0xe000,fr6 + test_fr_limmed 0xc000,0x8000,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsllhi fr4,#12,fr6 + test_fr_limmed 0x4000,0x8000,fr6 + test_fr_limmed 0xc000,0x0000,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsllhi fr4,#16,fr6 + test_fr_limmed 0x1234,0x5678,fr6 + test_fr_limmed 0x9abc,0xdef0,fr7 + + pass diff --git a/sim/testsuite/sim/frv/mqsrahi.cgs b/sim/testsuite/sim/frv/mqsrahi.cgs new file mode 100644 index 0000000..1d30179 --- /dev/null +++ b/sim/testsuite/sim/frv/mqsrahi.cgs @@ -0,0 +1,40 @@ +# frv testcase for mqsrahi $FRi,#u6,$FRj +# mach: fr450 + + .include "testutils.inc" + + start + + .global mqsrahi +mqsrahi: + set_fr_iimmed 0x0001,0x0002,fr4 + set_fr_iimmed 0x0003,0x0004,fr5 + mqsrahi fr4,#1,fr6 + test_fr_limmed 0x0000,0x0001,fr6 + test_fr_limmed 0x0001,0x0002,fr7 + + set_fr_iimmed 0xffff,0xfffe,fr4 + set_fr_iimmed 0xfffc,0xfff8,fr5 + mqsrahi fr4,#1,fr6 + test_fr_limmed 0xffff,0xffff,fr6 + test_fr_limmed 0xfffe,0xfffc,fr7 + + set_fr_iimmed 0x8000,0xc000,fr4 + set_fr_iimmed 0xe000,0xf000,fr5 + mqsrahi fr4,#12,fr6 + test_fr_limmed 0xfff8,0xfffc,fr6 + test_fr_limmed 0xfffe,0xffff,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsrahi fr4,#12,fr6 + test_fr_limmed 0x0001,0x0005,fr6 + test_fr_limmed 0xfff9,0xfffd,fr7 + + set_fr_iimmed 0x1234,0x5678,fr4 + set_fr_iimmed 0x9abc,0xdef0,fr5 + mqsrahi fr4,#16,fr6 + test_fr_limmed 0x1234,0x5678,fr6 + test_fr_limmed 0x9abc,0xdef0,fr7 + + pass -- cgit v1.1