From 4ce44c668ddc0a909c3f081d98c68bea90a93af9 Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Wed, 17 Nov 1999 02:31:06 +0000 Subject: import gdb-1999-11-16 snapshot --- sim/mips/ChangeLog | 5 +++++ sim/mips/interp.c | 9 +++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'sim/mips') diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index c12ec65..6c8bc4a 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,8 @@ +1999-11-11 Andrew Haley + + * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 + instructions. + Thu Sep 9 15:12:08 1999 Geoffrey Keating * mips.igen (MULT): Correct previous mis-applied patch. diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 68ffd27..9c53ff9 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3124,9 +3124,14 @@ decode_coproc (SIM_DESC sd, CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii) ERET Exception return (VR4100 = 01000010000000000000000000011000) */ - if (((code == 0x00) || (code == 0x04)) && tail == 0) + if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */ + || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */ + && tail == 0) { - /* M[TF]C0 - 32 bit word */ + /* Clear double/single coprocessor move bit. */ + code &= ~1; + + /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */ switch (rd) /* NOTEs: Standard CP0 registers */ { -- cgit v1.1