From 197fa1aa2ca7f943805196c37031b44f7b87d5a7 Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Mon, 23 Nov 2009 04:12:17 +0000 Subject: * cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define. (EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define. (EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype instead of CGEN_INSN_INT. plus, cgen files: Regenerate. --- sim/m32r/ChangeLog | 13 +++++ sim/m32r/cpu.h | 6 +++ sim/m32r/cpu2.h | 6 +++ sim/m32r/cpuall.h | 3 -- sim/m32r/cpux.h | 6 +++ sim/m32r/decode.c | 114 +++++++++++++++++++++---------------------- sim/m32r/decode.h | 2 +- sim/m32r/decode2.c | 138 ++++++++++++++++++++++++++--------------------------- sim/m32r/decode2.h | 2 +- sim/m32r/decodex.c | 138 ++++++++++++++++++++++++++--------------------------- sim/m32r/decodex.h | 2 +- 11 files changed, 229 insertions(+), 201 deletions(-) (limited to 'sim/m32r') diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index 7211f8e..1b28981 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,16 @@ +2009-11-22 Doug Evans + + * cpu.h: Regenerate. + * cpu2.h: Regenerate. + * cpux.h: Regenerate. + * cpuall.h: Regenerate. + * decode.c: Regenerate. + * decode.h: Regenerate. + * decode2.c: Regenerate. + * decode2.h: Regenerate. + * decodex.c: Regenerate. + * decodex.h: Regenerate. + 2009-11-03 Doug Evans * arch.c: Regenerate. diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 7f112d4..b7a684e 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h index 58334e5..6e95104 100644 --- a/sim/m32r/cpu2.h +++ b/sim/m32r/cpu2.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 2 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h index 36e128b..ad6e19a 100644 --- a/sim/m32r/cpuall.h +++ b/sim/m32r/cpuall.h @@ -29,21 +29,18 @@ This file is part of the GNU simulators. #ifdef WANT_CPU_M32RBF #include "eng.h" -#include "cgen-engine.h" #include "cpu.h" #include "decode.h" #endif #ifdef WANT_CPU_M32RXF #include "engx.h" -#include "cgen-engine.h" #include "cpux.h" #include "decodex.h" #endif #ifdef WANT_CPU_M32R2F #include "eng2.h" -#include "cgen-engine.h" #include "cpu2.h" #include "decode2.h" #endif diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h index 784536e..088abd3 100644 --- a/sim/m32r/cpux.h +++ b/sim/m32r/cpux.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 2 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index e94ff36..96ec765 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -216,14 +216,14 @@ m32rbf_init_idesc_table (SIM_CPU *cpu) const IDESC * m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ M32RBF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); @@ -586,7 +586,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -617,7 +617,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -650,7 +650,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -683,7 +683,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_or3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -716,7 +716,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -745,7 +745,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -776,7 +776,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -809,7 +809,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -840,7 +840,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -863,7 +863,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -886,7 +886,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r1; UINT f_r2; @@ -919,7 +919,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqz: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r2; SI f_disp16; @@ -947,7 +947,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -971,7 +971,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -995,7 +995,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1018,7 +1018,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1041,7 +1041,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1071,7 +1071,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r2; INT f_simm16; @@ -1099,7 +1099,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1130,7 +1130,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jl: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1156,7 +1156,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmp: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1181,7 +1181,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1211,7 +1211,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1244,7 +1244,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1274,7 +1274,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1307,7 +1307,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1337,7 +1337,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1370,7 +1370,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_plus: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1401,7 +1401,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld24: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld24.f UINT f_r1; UINT f_uimm24; @@ -1429,7 +1429,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi8: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -1457,7 +1457,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi16: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; INT f_simm16; @@ -1485,7 +1485,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lock: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1515,7 +1515,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_machi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1545,7 +1545,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulhi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1575,7 +1575,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mv: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1605,7 +1605,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfachi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; @@ -1630,7 +1630,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfc: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1658,7 +1658,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtachi: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; @@ -1683,7 +1683,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtc: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1756,7 +1756,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_seth: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; UINT f_hi16; @@ -1784,7 +1784,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll3: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1817,7 +1817,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slli: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_slli.f UINT f_r1; UINT f_uimm5; @@ -1846,7 +1846,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1876,7 +1876,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -1909,7 +1909,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1939,7 +1939,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -1972,7 +1972,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2002,7 +2002,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_d: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2035,7 +2035,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_plus: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2066,7 +2066,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trap: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_trap.f UINT f_uimm4; @@ -2089,7 +2089,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_unlock: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2119,7 +2119,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrpsw: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2136,7 +2136,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setpsw: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2153,7 +2153,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bset: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; @@ -2184,7 +2184,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &m32rbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h index 4930f34..6c5c645 100644 --- a/sim/m32r/decode.h +++ b/sim/m32r/decode.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define M32RBF_DECODE_H extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32rbf_init_idesc_table (SIM_CPU *); extern void m32rbf_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c index 66ffa11..e9fccce 100644 --- a/sim/m32r/decode2.c +++ b/sim/m32r/decode2.c @@ -259,14 +259,14 @@ m32r2f_init_idesc_table (SIM_CPU *cpu) const IDESC * m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ M32R2F_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); @@ -775,7 +775,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -806,7 +806,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -839,7 +839,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -872,7 +872,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_or3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -905,7 +905,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -934,7 +934,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -965,7 +965,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -998,7 +998,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1029,7 +1029,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1052,7 +1052,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1075,7 +1075,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r1; UINT f_r2; @@ -1108,7 +1108,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqz: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r2; SI f_disp16; @@ -1136,7 +1136,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1160,7 +1160,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1184,7 +1184,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1208,7 +1208,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1232,7 +1232,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1255,7 +1255,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1278,7 +1278,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1308,7 +1308,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpi: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r2; INT f_simm16; @@ -1336,7 +1336,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpz: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r2; @@ -1361,7 +1361,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1392,7 +1392,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jc: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1417,7 +1417,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jl: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1443,7 +1443,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmp: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1468,7 +1468,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1498,7 +1498,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1531,7 +1531,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1561,7 +1561,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1594,7 +1594,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1624,7 +1624,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1657,7 +1657,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1688,7 +1688,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld24: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld24.f UINT f_r1; UINT f_uimm24; @@ -1716,7 +1716,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi8: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -1744,7 +1744,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi16: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; INT f_simm16; @@ -1772,7 +1772,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lock: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1802,7 +1802,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_machi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1835,7 +1835,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulhi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1868,7 +1868,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mv: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1898,7 +1898,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfachi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvfachi_a.f UINT f_r1; UINT f_accs; @@ -1926,7 +1926,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfc: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1954,7 +1954,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtachi_a: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvtachi_a.f UINT f_r1; UINT f_accs; @@ -1982,7 +1982,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtc: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2023,7 +2023,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rac_dsi: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_rac_dsi.f UINT f_accd; UINT f_accs; @@ -2065,7 +2065,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_seth: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; UINT f_hi16; @@ -2093,7 +2093,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll3: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -2126,7 +2126,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slli: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_slli.f UINT f_r1; UINT f_uimm5; @@ -2155,7 +2155,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2185,7 +2185,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2218,7 +2218,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2248,7 +2248,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2281,7 +2281,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2311,7 +2311,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_d: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2344,7 +2344,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2375,7 +2375,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2406,7 +2406,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_plus: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2437,7 +2437,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trap: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_trap.f UINT f_uimm4; @@ -2460,7 +2460,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_unlock: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2490,7 +2490,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_satb: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2520,7 +2520,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sat: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2563,7 +2563,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_macwu1: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2593,7 +2593,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_msblo: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2623,7 +2623,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulwu1: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2666,7 +2666,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrpsw: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2683,7 +2683,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setpsw: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2700,7 +2700,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bset: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; @@ -2731,7 +2731,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &m32r2f_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h index a04c469..a681a45 100644 --- a/sim/m32r/decode2.h +++ b/sim/m32r/decode2.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define M32R2F_DECODE_H extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32r2f_init_idesc_table (SIM_CPU *); extern void m32r2f_sem_init_idesc_table (SIM_CPU *); diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c index f1644b9..1b58320 100644 --- a/sim/m32r/decodex.c +++ b/sim/m32r/decodex.c @@ -252,14 +252,14 @@ m32rxf_init_idesc_table (SIM_CPU *cpu) const IDESC * m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, - CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, + CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn, ARGBUF *abuf) { /* Result of decoder. */ M32RXF_INSN_TYPE itype; { - CGEN_INSN_INT insn = base_insn; + CGEN_INSN_WORD insn = base_insn; { unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); @@ -716,7 +716,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -747,7 +747,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_add3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -780,7 +780,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_and3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -813,7 +813,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_or3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_and3.f UINT f_r1; UINT f_r2; @@ -846,7 +846,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addi: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -875,7 +875,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -906,7 +906,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addv3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -939,7 +939,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_addx: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -970,7 +970,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -993,7 +993,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bc24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1016,7 +1016,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beq: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r1; UINT f_r2; @@ -1049,7 +1049,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_beqz: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_beq.f UINT f_r2; SI f_disp16; @@ -1077,7 +1077,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1101,7 +1101,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bl24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1125,7 +1125,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1149,7 +1149,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bcl24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1173,7 +1173,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl8.f SI f_disp8; @@ -1196,7 +1196,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bra24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bl24.f SI f_disp24; @@ -1219,7 +1219,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmp: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -1249,7 +1249,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpi: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r2; INT f_simm16; @@ -1277,7 +1277,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_cmpz: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r2; @@ -1302,7 +1302,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_div: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add.f UINT f_r1; UINT f_r2; @@ -1333,7 +1333,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jc: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1358,7 +1358,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jl: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1384,7 +1384,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_jmp: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_jl.f UINT f_r2; @@ -1409,7 +1409,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1439,7 +1439,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1472,7 +1472,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1502,7 +1502,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldb_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1535,7 +1535,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1565,7 +1565,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldh_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -1598,7 +1598,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1629,7 +1629,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ld24: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld24.f UINT f_r1; UINT f_uimm24; @@ -1657,7 +1657,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi8: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_addi.f UINT f_r1; INT f_simm8; @@ -1685,7 +1685,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_ldi16: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; INT f_simm16; @@ -1713,7 +1713,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_lock: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1743,7 +1743,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_machi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1776,7 +1776,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulhi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_machi_a.f UINT f_r1; UINT f_acc; @@ -1809,7 +1809,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mv: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1839,7 +1839,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfachi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvfachi_a.f UINT f_r1; UINT f_accs; @@ -1867,7 +1867,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvfc: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1895,7 +1895,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtachi_a: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_mvtachi_a.f UINT f_r1; UINT f_accs; @@ -1923,7 +1923,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mvtc: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -1964,7 +1964,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_rac_dsi: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_rac_dsi.f UINT f_accd; UINT f_accs; @@ -2006,7 +2006,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_seth: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_seth.f UINT f_r1; UINT f_hi16; @@ -2034,7 +2034,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sll3: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_add3.f UINT f_r1; UINT f_r2; @@ -2067,7 +2067,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_slli: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_slli.f UINT f_r1; UINT f_uimm5; @@ -2096,7 +2096,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2126,7 +2126,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2159,7 +2159,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2189,7 +2189,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2222,7 +2222,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2252,7 +2252,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_d: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_d.f UINT f_r1; UINT f_r2; @@ -2285,7 +2285,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_st_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2316,7 +2316,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sth_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2347,7 +2347,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_stb_plus: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2378,7 +2378,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_trap: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_trap.f UINT f_uimm4; @@ -2401,7 +2401,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_unlock: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2431,7 +2431,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_satb: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2461,7 +2461,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_sat: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_ld_plus.f UINT f_r1; UINT f_r2; @@ -2504,7 +2504,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_macwu1: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2534,7 +2534,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_msblo: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2564,7 +2564,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_mulwu1: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_st_plus.f UINT f_r1; UINT f_r2; @@ -2607,7 +2607,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_clrpsw: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2624,7 +2624,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_setpsw: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_clrpsw.f UINT f_uimm8; @@ -2641,7 +2641,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_bset: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; @@ -2672,7 +2672,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_btst: { const IDESC *idesc = &m32rxf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; + CGEN_INSN_WORD insn = entire_insn; #define FLD(f) abuf->fields.sfmt_bset.f UINT f_uimm3; UINT f_r2; diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h index e6e2395..89b3cbf 100644 --- a/sim/m32r/decodex.h +++ b/sim/m32r/decodex.h @@ -26,7 +26,7 @@ This file is part of the GNU simulators. #define M32RXF_DECODE_H extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32rxf_init_idesc_table (SIM_CPU *); extern void m32rxf_sem_init_idesc_table (SIM_CPU *); -- cgit v1.1