From b366059a5b384ed822e44a6407b35ab1386b925f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 2 Apr 2015 20:15:43 -0400 Subject: sim: d10v: fix signal updates Way back in aba6488e0b73756f31f154d12a228baa82a68d8a, a bunch of signal defines were changed to TARGET_SIGNAL_xxx. For d10v, the transition was incomplete which lead to sim_stop_reason using the new set but sim_resume still using the old set. Which meant in some cases, the sim would never actually stop. Convert all the remaining SIGxxx defines in here to TARGET_SIGNAL_xxx. This has the nice side effect of fixing the testsuite. --- sim/d10v/interp.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'sim/d10v/interp.c') diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 1aae3e4..7fc0745 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -80,7 +80,7 @@ lookup_hash (uint32 ins, int size) { if (h->next == NULL) { - State.exception = SIGILL; + State.exception = GDB_SIGNAL_ILL; State.pc_changed = 1; /* Don't increment the PC. */ return NULL; } @@ -936,17 +936,14 @@ sim_resume (SIM_DESC sd, int step, int siggnal) { case 0: break; -#ifdef SIGBUS - case SIGBUS: -#endif - case SIGSEGV: + case GDB_SIGNAL_BUS: SET_BPC (PC); SET_BPSW (PSW); SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); JMP (AE_VECTOR_START); SLOT_FLUSH (); break; - case SIGILL: + case GDB_SIGNAL_ILL: SET_BPC (PC); SET_BPSW (PSW); SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); @@ -963,7 +960,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) iaddr = imem_addr ((uint32)PC << 2); if (iaddr == State.mem.fault) { - State.exception = SIGBUS; + State.exception = GDB_SIGNAL_BUS; break; } @@ -1035,7 +1032,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) while ( !State.exception && !stop_simulator); if (step && !State.exception) - State.exception = SIGTRAP; + State.exception = GDB_SIGNAL_TRAP; } void -- cgit v1.1