From 39c1f96aef420f7b82935a370432c054d07b2476 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 29 Sep 2011 03:19:47 +0000 Subject: sim: bfin: use store buffer for VIT_MAX insns The VIT_MAX insns can be used in parallel, so we need to use the store buffer so we don't clobber the output register before we get a chance to do a memory store with it. Reported-by: Kai Iskratsch Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 4 ++++ sim/bfin/bfin-sim.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'sim/bfin') diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 4d246ba..3c4e2c0 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,7 @@ +2011-09-28 Mike Frysinger + + * bfin-sim.c (decode_dsp32shift_0): Use STORE() for VIT_MAX insns. + 2011-07-05 Mike Frysinger * interp.c (sim_do_command): Delete. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index fe4dc26..82410f1 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -5516,7 +5516,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) out = sL; SET_AREG (0, acc0); - SET_DREG (dst0, REG_H_L (DREG (dst0), out)); + STORE (DREG (dst0), REG_H_L (DREG (dst0), out)); } else if ((sop == 2 || sop == 3) && sopcde == 9) { @@ -5553,7 +5553,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) out1 = s1L; SET_AREG (0, acc0); - SET_DREG (dst0, REG_H_L (out1 << 16, out0)); + STORE (DREG (dst0), REG_H_L (out1 << 16, out0)); } else if (sop == 0 && sopcde == 10) { -- cgit v1.1