From fcd1ee07d35e970766622ea09e79a9b80c632cf9 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Sat, 26 Mar 2011 06:02:41 +0000
Subject: sim: bfin: add missing VS set with add/sub insns

The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 sim/bfin/ChangeLog | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'sim/bfin/ChangeLog')

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index eacab65..008edf0 100644
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,7 @@
+2011-03-26  Robin Getz  <robin.getz@analog.com>
+
+	* bfin-sim.c (decode_dsp32alu_0): Set VS when V is set.
+
 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 
 	* dv-bfin_gpio.c (bfin_gpio_port_event): Call HW_TRACE at every
-- 
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