From fd1dc4a0c1b87c1efa7e0398fd47fd1e87fa0fb4 Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Thu, 9 May 2019 10:29:26 +0100 Subject: [binutils][aarch64] New sve_size_tsz_bhs iclass. Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions. This iclass encodes one of three variants by the most significant bit set in a 3-bit value where only one bit may be set. include/ChangeLog: 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_tsz_bhs iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_tsz_bhs iclass decode. --- opcodes/ChangeLog | 7 +++++++ opcodes/aarch64-asm.c | 6 ++++++ opcodes/aarch64-dis.c | 11 +++++++++++ 3 files changed, 24 insertions(+) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b020582..bb823cd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2019-05-09 Matthew Malcomson + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_tsz_bhs iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_tsz_bhs iclass decode. + +2019-05-09 Matthew Malcomson + * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index ad50598..afb0e5b 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1673,6 +1673,12 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) aarch64_get_variant (inst) + 1, 0); break; + case sve_size_tsz_bhs: + insert_fields (&inst->value, + (1 << aarch64_get_variant (inst)), + 0, 2, FLD_SVE_tszl_19, FLD_SVE_sz); + break; + case sve_size_013: variant = aarch64_get_variant (inst); if (variant == 2) diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index b42e4d5..6b53a2c 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2843,6 +2843,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; + case sve_size_tsz_bhs: + i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); + while (i != 1) + { + if (i & 1) + return FALSE; + i >>= 1; + variant += 1; + } + break; + case sve_shift_tsz_hsd: i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); if (i == 0) -- cgit v1.1