From f5f38efc0a20cb50105da4fd2f656cda4561ccc2 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 25 Jun 2024 11:27:23 +0100 Subject: aarch64: Fix sve2p1 dupq instruction operands. This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way 2nd operand does the encoding and decoding using the [] value. dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter) and aarch64_ext_sve_index_imm (extractor) is removed in this patch. This issues was reported here: https://sourceware.org/pipermail/binutils/2024-February/132408.html --- opcodes/aarch64-asm-2.c | 1 - opcodes/aarch64-asm.c | 19 ++----------------- opcodes/aarch64-asm.h | 1 - opcodes/aarch64-dis-2.c | 1 - opcodes/aarch64-dis.c | 36 +++--------------------------------- opcodes/aarch64-dis.h | 1 - opcodes/aarch64-opc-2.c | 4 ++-- opcodes/aarch64-tbl.h | 11 ++++++----- 8 files changed, 13 insertions(+), 61 deletions(-) (limited to 'opcodes') diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 7578093..1838e04 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -959,7 +959,6 @@ aarch64_insert_operand (const aarch64_operand *self, case 238: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); case 240: - return aarch64_ins_sve_index_imm (self, info, code, inst, errors); case 241: return aarch64_ins_sve_index (self, info, code, inst, errors); case 242: diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index e738bb4..0867c08 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1291,23 +1291,8 @@ aarch64_ins_sve_index (const aarch64_operand *self, { unsigned int esize = aarch64_get_qualifier_esize (info->qualifier); insert_field (self->fields[0], code, info->reglane.regno, 0); - insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0, - 2, FLD_imm5, FLD_SVE_tszh); - return true; -} - -/* Encode Zn.[], where is an immediate with range of 0 to one less - than the number of elements in 128 bit, which can encode il:tsz. */ -bool -aarch64_ins_sve_index_imm (const aarch64_operand *self, - const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED, - aarch64_operand_error *errors ATTRIBUTE_UNUSED) -{ - insert_field (self->fields[0], code, info->reglane.regno, 0); - unsigned int esize = aarch64_get_qualifier_esize (info->qualifier); - insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0, - 2, self->fields[1],self->fields[2]); + insert_all_fields_after (self, 1, code, + (info->reglane.index * 2 + 1) * esize); return true; } diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index edeb6d8..88143ee 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -95,7 +95,6 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one); AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two); AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one); AARCH64_DECL_OPD_INSERTER (ins_sve_index); -AARCH64_DECL_OPD_INSERTER (ins_sve_index_imm); AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov); AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index); AARCH64_DECL_OPD_INSERTER (ins_sve_reglist); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index d16a43b..4d1271d 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -34756,7 +34756,6 @@ aarch64_extract_operand (const aarch64_operand *self, case 238: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); case 240: - return aarch64_ext_sve_index_imm (self, info, code, inst, errors); case 241: return aarch64_ext_sve_index (self, info, code, inst, errors); case 242: diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 6098204..d3f38c3 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2237,7 +2237,7 @@ aarch64_ext_sve_index (const aarch64_operand *self, int val; info->reglane.regno = extract_field (self->fields[0], code, 0); - val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5); + val = extract_all_fields_after (self, 1, code); if ((val & 31) == 0) return 0; while ((val & 1) == 0) @@ -2246,26 +2246,6 @@ aarch64_ext_sve_index (const aarch64_operand *self, return true; } -/* Decode Zn.[], where is an immediate with range of 0 to one less - than the number of elements in 128 bit, which can encode il:tsz. */ -bool -aarch64_ext_sve_index_imm (const aarch64_operand *self, - aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED, - aarch64_operand_error *errors ATTRIBUTE_UNUSED) -{ - int val; - - info->reglane.regno = extract_field (self->fields[0], code, 0); - val = extract_fields (code, 0, 2, self->fields[2], self->fields[1]); - if ((val & 15) == 0) - return 0; - while ((val & 1) == 0) - val /= 2; - info->reglane.index = val / 2; - return true; -} - /* Decode a logical immediate for the MOV alias of SVE DUPM. */ bool aarch64_ext_sve_limm_mov (const aarch64_operand *self, @@ -3456,19 +3436,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) break; case sve_index: - i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); - if ((i & 31) == 0) - return false; - while ((i & 1) == 0) - { - i >>= 1; - variant += 1; - } - break; + i = extract_field (FLD_imm5, inst->value, 0); - case sve_index1: - i = extract_fields (inst->value, 0, 2, FLD_SVE_tsz, FLD_SVE_i2h); - if ((i & 15) == 0) + if ((i & 31) == 0) return false; while ((i & 1) == 0) { diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 9e8f7c2..a71524f 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -119,7 +119,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index); -AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index_imm); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 1eb6dc3..c9580b3 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -264,8 +264,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz}, "a 5 bit idexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm5}, "a 5 bit indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 35d9e5c..7270dd1 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6640,7 +6640,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), - SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), + SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1), SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), @@ -7321,11 +7321,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an indexed SVE vector register") \ Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ "an SVE vector register") \ - Y(SVE_REG, sve_index_imm, "SVE_Zn_5_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz), \ - "a 5 bit idexed SVE vector register") \ - Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ + Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_index, "SVE_Zn_5_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_imm5), \ + "a 5 bit indexed SVE vector register") \ Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ "a list of SVE vector registers") \ Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ -- cgit v1.1