From e72cf3ec8eab6e6ca2528279a556c1370c4dd900 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 29 Mar 2007 04:27:54 +0000 Subject: gas/ 2007-03-28 H.J. Lu * config/tc-i386.c (build_modrm_byte): For instructions with 2 register operands, encode destination in i.rm.regmem if its RegMem bit is set. opcodes/ 2007-03-28 H.J. Lu * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and movq. Remove InvMem from sldt, smsw and str. * i386-opc.h (InvMem): Renamed to ... (RegMem): Update comments. (AnyMem): Remove InvMem. --- opcodes/ChangeLog | 12 ++++++++++-- opcodes/i386-opc.c | 26 +++++++++++++------------- opcodes/i386-opc.h | 14 +++++++------- 3 files changed, 30 insertions(+), 22 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7c4592c..6387349 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,14 @@ +2007-03-28 H.J. Lu + + * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and + movq. Remove InvMem from sldt, smsw and str. + + * i386-opc.h (InvMem): Renamed to ... + (RegMem): Update comments. + (AnyMem): Remove InvMem. + 2007-03-27 Paul Brook - opcodes/ * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??). 2007-03-24 Paul Brook @@ -9,7 +17,7 @@ (print_insn_coprocessor): Handle %x. 2007-03-24 Paul Brook - Mark Shinwell + Mark Shinwell * arm-dis.c (arm_opcodes): Print SRS base register. diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c index be12dce..9314f6a 100644 --- a/opcodes/i386-opc.c +++ b/opcodes/i386-opc.c @@ -63,9 +63,9 @@ const template i386_optab[] = size prefix. When moving to a 32 bit register, the upper 16 bits are set to an implementation defined value (on the Pentium Pro, the implementation defined value is zero). */ -{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } }, +{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|RegMem, 0 } }, { "mov", 2, 0x8c, X, 0, w_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } }, +{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|RegMem, 0 } }, { "mov", 2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } }, { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg2, 0 } }, { "mov", 2, 0x8e, X, 0, w_Suf|Modrm|IgnoreSize, { WordMem, SReg2, 0 } }, @@ -73,11 +73,11 @@ const template i386_optab[] = { "mov", 2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize, { WordMem, SReg3, 0 } }, /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit mode they are 64bit.*/ -{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|RegMem, 0} }, +{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|RegMem, 0} }, +{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|RegMem, 0} }, +{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|RegMem, 0} }, +{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|RegMem, 0} }, { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, @@ -537,11 +537,11 @@ const template i386_optab[] = {"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg, 0, 0} }, {"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg, 0, 0} }, {"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg, 0, 0} }, {"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, @@ -987,12 +987,12 @@ const template i386_optab[] = {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, /* The segment register moves accept Reg64 so that a segment register can be copied to a 64 bit register, and vice versa. */ -{"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|InvMem, 0 } }, +{"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|RegMem, 0 } }, {"movq", 2, 0x8e, X, Cpu64, NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } }, /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit mode they are 64bit.*/ -{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, -{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, +{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|RegMem, 0} }, +{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|RegMem, 0} }, /* Real MMX instructions. */ {"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, {"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 83211dd..39ebfbc 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -166,12 +166,12 @@ typedef struct template #define RegXMM 0x20000000 /* XMM registers in PIII */ #define EsSeg 0x40000000 /* String insn operand with fixed es segment */ - /* InvMem is for instructions with a modrm byte that only allow a - general register encoding in the i.tm.mode and i.tm.regmem fields, - eg. control reg moves. They really ought to support a memory form, - but don't, so we add an InvMem flag to the register operand to - indicate that it should be encoded in the i.tm.regmem field. */ -#define InvMem 0x80000000 + /* RegMem is for instructions with a modrm byte where the register + destination operand should be encoded in the mod and regmem fields. + Normally, it will be encoded in the reg field. We add a RegMem + flag to the destination register operand to indicate that it should + be encoded in the regmem field. */ +#define RegMem 0x80000000 #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ #define WordReg (Reg16|Reg32|Reg64) @@ -179,7 +179,7 @@ typedef struct template #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ -#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ +#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */ /* The following aliases are defined because the opcode table carefully specifies the allowed memory types for each instruction. At the moment we can only tell a memory reference size by the -- cgit v1.1