From e4bdd679556e4e4ba71bcd066cc98ee7c2f4fca2 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@suse.de>
Date: Wed, 5 Jul 2017 11:27:49 +0200
Subject: X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases
 correctly

The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.

Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:

  #include <stdio.h>

  int main(void)
  {
          int a = 2;

          printf ("a before: %d\n", a);

          asm volatile(".byte 0xd0,0xf0"          /* SHL %al */
                       : "+a" (a));

          printf("a after : %d\n", a);

          return 0;
  }

  $ ./a.out
  a before: 2
  a after : 4
---
 opcodes/ChangeLog  |  4 ++++
 opcodes/i386-dis.c | 12 ++++++------
 2 files changed, 10 insertions(+), 6 deletions(-)

(limited to 'opcodes')

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6c18442..a076189 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-07-05  Borislav Petkov  <bp@suse.de>
+
+	* i386-dis.c: Enable ModRM.reg /6 aliases.
+
 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 
         * opcodes/arm-dis.c: Support MVFR2 in disassembly
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 612e06f..e95311e 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3441,7 +3441,7 @@ static const struct dis386 reg_table[][8] = {
     { "rcrA",	{ Eb, Ib }, 0 },
     { "shlA",	{ Eb, Ib }, 0 },
     { "shrA",	{ Eb, Ib }, 0 },
-    { Bad_Opcode },
+    { "shlA",	{ Eb, Ib }, 0 },
     { "sarA",	{ Eb, Ib }, 0 },
   },
   /* REG_C1 */
@@ -3452,7 +3452,7 @@ static const struct dis386 reg_table[][8] = {
     { "rcrQ",	{ Ev, Ib }, 0 },
     { "shlQ",	{ Ev, Ib }, 0 },
     { "shrQ",	{ Ev, Ib }, 0 },
-    { Bad_Opcode },
+    { "shlQ",	{ Ev, Ib }, 0 },
     { "sarQ",	{ Ev, Ib }, 0 },
   },
   /* REG_C6 */
@@ -3485,7 +3485,7 @@ static const struct dis386 reg_table[][8] = {
     { "rcrA",	{ Eb, I1 }, 0 },
     { "shlA",	{ Eb, I1 }, 0 },
     { "shrA",	{ Eb, I1 }, 0 },
-    { Bad_Opcode },
+    { "shlA",	{ Eb, I1 }, 0 },
     { "sarA",	{ Eb, I1 }, 0 },
   },
   /* REG_D1 */
@@ -3496,7 +3496,7 @@ static const struct dis386 reg_table[][8] = {
     { "rcrQ",	{ Ev, I1 }, 0 },
     { "shlQ",	{ Ev, I1 }, 0 },
     { "shrQ",	{ Ev, I1 }, 0 },
-    { Bad_Opcode },
+    { "shlQ",	{ Ev, I1 }, 0 },
     { "sarQ",	{ Ev, I1 }, 0 },
   },
   /* REG_D2 */
@@ -3507,7 +3507,7 @@ static const struct dis386 reg_table[][8] = {
     { "rcrA",	{ Eb, CL }, 0 },
     { "shlA",	{ Eb, CL }, 0 },
     { "shrA",	{ Eb, CL }, 0 },
-    { Bad_Opcode },
+    { "shlA",	{ Eb, CL }, 0 },
     { "sarA",	{ Eb, CL }, 0 },
   },
   /* REG_D3 */
@@ -3518,7 +3518,7 @@ static const struct dis386 reg_table[][8] = {
     { "rcrQ",	{ Ev, CL }, 0 },
     { "shlQ",	{ Ev, CL }, 0 },
     { "shrQ",	{ Ev, CL }, 0 },
-    { Bad_Opcode },
+    { "shlQ",	{ Ev, CL }, 0 },
     { "sarQ",	{ Ev, CL }, 0 },
   },
   /* REG_F6 */
-- 
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