From e269fea784da752b49b5fc406ee7ea8403955a28 Mon Sep 17 00:00:00 2001 From: Andrew Bennett Date: Mon, 16 Dec 2013 07:19:34 -0800 Subject: Range of element index is too large on MIPS MSA element selection instructions. The element index range for the following MIPS MSA instructions: sldi, splati, copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue. ChangeLog: gas/testsuite/gas/mips/ * msa.s: Reduced maximum element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. * msa64.s: Likewise. * micromips@msa.d: Likewise. * micromips@msa64.d: Likewise. * msa.d: Likewise. * msa64.d: Likewise. include/opcode/ * mips.h: Updated description of +o, +u, +v and +w for MIPS and microMIPS. opcodes/ * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, +v and +w. (micromips_opcodes): Reduced element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u, +v and +w. (mips_builtin_opcodes): Reduced element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. --- opcodes/ChangeLog | 11 ++++++++++ opcodes/micromips-opc.c | 56 ++++++++++++++++++++++++------------------------- opcodes/mips-opc.c | 56 ++++++++++++++++++++++++------------------------- 3 files changed, 67 insertions(+), 56 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 955ace37..9c88d3f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2013-12-16 Andrew Bennett + + * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, + +v and +w. + (micromips_opcodes): Reduced element index range for sldi, splati, + copy_s, copy_u, insert and insve instructions. + * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u, + +v and +w. + (mips_builtin_opcodes): Reduced element index range for sldi, splati, + copy_s, copy_u, insert and insve instructions. + 2013-12-13 Jan-Benedict Glaw * nds32-dis.c (mnemonic_96): Fix typo. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index a68916a..f03aa0a 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -120,10 +120,10 @@ decode_micromips_operand (const char *p) case 'k': REG (5, 6, GP); case 'l': REG (5, 6, MSA_CTRL); case 'n': REG (5, 11, MSA_CTRL); - case 'o': SPECIAL (5, 16, IMM_INDEX); - case 'u': SPECIAL (4, 16, IMM_INDEX); - case 'v': SPECIAL (3, 16, IMM_INDEX); - case 'w': SPECIAL (2, 16, IMM_INDEX); + case 'o': SPECIAL (4, 16, IMM_INDEX); + case 'u': SPECIAL (3, 16, IMM_INDEX); + case 'v': SPECIAL (2, 16, IMM_INDEX); + case 'w': SPECIAL (1, 16, IMM_INDEX); case 'x': BIT (5, 16, 0); /* (0 .. 31) */ case '~': BIT (2, 6, 1); /* (1 .. 4) */ @@ -1601,18 +1601,18 @@ const struct mips_opcode micromips_opcodes[] = {"sld.h", "+d,+e+*", 0x5820000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"sld.w", "+d,+e+*", 0x5840000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"sld.d", "+d,+e+*", 0x5860000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sldi.b", "+d,+e+o", 0x58000016, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.h", "+d,+e+u", 0x58200016, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.w", "+d,+e+v", 0x58300016, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.d", "+d,+e+w", 0x58380016, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.b", "+d,+e+o", 0x58000016, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.h", "+d,+e+u", 0x58200016, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.w", "+d,+e+v", 0x58300016, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.d", "+d,+e+w", 0x58380016, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, {"splat.b", "+d,+e+*", 0x5880000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"splat.h", "+d,+e+*", 0x58a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"splat.w", "+d,+e+*", 0x58c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"splat.d", "+d,+e+*", 0x58e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splati.b", "+d,+e+o", 0x58400016, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.h", "+d,+e+u", 0x58600016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.w", "+d,+e+v", 0x58700016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.d", "+d,+e+w", 0x58780016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.b", "+d,+e+o", 0x58400016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.h", "+d,+e+u", 0x58600016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.w", "+d,+e+v", 0x58700016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.d", "+d,+e+w", 0x58780016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"pckev.b", "+d,+e,+h", 0x5900000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"pckev.h", "+d,+e,+h", 0x5920000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"pckev.w", "+d,+e,+h", 0x5940000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, @@ -1704,22 +1704,22 @@ const struct mips_opcode micromips_opcodes[] = {"nlzc.h", "+d,+e", 0x5b0d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"nlzc.w", "+d,+e", 0x5b0e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"nlzc.d", "+d,+e", 0x5b0f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.b", "+k,+e+o", 0x58800016, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.h", "+k,+e+u", 0x58a00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.w", "+k,+e+v", 0x58b00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.d", "+k,+e+w", 0x58b80016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"copy_u.b", "+k,+e+o", 0x58c00016, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.h", "+k,+e+u", 0x58e00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.w", "+k,+e+v", 0x58f00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.d", "+k,+e+w", 0x58f80016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"insert.b", "+d+o,d", 0x59000016, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.h", "+d+u,d", 0x59200016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.w", "+d+v,d", 0x59300016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.d", "+d+w,d", 0x59380016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, -{"insve.b", "+d+o,+e+&", 0x59400016, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.h", "+d+u,+e+&", 0x59600016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.w", "+d+v,+e+&", 0x59700016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.d", "+d+w,+e+&", 0x59780016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"copy_s.b", "+k,+e+o", 0x58800016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.h", "+k,+e+u", 0x58a00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.w", "+k,+e+v", 0x58b00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.d", "+k,+e+w", 0x58b80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"copy_u.b", "+k,+e+o", 0x58c00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.h", "+k,+e+u", 0x58e00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.w", "+k,+e+v", 0x58f00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.d", "+k,+e+w", 0x58f80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"insert.b", "+d+o,d", 0x59000016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.h", "+d+u,d", 0x59200016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.w", "+d+v,d", 0x59300016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.d", "+d+w,d", 0x59380016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, +{"insve.b", "+d+o,+e+&", 0x59400016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.h", "+d+u,+e+&", 0x59600016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.w", "+d+v,+e+&", 0x59700016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.d", "+d+w,+e+&", 0x59780016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, {"bnz.b", "+h,p", 0x83800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, {"bnz.h", "+h,p", 0x83a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, {"bnz.w", "+h,p", 0x83c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index cd43185..fd619f4 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -92,15 +92,15 @@ decode_mips_operand (const char *p) case 'l': REG (5, 6, MSA_CTRL); case 'm': REG (0, 0, R5900_ACC); case 'n': REG (5, 11, MSA_CTRL); - case 'o': SPECIAL (5, 16, IMM_INDEX); + case 'o': SPECIAL (4, 16, IMM_INDEX); case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */ case 'q': REG (0, 0, R5900_Q); case 'r': REG (0, 0, R5900_R); case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */ case 't': REG (5, 16, COPRO); - case 'u': SPECIAL (4, 16, IMM_INDEX); - case 'v': SPECIAL (3, 16, IMM_INDEX); - case 'w': SPECIAL (2, 16, IMM_INDEX); + case 'u': SPECIAL (3, 16, IMM_INDEX); + case 'v': SPECIAL (2, 16, IMM_INDEX); + case 'w': SPECIAL (1, 16, IMM_INDEX); case 'x': BIT (5, 16, 0); /* (0 .. 31) */ case 'y': REG (0, 0, R5900_I); case 'z': REG (5, 0, GP); @@ -2853,18 +2853,18 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sld.h", "+d,+e+*", 0x78200014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"sld.w", "+d,+e+*", 0x78400014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"sld.d", "+d,+e+*", 0x78600014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"sldi.b", "+d,+e+o", 0x78000019, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.h", "+d,+e+u", 0x78200019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.w", "+d,+e+v", 0x78300019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, -{"sldi.d", "+d,+e+w", 0x78380019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, {"splat.b", "+d,+e+*", 0x78800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"splat.h", "+d,+e+*", 0x78a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"splat.w", "+d,+e+*", 0x78c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"splat.d", "+d,+e+*", 0x78e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, -{"splati.b", "+d,+e+o", 0x78400019, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.h", "+d,+e+u", 0x78600019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.w", "+d,+e+v", 0x78700019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"splati.d", "+d,+e+w", 0x78780019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.b", "+d,+e+o", 0x78400019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.h", "+d,+e+u", 0x78600019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.w", "+d,+e+v", 0x78700019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.d", "+d,+e+w", 0x78780019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"pckev.b", "+d,+e,+h", 0x79000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"pckev.h", "+d,+e,+h", 0x79200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, {"pckev.w", "+d,+e,+h", 0x79400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, @@ -2956,22 +2956,22 @@ const struct mips_opcode mips_builtin_opcodes[] = {"nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, {"nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.b", "+k,+e+o", 0x78800019, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.h", "+k,+e+u", 0x78a00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.w", "+k,+e+v", 0x78b00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_s.d", "+k,+e+w", 0x78b80019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"copy_u.b", "+k,+e+o", 0x78c00019, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.h", "+k,+e+u", 0x78e00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, -{"copy_u.d", "+k,+e+w", 0x78f80019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 }, -{"insert.b", "+d+o,d", 0x79000019, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.h", "+d+u,d", 0x79200019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.w", "+d+v,d", 0x79300019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insert.d", "+d+w,d", 0x79380019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, -{"insve.b", "+d+o,+e+&", 0x79400019, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.h", "+d+u,+e+&", 0x79600019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.w", "+d+v,+e+&", 0x79700019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, -{"insve.d", "+d+w,+e+&", 0x79780019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"copy_s.b", "+k,+e+o", 0x78800019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.h", "+k,+e+u", 0x78a00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.w", "+k,+e+v", 0x78b00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.d", "+k,+e+w", 0x78b80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"copy_u.b", "+k,+e+o", 0x78c00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.h", "+k,+e+u", 0x78e00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.d", "+k,+e+w", 0x78f80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"insert.b", "+d+o,d", 0x79000019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.h", "+d+u,d", 0x79200019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.w", "+d+v,d", 0x79300019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.d", "+d+w,d", 0x79380019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, +{"insve.b", "+d+o,+e+&", 0x79400019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.h", "+d+u,+e+&", 0x79600019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.w", "+d+v,+e+&", 0x79700019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.d", "+d+w,+e+&", 0x79780019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, {"bnz.b", "+h,p", 0x47800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, {"bnz.h", "+h,p", 0x47a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, {"bnz.w", "+h,p", 0x47c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, -- cgit v1.1