From b009f915c9e744b1671f72806c5714af00a8ee89 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 30 Nov 2021 17:50:24 +0000 Subject: aarch64: Allow writes to MFAR_EL3 MFAR_EL3 is a read/write register, but was incorrectly marked as read-only [https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/MFAR-EL3--PA-Fault-Address-Register?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Mark mfar_el3 as read-write. gas/ * testsuite/gas/aarch64/rme.s: Test writing to mfar_el3. * testsuite/gas/aarch64/rme.d: Update accordingly. * testsuite/gas/aarch64/rme-invalid.s: Delete. * testsuite/gas/aarch64/rme-invalid.l: Likewise. * testsuite/gas/aarch64/rme-invalid.d: Likewise. --- opcodes/aarch64-opc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'opcodes') diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 372101a..34b141e 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4833,7 +4833,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0), - SR_CORE ("mfar_el3", CPENC (3,6,C6,C0,5), F_REG_READ), + SR_CORE ("mfar_el3", CPENC (3,6,C6,C0,5), 0), SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0), SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0), -- cgit v1.1