From 718aefcf55cc5a9de3f73d9a37259f8f792b1cef Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Thu, 2 Sep 2021 12:16:10 +0100 Subject: Fix the V850 assembler's generation of relocations for the st.b instruction. PR 28292 gas * config/tc-v850.c (handle_lo16): Also accept BFD_RELOC_V850_LO16_SPLIT_OFFSET. * testsuite/gas/v850/split-lo16.s: Add extra line. * testsuite/gas/v850/split-lo16.d: Update expected disassembly. opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place of BFD_RELOC_16. --- opcodes/ChangeLog | 6 ++++++ opcodes/v850-opc.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d0bfa80..ca3206d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2021-09-02 Nick Clifton + + PR 28292 + * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place + of BFD_RELOC_16. + 2021-08-17 Shahab Vahedi * arc-regs.h (DEF): Fix the register numbers. diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index 24720b3..852fe61 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -1190,7 +1190,7 @@ const struct v850_operand v850_operands[] = /* The disp16 field in a format 8 insn. */ #define D16 (I16U + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 }, + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_LO16_SPLIT_OFFSET }, /* The disp16 field in an format 7 unsigned byte load insn. */ #define D16_16 (D16 + 1) -- cgit v1.1