From 3e8b13bf7745cde3a0bb027041df7cad4b29b510 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Thu, 16 Mar 2023 11:52:09 +1030 Subject: cpu/mem.opc whitespace tidy cpu/ * mep.opc: Whitespace and formatting. opcodes/ * mep-asm.c: Regenerate. * mep-dis.c: Regenerate. --- opcodes/mep-asm.c | 9 ++++----- opcodes/mep-dis.c | 38 +++++++++++++++++++------------------- 2 files changed, 23 insertions(+), 24 deletions(-) (limited to 'opcodes') diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c index 219c448..f3c5f79 100644 --- a/opcodes/mep-asm.c +++ b/opcodes/mep-asm.c @@ -638,10 +638,10 @@ expand_macro (arg *args, int narg, const macro *mac) /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ while (*e) { - if (*e == '`' && - (*e+1) && - ((*(e + 1) - '1') <= MAXARGS) && - ((*(e + 1) - '1') <= narg)) + if (*e == '`' + && (*e+1) + && ((*(e + 1) - '1') <= MAXARGS) + && ((*(e + 1) - '1') <= narg)) { result = str_append (result, mark, e - mark); mac_arg = (*(e + 1) - '1'); @@ -759,7 +759,6 @@ expand_string (const char *in, int first_only) if (narg > -1) args[narg].len++; } - } ++in; } diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c index 72c6c10..91ea29b 100644 --- a/opcodes/mep-dis.c +++ b/opcodes/mep-dis.c @@ -154,8 +154,8 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, } status += my_status; - /* Print the + to indicate that the following copro insn is */ - /* part of a vliw group. */ + /* Print the + to indicate that the following copro insn is + part of a vliw group. */ if (copro1length > 0) (*info->fprintf_func) (info->stream, " + "); } @@ -336,16 +336,16 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) { - /* We have a 32 bit copro insn. */ - corebuflength = 0; + /* We have a 32 bit copro insn. */ + corebuflength = 0; /* All 4 4ytes are one copro insn. */ - cop1buflength = 4; + cop1buflength = 4; } else { - /* We have a 32 bit core. */ - corebuflength = 4; - cop1buflength = 0; + /* We have a 32 bit core. */ + corebuflength = 4; + cop1buflength = 0; } } else @@ -425,16 +425,16 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) { - /* We have a 64 bit copro insn. */ - corebuflength = 0; + /* We have a 64 bit copro insn. */ + corebuflength = 0; /* All 8 bytes are one copro insn. */ - cop1buflength = 8; + cop1buflength = 8; } else { - /* We have a 32 bit core insn and a 32 bit copro insn. */ - corebuflength = 4; - cop1buflength = 4; + /* We have a 32 bit core insn and a 32 bit copro insn. */ + corebuflength = 4; + cop1buflength = 4; } } else @@ -486,10 +486,10 @@ print_slot_insn (CGEN_CPU_DESC cd, if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) - { - insn_list = CGEN_DIS_NEXT_INSN (insn_list); + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); continue; - } + } if ((insn_value & CGEN_INSN_BASE_MASK (insn)) == CGEN_INSN_BASE_VALUE (insn)) @@ -656,13 +656,13 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) for (i = 0; i <= mep_config_index; i++) if (mep_config_map[i].name == NULL) break; - + if (i < mep_config_index) { opcodes_error_handler (_("illegal MEP INDEX setting '%x' in ELF header e_flags field"), mep_config_index); mep_config_index = 0; } - + cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; if (cop_type == EF_MEP_COP_IVC2) ivc2 = 1; -- cgit v1.1