From 369c9167d47e69aad2e260cc1db17f8c894c138b Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Fri, 29 Jun 2018 12:12:27 +0100 Subject: Fix AArch64 encodings for by element instructions. Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16. --- opcodes/ChangeLog | 14 +++++ opcodes/aarch64-asm-2.c | 137 ++++++++++++++++++++++++----------------------- opcodes/aarch64-dis-2.c | 139 ++++++++++++++++++++++++------------------------ opcodes/aarch64-dis.c | 19 +++++-- opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 3 +- opcodes/aarch64-tbl.h | 46 ++++++++-------- 7 files changed, 194 insertions(+), 165 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 01af9b0..c2d979a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2018-06-29 Tamar Christina + + PR binutils/23192 + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. + * aarch64-opc.c (operand_general_constraint_met_p, + aarch64_print_operand): Likewise. + * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, + smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, + fmlal2, fmlsl2. + (AARCH64_OPERANDS): Add Em2. + 2018-06-26 Nick Clifton * po/uk.po: Updated Ukranian translation. diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 45b0085..b0320db 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -614,7 +614,6 @@ aarch64_insert_operand (const aarch64_operand *self, case 27: case 28: case 29: - case 152: case 153: case 154: case 155: @@ -624,7 +623,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 159: case 160: case 161: - case 174: + case 162: case 175: case 176: case 177: @@ -633,8 +632,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 180: case 181: case 182: - case 186: - case 189: + case 183: + case 187: + case 190: return aarch64_ins_regno (self, info, code, inst, errors); case 13: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -645,21 +645,21 @@ aarch64_insert_operand (const aarch64_operand *self, case 30: case 31: case 32: - case 191: - return aarch64_ins_reglane (self, info, code, inst, errors); case 33: - return aarch64_ins_reglist (self, info, code, inst, errors); + case 192: + return aarch64_ins_reglane (self, info, code, inst, errors); case 34: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 35: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 36: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 37: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 38: case 39: case 40: - case 50: + case 41: case 51: case 52: case 53: @@ -673,13 +673,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 61: case 62: case 63: - case 75: + case 64: case 76: case 77: case 78: - case 149: - case 151: - case 166: + case 79: + case 150: + case 152: case 167: case 168: case 169: @@ -687,86 +687,86 @@ aarch64_insert_operand (const aarch64_operand *self, case 171: case 172: case 173: + case 174: return aarch64_ins_imm (self, info, code, inst, errors); - case 41: case 42: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 43: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 44: case 45: + case 46: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); - case 49: - case 140: + case 50: + case 141: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 64: - case 147: - return aarch64_ins_limm (self, info, code, inst, errors); case 65: - return aarch64_ins_aimm (self, info, code, inst, errors); + case 148: + return aarch64_ins_limm (self, info, code, inst, errors); case 66: - return aarch64_ins_imm_half (self, info, code, inst, errors); + return aarch64_ins_aimm (self, info, code, inst, errors); case 67: + return aarch64_ins_imm_half (self, info, code, inst, errors); + case 68: return aarch64_ins_fbits (self, info, code, inst, errors); - case 69: case 70: - case 145: - return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 71: - case 144: - return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + case 146: + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 72: + case 145: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 73: + case 74: return aarch64_ins_cond (self, info, code, inst, errors); - case 79: - case 86: - return aarch64_ins_addr_simple (self, info, code, inst, errors); case 80: - return aarch64_ins_addr_regoff (self, info, code, inst, errors); + case 87: + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 81: + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 82: case 83: - return aarch64_ins_addr_simm (self, info, code, inst, errors); case 84: - return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + return aarch64_ins_addr_simm (self, info, code, inst, errors); case 85: + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + case 86: return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 87: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 88: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 89: - return aarch64_ins_sysreg (self, info, code, inst, errors); + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 90: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 91: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 92: case 93: case 94: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 95: + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 96: - return aarch64_ins_barrier (self, info, code, inst, errors); case 97: - return aarch64_ins_prfop (self, info, code, inst, errors); + return aarch64_ins_barrier (self, info, code, inst, errors); case 98: - return aarch64_ins_hint (self, info, code, inst, errors); + return aarch64_ins_prfop (self, info, code, inst, errors); case 99: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); + return aarch64_ins_hint (self, info, code, inst, errors); case 100: + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 101: case 102: case 103: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 104: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 105: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 106: + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 107: case 108: case 109: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 110: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 111: case 112: case 113: @@ -779,8 +779,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 120: case 121: case 122: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 123: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 124: case 125: case 126: @@ -788,48 +788,49 @@ aarch64_insert_operand (const aarch64_operand *self, case 128: case 129: case 130: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 131: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 132: case 133: case 134: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 135: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 136: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 137: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 138: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 139: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 140: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 141: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 142: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 143: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + case 144: return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); - case 146: + case 147: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 148: + case 149: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 150: + case 151: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 162: case 163: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 164: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 165: + case 166: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 183: case 184: case 185: + case 186: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 187: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 188: - case 190: + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 189: + case 191: return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 5218297..a39ad9d 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -19742,7 +19742,6 @@ aarch64_extract_operand (const aarch64_operand *self, case 27: case 28: case 29: - case 152: case 153: case 154: case 155: @@ -19752,7 +19751,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 159: case 160: case 161: - case 174: + case 162: case 175: case 176: case 177: @@ -19761,8 +19760,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 180: case 181: case 182: - case 186: - case 189: + case 183: + case 187: + case 190: return aarch64_ext_regno (self, info, code, inst, errors); case 8: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -19777,21 +19777,21 @@ aarch64_extract_operand (const aarch64_operand *self, case 30: case 31: case 32: - case 191: - return aarch64_ext_reglane (self, info, code, inst, errors); case 33: - return aarch64_ext_reglist (self, info, code, inst, errors); + case 192: + return aarch64_ext_reglane (self, info, code, inst, errors); case 34: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 35: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 36: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 37: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 38: case 39: case 40: - case 50: + case 41: case 51: case 52: case 53: @@ -19805,14 +19805,14 @@ aarch64_extract_operand (const aarch64_operand *self, case 61: case 62: case 63: - case 74: + case 64: case 75: case 76: case 77: case 78: - case 149: - case 151: - case 166: + case 79: + case 150: + case 152: case 167: case 168: case 169: @@ -19820,88 +19820,88 @@ aarch64_extract_operand (const aarch64_operand *self, case 171: case 172: case 173: + case 174: return aarch64_ext_imm (self, info, code, inst, errors); - case 41: case 42: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 43: + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 44: case 45: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 46: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 47: return aarch64_ext_shll_imm (self, info, code, inst, errors); - case 49: - case 140: + case 50: + case 141: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 64: - case 147: - return aarch64_ext_limm (self, info, code, inst, errors); case 65: - return aarch64_ext_aimm (self, info, code, inst, errors); + case 148: + return aarch64_ext_limm (self, info, code, inst, errors); case 66: - return aarch64_ext_imm_half (self, info, code, inst, errors); + return aarch64_ext_aimm (self, info, code, inst, errors); case 67: + return aarch64_ext_imm_half (self, info, code, inst, errors); + case 68: return aarch64_ext_fbits (self, info, code, inst, errors); - case 69: case 70: - case 145: - return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 71: - case 144: - return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + case 146: + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 72: + case 145: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 73: + case 74: return aarch64_ext_cond (self, info, code, inst, errors); - case 79: - case 86: - return aarch64_ext_addr_simple (self, info, code, inst, errors); case 80: - return aarch64_ext_addr_regoff (self, info, code, inst, errors); + case 87: + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 81: + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 82: case 83: - return aarch64_ext_addr_simm (self, info, code, inst, errors); case 84: - return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + return aarch64_ext_addr_simm (self, info, code, inst, errors); case 85: + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + case 86: return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 87: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 88: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 89: - return aarch64_ext_sysreg (self, info, code, inst, errors); + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 90: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 91: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 92: case 93: case 94: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 95: + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 96: - return aarch64_ext_barrier (self, info, code, inst, errors); case 97: - return aarch64_ext_prfop (self, info, code, inst, errors); + return aarch64_ext_barrier (self, info, code, inst, errors); case 98: - return aarch64_ext_hint (self, info, code, inst, errors); + return aarch64_ext_prfop (self, info, code, inst, errors); case 99: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); + return aarch64_ext_hint (self, info, code, inst, errors); case 100: + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 101: case 102: case 103: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 104: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 105: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 106: + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 107: case 108: case 109: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 110: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 111: case 112: case 113: @@ -19914,8 +19914,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 120: case 121: case 122: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 123: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 124: case 125: case 126: @@ -19923,48 +19923,49 @@ aarch64_extract_operand (const aarch64_operand *self, case 128: case 129: case 130: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 131: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 132: case 133: case 134: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 135: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 136: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 137: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 138: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 139: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 140: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 141: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 142: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 143: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + case 144: return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); - case 146: + case 147: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 148: + case 149: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 150: + case 151: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 162: case 163: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 164: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 165: + case 166: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 183: case 184: case 185: + case 186: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 187: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 188: - case 190: + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 189: + case 191: return aarch64_ext_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index b9c1559..f7092b06 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -372,10 +372,18 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, switch (info->qualifier) { case AARCH64_OPND_QLF_S_H: - /* h:l:m */ - info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, - FLD_M); - info->reglane.regno &= 0xf; + if (info->type == AARCH64_OPND_Em16) + { + /* h:l:m */ + info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, + FLD_M); + info->reglane.regno &= 0xf; + } + else + { + /* h:l */ + info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); + } break; case AARCH64_OPND_QLF_S_S: /* h:l */ @@ -389,7 +397,8 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, return FALSE; } - if (inst->opcode->op == OP_FCMLA_ELEM) + if (inst->opcode->op == OP_FCMLA_ELEM + && info->qualifier != AARCH64_OPND_QLF_S_H) { /* Complex operand takes two elements. */ if (info->reglane.index & 1) diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 0e4d9f8..e2ab45e 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -57,6 +57,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 365cf15..2a10f00 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2516,7 +2516,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, 01 0:Rm 10 M:Rm 11 RESERVED */ - if (type == AARCH64_OPND_Em && qualifier == AARCH64_OPND_QLF_S_H + if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H && !value_in_range_p (opnd->reglane.regno, 0, 15)) { set_regno_out_of_range_error (mismatch_detail, idx, 0, 15); @@ -3161,6 +3161,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_Ed: case AARCH64_OPND_En: case AARCH64_OPND_Em: + case AARCH64_OPND_Em16: case AARCH64_OPND_SM3_IMM2: snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno, aarch64_get_qualifier_name (opnd->qualifier), diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 08eec60..c720fea 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2340,8 +2340,8 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), /* AdvSIMD vector x indexed element. */ - SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), @@ -2356,11 +2356,11 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), + SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), @@ -2370,9 +2370,9 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), - SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), - RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), - RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), + SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), + RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), + RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ), /* AdvSIMD EXT. */ SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), @@ -2680,15 +2680,15 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), - SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), + SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), - SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), + SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), - SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), + SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), - SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), - RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), - RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), + SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), + RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), + RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), /* AdvSIMD load/store multiple structures. */ SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), @@ -4361,15 +4361,15 @@ struct aarch64_opcode aarch64_opcode_table[] = FP16_V8_2_INSN ("fmlal2", 0x6e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), FP16_V8_2_INSN ("fmlsl2", 0x6ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0), - FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0), - FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0), - FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0), - FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0), + FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), + FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), + FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), + FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0), - FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0), - FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0), - FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0), - FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0), + FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), + FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), + FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), + FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0), /* System extensions ARMv8.4-a. */ V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0), V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0), @@ -4454,6 +4454,8 @@ struct aarch64_opcode aarch64_opcode_table[] = "a SIMD vector element") \ Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ "a SIMD vector element") \ + Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ + "a SIMD vector element limited to V0-V15") \ Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ "a SIMD vector register list") \ Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ -- cgit v1.1