From 33399f071c6c3cf9877a22eeea94767dacef757b Mon Sep 17 00:00:00 2001
From: Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
Date: Fri, 24 Aug 2012 08:06:36 +0000
Subject: 	* gas/config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL. 
 (NEON_ENC_FPV8_): New define. 	(do_vfp_nsyn_fpv8): New function. 
 (do_vsel): Likewise. 	(insns): Add VSEL instructions. 	*
 gas/testsuite/gas/arm/armv8-a+fp.d: New testcase. 	*
 gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. 	* opcodes/arm-dis.c
 (coprocessor_opcodes): Add VSEL. 	(print_insn_coprocessor): Add new %<>c
 bitfield format 	specifier.

---
 opcodes/ChangeLog |  6 ++++++
 opcodes/arm-dis.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+)

(limited to 'opcodes')

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 29b9391..3d5e26e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
+	* arm-dis.c (coprocessor_opcodes): Add VSEL.
+	(print_insn_coprocessor): Add new %<>c bitfield format
+	specifier.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
 	* arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
 	(thumb32_opcodes): Likewise.
 	(print_arm_insn): Add support for %<>T formatter.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 9bc466c..2e4b333 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -102,6 +102,7 @@ struct opcode16
    %Q			print floating point precision in ldf/stf insn
    %R			print floating point rounding mode
 
+   %<bitfield>c		print as a condition code (for vsel)
    %<bitfield>r		print as an ARM register
    %<bitfield>R		as %<>r but r15 is UNPREDICTABLE
    %<bitfield>ru        as %<>r but each u register must be unique.
@@ -486,6 +487,10 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
   {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 
+  /* FP v5.  */
+  {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
+  {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+
   /* Generic coprocessor instructions.  */
   { 0, SENTINEL_GENERIC_START, 0, "" },
   {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
@@ -2198,6 +2203,31 @@ print_insn_coprocessor (bfd_vma pc,
 			func (stream, "0x%lx", (value & 0xffffffffUL));
 			break;
 
+		      case 'c':
+			switch (value)
+			  {
+			  case 0:
+			    func (stream, "eq");
+			    break;
+
+			  case 1:
+			    func (stream, "vs");
+			    break;
+
+			  case 2:
+			    func (stream, "ge");
+			    break;
+
+			  case 3:
+			    func (stream, "gt");
+			    break;
+
+			  default:
+			    func (stream, "??");
+			    break;
+			  }
+			break;
+
 		      case '`':
 			c++;
 			if (value == 0)
-- 
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