From 2c830de8f260ebb1feb0b13c17eefdf12722d9f7 Mon Sep 17 00:00:00 2001 From: nobody <> Date: Sat, 15 Jun 2002 12:26:33 +0000 Subject: This commit was manufactured by cvs2svn to create branch 'kseitz_interps-20020528-branch'. Cherrypick from cagney_regbuf-20020515-branch 2002-06-15 12:26:32 UTC nobody 'This commit was manufactured by cvs2svn to create branch': .cvsignore COPYING COPYING.LIB COPYING.NEWLIB MAINTAINERS README README-maintainer-mode bfd/COPYING bfd/ChangeLog-0001 bfd/ChangeLog-9193 bfd/ChangeLog-9495 bfd/ChangeLog-9697 bfd/ChangeLog-9899 bfd/MAINTAINERS bfd/PORTING bfd/README bfd/TODO bfd/aix386-core.c bfd/aout-arm.c bfd/aout-cris.c bfd/aout-encap.c bfd/aout-ns32k.c bfd/aout-sparcle.c bfd/aout0.c bfd/aout32.c bfd/aout64.c bfd/aoutf1.h bfd/aoutx.h bfd/archive.c bfd/archive64.c bfd/armnetbsd.c bfd/bfd-in.h bfd/cache.c bfd/cf-i386lynx.c bfd/cf-m68klynx.c bfd/cf-sparclynx.c bfd/cisco-core.c bfd/coff-a29k.c bfd/coff-alpha.c bfd/coff-apollo.c bfd/coff-aux.c bfd/coff-go32.c bfd/coff-h8300.c bfd/coff-h8500.c bfd/coff-i386.c bfd/coff-i860.c bfd/coff-i960.c bfd/coff-ia64.c bfd/coff-m68k.c bfd/coff-m88k.c bfd/coff-mcore.c bfd/coff-mips.c bfd/coff-or32.c bfd/coff-pmac.c bfd/coff-ppc.c bfd/coff-sparc.c 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gdb/config/m68k/tm-m68kv4.h gdb/config/m68k/tm-mac.h gdb/config/m68k/tm-monitor.h gdb/config/m68k/tm-os68k.h gdb/config/m68k/tm-st2000.h gdb/config/m68k/tm-sun2.h gdb/config/m68k/tm-sun2os4.h gdb/config/m68k/tm-sun3.h gdb/config/m68k/tm-sun3os4.h gdb/config/m68k/tm-vx68.h gdb/config/m68k/vxworks68.mt gdb/config/m68k/xm-3b1.h gdb/config/m68k/xm-apollo68b.h gdb/config/m68k/xm-apollo68v.h gdb/config/m68k/xm-delta68.h gdb/config/m68k/xm-dpx2.h gdb/config/m68k/xm-hp300bsd.h gdb/config/m68k/xm-hp300hpux.h gdb/config/m68k/xm-linux.h gdb/config/m68k/xm-m68k.h gdb/config/m68k/xm-m68kv4.h gdb/config/m68k/xm-nbsd.h gdb/config/m68k/xm-sun2.h gdb/config/m68k/xm-sun3.h gdb/config/m68k/xm-sun3os4.h gdb/config/m88k/delta88.mh gdb/config/m88k/delta88.mt gdb/config/m88k/delta88v4.mh gdb/config/m88k/delta88v4.mt gdb/config/m88k/m88k.mh gdb/config/m88k/m88k.mt gdb/config/m88k/nm-delta88v4.h gdb/config/m88k/nm-m88k.h gdb/config/m88k/tm-delta88.h gdb/config/m88k/tm-delta88v4.h gdb/config/m88k/tm-m88k.h gdb/config/m88k/xm-delta88.h gdb/config/m88k/xm-delta88v4.h gdb/config/m88k/xm-dgux.h gdb/config/mcore/mcore.mt gdb/config/mcore/tm-mcore.h gdb/config/mips/bigmips.mt gdb/config/mips/bigmips64.mt gdb/config/mips/decstation.mh gdb/config/mips/decstation.mt gdb/config/mips/embed.mt gdb/config/mips/embed64.mt gdb/config/mips/embedl.mt gdb/config/mips/embedl64.mt gdb/config/mips/irix3.mh gdb/config/mips/irix3.mt gdb/config/mips/irix4.mh gdb/config/mips/irix5.mh gdb/config/mips/irix5.mt gdb/config/mips/irix6.mh gdb/config/mips/irix6.mt gdb/config/mips/linux.mh gdb/config/mips/linux.mt gdb/config/mips/littlemips.mh gdb/config/mips/littlemips.mt gdb/config/mips/mipsm3.mh gdb/config/mips/mipsm3.mt gdb/config/mips/mipsv4.mh gdb/config/mips/mipsv4.mt gdb/config/mips/news-mips.mh gdb/config/mips/nm-irix3.h gdb/config/mips/nm-irix4.h gdb/config/mips/nm-irix5.h gdb/config/mips/nm-irix6.h gdb/config/mips/nm-linux.h gdb/config/mips/nm-mips.h gdb/config/mips/nm-news-mips.h gdb/config/mips/nm-riscos.h gdb/config/mips/riscos.mh gdb/config/mips/tm-bigmips.h gdb/config/mips/tm-bigmips64.h gdb/config/mips/tm-embed.h gdb/config/mips/tm-embed64.h gdb/config/mips/tm-embedl.h gdb/config/mips/tm-embedl64.h gdb/config/mips/tm-irix3.h gdb/config/mips/tm-irix5.h gdb/config/mips/tm-irix6.h gdb/config/mips/tm-linux.h gdb/config/mips/tm-mips.h gdb/config/mips/tm-mips64.h gdb/config/mips/tm-mipsm3.h gdb/config/mips/tm-mipsv4.h gdb/config/mips/tm-tx39.h gdb/config/mips/tm-tx39l.h gdb/config/mips/tm-vr4100.h gdb/config/mips/tm-vr4300.h gdb/config/mips/tm-vr4300el.h gdb/config/mips/tm-vr4xxx.h gdb/config/mips/tm-vr4xxxel.h gdb/config/mips/tm-vr5000.h gdb/config/mips/tm-vr5000el.h gdb/config/mips/tm-vxmips.h gdb/config/mips/tm-wince.h gdb/config/mips/tx39.mt gdb/config/mips/tx39l.mt gdb/config/mips/vr4100.mt gdb/config/mips/vr4300.mt gdb/config/mips/vr4300el.mt gdb/config/mips/vr4xxx.mt gdb/config/mips/vr4xxxel.mt gdb/config/mips/vr5000.mt gdb/config/mips/vr5000el.mt gdb/config/mips/vxmips.mt gdb/config/mips/wince.mt gdb/config/mips/xm-irix3.h gdb/config/mips/xm-irix4.h gdb/config/mips/xm-irix5.h gdb/config/mips/xm-irix6.h gdb/config/mips/xm-linux.h gdb/config/mips/xm-mips.h gdb/config/mips/xm-mipsm3.h gdb/config/mips/xm-mipsv4.h gdb/config/mips/xm-riscos.h gdb/config/mn10200/mn10200.mt gdb/config/mn10200/tm-mn10200.h gdb/config/mn10300/mn10300.mt gdb/config/nm-gnu.h gdb/config/nm-linux.h gdb/config/nm-lynx.h gdb/config/nm-m3.h gdb/config/nm-sysv4.h gdb/config/none/nm-none.h gdb/config/none/none.mh gdb/config/none/none.mt gdb/config/none/tm-none.h gdb/config/none/xm-none.h gdb/config/ns32k/xm-nbsd.h gdb/config/pa/hppa64.mt gdb/config/pa/hppabsd.mh gdb/config/pa/hppabsd.mt gdb/config/pa/hppahpux.mh gdb/config/pa/hppahpux.mt gdb/config/pa/hppaosf.mh gdb/config/pa/hppaosf.mt gdb/config/pa/hppapro.mt gdb/config/pa/hpux1020.mh gdb/config/pa/hpux1020.mt gdb/config/pa/hpux11.mh gdb/config/pa/hpux11.mt gdb/config/pa/hpux11w.mt gdb/config/pa/nm-hppab.h gdb/config/pa/nm-hppah.h gdb/config/pa/nm-hppah11.h gdb/config/pa/nm-hppao.h gdb/config/pa/tm-hppa.h gdb/config/pa/tm-hppa64.h gdb/config/pa/tm-hppab.h gdb/config/pa/tm-hppah.h gdb/config/pa/tm-hppao.h gdb/config/pa/tm-pro.h gdb/config/pa/xm-hppab.h gdb/config/pa/xm-hppah.h gdb/config/pa/xm-pa.h gdb/config/powerpc/aix.mh gdb/config/powerpc/aix.mt gdb/config/powerpc/gdbserve.mt gdb/config/powerpc/linux.mh gdb/config/powerpc/linux.mt gdb/config/powerpc/nm-aix.h gdb/config/powerpc/nm-linux.h gdb/config/powerpc/ppc-eabi.mt gdb/config/powerpc/ppc-sim.mt gdb/config/powerpc/ppcle-eabi.mt gdb/config/powerpc/ppcle-sim.mt gdb/config/powerpc/tm-linux.h gdb/config/powerpc/tm-ppc-aix.h gdb/config/powerpc/tm-ppc-eabi.h gdb/config/powerpc/tm-ppc-sim.h gdb/config/powerpc/tm-ppcle-eabi.h gdb/config/powerpc/tm-ppcle-sim.h gdb/config/powerpc/tm-vxworks.h gdb/config/powerpc/vxworks.mt gdb/config/powerpc/xm-aix.h gdb/config/powerpc/xm-linux.h gdb/config/romp/rtbsd.mh gdb/config/romp/xm-rtbsd.h gdb/config/rs6000/aix4.mh gdb/config/rs6000/aix4.mt gdb/config/rs6000/nm-rs6000.h gdb/config/rs6000/nm-rs6000ly.h gdb/config/rs6000/rs6000.mh gdb/config/rs6000/rs6000.mt gdb/config/rs6000/rs6000lynx.mh gdb/config/rs6000/rs6000lynx.mt gdb/config/rs6000/tm-rs6000-aix4.h gdb/config/rs6000/tm-rs6000.h gdb/config/rs6000/tm-rs6000ly.h gdb/config/rs6000/xm-aix4.h gdb/config/rs6000/xm-rs6000.h gdb/config/s390/nm-linux.h gdb/config/s390/s390.mh gdb/config/s390/s390.mt gdb/config/s390/s390x.mt gdb/config/s390/tm-linux.h gdb/config/s390/tm-s390.h gdb/config/s390/xm-linux.h gdb/config/sh/embed.mt gdb/config/sh/linux.mt gdb/config/sh/nbsd.mh gdb/config/sh/nbsd.mt gdb/config/sh/nm-nbsd.h gdb/config/sh/tm-linux.h gdb/config/sh/tm-nbsd.h gdb/config/sh/tm-wince.h gdb/config/sh/wince.mt gdb/config/sparc/fbsd.mh gdb/config/sparc/fbsd.mt gdb/config/sparc/linux.mh gdb/config/sparc/linux.mt gdb/config/sparc/nbsd64.mh gdb/config/sparc/nbsd64.mt gdb/config/sparc/nm-fbsd.h gdb/config/sparc/nm-linux.h gdb/config/sparc/nm-nbsd.h gdb/config/sparc/nm-sparclynx.h gdb/config/sparc/nm-sun4os4.h gdb/config/sparc/nm-sun4sol2.h gdb/config/sparc/sp64.mt gdb/config/sparc/sp64linux.mt gdb/config/sparc/sp64sim.mt gdb/config/sparc/sp64sol2.mt gdb/config/sparc/sparc-em.mt gdb/config/sparc/sparclet.mt gdb/config/sparc/sparclite.mt gdb/config/sparc/sparclynx.mh gdb/config/sparc/sparclynx.mt gdb/config/sparc/sun4os4.mh gdb/config/sparc/sun4os4.mt gdb/config/sparc/sun4sol2.mh gdb/config/sparc/sun4sol2.mt gdb/config/sparc/tm-fbsd.h gdb/config/sparc/tm-linux.h gdb/config/sparc/tm-nbsd64.h gdb/config/sparc/tm-sp64.h gdb/config/sparc/tm-sp64linux.h gdb/config/sparc/tm-sp64sim.h gdb/config/sparc/tm-sparc.h gdb/config/sparc/tm-sparclet.h gdb/config/sparc/tm-sparclite.h gdb/config/sparc/tm-sparclynx.h gdb/config/sparc/tm-spc-em.h gdb/config/sparc/tm-sun4os4.h gdb/config/sparc/tm-sun4sol2.h gdb/config/sparc/tm-vxsparc.h gdb/config/sparc/vxsparc.mt gdb/config/sparc/xm-linux.h gdb/config/sparc/xm-nbsd.h gdb/config/sparc/xm-sun4sol2.h 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gdb/doc/configure.in gdb/doc/fdl.texi gdb/doc/gpl.texi gdb/doc/lpsrc.sed gdb/doc/psrc.sed gdb/doc/refcard.tex gdb/doc/stabs.texinfo gdb/doublest.c gdb/doublest.h gdb/dpx2-nat.c gdb/dsrec.c gdb/dst.h gdb/dstread.c gdb/dve3900-rom.c gdb/dwarf2cfi.h gdb/dwarfread.c gdb/elfread.c gdb/environ.c gdb/environ.h gdb/eval.c gdb/event-loop.h gdb/exc_request.defs gdb/exec.c gdb/expprint.c gdb/expression.h gdb/f-exp.y gdb/f-lang.c gdb/f-lang.h gdb/f-typeprint.c gdb/f-valprint.c gdb/fbsd-proc.c gdb/findvar.c gdb/fork-child.c gdb/fr30-tdep.c gdb/frame.c gdb/gcore.c gdb/gdb-events.c gdb/gdb-events.h gdb/gdb-events.sh gdb/gdb-stabs.h gdb/gdb.1 gdb/gdb.gdb gdb/gdb.h gdb/gdb_assert.h gdb/gdb_dirent.h gdb/gdb_proc_service.h gdb/gdb_regex.h gdb/gdb_stat.h gdb/gdb_string.h gdb/gdb_thread_db.h gdb/gdb_vfork.h gdb/gdb_wait.h gdb/gdbcmd.h gdb/gdbcore.h gdb/gdbinit.in gdb/gdbserver/Makefile.in gdb/gdbserver/README gdb/gdbserver/acconfig.h gdb/gdbserver/acinclude.m4 gdb/gdbserver/aclocal.m4 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include/opcode/pj.h include/opcode/pn.h include/opcode/ppc.h include/opcode/pyr.h include/opcode/s390.h include/opcode/tahoe.h include/opcode/tic30.h include/opcode/tic54x.h include/opcode/tic80.h include/opcode/v850.h include/opcode/vax.h include/os9k.h include/partition.h include/progress.h include/regs/ChangeLog include/remote-sim.h include/safe-ctype.h include/sort.h include/splay-tree.h include/symcat.h include/ternary.h include/xregex.h include/xregex2.h install-sh intl/ChangeLog intl/Makefile.in intl/acconfig.h intl/aclocal.m4 intl/bindtextdom.c intl/cat-compat.c intl/config.in intl/configure intl/configure.in intl/dcgettext.c intl/dgettext.c intl/explodename.c intl/finddomain.c intl/gettext.c intl/gettext.h intl/gettextP.h intl/hash-string.h intl/intl-compat.c intl/intlh.inst.in intl/l10nflist.c intl/libgettext.h intl/libintl.glibc intl/linux-msg.sed intl/loadinfo.h intl/loadmsgcat.c intl/localealias.c intl/po2tbl.sed.in intl/textdomain.c intl/xopen-msg.sed libiberty/COPYING.LIB libiberty/Makefile.in libiberty/README libiberty/_doprnt.c libiberty/aclocal.m4 libiberty/alloca.c libiberty/argv.c libiberty/asprintf.c libiberty/atexit.c libiberty/basename.c libiberty/bcmp.c libiberty/bcopy.c libiberty/bsearch.c libiberty/bzero.c libiberty/calloc.c libiberty/choose-temp.c libiberty/clock.c libiberty/concat.c libiberty/config.h-vms libiberty/config.in libiberty/config/mh-aix libiberty/config/mh-cxux7 libiberty/config/mh-fbsd21 libiberty/config/mh-openedition libiberty/config/mh-windows libiberty/configure libiberty/configure.in libiberty/copying-lib.texi libiberty/copysign.c libiberty/cp-demangle.c libiberty/cplus-dem.c libiberty/dyn-string.c libiberty/fdmatch.c libiberty/ffs.c libiberty/fibheap.c libiberty/floatformat.c libiberty/fnmatch.c libiberty/fnmatch.txh libiberty/functions.texi libiberty/gather-docs libiberty/getcwd.c libiberty/getopt.c libiberty/getopt1.c libiberty/getpagesize.c libiberty/getpwd.c libiberty/getruntime.c libiberty/hashtab.c libiberty/hex.c libiberty/index.c libiberty/insque.c libiberty/lbasename.c libiberty/libiberty.texi libiberty/maint-tool libiberty/make-temp-file.c libiberty/makefile.vms libiberty/md5.c libiberty/memchr.c libiberty/memcmp.c libiberty/memcpy.c libiberty/memmove.c libiberty/memset.c libiberty/mkstemps.c libiberty/mpw-config.in libiberty/mpw-make.sed libiberty/mpw.c libiberty/msdos.c libiberty/objalloc.c libiberty/obstack.c libiberty/obstacks.texi libiberty/partition.c libiberty/pexecute.c libiberty/putenv.c libiberty/random.c libiberty/regex.c libiberty/rename.c libiberty/rindex.c libiberty/safe-ctype.c libiberty/setenv.c libiberty/sigsetmask.c libiberty/sort.c libiberty/spaces.c libiberty/splay-tree.c libiberty/strcasecmp.c libiberty/strchr.c libiberty/strdup.c libiberty/strerror.c libiberty/strncasecmp.c libiberty/strncmp.c libiberty/strrchr.c libiberty/strsignal.c libiberty/strstr.c libiberty/strtod.c libiberty/strtol.c libiberty/strtoul.c libiberty/ternary.c libiberty/testsuite/Makefile.in libiberty/testsuite/demangle-expected libiberty/testsuite/regress-demangle libiberty/tmpnam.c libiberty/vasprintf.c libiberty/vfork.c libiberty/vfprintf.c libiberty/vmsbuild.com libiberty/vprintf.c libiberty/vsprintf.c libiberty/waitpid.c libiberty/xatexit.c libiberty/xexit.c libiberty/xmalloc.c libiberty/xmemdup.c libiberty/xstrdup.c libiberty/xstrerror.c libtool.m4 ltcf-c.sh ltcf-cxx.sh ltcf-gcj.sh ltconfig ltmain.sh makefile.vms missing mkdep mkinstalldirs mmalloc/COPYING.LIB mmalloc/ChangeLog mmalloc/MAINTAINERS mmalloc/Makefile.in mmalloc/TODO mmalloc/acinclude.m4 mmalloc/aclocal.m4 mmalloc/attach.c mmalloc/configure mmalloc/configure.in mmalloc/detach.c mmalloc/keys.c mmalloc/mcalloc.c mmalloc/mfree.c mmalloc/mm.c mmalloc/mmalloc.c mmalloc/mmalloc.h mmalloc/mmalloc.texi mmalloc/mmap-sup.c mmalloc/mmcheck.c mmalloc/mmemalign.c mmalloc/mmprivate.h mmalloc/mmstats.c mmalloc/mmtrace.awk mmalloc/mmtrace.c mmalloc/mrealloc.c mmalloc/mvalloc.c mmalloc/sbrk-sup.c move-if-change mpw-README mpw-build.in mpw-config.in mpw-configure mpw-install opcodes/ChangeLog-9297 opcodes/ChangeLog-9899 opcodes/MAINTAINERS opcodes/a29k-dis.c opcodes/alpha-dis.c opcodes/alpha-opc.c opcodes/arc-dis.h opcodes/arc-ext.c opcodes/arc-ext.h opcodes/arc-opc.c opcodes/arm-opc.h opcodes/avr-dis.c opcodes/cgen-asm.c opcodes/cgen-asm.in opcodes/cgen-dis.c opcodes/cgen-dis.in opcodes/cgen-ibld.in opcodes/cgen-opc.c opcodes/cgen.sh opcodes/config.in opcodes/cris-dis.c opcodes/cris-opc.c opcodes/d10v-dis.c opcodes/d10v-opc.c opcodes/d30v-dis.c opcodes/d30v-opc.c opcodes/dep-in.sed opcodes/dis-buf.c opcodes/fr30-desc.h opcodes/fr30-ibld.c opcodes/fr30-opc.c opcodes/fr30-opc.h opcodes/h8300-dis.c opcodes/h8500-dis.c opcodes/h8500-opc.h opcodes/hppa-dis.c opcodes/i370-dis.c opcodes/i370-opc.c opcodes/i386-dis.c opcodes/i860-dis.c opcodes/i960-dis.c opcodes/ia64-asmtab.c opcodes/ia64-asmtab.h opcodes/ia64-dis.c opcodes/ia64-gen.c opcodes/ia64-ic.tbl opcodes/ia64-opc-a.c opcodes/ia64-opc-b.c opcodes/ia64-opc-d.c opcodes/ia64-opc-f.c opcodes/ia64-opc-i.c opcodes/ia64-opc-m.c opcodes/ia64-opc-x.c opcodes/ia64-opc.c opcodes/ia64-opc.h opcodes/ia64-raw.tbl opcodes/ia64-war.tbl opcodes/ia64-waw.tbl opcodes/m10200-dis.c opcodes/m10200-opc.c opcodes/m10300-dis.c opcodes/m10300-opc.c opcodes/m32r-desc.h opcodes/m32r-ibld.c opcodes/m32r-opc.c opcodes/m32r-opc.h opcodes/m32r-opinst.c opcodes/m68hc11-dis.c opcodes/m68hc11-opc.c opcodes/m68k-opc.c opcodes/m88k-dis.c opcodes/makefile.vms opcodes/mcore-dis.c opcodes/mcore-opc.h opcodes/mips16-opc.c opcodes/mmix-dis.c opcodes/mmix-opc.c opcodes/mpw-config.in opcodes/mpw-make.sed opcodes/ns32k-dis.c opcodes/openrisc-desc.h opcodes/openrisc-ibld.c opcodes/openrisc-opc.c opcodes/openrisc-opc.h opcodes/opintl.h opcodes/or32-dis.c opcodes/or32-opc.c opcodes/pdp11-dis.c opcodes/pdp11-opc.c opcodes/pj-dis.c opcodes/pj-opc.c opcodes/po/.cvsignore opcodes/po/Make-in opcodes/po/POTFILES.in opcodes/po/da.po opcodes/po/de.po opcodes/po/es.po opcodes/po/fr.po opcodes/po/id.po opcodes/po/opcodes.pot opcodes/po/sv.po opcodes/po/tr.po opcodes/ppc-dis.c opcodes/ppc-opc.c opcodes/s390-dis.c opcodes/s390-mkopc.c opcodes/s390-opc.c opcodes/s390-opc.txt opcodes/sh-opc.h opcodes/sh64-opc.c opcodes/sh64-opc.h opcodes/sparc-dis.c opcodes/sparc-opc.c opcodes/stamp-h.in opcodes/sysdep.h opcodes/tic30-dis.c opcodes/tic54x-dis.c opcodes/tic54x-opc.c opcodes/tic80-dis.c opcodes/tic80-opc.c opcodes/v850-dis.c opcodes/v850-opc.c opcodes/vax-dis.c opcodes/w65-dis.c opcodes/w65-opc.h opcodes/xstormy16-desc.h opcodes/xstormy16-ibld.c opcodes/xstormy16-opc.c opcodes/xstormy16-opc.h opcodes/z8k-dis.c opcodes/z8k-opc.h opcodes/z8kgen.c readline/CHANGELOG readline/CHANGES readline/COPYING readline/ChangeLog.gdb readline/INSTALL readline/MANIFEST readline/Makefile.in readline/README readline/USAGE readline/acconfig.h readline/aclocal.m4 readline/ansi_stdlib.h readline/bind.c readline/callback.c readline/chardefs.h readline/complete.c readline/config.h.bot readline/config.h.in readline/configure readline/configure.in readline/cross-build/cygwin.cache readline/display.c readline/doc/ChangeLog.gdb readline/doc/Makefile.in readline/doc/hist.texinfo readline/doc/hstech.texinfo readline/doc/hsuser.texinfo readline/doc/inc-hist.texinfo readline/doc/manvers.texinfo readline/doc/readline.3 readline/doc/rlman.texinfo readline/doc/rltech.texinfo readline/doc/rluser.texinfo readline/doc/rluserman.texinfo readline/doc/texi2dvi readline/doc/texi2html readline/emacs_keymap.c readline/examples/ChangeLog.gdb readline/examples/Inputrc readline/examples/Makefile.in readline/examples/excallback.c readline/examples/fileman.c readline/examples/histexamp.c readline/examples/manexamp.c readline/examples/rl.c readline/examples/rlfe.c readline/examples/rltest.c readline/examples/rlversion.c readline/funmap.c readline/histexpand.c readline/histfile.c readline/histlib.h readline/history.c readline/history.h readline/histsearch.c readline/input.c readline/isearch.c readline/keymaps.c readline/keymaps.h readline/kill.c readline/macro.c readline/nls.c readline/parens.c readline/posixdir.h readline/posixjmp.h readline/posixstat.h readline/readline.c readline/readline.h readline/rlconf.h readline/rldefs.h readline/rlprivate.h readline/rlshell.h readline/rlstdc.h readline/rltty.c readline/rltty.h readline/rlwinsize.h readline/savestring.c readline/search.c readline/shell.c readline/shlib/Makefile.in readline/signals.c readline/support/config.guess readline/support/config.sub readline/support/install.sh readline/support/mkdirs readline/support/mkdist readline/support/shlib-install readline/support/shobj-conf readline/tcap.h readline/terminal.c readline/tilde.c readline/tilde.h readline/undo.c readline/util.c readline/vi_keymap.c readline/vi_mode.c readline/xmalloc.c readline/xmalloc.h setup.com sim/Makefile.in sim/README-HACKING sim/arm/COPYING sim/arm/README.Cygnus sim/arm/acconfig.h sim/arm/armdefs.h sim/arm/armemu.h sim/arm/armfpe.h sim/arm/arminit.c sim/arm/armopts.h sim/arm/armos.h sim/arm/armrdi.c sim/arm/bag.c sim/arm/bag.h sim/arm/communicate.c sim/arm/communicate.h sim/arm/config.in sim/arm/configure sim/arm/configure.in sim/arm/dbg_conf.h sim/arm/dbg_cp.h sim/arm/dbg_hif.h sim/arm/gdbhost.c sim/arm/gdbhost.h sim/arm/kid.c sim/arm/main.c sim/arm/parent.c sim/arm/tconfig.in sim/common/Make-common.in sim/common/Makefile.in sim/common/acconfig.h sim/common/aclocal.m4 sim/common/callback.c sim/common/cgen-accfp.c sim/common/cgen-cpu.h sim/common/cgen-defs.h sim/common/cgen-engine.h sim/common/cgen-fpu.c sim/common/cgen-fpu.h sim/common/cgen-mem.h sim/common/cgen-ops.h sim/common/cgen-par.c sim/common/cgen-par.h sim/common/cgen-run.c sim/common/cgen-scache.c sim/common/cgen-scache.h sim/common/cgen-sim.h sim/common/cgen-trace.c sim/common/cgen-trace.h sim/common/cgen-types.h sim/common/cgen-utils.c sim/common/cgen.sh sim/common/config.in sim/common/configure sim/common/configure.in sim/common/dv-core.c sim/common/dv-glue.c sim/common/dv-pal.c sim/common/dv-sockser.c sim/common/dv-sockser.h sim/common/gdbinit.in sim/common/genmloop.sh sim/common/gennltvals.sh sim/common/gentmap.c sim/common/gentvals.sh sim/common/hw-alloc.c sim/common/hw-alloc.h sim/common/hw-base.c sim/common/hw-base.h sim/common/hw-device.c sim/common/hw-device.h sim/common/hw-events.c sim/common/hw-events.h sim/common/hw-handles.c sim/common/hw-handles.h sim/common/hw-instances.c sim/common/hw-instances.h sim/common/hw-main.h sim/common/hw-ports.c sim/common/hw-ports.h sim/common/hw-properties.c sim/common/hw-properties.h sim/common/hw-tree.c sim/common/hw-tree.h sim/common/nltvals.def sim/common/nrun.c sim/common/run.1 sim/common/sim-abort.c sim/common/sim-alu.h sim/common/sim-arange.c sim/common/sim-arange.h sim/common/sim-assert.h sim/common/sim-base.h sim/common/sim-basics.h sim/common/sim-bits.c sim/common/sim-bits.h sim/common/sim-break.c sim/common/sim-break.h sim/common/sim-config.c sim/common/sim-config.h sim/common/sim-core.c sim/common/sim-core.h sim/common/sim-cpu.c sim/common/sim-cpu.h sim/common/sim-endian.c sim/common/sim-endian.h sim/common/sim-engine.c sim/common/sim-engine.h sim/common/sim-events.c sim/common/sim-events.h sim/common/sim-fpu.c sim/common/sim-fpu.h sim/common/sim-hload.c sim/common/sim-hrw.c sim/common/sim-hw.c sim/common/sim-hw.h sim/common/sim-info.c sim/common/sim-inline.c sim/common/sim-inline.h sim/common/sim-io.c sim/common/sim-io.h sim/common/sim-load.c sim/common/sim-memopt.c sim/common/sim-memopt.h sim/common/sim-model.c sim/common/sim-model.h sim/common/sim-module.c sim/common/sim-module.h sim/common/sim-n-bits.h sim/common/sim-n-core.h sim/common/sim-n-endian.h sim/common/sim-options.h sim/common/sim-profile.c sim/common/sim-profile.h sim/common/sim-reason.c sim/common/sim-reg.c sim/common/sim-resume.c sim/common/sim-run.c sim/common/sim-signal.c sim/common/sim-signal.h sim/common/sim-stop.c sim/common/sim-trace.c sim/common/sim-trace.h sim/common/sim-types.h sim/common/sim-utils.c sim/common/sim-utils.h sim/common/sim-watch.c sim/common/sim-watch.h sim/common/syscall.c sim/common/tconfig.in sim/configure sim/configure.in sim/d10v/acconfig.h sim/d10v/config.in sim/d10v/configure sim/d10v/configure.in sim/d10v/d10v_sim.h sim/d10v/endian.c sim/d10v/gencode.c sim/d30v/ChangeLog sim/d30v/Makefile.in sim/d30v/acconfig.h sim/d30v/alu.h sim/d30v/config.in sim/d30v/configure sim/d30v/configure.in sim/d30v/cpu.c sim/d30v/cpu.h sim/d30v/d30v-insns sim/d30v/dc-short sim/d30v/engine.c sim/d30v/ic-d30v sim/d30v/sim-calls.c sim/d30v/sim-main.h sim/d30v/tconfig.in sim/erc32/ChangeLog sim/erc32/Makefile.in sim/erc32/NEWS sim/erc32/README.erc32 sim/erc32/README.gdb sim/erc32/README.sis sim/erc32/acconfig.h sim/erc32/config.in sim/erc32/configure sim/erc32/configure.in sim/erc32/end.c sim/erc32/erc32.c sim/erc32/exec.c sim/erc32/float.c sim/erc32/func.c sim/erc32/help.c sim/erc32/interf.c sim/erc32/sis.c sim/erc32/sis.h sim/erc32/startsim sim/fr30/ChangeLog sim/fr30/Makefile.in sim/fr30/README sim/fr30/TODO sim/fr30/arch.c sim/fr30/arch.h sim/fr30/config.in sim/fr30/configure sim/fr30/configure.in sim/fr30/cpu.c sim/fr30/cpu.h sim/fr30/cpuall.h sim/fr30/decode.c sim/fr30/decode.h sim/fr30/devices.c sim/fr30/fr30-sim.h sim/fr30/fr30.c sim/fr30/mloop.in sim/fr30/model.c sim/fr30/sem-switch.c sim/fr30/sem.c sim/fr30/sim-if.c sim/fr30/sim-main.h sim/fr30/tconfig.in sim/fr30/traps.c sim/h8300/Makefile.in sim/h8300/acconfig.h sim/h8300/config.in sim/h8300/configure sim/h8300/configure.in sim/h8300/tconfig.in sim/h8300/writecode.c sim/h8500/ChangeLog sim/h8500/Makefile.in sim/h8500/acconfig.h sim/h8500/compile.c sim/h8500/config.in sim/h8500/configure sim/h8500/configure.in sim/h8500/inst.h sim/h8500/tconfig.in sim/i960/ChangeLog sim/i960/Makefile.in sim/i960/README sim/i960/TODO sim/i960/acconfig.h sim/i960/arch.c sim/i960/arch.h sim/i960/config.in sim/i960/configure sim/i960/configure.in sim/i960/cpu.c sim/i960/cpu.h sim/i960/cpuall.h sim/i960/decode.c sim/i960/decode.h sim/i960/devices.c sim/i960/i960-desc.c sim/i960/i960-desc.h sim/i960/i960-opc.h sim/i960/i960-sim.h sim/i960/i960.c sim/i960/mloop.in sim/i960/model.c sim/i960/sem-switch.c sim/i960/sem.c sim/i960/sim-if.c sim/i960/sim-main.h sim/i960/tconfig.in sim/i960/traps.c sim/igen/ChangeLog sim/igen/Makefile.in sim/igen/acconfig.h sim/igen/config.in sim/igen/configure sim/igen/configure.in sim/igen/filter.c sim/igen/filter.h sim/igen/filter_host.c sim/igen/filter_host.h sim/igen/gen-engine.c sim/igen/gen-engine.h sim/igen/gen-icache.c sim/igen/gen-icache.h sim/igen/gen-idecode.c sim/igen/gen-idecode.h sim/igen/gen-itable.c sim/igen/gen-itable.h sim/igen/gen-model.c sim/igen/gen-model.h sim/igen/gen-semantics.c sim/igen/gen-semantics.h sim/igen/gen-support.c sim/igen/gen-support.h sim/igen/gen.c sim/igen/gen.h sim/igen/igen.c sim/igen/igen.h sim/igen/ld-cache.c sim/igen/ld-cache.h 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sim/testsuite/sim/m32r/srli.cgs sim/testsuite/sim/m32r/st-d.cgs sim/testsuite/sim/m32r/st-minus.cgs sim/testsuite/sim/m32r/st-plus.cgs sim/testsuite/sim/m32r/st.cgs sim/testsuite/sim/m32r/stb-d.cgs sim/testsuite/sim/m32r/stb.cgs sim/testsuite/sim/m32r/sth-d.cgs sim/testsuite/sim/m32r/sth.cgs sim/testsuite/sim/m32r/sub.cgs sim/testsuite/sim/m32r/subv.cgs sim/testsuite/sim/m32r/subx.cgs sim/testsuite/sim/m32r/testutils.inc sim/testsuite/sim/m32r/trap.cgs sim/testsuite/sim/m32r/unlock.cgs sim/testsuite/sim/m32r/uread16.ms sim/testsuite/sim/m32r/uread32.ms sim/testsuite/sim/m32r/uwrite16.ms sim/testsuite/sim/m32r/uwrite32.ms sim/testsuite/sim/m32r/xor.cgs sim/testsuite/sim/m32r/xor3.cgs sim/tic80/ChangeLog sim/tic80/Makefile.in sim/tic80/acconfig.h sim/tic80/alu.h sim/tic80/config.in sim/tic80/configure sim/tic80/configure.in sim/tic80/cpu.h sim/tic80/interp.c sim/tic80/misc.c sim/tic80/sim-calls.c sim/tic80/sim-main.h sim/tic80/tic80.dc sim/tic80/tic80.ic sim/tic80/tic80.igen sim/v850/ChangeLog sim/v850/Makefile.in sim/v850/acconfig.h sim/v850/config.in sim/v850/configure sim/v850/configure.in sim/v850/interp.c sim/v850/sim-main.h sim/v850/simops.c sim/v850/simops.h sim/v850/v850-dc sim/v850/v850.igen sim/v850/v850_sim.h sim/w65/ChangeLog sim/w65/Makefile.in sim/w65/acconfig.h sim/w65/config.in sim/w65/configure sim/w65/configure.in sim/w65/gencode.c sim/w65/interp.c sim/w65/interp.h sim/w65/run.c sim/z8k/ChangeLog sim/z8k/Makefile.in sim/z8k/acconfig.h sim/z8k/comped1.c sim/z8k/comped2.c sim/z8k/comped3.c sim/z8k/compedb3.c sim/z8k/config.in sim/z8k/configure sim/z8k/configure.in sim/z8k/iface.c sim/z8k/inlines.h sim/z8k/list.c sim/z8k/mem.c sim/z8k/mem.h sim/z8k/quick.c sim/z8k/sim.h sim/z8k/support.c sim/z8k/syscall.h sim/z8k/tconfig.in sim/z8k/tm.h sim/z8k/writecode.c symlink-tree texinfo/texinfo.tex ylwrap Cherrypick from cagney_regbuf-20020515-branch 2002-05-15 21:19:22 UTC nobody 'This commit was manufactured by cvs2svn to create branch': gdb/blockframe.c gdb/frame.h gdb/gdbarch.c gdb/gdbarch.h gdb/gdbarch.sh gdb/infcmd.c gdb/inferior.h gdb/infrun.c gdb/regcache.c gdb/regcache.h gdb/valops.c gdb/value.h gdb/values.c Cherrypick from master 2002-05-28 20:06:27 UTC Marek Michalkiewicz '2002-05-28 Marek Michalkiewicz ': ChangeLog Makefile.in bfd/ChangeLog bfd/Makefile.am bfd/Makefile.in bfd/acinclude.m4 bfd/aclocal.m4 bfd/aix5ppc-core.c bfd/aout-adobe.c bfd/aout-target.h bfd/aout-tic30.c bfd/archures.c bfd/bfd-in2.h bfd/bfd.c bfd/binary.c bfd/bout.c bfd/coff-arm.c bfd/coff-rs6000.c bfd/coff-sh.c bfd/coff64-rs6000.c bfd/coffcode.h bfd/config.bfd bfd/config.in bfd/configure bfd/configure.in bfd/cpu-dlx.c bfd/cpu-mips.c bfd/doc/ChangeLog bfd/doc/Makefile.in bfd/doc/chew.c bfd/elf-bfd.h bfd/elf-eh-frame.c bfd/elf.c bfd/elf32-arm.h bfd/elf32-dlx.c bfd/elf32-i386.c bfd/elf32-m68k.c bfd/elf32-mips.c bfd/elf64-ppc.c bfd/elf64-x86-64.c bfd/elflink.h bfd/elfxx-ia64.c bfd/elfxx-mips.c bfd/elfxx-target.h bfd/hash.c bfd/i386msdos.c bfd/i386os9k.c bfd/ieee.c bfd/ihex.c bfd/libbfd-in.h bfd/libbfd.h bfd/libecoff.h bfd/linker.c bfd/mmo.c bfd/nlm-target.h bfd/oasys.c bfd/peXXigen.c bfd/ppcboot.c bfd/reloc.c bfd/rs6000-core.c bfd/section.c bfd/som.c bfd/srec.c bfd/syms.c bfd/targets.c bfd/tekhex.c bfd/versados.c bfd/version.h bfd/vms.c config-ml.in config.guess config.sub config/ChangeLog config/acinclude.m4 config/mh-apollo68 config/mh-dgux config/mh-dgux386 configure configure.in gdb/MAINTAINERS gdb/NEWS gdb/PROBLEMS gdb/alpha-linux-tdep.c gdb/alpha-osf1-tdep.c gdb/alpha-tdep.c gdb/alpha-tdep.h gdb/alphafbsd-tdep.c gdb/alphanbsd-tdep.c gdb/arm-linux-tdep.c gdb/arm-tdep.c gdb/arm-tdep.h gdb/armnbsd-tdep.c gdb/c-exp.y gdb/c-lang.c gdb/c-lang.h gdb/cli/cli-dump.c gdb/config/alpha/nm-nbsd.h gdb/config/alpha/tm-nbsd.h gdb/config/arm/nbsd.mt gdb/config/arm/nbsdaout.mh gdb/config/arm/nbsdelf.mh gdb/config/arm/nm-nbsd.h gdb/config/arm/nm-nbsdaout.h gdb/config/avr/avr.mt gdb/config/djgpp/fnchange.lst gdb/config/h8300/tm-h8300.h gdb/config/i386/nbsdaout.mh gdb/config/i386/nbsdaout.mt gdb/config/i386/nbsdelf.mh gdb/config/i386/nbsdelf.mt gdb/config/i386/nm-cygwin.h gdb/config/i386/nm-go32.h gdb/config/i386/nm-nbsd.h gdb/config/i386/nm-nbsdaout.h gdb/config/i386/tm-nbsd.h gdb/config/i386/tm-nbsdaout.h gdb/config/m68k/nbsdaout.mh gdb/config/m68k/nbsdaout.mt gdb/config/m68k/nm-nbsd.h gdb/config/m68k/nm-nbsdaout.h gdb/config/m68k/tm-nbsd.h gdb/config/mips/nbsd.mh gdb/config/mips/nbsd.mt gdb/config/mips/nm-nbsd.h gdb/config/mips/tm-nbsd.h gdb/config/nm-nbsd.h gdb/config/nm-nbsdaout.h gdb/config/ns32k/nbsdaout.mh gdb/config/ns32k/nbsdaout.mt gdb/config/ns32k/nm-nbsd.h gdb/config/ns32k/nm-nbsdaout.h gdb/config/ns32k/tm-nbsd.h gdb/config/ns32k/tm-ns32k.h gdb/config/pa/hpux11w.mh gdb/config/powerpc/nbsd.mh gdb/config/powerpc/nbsd.mt gdb/config/powerpc/nm-nbsd.h gdb/config/powerpc/tm-nbsd.h gdb/config/sh/tm-sh.h gdb/config/sparc/nbsdaout.mh gdb/config/sparc/nbsdaout.mt gdb/config/sparc/nbsdelf.mh gdb/config/sparc/nbsdelf.mt gdb/config/sparc/nm-nbsdaout.h gdb/config/sparc/tm-nbsd.h gdb/config/sparc/tm-nbsdaout.h gdb/config/v850/v850.mt gdb/configure.host gdb/configure.tgt gdb/corelow.c gdb/d10v-tdep.c gdb/doc/ChangeLog gdb/doc/gdb.texinfo gdb/doc/gdbint.texinfo gdb/dwarf2cfi.c gdb/dwarf2read.c gdb/gdb_indent.sh gdb/gdbserver/server.c gdb/gdbtypes.c gdb/gdbtypes.h gdb/h8300-tdep.c gdb/hpread.c gdb/i386-tdep.c gdb/macrocmd.c gdb/macroscope.c gdb/macroscope.h gdb/macrotab.c gdb/mi/ChangeLog gdb/mips-tdep.c gdb/mipsnbsd-nat.c gdb/mipsnbsd-tdep.c gdb/mipsnbsd-tdep.h gdb/ns32k-tdep.c gdb/ns32k-tdep.h gdb/ns32knbsd-tdep.c gdb/osabi.c gdb/osabi.h gdb/p-exp.y gdb/parse.c gdb/parser-defs.h gdb/ppcnbsd-nat.c gdb/ppcnbsd-tdep.c gdb/ppcnbsd-tdep.h gdb/remote.c gdb/rs6000-tdep.c gdb/ser-tcp.c gdb/sh-tdep.c gdb/sh-tdep.h gdb/sh3-rom.c gdb/shnbsd-tdep.c gdb/testsuite/ChangeLog gdb/testsuite/configure gdb/testsuite/configure.in gdb/testsuite/gdb.arch/Makefile.in gdb/testsuite/gdb.arch/altivec-abi.c gdb/testsuite/gdb.arch/altivec-abi.exp gdb/testsuite/gdb.arch/altivec-regs.c gdb/testsuite/gdb.arch/altivec-regs.exp gdb/testsuite/gdb.arch/configure gdb/testsuite/gdb.arch/configure.in gdb/testsuite/gdb.base/all-bin.exp gdb/testsuite/gdb.base/call-rt-st.exp gdb/testsuite/gdb.base/completion.exp gdb/testsuite/gdb.c++/inherit.exp gdb/testsuite/gdb.c++/local.exp gdb/testsuite/gdb.c++/m-data.cc gdb/testsuite/gdb.c++/m-data.exp gdb/testsuite/gdb.c++/try_catch.cc gdb/testsuite/gdb.c++/try_catch.exp gdb/testsuite/lib/gdb.exp gdb/v850-tdep.c gdb/version.in gdb/x86-64-tdep.c include/ChangeLog include/bfdlink.h include/dis-asm.h include/elf/ChangeLog include/elf/common.h include/elf/dlx.h include/elf/i386.h include/elf/ia64.h include/gdb/ChangeLog include/gdb/sim-d10v.h include/opcode/ChangeLog include/opcode/dlx.h include/opcode/h8300.h include/opcode/ia64.h include/opcode/mips.h include/opcode/sparc.h libiberty/ChangeLog libiberty/config.table opcodes/ChangeLog opcodes/Makefile.am opcodes/Makefile.in opcodes/acinclude.m4 opcodes/aclocal.m4 opcodes/arc-dis.c opcodes/arm-dis.c opcodes/configure opcodes/configure.in opcodes/disassemble.c opcodes/dlx-dis.c opcodes/fr30-asm.c opcodes/fr30-desc.c opcodes/fr30-dis.c opcodes/m32r-asm.c opcodes/m32r-desc.c opcodes/m32r-dis.c opcodes/m68k-dis.c opcodes/mips-dis.c opcodes/mips-opc.c opcodes/openrisc-asm.c opcodes/openrisc-desc.c opcodes/openrisc-dis.c opcodes/sh-dis.c opcodes/sh64-dis.c opcodes/xstormy16-asm.c opcodes/xstormy16-desc.c opcodes/xstormy16-dis.c sim/ChangeLog sim/MAINTAINERS sim/arm/ChangeLog sim/arm/Makefile.in sim/arm/armcopro.c sim/arm/armemu.c sim/arm/armos.c sim/arm/armsupp.c sim/arm/armvirt.c sim/arm/dbg_rdi.h sim/arm/thumbemu.c sim/arm/wrapper.c sim/common/ChangeLog sim/common/run-sim.h sim/common/run.c sim/common/sim-options.c sim/d10v/ChangeLog sim/d10v/Makefile.in sim/d10v/interp.c sim/d10v/simops.c sim/h8300/ChangeLog sim/h8300/compile.c sim/h8300/inst.h --- opcodes/ChangeLog | 2776 +++++++++++++++++ opcodes/ChangeLog-9297 | 3797 +++++++++++++++++++++++ opcodes/ChangeLog-9899 | 1669 +++++++++++ opcodes/MAINTAINERS | 1 + opcodes/Makefile.am | 697 +++++ opcodes/Makefile.in | 1197 ++++++++ opcodes/a29k-dis.c | 367 +++ opcodes/acinclude.m4 | 24 + opcodes/aclocal.m4 | 185 ++ opcodes/alpha-dis.c | 209 ++ opcodes/alpha-opc.c | 1554 ++++++++++ opcodes/arc-dis.c | 1246 ++++++++ opcodes/arc-dis.h | 81 + opcodes/arc-ext.c | 260 ++ opcodes/arc-ext.h | 62 + opcodes/arc-opc.c | 1818 ++++++++++++ opcodes/arm-dis.c | 1203 ++++++++ opcodes/arm-opc.h | 518 ++++ opcodes/avr-dis.c | 359 +++ opcodes/cgen-asm.c | 373 +++ opcodes/cgen-asm.in | 455 +++ opcodes/cgen-dis.c | 249 ++ opcodes/cgen-dis.in | 466 +++ opcodes/cgen-ibld.in | 540 ++++ opcodes/cgen-opc.c | 650 ++++ opcodes/cgen.sh | 154 + opcodes/config.in | 141 + opcodes/configure | 5133 ++++++++++++++++++++++++++++++++ opcodes/configure.in | 282 ++ opcodes/cris-dis.c | 1406 +++++++++ opcodes/cris-opc.c | 885 ++++++ opcodes/d10v-dis.c | 303 ++ opcodes/d10v-opc.c | 349 +++ opcodes/d30v-dis.c | 407 +++ opcodes/d30v-opc.c | 513 ++++ opcodes/dep-in.sed | 22 + opcodes/dis-buf.c | 118 + opcodes/disassemble.c | 354 +++ opcodes/dlx-dis.c | 544 ++++ opcodes/fr30-asm.c | 751 +++++ opcodes/fr30-desc.c | 1789 +++++++++++ opcodes/fr30-desc.h | 273 ++ opcodes/fr30-dis.c | 747 +++++ opcodes/fr30-ibld.c | 1493 ++++++++++ opcodes/fr30-opc.c | 1397 +++++++++ opcodes/fr30-opc.h | 151 + opcodes/h8300-dis.c | 435 +++ opcodes/h8500-dis.c | 352 +++ opcodes/h8500-opc.h | 3858 ++++++++++++++++++++++++ opcodes/hppa-dis.c | 1201 ++++++++ opcodes/i370-dis.c | 166 ++ opcodes/i370-opc.c | 959 ++++++ opcodes/i386-dis.c | 4144 ++++++++++++++++++++++++++ opcodes/i860-dis.c | 288 ++ opcodes/i960-dis.c | 956 ++++++ opcodes/ia64-asmtab.c | 7436 ++++++++++++++++++++++++++++++++++++++++++++++ opcodes/ia64-asmtab.h | 148 + opcodes/ia64-dis.c | 273 ++ opcodes/ia64-gen.c | 2789 +++++++++++++++++ opcodes/ia64-ic.tbl | 234 ++ opcodes/ia64-opc-a.c | 412 +++ opcodes/ia64-opc-b.c | 489 +++ opcodes/ia64-opc-d.c | 14 + opcodes/ia64-opc-f.c | 646 ++++ opcodes/ia64-opc-i.c | 296 ++ opcodes/ia64-opc-m.c | 1060 +++++++ opcodes/ia64-opc-x.c | 178 ++ opcodes/ia64-opc.c | 762 +++++ opcodes/ia64-opc.h | 130 + opcodes/ia64-raw.tbl | 174 ++ opcodes/ia64-war.tbl | 2 + opcodes/ia64-waw.tbl | 128 + opcodes/m10200-dis.c | 341 +++ opcodes/m10200-opc.c | 360 +++ opcodes/m10300-dis.c | 687 +++++ opcodes/m10300-opc.c | 1427 +++++++++ opcodes/m32r-asm.c | 753 +++++ opcodes/m32r-desc.c | 1483 +++++++++ opcodes/m32r-desc.h | 234 ++ opcodes/m32r-dis.c | 678 +++++ opcodes/m32r-ibld.c | 1198 ++++++++ opcodes/m32r-opc.c | 1714 +++++++++++ opcodes/m32r-opc.h | 132 + opcodes/m32r-opinst.c | 707 +++++ opcodes/m68hc11-dis.c | 640 ++++ opcodes/m68hc11-opc.c | 1074 +++++++ opcodes/m68k-dis.c | 1327 +++++++++ opcodes/m68k-opc.c | 2211 ++++++++++++++ opcodes/m88k-dis.c | 294 ++ opcodes/makefile.vms | 42 + opcodes/mcore-dis.c | 275 ++ opcodes/mcore-opc.h | 209 ++ opcodes/mips-dis.c | 1166 ++++++++ opcodes/mips-opc.c | 955 ++++++ opcodes/mips16-opc.c | 227 ++ opcodes/mmix-dis.c | 523 ++++ opcodes/mmix-opc.c | 340 +++ opcodes/mpw-config.in | 27 + opcodes/mpw-make.sed | 25 + opcodes/ns32k-dis.c | 904 ++++++ opcodes/openrisc-asm.c | 672 +++++ opcodes/openrisc-desc.c | 1059 +++++++ opcodes/openrisc-desc.h | 250 ++ opcodes/openrisc-dis.c | 565 ++++ opcodes/openrisc-ibld.c | 1023 +++++++ opcodes/openrisc-opc.c | 707 +++++ opcodes/openrisc-opc.h | 113 + opcodes/opintl.h | 42 + opcodes/or32-dis.c | 348 +++ opcodes/or32-opc.c | 1052 +++++++ opcodes/pdp11-dis.c | 394 +++ opcodes/pdp11-opc.c | 272 ++ opcodes/pj-dis.c | 181 ++ opcodes/pj-opc.c | 536 ++++ opcodes/po/.cvsignore | 1 + opcodes/po/Make-in | 251 ++ opcodes/po/POTFILES.in | 119 + opcodes/po/da.po | 400 +++ opcodes/po/de.po | 391 +++ opcodes/po/es.po | 399 +++ opcodes/po/fr.po | 398 +++ opcodes/po/id.po | 395 +++ opcodes/po/opcodes.pot | 427 +++ opcodes/po/sv.po | 438 +++ opcodes/po/tr.po | 397 +++ opcodes/ppc-dis.c | 273 ++ opcodes/ppc-opc.c | 4066 +++++++++++++++++++++++++ opcodes/s390-dis.c | 257 ++ opcodes/s390-mkopc.c | 190 ++ opcodes/s390-opc.c | 318 ++ opcodes/s390-opc.txt | 626 ++++ opcodes/sh-dis.c | 734 +++++ opcodes/sh-opc.h | 842 ++++++ opcodes/sh64-dis.c | 638 ++++ opcodes/sh64-opc.c | 774 +++++ opcodes/sh64-opc.h | 139 + opcodes/sparc-dis.c | 983 ++++++ opcodes/sparc-opc.c | 2056 +++++++++++++ opcodes/stamp-h.in | 1 + opcodes/sysdep.h | 42 + opcodes/tic30-dis.c | 710 +++++ opcodes/tic54x-dis.c | 598 ++++ opcodes/tic54x-opc.c | 494 +++ opcodes/tic80-dis.c | 387 +++ opcodes/tic80-opc.c | 1216 ++++++++ opcodes/v850-dis.c | 384 +++ opcodes/v850-opc.c | 813 +++++ opcodes/vax-dis.c | 339 +++ opcodes/w65-dis.c | 121 + opcodes/w65-opc.h | 569 ++++ opcodes/xstormy16-asm.c | 659 ++++ opcodes/xstormy16-desc.c | 1500 ++++++++++ opcodes/xstormy16-desc.h | 292 ++ opcodes/xstormy16-dis.c | 598 ++++ opcodes/xstormy16-ibld.c | 1246 ++++++++ opcodes/xstormy16-opc.c | 1177 ++++++++ opcodes/xstormy16-opc.h | 137 + opcodes/z8k-dis.c | 600 ++++ opcodes/z8k-opc.h | 4481 ++++++++++++++++++++++++++++ opcodes/z8kgen.c | 1330 +++++++++ 160 files changed, 125871 insertions(+) create mode 100644 opcodes/ChangeLog create mode 100644 opcodes/ChangeLog-9297 create mode 100644 opcodes/ChangeLog-9899 create mode 100644 opcodes/MAINTAINERS create mode 100644 opcodes/Makefile.am create mode 100644 opcodes/Makefile.in create mode 100644 opcodes/a29k-dis.c create mode 100644 opcodes/acinclude.m4 create mode 100644 opcodes/aclocal.m4 create mode 100644 opcodes/alpha-dis.c create mode 100644 opcodes/alpha-opc.c create mode 100644 opcodes/arc-dis.c create mode 100644 opcodes/arc-dis.h create mode 100644 opcodes/arc-ext.c create mode 100644 opcodes/arc-ext.h create mode 100644 opcodes/arc-opc.c create mode 100644 opcodes/arm-dis.c create mode 100644 opcodes/arm-opc.h create mode 100644 opcodes/avr-dis.c create mode 100644 opcodes/cgen-asm.c create mode 100644 opcodes/cgen-asm.in create mode 100644 opcodes/cgen-dis.c create mode 100644 opcodes/cgen-dis.in create mode 100644 opcodes/cgen-ibld.in create mode 100644 opcodes/cgen-opc.c create mode 100644 opcodes/cgen.sh create mode 100644 opcodes/config.in create mode 100755 opcodes/configure create mode 100644 opcodes/configure.in create mode 100644 opcodes/cris-dis.c create mode 100644 opcodes/cris-opc.c create mode 100644 opcodes/d10v-dis.c create mode 100644 opcodes/d10v-opc.c create mode 100644 opcodes/d30v-dis.c create mode 100644 opcodes/d30v-opc.c create mode 100644 opcodes/dep-in.sed create mode 100644 opcodes/dis-buf.c create mode 100644 opcodes/disassemble.c create mode 100644 opcodes/dlx-dis.c create mode 100644 opcodes/fr30-asm.c create mode 100644 opcodes/fr30-desc.c create mode 100644 opcodes/fr30-desc.h create mode 100644 opcodes/fr30-dis.c create mode 100644 opcodes/fr30-ibld.c create mode 100644 opcodes/fr30-opc.c create mode 100644 opcodes/fr30-opc.h create mode 100644 opcodes/h8300-dis.c create mode 100644 opcodes/h8500-dis.c create mode 100644 opcodes/h8500-opc.h create mode 100644 opcodes/hppa-dis.c create mode 100644 opcodes/i370-dis.c create mode 100644 opcodes/i370-opc.c create mode 100644 opcodes/i386-dis.c create mode 100644 opcodes/i860-dis.c create mode 100644 opcodes/i960-dis.c create mode 100644 opcodes/ia64-asmtab.c create mode 100644 opcodes/ia64-asmtab.h create mode 100644 opcodes/ia64-dis.c create mode 100644 opcodes/ia64-gen.c create mode 100644 opcodes/ia64-ic.tbl create mode 100644 opcodes/ia64-opc-a.c create mode 100644 opcodes/ia64-opc-b.c create mode 100644 opcodes/ia64-opc-d.c create mode 100644 opcodes/ia64-opc-f.c create mode 100644 opcodes/ia64-opc-i.c create mode 100644 opcodes/ia64-opc-m.c create mode 100644 opcodes/ia64-opc-x.c create mode 100644 opcodes/ia64-opc.c create mode 100644 opcodes/ia64-opc.h create mode 100644 opcodes/ia64-raw.tbl create mode 100644 opcodes/ia64-war.tbl create mode 100644 opcodes/ia64-waw.tbl create mode 100644 opcodes/m10200-dis.c create mode 100644 opcodes/m10200-opc.c create mode 100644 opcodes/m10300-dis.c create mode 100644 opcodes/m10300-opc.c create mode 100644 opcodes/m32r-asm.c create mode 100644 opcodes/m32r-desc.c create mode 100644 opcodes/m32r-desc.h create mode 100644 opcodes/m32r-dis.c create mode 100644 opcodes/m32r-ibld.c create mode 100644 opcodes/m32r-opc.c create mode 100644 opcodes/m32r-opc.h create mode 100644 opcodes/m32r-opinst.c create mode 100644 opcodes/m68hc11-dis.c create mode 100644 opcodes/m68hc11-opc.c create mode 100644 opcodes/m68k-dis.c create mode 100644 opcodes/m68k-opc.c create mode 100644 opcodes/m88k-dis.c create mode 100644 opcodes/makefile.vms create mode 100644 opcodes/mcore-dis.c create mode 100644 opcodes/mcore-opc.h create mode 100644 opcodes/mips-dis.c create mode 100644 opcodes/mips-opc.c create mode 100644 opcodes/mips16-opc.c create mode 100644 opcodes/mmix-dis.c create mode 100644 opcodes/mmix-opc.c create mode 100644 opcodes/mpw-config.in create mode 100644 opcodes/mpw-make.sed create mode 100644 opcodes/ns32k-dis.c create mode 100644 opcodes/openrisc-asm.c create mode 100644 opcodes/openrisc-desc.c create mode 100644 opcodes/openrisc-desc.h create mode 100644 opcodes/openrisc-dis.c create mode 100644 opcodes/openrisc-ibld.c create mode 100644 opcodes/openrisc-opc.c create mode 100644 opcodes/openrisc-opc.h create mode 100644 opcodes/opintl.h create mode 100644 opcodes/or32-dis.c create mode 100644 opcodes/or32-opc.c create mode 100644 opcodes/pdp11-dis.c create mode 100644 opcodes/pdp11-opc.c create mode 100644 opcodes/pj-dis.c create mode 100644 opcodes/pj-opc.c create mode 100644 opcodes/po/.cvsignore create mode 100644 opcodes/po/Make-in create mode 100644 opcodes/po/POTFILES.in create mode 100644 opcodes/po/da.po create mode 100644 opcodes/po/de.po create mode 100644 opcodes/po/es.po create mode 100644 opcodes/po/fr.po create mode 100644 opcodes/po/id.po create mode 100644 opcodes/po/opcodes.pot create mode 100644 opcodes/po/sv.po create mode 100644 opcodes/po/tr.po create mode 100644 opcodes/ppc-dis.c create mode 100644 opcodes/ppc-opc.c create mode 100644 opcodes/s390-dis.c create mode 100644 opcodes/s390-mkopc.c create mode 100644 opcodes/s390-opc.c create mode 100644 opcodes/s390-opc.txt create mode 100644 opcodes/sh-dis.c create mode 100644 opcodes/sh-opc.h create mode 100644 opcodes/sh64-dis.c create mode 100644 opcodes/sh64-opc.c create mode 100644 opcodes/sh64-opc.h create mode 100644 opcodes/sparc-dis.c create mode 100644 opcodes/sparc-opc.c create mode 100644 opcodes/stamp-h.in create mode 100644 opcodes/sysdep.h create mode 100644 opcodes/tic30-dis.c create mode 100644 opcodes/tic54x-dis.c create mode 100644 opcodes/tic54x-opc.c create mode 100644 opcodes/tic80-dis.c create mode 100644 opcodes/tic80-opc.c create mode 100644 opcodes/v850-dis.c create mode 100644 opcodes/v850-opc.c create mode 100644 opcodes/vax-dis.c create mode 100644 opcodes/w65-dis.c create mode 100644 opcodes/w65-opc.h create mode 100644 opcodes/xstormy16-asm.c create mode 100644 opcodes/xstormy16-desc.c create mode 100644 opcodes/xstormy16-desc.h create mode 100644 opcodes/xstormy16-dis.c create mode 100644 opcodes/xstormy16-ibld.c create mode 100644 opcodes/xstormy16-opc.c create mode 100644 opcodes/xstormy16-opc.h create mode 100644 opcodes/z8k-dis.c create mode 100644 opcodes/z8k-opc.h create mode 100644 opcodes/z8kgen.c (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog new file mode 100644 index 0000000..2c5816b --- /dev/null +++ b/opcodes/ChangeLog @@ -0,0 +1,2776 @@ +2002-05-28 Kuang Hwa Lin + + * configure.in: Add DLX configuraton support. + * configure: Regenerate. + * Makefile.am: Add DLX configuraton support. + * Makefile.in: Regenerate. + * disassemble.c: Add DLX support. + * dlx-dis.c: New file. + +2002-05-25 Alan Modra + + * Makefile.am (sh-dis.lo): Don't put make commands in deps. + * Makefile.in: Regenerate. + * arc-dis.c: Use #include "" instead of <> for local header files. + * m68k-dis.c: Likewise. + +Wed May 22 20:11:51 2002 J"orn Rennecke + + * Makefile.am (sh-dis.lo): Compile with @archdefs@. + * Makefile.in: regenerate. + + * sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 + for disassembly. + +2002-05-22 Thiemo Seufer + + * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. + +Fri May 17 14:26:44 2002 J"orn Rennecke + + * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. + * sh-dis.c (LITTLE_BIT): Delete. + (print_insn_sh, print_insn_shl): Deleted. + (print_insn_shx): Renamed to + (print_insn_sh). No longer static. Handle SHmedia instructions. + Use info->endian to determine endianness. + * sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete. + (print_insn_sh64x): No longer static. Renamed to + (print_insn_sh64). Removed pfun_compact and endian arguments. + If we got an uneven address to indicate SHmedia, adjust it. + Return -2 for SHcompact instructions. + +2002-05-17 Alan Modra + + * acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools. + * configure.in: Invoke AM_INSTALL_LIBBFD. + * Makefile.am (install-data-local): Move to.. + (install_libopcodes): .. New target. + (uninstall_libopcodes): Likewise. + (install-bfdlibLTLIBRARIES): Likewise. + (uninstall-bfdlibLTLIBRARIES): Likewise. + (bfdlibdir): New. + (bfdincludedir): New. + (lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * Makefile.in: Regenerate. + +2002-05-15 Nick Clifton + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Regenerate. + * xstormy16-dis.c: Regenerate. + +2002-05-15 Thiemo Seufer + + * mips-dis.c (is_newabi): EABI is not a NewABI. + +2002-05-13 Jason Thorpe + + * configure.in (shle-*-*elf*): Include sh64 support. + * configure: Regenerate. + +2002-04-28 Jason Thorpe + + * vax-dis.c (print_insn_arg): Pass the insn info to print_insn_mode. + (print_insn_mode): Print some basic info about floating point values. + +2002-05-09 Anton Blanchard + + * ppc-opc.c: Add "tlbiel" for POWER4. + +2002-05-07 Graydon Hoare + + * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather + than just most-recently-opened. + +2002-05-01 Alan Modra + + * ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke. + +2002-04-24 Christian Groessler + + * z8k-dis.c (print_insn_z8k): Set disassemble_info to 2 + bytes_per_chunk, 6 bytes_per_line for nicer display of the hex + codes. + (z8k_lookup_instr): CLASS_IGNORE case added. + (output_instr): Don't print hex codes, they are already + printed. + (unpack_instr): ARG_NIM4 case added. ARG_NIM8 case + fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases. + (unparse_instr): Fix base and indexed addressing disassembly: + The index is inside the brackets. + * z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines. + (opt): Fix shift left/right arithmetic/logical byte defines: + The high byte of the immediate word is ignored by the + processor. + Fix n parameter of ldm opcodes: The opcode contains (n-1). + (args): Fix "n" entry. + (toks): Add "nim4" and "iiii" entries. + * z8k-opc.h: Regenerated with new z8kgen.c. + +2002-04-24 Nick Clifton + + * po/id.po: New Indonesian translation. + * configure.in (ALL_LIGUAS): Add id.po + * configure: Regenerate. + +2002-04-17 matthew green + + * ppc-opc.c (powerpc_opcode): Fix dssall operand list. + +2002-04-04 Alan Modra + + * dep-in.sed: Cope with absolute paths. + * Makefile.am (dep.sed): Subst TOPDIR. + Run "make dep-am". + * Makefile.in: Regenerate. + * ppc-opc.c: Whitespace. + * s390-dis.c: Fix copyright date. + +2002-03-23 matthew green + + * ppc-opc.c (vmaddfp): Fix operand order. + +2002-03-21 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2002-03-21 Anton Blanchard + + * ppc-opc.c: Add optional field to mtmsrd. + (MTMSRD_L, XRLARB_MASK): Define. + +Mon Mar 18 21:10:43 CET 2002 Jan Hubicka + + * i386-dis.c (prefix_name): Fix handling of 32bit address prefix + in 64bit mode. + (print_insn) Likewise. + (putop): Fix handling of 'E' + (OP_E, OP_OFF): handle 32bit addressing mode in 64bit. + (ptr_reg): Likewise. + +2002-03-18 Nick Clifton + + * po/fr.po: Updated version. + +2002-03-16 Chris Demetriou + + * mips-opc.c (M3D): Tweak comment. + (mips_builtin_op): Add comment indicating that opcodes of the + same name must be placed together in the table, and sort + the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", + "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name. + +2002-03-16 Nick Clifton + + * Makefile.am: Tidy up sh64 rules. + * Makefile.in: Regenerate. + +2002-03-15 Chris G. Demetriou + + * mips-dis.c: Update copyright years. + +2002-03-15 Chris G. Demetriou + + * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA + bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add + comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that + indicate that they should dissassemble all applicable + MIPS-specified ASEs. + * mips-opc.c: Add support for MIPS-3D instructions. + (M3D): New definition. + + * mips-opc.c: Update copyright years. + +2002-03-15 Chris G. Demetriou + + * mips-opc.c (mips_builtin_opcodes): Sort bc opcodes by name. + +2002-03-15 Chris Demetriou + + * mips-dis.c (is_newabi): Fix ABI decoding. + +2002-03-14 Chris G. Demetriou + + * mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32 + and bfd_mach_mipsisa64 cases to match the rest. + +2002-03-13 Nick Clifton + + * po/fr.po: Updated version. + +2002-03-13 Alan Modra + + * ppc-opc.c: Add optional `L' field to tlbie. + (XRTLRA_MASK): Define. + +2002-03-06 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Mark "pref" as being + present on I4. + + * mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps". + +2002-03-05 Paul Koning + + * pdp11-opc.c: Fix "mark" operand type. Fix operand types + for float opcodes that take float operands. Add alternate + names (xxxD vs. xxxF) for float opcodes. + * pdp11-dis.c (print_operand): Clean up formatting for mode 67. + (print_foperand): New function to handle float opcode operands. + (print_insn_pdp11): Use print_foperand to disassemble float ops. + +2002-02-27 Nick Clifton + + * po/de.po: Updated. + +2002-02-26 Brian Gaeke + + * Makefile.am (install-data-local): Install dis-asm.h. + +2002-02-26 Nick Clifton + + * configure.in (LINGUAS): Add de.po. + * configure: Regenerate. + * po/de.po: New file. + +2002-02-25 Alan Modra + + * ppc-dis.c (powerpc_dialect): Handle power4 option. + * ppc-opc.c (insert_bdm): Correct description of "at" branch + hints. Test PPC_OPCODE_POWER4 to determine branch hint flavour. + (extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise. + (BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise. + (PPCCOM32, PPCCOM64): Delete. + (NOPOWER4, POWER4): Define. + (powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4, + and PPCCOM4 with POWER4 so that "at" style branch hint opcodes + are enabled for power4 rather than ppc64. + +2002-02-20 Tom Rix + + * ppc-opc.c (powerpc_operands): Add WS feild. Use for tlbre, tlbwe. + +2002-02-19 Martin Schwidefsky + + * s390-dis.c (init_disasm): Use renamed architecture defines. + +2002-02-19 matthew green + + * ppc-opc.c (powerpc_dialect): Fix comment; BookE is not Motorola + specific. + +2002-02-18 Nick Clifton + + * po/tr.po: Updated translation. + +2002-02-15 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Fix thinko in ret pseudo + disassembly mask. + +2002-02-15 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Add simple pseudos for + lda, ldah, jmp, ret. + +2002-02-14 Nick Clifton + + * po/da.po: Updated translation. + +2002-02-12 Graydon Hoare + + * cgen-asm.in (parse_insn_normal): Change call from + @arch@_cgen_parse_operand to cd->parse_operand, to + facilitate CGEN_ASM_INIT_HOOK doing useful work. + +2002-02-11 Alexandre Oliva + + * sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not + sign-extended. + +2002-02-11 Alan Modra + + * Makefile.am: "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + +2002-02-10 Hans-Peter Nilsson + + * configure.in : For sh-* and shl-*, enable sh64 + support only for sh-*-*elf*, shl-*-*elf*, sh-*-linux* and + shl-*-linux*. + * configure: Regenerate. + +2002-02-10 Daniel Jacobowitz + + * cgen-dis.c: Add prototypes for count_decodable_bits + and add_insn_to_hash_chain. + +2002-02-08 Alexandre Oliva + + * configure.in : Enable sh64 support on sh-*. + * configure: Rebuilt. + +2002-02-08 Ivan Guzvinec + + * or32-opc.c: Fix compile time warning messages. + * or32-dis.c: Fix compile time warning messages. + +2002-02-08 Alexandre Oliva + + Contribute sh64-elf. + 2001-10-08 Nick Clifton + * sh64-opc.c: Regenerate. + 2001-03-13 DJ Delorie + * sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its + purpose is more obvious. + * sh64-opc.c (shmedia_table): Ditto. + * sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto. + (print_insn_shmedia): Ditto. + 2001-03-12 DJ Delorie + * sh64-opc.c: Adjust comments to reflect reality: replace bits + 3:0 with zeros (not "reserved"), replace "rrrrrr" with + "gggggg" for two-operand floating point opcodes. Remove + "fsina". + 2001-01-08 Hans-Peter Nilsson + * sh64-dis.c (print_insn_shmedia) : + Correct printing of .byte:s. Return number of printed bytes or + -1; never 0. + (print_insn_sh64x) : Ditto. Print as .byte:s + to next four-byte-alignment if insn or data is not aligned. + 2001-01-06 Hans-Peter Nilsson + * sh64-dis.c: Update comments and fix comment formatting. + (initialize_shmedia_opcode_mask_table) : + Abort instead of setting length to 0. + (crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb, + crange_bsearch_cmpl, sh64_get_contents_type, + sh64_address_in_cranges): Move to bfd/elf32-sh64.c. + 2001-01-05 Hans-Peter Nilsson + * sh64-opc.c: Remove #if 0:d entries for instructions not found in + SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo. + 2000-12-30 Hans-Peter Nilsson + * sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed + address with same prefix as SHcompact. + In the disassembler, use a .cranges section for linked executables. + * sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file + and update for using structure in info->private_data. + (struct sh64_disassemble_info): New. + (is_shmedia_p): Delete. + (crange_qsort_cmpb): New function. + (crange_qsort_cmpl, crange_bsearch_cmpb): New functions. + (crange_bsearch_cmpl, sh64_address_in_cranges): New functions. + (init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions. + (sh64_get_contents_type, sh64_address_is_shmedia): New functions. + (print_insn_shmedia): Correct displaying of address after MOVI/SHORI + pair. Display addresses for linked executables only. + (print_insn_sh64x_media): Initialize info->private_data by calling + init_sh64_disasm_info. + (print_insn_sh64x): Ditto. Find out type of contents by calling + sh64_contents_type_disasm. Display data regions using ".long" and + ".byte" similar to unrecognized opcodes. + 2000-12-19 Hans-Peter Nilsson + * sh64-dis.c (is_shmedia_p): Check info->section and look for ISA + information in section flags before considering symbols. Don't + assume an info->mach setting of bfd_mach_sh5 means SHmedia code. + * configure.in (bfd_sh_arch): Check presence of sh64 insns by + matching $target $canon_targets instead of looking at the + now-removed -DINCLUDE_SHMEDIA in $targ_cflags. + * configure: Regenerate. + 2000-11-25 Hans-Peter Nilsson + * sh64-opc.c (shmedia_creg_table): New. + * sh64-opc.h (shmedia_creg_info): New type. + (shmedia_creg_table): Declare. + * sh64-dis.c (creg_name): New function. + (print_insn_shmedia): Use it. + * disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map + bfd_mach_sh5 to print_insn_sh64 if big-endian and to + print_insn_sh64l if little-endian. + * sh64-dis.c (print_insn_shmedia): Make r unsigned. + (print_insn_sh64l): New. + (print_insn_sh64x): New. + (print_insn_sh64x_media): New. + (print_insn_sh64): Break out code to print_insn_sh64x and + print_insn_sh64x_media. + 2000-11-24 Hans-Peter Nilsson + * sh64-opc.h: New file + * sh64-opc.c: New file + * sh64-dis.c: New file + * Makefile.am: Add sh64 targets. + (HFILES): Add sh64-opc.h. + (CFILES): Add sh64-opc.c and sh64-dis.c. + (ALL_MACHINES): Add sh64 files. + * Makefile.in: Regenerate. + * configure.in: Add support for sh64 to bfd_sh_arch. + * configure: Regenerate. + * disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define. + (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to + print_insn_sh64. + * sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2002-02-04 Frank Ch. Eigler + + * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. + +2002-02-04 Alexandre Oliva + + * sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS. + +2002-02-01 Alan Modra + + * Makefile.am: Run "make dep-am" + * Makefile.in: Regenerate. + +2002-01-31 Ivan Guzvinec + + * or32-dis.c: New file. + * or32-opc.c: New file. + * configure.in: Add support for or32. + * configure: Regenerate. + * Makefile.am: Add support for or32. + * Makefile.in: Regenerate. + * disassemble.c: Add support for or32. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2002-01-27 Daniel Jacobowitz + + * configure: Regenerated. + +2002-01-26 Nick Clifton + + * po/fr.po: Updated version. + +2002-01-25 Nick Clifton + + * po/es.po: Updated version. + +2002-01-24 Nick Clifton + + * po/da.po: New version. + +2002-01-23 Nick Clifton + + * po/da.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add da. + * configure: Regenerate. + +2002-01-22 Graydon Hoare + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Likewise. + * fr30-desc.h: Likewise. + * fr30-dis.c: Likewise. + * fr30-ibld.c: Likewise. + * fr30-opc.c: Likewise. + * fr30-opc.h: Likewise. + * m32r-asm.c: Likewise. + * m32r-desc.c: Likewise. + * m32r-desc.h: Likewise. + * m32r-dis.c: Likewise. + * m32r-ibld.c: Likewise. + * m32r-opc.c: Likewise. + * m32r-opc.h: Likewise. + * m32r-opinst.c: Likewise. + * openrisc-asm.c: Likewise. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + * xstormy16-desc.c: Likewise. + +2002-01-22 Richard Henderson + + * alpha-dis.c (print_insn_alpha): Also mask the base opcode for + comparison. + +2002-01-22 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * opcodes/po/POTFILES.in: Regenerate. + +2002-01-19 Richard Earnshaw + + * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. + * arm-dis.c (print_insn_arm): Don't handle 'h' case. + +2002-01-18 Keith Walker + + * arm-opc.h (arm_opcodes): Add bxj instruction. + +2002-01-17 Nick Clifton + + * po/opcodes.pot: Regenerate. + * po/fr.po: Regenerate. + * po/sv.po: Regenerate. + * po/tr.po: Regenerate. + +2002-01-16 Nick Clifton + + * po/tr.po: Import new version. + +2002-01-15 Richard Earnshaw + + * arm-opc.h (arm_opcodes): Add patterns for VFP instructions. + * arm-dis.c (print_insn_arm): Support new disassembly qualifiers for + VFP bitfields. + +2002-01-10 matthew green + + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Likewise. + * xstormy16-desc.h: Likewise. + * xstormy16-dis.c: Likewise. + * xstormy16-opc.c: Likewise. + * xstormy16-opc.h: Likewise. + +2002-01-07 Nick Clifton + + * po/es.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add es. + * configure: Regenerate. + +2001-12-31 Jeffrey A Law (law@redhat.com) + + * hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers, + 'X', 'M', and 'A'. No longer emit a space after 'x' or 's'. + Always emit a space after 'H'. + +2001-12-18 matthew green + + * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY. + +2001-12-17 Richard Henderson + + * alpha-opc.c (unop): Encode with RB as $sp. + +2001-12-07 Geoffrey Keating + + * Makefile.am: Add support for xstormy16. + * Makefile.in: Regenerate. + * configure.in: Add support for xstormy16. + * configure: Regenerate. + * disassemble.c: Add support for xstormy16. + * xstormy16-asm.c: New generated file. + * xstormy16-desc.c: New generated file. + * xstormy16-desc.h: New generated file. + * xstormy16-dis.c: New generated file. + * xstormy16-ibld.c: New generated file. + * xstormy16-opc.c: New generated file. + * xstormy16-opc.h: New generated file. + +2001-12-06 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Add wh64en. + +2001-12-04 Alexandre Oliva + + * d10v-opc.c (d10v_predefined_registers): Remove warnings + introduced in Nov 29's patch. + + * d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of + unmatched register. + + * d10v-dis.c (print_operand): Disregard OPERAND_SP in register + predefined value. + + * d10v-opc.c (RSRC_NOSP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". + +2001-11-29 Alexandre Oliva + + * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. + (RSRC_SP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. + +2001-11-23 Lars Brinkhoff + + * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. + Also, break out of the loop as soon as an instruction has been + printed. + +2001-11-17 matthew green + + * ppc-opc.c (mfvrsave, mtvrsave): New instructions. + +2001-11-15 Alan Modra + + * po/POTFILES.in: Regenerate. + + * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. + (insert_bat, extract_bat, insert_bba, extract_bba, + insert_bd, extract_bd, insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo, + insert_bo, extract_bo, insert_boe, extract_boe, + insert_ds, extract_ds, insert_de, extract_de, + insert_des, extract_des, insert_li, extract_li, + insert_mbe, extract_mbe, insert_mb6, extract_mb6, + insert_nb, extract_nb, insert_nsi, extract_nsi, + insert_ral, insert_ram, insert_ras, + insert_rbs, extract_rbs, insert_sh6, extract_sh6, + insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. + (extract_bd, extract_bdm, extract_bdp, + extract_ds, extract_des, + extract_li, extract_nsi): Implement sign extension without conditional. + (insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. + (extract_bdm, extract_bdp): Correct 32 bit validation. + (AT1_MASK, AT2_MASK): Define. + (BBOAT_MASK): Define. + (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. + (BOFM64, BOFP64, BOTM64, BOTP64): Define. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. + (PPCCOM32, PPCCOM64): Define. + (powerpc_opcodes): Modify existing 32 bit insns with branch hints + and add new patterns to implement 64 bit branches with hints. Move + booke instructions so they match before ppc64. + + * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for + 64 bit default targets, and parse "32" and "64" in options. + Formatting fixes. + (print_insn_powerpc): Pass dialect to operand->extract. + +2001-11-14 Dave Brolley + + * cgen-dis.c (count_decodable_bits): New function. + (add_insn_to_hash_chain): New function. + (hash_insn_array): Call add_insn_to_hash_chain. + (hash_insn_list): Call add_insn_to_hash_chain. + * m32r-dis.c: Regenerated. + * fr30-dis.c: Regenerated. + +2001-11-14 Andreas Jaeger + + * i386-dis.c (print_insn): Use x86-64 as option. + +2001-11-14 Alan Modra + + * disassemble.c (disassembler): Call print_insn_i386. + * i386-dis.c (SUFFIX_ALWAYS): Define. + (struct dis_private): Add orig_sizeflag. + (print_insn_i386): Make it a wrapper, calling.. + (print_insn): ..The old body of print_insn_i386. Avoid longjmp + warning without using volatile by moving orig_sizeflag to priv, + and removing inbuf. Parse disassembler_options. + (print_insn_i386_att, print_insn_i386_intel): Move initialisation + code to print_insn. + (putop): Remove #ifdef SUFFIX_ALWAYS. + +2001-11-11 Timothy Wall + + * tic54x-dis.c: Use revised opcode structure. Export opcode + template lookup. + (has_lkaddr): Don't forget about Lmem insns. + * tic54x-opc.c: Add emulation trap. Parallel table now uses + standard opcode templates. + +2001-11-13 Zack Weinberg + + * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries + to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand + category instead of Ew. + +2001-11-12 Niraj Gupta + + * m68k-opc.c: Fix definitions of wddata[bwl]. + +2001-11-09 Richard Sandiford + + * cgen-asm.c (cgen_parse_keyword): If the keyword is too big to + fit in the buffer, try to match the empty keyword. + +2001-11-09 Nick Clifton + + * cgen-ibld.in (extract_1): Fix badly placed #if 0. + * fr30-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-ibld.c: Regenerate. + +2001-11-04 Chris Demetriou + + * mips-dis.c (print_insn_mips): Remove spaces at end of line. + +2001-11-02 Nick Clifton + + * configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr". + * configure: Regernate. + * po/fr.po: New file. + * po/sv.po: New file. + * po/tr.po: New file. + +2001-11-01 Stephane Carrez + + * m68hc11-dis.c (print_insn): Fix disassembly of movb with a + constant as source. + +2001-10-30 Hans-Peter Nilsson + + * Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c. Regenerate + dependencies. + * Makefile.in: Regenerate. + * mmix-dis.c, mmix-opc.c: New files. + +2001-10-29 Kazu Hirata + + * d30v-dis.c: Fix a comment typo. + +2001-10-23 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and + "bltzall" as writing GPR 31 (since they do). + + * mips-dis.c (print_insn_arg): Calculate info->target + where appropriate. + (print_insn_mips): Fill in instruction info. + (print_mips16_insn_arg): Remove unneded variable 'val'. + Removed duplicated instruction target calculations, + calculate once and print that result. Use same idiom for + masking the jump segment bits as is used in print_insn_arg. + +2001-10-20 Alan Modra + + * ppc-opc.c (CT): Make it an optional operand. + +2001-10-17 Chris Demetriou + + * mips-dis.c (mips_isa_type): Make the ISA used to disassemble + SB-1 binaries include instructions specific to the SB-1. + * mips-opc.c (SB1): New definition. + (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", + "recip.ps", "rsqrt.ps", and "sqrt.ps". + +2001-10-17 matthew green + + * ppc-opc.c (STRM): New AltiVec operand. + (XDSS): New AltiVec instruction form. + (mtvscr): Correct operand list. + (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. + +2001-10-17 Alan Modra + + * po/POTFILES.in: Regenerate. + +2001-10-13 matthew green + + * ppc-opc.c (MO): New macro for MO field of mbar instruction. + (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr, + mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions. + +2001-10-13 Nick Clifton + + * cgen-ibld.in: Include safe-ctype.h in preference to + ctype.h. + * cgen-asm.in: Include safe-ctype.h in preference to + ctype.h. Fix formatting. Use ISSPACE instead of isspace and + TOLOWER instead of tolower. + (@arch@_cgen_build_insn_regex): Remove duplication of syntax + string elements in constructed regular expression. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-ibld.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-12 matthew green + + * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New + instruction field instruction/extraction functions for new BookE + DE form instructions. + (CT): New macro for CT field in an X form instruction. + (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form + instructions. + (PPC64): Don't include PPC_OPCODE_PPC. + (403): New opcode macro for PPC403 processors. + (BOOKE): New opcode macro for BookE processors. + (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. + (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. + (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. + (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. + (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. + (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. + (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. + (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. + (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. + (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. + (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. + (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. + (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. + (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. + + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look + for a disassembler option of `booke', `booke32' or `booke64' to enable + BookE support in the disassembler. + +2001-10-12 John Healy + + * cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8) + for the length when extracting the base part of the insn. + +2001-10-09 Bruno Haible + + * cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive + regular expression. Fix some formatting problems. + * fr30-asm.c: Regenerate. + * openrisc-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + +2001-10-09 Christian Groessler + + * z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly + of indirect register memory accesses to be same format the + assembler accepts. + +2001-10-09 Nick Clifton + + * sh-opc.h: Fix encoding of least significant nibble of the + DSP single data transfer instructions. + + * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP + instructions. + +2001-10-08 Nick Clifton + + * cgen-asm.in: Fix compile time warning messages in generated + C files. + * cgen-dis.in: The same. + * cgen-ibld.in: The same. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opinst.c Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * openrisc-opc.c: Regenerate. + * openrisc-opc.h: Regenerate. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-08 Aldy Hernandez + + * arm-opc.h (arm_opcodes): Add cirrus insns. + + * arm-dis.c (print_insn_arm): Add 'I' case. + +2001-10-03 Alan Modra + + * po/POTFILES.in: Regenerate. + * configure: Regenerate. + +2001-10-02 Alan Modra + + * Makefile.am (Makefile): Depend on bfd/configure.in. + Run "make dep-am". + * Makefile.in: Regenerate. + +2001-09-30 John Healy + + * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits + calls to cgen_get_insn_value and cgen_put_insn_value calls. + (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call. + +2001-09-30 Hans-Peter Nilsson + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate. + +2001-09-26 Alan Modra + + * arc-dis.c: Formatting fixes. + (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE. + +2001-09-21 Bruno Haible + + * arc-dis.c: Don't include . + * openrisc-desc.c: Likewise. + * openrisc-ibld.c: Likewise. + +2001-09-20 Nick Clifton + + * fr30-opc.c: Fix compile time warning messages. + * i370-opc.c: Fix compile time warning messages. + * i960-dis.c: Fix compile time warning messages. + * m32r-asm.c: Fix compile time warning messages. + * m32r-desc.c: Fix compile time warning messages. + * m32r-dis.c: Fix compile time warning messages. + * m32r-ibld.c: Fix compile time warning messages. + * m32r-opc.c: Fix compile time warning messages. + * m32r-opinst.c: Fix compile time warning messages. + * ns32k-dis.c: Fix compile time warning messages. + * openrisc-asm.c: Fix compile time warning messages. + * openrisc-desc.c: Fix compile time warning messages. + * openrisc-dis.c: Fix compile time warning messages. + * openrisc-ibld.c: Fix compile time warning messages. + * openrisc-opc.c: Fix compile time warning messages. + * pdp11-dis.c: Fix compile time warning messages. + * tic54x-dis.c: Fix compile time warning messages. + * v850-opc.c: Fix compile time warning messages. + * vax-dis.c: Fix compile time warning messages. + * w65-opc.h: Fix compile time warning messages. + * z8k-opc.h: Fix compile time warning messages. + * z8kgen.c: Fix compile time warning messages. + +2001-09-19 Nick Clifton + + * arm-dis.c: Fix compile time warning messages. + * cgen-asm.c: Fix compile time warning messages. + * cgen-dis.c: Fix compile time warning messages. + * cris-dis.c: Fix compile time warning messages. + * d10v-dis.c: Fix compile time warning messages. + * fr30-asm.c: Fix compile time warning messages. + * fr30-desc.c: Fix compile time warning messages. + * fr30-dis.c: Fix compile time warning messages. + * fr30-ibld.c: Fix compile time warning messages. + +2001-09-18 Bruno Haible + + * cgen-asm.c: Include "safe-ctype.h" instead of . + (cgen_parse_keyword): Use ISALNUM instead of isalnum. + * cgen-opc.c: Include "safe-ctype.h" instead of . + (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of + isalpha/tolower. + (cgen_keyword_add): Use ISALNUM instead of isalnum. + (hash_keyword_name): Use TOLOWER instead of tolower. + * fr30-asm.c: Include "safe-ctype.h" instead of . + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace. + * fr30-desc.c: Don't include . + * fr30-ibld.c: Likewise. + * ia64-gen.c: Include "safe-ctype.h" instead of . + (load_insn_classes, parse_resource_users, load_depfile): Use + ISSPACE instead of isspace. + * m32r-asm.c: Include "safe-ctype.h" instead of . + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace. + * m32r-desc.c: Don't include . + * m32r-ibld.c: Likewise. + * openrisc-asm.c: Include "safe-ctype.h" instead of . + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace. + +2001-09-18 Martin Schwidefsky + + * Makefile.am: Add rules and dependencies to create the s/390 opcode + table out of s390-opc.txt automatically. + * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used. + * s390-mkopc.c (dumpTable): Change output to create a complete file. + * s390-opc.c: New improved opcode format macros and remove the + pregenerated opcode table. + * s390-opc.txt: Adapt to new improved opcode format macros. + +2001-09-14 David Schleef + + * ppc-opc.c (VXA, VXA_MASK): Fix mask bits. + +2001-09-04 Alan Modra + + * i386-dis.c (grps): Don't print the implicit al/ax/eax register + for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns. + +2001-08-31 Eric Christopher + Jason Eckhardt + + * mips-dis.c: Add support for bfd_mach_mipsisa32 and + bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, + bfd_mach_mips64. + +2001-08-31 Andreas Jaeger + + * tic54x-opc.c: Add default initializers to avoid warnings. + + * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. + * arc-ext.c: Likewise. + +2001-08-28 matthew green + + * ppc-opc.c (icbt): Order correctly. + +2001-08-27 David Edelsohn + Torbjorn Granlund + + * ppc-opc.c (DS): Add PPC_OPERAND_DS flag. + (LS): Define. + (insert_ds): Complain if not a multiple of 4. + (XSYNC): Define. + (XSYNC_MASK): Define. + (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev", + "slbmfee". Modify "sync" to use XSYNC_MASK and LS. + +2001-08-26 Andreas Jaeger + + * h8500-opc.h: Add default initializers to h8500_table to shut up + GCC warnings. + +2001-08-25 Andreas Jaeger + + * tic54x-dis.c: Add unused attributes where needed. + + * z8k-dis.c (output_instr): Add unused attribute. + + * h8300-dis.c: Add missing prototypes. + (bfd_h8_disassemble): Make static. + + * cris-dis.c: Add missing prototype. + * h8500-dis.c: Likewise. + * m68hc11-dis.c: Likewise. + * pj-dis.c: Likewise. + * tic54x-dis.c: Likewise. + * v850-dis.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * z8k-dis.c: Likewise. + + * d10v-dis.c: Add missing prototype. + (dis_long): Remove unused variable. + (dis_2_short): Likewise. + + * sh-dis.c: Add missing prototypes. + * v850-opc.c: Likewise. + Add unused attributes where needed. + + * ns32k-dis.c: Add missing prototypes. + (bit_extract_simple): Remove unused variable. + +2001-08-23 Martin Schwidefsky + + * opcodes/s390-opc.c: Add "low or high" and "not low or high" + branch instructions for gcc 3.0. + * opcodes/s390-opc.txt: Likewise. + +2001-08-21 Andreas Jaeger + + * i960-dis.c: Add parameters for prototypes + (ctrl): Add unused attributes. + (cobr): Likewise. + (put_abs): Likewise. + + * mips-dis.c: Add missing prototypes. + * a29k-dis.c: Likewise. + * arc-dis.c: Likewise. + * ia64-opc.c: Likewise. + + * s390-dis.c: Add missing prototypes. + (init_disasm): Remove unused attribute since the parameter is + used. + +2001-08-16 Thiemo Seufer + + * mips-opc.c (M1): Define. Reformatted Code. + (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps, + mtps, mtps. Typo. + +2001-08-16 Jonathan Larmour + + * mips-opc.c: R3900s can support all branch likely INSN_MACROs where + the corresponding non-likely insn is in MIPS I. + +2001-08-13 Kazu Hirata + + * mcore-dis.c: Fix formatting. + * mips-dis.c: Likewise. + * pj-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-08-12 Richard Henderson + + * cgen-ibld.in (extract_normal): Match type of VALUE and MASK + to *VALUEP. Regenerate all cgen files. + +2001-08-10 Richard Sandiford + + * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 + argument. + * mips-opc.c (G6): Undefine. + (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro + as the first "move" alternative. + +2001-08-10 Andreas Jaeger + + * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes + to build warnings. + * configure: Regenerate. + +2001-08-10 Alan Modra + + * ppc-opc.c: Revert 2001-08-08. + +2001-08-09 Alan Modra + + * dis-buf.c (generic_strcat_address): Add missing prototype. + #if 0 the functions as it is unused. + +2001-08-08 Alan Modra + + 1999-10-25 Torbjorn Granlund + * ppc-opc.c: Include "bfd.h". + (powerpc_operands): Add new field for reloc type. + +2001-07-21 Thiemo Seufer + + * mips-dis.c (print_insn_arg): Don't use software integer registers + for coprocessor registers. + (get_mips_isa): Removed. + (is_newabi): New function, checks if NewABI is used. + (_print_insn_mips): Get distinction between old ABI and new ABI right. + +2001-08-01 Christian Groessler + + * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to + get stderr definition. + (internal, gas): Removed warnings. + (gas): Create a correct final entry for created array. + * z8k-opc.h: Recreated with new z8kgen. + +2001-07-28 Kazu Hirata + + * i386-dis.c: Fix formatting. + +2001-07-28 Matthias Kramm + + * i386-dis.c: Change formatting conventions for architecture + i386:intel to better match the format of various intel i386 + assemblers, like nasm, tasm or masm. + +2001-07-24 Alan Modra + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate + +2001-07-24 Kazu Hirata + + * alpha-dis.c: Fix formatting. + * cris-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d30v-dis.c: Likewise. + * m10300-dis.c: Likewise. + * tic54x-dis.c: Likewise. + +2001-07-23 Kazu Hirata + + * m68k-dis.c: Fix formatting. + * pj-dis.c: Likewise. + * s390-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-07-21 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s + into the rest of the surrounding definitions. + +2001-07-18 Alan Modra + + * i386-dis.c (grps): Print l or w suffix, and require mem modrm + for lgdt, lidt, sgdt, sidt. + +2001-07-13 Philip Blundell + + * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. + +2001-07-12 Jeff Johnston + + * cgen-asm.in: Include "xregex.h" always to enable the libiberty + regex support. + (@arch@_cgen_build_insn_regex): New routine from Graydon. + (@arch@_cgen_assemble_insn): Add Graydon's code to use regex + to verify if it is worth parsing the insn as insn "x". Also update + error message when insn is not a recognized format of the insn vs + when the insn is completely unrecognized. + +2001-07-11 Frank Ch. Eigler + + * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of + bfd_get_bits. + * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect + non-zero CGEN_CPU_DESC->insn_chunk_bitsize. + +2001-07-09 Andreas Jaeger , Karsten Keil + + * i386-dis.c (set_op): Handle 64 bit and 32 bit mode. + (OP_J): Use bfd_vma for mask to work properly with 64 bits. + (op_address,op_riprel): Use bfd_vma to handle 64 bits. + +2001-07-05 Ben Elliston + + * Makefile.am (CPUDIR): Define. + (stamp-m32r): Update dependencies. + (stamp-fr30): Ditto. + (stamp-openrisc): Ditto. + * Makefile.in: Regenerate. + +2001-07-03 Zoltan Hidvegi + + * ppc-opc.c: Fix encoding of 'clf' instruction. + +2001-06-30 Geoffrey Keating + + * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT. + +2001-06-28 Geoffrey Keating + + * cgen-asm.c (cgen_parse_keyword): Allow any first character. + * cgen-opc.c (cgen_keyword_add): Ignore special first + character when building nonalpha_chars field. + +2001-06-24 Ben Elliston + + * m88k-dis.c: Format to conform to GNU coding standards. + +2001-06-23 Andreas Jaeger + + * disassemble.c (disassembler_usage): Add unused attribute. + +2001-06-22 Eric Christopher + + * mips-opc.c: Move prefx to start of the table. + +2001-06-22 Stacey Sheldon + + * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST + instruction. + +2001-06-22 Pauli + + * m68k-opc.c: Add wdebug instruction. + +2001-06-15 Aldy Hernandez + + * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc. + +2001-06-14 Geoffrey Keating + + * cgen-asm.c (cgen_parse_keyword): When looking for the + boundaries of a keyword, allow any special characters + that are actually in one of the allowed keyword. + * cgen-opc.c (cgen_keyword_add): Add any special characters + to the nonalpha_chars field. + +2001-06-12 Martin Schwidefsky + + * s390-opc.c: Add lgh instruction. + * s390-opc.txt: Likewise. + +2001-06-11 Alan Modra + + * i386-dis.c: Group function prototypes in one place. + (FLOATCODE): Redefine as 1. + (USE_GROUPS): Redefine as 2. + (USE_PREFIX_USER_TABLE): Redefine as 3. + (X86_64_SPECIAL): Define as 4. + (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2. + (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE. + (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete. + (dis386): New table combining above four tables. + (dis386_twobyte_att, dis386_twobyte_intel): Delete. + (dis386_twobyte): New table combining above two tables. + (x86_64_table): New table to handle x86_64. + (X86_64_0): Define. + (float_mem_att, float_mem_intel): Delet. + (float_mem): New table combining above two tables. + (print_insn_i386): Modify for above. + (dofloat): Likewise. + (putop): Handle '{', '|' and '}' to select alternative mnemonics. + Return 0 on success, 1 if no valid alternative. + (putop , ): Print nothing for intel_syntax. + (putop ): Move to case 'U', and share case 'Q' code. + (putop ): Move to case 'T', and share case 'P' code. + (OP_REG ): Handle as for eAX_reg .. eDI_reg + if not 64-bit mode. + (OP_I ): Handle as for v_mode if not 64-bit mode. + (OP_I64): If not 64-bit mode, call OP_I. + OP_OFF64): If not 64-bit mode, call OP_OFF. + (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename + 'ignore'/'ignored' to 'bytemode'. + +2001-06-10 Alan Modra + + * configure.in: Sort 'ta' case statement. + * configure: Regenerate. + + * i386-dis.c (dis386_att): Add 'H' to conditional branch and + loop,jcxz insns. + (disx86_64_att): Likewise. + (dis386_twobyte_att): Likewise. + (print_insn_i386): Don't print branch hints as a prefix. + (putop): 'H' macro prints branch hints. + (get64): Kill compile warnings. + +2001-06-09 Alexandre Oliva + + * sh-opc.h (sh_table): Don't use empty initializers. + +2001-06-06 Christian Groessler + + * z8k-dis.c: Fix formatting. + (unpack_instr): Remove unused cases in switch statement. Add + safety abort() in default case. + (unparse_instr): Add safety abort() in default case. + +2001-06-06 Peter Jakubek + + * m68k-dis.c (print_insn_m68k): Fix typo. + * m68k-opc.c (m68k_opcodes): Correct allowed operands for + mcf (ColdFire) div, rem and moveb instructions. + +2001-06-06 Alan Modra + + * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define. + (cond_jump_mode, loop_jcxz_mode): Define. + (dis386_att): Add cond_jump_flag and loop_jcxz_flag as + appropriate, and 'F' suffix to loop insns. + (disx86_64_att): Likewise. + (dis386_twobyte_att): Likewise. + (print_insn_i386): Don't output addr prefix for loop, jcxz insns. + Output data size prefix for long conditional jumps. Output cs and + ds branch hints. + (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'. + (OP_J): Don't make PREFIX_DATA used. + +2001-06-04 Alexandre Oliva + + * sh-opc.h (sh_table): Complete last element entry to avoid + compiler warning. + +2001-05-16 Thiemo Seufer + + * mips-dis.c (mips_isa_type): Add MIPS r12k support. + +2001-05-23 Alan Modra + + * arc-opc.c: Whitespace changes. + +2001-05-18 Hans-Peter Nilsson + + * cris-opc.c (cris_spec_regs): Add missing initializer field for + last element. + +2001-05-15 Frank Ch. Eigler + + * cgen-dis.in (extract_normal): Complete support for min + + * mips-dis.c (INSNLEN): Rename MAXLEN. + (std_reg_names): Replace by mips32_reg_names and mips64_reg_names. + (print_insn_arg): Remove $ prefix of register names. + (set_mips_isa_type): Remove. + (mips_isa_type): New function. + (get_mips_isa): New Function. + (print_insn_mips): Rename _print_insn_mips. + (_print_insn_mips): New function, contains code which was + duplicated in print_insn_big_mips and print_insn_little_mips. + (print_insn_big_mips): Moved code to _print_insn_mips. + (print_insn_little_mips): Likewise. + (print_mips16_insn_arg): Remove $ prefix of register names. + Print error message before abort. + +2001-05-14 J.T. Conklin + + * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of + simplified mnemonics used for setting PPC750-specific special + purpose registers. + +2001-05-12 H.J. Lu + + * i386-dis.c (print_insn_i386): Always set `mod', `reg' and + `rm'. + +2001-05-12 Peter Targett + + * arc-opc.c (arc_reg_names): Correct attribute for lp_count + register to r/w. Formatting fixes throughout file. + +2001-05-12 Alan Modra + + * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and + movq operands. + (twobyte_has_modrm): Update table. + (need_modrm): Give it file scope. + (MODRM_CHECK): Define. + (dofloat): Use MODRM_CHECK. + (OP_E): Likewise. + (OP_EM): Likewise. + (OP_EX): Likewise. + +2001-05-07 Frank Ch. Eigler + + * cgen-dis.in (default_print_insn): Tolerate min + + * disassemble.c (disassembler_usage): Remove unused attribute. + +2001-05-04 Frank Ch. Eigler + + * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes. + +2001-05-04 Frank Ch. Eigler + + * cgen-dis.in (print_insn): Remove call to read_insn. Instead, + assume incoming buffer already has the base insn loaded. Handle + smaller-than-base instructions for variable-length case. + +2001-05-04 Alan Modra + + * i386-dis.c (Ev, Ed): Remove duplicate define. + (Gd): Define. + (XS): Define. + (OP_XS): New function. + (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and + movmskp operands. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Use MS for maskmovq operand. + +2001-04-27 Johan Rydberg + + * Makefile.am: Add OpenRISC target. + * Makefile.in: Regenerated. + + * disassemble.c (disassembler): Recognize the OpenRISC disassembly. + + * configure.in (bfd_openrisc_arch): Add target. + * configure: Regenerated. + + * openrisc-asm.c: New file. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + +2001-04-24 Christian Groessler + + * z8k-dis.c: add names of control registers (ctrl_names); + (seg_length): provides instruction length fixup for segmented + mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12, + CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases; + (unparse_intr): handle CLASS_PR, print addresses without '#' + * z8k-opc.h: re-created with new z8kgen + * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new + entries for ldctl/ldctlb instruction + +2001-04-06 Andreas Jaeger + + * i386-dis.c: Add ffreep instruction. + +2001-03-30 Alexandre Oliva + + * ppc-opc.c (insert_mbe): Shift mask initializer as long. + +2001-03-24 Alan Modra + + * i386-dis.c (PREGRP25): Define. + (dis386_twobyte_att): Use here in place of "movntq" entry. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq". + (PREGRP26): Define. + (dis386_twobyte_att): Use here. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Add PREGRP26 entry for "punpcklqdq". + (prefix_user_table ): XM operand, not MX. + (prefix_user_table): Cosmetic changes to "bad" entries. + +2001-03-23 Nick Clifton + + * mips-opc.c: Remove extraneous whitespace. + * mips-dis.c: Remove extraneous whitespace. + +2001-03-22 Ben Elliston + + * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg + declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional. + * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused + to allay a compiler warning. + +2001-03-22 Alan Modra + + * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq. + (dis386_twobyte_intel): Likewise. + (twobyte_has_modrm): Set entry for paddq, psubq. + +2001-03-20 Patrick Macdonald + + * cgen-dis.in (print_insn_@arch@): Add support for target machine + determination via CGEN_COMPUTE_MACH. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-03-20 H.J. Lu + + * configure.in: Remove the redundent AC_ARG_PROGRAM. + * configure: Rebuild. + +2001-03-19 Jim Wilson + + * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and + notestr if larger than xsect. + (in_class): Handle format M5. + * ia64-asmtab.c: Regnerate. + +2001-03-19 John David Anglin + + * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer + has more than one byte left to read. + +2001-03-16 Martin Schwidefsky + + * s390-opc.c: Add new opcodes. Smooth out formatting. + * s390-opc.txt: Add new opcodes. + +2001-03-06 Nick Clifton + + * arm-dis.c (print_insn_thumb): Compute destination address + of BLX(1) instruction by taking bit 1 from PC and not from bit + 0 of the offset. + +2001-03-06 Igor Shevlyakov + + * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs + so command line switches will work. + +2001-03-05 Dave Brolley + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-desc.h: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-02-28 Igor Shevlyakov + + * m68k-opc.c: fix cpushl according to Motorola. Enable + bunch of instructions for Coldfire 5407 and add all new. + +2001-02-27 Alan Modra + + * configure.in (BFD_VERSION): Do without grep. + * configure: Regenerate. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2001-02-23 David Mosberger + + * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4". + * ia64-asmtab.c: Regenerate. + +2001-02-21 David Mosberger + + * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two + separate variants: one for IMM22 and the other for IMM14. + * ia64-asmtab.c: Regenerate. + +2001-02-21 Greg McGary + + * cgen-opc.c (cgen_get_insn_value): Add missing `return'. + +2001-02-20 H.J. Lu + + * Makefile.am (ia64-ic.tbl): Remove the target. + (ia64-raw.tbl): Likewise. + (ia64-waw.tbl): Likewise. + (ia64-war.tbl): Likewise. + (ia64-asmtab.c): Generate it in the source directory. + * Makefile.in: Regenerated. + +2001-02-18 lars brinkhoff + + * Makefile.am: Add PDP-11 target. + * configure.in: Likewise. + * disassemble.c: Likewise. + * pdp11-dis.c: New file. + * pdp11-opc.c: New file. + +2001-02-14 Jim Wilson + + * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. + * ia64-asmtab.c: Regenerate. + +Mon Feb 12 17:41:26 CET 2001 Jan Hubicka + + * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison + instructions. + (putop): Handle 'Y' + +2001-02-11 Maciej W. Rozycki + + * mips-dis.c (print_insn_arg): Use top four bits of the address of + the following instruction not of the jump itself for the jump + target. + (print_mips16_insn_arg): Likewise. + +2001-02-11 Michael Sokolov + + * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build + directory. + * Makefile.in: Regenerate. + +2001-02-09 Schwidefsky + + * Makefile.am: Add linux target for S/390. + * Makefile.in: Likewise. + * configure.in: Likewise. + * disassemble.c: Likewise. + * s390-dis.c: New file. + * s390-mkopc.c: New file. + * s390-opc.c: New file. + * s390-opc.txt: New file. + +2001-02-05 Jim Wilson + + * ia64-asmtab.c: Revert 2000-12-16 change. + +2001-02-02 Patrick Macdonald + + * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. + * m32r-desc.h: Regenerate. + +Thu Feb 1 16:29:06 MET 2001 Jan Hubicka + + * i386-dis.c (dis386_att, grps): Use 'T' for push/pop + (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax + +2001-01-14 Alan Modra + + * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types. + +2001-01-13 Nick Clifton + + * disassemble.c: Remove spurious white space. + +Sat Jan 13 01:48:24 MET 2001 Jan Hubicka + + * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret + templates. + +2001-01-11 Peter Targett + + * configure.in: Add arc-ext.lo for bfd_arc_arch selection. + * Makefile.am (C_FILES): Add arc-ext.c. + (ALL_MACHINES) Add arc-ext.lo. + (INCLUDES) Add opcode directory to list. + New dependency entry for arc-ext.lo. + * disassemble.c (disassembler): Correct call to + arc_get_disassembler. + * arc-opc.c: New update for ARC, including full base + instructions for ARC variants. + * arc-dis.h, arc-dis.c: New update for ARC, including + extensibility functionality. + * arc-ext.h, arc-ext.c: New files for handling extensibility. + +2001-01-10 Jan Hubicka + + * i386-dis.c (PREGRP15 - PREGRP24): New. + (dis386_twobyt): Add SSE2 instructions. + (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions. + (twobyte_uses_f3_prefix): ... this one. + (grps): Add SSE instructions. + (prefix_user_table): Add two new slots; add SSE2 instructions. + (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix; + Handle the REPNZ and Data16 prefixes as well; do proper lookup + to prefix_user_table. + (OP_E): Accept mfence and lfence as well. + (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions. + (OP_XMM): Support REX extensions. + (OP_EM): Likewise. + (OP_EX): Likewise. + +2001-01-09 Nick Clifton + + * arm-dis.c (print_insn): Set pc to zero for instructions with + a reloc associated with them. + +2001-01-09 Jeff Johnston + + * cgen-asm.in (parse_insn_normal): Changed syn to be + CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn + as character to use CGEN_SYNTAX_CHAR macro and all comparisons + to '\0' to use 0 instead. + * cgen-dis.in (print_insn_normal): Ditto. + * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto. + +2001-01-05 Jan Hubicka + + * i386-dis.c: Add x86_64 support. + (rex): New static variable. + (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants. + (USED_REX): New macro. + (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros. + (OP_I64, OP_OFF64, OP_IMREG): New functions. + (OP_REG, OP_OFF): Declare. + (get64, get32, get32s): New functions. + (r??_reg): New constants. + (dis386_att): Change templates of instruction implicitly promoted + to 64bit; change e?? to RMe?? for unwind RM byte instructions. + (grps): Likewise. + (dis386_intel): Likewise. + (dixx86_64_att): New table based on dis386_att. + (dixx86_64_intel): New table based on dis386_intel. + (names64, names8rex): New global variable. + (names32, names16): Add extended registers. + (prefix_user_t): Recognize rex prefixes. + (prefix_name): Print REX prefixes nicely. + (op_riprel): New global variable. + (start_pc): Set type to bfd_vma. + (print_insn_i386): Detect the 64bit mode and use proper table; + move ckprefix after initializing the buffer; output unused rex prefixes; + output information about target of RIP relative addresses. + (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S'; + (print_operand_value): New function. + (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for + REX prefix and new modes. + (get64, get32s): New. + (get32): Return bfd_signed_vma type. + (set_op): Initialize the op_riprel. + * disassemble.c (disassembler): Recognize the x86-64 disassembly. + +2001-01-03 Richard Sandiford + + cgen-dis.in (read_insn): Use bfd_get_bits() + +2001-01-02 Richard Sandiford + + * cgen-dis.c (hash_insn_array): Use bfd_put_bits(). + (hash_insn_list): Likewise + * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits(). + (extract_1): Use bfd_get_bits(). + (extract_normal): Apply sign extension to both extraction + methods. + * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits() + (cgen_put_insn_value): Use bfd_put_bits() + +2000-12-28 Frank Ch. Eigler + + * cgen-asm.in (parse_insn_normal): Print better error message for + instructions with missing operands. + +2000-12-21 Santeri Paavolainen + + * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined. + +2000-12-16 Nick Clifton + + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure.in: Add spacing. + * configure: Regenerate. + * ia64-asmtab.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2000-12-12 Frank Ch. Eigler + + * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time + error messages over later parse-time ones. + +2000-12-12 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode + argument. + * ia64-gen.c (insert_deplist): Cast sizeof result to int. + (print_dependency_table): Print NULL if semantics field not set. + (insert_opcode_dependencies): Mark cmp parameter as unused. + (print_main_table): Use fprintf_vma to print long long fields. + (main): Mark argv paramter as unused. Convert to old style definition. + * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int. + * ia64-asmtab.c: Regnerate. + +2000-12-09 Nick Clifton + + * m32r-dis.c (print_insn): Prevent re-read of instruction from + wrong address. + + * fr30-dis.c: Regenerate. + +2000-12-08 Peter Targett + + * configure.in: Add arc-ext.lo for bfd_arc_arch selection. + * Makefile.am (C_FILES): Add arc-ext.c. + (ALL_MACHINES) Add arc-ext.lo. + (INCLUDES) Add opcode directory to list. + New dependency entry for arc-ext.lo. + * disassemble.c (disassembler): Correct call to + arc_get_disassembler. + * arc-opc.c: New update for ARC, including full base + instructions for ARC variants. + * arc-dis.h, arc-dis.c: New update for ARC, including + extensibility functionality. + * arc-ext.h, arc-ext.c: New files for handling extensibility. + +2000-12-03 Chris Demetriou cgd@sibyte.com + + * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO, + MOD_HILO, and MOD_LO macros. + + * mips-opc.c (M1, M2): Delete. + (mips_builtin_opcodes): Remove all uses of M1. + + * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2 + instructions take "G" format second operands and use the + correct flags. + There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to + match. + Delete "sel" code operands from mfc1 and mtc1. + Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants + for dm[ft]c[023]. + +2000-12-03 Ed Satterthwaite ehs@sibyte.com and + Chris Demetriou cgd@sibyte.com + + * mips-opc.c (mips_builtin_opcodes): Finish additions + for MIPS32 support, and clean up existing entries for + aesthetics, consistency with the MIPS32 ISA, and + with consistency the rest of the table. + +2000-12-01 Nick Clifton + + * mips16-opc.c (mips16_opcodes): Add initialiser for membership + field. + +2000-12-01 Chris Demetriou + + mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument + specifiers. Update 'B' for new constant names, and remove + 'm'. + mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop" + near the top of the array, so they are disassembled properly. + Enable "ssnop" for MIPS32. Add "break" variant with 20 bit + code for MIPS32. Update "clo" and "clz" to use 'U' operand + specifier. Add 'H' format specifier variants for "mfc1," + "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update + MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32 + "wait" variant which uses 'J' operand specifier. + + * mips-dis.c (set_mips_isa_type): Update to use + CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case. + Replace bfd_mach_mips4K with bfd_mach_mips32_4k case. + * mips-opc.c (I32): New constant for instructions added in + MIPS32. + (P4): Delete. + (mips_builtin_opcodes) Replace all uses of P4 with I32. + + * mips-dis.c (set_mips_isa_type): Add cases for + bfd_mach_mips5 and bfd_mach_mips64. + * mips-opc.c (I64): New definitions. + + * mips-dis.c (set_mips_isa_type): Add case for + bfd_mach_mips_sb1. + +2000-11-28 Hans-Peter Nilsson + + * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned. + (print_insn_ppi): Make nib1, nib2, nib3 unsigned. + Initialize variable dc to NULL. + (print_insn_shx): Remove unused label d_reg_n. + +2000-11-24 Nick Clifton + + * arm-opc.h: Add new opcode formatting parameter 'B'. + (arm_opcodes): Add XScale, v5, and v5te instructions. + (thumb_opcodes): Add v5t instructions. + + * arm-dis.c (print_insn_arm): Handle new 'B' format + parameter. + (print_insn_thumb): Decode BLX(1) instruction. + +2000-11-21 Chris Demetriou + + * mips-opc.c: Fix file header comment. + +2000-11-14 Hans-Peter Nilsson + + * cris-dis.c (cris_get_disassembler): If abfd is NULL, return + print_insn_cris_with_register_prefix. + +2000-11-11 Alexandre Oliva + + * sh-opc.h: The operand of `mov.w r0, (,GBR)' is IMM1, not 0. + +2000-11-07 Matthew Green + + * cgen-dis.in (print_insn): All insns which can fit into insn_value + must be loaded there in their entirety. + +2000-10-20 Jakub Jelinek + + * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. + (compute_arch_mask): Add v8plusb and v9b machines. + (print_insn_sparc): siam mode decoding, accept ASRs up to 25. + * sparc-opc.c: Support for Cheetah instruction set. + (prefetch_table): Add #invalidate. + +2000-10-16 Nick Clifton + + * mcore-dis.c (imsk): Change mask for OC to 0xFE00. + +2000-10-06 Dave Brolley + + * fr30-desc.h: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-ibld.c: Regenerate. + +2000-10-05 Jim Wilson + + * ia64-ic.tbl: Update from Intel. + * ia64-asmtab.c: Regenerate. + +2000-10-04 Kazu Hirata + + * ia64-gen.c: Convert C++-style comments to C-style comments. + * tic54x-dis.c: Likewise. + +2000-09-29 Hans-Peter Nilsson + + Changes to add dollar prefix to registers for files where user symbols + don't have a leading underscore. Fix formatting. + * cris-dis.c (REGISTER_PREFIX_CHAR): New. + (format_reg): Add parameter with_reg_prefix. All callers changed. + (print_with_operands): Ditto. + (print_insn_cris_generic): Renamed from print_insn_cris, add + parameter with_reg_prefix. + (print_insn_cris_with_register_prefix, + print_insn_cris_without_register_prefix, cris_get_disassembler): + New. + * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler. + +2000-09-22 Jim Wilson + + * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for + gt, ge, ngt, and nge. + * ia64-asmtab.c: Regenerate. + + * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. + * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. + (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". + * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. + * ia64-asmtab.c: Regnerate. + +2000-09-13 Anders Norlander + + * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores. + Add mfc0 and mtc0 with sub-selection values. + Add clo and clz opcodes. + Add msub and msubu instructions for MIPS32. + Add madd/maddu aliases for mad/madu for MIPS32. + Support wait, deret, eret, movn, pref for MIPS32. + Support tlbp, tlbr, tlbwi, tlbwr. + (P4): New define. + + * mips-dis.c (print_insn_arg): Print sdbbp 'm' args. + (print_insn_arg): Handle 'H' args. + (set_mips_isa_type): Recognize 4K. + Use CPU_* defines instead of hardcoded numbers. + +2000-09-11 Catherine Moore + + * d30v-opc.c (d30v_operand_t): New operand type Rb2. + (d30v_format_tab): Use Rb2 for modinc and moddec. + +2000-09-07 Catherine Moore + + * d30v-opc.c (d30v_format_tab): Use format Ra for + modinc and moddec. + +2000-09-06 Alexandre Oliva + + * configure: Rebuilt with new libtool.m4. + +2000-09-05 Nick Clifton + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2000-08-31 Alexandre Oliva + + * acinclude.m4: Include libtool and gettext macros from the + top level. + * aclocal.m4, configure: Rebuilt. + +2000-08-30 Kazu Hirata + + * tic80-dis.c: Fix formatting. + +2000-08-29 Kazu Hirata + + * w65-dis.c: Fix formatting. + +2000-08-28 Mark Hatle + + * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics. + (powerpc_opcodes): Add table entries for PPC 405 instructions. + Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403 + instructions. Added extended mnemonic mftbl as defined in the + 405GP manual for all PPCs. + +2000-08-28 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode + call. Change last goto to use failed instead of done. + +2000-08-28 Dave Brolley + + * cgen-ibld.in (cgen_put_insn_int_value): New function. + (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. + (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. + (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. + * cgen-dis.in (read_insn): New static function. + (print_insn): Use read_insn to read the insn into the buffer and set + up for disassembly. + (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is + in the buffer. + * fr30-asm.c: Regenerated. + * fr30-desc.c: Regenerated. + * fr30-desc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-ibld.c: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * m32r-asm.c: Regenerated. + * m32r-desc.c: Regenerated. + * m32r-desc.h: Regenerated. + * m32r-dis.c: Regenerated. + * m32r-ibld.c: Regenerated. + * m32r-opc.c: Regenerated. + +2000-08-28 Kazu Hirata + + * tic30-dis.c: Fix formatting. + +2000-08-27 Kazu Hirata + + * sh-dis.c: Fix formatting. + +2000-08-24 David Edelsohn + + * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd. + +2000-08-24 Kazu Hirata + + * z8k-dis.c: Fix formatting. + +2000-08-16 Jim Wilson + + * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete + break, mov-immediate, nop. + * ia64-opc-f.c: Delete fpsub instructions. + * ia64-opc-m.c: Add POSTINC to all instructions with postincrement + address operand. Rewrite using macros to avoid long lines. + * ia64-opc.h (POSTINC): Define. + * ia64-asmtab.c: Regenerate. + +2000-08-15 Jim Wilson + + * ia64-ic.tbl: Add missing entries. + +2000-08-08 Jason Eckhardt + + * i860-dis.c (print_br_address): Change third argument from int + to long. + +2000-08-07 Richard Henderson + + * ia64-dis.c (print_insn_ia64): Get byte skip count correct + for MLI templates. Handle IA64_OPND_TGT64. + +2000-08-04 Ben Elliston + + * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files. + * cgen.sh: Likewise. + +2000-08-02 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end. + +2000-07-29 Marek Michalkiewicz + + * avr-dis.c (avr_operand): Use PARAMS macro in declaration. + Change return type from void to int. Check the combination + of operands, return 1 if valid. Fix to avoid BUF overflow. + Report undefined combinations of operands in COMMENT. + Report internal errors to stderr. Output the adiw/sbiw + constant operand in both decimal and hex. + (print_insn_avr): Disassemble ldd/std with displacement of 0 + as ld/st. Check avr_operand () return value, handle invalid + combinations of operands like unknown opcodes. + +2000-07-28 Ben Elliston + + * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New. + (run-cgen, stamp-m32r, stamp-fr30): New targets. + * Makefile.in: Regenerate. + * configure.in: Add --enable-cgen-maint option. + * configure: Regenerate. + +2000-07-26 Dave Brolley + + * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned. + (cgen_hw_lookup_by_num): Ditto. + (cgen_operand_lookup_by_name): Ditto. + (print_address): Ditto. + (print_keyword): Ditto. + * cgen-dis.c (hash_insn_array): Mark unused parameters with + ATTRIBUTE_UNUSED. + * cgen-asm.c (hash_insn_array): Mark unused parameters with + ATTRIBUTE_UNUSED. + (cgen_parse_keyword): Ditto. + +2000-07-22 Jason Eckhardt + + * i860-dis.c: New file. + (print_insn_i860): New function. + (print_br_address): New function. + (sign_extend): New function. + (BITWISE_OP): New macro. + (I860_REG_PREFIX): New macro. + (grnames, frnames, crnames): New structures. + + * disassemble.c (ARCH_i860): Define. + (disassembler): Add check for bfd_arch_i860 to set disassemble + function to print_insn_i860. + + * Makefile.in (CFILES): Added i860-dis.c. + (ALL_MACHINES): Added i860-dis.lo. + (i860-dis.lo): New dependences. + + * configure.in: New bits for bfd_i860_arch. + + * configure: Regenerated. + +2000-07-20 Hans-Peter Nilsson + + * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c. + (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo. + (cris-dis.lo, cris-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure.in (bfd_cris_arch): New target. + * configure: Rebuild. + * disassemble.c (ARCH_cris): Define. + (disassembler): Support ARCH_cris. + * cris-dis.c, cris-opc.c: New files. + * po/POTFILES.in, po/opcodes.pot: Regenerate. + +2000-07-11 Jakub Jelinek + + * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2. + Reported by Bill Clarke . + +2000-07-09 Geoffrey Keating + + * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw. + Patch by Randall J Fisher . + +2000-07-09 Alan Modra + + * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg, + fput_const, extract_3, extract_5_load, extract_5_store, + extract_5r_store, extract_5R_store, extract_10U_store, + extract_5Q_store, extract_11, extract_14, extract_16, extract_21, + extract_12, extract_17, extract_22): Prototype. + (print_insn_hppa): Rename inner block opcode -> opc to avoid + shadowing outer block. + (GET_BIT): Define. + +2000-07-05 DJ Delorie + + * MAINTAINERS: new + +2000-07-04 Alexandre Oliva + + * arm-dis.c (print_insn_arm): Output combinations of PSR flags. + +2000-07-03 Marek Michalkiewicz + + * avr-dis.c (avr_operand): Change _ () to _() around all strings + marked for translation (exception from the usual coding style). + (print_insn_avr): Initialize insn2 to avoid warnings. + +2000-07-03 Kazu Hirata + + * h8300-dis.c (bfd_h8_disassemble): Improve readability. + * h8500-dis.c: Fix formatting. + +2000-07-01 Alan Modra + + * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed + (CLEANFILES): Add DEPA. + * Makefile.in: Regenerate. + +2000-06-26 Scott Bambrough + + * arm-dis.c (regnames): Add an additional register set to match + the set used by GCC. Make it the default. + +2000-06-22 Alan Modra + + * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we + find one. + * Makefile.in: Regenerate. + +2000-06-20 H.J. Lu + + * Makefile.am: Rebuild dependency. + * Makefile.in: Rebuild. + +2000-06-18 Stephane Carrez + + * Makefile.in, configure: regenerate + * disassemble.c (disassembler): Recognize ARCH_m68hc12, + ARCH_m68hc11. + * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12): + New functions. + * configure.in: Recognize m68hc12 and m68hc11. + * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x + * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly + and opcode generation for m68hc11 and m68hc12. + +2000-06-16 Nick Duffek + + * disassemble.c (disassembler): Refer to the PowerPC 620 using + bfd_mach_ppc_620 instead of 620. + +2000-06-12 Kazu Hirata + + * h8300-dis.c: Fix formatting. + (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl] + correctly. + +2000-06-09 Denis Chertykov + + * avr-dis.c (avr_operand): Bugfix for jmp/call address. + +2000-06-07 Denis Chertykov + + * avr-dis.c: completely rewritten. + +2000-06-02 Kazu Hirata + + * h8300-dis.c: Follow the GNU coding style. + (bfd_h8_disassemble) Fix a typo. + +2000-06-01 Kazu Hirata + + * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo. + (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl] + correctly. Fix a typo. + +2000-05-31 Nick Clifton + + * opintl.h (_(String)): Explain why dgettext is used instead of + gettext. + +2000-05-30 Nick Clifton + + * opintl.h (gettext, dgettext, dcgettext, textdomain, + bindtextdomain): Replace defines with those from intl/libgettext.h + to quieten gcc warnings. + +2000-05-26 Alan Modra + + * Makefile.am: Update dependencies with "make dep-am" + * Makefile.in: Regenerate. + +2000-05-25 Alexandre Oliva + + * m10300-dis.c (disassemble): Don't assume 32-bit longs when + sign-extending operands. + +2000-05-15 Donald Lindsay + + * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches + except brf's. + +2000-05-21 Nick Clifton + + * Makefile.am (LIBIBERTY): Define. + +2000-05-19 Diego Novillo + + * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES. + (STD_REGISTER_NAMES): New name for REGISTER_NAMES. + (reg_names): Rename to std_reg_names. Change it to a char ** + static variable. + (std_reg_names): New name for reg_names. + (set_mips_isa_type): Set reg_names to point to std_reg_names by + default. + +2000-05-16 Frank Ch. Eigler + + * fr30-desc.h: Partially regenerated to account for changed + CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. + * m32r-desc.h: Ditto. + +2000-05-15 Nick Clifton + + * arm-opc.h: Use upper case for flasg in MSR and MRS + instructions. Allow any bit to be set in the field_mask of + the MSR instruction. + + * arm-dis.c (print_insn_arm): Decode _x and _s bits of the + field_mask of an MSR instruction. + +2000-05-11 Thomas de Lellis + + * arm-opc.h: Disassembly of thumb ldsb/ldsh + instructions changed to ldrsb/ldrsh. + +2000-05-11 Ulf Carlsson + + * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit + target addresses for 'jal' and 'j'. + +2000-05-10 Geoff Keating + + * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes + also available in common mode when powerpc syntax is being used. + +2000-05-08 Alan Modra + + * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args. + (dummy_print_address): Ditto. + +2000-05-04 Timothy Wall + + * tic54x-opc.c: New. + * tic54x-dis.c: New. + * disassemble.c (disassembler): Add ARCH_tic54x. + * configure.in: Added tic54x target. + * configure: Ditto. + * Makefile.am: Add tic54x dependencies. + * Makefile.in: Ditto. + +2000-05-03 J.T. Conklin + + * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for + vector unit operands. + (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector + unit instruction formats. + (PPCVEC): New macro, mask for vector instructions. + (powerpc_operands): Add table entries for above operand types. + (powerpc_opcodes): Add table entries for vector instructions. + + * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Prepend 'v' when printing vector registers. + +2000-04-24 Clinton Popetz + + * configure.in: Add bfd_powerpc_64_arch. + * disassemble.c (disassembler): Use print_insn_big_powerpc for + 64 bit code. + +2000-04-24 Nick Clifton + + * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow + field. + +2000-04-23 Denis Chertykov + + * avr-dis.c (reg_fmul_d): New. Extract destination register from + FMUL instruction. + (reg_fmul_r): New. Extract source register from FMUL instruction. + (reg_muls_d): New. Extract destination register from MULS instruction. + (reg_muls_r): New. Extract source register from MULS instruction. + (reg_movw_d): New. Extract destination register from MOVW instruction. + (reg_movw_r): New. Extract source register from MOVW instruction. + (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU, + EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions. + +2000-04-22 Timothy Wall + + * ia64-gen.c (general): Add an ordered table of primary + opcode names, as well as priority fields to disassembly data + structures to enforce a preferred disassembly format based on the + ordering of the opcode tables. + (load_insn_classes): Show a useful message if IC tables are missing. + (load_depfile): Ditto. + * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to + distinguish preferred disassembly. + * ia64-opc-f.c: Reorder some insn for preferred disassembly + format. Fix incorrect flag on fma.s/fma.s.s0. + * ia64-opc.c: Scan *all* disassembly matches and use the one with + the highest priority. + * ia64-opc-b.c: Use more abbreviations. + * ia64-asmtab.c: Regenerate. + +2000-04-21 Jason Eckhardt + + * hppa-dis.c (extract_16): New function. + (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of + new operand types l,y,&,fe,fE,fx. + +2000-04-21 Richard Henderson + David Mosberger + Timothy Wall + Bob Manson + Jim Wilson + + * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h. + (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, + ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c, + ia64-asmtab.c. + (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo. + (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen, + ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure Rebuild. + * configure.in (bfd_ia64_arch): New target. + * disassemble.c (ARCH_ia64): Define. + (disassembler): Support ARCH_ia64. + * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl, + ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c, + ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl, + ia64-war.tbl, ia64-waw.tbl: New files. + +2000-04-20 Alexandre Oliva + + * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. + (disassemble): Use them. + +2000-04-14 Alan Modra + + * sysdep.h: Include "ansidecl.h" not + * Makefile.am: Update dependencies. + * Makefile.in: Regenerate. + +2000-04-14 Michael Sokolov + + * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, + avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, + disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, + i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, + m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, + mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, + ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, + tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, + w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove + ansidecl.h as sysdep.h includes it. + +2000-04-7 Andrew Cagney + + * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add + --enable-build-warnings option. + * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions. + * Makefile.in, configure: Re-generate. + +2000-04-05 J"orn Rennecke + + * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. + stc GBR,@- is available for arch_sh1_up. + Group parallel processing insn with identical mnemonics together. + Make three-operand psha / pshl come first. + +2000-04-05 J"orn Rennecke + + * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. + Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. + (sh_arg_type): Add A_PC. + (sh_table): Update entries using immediates. Add repeat. + * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. + Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. + +2000-04-04 Alan Modra + + * po/opcodes.pot: Regenerate. + + * Makefile.am (MKDEP): Use gcc -MM rather than mkdep. + (DEP): Quote when passing vars to sub-make. Add warning message + to end. + (DEP1): Rewrite for "gcc -MM". + (CLEANFILES): Add DEP2. + Update dependencies. + * Makefile.in: Regenerate. + +2000-04-03 Denis Chertykov + + * avr-dis.c: Syntax cleanup. + (add0fff): Print the pc relative address as a signed number. + (add03f8): Likewise. + +2000-04-01 Ian Lance Taylor + + * disassemble.c (disassembler_usage): Don't use a prototype. Mark + the parameter ATTRIBUTE_UNUSED. + * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed. + +2000-04-01 Alexandre Oliva + + * m10300-opc.c: SP-based offsets are always unsigned. + +2000-03-29 Thomas de Lellis + + * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal" + [branch always] instead of "undefined". + +2000-03-27 Nick Clifton + + * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of + short instructions, from end of list of long instructions. + +2000-03-27 Ian Lance Taylor + + * Makefile.am (CFILES): Add avr-dis.c. + (ALL_MACHINES): Add avr-dis.lo. + +2000-03-27 Alan Modra + + * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to + truncate integers. + (print_insn_avr): Call function via pointer in K&R compatible way. + (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204, + add0fff, add03f8): Convert to old style function declaration and + add prototype. + (avrdis_opcode): Add prototype. + +2000-03-27 Denis Chertykov + + * avr-dis.c: New file. AVR disassembler. + * configure.in (bfd_avr_arch): New architecture support. + * disassemble.c: Likewise. + * configure: Regenerate. + +2000-03-06 J"oern Rennecke + + * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement. + +2000-03-02 J"orn Rennecke + + * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand + flag to determine if operand is pc-relative. + * d30v-opc.c: + (d30v_format_table): + (REL6S3): Renamed from IMM6S3. + Added flag OPERAND_PCREL. + (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with + added flag OPERAND_PCREL. + (IMM12S3U): Replaced with REL12S3. + (SHORT_D2, LONG_D): Delay target is pc-relative. + (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r): + Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r, + using the REL* operands. + (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D. + (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B, + LONG_Db, using REL* operands. + (SHORT_U, SHORT_A5S): Removed stray alternatives. + (d30v_opcode_table): Use new *r formats. + +2000-02-28 Nick Clifton + + * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with + 'signed_overflow_ok_p'. + +2000-02-27 Eli Zaretskii + + * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the + name of the libtool directory. + * Makefile.in: Rebuild. + +2000-02-24 Nick Clifton + + * cgen-opc.c (cgen_set_signed_overflow_ok): New function. + (cgen_clear_signed_overflow_ok): New function. + (cgen_signed_overflow_ok_p): New function. + +2000-02-23 Andrew Haley + + * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, + m32r-ibld.c, m32r-opc.h: Rebuild. + +2000-02-23 Linas Vepstas + + * i370-dis.c, i370-opc.c: New. + + * disassemble.c (ARCH_i370): Define. + (disassembler): Handle it. + + * Makefile.am: Add support for Linux/IBM 370. + * configure.in: Likewise. + + * Makefile.in: Regenerate. + * configure: Likewise. + +2000-02-22 Chandra Chavva + + * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to + ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel + procedure. + +2000-02-22 Andrew Haley + + * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: + force gp32 to zero. + * mips-opc.c (G6): New define. + (mips_builtin_op): Add "move" definition for -gp32. + +2000-02-22 Ian Lance Taylor + + From Grant Erickson : + * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2. + +2000-02-21 Alan Modra + + * dis-buf.c (buffer_read_memory): Change `length' param and all int + vars to unsigned. + +2000-02-17 J"orn Rennecke + + * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. + (print_insn_ppi): Likewise. + (print_insn_shx): Use info->mach to select appropriate insn set. + Add support for sh-dsp. Remove FD_REG_N support. + * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. + (sh_arg_type): Likewise. Remove FD_REG_N. + (sh_dsp_reg_nums): New enum. + (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. + (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. + (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. + (arch_sh3_dsp_up): Likewise. + (sh_opcode_info): New field: arch. + (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and + D_REG_N. Fill in arch field. Add sh-dsp insns. + +2000-02-14 Fernando Nasser + + * arm-dis.c: Change flavor name from atpcs-special to + special-atpcs to prevent name conflict in gdb. + (get_arm_regname_num_options, set_arm_regname_option, + get_arm_regnames): New functions. API to access the several + flavor of register names. Note: Used by gdb. + (print_insn_thumb): Use the register name entry from the currently + selected flavor for LR and PC. + +2000-02-10 Nick Clifton + + * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR + classes. + (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and + "mulsh.h" instructions. + * mcore-dis.c (imsk array): Add masks for MULSH and OPSR + classes. + (print_insn_mcore): Add support for little endian targets. + Add support for MULSH and OPSR classes. + +2000-02-07 Nick Clifton + + * arm-dis.c (parse_arm_diassembler_option): Rename again. + Previous delat did not take. + +2000-02-03 Timothy Wall + + * dis-buf.c (buffer_read_memory): Use octets_per_byte field + to adjust target address bounds checking and calculate the + appropriate octet offset into data. + +2000-01-27 Nick Clifton + + * arm-dis.c: (parse_disassembler_option): Rename to + parse_arm_disassembler_option and allow to be exported. + + * disassemble.c (disassembler_usage): New function: Print out any + target specific disassembler options. + Call arm_disassembler_options() if the ARM architecture is being + supported. + + * arm-dis.c (NUM_ELEM): Define this macro if not already + defined. + (arm_regname): New struct type for ARM register names. + (arm_toggle_regnames): Delete. + (parse_disassembler_option): Use register name structure. + (print_insn): New function: Combines duplicate code found in + print_insn_big_arm and print_insn_little_arm. + (print_insn_big_arm): Call print_insn. + (print_insn_little_arm): Call print_insn. + (print_arm_disassembler_options): Display list of supported, + ARM specific disassembler options. + +2000-01-27 Thomas de Lellis + + * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the + ARM_STT_16BIT flag as Thumb code symbols. + + * arm-dis.c (printf_insn_little_arm): Ditto. + +2000-01-25 Thomas de Lellis + + * arm-dis.c (printf_insn_thumb): Prevent double dumping + of raw thumb instructions. + +2000-01-20 Nick Clifton + + * mcore-opc.h (mcore_table): Add "add" as an alias for "addu". + +2000-01-03 Nick Clifton + + * arm-dis.c (streq): New macro. + (strneq): New macro. + (force_thumb): ew local variable. + (parse_disassembler_option): New function: Parse a single, ARM + specific disassembler command line switch. + (parse_disassembler_option): Call parse_disassembler_option to + parse individual command line switches. + (print_insn_big_arm): Check force_thumb. + (print_insn_little_arm): Check force_thumb. + +For older changes see ChangeLog-9899 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/opcodes/ChangeLog-9297 b/opcodes/ChangeLog-9297 new file mode 100644 index 0000000..799457e --- /dev/null +++ b/opcodes/ChangeLog-9297 @@ -0,0 +1,3797 @@ +Mon Dec 22 12:37:06 1997 Ian Lance Taylor + + * mips-opc.c: Add FP_D to s.d instruction flags. + +Wed Dec 17 11:38:29 1997 Andreas Schwab + + * m68k-opc.c (halt, pulse): Enable them on the 68060. + +Tue Dec 16 15:22:53 1997 Fred Fish + + * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit + PC relative offset forms before the 15 bit forms. An assembler command + line option now chooses the default. + +Tue Dec 16 15:22:51 1997 Michael Meissner + + * d30v-opc.c (d30v_opcode_table): Set new flags bits + FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions. + +1997-12-15 Brendan Kehoe + + * configure: Only build libopcodes shared if --enable-shared's value + was `yes', or was set to `*opcodes*'. + * aclocal.m4: Likewise. + * NOTE: this really needs to be fixed in libtool/libtool.m4, the + original source of this bit of code. It's not clear what the best fix + would be, though. + +Fri Dec 12 11:57:04 1997 Fred Fish + + * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change. + (tic80_opcodes): Reorder table entries to put the 32 bit PC relative + offset forms before the 15 bit forms, to default to the long forms. + +Fri Dec 12 01:32:30 1997 Richard Henderson + + * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid. + +Wed Dec 10 17:42:35 1997 Nick Clifton + + * arm-dis.c (print_insn_little_arm): Prevent examination of stored + symbol if none is present. + (print_insn_big_arm): Prevent examination of stored symbol if + none is present. + +Thu Oct 23 21:13:37 1997 Fred Fish + + * d10v-opc.c (d10v_opcodes): Correct entry for RTE. + +Mon Dec 8 11:21:07 1997 Nick Clifton + + * disassemble.c: Remove disasm_symaddr() function. + + * arm-dis.c: Use info->symbol instead of info->flags to determine + if disassmbly should be in Thumb or Arm mode. + +Tue Dec 2 09:54:27 1997 Nick Clifton + + * arm-dis.c: Add support for disassembling Thumb opcodes. + (print_insn_thumb): New function. + + * disassemble.c (disasm_symaddr): New function. + + * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly. + (thumb_opcodes): Table of Thumb opcodes. + +Mon Dec 1 12:25:57 1997 Andreas Schwab + + * m68k-opc.c (btst): Change Dd@s to Dd;b. + + * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q', + and 'v' as operand types. + +Mon Dec 1 11:56:50 1997 Ian Lance Taylor + + * m68k-opc.c: Add argument for lpstop. From Olivier Carmona + . + * m68k-dis.c (print_insn_m68k): Handle special case of lpstop, + which has a two word opcode with a one word argument. + +Sun Nov 23 22:25:21 1997 Michael Meissner + + * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is + unsigned, not signed. + (d30v_format_table): Add SHORT_CMPU cases for cmpu. + +Tue Nov 18 23:10:03 1997 J"orn Rennecke + + * d10v-dis.c (print_operand): + Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG. + +Tue Nov 18 18:45:14 1997 J"orn Rennecke + + * d10v-opc.c (OPERAND_FLAG): Split into: + (OPERAND_FFLAG, OPERAND_CFLAG) . + (FSRC): Split into: + (FFSRC, CFSRC). + +Thu Nov 13 11:05:33 1997 Gavin Koch + + * mips-opc.c: Move the INSN_MACRO ISA value to the membership + field for all INSN_MACRO's. + * mips16-opc.c: same + +Wed Nov 12 10:16:57 1997 Gavin Koch + + * mips-opc.c (sync,cache): These are 3900 insns. + +Tue Nov 11 23:53:41 1997 J"orn Rennecke + + sh-opc.h (sh_table): Remove ftst/nan. + +Tue Oct 28 17:59:32 1997 Ken Raeburn + + * mips-opc.c (ffc, ffs): Fix mask. + +Tue Oct 28 16:34:54 1997 Michael Meissner + + * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m + control registers. + +Mon Oct 27 22:34:03 1997 Ken Raeburn + + * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. + (WR_HILO, RD_HILO, MOD_HILO): New macros. + +Mon Oct 27 22:34:03 1997 Ken Raeburn + + * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. + (WR_HILO, RD_HILO, MOD_HILO): New macros. + +Thu Oct 23 14:57:58 1997 Nick Clifton + + * v850-dis.c (disassemble): Replace // with /* ... */ + +Wed Oct 22 17:33:21 1997 Richard Henderson + + * sparc-opc.c: Add wr & rd for v9a asr's. + * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's. + (v9a_asr_reg_names): New variable. + Patch from David Miller . + +Wed Oct 22 17:18:02 1997 Richard Henderson + + * sparc-opc.c (v9notv9a): New insn type. + (IMPDEP): Move to the end to not conflict with edge8 et al. + Patch from David Miller . + +Fri Oct 17 13:18:53 1997 Gavin Koch + + * mips-opc.c (bnezl,beqzl): Mark these as also tx39. + +Thu Oct 16 11:55:20 1997 Gavin Koch + + * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. + +Tue Oct 14 16:10:31 1997 Nick Clifton + + * v850-dis.c (disassemble): Use new symbol_at_address_func() field + of disassemble_info structure to determine if an overlay address + has a matching symbol in low memory. + + * dis-buf.c (generic_symbol_at_address): New (dummy) function for + new symbol_at_address_func field in disassemble_info structure. + +Fri Oct 10 16:44:52 1997 Nick Clifton + + * v850-opc.c (extract_d22): Use signed arithmatic. + +Tue Oct 7 23:40:43 1997 Gavin Koch + + * mips-opc.c: Three op mult is not an ISA insn. + +Tue Oct 7 23:37:21 1997 Gavin Koch + + * mips-opc.c: Fix formatting. + +Fri Oct 3 17:26:54 1997 Ian Lance Taylor + + * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather + than assuming that char is signed. Explicitly sign extend 16 bit + values, rather than assuming that short is 16 bits. + (OP_sI, OP_J, OP_DIR): Likewise. + +Thu Oct 2 13:36:45 1997 Nick Clifton + + * v850-dis.c (v850_sreg_names): Use symbolic names for higher + system registers. + +Wed Oct 1 16:58:54 1997 Nick Clifton + + * v850-opc.c: Fix typo in comment. + + * v850-dis.c (disassemble): Add test of processor type when + determining opcodes. + +Wed Oct 1 14:10:20 1997 Ian Lance Taylor + + * configure.in: Use a diversion to set enable_shared before the + arguments are parsed. + * configure: Rebuild. + +Thu Sep 25 13:04:59 1997 Ian Lance Taylor + + * m68k-opc.c (TBL1): Use ! rather than `. + * m68k-dis.c (print_insn_arg): Remove ` operand specifier. + +Wed Sep 24 11:29:35 1997 Ian Lance Taylor + + * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. + + * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. + + * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr + for mcf5200. + + * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. + * aclocal.m4: Rebuild with new libtool. + * configure: Rebuild. + +Fri Sep 19 11:45:49 1997 Andrew Cagney + + * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2. + +Thu Sep 18 11:21:43 1997 Doug Evans + + * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. + +Tue Sep 16 15:18:20 1997 Nick Clifton + + * v850-opc.c (v850_opcodes): Further rearrangements. + +Tue Sep 16 16:12:11 1997 Ken Raeburn + + * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. + +Tue Sep 16 09:48:50 1997 Nick Clifton + + * v850-opc.c (v850_opcodes): Fields reordered to allow assembler + parser to work. + +Tue Sep 16 10:01:00 1997 Gavin Koch + + * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. + +Mon Sep 15 18:31:52 1997 Nick Clifton + + * v850-opc.c: Initialise processors field of v850_opcode structure. + +Wed Aug 27 21:42:39 1997 Ken Raeburn + + Merge changes from Martin Hunt: + + * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values. + + * d30v-opc.c (pre_defined_registers): Add control registers from 0-63. + (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix + rot2h, sra2h, and srl2h to use new SHORT_A5S format. + + * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes. + + * d30v-dis.c (print_insn): First operand of d*i (delayed + branch) instructions is relative. + + * d30v-opc.c (d30v_opcode_table): Change form for repeati. + (d30v_operand_table): Add IMM6S3 type. + (d30v_format_table): Change SHORT_D2. Add LONG_Db. + + * d30v-dis.c: Fix bug with ".s" and ".l" extensions + and cmp instructions. + + * d30v-opc.c: Correct entries for repeat*, and sat*. + Make IMM5 unsigned. Create IMM6U and IMM12S3U operand + types. Correct several formats. + + * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. + + * d30v-opc.c (pre_defined_registers): Change control registers. + + * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and + SHORT_C2. Manual was incorrect. + + * d30v-dis.c (lookup_opcode): Return value now indicates + if an opcode has a short and a long form. Used for deciding + to append a ".s" or ".l". + (print_insn): Append a ".s" to an instruction if it is + the short form and ".l" if it is a long form. Do not append + anything if the instruction has only one possible size. + + * d30v-opc.c: Change mulx2h to require an even register. + New form: SHORT_A2; a SHORT_A form that needs an even + register as the first operand. + + * d30v-dis.c (print_insn_d30v): Fix problem where the last + instruction was not being disassembled if there were an odd + number of instructions. + + * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms. + +Fri Sep 12 11:43:54 1997 Nick Clifton + + * v850-dis.c (disassemble): Improved display of register lists. + +Thu Sep 11 17:35:10 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix assembler args to + fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s, + fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s, + fandnot1s, fandnot2s. + +Tue Sep 9 10:03:49 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. + +Mon Sep 8 14:06:59 1997 Doug Evans + + * cgen-asm.c (cgen_parse_address): New argument resultp. + All callers updated. + * m32r-asm.c (parse_h_hi16): Right shift numbers by 16. + +Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): PC relative instructions are + relative to the next instruction, not the current instruction. + +Tue Sep 2 15:41:55 1997 Nick Clifton + + * v850-dis.c (disassemble): Only signed extend values that are not + returned by extract functions. + Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag. + +Tue Sep 2 15:39:40 1997 Nick Clifton + + * v850-opc.c: Update comments. Remove use of + V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns. + +Tue Aug 26 09:42:28 1997 Nick Clifton + + * v850-opc.c (MOVHI): Immediate parameter is unsigned. + +Mon Aug 25 15:58:07 1997 Christopher Provenzano + + * configure: Rebuilt with latest devo autoconf for NT support. + +Fri Aug 22 10:35:15 1997 Nick Clifton + + * v850-dis.c (disassemble): Use curly brace syntax for register + lists. + + * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases + where r0 is being used as a destination register. + +Thu Aug 21 11:09:09 1997 Nick Clifton + + * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other. + +Tue Aug 19 10:59:59 1997 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage. + +Mon Aug 18 11:10:03 1997 Nick Clifton + + * v850-opc.c (v850_opcodes[]): Remove use of flag field. + * v850-opc.c (v850_opcodes[]): Add support for reversed short load + opcodes.. + +Mon Aug 18 11:08:25 1997 Nick Clifton + + * configure (cgen_files): Add support for v850e target. + * configure.in (cgen_files): Add support for v850e target. + +Mon Aug 18 11:08:25 1997 Nick Clifton + + * configure (cgen_files): Add support for v850ea target. + * configure.in (cgen_files): Add support for v850ea target. + +Fri Aug 15 05:17:48 1997 Doug Evans + + * configure.in (bfd_arc_arch): Add. + * configure: Rebuild. + * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo. + * Makefile.in: Rebuild. + * arc-dis.c, arc-opc.c: New files. + * disassemble.c (ARCH_all): Define ARCH_arc. + (disassembler): Add ARC support. + +Wed Aug 13 18:52:11 1997 Nick Clifton + + * v850-dis.c (disassemble): Add support for v850EA instructions. + + * v850-opc.c (insert_i5div, extract_i5div): New Functions. + (v850_opcodes): Add v850EA instructions. + + * v850-dis.c (disassemble): Add support for v850E instructions. + + * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, + extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, + insert_spe, extract_spe): New Functions. + (v850_opcodes): Add v850E instructions. + + * v850-opc.c: Reorganised and re-layed out to improve readability + and portability. + +Tue Aug 5 23:09:31 1997 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.12.1. + +Mon Aug 4 12:02:16 1997 Ian Lance Taylor + + * aclocal.m4, configure: Rebuild with new automake patches. + +Fri Aug 1 13:02:04 1997 Ian Lance Taylor + + * configure.in: Set enable_shared before AM_PROG_LIBTOOL. + * acinclude.m4: Just include acinclude.m4 from BFD. + * aclocal.m4, configure: Rebuild. + +Thu Jul 31 21:44:42 1997 Ian Lance Taylor + + * Makefile.am: New file, based on old Makefile.in. + * acconfig.h: New file. + * acinclude.m4: New file. + * stamp-h.in: New file. + * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL. + Removed shared library handling; now handled by libtool. Replace + AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE, + AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with + AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h + handling in AC_OUTPUT. + * dep-in.sed: Change .o to .lo. + * Makefile.in: Now built with automake. + * aclocal.m4: Now built with aclocal. + * config.in, configure: Rebuild. + +Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Fix typo/thinko in "eret" instruction. + +Thu Jul 24 13:03:26 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. + Make array const. + * sparc-dis.c (sorted_opcodes): New static local. + (struct opcode_hash): `opcode' is pointer to const element. + (build_hash): First arg is now table of sorted pointers. + (print_insn_sparc): Sort opcodes by sorting table of pointers. + (compare_opcodes): Update. + +Tue Jul 15 12:05:23 1997 Doug Evans + + * cgen-opc.c: #include . + (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. + Handle case insensitive hashing. + (hash_keyword_value): Change type of `value' to unsigned int. + +Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (mips_builtin_opcodes): If an insn uses single + precision FP, mark it as such. Likewise for double precision + FP. Mark ISA1 insns. Consolidate duplicate opcodes where + possible. + +Wed Jun 25 15:25:57 1997 Felix Lee + + * ppc-opc.c (extract_nsi): make unsigned expression signed before + negating it. + (UNUSED): remove one level of parens, so MSVC doesn't choke on + nesting depth when all the macros are expanded. + +Tue Jun 17 17:02:17 1997 Ian Lance Taylor + + * sparc-opc.c: The fcmp v9a instructions take an integer register + as a destination, not a floating point register. From Christian + Kuehnke . + +Mon Jun 16 14:13:18 1997 Ian Lance Taylor + + * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() + syntax. From Roman Hodek + . + + * i386-dis.c (twobyte_has_modrm): Fix pand. + +Mon Jun 16 14:08:38 1997 Michael Taylor + + * i386-dis.c (dis386_twobyte): Fix pand and pandn. + +Tue Jun 10 11:26:47 1997 H.J. Lu + + * arm-dis.c: Add prototypes for arm_decode_shift and + print_insn_arm. + +Mon Jun 2 11:39:04 1997 Gavin Koch + + * mips-opc.c: Add r3900 insns. + +Tue May 27 15:55:44 1997 Ian Lance Taylor + + * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't + print delay slot instructions on the same line. When using a PC + relative load, add a comment with the value being loaded if it can + be obtained. + +Tue May 27 11:02:08 1997 Alan Modra + + * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl + to pushS/popS for segment regs and byte constant so that + pushw/popw printed when in 16 bit data mode. + + * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to + print cbtw, cwtd in 16 bit data mode. + * i386-dis.c (putop): extra case W to support above. + + * i386-dis.c (print_insn_x86): print addr32 prefix when given + address size prefix in 16 bit address mode. + +Fri May 23 16:47:23 1997 Ian Lance Taylor + + * sh-dis.c: Reindent. Rename local variable fprintf to + fprintf_fn. + +Thu May 22 14:06:02 1997 Doug Evans + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. + +Tue May 20 11:26:27 1997 Gavin Koch + + * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new + field membership. + * mips16-opc.c (mip16_opcodes): same. + +Mon May 12 15:10:53 1997 Jim Wilson + + * m68k-opc.c (moveb): Change $d to %d. + +Mon May 5 14:28:41 1997 Ian Lance Taylor + + * i386-dis.c: (dis386_twobyte): Add MMX instructions. + (twobyte_has_modrm): Likewise. + (grps): Likewise. + (OP_MMX, OP_EM, OP_MS): New static functions. + + * i386-dis.c: Revert patch of April 4. The output now matches + what gcc generates. + +Fri May 2 12:48:37 1997 Doug Evans + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead + of $simm16. + +Thu May 1 15:34:15 1997 Doug Evans + + * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. + +Tue Apr 15 12:40:08 1997 Ian Lance Taylor + + * Makefile.in (install): Depend upon installdirs. + (installdirs): New target. + +Mon Apr 14 12:13:51 1997 Ian Lance Taylor + + From Thomas Graichen : + * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. + * configure: Rebuild. + +Sun Apr 13 17:50:41 1997 Doug Evans + + * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. + Delete string{,s}.h support. + +Thu Apr 10 14:44:56 1997 Doug Evans + + * cgen-asm.c (cgen_parse_operand_fn): New global. + (cgen_parse_{{,un}signed_integer,address}): Update call to + cgen_parse_operand_fn. + (cgen_init_parse_operand): New function. + * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed + from cgen_asm_init_parse. + (m32r_cgen_assemble_insn): New operand `errmsg'. + Delete call to as_bad, return error message to caller. + (m32r_cgen_asm_hash_keywords): #if 0 out. + +Wed Apr 9 12:05:25 1997 Andreas Schwab + + * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, + not data register. + [case 'J']: Fix typo in register name. + +Mon Apr 7 16:48:22 1997 Ian Lance Taylor + + * configure.in: Substitute SHLIB_LIBS. + * configure: Rebuild. + * Makefile.in (SHLIB_LIBS): New variable. + ($(SHLIB)): Use $(SHLIB_LIBS). + +Mon Apr 7 11:45:44 1997 Doug Evans + + * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. + + * cgen-opc.c (hash_keyword_name): Improve algorithm. + + * disassemble.c (disassembler): Handle m32r. + +Fri Apr 4 12:29:38 1997 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. + * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. + * Makefile.in (CFILES): Add them. + (ALL_MACHINES): Add them. + (dependencies): Regenerate. + * configure.in (cgen_files): New variable. + (bfd_m32r_arch): Add entry. + * configure: Regenerate. + +Fri Apr 4 14:04:16 1997 Ian Lance Taylor + + * configure.in: Correct file names for bfd_mn10[23]00_arch. + * configure: Rebuild. + + * Makefile.in: Rebuild dependencies. + + * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". + + * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and + fdivp. + +Thu Apr 3 13:22:45 1997 Ian Lance Taylor + + * Branched binutils 2.8. + +Wed Apr 2 12:23:53 1997 Ian Lance Taylor + + * m10200-dis.c: Rename from mn10200-dis.c. + * m10200-opc.c: Rename from mn10200-opc.c. + * m10300-dis.c: Rename from mn10300-dis.c + * m10300-opc.c: Rename from mn10300-opc.c. + * Makefile.in: Update accordingly. + + * mips16-opc.c: Add mul and dmul macros. + +Tue Apr 1 16:27:45 1997 Klaus Kaempf + + * makefile.vms: Update CFLAGS, add clean target. + +Fri Mar 28 12:10:09 1997 Ian Lance Taylor + + * mips-opc.c: Add "wait". From Ralf Baechle + . + + * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. + * configure, config.in: Rebuild. + * sysdep.h: Include if it exists. + * sparc-dis.c: Include and "sysdep.h". Don't include + . + * Makefile.in: Rebuild dependencies. + +Thu Mar 27 14:24:43 1997 Ian Lance Taylor + + * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From + Andrew Bray . + + * mips-opc.c: Add cast when setting mips_opcodes. + +Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Fix sign extension problem. + * v850-opc.c (extract_d*): Fix sign extension problems to make + disassembly calculate branch offsets correctly. + +Mon Mar 24 13:22:13 1997 Ian Lance Taylor + + * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. + + * mips-opc.c: Add dctr and dctw. + +Sun Mar 23 18:08:10 1997 Martin M. Hunt + + * d30v-dis.c (print_insn): Change the way signed constants + are displayed. + +Fri Mar 21 14:37:52 1997 Ian Lance Taylor + + * Makefile.in (BFD_H): New variable. + (HFILES): New variable. + (CFILES): Add all C files. + (.dep, .dep1, dep.sed, dep, dep-in): New targets. + Delete old dependencies, and build new ones. + * dep-in.sed: New file. + +Thu Mar 20 19:03:30 1997 Philippe De Muyter + + * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}. + +Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Change "trap" to "syscall". + * mn10300-opc.c: Add new "syscall" instruction. + +Mon Mar 17 08:48:03 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and + mulul insns on the coldfire. + +Sat Mar 15 17:13:05 1997 Ian Lance Taylor + + * arm-dis.c (print_insn_arm): Don't print instruction bytes. + (print_insn_big_arm): Set bytes_per_chunk and display_endian. + (print_insn_little_arm): Likewise. + +Fri Mar 14 15:08:59 1997 Ian Lance Taylor + + Based on patches from H.J. Lu : + * i386-dis.c (fetch_data): Add prototype. + * m68k-dis.c (fetch_data): Add prototype. + (dummy_print_address): Add prototype. Make static. + * ppc-opc.c (valid_bo): Add prototype. + * sparc-dis.c (build_hash_table): Add prototype. + (is_delayed_branch, compute_arch_mask): Add prototypes. + (print_insn_sparc): Make several local variables const. + (compare_opcodes): Change arguments to const PTR. Add prototype. + * sparc-opc.c (arg): Change name field to be const. + (lookup_name, lookup_value): Add prototypes. Change table and + name parameters to be const. + (sparc_encode_asi): Change name parameter to be const. + (sparc_encode_membar, sparc_encode_prefetch): Likewise. + (sparc_encode_sparclet_cpreg): Likewise. + (sparc_decode_asi): Change return type to be const. + (sparc_decode_membar, sparc_decode_prefetch): Likewise. + (sparc_decode_sparclet_cpreg): Likewise. + +Fri Mar 7 10:51:49 1997 Ian Lance Taylor + + * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since + Solaris doesn't like the combined options, and the -f is + unnecessary. + (stamp-tshlink, install): Likewise. + +Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these + as relaxable. + +Tue Mar 4 06:10:36 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. + +Mon Mar 3 07:45:20 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on + the mc68000. + +Thu Feb 27 14:04:32 1997 Philippe De Muyter + + * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. + +Thu Feb 27 11:36:41 1997 Michael Meissner + + * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8. + +Wed Feb 26 15:34:48 1997 Michael Meissner + + * tic80-opc.c (tic80_predefined_symbols): Define r25 properly. + +Wed Feb 26 13:38:30 1997 Andreas Schwab + + * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use + floatformat_to_double to make portable. + (print_insn_arg): Use NEXTEXTEND macro when extracting extended + precision float. + +Mon Feb 24 19:26:12 1997 Dawn Perchik + + * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes, + and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes. + +Mon Feb 24 15:19:01 1997 Martin M. Hunt + + * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to + d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. + +Mon Feb 24 14:33:26 1997 Fred Fish + + * tic80-opc.c (LSI_SCALED): Renamed from this ... + (OFF_SL_BR_SCALED): ... to this, and added the flag + TIC80_OPERAND_BASEREL to the flags word. + (tic80_opcodes): Replace all occurances of LSI_SCALED with + OFF_SL_BR_SCALED. + +Sat Feb 22 21:25:00 1997 Dawn Perchik + + * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. + Change mips_opcodes from const array to a pointer, + and change bfd_mips_num_opcodes from const int to int, + so that we can increase the size of the mips opcodes table + dynamically. + +Sat Feb 22 21:03:47 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Revert change to + store BITNUM values in the table in one's complement form + to match behavior when assembler is given a raw numeric + value for a BITNUM operand. + * tic80-dis.c (print_operand_bitnum): Ditto. + +Fri Feb 21 16:31:18 1997 Martin M. Hunt + + * d30v-opc.c: Removed references to FLAG_X. + +Wed Feb 19 14:51:20 1997 Ian Lance Taylor + + * Makefile.in: Add dependencies on ../bfd/bfd.h as required. + +Tue Feb 18 17:43:43 1997 Martin M. Hunt + + * Makefile.in: Added d30v object files. + * configure: (bfd_d30v_arch) Rebuilt. + * configure.in: (bfd_d30v_arch) Added new case. + * d30v-dis.c: New file. + * d30v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d30v. + +Tue Feb 18 16:32:08 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Add symbolic + representations for the floating point BITNUM values. + +Fri Feb 14 12:14:05 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values + in the table in one's complement form, as they appear in the + actual instruction. + (tic80_symbol_to_value): Use macros to access predefined + symbol fields. + (tic80_value_to_symbol): Ditto. + (tic80_next_predefined_symbol): New function. + * tic80-dis.c (print_operand_bitnum): Remove code that did + one's complement for BITNUM values. + +Thu Feb 13 21:56:51 1997 Klaus Kaempf + + * makefile.vms: Remove 8 bit characters. Update to latest + gcc release. + +Thu Feb 13 20:41:22 1997 Philippe De Muyter + + * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction. + +Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (IMM16_PCREL): This is a signed operand. + (IMM24_PCREL): Likewise. + +Thu Feb 13 13:28:43 1997 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base + address for an extended PC relative instruction that is not a + branch. + +Wed Feb 12 12:27:40 1997 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and + bytes_per_line. + +Tue Feb 11 16:36:31 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. + (tic80_opcodes): Sort entries so that long immediate forms + come after short immediate forms, making it easier for + assembler to select the right one for a given operand. + +Tue Feb 11 15:26:47 1997 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and + display_endian. + (print_insn_mips16): Likewise. + +Mon Feb 10 10:12:41 1997 Fred Fish + + * tic80-opc.c (tic80_symbol_to_value): Changed to accept + a symbol class that restricts translation to just that + class (general register, condition code, etc). + +Thu Feb 6 17:34:09 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, + and REG_DEST_E for register operands that have to be + an even numbered register. Add REG_FPA for operands that + are one of the floating point accumulator registers. + Add TIC80_OPERAND_MASK to flags for ENDMASK operand. + (tic80_opcodes): Change entries that need even numbered + register operands to use the new operand table entries. + Add "or" entries that are identical to "or.tt" entries. + +Wed Feb 5 11:12:44 1997 Ian Lance Taylor + + * mips16-opc.c: Add new cases of exit instruction for + disassembler. + * mips-dis.c (print_mips16_insn_arg): Display floating point + registers in operands of exit instruction. Print `$' before + register names in operands of entry and exit instructions. + +Thu Jan 30 14:09:03 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Table of name/value + pairs for all predefined symbols recognized by the assembler. + Also used by the disassembling routines. + (tic80_symbol_to_value): New function. + (tic80_value_to_symbol): New function. + * tic80-dis.c (print_operand_control_register, + print_operand_condition_code, print_operand_bitnum): + Remove private tables and use tic80_value_to_symbol function. + +Thu Jan 30 11:30:45 1997 Martin M. Hunt + + * d10v-dis.c (print_operand): Change address printing + to correctly handle PC wrapping. Fixes PR11490. + +Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative + branches relaxable. + +Tue Jan 28 15:57:34 1997 Ian Lance Taylor + + * mips-dis.c (print_insn_mips16): Set insn_info information. + (print_mips16_insn_arg): Likewise. + + * mips-dis.c (print_insn_mips16): Better handling of an extend + opcode followed by an instruction which can not be extended. + +Fri Jan 24 12:08:21 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Changed operand specifier for the + coldfire moveb instruction to not allow an address register as + destination. Although the documentation does not indicate that + this is invalid, experiments uncovered unexpected behavior. + Added a comment explaining the situation. Thanks to Andreas + Schwab for pointing this out to me. + +Wed Jan 22 20:13:51 1997 Fred Fish + + * tic80-opc.c (tic80_opcodes): Expand comment to note that the + entries are presorted so that entries with the same mnemonic are + adjacent to each other in the table. Sort the entries for each + instruction so that this is true. + +Mon Jan 20 12:48:57 1997 Andreas Schwab + + * m68k-dis.c: Include . + (print_insn_m68k): Sort the opcode table on the most significant + nibble of the opcode. + +Sat Jan 18 15:15:05 1997 Fred Fish + + * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", + "vsub", "vst", "xnor", and "xor" instructions. + (V_a1): Renamed from V_a, msb of accumulator reg number. + (V_a0): Add macro, lsb of accumulator reg number. + +Fri Jan 17 18:24:31 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Broke excessively long + function up into several smaller ones and arranged for + the instruction printing function to be callable recursively + to print vector instructions that have both a load and a + math instruction packed into a single opcode. + * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode + to explain why it comes after the other vector opcodes. + +Fri Jan 17 16:19:15 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire + move insns to handle immediate operands. + +Thu Jan 17 16:19:00 1997 Andreas Schwab + + * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". + fix operand mask in the "moveml" entries for the coldfire. + +Thu Jan 16 20:54:40 1997 Fred Fish + + * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): + New macros for building vector instruction opcodes. + (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and + FMT_LI, which were unused. The field is now a flags field. + Remove some opcodes that are possible, but illegal, such + as long immediate instructions with doubles for immediate + values. Add "vadd" and "vld" instructions. + +Wed Jan 15 18:59:51 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Reorder some table entries to make + the order more logical. Move the shift alias instructions ("rotl", + "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be + interspersed with the regular sr.x and sl.x instructions. Add + and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", + "sub", "subu", "swcr", and "trap". + +Tue Jan 14 19:42:50 1997 Fred Fish + + * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. + (OFF_SL_PC): Renamed from OFF_SL. + (OFF_SS_BR): New operand type for base relative operand. + (OFF_SL_BR): New operand type for base relative operand. + (REG_BASE): New operand type for base register operand. + (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", + "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", + "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" + instructions. + * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width + 10 char field, padded with spaces on rhs, rather than a string + followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather + than old TIC80_OPERAND_RELATIVE. Add support for new + TIC80_OPERAND_BASEREL flag bit. + +Mon Jan 13 15:58:56 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Print floating point operands + as floats. + * tic80-opc.c (SPFI): Add single precision floating point + immediate operand type. + (ROTATE): Add rotate operand type for shifts. + (ENDMASK): Add for shifts. + (n): Macro for the 'n' bit. + (i): Macro for the 'i' bit. + (PD): Macro for the 'PD' field. + (P2): Macro for the 'P2' field. + (P1): Macro for the 'P1' field. + (tic80_opcodes): Add entries for "exts", "extu", "fadd", + "fcmp", and "fdiv". + +Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): Mask off unwanted bits after + adding in current address for pc-relative operands. + +Mon Jan 6 10:56:25 1997 Fred Fish + + * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. + (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. + * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names + changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. + (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, + REG_BASE_M_SI, REG_BASE_M_LI respectively. + (REG_SCALED, LSI_SCALED): New operand types. + (E): New macro for 'E' bit at bit 27. + (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap + opcodes, including the various size flavors (b,h,w,d) for + the direct load and store instructions. + +Sun Jan 5 12:18:14 1997 Fred Fish + + * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit + in an instruction. + * tic80-dis.c (print_insn_tic80): Change comma and paren handling. + Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. + * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. + (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. + (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode + masks with "MASK_* & ~M_*" to get the M bit reset. + (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. + +Sat Jan 4 19:05:05 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE + correctly. Add support for printing TIC80_OPERAND_BITNUM and + TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic + form. + * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, + CC, SICR, and LICR table entries. + (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", + "bcnd", and "brcr" opcodes. + +Fri Jan 3 18:32:11 1997 Fred Fish + + * ppc-opc.c (powerpc_operands): Make comment match the + actual fields (no shift field). + * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". + * tic80-dis.c (print_insn_tic80): Replace abort stub with a + partial implementation, work in progress. + * tic80-opc.c (tic80_operands): Begin construction operands table. + (tic80_opcodes): Continue populating opcodes table and start + filling in the operand indices. + (tic80_num_opcodes): Add this. + +Fri Jan 3 12:13:52 1997 Ian Lance Taylor + + * m68k-opc.c: Add #B case for moveq. + +Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Make sure all variables are initialized + before they are used. + +Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Put curly-braces around operands + for "breakpoint" instruction. + +Tue Dec 31 15:38:13 1996 Ian Lance Taylor + + * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. + (dep): Use ALL_CFLAGS rather than CFLAGS. + +Tue Dec 31 15:09:16 1996 Michael Meissner + + * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY + flag. + +Mon Dec 30 17:02:11 1996 Fred Fish + + * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. + (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. + +Mon Dec 30 11:38:01 1996 Ian Lance Taylor + + * mips16-opc.c: Add "abs". + +Sun Dec 29 10:58:22 1996 Fred Fish + + * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. + * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. + (disassembler): Add bfd_arch_tic80 support to set disassemble + to print_insn_tic80. + * tic80-dis.c (print_insn_tic80): Add stub. + +Fri Dec 27 22:30:57 1996 Fred Fish + + * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. + * configure: Regenerate with autoconf. + * tic80-dis.c: Add file. + * tic80-opc.c: Add file. + +Fri Dec 20 14:30:19 1996 Martin M. Hunt + + * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. + +Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Add SIMM16N. + (mn10200_opcodes): Use it for some logicals and btst insns. + Add "break" and "trap" instructions. + + * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. + + * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". + +Sat Dec 14 22:36:20 1996 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): The base address of a PC + relative load or add now depends upon whether the instruction is + in a delay slot. + +Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c: Finish writing disassembler. + * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". + Fix mask for "jmp (an)". + + * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently + handle endianness issues for mn10300. + + * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". + +Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 + instruction. Fix opcode field for "movb (imm24),dn". + + * mn10200-opc.c (mn10200_operands): Fix insertion position + for DI operand. + +Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Create mn10200 opcode table. + * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, + but moving along nicely. + +Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add mips16-opc.o. + +Fri Dec 6 16:47:40 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Revert change to use < and > + specifiers for fmovem* instructions. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Remove '$' register prefixing. + +Fri Dec 6 17:34:39 1996 Ian Lance Taylor + + * mips16-opc.c: Change opcode for entry/exit to avoid conflicting + with dsrl. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c: Add some comments explaining the various + operands and such. + + * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings. + +Thu Dec 5 12:09:48 1996 J.T. Conklin + + * m68k-dis.c (print_insn_arg): Handle new < and > operand + specifiers. + + * m68k-opc.c (m68k_opcodes): Simplify table by using < and > + operand specifiers in fmovm* instructions. + +Wed Dec 4 14:52:18 1996 Ian Lance Taylor + + * ppc-opc.c (insert_li): Give an error if the offset has the two + least significant bits set. + +Wed Nov 27 13:09:01 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_mips16): Separate the instruction from + the arguments with a tab, not a space. + +Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disasemble): Finish conversion to '$' as + register prefix. + + * mn10300-opc.c (mn10300_opcodes): Fix mask field for + mov am,(imm32,sp). + +Tue Nov 26 10:53:21 1996 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.12. + + Add support for mips16 (16 bit MIPS implementation): + * mips16-opc.c: New file. + * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h". + (mips16_reg_names): New static array. + (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or + after seeing a 16 bit symbol. + (print_insn_little_mips): Likewise. + (print_insn_mips16): New static function. + (print_mips16_insn_arg): New static function. + * mips-opc.c: Add jalx instruction. + * Makefile.in (mips16-opc.o): New target. + * configure.in: Use mips16-opc.o for bfd_mips_arch. + * configure: Rebuild. + +Mon Nov 25 16:15:17 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Simplify table by using < and > + operand specifiers in *save, *restore and movem* instructions. + + * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for + the coldfire. + + * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use + register operands for immediate arithmetic, not, neg, negx, and + set according to condition instructions. + + * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage + specifier of the effective-address operand in immediate forms of + arithmetic instructions. The specifier for the immediate operand + notes how and where the constant will be stored. + +Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" + opcode. + + * mn10300-dis.c (disassemble): Use '$' instead of '%' for + register prefix. + + * mn10300-dis.c (disassemble): Prefix registers with '%'. + +Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Handle register lists. + + * mn10300-opc.c: Fix handling of register list operand for + "call", "ret", and "rets" instructions. + + * mn10300-dis.c (disassemble): Print PC-relative and memory + addresses symbolically if possible. + * mn10300-opc.c: Distinguish between absolute memory addresses, + pc-relative offsets & random immediates. + + * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte + in 7 byte insns. + (disassemble): Handle SPLIT and EXTENDED operands. + +Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c: Rough cut at printing some operands. + + * mn10300-dis.c: Start working on disassembler support. + * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. + + * mn10300-opc.c (mn10300_operands): Add "REGS" for a register + list. + (mn10300_opcodes): Use REGS for register list in "movm" instructions. + +Mon Nov 18 15:20:35 1996 Michael Meissner + + * d10v-opc.c (d10v_opcodes): Add3 sets the carry. + +Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Demand parens around + register argument is calls and jmp instructions. + +Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and + getx operand. Fix opcode for mulqu imm,dn. + +Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Hijack "bits" field + in MN10300_OPERAND_SPLIT operands for how many bits + appear in the basic insn word. Add IMM32_HIGH24, + IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. + (mn10300_opcodes): Use new operands as needed. + + * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 + for bset, bclr, btst instructions. + (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. + + * mn10300-opc.c (mn10300_operands): Remove many redundant + operands. Update opcode table as appropriate. + (IMM32): Add MN10300_OPERAND_SPLIT flag. + (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. + +Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 + operands (for indexed load/stores). Fix bitpos for DI + operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the + few instructions that insert immediates/displacements in the + middle of the instruction. Add IMM8E for 8 bit immediate in + the extended part of an instruction. + (mn10300_operands): Use new opcodes as appropriate. + +Tue Nov 5 10:30:51 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Declare the trap instruction + sequential so the assembler never parallelizes it with + other instructions. + +Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for + a data/address register that appears in register field 0 + and register field 1. + (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN + +Fri Nov 1 10:29:11 1996 Richard Henderson + + * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for + standard disassembly. + + * alpha-opc.c (alpha_operands): Rearrange flags slot. + (alpha_opcodes): Add new BWX, CIX, and MAX instructions. + Recategorize PALcode instructions. + +Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Add relaxing "jbr". + +Tue Oct 29 16:30:28 1996 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Don't print a trailing tab if + there are no operand types. + +Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (D9_RELAX): Renamed from D9, all references + changed. + (v850_operands): Make sure D22 immediately follows D9_RELAX. + +Fri Oct 25 12:12:53 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. + +Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w + and sst.w instructions. + + * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for + "bCC"instructions). + +Thu Oct 24 17:21:20 1996 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Use a tab between the instruction + and the arguments. + +Tue Oct 22 23:32:56 1996 Ian Lance Taylor + + * ppc-opc.c (PPCPWR2): Define. + (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating + it. + +Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode + field for movhu instruction. + + * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, + cast value to "long" not "signed long" to keep hpux10 + compiler quiet. + +Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field + for mov (abs16),DN. + + * mn10300-opc.c (FMT*): Remove definitions. + + * mn10300-opc.c (mn10300_opcodes): Fix destination register + for shift-by-register opcodes. + + * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM + into [AD][MN][01] for encoding the position of the register + in the opcode. + +Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, + "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". + +Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. + Fix various typos. Add "PAREN" operand. + (MEM, MEM2): Define. + (mn10300_opcodes): Surround all memory addresses with "PAREN" + operands. Fix several typos. + + * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's + changes. + +Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (FMT_XX): Renumber starting at one. + (mn10300_operands): Rough cut. Enough to parse "mov" instructions + at this time. + (mn10300_opcodes): Break opcode format out into its own field. + Update many operand fields to deal with signed vs unsigned + issues. Fix one or two typos in the "mov" instruction + opcode, mask and/or operand fields. + +Mon Oct 7 11:39:49 1996 Andreas Schwab + + * m68k-opc.c (plusha): Prefer encoding for m68040up, in case + m68851 wasn't reset. + +Thu Oct 3 17:17:02 1996 Ian Lance Taylor + + * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for + all opcodes. Very rough cut at operands for all opcodes. + + * mn10300-opc.c (mn10300_opcodes): Start fleshing out the + opcode table. + +Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c, mn10300-opc.c: New files. + * mn10200-dis.c, mn10300-dis.c: New files. + * mn10x00-opc.c, mn10x00-dis.c: Deleted. + * disassemble.c: Break mn10x00 support into 10200 and 10300 + support. + * configure.in: Likewise. + * configure: Rebuilt. + +Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. + +Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita + MN10x00 processors. + * disassemble.c (ARCH_mn10x00): Define. + (disassembler): Handle bfd_arch_mn10x00. + * configure.in: Recognize bfd_mn10x00_arch. + * configure: Rebuilt. + +Tue Oct 1 10:49:11 1996 Ian Lance Taylor + + * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses + accordingly. Don't declare functions using op_rtn. + +Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Add memaddr argument. Re-arrange + params to be more standard. + * (disassemble): Print absolute addresses and symbolic names for + branch and jump targets. + * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 + bit operands. + * (v850_opcodes): Add breakpoint insn. + +Mon Sep 23 12:32:26 1996 Ian Lance Taylor + + * m68k-opc.c: Move the fmovemx data register cases before the + other cases, so that they get recognized before the data register + does gets treated as a degenerate register list. + +Tue Sep 17 12:06:51 1996 Ian Lance Taylor + + * mips-opc.c: Add a case for "div" and "divu" with two registers + and a destination of $0. + +Tue Sep 10 16:12:39 1996 Fred Fish + + * mips-dis.c (print_insn_arg): Add prototype. + (_print_insn_mips): Ditto. + +Mon Sep 9 14:26:26 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_arg): Print condition code registers as + $fccN. + +Tue Sep 3 12:09:46 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. + +Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Make static. Provide prototype. + +Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d9, insert_d22): Fix boundary case + in range checks. + +Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Handle insertion of ',', '[' and + ']' characters into the output stream. + * v850-opc.c (v850_opcodes: Remove size field from all opcodes. + Add "memop" field to all opcodes (for the disassembler). + Reorder opcodes so that "nop" comes before "mov" and "jr" + comes before "jarl". + + * v850-dis.c (print_insn_v850): Fix typo in last change. + + * v850-dis.c (print_insn_v850): Properly handle disassembling + a two byte insn at the end of a memory region when the memory + region's size is only two byte aligned. + + * v850-dis.c (v850_cc_names): Fix stupid thinkos. + + * v850-dis.c (v850_reg_names): Define. + (v850_sreg_names, v850_cc_names): Likewise. + (disassemble): Very rough cut at printing operands (unformatted). + + * v850-opc.c (BOP_MASK): Fix. + (v850_opcodes): Fix mask for jarl and jr. + + * v850-dis.c: New file. Skeleton for disassembler support. + * Makefile.in Remove v850 references, they're not needed here. + * configure.in: Add v850-dis.o when building v850 toolchains. + * configure: Rebuilt. + * disassemble.c (disassembler): Call v850 disassembler. + + * v850-opc.c (insert_d8_7, extract_d8_7): New functions. + (insert_d8_6, extract_d8_6): New functions. + (v850_operands): Rename D7S to D7; operand for D7 is unsigned. + Rename D8 to D8_7, use {insert,extract}_d8_7 routines. + Add D8_6. + (IF4A, IF4B): Use "D7" instead of "D7S". + (IF4C, IF4D): Use "D8_7" instead of "D8". + (IF4E, IF4F): New. Use "D8_6". + (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for + sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. + + * v850-opc.c (insert_d16_15, extract_d16_15): New functions. + (v850_operands): Change D16 to D16_15, use special insert/extract + routines. New new D16 that uses the generic insert/extract code. + (IF7A, IF7B): Use D16_15. + (IF7C, IF7D): New. Use D16. + (v850_opcodes): Use IF7C and IF7D for ld.b and st.b. + + * v850-opc.c (insert_d9, insert_d22): Slightly improve error + message. Issue an error if the branch offset is odd. + + * v850-opc.c: Add notes about needing special insert/extract + for all the load/store insns, except "ld.b" and "st.b". + + * v850-opc.c (insert_d22, extract_d22): New functions. + (v850_operands): Use insert_d22 and extract_d22 for + D22 operands. + (insert_d9): Fix range check. + +Fri Aug 30 18:01:02 1996 J.T. Conklin + + * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag + and set bits field to D9 and D22 operands. + +Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Define SR2 operand. + (v850_opcodes): "ldsr" uses R1,SR2. + + * v850-opc.c (v850_opcodes): Fix opcode specs for + sld.w, sst.b, sst.h, sst.w, and nop. + +Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Add null opcode to mark the + end of the opcode table. + +Mon Aug 26 13:35:53 1996 Martin M. Hunt + + * d10v-opc.c (pre_defined_registers): Added register pairs, + "r0-r1", "r2-r3", etc. + +Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Make I16 be a signed operand. + Create I16U for an unsigned 16bit mmediate operand. + (v850_opcodes): Use I16U for "ori", "andi" and "xori". + + * v850-opc.c (v850_operands): Define EP operand. + (IF4A, IF4B, IF4C, IF4D): Use EP. + + * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" + with immediate operand, "movhi". Tweak "ldsr". + + * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] + correct. Get sld.[bhw] and sst.[bhw] closer. + + * v850-opc.c (v850_operands): "not" is a two byte insn + + * v850-opc.c (v850_opcodes): Correct bit pattern for setf. + + * v850-opc.c (v850_operands): D16 inserts at offset 16! + + * v850-opc.c (two): Get order of words correct. + + * v850-opc.c (v850_operands): I16 inserts at offset 16! + + * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system + register source and destination operands. + (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". + + * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix + same thinko in "trap" opcode. + + * v850-opc.c (v850_opcodes): Add initializer for size field + on all opcodes. + + * v850-opc.c (v850_operands): D6 -> DS7. References changed. + Add D8 for 8-bit unsigned field in short load/store insns. + (IF4A, IF4D): These both need two registers. + (IF4C, IF4D): Define. Use 8-bit unsigned field. + (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use + IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand + for "ldsr" and "stsr". + * v850-opc.c (v850_operands): 3-bit immediate for bit insns + is unsigned. + + * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and + short store word (sst.w). + +Thu Aug 22 16:57:27 1996 J.T. Conklin + + * v850-opc.c (v850_operands): Added insert and extract fields, + pointers to functions that handle unusual operand encodings. + +Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Enable "trap". + + * v850-opc.c (v850_opcodes): Fix order of displacement + and register for "set1", "clr1", "not1", and "tst1". + +Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Add "B3" support. + (v850_opcodes): Fix and enable "set1", "clr1", "not1" + and "tst1". + + * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand. + + * v850-opc.c: Close unterminated comment. + +Wed Aug 21 17:31:26 1996 J.T. Conklin + + * v850-opc.c (v850_operands): Add flags field. + (v850_opcodes): add move opcodes. + +Tue Aug 20 14:41:03 1996 J.T. Conklin + + * Makefile.in (ALL_MACHINES): Add v850-opc.o. + * configure: (bfd_v850v_arch) Add new case. + * configure.in: (bfd_v850_arch) Add new case. + * v850-opc.c: New file. + +Mon Aug 19 15:21:38 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. + +Thu Aug 15 13:14:43 1996 Martin M. Hunt + + * d10v-opc.c: Add additional information to the opcode + table to help determinine which instructions can be done + in parallel. + +Thu Aug 15 13:11:13 1996 Stan Shebs + + * mpw-make.sed: Update editing of include pathnames to be + more general. + +Thu Aug 15 16:28:41 1996 James G. Smith + + * arm-opc.h: Added "bx" instruction definition. + +Wed Aug 14 17:00:04 1996 Richard Henderson + + * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. + +Mon Aug 12 14:30:37 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l. + +Fri Aug 9 13:21:59 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER. + +Thu Aug 8 12:43:52 1996 Klaus Kaempf + + * makefile.vms: Update for alpha-opc changes. + +Wed Aug 7 11:55:10 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_i386): Actually return the correct value. + (ONE, OP_ONE): #ifdef out; not used. + +Fri Aug 2 17:47:03 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions. + Changed subi operand type to treat 0 as 16. + +Wed Jul 31 16:21:41 1996 Ian Lance Taylor + + * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose + . + +Wed Jul 31 14:39:27 1996 James G. Smith + + * arm-opc.h: (arm_opcodes): Added halfword and sign-extension + memory transfer instructions. Add new format string entries %h and %s. + * arm-dis.c: (print_insn_arm): Provide decoding of the new + formats %h and %s. + +Fri Jul 26 11:45:04 1996 Martin M. Hunt + + * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. + (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S. + +Fri Jul 26 14:01:43 1996 Ian Lance Taylor + + * alpha-dis.c (print_insn_alpha_osf): Remove. + (print_insn_alpha_vms): Remove. + (print_insn_alpha): Make globally visible. Chose the register + names based on info->flavour. + * disassemble.c: Always return print_insn_alpha for the alpha. + +Thu Jul 25 15:24:17 1996 Martin M. Hunt + + * d10v-dis.c (dis_long): Handle unknown opcodes. + +Thu Jul 25 12:08:09 1996 Martin M. Hunt + + * d10v-opc.c: Changes to support signed and unsigned numbers. + All instructions with the same name that have long and short forms + now end in ".l" or ".s". Divs added. + * d10v-dis.c: Changes to support signed and unsigned numbers. + +Tue Jul 23 11:02:53 1996 Martin M. Hunt + + * d10v-dis.c: Change all functions to use info->print_address_func. + +Mon Jul 22 15:38:53 1996 Andreas Schwab + + * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire + move ccr/sr insns more strict so that the disassembler only + selects them when the addressing mode is data register. + +Mon Jul 22 11:25:24 1996 Martin M. Hunt + * d10v-opc.c (pre_defined_registers): Declare. + * d10v-dis.c (print_operand): Now uses pre_defined_registers + to pick a better name for the registers. + +Mon Jul 22 13:47:23 1996 Ian Lance Taylor + + * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix + operands for fexpand and fpmerge. From Christian Kuehnke + . + +Mon Jul 22 13:17:06 1996 Richard Henderson + + * alpha-dis.c (print_insn_alpha): No longer the user-visible + print routine. Take new regnames and cpumask arguments. + Kill the environment variable nonsense. + (print_insn_alpha_osf): New function. Do OSF/1 style regnames. + (print_insn_alpha_vms): New function. Do VMS style regnames. + * disassemble.c (disassembler): Test bfd flavour to pick + between OSF and VMS routines. Default to OSF. + +Thu Jul 18 17:19:34 1996 Ian Lance Taylor + + * configure.in: Call AC_SUBST (INSTALL_SHLIB). + * configure: Rebuild. + * Makefile.in (install): Use @INSTALL_SHLIB@. + +Wed Jul 17 14:39:05 1996 Martin M. Hunt + + * configure: (bfd_d10v_arch) Add new case. + * configure.in: (bfd_d10v_arch) Add new case. + * d10v-dis.c: New file. + * d10v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d10v. + +Wed Jul 17 10:12:05 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating + to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. + +Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to + distinguish between variants of the instruction set. + * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to + distinguish between variants of the instruction set. + +Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c (print_insn_i8086): New routine to disassemble using + the 8086 instruction set. + * i386-dis.c: General cleanups. Make most things static. Add + prototypes. Get rid of static variables aflags and dflags. Pass + them as args (to almost everything). + +Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. + + * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". + + * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two + if the next arg is marked with SRC_IN_DST. Gross. + + * h8300-dis.c (bfd_h8_disassemble): Print "exr" when + we're looking for and find EXR. + + * h8300-dis.c (bfd_h8_disassemble): We don't have a match + if we're looking for KBIT and we don't find it. + + * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits + for L_3 and L_2. + + * h8300-dis.c (bfd_h8_disassemble): Don't set plen for + 3bit immediate operands. + +Tue Jul 9 10:55:20 1996 Ian Lance Taylor + + * Released binutils 2.7. + + * alpha-opc.c: Add new case of "mov". From Klaus Kaempf + . + +Thu Jul 4 11:42:51 1996 Ian Lance Taylor + + * alpha-opc.c: Correct second case of "mov" to use OPRL. + +Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) + + * sparc-dis.c (print_insn_sparclite): New routine to print + sparclite instructions. + +Wed Jul 3 14:21:18 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Add coldfire support. + +Fri Jun 28 15:53:51 1996 Doug Evans + + * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, + #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L + to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. + +Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): + Use autoconf-set values. + (docdir, oldincludedir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + +Fri Jun 21 13:53:36 1996 Richard Henderson + + * alpha-opc.c: New file. + * alpha-opc.h: Remove. + * alpha-dis.c: Complete rewrite to use new opcode table. + * configure.in: For bfd_alpha_arch, use alpha-opc.o. + * configure: Rebuild with autoconf 2.10. + * Makefile.in (ALL_MACHINES): Add alpha-opc.o. + (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not + alpha-opc.h. + (alpha-opc.o): New target. + +Wed Jun 19 15:55:12 1996 Ian Lance Taylor + + * sparc-dis.c (print_insn_sparc): Remove unused local variable i. + Set imm_added_to_rs1 even if the source and destination register + are not the same. + + * sparc-opc.c: Add some two operand forms of the wr instruction. + +Tue Jun 18 15:58:27 1996 Jeffrey A. Law + + * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument + to just "mode". + + * disassemble.c (disassembler): Handle H8/S. + * h8300-dis.c (print_insn_h8300s): New function for H8/S. + +Tue Jun 18 18:06:50 1996 Ian Lance Taylor + + * sparc-opc.c: Add beq/teq as aliases for be/te. + + * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko + . + +Tue Jun 18 15:08:54 1996 Klaus Kaempf + + * makefile.vms: New file. + + * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. + +Mon Jun 10 18:50:38 1996 Ian Lance Taylor + + * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, + regardless of plen. + +Tue Jun 4 09:15:53 1996 Doug Evans + + * i386-dis.c (OP_OFF): Call append_prefix. + +Thu May 23 15:18:23 1996 Michael Meissner + + * ppc-opc.c (instruction encoding macros): Add explicit casts to + unsigned long to silence a warning from the Solaris PowerPC + compiler. + +Thu Apr 25 19:33:32 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions. + +Mon Apr 22 17:12:35 1996 Doug Evans + + * sparc-dis.c (X_IMM,X_SIMM): New macros. + (X_IMM13): Delete. + (print_insn_sparc): Merge cases i,I,j together. New cases X,Y. + * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants, + Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt, + cpush, cpusha, cpull sparclet insns. + +Wed Apr 17 14:20:22 1996 Doug Evans + + * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R. + +Thu Apr 11 17:30:02 1996 Ian Lance Taylor + + * sparc-opc.c: Set F_FBR on floating point branch instructions. + Set F_FLOAT on other floating point instructions. + +Mon Apr 8 17:02:48 1996 Michael Meissner + + * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and + registers. + (powerpc_opcodes): Add 860/821 specific SPRs. + +Mon Apr 8 14:00:44 1996 Ian Lance Taylor + + * configure.in: Permit --enable-shared to specify a list of + directories. Set and substitute BFD_PICLIST. + * configure: Rebuild. + * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all + uses. Set to @BFD_PICLIST@. + +Fri Apr 5 17:12:27 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates, + not "abs", which may be needed for the absolute in something + like btst #0,@10:8. Print L_3 immediates separately from other + immediates. Change ABSMOV reference to ABS8MEM. + +Wed Apr 3 10:40:45 1996 Doug Evans + + * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc. + (current_arch_mask): New static global. + (compute_arch_mask): New static function. + (print_insn_sparc): Delete sparc_v9_p. New static local + current_mach. Resort opcode table if current_mach changes. + Generalize "insn not supported" test. + (compare_opcodes): Prefer supported opcodes to nonsupported ones. + Delete test for v9/!v9. + * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. + (v6notlet): Define. + (brfc): Split into CBR and FBR for coprocessor/fp branches. + (brfcx): Renamed to FBRX. + (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard + coprocessor mnemonics are not supported on the sparclet). + (condf): Renamed to CONDF. + (SLCBCC2): Delete F_ALIAS flag. + +Sat Mar 30 21:45:59 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): rd must be 0 for + mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX. + +Fri Mar 29 13:02:40 1996 Ian Lance Taylor + + * Makefile.in (config.status): Depend upon BFD VERSION file, so + that the shared library version number is set correctly. + +Tue Mar 26 15:47:14 1996 Ian Lance Taylor + + * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From + Miles Bader . + * configure: Rebuild. + +Sat Mar 16 13:04:07 1996 Fred Fish + + * z8kgen.c (internal, gas): Call xmalloc rather than unchecked + malloc. + +Tue Mar 12 12:14:10 1996 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.8. + +Thu Mar 7 15:11:10 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'. + * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'. + +Tue Mar 5 15:51:57 1996 Ian Lance Taylor + + * configure.in: Don't set SHLIB or SHLINK to an empty string, + since they appear as targets in Makefile.in. + * configure: Rebuild. + +Mon Feb 26 13:03:40 1996 Stan Shebs + + * mpw-make.sed: Edit out shared library support bits. + +Tue Feb 20 20:48:28 1996 Doug Evans + + * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET. + (sparc_opcode_archs): Add MASK_V8 to sparclet entry. + (sparc_opcodes): Add sparclet insns. + (sparclet_cpreg_table): New static local. + (sparc_{encode,decode}_sparclet_cpreg): New functions. + * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs. + +Tue Feb 20 11:02:44 1996 Alan Modra + + * i386-dis.c (index16): New static variable. + (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the + other way around. + (OP_indirE): Return result of OP_E. + (OP_E): Check for 16 bit addressing mode, and disassemble + correctly. Optimised 32 bit case a little. Don't print + "(base,index,scale)" when sib specifies only an offset. + +Mon Feb 19 12:32:17 1996 Ian Lance Taylor + + * configure.in: Set and substitute SHLIB_DEP. + * configure: Rebuild. + * Makefile.in (SHLIB_DEP): New variable. + (LIBIBERTY_LISTS, BFD_LIST): New variables. + (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If + COMMON_SHLIB, add them to piclist with appropriate modifications. + ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB + here: just use piclist. + +Mon Feb 19 02:03:50 1996 Doug Evans + + * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define. + (print_insn_sparc): Rewrite v9/not-v9 tests. + (compare_opcodes): Likewise. + * sparc-opc.c (MASK_): Define. + (v6,v7,v8,sparclite,v9,v9a): Redefine. + (sparclet,v6notv9): Define. + (sparc_opcode_archs): Delete member `conflicts'. Add `supported'. + (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead. + +Thu Feb 15 14:45:05 1996 Ian Lance Taylor + + * configure.in: Call AC_PROG_CC before configure.host. + * configure: Rebuild. + + * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB). + +Wed Feb 14 19:01:27 1996 Alan Modra + + * i386-dis.c (onebyte_has_modrm): New static array. + (twobyte_has_modrm): New static array. + (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed. + +Tue Feb 13 15:15:01 1996 Ian Lance Taylor + + * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not + $(SHLINK). + +Mon Feb 12 16:26:06 1996 Michael Meissner + + * ppc-opc.c (PPC): Undef, so default defination on Windows NT + doesn't conflict. + +Wed Feb 7 13:59:54 1996 Ian Lance Taylor + + * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on + m68010up, not just m68020up | cpu32. + + * Makefile.in (SONAME): New variable. + ($(SHLINK)): Make a link to the transformed name, as well. + (stamp-tshlink): New target. + (install): Skip stamp-tshlink during install. + +Tue Feb 6 12:28:54 1996 Ian Lance Taylor + + * configure.in: Call AC_ARG_PROGRAM. + * configure: Rebuild. + * Makefile.in (program_transform_name): New variable. + (install): Transform library name before installing it. + +Mon Feb 5 16:14:42 1996 Ian Lance Taylor + + * i960-dis.c (mem): Add HX dcinva instruction. + + Support for building as a shared library, based on patches from + Alan Modra : + * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib. + New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC, + SHLIB_CFLAGS, COMMON_SHLIB, SHLINK. + * configure: Rebuild. + * Makefile.in (ALLLIBS): New variable. + (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables. + (COMMON_SHLIB, SHLINK): New variables. + (.c.o): If PICFLAG is set, compile twice, once PIC, once normal. + (STAGESTUFF): Remove variable. + (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB). + (stamp-piclist, piclist): New targets. + ($(SHLIB), $(SHLINK)): New targets. + ($(OFILES)): Depend upon stamp-picdir. + (disassemble.o): Build twice if PICFLAG is set. + (MOSTLYCLEAN): Add pic/*.o. + (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist. + (distclean): Remove pic and stamp-picdir. + (install): Install shared libraries. + (stamp-picdir): New target. + +Fri Feb 2 17:15:25 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support. + Print unknown instruction as "unknown", rather than in hex. + +Tue Jan 30 14:06:08 1996 Ian Lance Taylor + + * dis-buf.c: Include "sysdep.h" before "dis-asm.h". + +Thu Jan 25 20:24:07 1996 Doug Evans + + * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting. + +Thu Jan 25 11:56:49 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte + when necessary. From Ulrich Drepper + . + +Thu Jan 25 03:39:10 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with + sparc_num_opcodes. Update architecture enum values. + * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. + (sparc_opcode_lookup_arch): New function. + (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. + (sparc_opcodes): Add v9a shutdown insn. + +Mon Jan 22 08:29:59 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Renamed from print_insn. + If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode + architecture. + (print_insn_sparc64): Deleted. + * disassemble.c (disassembler, case bfd_arch_sparc): Always use + print_insn_sparc. + + * sparc-opc.c (architecture_pname): Add v9a. + +Fri Jan 12 14:35:58 1996 David Mosberger-Tang + + * alpha-opc.h (alpha_insn_set): VAX floating point opcode was + incorrectly defined as 0x16 when it should be 0x15. + (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits! + (alpha_insn_set): added cvtst and cvttq float ops. Also added + excb (exception barrier) which is defined in the Alpha + Architecture Handbook version 2. + * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for + OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be + disassembled as or, for example. + +Wed Jan 10 12:37:22 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex. + (_print_insn_mips): Change i from int to unsigned int. + +Thu Jan 4 17:21:10 1996 David Edelsohn + + * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different + from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli. + +Thu Dec 28 13:29:19 1995 John Hassey + + * i386-dis.c: Added Pentium Pro instructions. + +Tue Dec 19 22:56:35 1995 Michael Meissner + + * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to + being for Power2. + +Fri Dec 15 14:14:15 1995 J.T. Conklin + + * sh-opc.h (sh_nibble_type): Added REG_B. + (sh_arg_type): Added A_REG_B. + (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc + and stc.l opcodes. + * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B. + +Fri Dec 15 16:44:31 1995 Ian Lance Taylor + + * disassemble.c (disassembler): Use new bfd_big_endian macro. + +Tue Dec 12 12:22:24 1995 Ian Lance Taylor + + * Makefile.in (distclean): Remove stamp-h. From Ronald + F. Guilmette . + +Tue Dec 5 13:42:44 1995 Stan Shebs + + From David Mosberger-Tang : + * alpha-dis.c (print_insn_alpha): fixed decoding of cpys + instruction. + +Mon Dec 4 12:29:05 1995 J.T. Conklin + + * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. + (sh_table): Added many SH3 opcodes. + * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC. + +Fri Dec 1 07:42:18 1995 Michael Meissner + + * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC. + (subco,subco.): Mark this PPC, not PPCCOM. + +Mon Nov 27 13:09:52 1995 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.7. + +Tue Nov 21 18:28:06 1995 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.6. + +Wed Nov 15 19:02:53 1995 Ken Raeburn + + * configure.in: Sort list of architectures. Accept but do nothing + for alliant, convex, pyramid, romp, and tahoe. + +Wed Nov 8 20:18:59 1995 Ian Lance Taylor + + * a29k-dis.c (print_special): Change num to unsigned int. + +Wed Nov 8 20:10:35 1995 Eric Freudenthal + + * a29k-dis.c (print_insn): Cast insn24 to unsigned long when + shifting it. + +Tue Nov 7 15:21:06 1995 Ian Lance Taylor + + * configure.in: Call AC_CHECK_PROG to find and cache AR. + * configure: Rebuilt. + +Mon Nov 6 17:39:47 1995 Harry Dolan + + * configure.in: Add case for bfd_i860_arch. + * configure: Rebuild. + +Fri Nov 3 12:45:31 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcodes): Correct fmoveml operands. + * m68k-dis.c (NEXTSINGLE): Change i to unsigned int. + (NEXTDOUBLE): Likewise. + (print_insn_m68k): Don't match fmoveml if there is more than one + register in the list. + (print_insn_arg): Handle a place of '8' for a type of 'L'. + +Thu Nov 2 23:06:33 1995 Ian Lance Taylor + + * m68k-opc.c: Use #W rather than #w. + * m68k-dis.c (print_insn_arg): Handle new 'W' place. + +Wed Nov 1 13:30:24 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf, + and likewise for all the dbxx opcodes. + +Mon Oct 30 20:50:40 1995 Fred Fish + + * arc-dis.c: Include elf-bfd.h rather than libelf.h. + +Mon Oct 23 11:11:34 1995 James G. Smith + + * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added + the VR4100 specific instructions to the mips_opcodes structure. + +Thu Oct 19 11:05:23 1995 Stan Shebs + + * mpw-config.in, mpw-make.sed: Remove ugly workaround for + ugly Metrowerks bug in CW6, is fixed in CW7. + +Mon Oct 16 12:59:01 1995 Michael Meissner + + * ppc-opc.c (whole file): Add flags for common/any support. + +Tue Oct 10 11:06:07 1995 Fred Fish + + * Makefile.in (BISON): Remove macro. + (FLAGS_TO_PASS): Remove BISON. + +Fri Oct 6 16:26:45 1995 Ken Raeburn + + Mon Sep 25 22:49:32 1995 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Recognize all two-word + instructions that take no args by looking at the match mask. + (print_insn_arg): Always print "%" before register names. + [case 'c']: Use "nc" for the no-cache case, as recognized by gas. + [case '_']: Don't print "@#" before address. + [case 'J']: Use "%s" as format string, not register name. + [case 'B']: Treat place == 'C' like 'l' and 'L'. + +Thu Oct 5 22:16:20 1995 Ken Raeburn + + * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode + name correctly. + +Tue Oct 3 08:30:20 1995 steve chamberlain + + From David Mosberger-Tang + + * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added. + (alpha_insn_set): added definitions for VAX floating point + instructions (Unix compilers don't generate these, but handcoded + assembly might still use them). + + * alpha-dis.c (print_insn_alpha): added support for disassembling + the miscellaneous instructions in the Alpha instruction set. + +Tue Sep 26 18:47:20 1995 Stan Shebs + + * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k, + no longer create sysdep.h, sed ppc-opc.c to work around a + serious Metrowerks C bug. + * mpw-make.in: Remove. + * mpw-make.sed: New file, used by mpw-configure to edit + Makefile.in into an MPW makefile. + +Wed Sep 20 12:55:28 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Tue Sep 19 15:28:36 1995 Ian Lance Taylor + + * m68k-opc.c: Split pmove patterns which use 'P' into patterns + which use '0', '1', and '2' instead. Specify the proper size for + a pmove immediate operand. Correct the pmovefd patterns to be + moves to a register, not from a register. + * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'. + +Thu Sep 14 11:58:22 1995 Doug Evans + + * sparc-opc.c (sparc_opcodes): Mark all insns that reference + %psr, %wim, %tbr as F_NOTV9. + +Fri Sep 8 01:07:38 1995 Ian Lance Taylor + + * Makefile.in (Makefile): Just rebuild Makefile when running + config.status. + (config.h, stamp-h): New targets. + * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM + earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when + rebuilding config.h. + * configure: Rebuild. + + * mips-opc.c: Change unaligned loads and stores with "t,A" + operands to use "t,A(b)". + +Thu Sep 7 19:02:46 1995 Jim Wilson + + * sh-dis.c (print_insn_shx): Add F_FR0 support. + +Thu Sep 7 19:02:46 1995 Jim Wilson + + * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate + until 3 instead of until 2. + +Wed Sep 6 21:21:33 1995 Ian Lance Taylor + + * Makefile.in (ALL_CFLAGS): Define. + (.c.o, disassemble.o): Use $(ALL_CFLAGS). + (MOSTLYCLEAN): Add config.log. + (distclean): Don't remove config.log. + * configure.in: Substitute HDEFINES. + * configure: Rebuild. + +Wed Sep 6 15:08:09 1995 Jim Wilson + + * sh-opc.h (sh_arg_type): Add F_FR0. + (sh_table, case fmac): Add F_FR0 as first argument. + +Wed Sep 6 15:08:09 1995 Jim Wilson + + * sh-opc.h (sh_opcode_info): Increase arg array size to 4. + +Tue Sep 5 18:28:10 1995 Doug Evans + + * sparc-dis.c: Remove all references to NO_V9. + +Tue Sep 5 20:03:26 1995 Ian Lance Taylor + + * aclocal.m4: Just include ../bfd/aclocal.m4. + * configure: Rebuild. + +Tue Sep 5 16:09:59 1995 Doug Evans + + * sparc-dis.c (X_DISP19): Define. + (print_insn, case 'G'): Use it. + (print_insn, case 'L'): Sign extend displacement. + +Mon Sep 4 14:28:46 1995 Ian Lance Taylor + + * configure.in: Run ../bfd/configure.host before AC_PROG_CC. + Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute + host_makefile_frag or frags. + * aclocal.m4: New file. + * configure: Rebuild. + * Makefile.in (INSTALL): Set to @INSTALL@. + (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@. + (INSTALL_DATA): Set to @INSTALL_DATA@. + (AR): Set to @AR@. + (AR_FLAGS): Set to rc rather than qc. + (CC): Define as @CC@. + (CFLAGS): Set to @CFLAGS@. + (@host_makefile_frag@): Remove. + (config.status): Remove dependency upon @frags@. + + * configure.in: ../bfd/config.bfd now just sets shell variables. + Use them rather than looking through target Makefile fragments. + * configure: Rebuild. + +Thu Aug 31 12:35:32 1995 Jim Wilson + + * sh-opc.h (ftrc): Change FPUL_N to FPUL_M. + +Wed Aug 30 13:52:28 1995 Doug Evans + + * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn. + Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic + sparc64 insns. + + * sparc-opc.c (sparc_opcodes): Fix prefetcha insn. + (lookup_{name,value}): New functions. + (prefetch_table): New static local. + (sparc_{encode,decode}_prefetch): New functions. + * sparc-dis.c (print_insn): Handle '*' arg (prefetch function). + +Wed Aug 30 11:11:58 1995 Jim Wilson + + * sh-opc.h: Add blank lines to improve readabililty of sh3e + instructions. + +Wed Aug 30 11:09:38 1995 Jim Wilson + + * sh-dis.c: Correct comment on first line of file. + +Tue Aug 29 15:37:18 1995 Doug Evans + + * disassemble.c (disassembler): Handle bfd_mach_sparc64. + + * sparc-opc.c (asi, membar): New static locals. + (sparc_{encode,decode}_{asi,membar}): New functions. + (sparc_opcodes, membar insn): Fix. + * sparc-dis.c (print_insn): Call sparc_decode_asi. + Support decoding of membar masks. + (X_MEMBAR): Define. + +Sat Aug 26 21:22:48 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl. + +Mon Aug 21 17:33:36 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis, + and likewise for the other branches. Add bhs as an alias for bcc, + and likewise for the size variants. Add dbhs as an alias for + dbcc. + +Fri Aug 11 13:40:24 1995 Jeff Law (law@snake.cs.utah.edu) + + * sh-opc.h (FP sts instructions): Update to match reality. + +Mon Aug 7 16:12:58 1995 Ian Lance Taylor + + * m68k-dis.c: (fpcr_names): Add % before all register names. + (reg_names): Likewise. + (print_insn_arg): Don't explicitly print % before register names. + Add % before register names in static array names. In case 'r', + print data registers as `@(Dn)', not `Dn@'. When printing a + memory address, don't print @# before it. + (print_indexed): Change base_disp and outer_disp from int to + bfd_vma. Print using MIT syntax, not mutant invalid Motorola + syntax. Sign extend 8 byte displacement correctly. + (print_base): Print using MIT syntax. Print zpc when appropriate. + Change parameter disp from int to bfd_vma. + + * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases + for jsr. + +Mon Aug 7 02:21:40 1995 Jeff Law (law@snake.cs.utah.edu) + + * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, + F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. + * sh-opc.h (sh_arg_type): Add new operand types. + (sh_table): Add new opcodes from SH3E Floating Point ISA. + +Sat Aug 5 16:50:14 1995 Fred Fish + + * Makefile.in (distclean): Remove generated file config.h. + +Sat Aug 5 16:50:14 1995 Fred Fish + + * Makefile.in (distclean): Remove generated file config.h. + +Wed Aug 2 18:33:40 1995 Ian Lance Taylor + + * m68k-opc.c: New file, holding tables from include/opcode/m68k.h. + Clean up tables. + * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff. + (opcode): Remove. + (print_insn_m68k): Change d to be const. Use m68k_numopcodes + rather than numopcodes. Use m68k_opcodes rather than removed + opcode function. Don't check F_ALIAS. + (print_insn_arg): Change first parameter to be const char *. + * Makefile.in (ALL_MACHINES): Add m68k-opc.o. + (m68k-opc.o): New target. + * configure.in: Build m68k-opc.o for bfd_m68k_arch. + * configure: Rebuild. + +Wed Aug 2 08:23:38 1995 Doug Evans + + * sparc-dis.c (HASH_SIZE, HASH_INSN): Define. + (opcode_bits, opcode_hash_table): New variables. + (opcodes_initialized): Renamed from opcodes_sorted. + (build_hash_table): New function. + (is_delayed_branch): Use hash table. + (print_insn): Renamed from print_insn_sparc, made static. + Build and use hash table. If !sparc64, ignore sparc64 insns, + and vice-versa if sparc64. + (print_insn_sparc, print_insn_sparc64): New functions. + (compare_opcodes): Move sparc64 opcodes to end. + Print commutative insns with constant second. + * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS. + +Tue Aug 1 00:12:49 1995 Ian Lance Taylor + + * sh-dis.c (print_insn_shx): Remove unused local dslot. Use + print_address_func for A_BDISP12 and A_BDISP8. Correct test which + avoids printing a delay slot in a delay slot. + * sh-opc.h (sh_table): Fully bracket last entry. + +Mon Jul 31 12:04:47 1995 Doug Evans + + * sparc-opc.c (sllx, srax, srlx): Fix disassembly. + +Wed Jul 12 00:59:34 1995 Ken Raeburn + + * configure.in: Get host_makefile_frag from ${srcdir}. + + * configure.in: Autoconfiscated. Check for string[s].h. Create + config.h from config.in. Don't set up sysdep.h link. + * sysdep.h: New file. + * configure, config.in: New files, generated from configure.in. + * Makefile.in: Updated to be processed autoconf-style. + (distclean): Keep sysdep.h. Remove config.log and config.cache. + (Makefile): Depend on config.status. + (config.status): New rule. + * configure.bat: Update Makefile substitutions. + +Tue Jul 11 14:23:37 1995 Jeff Spiegel + + * mips-opc.c (L1): Define. + (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, + addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, + and wb. + +Tue Jul 11 11:49:49 1995 Ian Lance Taylor + + * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu + if ISA 3 and addu otherwise, replacing or, since some MIPS chips + have multiple add units but only a single logical unit. + + * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3, + shifted by 18, without any insertion or extraction function. + (insert_cr, extract_cr): Remove. + +Wed Jun 21 20:05:39 1995 Ken Raeburn + + * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before + register names. + +Thu Jun 15 17:23:31 1995 Stan Shebs + + * mpw-config.in: Add sh and i386 configs, remove sparc config. + * sh-opc.h: Add copyright. + +Mon Jun 5 03:30:43 1995 Ken Raeburn + + * Makefile.in (crunch-m68k): Delete extra target accidentally + checked in a while ago. + +Wed May 24 16:22:13 1995 Jim Wilson + + * sh-opc.h (sh_table): Add SH3 support. + +Wed May 24 14:16:08 1995 Steve Chamberlain + + * sh-opc.h: Added bsrf and braf. + +Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete + bogus [ls]fm{ea,fd} patterns. + + * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc. + * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and + initialize it from memory. Make function static. + (print_insn_{big,little}_arm): New functions. + * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for + the correct endianness. + +Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com> + + * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from + enum list. + +Wed Apr 19 14:07:03 1995 Michael Meissner + + * m68k-dis.c (opcode): Finish change made by Kung Hsu on April + 17th, so that it builds again using GCC as the compiler. + +Tue Apr 18 12:14:51 1995 Ken Raeburn + + * mips-dis.c (print_insn_little_mips): Cast return value from + bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips + expects an unsigned long, and that might be fewer words of + argument storage (e.g., if bfd_vma is long long on a 32-bit + machine). + (print_insn_big_mips): Likewise with bfd_getb32 value. + (_print_insn_mips): Now static. + +Mon Apr 17 12:23:28 1995 Kung Hsu + + * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because + gcc memory hog problem with initializer is fixed. + +Mon Apr 10 15:55:01 1995 Stan Shebs + + Merge in support for Mac MPW as a host. + (Old change descriptions retained for informational value.) + + * mpw-config.in (archname): Compute from the config. + (BFD_MACHINES, ARCHDEFS): Put into mk.tmp. + + * mpw-config.in (target_arch): Compute from canonical target. + (m68k, mips, powerpc, sparc): Add architectures. + * mpw-make.in (disassemble.c.o): Add. + (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). + + * mpw-config.in (BFD_MACHINES): Set to a default value. + * mpw-make.in (BFD_MACHINES): Remove wired-in value. + + * mpw-make.in (CSEARCH): Add extra-include to search path. + + * mpw-config.in (varargs.h): Don't create. + (sysdep.h): Create using forward-include. + * mpw-make.in (CSEARCH): Add include/mpw to search path. + + * mpw-config.in: New file, MPW version of configure.in. + * mpw-make.in: New file, MPW version of Makefile.in. + +Fri Mar 31 14:23:38 1995 Ken Raeburn + + * alpha-dis.c (print_insn_alpha): Put empty statement after + default label. + +Tue Mar 21 10:51:40 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version. + (low_sign_extend): Likewise. + (get_field): Delete unused function. + (set_field, deposit_14, deposit_21): Likewise. + +Fri Mar 17 15:55:53 1995 J.T. Conklin + + * i386-dis.c: Support for more pentium opcodes. From Guy Harris + (guy@netapp.com). + +Tue Mar 14 00:52:57 1995 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + Sat Feb 11 17:22:41 1995 Klaus Kaempf (kkaempf@didymus.rmi.de) + + * alpha-opc.h (OSF_ASMCODE): define + print pal-code names as defined in App C of the + Alpha Architecture Reference Manual + + * alpha-dis.c: cleaned up output + print stylized code forms as defined in App A.4.3 of the + Alpha Architecture Reference Manual + +Wed Mar 8 15:21:14 1995 Ian Lance Taylor + + * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for + `rfe'. + * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R', + 'N', and 'M'. + +Wed Mar 8 02:54:05 1995 Ken Raeburn + + * m68k-dis.c (opcode): New function. Returns address of opcode + table entry given index, even if the opcode table was split to + work around gcc bugs. + (print_insn_m68k): Call opcode instead of referencing m68k_opcodes + directly. + (BREAK_UP_BIG_DECL): Make secondary array static and const. + (reg_names): Now const. + (print_insn_arg): Arrays cacheFieldName and names now const. + (print_indexed): Array scales now const. + +Tue Mar 7 16:41:21 1995 Ian Lance Taylor + + * ppc-opc.c: Sort recently added instructions by minor opcode + number within major opcode number. + +Mon Mar 6 10:04:36 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c: Include libhppa.h. + +Fri Feb 24 19:15:36 1995 Ian Lance Taylor + + * mips-opc.c: Change dli to use M_DLI, and add dla. + +Mon Feb 20 23:54:38 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add w65-dis.o. + +Thu Feb 16 17:34:41 1995 Ian Lance Taylor + + * mips-opc.c: Add r4650 mul instruction. + +Wed Feb 15 15:45:20 1995 Ian Lance Taylor + + * mips-opc.c: Add uld and usd macros for unaligned double load and + store. + +Tue Feb 14 13:17:37 1995 Michael Meissner + + * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci, + mfdcr, mtdcr, icbt, iccci. + +Thu Feb 9 12:28:13 1995 Stan Shebs + + * i960-dis.c (struct tabent, struct sparse_tabent): Change the + signed char fields to shorts, more portable. + +Wed Feb 8 17:29:29 1995 Stan Shebs + + * i960-dis.c (struct tabent, struct sparse_tabent): Declare the + char fields as signed chars, since they may have negative values. + +Mon Feb 6 10:52:06 1995 J.T. Conklin + + * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum + (mycroft@netbsd.org). + +Mon Jan 30 12:38:00 1995 Ian Lance Taylor + + From "Logg, Ed" : + * ppc-opc.c (extract_bdm): Correct parenthezisation. + * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized + value. + +Thu Jan 26 18:32:08 1995 Ian Lance Taylor + + * ppc-opc.c: Changes based on patch from David Edelsohn + . + (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of + SPR. + (FXM_MASK): Define. + (insert_tbr): New static function. + (extract_tbr): New static function. + (XFXFXM_MASK, XFXM): Define. + (XSPRBAT_MASK, XSPRG_MASK): Define. + (powerpc_opcodes): Add instructions to access special registers by + name. Add mtcr and mftbu. + +Tue Jan 17 10:56:43 1995 Ian Lance Taylor + + * mips-opc.c (P3): Define. + (mips_opcodes): Add mad and madu. + +Sun Jan 15 16:32:59 1995 Steve Chamberlain + + * configure.in: Add W65 support. + * disassemble.c: Likewise. + * w65-opc.h, w65-dis.c: New files. + +Wed Dec 28 22:15:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit + immediates. + +Tue Dec 20 11:25:12 1994 Ian Lance Taylor + + * mips-opc.c: Add dli as a synonym for li. + +Thu Dec 8 18:23:31 1994 Ken Raeburn + + * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and + print something for reserved opcode values, even if it won't + assemble again. + + * mips-dis.c (_print_insn_mips): When initializing, shift right + and mask, to avoid sign extension problems on the Alpha. + + * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr + control registers. + +Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * sh-opc.h (mov.l gbr): Get direction right. + * sh-dis.c (print_insn_shx): New function. + (print_insn_shl, print_insn_sh): Call print_insn_shx to + print opcodes with right byte order. + +Thu Nov 3 19:32:22 1994 Ken Raeburn + + * ns32k-dis.c (struct ns32k_option): Renamed from struct option, + to avoid conflicts with getopt. + +Mon Oct 31 18:48:10 1994 Ian Lance Taylor + + * hppa-dis.c (print_insn_hppa): Read the instruction using + bfd_getb32, so that it works on a little endian or 64 bit host. + Remove unused local variable op. + +Tue Oct 25 17:07:57 1994 Ian Lance Taylor + + * mips-opc.c: Use or instead of addu for pseudo-op move, since + addu does not work correctly if -mips3. + +Wed Oct 19 13:40:16 1994 Ian Lance Taylor + + * a29k-dis.c (print_special): Add special register names defined + on 29030, 29040 and 29050. + (print_insn): Handle new operand type 'I'. + +Wed Oct 12 11:59:55 1994 Ian Lance Taylor + + * Makefile.in (INSTALL): Use top level install.sh script. + +Wed Oct 5 19:16:29 1994 Ian Lance Taylor + + * sparc-dis.c: Rewrite to use bitfields, rather than a union, so + that it works on a little endian host. + +Tue Oct 4 12:14:21 1994 Ian Lance Taylor + + * configure.in: Use ${config_shell} when running config.bfd. + +Wed Sep 21 18:49:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3. + +Thu Sep 15 16:30:22 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * a29k-dis.c (print_insn): Print the opcode. + +Wed Sep 14 17:52:14 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. + +Sun Sep 11 22:32:17 1994 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3. + +Tue Sep 6 11:37:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions + which store a value into memory. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * configure.in, Makefile.in, disassemble.c: Add support for the ARM. + * arm-dis.c, arm-opc.h: New files. + +Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com) + + * Makefile.in (ns32k-dis.o): Add dependency. + * ns32k-dis.c (print_insn_arg): Declare initialized local as + string, not as array of chars. + +Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'. + + * sparc-opc.c: Added sparclite extended FP operations, and + versions of v9 impdep* instructions permitting specification of + the OPF field. + +Tue Jul 26 16:36:03 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960-dis.c (reg_names): Now const. + (struct sparse_tabent): New type, copied from array type in mem + function. + (ctrl): Local static array ctrl_tab now const. + (cobr): Local static array cobr_tab now const. + (mem): Local variables reg1, reg2, reg3 now point to const. Local + static variable mem_tab no longer explicitly initialized. Changed + mem_init to const array of struct sparse_tabent. + (reg): Local static variable reg_tab no longer explicitly + initialized. Changed reg_init to const array of struct + sparse_tabent. + (ea): Local static array scale_tab now const. + + * i960-dis.c (reg): Added i960JX instructions to reg_init table. + (REG_MAX): Updated. + +Tue Jul 19 21:00:00 1994 DJ Delorie (dj@ctron.com) + + * configure.bat: the disassember needs to be enabled for + "objdump -d" to work in djgpp. + +Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * ns32k-dis.c: Deleted all code in "#ifdef GDB". + (invalid_float): Enabled general version, doesn't require running + on ns32k host. Changed to take char* argument, and test for + explicitly specified sizes, instead of using sizeof() on host CPU + types. + (INVALID_FLOAT): Cast first argument. + (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532, + list_P032, list_M032): Now const. + (optlist, list_search): Made appropriate arguments now point to + const. + (print_insn_arg): Changed static array of one-character-string + pointers into a static const array of characters; fixed sprintf + statement accordingly. + +Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * ns32k-dis.c: Semi-new file. Had apparently been dropped + from distribution. A ns32k-dis.c from a previous distribution has + been brought up to date and supports the new interface. + + * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k. + + * configure.in: add bfd_ns32k_arch target support. + + * Makefile.in: add ns32k-dis.o to ALL_MACHINES. + Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o. + +Wed Jun 29 22:10:37 1994 Steve Chamberlain (sac@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch + disassembly right. + +Tue Jun 28 13:22:06 1994 Stan Shebs (shebs@andros.cygnus.com) + + * h8300-dis.c, mips-dis.c: Don't use true and false. + +Thu Jun 23 12:53:19 1994 David J. Mackenzie (djm@rtl.cygnus.com) + + * configure.in: Change --with-targets to --enable-targets. + +Wed Jun 22 13:38:32 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-dis.c (_print_insn_mips): Build a static hash table mapping + opcodes to the first instruction with that opcode, to speed + disassembly of large files. From ralphc@pyramid.com (Ralph + Campbell). + +Tue Jun 7 12:49:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * Makefile.in (mostlyclean): Fix typo (was mostyclean). + +Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) + + * configure.bat: update to latest makefile.in + +Sat May 7 17:13:21 1994 Steve Chamberlain (sac@cygnus.com) + + * a29k-dis.c (print_insn): Print 'x' type operand in hex. + * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly. + * sh-dis.c (print_insn_sh): Don't recur endlessly if delay + slot insn is in a delay slot. + * z8k-opc.h: (resflg): Fix patterns. + * h8500-opc.h Fix CR insn patterns. + +Fri May 6 14:34:46 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and + "cmpl" before POWER versions, so that gas -many uses them. + +Thu Apr 28 18:32:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * disassemble.c: New file. + * Makefile.in (OFILES): Add disassemble.o. + (disassemble.o): Provide dependencies; compile with $(ARCHDEFS). + * configure.in: Define ARCHDEFS in Makefile. Code taken from + binutils/configure.in. + + * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the + opcode being examined. + +Thu Apr 21 17:08:40 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS. + (insert_ral, insert_ram, insert_ras): New functions. + (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and + RAS for store with update. + +Sat Apr 16 23:41:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn + (edelsohn@npac.syr.edu). + +Wed Apr 6 17:11:45 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c (mips_opcodes): Correct operands of "nor" with an + immediate argument. + +Mon Apr 4 16:30:46 1994 Doug Evans (dje@canuck.cygnus.com) + + * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0". + +Mon Apr 4 13:22:00 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): The signedp field has been + removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag + instead. Add new operand SISIGNOPT. + (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT. + Based on patch from David Edelsohn (edelsohn@npac.syr.edu). + * ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather + than signedp field. + +Wed Mar 30 00:31:49 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * i386-dis.c (struct private): Renamed to dis_private. `private' + is a reserved word for dynix cc. + +Mon Mar 28 13:00:15 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in: Change error message to refer to bfd/config.bfd + rather than bfd/configure.in. + +Mon Mar 28 12:28:30 1994 David Edelsohn (edelsohn@npac.syr.edu) + + * ppc-opc.c: Define POWER2 as short alias flag. + (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and + fsqrt. + +Wed Mar 23 12:23:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960-dis.c (print_insn_i960): Don't read a second word for + opcodes 0, 1, 2 and 3. + +Wed Mar 16 15:37:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in: Don't build m68881-ext.o for bfd_m68k_arch. + +Mon Mar 14 14:53:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68881-ext.c: Removed; no longer used. + * Makefile.in: Changed accordingly. + + * m68k-dis.c (ext_format_68881): Don't declare. + (print_insn_m68k): If an instruction uses place 'i', it uses at + least four fixed bytes. + (print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For + extended float, convert to double using floatformat_to_double, not + ieee_extended_to_double, and fetch the data before converting it. + +Tue Mar 8 18:12:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: It's sqrt.s, not sqrt.w. From + davidj@ICSI.Berkeley.EDU (David Johnson). + +Tue Feb 8 16:55:27 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the + PowerPC uses bdnz[l][a]. + +Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * dis-buf.c, i386-dis.c: Include sysdep.h. + +Mon Feb 7 19:22:23 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o. + + * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported + by Motorola PowerPC 601 with PPC_OPCODE_601. + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): + Disassemble Motorola PowerPC 601 instructions as well as normal + PowerPC instructions. + +Sun Feb 6 07:45:17 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * i960-dis.c (reg, mem): Just use a static array instead of + calling xmalloc. + +Sat Feb 5 00:04:02 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the + condition name index if this is for a negated condition. + + * hppa-dis.c (print_insn_hppa): No space before 'H' operand. + Floating point format for 'H' operand is backwards from normal + case (0 == double, 1 == single). For '4', '6', '7', '9', and '8' + operands (fmpyadd and fmpysub), handle bizarre register + translation correctly for single precision format. + + * hppa-dis.c (print_insn_hppa): Do not emit a space after 'F' + or 'I' operands if the next format specifier is 'M' (fcmp + condition completer). + +Feb 4 23:38:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): New operand type MBE to handle a + single number giving a bitmask for the MB and ME fields of an M + form instruction. Change NB to accept 32, and turn it into 0; + also turn 0 into 32 when disassembling. Seperated SH from NB. + (insert_mbe, extract_mbe): New functions. + (insert_nb, extract_nb): New functions. + (SC_MASK): Mask out SA and LK bits. + (powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT, + RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark + "bctr" and "bctrl" as accepted by POWER. Change "rlwimi", + "rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.", + "rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to + use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions. + (powerpc_macros): Define table of macro definitions. + (powerpc_num_macros): Define. + + * ppc-dis.c (print_insn_powerpc): Don't skip optional operands + if PPC_OPERAND_NEXT is set. + +Sat Jan 22 23:10:07 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of + char. Retrieve contents using bfd_getl32 instead of shifting. + +Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c: New file. Opcode table for PowerPC, including + opcodes for POWER (RS/6000). + * ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler. + * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o. + (CFILES): Add ppc-dis.c. + (ppc-dis.o, ppc-opc.o): New targets. + * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch. + +Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. + No space before 'u', 'f', or 'N'. + +Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * i386-dis.c (print_insn_i386): Add FIXME comment regarding reading + farther than we should. + + * i386-dis.c (dis386): Use Yb and Yv for scasb and scasS. + +Thu Jan 6 12:38:05 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments. + +Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * i960-dis.c (print_insn_i960): Only read word2 if the instruction + needs it, to prevent reading past the end of a section. + +Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Use macro for j instruction, to support SVR4 PIC. + Removed t,A case for la; always use t,A(b) case. + +Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + From Ted Lemen + * mips-dis.c (print_insn_arg): Handle 'k'. + * mips-opc.c: Make cache use k, not t. + +Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add + FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct + FLOAT_FORMAT_CODE to put out floating point register names. + +Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Use macros for jal variants, to support SVR4 PIC. + +Thu Oct 28 17:42:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x. + +Wed Oct 27 11:48:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts + larger than 32. Moved dsxx32 variants first for disassembler. + +Mon Oct 25 11:33:14 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * z8kgen.c, z8k-opc.h: Add full lda information. + +Tue Oct 19 12:39:25 1993 Jeffrey A Law (law@cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Do not emit a space after + movb instructions. Any necessary space will be emitted by + the code to handle nullification completers. + +Wed Oct 13 16:19:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Moved l.d down so that it disassembles as ldc1. + +Fri Oct 8 02:34:21 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-opc.h: Add ldl_l, fix typo for ldq_u. + * alpha-dis.c (print_insn_alpha): Add code for PAL_FORMAT_CODE. + +Tue Oct 5 17:47:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Correct lwu opcode value (book had it wrong). + +Thu Sep 30 11:26:18 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * z8k-dis.c (FETCH_DATA): get just the right amount of data. + (unpack_instr): Cope with ARG_IMM4M1 type instructions. + +Wed Sep 29 16:24:49 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k-dis.c (m88kdis): comment change. Remove space after + printing mnemonic. + (printop): handle new arg types DEC and XREG for m88110. + +Tue Sep 28 19:20:16 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Handle 'z' operand + type for absolute branch addresses. Delete special + "ble" and "be" code in 'W' operand code. + +Fri Sep 24 14:08:33 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Set hazard information correctly for branch + likely instructions. + +Fri Sep 17 04:41:17 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use + info->fprintf_func for printing and info->print_address_func for + address output. + +Wed Sep 15 12:12:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Set INSN_TRAP for tXX instructions. + +Thu Sep 9 10:11:27 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): + Corrected second case of "b" for disassembler. + +Tue Sep 7 14:25:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-dis.c, m88k-dis.c: Don't include libbfd.h. Changed calls + to BFD swapping routines to correspond to BFD name changes. + +Thu Sep 2 10:35:25 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Change div machine instruction to be z,s,t rather + than s,t. Change div macro to be d,v,t rather than d,s,t. + Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu, + rem and remu which generates only the corresponding div + instruction. This is for compatibility with the MIPS assembler, + which only generates the simple machine instruction when an + explicit destination of $0 is used. + * mips-dis.c (print_insn_arg): Handle 'z' (always register zero). + +Thu Aug 26 17:41:44 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set + WR_31 hazard for bal, bgezal, bltzal. + +Thu Aug 26 17:20:02 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Use print function + from within the disassemble_info, not fprintf_filtered. + +Wed Aug 25 13:51:40 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Handle '|' like '>'. (From Jeff + Law, law@cs.utah.edu.) + +Mon Aug 23 12:44:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c ("absu"): Removed. + ("dabs"): Added. + +Fri Aug 20 10:52:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Added r6000 and r4000 instructions and macros. + Changed hazard information to distinguish between memory load + delays and coprocessor load delays. + +Wed Aug 18 15:39:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. + +Tue Aug 17 09:44:42 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * configure.in: Don't pass cpu to config.bfd. + +Tue Aug 17 12:23:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k-dis.c (m88kdis): Make class unsigned. + +Thu Aug 12 15:08:18 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha-dis.c (print_insn_alpha): One branch format case was + missing the instruction name. + +Wed Aug 11 19:29:39 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS. + Add the arch-specific auxiliary files. + (OFILES): Remove the arch-specific auxiliary files + and use BFD_MACHINES instead of DIS_LIBS. + * configure.in: Set BFD_MACHINES based on --with-targets option. + +Thu Aug 12 12:04:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly + for swc1. + +Sun Aug 8 15:09:30 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc-opc.c: Change CONST to const to deal with gcc + -Dconst=__const -traditional. + +Fri Aug 6 10:58:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took + coprocessor instructions out of #if 0, and made them use new + argument type "C". + +Thu Aug 5 17:11:06 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc-dis.c: Include ansidecl.h before opcodes/sparc.h. + +Fri Jul 30 18:48:15 1993 John Gilmore (gnu@cygnus.com) + + * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch + instruction, for use by the disassembler. + + * sparc-dis.c (SEX): Add sign extension macro. Replace many + hand-coded sign extensions that depended on 32-bit host ints. + FIXME, we still depend on big-endian host bitfield ordering. + (sparc_print_insn): Set the insn_info_valid field, and the + other fields that describe the instruction being printed. + +Tue Jul 27 17:04:58 1993 Jim Wilson (wilson@sphagnum.cygnus.com) + + * sparc-opc.c (call): Accept all 6 addressing modes valid for + `jmp' instead of just one of them. + +Wed Jul 21 11:43:32 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. + (fput_fp_reg_r): Renamed from fput_reg_r. + (fput_fp_reg): New function. + (print_insn_hppa): Use fput_fp_reg{,_r} where appropriate. + + * hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards. + + * hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD. + +Mon Jul 19 13:52:21 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'. + + * hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n', + don't output a space. + + * hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad. + +Sun Jul 18 16:30:02 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * mips-opc.c: New file, containing opcode table from + ../include/opcode/mips.h. + * Makefile.in: Add it. + +Thu Jul 15 12:37:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k-dis.c: New file, moved in from gdb and changed to use the + new dis-asm.h disassembler interface. + * Makefile.in (DIS_LIBS): Added m88k-dis.o. + (m88k-dis.o): New target. + +Tue Jul 13 10:04:16 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to + argument string const char * to correspond to opcode/mips.h. + +Tue Jul 6 15:18:37 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips-dis.c: Updated to account for name changes in new version + of opcode/mips.h. + * Makefile.in: Added header file dependencies. + +Sat Jul 3 23:47:56 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction. + +Thu Jul 1 12:23:38 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign + extend, rather than shifts. + +Sun Jun 20 20:56:56 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * Makefile.in: Undo 15 June change. + +Fri Jun 18 14:15:15 1993 Per Bothner (bothner@deneb.cygnus.com) + + * m68k-dis.c (print_insn_arg): Change return value to byte count + or error code. + * m68k-dis.c: Re-write to detect invalid operands before + printing anything, so we can handle this the same way we + handle invalid opcodes. + +Thu Jun 17 15:01:36 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * sh-dis.c, sh-opc.h: Understand some more opcodes. + +Wed Jun 16 13:48:05 1993 Ian Lance Taylor (ian@cygnus.com) + + * hppa-dis.c: Include and sysdep.h before other + header files. + +Tue Jun 15 21:45:26 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * sparc-dis.c: Don't declare qsort, since sysdep.h might. + + * configure.in: Do make sysdep.h link. + * Makefile.in: Search ../include. Don't search ../bfd. + +Tue Jun 15 13:36:10 1993 Stu Grossman (grossman@cygnus.com) + + Changes from Jeff Law, law@cs.utah.edu: + * hppa-dis.c: Fix typo. 'a' and 'd' were reversed. + Do not print a space before the completers specified by + 'a' and 'd'. + +Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) + + * mips-dis.c: No longer need to bomb out if HOST_64_BIT is + defined, since gdb has been fixed. + + Changes from Jeff Law, law@cs.utah.edu: + * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, + fput_reg_r, fput_creg, fput_const, and fputs_filtered should + be a *disassemble_info, not a *FILE. + * hppa-dis.c: Support 'd', '!', and 'a'. + * hppa-dis.c: Support 's' to extract a 2 bit space register. + * hppa-dis.c: Delete cases which are no longer needed. + +Fri Jun 11 07:53:48 1993 Jim Kingdon (kingdon@cygnus.com) + + * m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes. + +Tue Jun 8 12:25:01 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with + H8/300-H opcodes. + +Mon Jun 7 12:58:49 1993 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h. + * configure.in: No longer need to configure to get sysdep.h. + +Thu Jun 3 15:56:49 1993 Stu Grossman (grossman@cygnus.com) + + * Patches from Jeffrey Law . + * hppa-dis.c: Support 'I', 'J', and 'K' in output + templates for 1.1 FP computational instructions. + +Tue May 25 13:05:48 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * h8500-dis.c (print_insn_h8500): Address argument is type + bfd_vma. + * z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002): + Ditto. + + * h8500-opc.h (addr_class_type): No comma at end of enumerator. + * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto. + + * sparc-dis.c (compare_opcodes): Move static declaration to + top-level. + +Fri May 21 14:17:37 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp + instruction, remove unimp hack from 'l' argument. + +Wed May 19 15:35:54 1993 Stu Grossman (grossman@cygnus.com) + + * z8k-dis.c (fetch_data): Use unsigned char to make ancient gcc's + happy. + +Fri May 14 15:22:46 1993 Ian Lance Taylor (ian@cygnus.com) + + * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): + * mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor + instructions. + +Fri May 14 00:09:14 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c: Include dis-asm.h before sysdep.h. Changed some + arrays of string pointers to 2-d arrays of chars, to save + space. + +Thu May 6 20:51:17 1993 Fred Fish (fnf@cygnus.com) + + * a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c: + Cast second arg to read_memory_func to "bfd_byte *", as necessary. + +Tue May 4 20:31:10 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c: New file from Utah, adapted to new disassembler + calling interface. + * Makefile.in: Include it. + +Mon Apr 26 18:17:42 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * sh-dis.c, sh-opc.h: New files. + +Fri Apr 23 18:51:22 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * alpha-dis.c, alpha-opc.h: New files. + +Tue Apr 6 12:54:08 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed + value. + +Mon Apr 5 17:37:37 1993 John Gilmore (gnu@cygnus.com) + + * sparc-dis.c: Make "ta" the default trap instruction, "t" the alias. + +Fri Apr 2 07:24:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than + const. + +Thu Apr 1 11:20:43 1993 Jim Kingdon (kingdon@cygnus.com) + + * sparc-dis.c: Use fprintf_func a few places where I forgot, + and double percent signs a few places. + + * a29k-dis.c, i960-dis.c: New, merged from gdb and binutils. + + * i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c: + Use info->print_address_func not print_address. + + * dis-buf.c (generic_print_address): New function. + +Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Add sparc-dis.c. + sparc-dis.c: New file, merges binutils and gdb versions as follows: + From GDB: + Add `add' instruction to the set that get checked + for a preceding `sethi' in order to print an absolute address. + * (print_insn): Disassembly prefers real instructions. + (is_delayed_branch): Speed up. + * sparc-opc.c: Add ALIAS bit to aliases. Fix up opcode tables. + Still missing some float ops, and needs testing. + * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by + F_ALIAS. Use printf, not fprintf, when not passing a file + pointer... + (compare_opcodes): Check that identical instructions have + identical opcodes, complain otherwise. + From binutils: + * New 'm' arg. + * Include reg_names. + From neither: + Use dis-asm.h/read_memory_func interface. + +Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com) + + * h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data): + deliberately return non-zero to setjmp from longjmp. Otherwise + this code fails to compile. + +Wed Mar 31 17:04:31 1993 Stu Grossman (grossman@cygnus.com) + + * m68k-dis.c: Fix prototype for fetch_arg(). + +Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-buf.c: New file, for new read_memory_func interface. + Makefile.in (OFILES): Include it. + m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c: + Use new read_memory_func interface. + +Mon Mar 29 14:02:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8500-dis.c (print_insn_h8500): Get sign of fp offsets right. + * h8500-opc.h: Fix couple of opcodes. + +Wed Mar 24 02:03:36 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) + + * Makefile.in: add dvi & installcheck targets + +Mon Mar 22 18:55:04 1993 John Gilmore (gnu@cygnus.com) + + * Makefile.in: Update for h8500-dis.c. + +Fri Mar 19 14:27:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8500-dis.c, h8500-opc.h: New files + +Thu Mar 18 14:12:37 1993 Per Bothner (bothner@rtl.cygnus.com) + + * mips-dis.c, z8k-dis.c: Converted to use interface defined in + ../include/dis-asm.h. + * m68k-dis.c: New file (merge of ../binutils/m68k-pinsn.c + and ../gdb/m68k-pinsn.c). + * i386-dis.c: New file (merge of ../binutils/i386-pinsn.c + and ../gdb/i386-pinsn.c). + * m68881-ext.c: New file. Moved definition of + ext_format ext_format_68881 from ../gdb/m68k-tdep.c. + * Makefile.in: Adjust for new files. + * i386-dis.c: Patches from John Hassey (hassey@dg-rtp.dg.com). + * m68k-dis.c: Recognize '9' placement code, so (say) pflush + can be dis-assembled. + +Wed Feb 17 09:19:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * mips-dis.c (print_insn_arg): Now returns void. + +Mon Jan 11 16:09:16 1993 Fred Fish (fnf@cygnus.com) + + * mips-dis.c (ansidecl.h): Include for benefit of sysdep.h + files that use the macros. + +Thu Jan 7 13:15:17 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-dis.c: New file, from gdb/mips-pinsn.c. + * Makefile.in (DIS_LIBS): Added mips-dis.o. + (CFILES): Added mips-dis.c. + +Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines + * z8kgen.c, z8k-opc.h: fix sizes of some shifts. + +Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in: Improve *clean rules. + * configure.in: Allow a default host. + +Tue Nov 17 19:53:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep + files include other sysdep files + +Thu Nov 12 16:10:37 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint + +Fri Oct 9 04:56:05 1992 John Gilmore (gnu@cygnus.com) + + * configure.in: For host support, use ../bfd/configure.host + so it stays in sync with the ../bfd/hosts database. + +Thu Oct 1 23:38:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: use cpu-vendor-os triple instead of nested cases + +Wed Sep 30 16:09:20 1992 Michael Werner (mtw@cygnus.com) + + * z8k-dis.c (unparse_instr): fix bug where opcode returned was + *always* the wrong one. + +Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8kgen.c: added copyright info + +Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c (unparse_instr): prettier tabs + * z8kgen.c z8k-opc.h: bug fixes in tables + +Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) + + * configure.in: Add ncr* configuration. + * z8k-dis.c (struct instr_data_s): Make instr_asmsrc char to make + picayune ANSI compilers happy. + +Sep 20 08:50:55 1992 Fred Fish (fnf@cygnus.com) + + * configure.in (i386): Make i386 and i486 synonymous for now. + * configure.in (i[34]86-*-sysv4): Add my_host definition. + +Fri Sep 18 17:01:23 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * Makefile.in (install): Fix typo. + +Fri Sep 18 02:04:24 1992 John Gilmore (gnu@cygnus.com) + + * Makefile.in (make): Remove obsolete crud. + (sparc-opc.o): Avoid Sun Make VPATH bug. + +Tue Sep 8 17:29:27 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * Makefile.in: since there are no SUBDIRS, remove rule and + references of subdir_do. + +Tue Sep 8 17:02:58 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * Makefile.in (install): Get the library name right here too. + Don't install bfd.h, since it's unrelated to this library. No + subdirs to recurse into, either. + (CFILES): The source file has a .c suffix, not .o. + + * sparc-opc.c: New file, moved from BFD. + * Makefile.in (OFILES): Build it. + +Thu Sep 3 16:59:20 1992 Michael Werner (mtw@cygnus.com) + + * z8k-dis.c: fixed forward refferences of some declarations. + +Mon Aug 31 16:09:45 1992 Michael Werner (mtw@cygnus.com) + + * Makefile.in: get the name of the library right + +Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c: knows how to disassemble z8k stuff + * z8k-opc.h: new file full of z8000 opcodes + +Fri Aug 28 15:38:03 1992 Ken Raeburn (raeburn@cygnus.com) + + * Renamed opc-sparc.c to sparc-opc.c for systems with short + filename constraints. + * Makefile.in: Updated to reflect change. + + +Local Variables: +version-control: never +End: diff --git a/opcodes/ChangeLog-9899 b/opcodes/ChangeLog-9899 new file mode 100644 index 0000000..3f8bf77 --- /dev/null +++ b/opcodes/ChangeLog-9899 @@ -0,0 +1,1669 @@ +1999-12-27 Alan Modra + + * i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall". + +Wed Dec 1 03:34:53 1999 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c, m10300-dis.c: Add am33 support. + +Wed Nov 24 20:29:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names. + (print_insn_hppa): Handle 'B' operand. + +1999-11-22 Nick Clifton + + * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction. + +1999-11-18 Gavin Romig-Koch + + * mips-opc.c (I5): New. + (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s + madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, + pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New. + +Mon Nov 15 19:34:58 1999 Donald Lindsay + + * arm-dis.c (print_insn_arm): Added general purpose 'X' format. + * arm-opc.h (print_insn_arm): Added comment documenting + the 'X' format just added to arm-dis.c. + +1999-11-15 Gavin Romig-Koch + + * mips-opc.c (la): Create a version that just uses addiu directly. + (dla): Expand to daddiu if possible. + +1999-11-11 Nick Clifton + + * mips-opc.c: Add ssnop pattern. + +1999-11-01 Gavin Romig-Koch + + * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER. + +1999-10-29 Nick Clifton + + * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA + (d30v_format_tab): Define the SHORT_AR format. + +1999-10-28 Nick Clifton + + * mcore-dis.c: Remove spurious code introduced in previous delta. + +1999-10-27 Scott Bambrough + + * arm-dis.c: Include sysdep.h to prevent compile time warnings. + +1999-10-18 Michael Meissner + + * alpha-opc.c (alpha_operands): Fill in missing initializer. + (alpha_num_operands): Convert to unsigned. + (alpha_num_opcodes): Ditto. + (insert_rba): Declare unused arguments ATTRIBUTE_UNUSED. + (insert_rca): Ditto. + (insert_za): Ditto. + (insert_zb): Ditto. + (insert_zc): Ditto. + (extract_bdisp): Ditto. + (extract_jhint): Ditto. + (extract_ev6hwjhint): Ditto. + +Sun Oct 10 01:48:01 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Add new codes 'cc', 'cd', 'cC', + 'co', '@'. + + * hppa-dis.c (print_insn_hppa): Removed unused args. Fix '?W'. + + * hppa-dis.c (print_insn_hppa): Implement codes "?N", "?Q". + +Thu Oct 7 00:12:43 MDT 1999 Diego Novillo + + * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for + rac/rachi instructions. + (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi, + slae, st and st2w. + +1999-10-04 Doug Evans + + * fr30-asm.c, fr30-desc.h: Rebuild. + * m32r-asm.c, m32r-desc.c, m32r-desc.h: Rebuild. Add m32rx support. + * m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c: Ditto. + +1999-09-29 Nick Clifton + + * sh-opc.h: Fix bit patterns for several load and store + instructions. + +Thu Sep 23 08:27:20 1999 Jerry Quinn + + * configure.in (Canonicalization of target names): Remove adding + ${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14 + generates $ac_config_sub with a ${CONFIG_SHELL} already. + * configure: Regenerate. + +Tue Sep 7 13:50:32 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa): Escape '%' in output strings. + + * hppa-dis.c (print_insn_hppa): Handle 'Z' argument. + +1999-09-07 Nick Clifton + + * sh-opc.h: Add mulu.w and muls.w patterns. These are the correct + names for the mulu and muls patterns. + +1999-09-04 Steve Chamberlain + + * pj-opc.c: New file. + * pj-dis.c: New file. + * disassemble.c (disassembler): Handle bfd_arch_pj. + * configure.in: Handle bfd_pj_arch. + * Makefile.am: Rebuild dependencies. + (CFILES): Add pj-dis.c and pj-opc.c. + (ALL_MACHINES): Add pj-dis.lo and pj-opc.lo. + * configure, Makefile.in: Rebuild. + +1999-09-04 H.J. Lu + + * i386-dis.c (print_insn_i386): Set bytes_per_line to 7. + +Mon Aug 30 18:56:14 1999 Richard Henderson + + * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31. + +1999-08-04 Doug Evans + + * fr30-asm.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-asm.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + +Sat Aug 28 00:27:24 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float + register args by 'f'. + + * hppa-dis.c (print_insn_hppa): Add args q, %, !, and |. + + * hppa-dis.c (MASK_10, read_write_names, add_compl_names, + extract_10U_store): New. + (print_insn_hppa): Add new completers. + + * hppa-dis.c (signed_unsigned_names,mix_half_names, + saturation_names): New. + (print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'. + + * hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. + + * hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!' + + * hppa-dis.c (print_insn_hppa): Look at next arg instead of bits + to decide to print a space. + +1999-08-21 Alan Modra + + * i386-dis.c: Add AMD athlon instruction support. + +1999-08-10 Ian Lance Taylor + + From Wally Iimura : + * dis-buf.c (buffer_read_memory): Rewrite expression to avoid + overflow at end of address space. + (generic_print_address): Use sprintf_vma. + +1999-08-08 Ian Lance Taylor + + * Makefile.am: Rename .dep* files to DEP*. Change DEP variable to + MKDEP. Rebuild dependencies. + * Makefile.in: Rebuild. + +Fri Aug 6 09:46:35 1999 Jerry Quinn + + * hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names, + add_cond_64_names, wide_add_cond_names, logical_cond_64_names, + unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New. + (print_insn_hppa): Add 64 bit condition completers. + +Thu Aug 5 16:59:58 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Change condition args to use + '?' prefix. + +Wed Jul 28 04:33:58 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E' + code. + +1999-07-21 Ian Lance Taylor + + From Mark Elbrecht: + * configure.bat: Remove; obsolete. + +1999-07-11 Ian Lance Taylor + + * dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate. + (generic_strcat_address): Add cast to avoid warning. + * i386-dis.c: Initialize all structure fields to avoid warnings. + Add ATTRIBUTE_UNUSED as appropriate. + +1999-07-08 Jakub Jelinek + + * sparc-dis.c (print_insn_sparc): Differentiate between + addition and oring when guessing symbol for comment. + +1999-07-05 Nick Clifton + + * arm-dis.c (print_insn_arm): Display hex equivalent of rotated + constant. + +1999-06-23 Alan Modra + + * i386-dis.c: Mention intel mode specials in macro char comment. + +1999-06-21 Ian Lance Taylor + + * alpha-dis.c: Don't include . + * arm-dis.c: Include "sysdep.h". + * tic30-dis.c: Don't include or . Include + "sysdep.h". + * Makefile.am: Rebuild dependencies. + * Makefile.in: Rebuild. + +1999-06-16 Nick Clifton + + * arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange + SWIs. + +1999-06-14 Nick Clifton & Drew Mosley + + * arm-dis.c (arm_regnames): Turn into a pointer to a register + name set. + (arm_regnames_standard): New variable: Array of ARM register + names according to ARM instruction set nomenclature. + (arm_regnames_apcs): New variable: Array of ARM register names + according to ARM Procedure Call Standard. + (arm_regnames_raw): New variable: Array of ARM register names + using just 'r' and the register number. + (arm_toggle_regnames): New function: Toggle the chosen register set + naming scheme. + (parse_disassembler_options): New function: Parse any target + disassembler command line options. + (print_insn_big_arm): Call parse_disassembler_options if any + are defined. + (print_insn_little_arm): Call parse_disassembler_options if any + are defined. + +1999-06-13 Ian Lance Taylor + + * i386-dis.c (FWAIT_OPCODE): Define. + (used_prefixes): New static variable. + (fetch_data): Don't print an error message if we have already + fetched some bytes successfully. + (ckprefix): Clear used_prefixes. Use FWAIT_OPCODE, not 0x9b. + (prefix_name): New static function. + (print_insn_i386): If setjmp fails, indicating a data error, but + we have managed to fetch some bytes, print the first one as a + prefix or a .byte pseudo-op. If fwait is followed by a non + floating point instruction, print the first prefix. Set + used_prefixes when prefixes are used. If any prefixes were not + used after disassembling the instruction, print the first prefix + instead of printing the instruction. + (putop): Set used_prefixes when prefixes are used. + (append_seg, OP_E, OP_G, OP_REG, OP_I, OP_sI, OP_J): Likewise. + (OP_DIR, OP_SIMD_Suffix): Likewise. + +1999-06-07 Jakub Jelinek + + * sparc-opc.c: Fix up set, setsw, setuw operand kinds. + Support signx %reg, clruw %reg. + +1999-06-07 Jakub Jelinek + + * sparc-opc.c: Add aliases Solaris as supports. + +Mon Jun 7 12:04:52 1999 Andreas Schwab + + * Makefile.am (CFILES): Add arc-{dis,opc}.c and v850-{dis,opc}.c. + * Makefile.in: Regenerated. + +1999-06-03 Philip Blundell + + * arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR + when target is PC-relative. + +1999-05-28 Linus Nordberg + + * m68k-opc.c: Rename MACL/MSACL to MAC/MSAC. Add MACM/MSACM. Add + MOVE MACSR,CCR. + + * m68k-dis.c (fetch_arg): Add places `n', `o'. + + * m68k-opc.c: Add MSAC, MACL, MOVE to/from ACC, MACSR, MASK. + Add mcf5206e to appropriate instructions. + Add alias for MAC, MSAC. + + * m68k-dis.c (print_insn_arg): Add formats `E', `G', `H' and place + `N'. + + * m68k-opc.c (m68k_opcodes): Add divsw, divsl, divuw, divul, macl, + macw, remsl, remul for mcf5307. Change mcf5200 --> mcf. + + * m68k-dis.c: Add format `u' and places `h', `m', `M'. + +1999-05-18 Alan Modra + + * i386-dis.c (Ed): Define. + (dis386_twobyte_att, dis386_twobyte_intel): Use Ed for movd. + (Rw): Remove. + (OP_rm): Rename to OP_Rd. + (ONE): Remove. + (OP_ONE): Remove. + (putop): Add const to template and p. + (print_insn_x86): Delete. + (print_insn_i386): Merge old function print_insn_x86. Add const + to dp. + (struct dis386): Add const to name. + (dis386_att, dis386_intel): Add const. + (dis386_twobyte_att, dis386_twobyte_intel): Add const. + (names32, names16, names8, names_seg, index16): Add const. + (grps, prefix_user_table, float_reg): Add const. + (float_mem_att, float_mem_intel): Add const. + (oappend): Add const to s. + (OP_REG): Add const to s. + (ptr_reg): Add const to s. + (dofloat): Add const to dp. + (OP_C): Don't skip modrm, it's now done in OP_Rd. + (OP_D): Ditto. + (OP_T): Ditto. + (OP_Rd): Check for valid mod. Call Op_E to print. + (OP_E): Handle d_mode arg. Check for bad sfence,lea,lds etc. + (OP_MS): Check for valid mod. Call Op_EM to print. + (OP_3DNowSuffix): Set obufp and use oappend rather than + strcat. Call BadOp() for errors. + (OP_SIMD_Suffix): Likewise. + (BadOp): New function. + +1999-05-12 Alan Modra + + * i386-dis.c (dis386_intel): Remove macro chars, except for + jEcxz. Change cWtR and cRtd to cW and cR. + (dis386_twobyte_intel): Remove macro chars here too. + (putop): Handle R and W macros for intel mode. + + * i386-dis.c (SIMD_Fixup): New function. + (dis386_twobyte_att): Use it on movlps and movhps, and change + Ev to EX on these insns. Change movmskps Ev, XM to Gv, EX. + (dis386_twobyte_intel): Same here. + + * i386-dis.c (Av): Remove. + (Ap): remove lptr. + (lptr): Remove. + (OPSIMD): Define. + (OP_SIMD_Suffix): New function. + (OP_DIR): Remove dead code. + (eAX_reg..eDI_reg): Renumber. + (onebyte_has_modrm): Table numbering comments. + (INTERNAL_DISASSEMBLER_ERROR): Move to before print_insn_x86. + (print_insn_x86): Move all prefix oappends to after uses_f3_prefix + checks. Print error on invalid dp->bytemode2. Remove simd_cmp, + and handle SIMD cmp insns in OP_SIMD_Suffix. + (info->bytes_per_line): Bump from 5 to 6. + (OP_None): Remove. + (OP_E): Use INTERNAL_DISASSEMBLER_ERROR. Handle sfence. + (OP_3DNowSuffix): Ensure mnemonic index unsigned. + + PIII SIMD support from Doug Ledford + * i386-dis.c (XM, EX, None): Define. + (OP_XMM, OP_EX, OP_None): New functions. + (USE_GROUPS, USE_PREFIX_USER_TABLE): Define. + (GRP14): Rename to GRPAMD. + (GRP*): Add USE_GROUPS flag. + (PREGRP*): Define. + (dis386_twobyte_att, dis386_twobyte_intel): Add SIMD insns. + (twobyte_has_modrm): Add SIMD entries. + (twobyte_uses_f3_prefix, simd_cmp_op, prefix_user_table): New. + (grps): Add SIMD insns. + (print_insn_x86): New vars uses_f3_prefix and simd_cmp. Don't + oappend repz if uses_f3_prefix. Add code to handle new groups for + SIMD insns. + + From Maciej W. Rozycki + * i386-dis.c (dis386_att, dis386_intel): Change 0xE8 call insn + operand from Av to Jv. + +1999-05-07 Nick Clifton + + * mcore-dis.c (print_insn_mcore): Use .short to display + unidentified instructions, not .word. + +1999-04-26 Tom Tromey + + * aclocal.m4, configure: Updated for new version of libtool. + +1999-04-14 Doug Evans + + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. + +Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa, case '3'): New case for PA2.0 + instructions. + +1999-04-10 Doug Evans + + * fr30-desc.c, fr30-desc.h, fr30-ibld.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-opinst.c: Rebuild. + +1999-04-06 Ian Lance Taylor + + * opintl.h (LC_MESSAGES): Never define. + +1999-04-04 Ian Lance Taylor + + * i386-dis.c (intel_syntax, open_char, close_char): Make static. + (separator_char, scale_char): Likewise. + (print_insn_x86): Likewise. + (print_insn_i386): Likewise. Add declaration. + +1999-03-26 Doug Evans + + * fr30-dis.c: Rebuild. + * m32r-dis.c: Rebuild. + +1999-03-23 Ian Lance Taylor + + * m68k-opc.c: Change compare instructions to use "@s" rather than + ";s" when used with an immediate operand. + +1999-03-22 Doug Evans + + * cgen-opc.c (cgen_set_cpu): Delete. + (cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c, + fr30-opc.h: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c, + m32r-opc.h: Rebuild. + * po/opcodes.pot: Rebuild. + +1999-03-16 Martin Hunt + + * d30v-opc.c (mvtsys): Remove FLAG_LKR. + +1999-03-11 Doug Evans + + * cgen-opc.c (cgen_set_cpu): New arg `isa'. All callers updated. + (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns. + (cgen_get_insn_operands): Rewrite test for hardcoded/operand index. + * fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c: Rebuild. + * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c: Rebuild. + * m32r-opinst.c: Rebuild. + +1999-02-25 Doug Evans + + * cgen-opc.c (cgen_hw_lookup_by_name): Rewrite. + (cgen_hw_lookup_by_num): Rewrite. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + +Sat Feb 13 14:06:19 1999 Richard Henderson + + * alpha-opc.c: Add sqrt+flags patterns. Add EV6 PALcode insns. + (insert_jhint): Fix insertion mask. + * alpha-dis.c (print_insn_alpha): Disassemble EV6 PALcode insns. + +1999-02-10 Doug Evans + + * Makefile.in: Rebuild. + +1999-02-09 Doug Evans + + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: Delete. + * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. + * Makefile.am: Remove references to them. + (HFILES): Add fr30-desc.h, m32r-desc.h. + (CFILES): Add fr30-desc.c, fr30-ibld.c, m32r-desc.c, m32r-ibld.c, + m32r-opinst.c. + (ALL_MACHINES): Update. + * configure.in: Redo handling of cgen_files. + (bfd_i960_arch): Delete i960c-*.lo files. + * configure: Regenerate. + * cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (hash_insn_array): Rewrite. + * cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (hash_insn_array): Rewrite. + * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (cgen_lookup_insn,cgen_get_insn_operands): Define here. + (cgen_lookup_get_insn_operands): Ditto. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. + * po/POTFILES.in: Rebuild. + * po/opcodes.pot: Rebuild. + +Fri Feb 5 00:04:24 1999 Ian Lance Taylor + + * Makefile.am: Rebuild dependencies. + (HFILES): Add fr30-opc.h. + (CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c. + * Makefile.in: Rebuild. + + * configure.in: Change AC_PREREQ to 2.13. Remove AM_CYGWIN32. + Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to + AC_PROG_INSTALL. + * acconfig.h: Remove. + * configure: Rebuild with current autoconf/automake. + * aclocal.m4: Likewise. + * config.in: Likewise. + * Makefile.in: Likewise. + +Thu Feb 4 13:48:52 1999 Ian Lance Taylor + + * m68k-opc.c: Correct move (not movew) to status word on 5200. + +Mon Feb 1 20:54:36 1999 Catherine Moore + + * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax. + * i386-dis.c (x_mode): Define. + (dis386): Remove. + (dis386_att): New. + (dis386_intel): New. + (dis386_twobyte): Remove. + (dis386_twobyte_att): New. + (dis386_twobyte_intel): New. + (print_insn_x86): Use new arrays. + (float_mem): Remove. + (float_mem_intel): New. + (float_mem_att): New. + (dofloat): Use new float_mem arrays. + (print_insn_i386_att): New. + (print_insn_i386_intel): New. + (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax. + (putop): Handle intel syntax. + (OP_indirE): Handle intel syntax. + (OP_E): Handle intel syntax. + (OP_I): Handle intel syntax. + (OP_sI): Handle intel syntax. + (OP_OFF): Handle intel syntax. + +1999-01-27 Doug Evans + + * fr30-opc.h, fr30-opc.c: Rebuild. + * i960c-opc.h, i960c-opc.c: Rebuild. + * m32r-opc.c: Rebuild. + +Tue Jan 19 18:01:54 1999 David Taylor + + * hppa-dis.c: revert HP merge changes until HP gives us + an updated file. + +1999-01-19 Nick Clifton + + * arm-dis.c (print_insn_arm): Display ARM syntax for PC relative + offsets as well as symbloic address. + +Tue Jan 19 10:51:01 1999 David Taylor + + * hppa-dis.c: fix comments and some indentation. + +1999-01-12 Doug Evans + + * fr30-opc.c, i960c-opc.c: Regenerate. + +1999-01-11 Doug Evans + + * fr30-opc.c: Regenerate. + +1999-01-06 Doug Evans + + * m32r-dis.c: Regenerate. + +1999-01-05 Doug Evans + + * fr30-asm.c, fr30-dis.c, fr30-opc.h, fr30-opc.c: Regenerate. + * i960c-asm.c, i960c-dis.c, i960c-opc.h, i960c-opc.c: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. + +1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) + + * configure.in: Require autoconf 2.12.1 or higher. + +1998-12-30 Gavin Romig-Koch + + * mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH. + +Wed Dec 16 16:17:49 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + +1998-12-16 Gavin Romig-Koch + + * mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111. + +1998-12-15 Dave Brolley + + * fr30-opc.c, fr30-opc.h: Regenerated. + +1998-12-14 Dave Brolley + + * fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 10 18:39:46 1998 Dave Brolley + + * fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 10 12:49:24 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Tue Dec 8 13:56:18 1998 David Taylor + + * dis-buf.c (generic_strcat_address): reformat to GNU coding + conventions. change sprintf call to an sprintf_vma call. + +Tue Dec 8 13:12:44 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Tue Dec 8 10:50:46 1998 David Taylor + + The following changes were made by + Elena Zannoni , + David Taylor , and + Edith Epstein as part of a project to + merge in changes by HP; HP did not create ChangeLog entries. + + * dis-buf.c (generic_strcat_address): new function. + + * hppa-dis.c: Changes to improve hppa disassembly. + Changed formatting in : reg_names, fp_reg_names,control_reg, + New variables : sign_extension_names, deposit_names, conversion_names + float_test_names, compare_cond_names_double, add_cond_names_double, + logical_cond_names_double, unit_cond_names_double, + branch_push_pop_names, saturation_names, shift_names, mix_names, + New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG + Move some definitions to libhppa.h: GET_FIELD, GET_BIT + (fput_const): renamed as fput_hex_const + (print_insn_hppa): + - use the macros fputs_filtered and + fput_decimal_const whenever possible; calls to sign_extend require + 2 params -- add a missing second param of 0. + - Some new code ifdefed for LOCAL_ONLY, all related to figuring out + architecture version number of current machine. HP folks are + trying to handle situation where the target program was compiled + for PA 1.x (32-bit), but is running on a PA 2.0 machine and + visa versa. + - added new cases : 'g', 'B', 'm' + - added cases specifically for PA 2.0 + - changed the following cases : '"', 'n', 'N', 'p', 'Z', + - calls to fput_const become calls to fput_hex_const + +1998-12-07 James E Wilson + + * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. + (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. + (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. + * Makefile.in: Rebuilt. + * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, + i960-dis.c to ta. + * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. + +Mon Dec 7 14:33:44 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Sun Dec 6 14:06:48 1998 Ian Lance Taylor + + * mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2. + + * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions. + From Saitoh Masanobu . + +Fri Dec 4 17:45:51 1998 Doug Evans + + * fr30-opc.c: Regenerate. + +Fri Dec 4 17:08:08 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 3 14:26:20 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 3 00:09:17 1998 Doug Evans + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. + +1998-11-30 Doug Evans + + * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> + CGEN_INSN_BASE_VALUE. + * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. + * fr30-opc.c, fr30-opc.h, fr30-asm.c, fr30-dis.c: Regenerate. + +Thu Nov 26 11:26:32 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c: Regenerated. + +Tue Nov 24 11:20:54 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c: Regenerated. + +Mon Nov 23 18:28:48 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +1998-11-20 Doug Evans + + * fr30-opc.c: Regenerated. + +Thu Nov 19 16:02:46 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Thu Nov 19 07:54:15 1998 Doug Evans + + * mips-opc.c (sync.p,sync.l): Swap insn values. + +1998-11-19 Doug Evans + + * fr30-opc.c: Regenerate. + +Wed Nov 18 21:36:37 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + +1998-11-18 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c: Rebuild. + * fr30-asm.c, fr30-dis.c, fr30-opc.c: Rebuild. + +Wed Nov 18 11:30:04 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + +Mon Nov 16 19:21:48 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Thu Nov 12 19:24:18 1998 Dave Brolley + + * po/opcodes.pot: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Tue Nov 10 15:26:27 1998 Nick Clifton + + * disassemble.c (disassembler): Add support for FR30 target. + +Tue Nov 10 11:00:04 1998 Doug Evans + + * m32r-dis.c, m32r-opc.c, m32r-opc.h: Rebuild. + * fr30-dis.c, fr30-opc.c, fr30-opc.h: Rebuild. + +Mon Nov 9 18:22:55 1998 Dave Brolley + + * po/opcodes.pot: Regenerate. + * po/POTFILES.in: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + +Fri Nov 6 17:21:38 1998 Doug Evans + + * m32r-asm.c: Regenerate. + +Wed Nov 4 18:46:47 1998 Dave Brolley + + * configure.in: Added case for bfd_fr30_arch. + * Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c. + (ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo. + (CLEANFILES): Added stamp-fr30. + (FR30_DEPS): Added. + * fr30-asm.c: New file. + * fr30-dis.c: New file. + * fr30-opc.c: New file. + * fr30-opc.h: New file. + * po/POTFILES.in: Regenerated + * po/opcodes.pot: Regenerated + +Mon Nov 2 15:05:33 1998 Geoffrey Noer + + * configure.in: detect cygwin* instead of cygwin32* + * configure: regenerate + +Tue Oct 27 08:58:37 1998 Gavin Romig-Koch + + * mips-opc.c (IS_M): Added. + +Mon Oct 19 13:03:19 1998 Doug Evans + + * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. + +Fri Oct 9 14:01:56 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c: Regenerate. + +Sun Oct 4 21:01:44 1998 Alan Modra + + * i386-dis.c (OP_3DNowSuffix): New static function. + (OPSUF): Define. + (GRP14): Define. + (dis386_twobyte): Add GRP14, femms, and 3DNow entries. + (twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow. + (insn_codep): New static variable. + (print_insn_x86): Init insn_codep after prefixes. + (grps): Add GRP14 entries for prefetch, prefetchw. + (OP_REG): Reformat. + + From Jeff B Epler + * i386-dis.c (Suffix3DNow): New table. + +Wed Sep 30 10:17:50 1998 Nick Clifton + + * d10v-opc.c: Treat TRAP as if it were a branch type instruction. + +Mon Sep 28 14:35:43 1998 Martin M. Hunt + + * d10v-dis.c (print_operand): If num is nonzero, then + add OPERAND_ACC1, not OPERAND_ACC0. + +Thu Sep 24 09:20:03 1998 Nick Clifton + + * d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP + insns. + +Tue Sep 22 17:55:14 1998 Nick Clifton + + * d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit + class. + +Tue Sep 15 15:14:45 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c: Add bbpc,bbpsw support. + +1998-09-09 Michael Meissner + + * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move + to/from SPRs. + +Fri Sep 4 19:42:59 1998 Nick Clifton + + * arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf + object files. + (print_insn_little_arm): Detect Thumb symbols in elf object + files. + +Sat Aug 29 22:24:09 1998 Richard Henderson + + * alpha-dis.c (print_insn_alpha): Use the machine type to + decide which PALcode set to include. + +Sun Aug 23 02:16:18 1998 Richard Henderson + + * sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case. + +Fri Aug 21 16:07:52 1998 Nick Clifton + + * d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS, + MSUB and MSUBS instructions. + +Thu Aug 13 16:23:04 1998 Ian Lance Taylor + + * ppc-opc.c (powerpc_operands): Omit parens around additions in + operand name macros. + +Wed Aug 12 14:00:38 1998 Ian Lance Taylor + + From Peter Jeremy : + * m68k-opc.c: Correct mulsl and mulul to use q rather than D, a, + +, -, and d for ColdFire. + + From Peter Thiemann : + * ppc-opc.c (insert_mbe): Handle wrapping bitmasks. + (extract_mbe): Likewise. + +Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. + + * m10300-opc.c: First cut at UDF instructions. + +Mon Aug 10 14:08:22 1998 Doug Evans + + * m32r-opc.c: Regenerate (remove semantic descriptions). + +Mon Aug 10 12:51:12 1998 Catherine Moore + + * arm-dis.c (print_insn_big_arm): Fix indentation. + (print_insn_little_arm): Likewise. + +Sun Aug 9 20:17:28 1998 Catherine Moore + + * arm-dis.c (print_insn_big_arm): Check for thumb symbol + attributes. + (print_insn_little_arm): Likewise. + +Mon Aug 3 12:43:16 1998 Doug Evans + + Move all global state data into opcode table struct, and treat + opcode table as something that is "opened/closed". + * cgen-asm.c (all fns): New first arg of opcode table descriptor. + (cgen_asm_init): Delete. + (cgen_set_parse_operand_fn): New function. + * cgen-dis.c (all fns): New first arg of opcode table descriptor. + (cgen_dis_init): Delete. + * cgen-opc.c (all fns): New first arg of opcode table descriptor. + (cgen_current_{opcode_table_mach,endian}): Delete. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. + +Thu Jul 30 21:41:10 1998 Frank Ch. Eigler + + * d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some + instructions. + +Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Add entries for "no_match_operands" field in + the opcode table. + +Fri Jul 24 11:41:37 1998 Doug Evans + + * m32r-asm.c, m32r-opc.c: Regenerate (-Wall cleanups). + +Tue Jul 21 13:41:07 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Mon Jul 13 14:53:59 1998 Alan Modra + + * i386-dis.c (ckprefix): Handle fwait specially only when it isn't + the first prefix. + (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather + than `fnstsw %eax'. + (OP_J): Remove unnecessary subtraction when 16-bit displacement + will be masked later. + +Thu Jul 2 17:11:27 1998 Doug Evans + + * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. + +Wed Jul 1 16:11:16 1998 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. + +Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-dis.c: Only recognize instructions from the currently + selected machine. + * m10300-opc.c: Add field indicating the particular variant of + the mn10300 each instruction is available on. + +Fri Jun 26 12:04:21 1998 Ian Lance Taylor + + * configure.in: For bfd_vax_arch, build vax-dis.lo. + * Makefile.am: Rebuild dependencies. + (CFILES): Add vax-dis.c. + (ALL_MACHINES): Add vax-dis.lo. + * aclocal.m4: Rebuild with current libtool. + * configure, Makefile.in: Rebuild. + +Fri Jun 26 12:03:20 1998 Klaus Kaempf + + * vax-dis.c: New file, from work by Pauline Middelink + . + * disassemble.c (ARCH_vax): Define if ARCH_all. + (disassembler): Add case for ARCH_vax. + * makefile.vms: Support compilation on vms/vax. + +Tue Jun 23 19:42:18 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities + related to sign extension and the size of ints. + +Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Support one operand "asr", "lsr" and "asl" + instructions. Support (sp) addressing mode by expanding it into + (0,sp). + +Sat Jun 20 14:46:20 1998 Frank Ch. Eigler + + * mips-dis.c (_print_insn_mips): Fix argument interchange typo. + +Fri Jun 19 09:16:42 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. + +1998-06-18 Ulrich Drepper + + * i386-dis.c: Add support for fxsave, fxrstor, sysenter and + sysexit. + +Thu Jun 18 10:22:24 1998 John Metzler + + * mips-dis.c (print_insn_little_mips): Previously, instruction + printing references the symbol table to determine whether the + instruction resides in a block regular instructions or mips16 + instructions. However, when the disassembler gets used in other + environments where the symbol table is not present, we no longer + rely in the symbol table, rather, use the low bit of the + instructions address to guess. There should be no change for usage + of the disassembler in host based programs, gdb, objdump. + (print_insn_big_mips): ditto. + (print_insn_mips): ditto + +Wed Jun 17 21:19:01 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. + +Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". + +Tue Jun 16 13:10:51 1998 Alan Modra + + * i386-dis.c (index16): Add '%' to register names. Use ',' + instead of '+'. + +Sat Jun 13 11:33:55 1998 Alan Modra + + * i386-dis.c: Don't print opcode suffix when we can figure out the + size (and gas can!) by register operands, or from the default + size. + (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' + macro to 'E'. + (dis386, dis386_twobyte, grps): Use new suffix macros. + (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be + consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse + order of cmps operands to agree with Intel docs. Correct operand + of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to + agree with Intel docs. + (print_insn_x86): Print orphan fwait before other prefixes. + Return correct byte count for orphan fwait with prefixes. Don't + print `bound' operands in reverse order. + (ckprefix): Stop accumulating prefixes if we get fwait. + (OP_DIR): Print `$' before Ap operands of ljmp, lcall. + +Fri Jun 12 13:40:38 1998 Tom Tromey + + * po/Make-in (all-yes): If maintainer mode, depend on .pot file. + ($(PACKAGE).pot): Unconditionally depend on POTFILES. + +Fri Jun 12 11:04:06 1998 Andreas Schwab + + Fix problems when bfd_vma is wider than long. + * i386-dis.c: Make op_address and start_pc unsigned. + (set_op): Make parameter unsigned. + (print_insn_x86): Cast to bfd_vma when passing a value to + print_address_func. + * ns32k-dis.c (CORE_ADDR): Don't define. + (print_insn_ns32k): Change type of addr to bfd_vma. Use + bfd_scan_vma to read back address. + (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma + to format it. + * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. + (NEXTULONG): New definition. + (print_insn_m68k): Avoid overflow when computing third argument of + print_insn_arg. + (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. + Use disp instead of val to store offset values. + (print_indexed): Use base_disp instead of word to store base + displacement, to avoid overflow. + * m10300-dis.c (disassemble): Cast value to long when computing + pc-relative address, to get correct sign extension. + +Wed Jun 10 15:58:37 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Tue Jun 9 14:27:57 1998 Nick Clifton + + * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as + 'mov rX, rY'. Patch courtesy of Tony Thompson + +Mon Jun 8 18:17:21 1998 Nick Clifton + + * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. + +Fri Jun 5 23:47:55 1998 Alan Modra + + * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* + functions to void. + (OP_DSreg): Rename from OP_DSSI. + (OP_ESreg): Rename from OP_ESDI. + (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. + (DSBX): Define. + (append_seg): Rename from append_prefix. + (ptr_reg): New function. + (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. + Add DSBX for xlat. + (PREFIX_ADDR): Rename from PREFIX_ADR. + (float_reg): Add non-broken opcodes for people who don't want + UNIXWARE_COMPAT. + +Fri Jun 5 19:15:04 1998 Andreas Schwab + + * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on + 68000/68008/68010. + +Wed Jun 3 18:56:22 1998 H.J. Lu + + * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". + +Tue Jun 2 15:06:46 1998 Geoff Keating + + * ppc-opc.c (powerpc_macros): Support shifts and rotates of size + 0; produce error message for shifts of size 32 (or 64 for 64-bit + shifts), because the hardware doesn't support them. + +Wed May 27 15:29:13 1998 Nick Clifton + + * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, + LONG_2, LONG_2b formats to use this new operand. + +Tue May 26 20:47:48 1998 Stan Cox + + * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. + +Tue May 26 20:45:33 1998 Mark Alexander + + * sparc-dis.c (print_insn_sparc): big endian instruction / little + endian data support. + +Tue May 26 16:14:39 1998 Nick Clifton + + * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 + and SHORT_B3b formats to use Rb instead of Ra. + + Add FLAG_MUL16 to MUL2XH opcode. + + Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension + to existing 1.1.1 parallelisation prohibition procedure. + +Fri May 22 16:00:00 1998 Doug Evans + + * m32r-asm.c, m32r-dis.c: Regenerate. + +Tue May 19 17:36:08 1998 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly + with a shift count of 0. + +Fri May 15 14:58:31 1998 Doug Evans + + * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): New function. + +Wed May 13 17:03:59 1998 Doug Evans + + * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). + +Wed May 13 14:34:31 1998 Mark Alexander + + * sparc-dis.c (print_insn_sparc): Always fetch instructions + as big-endian on SPARClite. + +Tue May 12 11:46:31 1998 Richard Henderson + + * d30v-opc.c (pre_defined_register): Remove alias for r0. + +Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) + + * po/Make-in (install-info): New target. + +Thu May 7 17:15:59 1998 Ian Lance Taylor + + * configure.in (WIN32LIBADD): Add -lintl on cygwin32. + * configure: Rebuild. + +Thu May 7 12:49:46 1998 Frank Ch. Eigler + + * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand + variety of ISA2 instructions to set bottom ten bits of trap code. + +Thu May 7 11:54:25 1998 Ian Lance Taylor + + * Makefile.am (config.status): Add explicit target so that + config.status depends upon bfd/configure.in. + * Makefile.in: Rebuild. + +Thu May 7 09:33:02 1998 Frank Ch. Eigler + + * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 + instructions to set bottom ten bits of break code. + * mips-dis.c (print_insn_arg): Implement 'q' operand format used + for above optional argument. + +Wed May 6 15:30:06 1998 Klaus Kaempf + + * makefile.vms: Run dec c with /nodebug. + +Mon May 4 10:19:57 1998 Tom Tromey + + * Makefile.in: Rebuilt. + * Makefile.am: Regenerated dependencies with mkdep. + + * opintl.h (_): Define as dgettext. + +Tue Apr 28 14:12:12 1998 Nick Clifton + + * cgen-asm.c: Internationalised. + * m32r-asm.c: Internationalised. + * m32r-dis.c: Internationalised. + * m32r-opc.c: Internationalised. + + * aclocal.m4: Regenerated. + * configure: Regenerated. + * Makefile.am (POTFILES): Remove inclusion of BFD_H. + * Makefile.in: Rebuild. + * po/POTFILES.in: Rebuilt using rule in Makefile.in. + * po/opcodes.pot: Rebuilt after changing POTFILES.in. + +Tue Apr 28 13:13:13 1998 Ian Lance Taylor + + * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT + after AC_PROG_CC. + * aclocal.m4, configure: Rebuild with current tools. + +Mon Apr 27 14:31:00 1998 Nick Clifton + + * opintl.h: New file - contains internationalisation macros used + by source files in this directory. + * po/: New subdirectory - contains internationalisation files. + * po/Make-in: New file - Makefile constructor. + * po/POTFILES.in: New file - list of files in opcodes directory + that should be scan for internationalisation macros. + * po/opcodes.pot: New file - list of internationisation strings + found in files mentioned in po/POTFILES.in. + * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS + entry. Add intl directory to include paths. + * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, + HAVE_STRCPY, HAVE_LC_MESSAGES + * configure.in: Add rule to build Makefile in po subdirectory. + * Makefile.in: Rebuilt. + * aclocal.m4: Rebuilt. + * config.in: Rebuilt. + * configure: Rebuilt. + * alpha-opc.c: Internationalised. + * arc-dis.c: Internationalised. + * arc-opc.c: Internationalised. + * arm-dis.c: Internationalised. + * cgen-asm.c: Internationalised. + * d30v-dis.c: Internationalised. + * dis-buf.c: Internationalised. + * h8300-dis.c: Internationalised. + * h8500-dis.c: Internationalised. + * i386-dis.c: Internationalised. + * m10200-dis.c: Internationalised. + * m10300-dis.c: Internationalised. + * m68k-dis.c: Internationalised. + * m88k-dis.c: Internationalised. + * mips-dis.c: Internationalised. + * ns32k-dis.c: Internationalised. + * opintl.h: Internationalised. + * ppc-opc.c: Internationalised. + * sparc-dis.c: Internationalised. + * v850-dis.c: Internationalised. + * v850-opc.c: Internationalised. + +Mon Apr 27 10:33:56 1998 Doug Evans + + * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. + (asm_hash_table_entries): New variable. + (cgen_asm_init): Free asm_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_asm_hash_table): Use them. Hash macro insns as well. + (cgen_asm_lookup_insn): Update. + * cgen-dis.c (cgen_current_opcode_table): Renamed from ..._data. + (dis_hash_table_entries): New variable. + (cgen_dis_init): Free dis_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_dis_hash_table): Use them. Hash macro insns as well. + (cgen_dis_lookup_insn): Update. + * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. + (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. + (cgen_macro_insn_count): New function. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Fri Apr 24 16:07:57 1998 Alan Modra + + * i386-dis.c (OP_DSSI): Print segment override. + +Mon Apr 13 16:59:39 1998 Nick Clifton + + * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' + operator. + +Mon Apr 13 16:50:27 1998 Ian Lance Taylor + + * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. + (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. + * configure.in: Define and substitute WIN32LDFLAGS and + WIN32LIBADD. + * aclocal.m4: Rebuild with new libtool. + * configure, Makefile.in: Rebuild. + +Fri Apr 10 18:14:31 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Sun Apr 5 16:04:39 1998 H.J. Lu + + * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists + before trying to copy it. + * Makefile.in: Rebuild. + +Thu Apr 2 17:25:49 1998 Nick Clifton + + * m32r-opc.c: Use signed immediate values for CMPUI instruction. + +Wed Apr 1 16:20:27 1998 Ian Dall + + * ns32k-dis.c (bit_extract_simple): New function to extract bits + from an arbitrary valid buffer instead of fetching them on demand + using fetch_data(). + (invalid_float): use bit_extract_simple() instead of bit_extract(). + +Tue Mar 31 11:09:08 1998 Ian Lance Taylor + + From H.J. Lu : + * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew + to Ev for both. + +Mon Mar 30 17:32:03 1998 Ian Lance Taylor + + * Branched binutils 2.9. + +Mon Mar 30 15:18:00 1998 Ken Raeburn + + * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when + disassembling last 4 bytes of a section. + +Fri Mar 27 18:08:13 1998 Ian Lance Taylor + + Fix some gcc -Wall warnings: + * arc-dis.c (print_insn): Add casts to avoid warnings. + * cgen-opc.c (cgen_keyword_lookup_name): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. + * m10200-dis.c (disassemble): Likewise. + * m10300-dis.c (disassemble): Likewise. + * ns32k-dis.c (print_insn_ns32k): Likewise. + * ppc-opc.c (insert_ral, insert_ram): Likewise. + * cgen-dis.c (build_dis_hash_table): Remove used local variables. + * cgen-opc.c (cgen_keyword_search_next): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. + * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. + * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. + * tic80-dis.c (print_one_instruction): Likewise. + * w65-dis.c (print_operand): Likewise. + * z8k-dis.c (fetch_data): Likewise. + * a29k-dis.c: Add return type for find_byte_func_type. + * arc-opc.c: Include . Remove declarations of + insert_multshift and extract_multshift. + * d30v-dis.c (lookup_opcode): Parenthesize assignments in + conditionals. + (extract_value): Fully parenthesize expression. + * h8500-dis.c (print_insn_h8500): Initialize local variables. + * h8500-opc.h (h8500_table): Fully bracket initializer. + * w65-opc.h (optable): Likewise. + * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. + * i386-dis.c (OP_E): Initialize local variables. + * m10200-dis.c (print_insn_mn10200): Likewise. + * mips-dis.c (print_insn_mips16): Likewise. + * sh-dis.c (print_insn_shx): Likewise. + * v850-dis.c (print_insn_v850): Likewise. + * ns32k-dis.c (print_insn_arg): Declare. + (get_displacement, invalid_float): Declare. + (list_search, sign_extend, flip_bytes): Declare return type. + (get_displacement): Likewise. + (print_insn_arg): Likewise. Make d int. Fix sprintf format + string. + (print_insn_ns32k): Make i unsigned. + (invalid_float): Make static. Declare type of val. + * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen + on each for iteration. + * tic30-dis.c (get_indirect_operand): Likewise. + * z8k-dis.c (print_insn_z8001): Declare return type. + (print_insn_z8002): Likewise. + (unparse_instr): Fix sprintf format strings. + +Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Add "sync.l" and "sync.p". + +Wed Mar 25 14:32:48 1998 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Use info->mach to select the + default m68k variant to recognize. + + * i960-dis.c (pinsn): Change type of first argument to bfd_vma. + (ctrl, cobr, mem, ea): Likewise. + (print_addr): Likewise. Remove cast. + (ea): Cast argument of print_addr to bfd_vma. + + * cgen-asm.c (cgen_parse_signed_integer): Fix type of local + variable value. + (cgen_parse_unsigned_integer): Likewise. + (cgen_parse_address): Likewise. + +Wed Mar 25 14:31:31 1998 Ian Lance Taylor + + * i960-dis.c (ctrl): Add full braces to structure initialization. + (cobr, mem, reg): Likewise. + (ea): Correct parenthesization in expression. + + * cgen-asm.c: Include . + (build_asm_hash_table): Remove unused local variable i. + (cgen_parse_keyword): Add casts to avoid warnings. + + * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF + symbol. Fix indentation. + (print_insn_little_arm): Likewise. + +Fri Mar 20 18:55:18 1998 Ian Lance Taylor + + * configure.in: Use AM_DISABLE_SHARED. + * aclocal.m4, configure: Rebuild with libtool 1.2. + +Thu Mar 19 15:46:53 1998 Nick Clifton + + These patches are courtesy of Jonathan Walton and Tony Thompson + (athompso@cambridge.arm.com). + + * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC + relative addresses. + + * arm-opc.h (thumb_opcodes): Annotate PC relative addresses with + both the offset and the label closest to the destination. + +Sat Mar 14 23:47:14 1998 Doug Evans + + * m32r-opc.h: Regenerate. + +Wed Mar 4 12:08:14 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Sat Feb 28 16:02:34 1998 Nick Clifton + + * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not + assume that info->symbols is non-empty. + +Sat Feb 28 12:19:05 1998 Richard Henderson + + * alpha-opc.c (cvtqs) There is no such thing. + (cvttq): Missing most of the /*d variants. + +Thu Feb 26 15:53:09 1998 Michael Meissner + + * d30v-opc.c (d30v_opcode_table): Indicate which instructions are + delayed branches or jumps. + +Tue Feb 24 10:46:44 1998 Doug Evans + + * arm-dis.c (print_insn_{big,little}_arm): info->symbol changed + to *info->symbols. + * mips-dis.c (print_insn_{big,little}_mips): Likewise. + * tic30-dis.c (print_branch): Likewise. + +Tue Feb 24 11:06:18 1998 Nick Clifton + + * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove + saved_symbol code as it is no longer needed. + +Mon Feb 23 13:16:17 1998 Doug Evans + + * cgen-asm.c: Include symcat.h. + * cgen-dis.c, cgen-opc.c: Ditto. + * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. + +Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'. + +Thu Feb 19 16:51:13 1998 Doug Evans + + * m32r-opc.[ch]: Regenerate. + +Tue Feb 17 17:14:50 1998 Doug Evans + + * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max + arguments. Don't perform validation here. + * m32r-asm.c, m32r-dis.c, m32r-opc.c: Regenerate. + +Fri Feb 13 14:26:06 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Fri Feb 13 14:53:02 1998 Ian Lance Taylor + + * Makefile.am (AUTOMAKE_OPTIONS): Define. + * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e. + +Fri Feb 13 10:21:09 1998 Mark Alexander + + * m10300-dis.c (print_insn_mn10300): Recognize break instruction. + +Fri Feb 13 13:12:14 1998 Ian Lance Taylor + + * configure.in: Get the version number from BFD. + * configure: Rebuild. + + From H.J. Lu : + * Makefile.am (libopcodes_la_LDFLAGS): Define. + * Makefile.in: Rebuild. + +Fri Feb 13 09:50:32 1998 Nick Clifton + + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + +Thu Feb 12 11:01:40 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Thu Feb 12 03:41:00 1998 J"orn Rennecke + + Fix rac to accept only a0: + * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): + Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. + Introduce OPERAND_GPR. + * d10v-dis.c (print_operand): Likewise. + +Wed Feb 11 18:58:34 1998 Doug Evans + + * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. + (cgen_hw_lookup): Make result const. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Sat Feb 7 15:30:27 1998 Ian Lance Taylor + + * configure, aclocal.m4: Rebuild with new libtool. + +Thu Feb 5 17:56:10 1998 Michael Meissner + + * d30v-opc.c (repeat{,i} instructions): Repeat/repeati + instructions use a PC relative branch, not absolute. + +Wed Feb 4 19:17:37 1998 Ian Lance Taylor + + * configure.in: Set libtool_enable_shared rather than + libtool_shared. Remove diversion hack. + * configure, Makefile.in, aclocal.m4: Rebuild with new libtool. + +Tue Feb 3 17:19:40 1998 Doug Evans + + * cgen-opc.c (cgen_set_cpu): Initialize hardware table. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Mon Feb 2 19:22:15 1998 Steve Haworth + + * tic30-dis.c: New file. + * disassemble.c (disassembler): Add bfd_arch_tic30 case. + * configure.in: Handle bfd_tic30_arch. + * Makefile.am: Rebuild dependencies. + (CFILES): Add tic30-dis.c + (ALL_MACHINES): Add tic30-dis.lo. + * configure, Makefile.in: Rebuild. + +Thu Jan 29 13:02:56 1998 Doug Evans + + * m32r-opc.h (HAVE_CPU_M32R): Define. + +Wed Jan 28 09:55:03 1998 Nick Clifton + + * v850-opc.c (insertion routines): If both alignment and size is + wrong then report this. + +Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (_print_insn_mips): Set target_processor as appropriate. + Only recognize instructions for the current target_processor. + +Thu Jan 22 16:20:17 1998 Fred Fish + + * d10v-dis.c (PC_MASK): Correct value. + (print_operand): If there's a reloc, don't calculate the + address because they could be in different sections. + +Fri Jan 16 15:29:11 1998 Jim Blandy + + * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu" + instruction after the 4650's "mul" instruction; nobody's using the + 4010 these days. If object files someday indicate which processor + variant they're intended for, we can do a better job at this. + +Mon Jan 12 14:43:54 1998 Doug Evans + + * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using + table provided entry size. Use CGEN_INSN_MNEMONIC. + (cgen_parse_keyword): Rewrite. + * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using + table provided entry size. Use CGEN_INSN_MASK_BITSIZE. + * cgen-opc.c: Clean up pass over `struct foo' usage. + (cgen_keyword_lookup_value): Handle "" entry. + (cgen_keyword_add): Likewise. + +For older changes see ChangeLog-9297 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/opcodes/MAINTAINERS b/opcodes/MAINTAINERS new file mode 100644 index 0000000..d59a3bd --- /dev/null +++ b/opcodes/MAINTAINERS @@ -0,0 +1 @@ +See ../binutils/MAINTAINERS diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am new file mode 100644 index 0000000..0996b2e --- /dev/null +++ b/opcodes/Makefile.am @@ -0,0 +1,697 @@ +## Process this file with automake to generate Makefile.in + +AUTOMAKE_OPTIONS = cygnus + +SUBDIRS = po + +INCDIR = $(srcdir)/../include +BFDDIR = $(srcdir)/../bfd +MKDEP = gcc -MM + +WARN_CFLAGS = @WARN_CFLAGS@ +AM_CFLAGS = $(WARN_CFLAGS) + +bfdlibdir = @bfdlibdir@ +bfdincludedir = @bfdincludedir@ + +bfdlib_LTLIBRARIES = libopcodes.la + +# This is where bfd.h lives. +BFD_H = ../bfd/bfd.h + +# This is where libiberty lives. +LIBIBERTY = ../libiberty/libiberty.a + +# Header files. +HFILES = \ + arm-opc.h \ + fr30-desc.h fr30-opc.h \ + h8500-opc.h \ + ia64-asmtab.h \ + ia64-opc.h \ + m32r-desc.h m32r-opc.h \ + mcore-opc.h \ + openrisc-desc.h openrisc-opc.h \ + sh-opc.h \ + sh64-opc.h \ + sysdep.h \ + w65-opc.h \ + xstormy16-desc.h xstormy16-opc.h \ + z8k-opc.h + +# C source files that correspond to .o's. +CFILES = \ + a29k-dis.c \ + alpha-dis.c \ + alpha-opc.c \ + arc-dis.c \ + arc-opc.c \ + arc-ext.c \ + arm-dis.c \ + avr-dis.c \ + cgen-asm.c \ + cgen-dis.c \ + cgen-opc.c \ + cris-dis.c \ + cris-opc.c \ + d10v-dis.c \ + d10v-opc.c \ + d30v-dis.c \ + d30v-opc.c \ + dlx-dis.c \ + dis-buf.c \ + disassemble.c \ + fr30-asm.c \ + fr30-desc.c \ + fr30-dis.c \ + fr30-ibld.c \ + fr30-opc.c \ + h8300-dis.c \ + h8500-dis.c \ + hppa-dis.c \ + i370-dis.c \ + i370-opc.c \ + i386-dis.c \ + i860-dis.c \ + i960-dis.c \ + ia64-dis.c \ + ia64-opc-a.c \ + ia64-opc-b.c \ + ia64-opc-f.c \ + ia64-opc-i.c \ + ia64-opc-m.c \ + ia64-opc-d.c \ + ia64-opc.c \ + ia64-gen.c \ + ia64-asmtab.c \ + m32r-asm.c \ + m32r-desc.c \ + m32r-dis.c \ + m32r-ibld.c \ + m32r-opc.c \ + m32r-opinst.c \ + m68hc11-dis.c \ + m68hc11-opc.c \ + m68k-dis.c \ + m68k-opc.c \ + m88k-dis.c \ + mcore-dis.c \ + mips-dis.c \ + mips-opc.c \ + mips16-opc.c \ + m10200-dis.c \ + m10200-opc.c \ + m10300-dis.c \ + m10300-opc.c \ + mmix-dis.c \ + mmix-opc.c \ + ns32k-dis.c \ + openrisc-asm.c \ + openrisc-desc.c \ + openrisc-dis.c \ + openrisc-ibld.c \ + openrisc-opc.c \ + or32-dis.c \ + or32-opc.c \ + pdp11-dis.c \ + pdp11-opc.c \ + pj-dis.c \ + pj-opc.c \ + ppc-dis.c \ + ppc-opc.c \ + s390-mkopc.c \ + s390-opc.c \ + s390-dis.c \ + sh-dis.c \ + sh64-dis.c \ + sh64-opc.c \ + sparc-dis.c \ + sparc-opc.c \ + tic30-dis.c \ + tic54x-dis.c \ + tic54x-opc.c \ + tic80-dis.c \ + tic80-opc.c \ + v850-dis.c \ + v850-opc.c \ + vax-dis.c \ + w65-dis.c \ + xstormy16-asm.c \ + xstormy16-desc.c \ + xstormy16-dis.c \ + xstormy16-ibld.c \ + xstormy16-opc.c \ + z8k-dis.c \ + z8kgen.c + +ALL_MACHINES = \ + a29k-dis.lo \ + alpha-dis.lo \ + alpha-opc.lo \ + arc-dis.lo \ + arc-opc.lo \ + arc-ext.lo \ + arm-dis.lo \ + avr-dis.lo \ + cgen-asm.lo \ + cgen-dis.lo \ + cgen-opc.lo \ + cris-dis.lo \ + cris-opc.lo \ + d10v-dis.lo \ + d10v-opc.lo \ + d30v-dis.lo \ + d30v-opc.lo \ + dlx-dis.lo \ + fr30-asm.lo \ + fr30-desc.lo \ + fr30-dis.lo \ + fr30-ibld.lo \ + fr30-opc.lo \ + h8300-dis.lo \ + h8500-dis.lo \ + hppa-dis.lo \ + i386-dis.lo \ + i370-dis.lo \ + i370-opc.lo \ + i860-dis.lo \ + i960-dis.lo \ + ia64-dis.lo \ + ia64-opc.lo \ + m32r-asm.lo \ + m32r-desc.lo \ + m32r-dis.lo \ + m32r-ibld.lo \ + m32r-opc.lo \ + m32r-opinst.lo \ + m68hc11-dis.lo \ + m68hc11-opc.lo \ + m68k-dis.lo \ + m68k-opc.lo \ + m88k-dis.lo \ + m10200-dis.lo \ + m10200-opc.lo \ + m10300-dis.lo \ + m10300-opc.lo \ + mcore-dis.lo \ + mips-dis.lo \ + mips-opc.lo \ + mips16-opc.lo \ + mmix-dis.lo \ + mmix-opc.lo \ + ns32k-dis.lo \ + openrisc-asm.lo \ + openrisc-desc.lo \ + openrisc-dis.lo \ + openrisc-ibld.lo \ + openrisc-opc.lo \ + or32-dis.lo \ + or32-opc.lo \ + pdp11-dis.lo \ + pdp11-opc.lo \ + pj-dis.lo \ + pj-opc.lo \ + ppc-dis.lo \ + ppc-opc.lo \ + s390-dis.lo \ + s390-opc.lo \ + sh-dis.lo \ + sh64-dis.lo \ + sh64-opc.lo \ + sparc-dis.lo \ + sparc-opc.lo \ + tic30-dis.lo \ + tic54x-dis.lo \ + tic54x-opc.lo \ + tic80-dis.lo \ + tic80-opc.lo \ + v850-dis.lo \ + v850-opc.lo \ + vax-dis.lo \ + w65-dis.lo \ + xstormy16-asm.lo \ + xstormy16-desc.lo \ + xstormy16-dis.lo \ + xstormy16-ibld.lo \ + xstormy16-opc.lo \ + z8k-dis.lo + +OFILES = @BFD_MACHINES@ + +INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl + +disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h + $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c + +libopcodes_la_SOURCES = dis-buf.c disassemble.c +libopcodes_la_DEPENDENCIES = $(OFILES) +libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ +libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ + +# libtool will build .libs/libopcodes.a. We create libopcodes.a in +# the build directory so that we don't have to convert all the +# programs that use libopcodes.a simultaneously. This is a hack which +# should be removed if everything else starts using libtool. FIXME. + +noinst_LIBRARIES = libopcodes.a + +stamp-lib: libopcodes.la + libtooldir=`$(LIBTOOL) --config | sed -n -e 's/^objdir=//p'`; \ + if [ -f $$libtooldir/libopcodes.a ]; then \ + cp $$libtooldir/libopcodes.a libopcodes.tmp; \ + $(RANLIB) libopcodes.tmp; \ + $(SHELL) $(srcdir)/../move-if-change libopcodes.tmp libopcodes.a; \ + else true; fi + touch stamp-lib + +libopcodes.a: stamp-lib ; @true + +POTFILES = $(HFILES) $(CFILES) +po/POTFILES.in: @MAINT@ Makefile + for file in $(POTFILES); do echo $$file; done | sort > tmp \ + && mv tmp $(srcdir)/po/POTFILES.in + +# We should reconfigure whenever bfd/configure.in changes, because +# that's where the version number comes from. +config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in + $(SHELL) ./config.status --recheck + +install-bfdlibLTLIBRARIES: @INSTALL_LIBBFD_TRUE@install_libopcodes + @$(NORMAL_INSTALL) + +uninstall-bfdlibLTLIBRARIES: @INSTALL_LIBBFD_TRUE@uninstall_libopcodes + @$(NORMAL_UNINSTALL) + +.PHONY: install_libopcodes uninstall_libopcodes +install_libopcodes: $(bfdlib_LTLIBRARIES) + $(mkinstalldirs) $(DESTDIR)$(bfdlibdir) + $(mkinstalldirs) $(DESTDIR)$(bfdincludedir) + @list='$(bfdlib_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + echo "$(LIBTOOL) --mode=install $(INSTALL) $$p $(DESTDIR)$(bfdlibdir)/$$p"; \ + $(LIBTOOL) --mode=install $(INSTALL) $$p $(DESTDIR)$(bfdlibdir)/$$p; \ + else :; fi; \ + done + $(INSTALL_DATA) $(INCDIR)/dis-asm.h $(DESTDIR)$(bfdincludedir)/dis-asm.h + +uninstall_libopcodes: + list='$(bfdlib_LTLIBRARIES)'; for p in $$list; do \ + $(LIBTOOL) --mode=uninstall rm -f $(DESTDIR)$(bfdlibdir)/$$p; \ + done + rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h + +CLEANFILES = \ + stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-xstormy16 \ + libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 + + +CGENDIR = @cgendir@ +CPUDIR = $(CGENDIR)/cpu +CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` +CGENFLAGS = -v + +CGENDEPS = ../cgen/stamp-cgen \ + $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ + $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ + $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ + $(CGENDIR)/opc-opinst.scm \ + cgen-asm.in cgen-dis.in cgen-ibld.in + +if CGEN_MAINT +M32R_DEPS = stamp-m32r +FR30_DEPS = stamp-fr30 +OPENRISC_DEPS = stamp-openrisc +XSTORMY16_DEPS = stamp-xstormy16 +else +M32R_DEPS = +FR30_DEPS = +OPENRISC_DEPS = +XSTORMY16_DEPS = +endif + +run-cgen: + $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \ + "$(options)" $(extrafiles) + touch stamp-${prefix} +.PHONY: run-cgen + +# For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) + @true +stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst + +$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) + @true +stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= + +$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) + @true +stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + +$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) + @true +stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + +ia64-gen: ia64-gen.o + $(LINK) ia64-gen.o $(LIBIBERTY) + +ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ + ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h + +ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl + here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c + +s390-mkopc: s390-mkopc.c + $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c + +s390-opc.tab: s390-mkopc s390-opc.txt + ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab + +sh-dis.lo: sh-dis.c + $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $< + +Makefile: $(BFDDIR)/configure.in + +# This dependency stuff is copied from BFD. + +DEP: dep.sed $(CFILES) $(HFILES) config.h + rm -f DEP1 + $(MAKE) MKDEP="$(MKDEP)" DEP1 + sed -f dep.sed < DEP1 > DEPA + echo '# IF YOU PUT ANYTHING HERE IT WILL GO AWAY' >> DEPA + if grep ' /' DEPA > /dev/null 2> /dev/null; then \ + echo 'make DEP failed!'; exit 1; \ + else \ + mv -f DEPA $@; \ + fi + +DEP1: $(CFILES) + echo '# DO NOT DELETE THIS LINE -- mkdep uses it.' > DEP2 + echo '# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.' >> DEP2 + $(MKDEP) $(INCLUDES) $(CFLAGS) $? >> DEP2 + mv -f DEP2 $@ + +dep.sed: dep-in.sed config.status + sed <$(srcdir)/dep-in.sed >dep.sed \ + -e 's!@BFD_H@!$(BFD_H)!' \ + -e 's!@INCDIR@!$(INCDIR)!' \ + -e 's!@BFDDIR@!$(BFDDIR)!' \ + -e 's!@SRCDIR@!$(srcdir)!' \ + -e 's!@TOPDIR@!'`echo $(srcdir) | sed -e s,/opcodes$$,,`'!' + +dep: DEP + sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < Makefile > tmp-Makefile + cat DEP >> tmp-Makefile + $(srcdir)/../move-if-change tmp-Makefile Makefile + +dep-in: DEP + sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.in > tmp-Makefile.in + cat DEP >> tmp-Makefile.in + $(srcdir)/../move-if-change tmp-Makefile.in $(srcdir)/Makefile.in + +dep-am: DEP + sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.am > tmp-Makefile.am + cat DEP >> tmp-Makefile.am + $(srcdir)/../move-if-change tmp-Makefile.am $(srcdir)/Makefile.am + +.PHONY: dep dep-in dep-am + +# What appears below is generated by a hacked mkdep using gcc -MM. + +# DO NOT DELETE THIS LINE -- mkdep uses it. +# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. +a29k-dis.lo: a29k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/a29k.h +alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h +alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h +arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ + $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h +arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/arc.h +arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h +arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ + $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ + opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ + $(INCDIR)/elf/reloc-macros.h +avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ + $(INCDIR)/opcode/avr.h +cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h +cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h +cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h +cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h +cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h +d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d10v.h +d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d30v.h +dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/dlx.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h +disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ + fr30-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ + fr30-opc.h opintl.h $(INCDIR)/libiberty.h +fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ + $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h +fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ + $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h +fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ + fr30-opc.h $(INCDIR)/libiberty.h +h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h +hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(BFDDIR)/libhppa.h \ + $(INCDIR)/opcode/hppa.h +i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/i370.h +i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/i370.h +i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + opintl.h +i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h +i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h +ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h +ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h +ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h +ia64-opc-i.lo: ia64-opc-i.c ia64-opc.h $(INCDIR)/opcode/ia64.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h +ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h +ia64-opc-d.lo: ia64-opc-d.c +ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \ + $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c +ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \ + $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ + ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ + ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c +ia64-asmtab.lo: ia64-asmtab.c +m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ + m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ + m32r-opc.h opintl.h $(INCDIR)/libiberty.h +m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ + $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h +m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ + $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h +m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ + m32r-opc.h $(INCDIR)/libiberty.h +m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ + m32r-opc.h +m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/m68hc11.h +m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/floatformat.h \ + $(INCDIR)/libiberty.h opintl.h $(INCDIR)/opcode/m68k.h +m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/m68k.h +m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \ + opintl.h +mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/mips.h \ + opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ + $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h +mips-opc.lo: mips-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/mips.h +mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/mips.h +m10200-dis.lo: m10200-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +m10200-opc.lo: m10200-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/mn10200.h +m10300-dis.lo: m10300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/mn10300.h +mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + opintl.h +mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h +ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(INCDIR)/opcode/ns32k.h opintl.h +openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \ + openrisc-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h +openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h +openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +openrisc-opc.lo: openrisc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \ + openrisc-opc.h $(INCDIR)/libiberty.h +or32-dis.lo: or32-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/or32.h \ + $(INCDIR)/safe-ctype.h +or32-opc.lo: or32-opc.c $(INCDIR)/safe-ctype.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/or32.h +pdp11-dis.lo: pdp11-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/pdp11.h +pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h +pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/pj.h +ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/ppc.h +ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/ppc.h opintl.h +s390-mkopc.lo: s390-mkopc.c +s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \ + s390-opc.tab +s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \ + config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/s390.h +sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h +sh64-opc.lo: sh64-opc.c sh64-opc.h +sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h +sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/sparc.h +tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h +tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ + $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h +tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h +tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/tic80.h +v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/v850.h opintl.h +vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h +xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h +xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h +z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h +z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h +# IF YOU PUT ANYTHING HERE IT WILL GO AWAY diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in new file mode 100644 index 0000000..3602cbd --- /dev/null +++ b/opcodes/Makefile.in @@ -0,0 +1,1197 @@ +# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am + +# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + + +SHELL = @SHELL@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +bindir = @bindir@ +sbindir = @sbindir@ +libexecdir = @libexecdir@ +datadir = @datadir@ +sysconfdir = @sysconfdir@ +sharedstatedir = @sharedstatedir@ +localstatedir = @localstatedir@ +libdir = @libdir@ +infodir = @infodir@ +mandir = @mandir@ +includedir = @includedir@ +oldincludedir = /usr/include + +DESTDIR = + +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ + +top_builddir = . + +ACLOCAL = @ACLOCAL@ +AUTOCONF = @AUTOCONF@ +AUTOMAKE = @AUTOMAKE@ +AUTOHEADER = @AUTOHEADER@ + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ $(AM_INSTALL_PROGRAM_FLAGS) +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +transform = @program_transform_name@ + +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_alias = @build_alias@ +build_triplet = @build@ +host_alias = @host_alias@ +host_triplet = @host@ +target_alias = @target_alias@ +target_triplet = @target@ +AR = @AR@ +AS = @AS@ +BFD_MACHINES = @BFD_MACHINES@ +CATALOGS = @CATALOGS@ +CATOBJEXT = @CATOBJEXT@ +CC = @CC@ +CC_FOR_BUILD = @CC_FOR_BUILD@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +DATADIRNAME = @DATADIRNAME@ +DLLTOOL = @DLLTOOL@ +EXEEXT = @EXEEXT@ +EXEEXT_FOR_BUILD = @EXEEXT_FOR_BUILD@ +GCJ = @GCJ@ +GCJFLAGS = @GCJFLAGS@ +GMOFILES = @GMOFILES@ +GMSGFMT = @GMSGFMT@ +GT_NO = @GT_NO@ +GT_YES = @GT_YES@ +HDEFINES = @HDEFINES@ +INCLUDE_LOCALE_H = @INCLUDE_LOCALE_H@ +INSTOBJEXT = @INSTOBJEXT@ +INTLDEPS = @INTLDEPS@ +INTLLIBS = @INTLLIBS@ +INTLOBJS = @INTLOBJS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MKINSTALLDIRS = @MKINSTALLDIRS@ +MSGFMT = @MSGFMT@ +OBJDUMP = @OBJDUMP@ +OBJEXT = @OBJEXT@ +PACKAGE = @PACKAGE@ +POFILES = @POFILES@ +POSUB = @POSUB@ +RANLIB = @RANLIB@ +STRIP = @STRIP@ +USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@ +USE_NLS = @USE_NLS@ +VERSION = @VERSION@ +WIN32LDFLAGS = @WIN32LDFLAGS@ +WIN32LIBADD = @WIN32LIBADD@ +archdefs = @archdefs@ +cgendir = @cgendir@ +l = @l@ + +AUTOMAKE_OPTIONS = cygnus + +SUBDIRS = po + +INCDIR = $(srcdir)/../include +BFDDIR = $(srcdir)/../bfd +MKDEP = gcc -MM + +WARN_CFLAGS = @WARN_CFLAGS@ +AM_CFLAGS = $(WARN_CFLAGS) + +bfdlibdir = @bfdlibdir@ +bfdincludedir = @bfdincludedir@ + +bfdlib_LTLIBRARIES = libopcodes.la + +# This is where bfd.h lives. +BFD_H = ../bfd/bfd.h + +# This is where libiberty lives. +LIBIBERTY = ../libiberty/libiberty.a + +# Header files. +HFILES = \ + arm-opc.h \ + fr30-desc.h fr30-opc.h \ + h8500-opc.h \ + ia64-asmtab.h \ + ia64-opc.h \ + m32r-desc.h m32r-opc.h \ + mcore-opc.h \ + openrisc-desc.h openrisc-opc.h \ + sh-opc.h \ + sh64-opc.h \ + sysdep.h \ + w65-opc.h \ + xstormy16-desc.h xstormy16-opc.h \ + z8k-opc.h + + +# C source files that correspond to .o's. +CFILES = \ + a29k-dis.c \ + alpha-dis.c \ + alpha-opc.c \ + arc-dis.c \ + arc-opc.c \ + arc-ext.c \ + arm-dis.c \ + avr-dis.c \ + cgen-asm.c \ + cgen-dis.c \ + cgen-opc.c \ + cris-dis.c \ + cris-opc.c \ + d10v-dis.c \ + d10v-opc.c \ + d30v-dis.c \ + d30v-opc.c \ + dlx-dis.c \ + dis-buf.c \ + disassemble.c \ + fr30-asm.c \ + fr30-desc.c \ + fr30-dis.c \ + fr30-ibld.c \ + fr30-opc.c \ + h8300-dis.c \ + h8500-dis.c \ + hppa-dis.c \ + i370-dis.c \ + i370-opc.c \ + i386-dis.c \ + i860-dis.c \ + i960-dis.c \ + ia64-dis.c \ + ia64-opc-a.c \ + ia64-opc-b.c \ + ia64-opc-f.c \ + ia64-opc-i.c \ + ia64-opc-m.c \ + ia64-opc-d.c \ + ia64-opc.c \ + ia64-gen.c \ + ia64-asmtab.c \ + m32r-asm.c \ + m32r-desc.c \ + m32r-dis.c \ + m32r-ibld.c \ + m32r-opc.c \ + m32r-opinst.c \ + m68hc11-dis.c \ + m68hc11-opc.c \ + m68k-dis.c \ + m68k-opc.c \ + m88k-dis.c \ + mcore-dis.c \ + mips-dis.c \ + mips-opc.c \ + mips16-opc.c \ + m10200-dis.c \ + m10200-opc.c \ + m10300-dis.c \ + m10300-opc.c \ + mmix-dis.c \ + mmix-opc.c \ + ns32k-dis.c \ + openrisc-asm.c \ + openrisc-desc.c \ + openrisc-dis.c \ + openrisc-ibld.c \ + openrisc-opc.c \ + or32-dis.c \ + or32-opc.c \ + pdp11-dis.c \ + pdp11-opc.c \ + pj-dis.c \ + pj-opc.c \ + ppc-dis.c \ + ppc-opc.c \ + s390-mkopc.c \ + s390-opc.c \ + s390-dis.c \ + sh-dis.c \ + sh64-dis.c \ + sh64-opc.c \ + sparc-dis.c \ + sparc-opc.c \ + tic30-dis.c \ + tic54x-dis.c \ + tic54x-opc.c \ + tic80-dis.c \ + tic80-opc.c \ + v850-dis.c \ + v850-opc.c \ + vax-dis.c \ + w65-dis.c \ + xstormy16-asm.c \ + xstormy16-desc.c \ + xstormy16-dis.c \ + xstormy16-ibld.c \ + xstormy16-opc.c \ + z8k-dis.c \ + z8kgen.c + + +ALL_MACHINES = \ + a29k-dis.lo \ + alpha-dis.lo \ + alpha-opc.lo \ + arc-dis.lo \ + arc-opc.lo \ + arc-ext.lo \ + arm-dis.lo \ + avr-dis.lo \ + cgen-asm.lo \ + cgen-dis.lo \ + cgen-opc.lo \ + cris-dis.lo \ + cris-opc.lo \ + d10v-dis.lo \ + d10v-opc.lo \ + d30v-dis.lo \ + d30v-opc.lo \ + dlx-dis.lo \ + fr30-asm.lo \ + fr30-desc.lo \ + fr30-dis.lo \ + fr30-ibld.lo \ + fr30-opc.lo \ + h8300-dis.lo \ + h8500-dis.lo \ + hppa-dis.lo \ + i386-dis.lo \ + i370-dis.lo \ + i370-opc.lo \ + i860-dis.lo \ + i960-dis.lo \ + ia64-dis.lo \ + ia64-opc.lo \ + m32r-asm.lo \ + m32r-desc.lo \ + m32r-dis.lo \ + m32r-ibld.lo \ + m32r-opc.lo \ + m32r-opinst.lo \ + m68hc11-dis.lo \ + m68hc11-opc.lo \ + m68k-dis.lo \ + m68k-opc.lo \ + m88k-dis.lo \ + m10200-dis.lo \ + m10200-opc.lo \ + m10300-dis.lo \ + m10300-opc.lo \ + mcore-dis.lo \ + mips-dis.lo \ + mips-opc.lo \ + mips16-opc.lo \ + mmix-dis.lo \ + mmix-opc.lo \ + ns32k-dis.lo \ + openrisc-asm.lo \ + openrisc-desc.lo \ + openrisc-dis.lo \ + openrisc-ibld.lo \ + openrisc-opc.lo \ + or32-dis.lo \ + or32-opc.lo \ + pdp11-dis.lo \ + pdp11-opc.lo \ + pj-dis.lo \ + pj-opc.lo \ + ppc-dis.lo \ + ppc-opc.lo \ + s390-dis.lo \ + s390-opc.lo \ + sh-dis.lo \ + sh64-dis.lo \ + sh64-opc.lo \ + sparc-dis.lo \ + sparc-opc.lo \ + tic30-dis.lo \ + tic54x-dis.lo \ + tic54x-opc.lo \ + tic80-dis.lo \ + tic80-opc.lo \ + v850-dis.lo \ + v850-opc.lo \ + vax-dis.lo \ + w65-dis.lo \ + xstormy16-asm.lo \ + xstormy16-desc.lo \ + xstormy16-dis.lo \ + xstormy16-ibld.lo \ + xstormy16-opc.lo \ + z8k-dis.lo + + +OFILES = @BFD_MACHINES@ + +INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl + +libopcodes_la_SOURCES = dis-buf.c disassemble.c +libopcodes_la_DEPENDENCIES = $(OFILES) +libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ +libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ + +# libtool will build .libs/libopcodes.a. We create libopcodes.a in +# the build directory so that we don't have to convert all the +# programs that use libopcodes.a simultaneously. This is a hack which +# should be removed if everything else starts using libtool. FIXME. + +noinst_LIBRARIES = libopcodes.a + +POTFILES = $(HFILES) $(CFILES) + +CLEANFILES = \ + stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-xstormy16 \ + libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 + + +CGENDIR = @cgendir@ +CPUDIR = $(CGENDIR)/cpu +CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` +CGENFLAGS = -v + +CGENDEPS = ../cgen/stamp-cgen \ + $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ + $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ + $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ + $(CGENDIR)/opc-opinst.scm \ + cgen-asm.in cgen-dis.in cgen-ibld.in + +@CGEN_MAINT_TRUE@M32R_DEPS = @CGEN_MAINT_TRUE@stamp-m32r +@CGEN_MAINT_FALSE@M32R_DEPS = +@CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 +@CGEN_MAINT_FALSE@FR30_DEPS = +@CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc +@CGEN_MAINT_FALSE@OPENRISC_DEPS = +@CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16 +@CGEN_MAINT_FALSE@XSTORMY16_DEPS = +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs +CONFIG_HEADER = config.h +CONFIG_CLEAN_FILES = +LIBRARIES = $(noinst_LIBRARIES) + + +DEFS = @DEFS@ -I. -I$(srcdir) -I. +CPPFLAGS = @CPPFLAGS@ +LDFLAGS = @LDFLAGS@ +LIBS = @LIBS@ +libopcodes_a_LIBADD = +libopcodes_a_SOURCES = libopcodes.a.c +libopcodes_a_OBJECTS = libopcodes.a.$(OBJEXT) +LTLIBRARIES = $(bfdlib_LTLIBRARIES) + +libopcodes_la_OBJECTS = dis-buf.lo disassemble.lo +CFLAGS = @CFLAGS@ +COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(LDFLAGS) -o $@ +DIST_COMMON = ./stamp-h.in ChangeLog Makefile.am Makefile.in \ +acinclude.m4 aclocal.m4 config.in configure configure.in + + +DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) + +TAR = gtar +GZIP_ENV = --best +SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES) +OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS) + +all: all-redirect +.SUFFIXES: +.SUFFIXES: .S .c .lo .o .obj .s +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4) + cd $(top_srcdir) && $(AUTOMAKE) --cygnus Makefile + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$@ CONFIG_HEADERS= $(SHELL) ./config.status + +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ configure.in acinclude.m4 + cd $(srcdir) && $(ACLOCAL) +$(srcdir)/configure: @MAINTAINER_MODE_TRUE@$(srcdir)/configure.in $(ACLOCAL_M4) $(CONFIGURE_DEPENDENCIES) + cd $(srcdir) && $(AUTOCONF) + +config.h: stamp-h + @if test ! -f $@; then \ + rm -f stamp-h; \ + $(MAKE) stamp-h; \ + else :; fi +stamp-h: $(srcdir)/config.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES= CONFIG_HEADERS=config.h:config.in \ + $(SHELL) ./config.status + @echo timestamp > stamp-h 2> /dev/null +$(srcdir)/config.in: @MAINTAINER_MODE_TRUE@$(srcdir)/stamp-h.in + @if test ! -f $@; then \ + rm -f $(srcdir)/stamp-h.in; \ + $(MAKE) $(srcdir)/stamp-h.in; \ + else :; fi +$(srcdir)/stamp-h.in: $(top_srcdir)/configure.in $(ACLOCAL_M4) + cd $(top_srcdir) && $(AUTOHEADER) + @echo timestamp > $(srcdir)/stamp-h.in 2> /dev/null + +mostlyclean-hdr: + +clean-hdr: + +distclean-hdr: + -rm -f config.h + +maintainer-clean-hdr: + +mostlyclean-noinstLIBRARIES: + +clean-noinstLIBRARIES: + -test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES) + +distclean-noinstLIBRARIES: + +maintainer-clean-noinstLIBRARIES: + +.c.o: + $(COMPILE) -c $< + +# FIXME: We should only use cygpath when building on Windows, +# and only if it is available. +.c.obj: + $(COMPILE) -c `cygpath -w $<` + +.s.o: + $(COMPILE) -c $< + +.S.o: + $(COMPILE) -c $< + +mostlyclean-compile: + -rm -f *.o core *.core + -rm -f *.$(OBJEXT) + +clean-compile: + +distclean-compile: + -rm -f *.tab.c + +maintainer-clean-compile: + +.c.lo: + $(LIBTOOL) --mode=compile $(COMPILE) -c $< + +.s.lo: + $(LIBTOOL) --mode=compile $(COMPILE) -c $< + +.S.lo: + $(LIBTOOL) --mode=compile $(COMPILE) -c $< + +mostlyclean-libtool: + -rm -f *.lo + +clean-libtool: + -rm -rf .libs _libs + +distclean-libtool: + +maintainer-clean-libtool: + +mostlyclean-bfdlibLTLIBRARIES: + +clean-bfdlibLTLIBRARIES: + -test -z "$(bfdlib_LTLIBRARIES)" || rm -f $(bfdlib_LTLIBRARIES) + +distclean-bfdlibLTLIBRARIES: + +maintainer-clean-bfdlibLTLIBRARIES: + +libopcodes.la: $(libopcodes_la_OBJECTS) $(libopcodes_la_DEPENDENCIES) + $(LINK) -rpath $(bfdlibdir) $(libopcodes_la_LDFLAGS) $(libopcodes_la_OBJECTS) $(libopcodes_la_LIBADD) $(LIBS) + +# This directory's subdirectories are mostly independent; you can cd +# into them and run `make' without going through this Makefile. +# To change the values of `make' variables: instead of editing Makefiles, +# (1) if the variable is set in `config.status', edit `config.status' +# (which will cause the Makefiles to be regenerated when you run `make'); +# (2) otherwise, pass the desired values on the `make' command line. + +@SET_MAKE@ + +all-recursive install-data-recursive install-exec-recursive \ +installdirs-recursive install-recursive uninstall-recursive install-info-recursive \ +check-recursive installcheck-recursive info-recursive dvi-recursive: + @set fnord $(MAKEFLAGS); amf=$$2; \ + dot_seen=no; \ + target=`echo $@ | sed s/-recursive//`; \ + list='$(SUBDIRS)'; for subdir in $$list; do \ + echo "Making $$target in $$subdir"; \ + if test "$$subdir" = "."; then \ + dot_seen=yes; \ + local_target="$$target-am"; \ + else \ + local_target="$$target"; \ + fi; \ + (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ + || case "$$amf" in *=*) exit 1;; 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changes, because +# that's where the version number comes from. +config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in + $(SHELL) ./config.status --recheck + +install-bfdlibLTLIBRARIES: @INSTALL_LIBBFD_TRUE@install_libopcodes + @$(NORMAL_INSTALL) + +uninstall-bfdlibLTLIBRARIES: @INSTALL_LIBBFD_TRUE@uninstall_libopcodes + @$(NORMAL_UNINSTALL) + +.PHONY: install_libopcodes uninstall_libopcodes +install_libopcodes: $(bfdlib_LTLIBRARIES) + $(mkinstalldirs) $(DESTDIR)$(bfdlibdir) + $(mkinstalldirs) $(DESTDIR)$(bfdincludedir) + @list='$(bfdlib_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + echo "$(LIBTOOL) --mode=install $(INSTALL) $$p $(DESTDIR)$(bfdlibdir)/$$p"; \ + $(LIBTOOL) --mode=install $(INSTALL) $$p $(DESTDIR)$(bfdlibdir)/$$p; \ + else :; fi; \ + done + $(INSTALL_DATA) $(INCDIR)/dis-asm.h $(DESTDIR)$(bfdincludedir)/dis-asm.h + +uninstall_libopcodes: + list='$(bfdlib_LTLIBRARIES)'; for p in $$list; do \ + $(LIBTOOL) --mode=uninstall rm -f $(DESTDIR)$(bfdlibdir)/$$p; \ + done + rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h + +run-cgen: + $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \ + "$(options)" $(extrafiles) + touch stamp-${prefix} +.PHONY: run-cgen + +# For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) + @true +stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst + +$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) + @true +stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= + +$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) + @true +stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + +$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) + @true +stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + +ia64-gen: ia64-gen.o + $(LINK) ia64-gen.o $(LIBIBERTY) + +ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ + ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h + +ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl + here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c + +s390-mkopc: s390-mkopc.c + $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c + +s390-opc.tab: s390-mkopc s390-opc.txt + ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab + +sh-dis.lo: sh-dis.c + $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $< + +Makefile: $(BFDDIR)/configure.in + +# This dependency stuff is copied from BFD. + +DEP: dep.sed $(CFILES) $(HFILES) config.h + rm -f DEP1 + $(MAKE) MKDEP="$(MKDEP)" DEP1 + sed -f dep.sed < DEP1 > DEPA + echo '# IF YOU PUT ANYTHING HERE IT WILL GO AWAY' >> DEPA + if grep ' /' DEPA > /dev/null 2> /dev/null; then \ + echo 'make DEP failed!'; exit 1; \ + else \ + mv -f DEPA $@; \ + fi + +DEP1: $(CFILES) + echo '# DO NOT DELETE THIS LINE -- mkdep uses it.' > DEP2 + echo '# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.' >> DEP2 + $(MKDEP) $(INCLUDES) $(CFLAGS) $? >> DEP2 + mv -f DEP2 $@ + +dep.sed: dep-in.sed config.status + sed <$(srcdir)/dep-in.sed >dep.sed \ + -e 's!@BFD_H@!$(BFD_H)!' \ + -e 's!@INCDIR@!$(INCDIR)!' \ + -e 's!@BFDDIR@!$(BFDDIR)!' \ + -e 's!@SRCDIR@!$(srcdir)!' \ + -e 's!@TOPDIR@!'`echo $(srcdir) | sed -e s,/opcodes$$,,`'!' + +dep: DEP + sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < Makefile > tmp-Makefile + cat DEP >> tmp-Makefile + $(srcdir)/../move-if-change tmp-Makefile Makefile + +dep-in: DEP + sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.in > tmp-Makefile.in + cat DEP >> tmp-Makefile.in + $(srcdir)/../move-if-change tmp-Makefile.in $(srcdir)/Makefile.in + +dep-am: DEP + sed -e '/^..DO NOT DELETE THIS LINE/,$$d' < $(srcdir)/Makefile.am > tmp-Makefile.am + cat DEP >> tmp-Makefile.am + $(srcdir)/../move-if-change tmp-Makefile.am $(srcdir)/Makefile.am + +.PHONY: dep dep-in dep-am + +# What appears below is generated by a hacked mkdep using gcc -MM. + +# DO NOT DELETE THIS LINE -- mkdep uses it. +# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. +a29k-dis.lo: a29k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/a29k.h +alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h +alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h +arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ + $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h +arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/arc.h +arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h +arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ + $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ + opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ + $(INCDIR)/elf/reloc-macros.h +avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ + $(INCDIR)/opcode/avr.h +cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h +cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h +cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h +cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h +cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h +d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d10v.h +d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/d30v.h +dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/dlx.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h +disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ + fr30-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ + fr30-opc.h opintl.h $(INCDIR)/libiberty.h +fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ + $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h +fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ + $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h +fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ + fr30-opc.h $(INCDIR)/libiberty.h +h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h +hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(BFDDIR)/libhppa.h \ + $(INCDIR)/opcode/hppa.h +i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/i370.h +i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/i370.h +i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + opintl.h +i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h +i960-dis.lo: i960-dis.c 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pdp11-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/pdp11.h +pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h +pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/pj.h +ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/ppc.h +ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/ppc.h opintl.h +s390-mkopc.lo: s390-mkopc.c +s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \ + s390-opc.tab +s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \ + config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/s390.h +sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h +sh64-opc.lo: sh64-opc.c sh64-opc.h +sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h +sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/sparc.h +tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h +tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ + $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h +tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h +tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/tic80.h +v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h opintl.h +v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/v850.h opintl.h +vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h +w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h +xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h +xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h +z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h +z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h +# IF YOU PUT ANYTHING HERE IT WILL GO AWAY + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/opcodes/a29k-dis.c b/opcodes/a29k-dis.c new file mode 100644 index 0000000..0e937ba --- /dev/null +++ b/opcodes/a29k-dis.c @@ -0,0 +1,367 @@ +/* Instruction printing code for the AMD 29000 + Copyright 1990, 1993, 1994, 1995, 1998, 2000, 2001 + Free Software Foundation, Inc. + Contributed by Cygnus Support. Written by Jim Kingdon. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/a29k.h" + +static void print_general PARAMS ((int, struct disassemble_info *)); +static void print_special PARAMS ((unsigned int, struct disassemble_info *)); +static int is_delayed_branch PARAMS ((int)); +static void find_bytes_little + PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *, + unsigned char *)); +static void find_bytes_big + PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *, + unsigned char *)); +static int print_insn PARAMS ((bfd_vma, struct disassemble_info *)); + + +/* Print a symbolic representation of a general-purpose + register number NUM on STREAM. + NUM is a number as found in the instruction, not as found in + debugging symbols; it must be in the range 0-255. */ +static void +print_general (num, info) + int num; + struct disassemble_info *info; +{ + if (num < 128) + (*info->fprintf_func) (info->stream, "gr%d", num); + else + (*info->fprintf_func) (info->stream, "lr%d", num - 128); +} + +/* Like print_general but a special-purpose register. + + The mnemonics used by the AMD assembler are not quite the same + as the ones in the User's Manual. We use the ones that the + assembler uses. */ +static void +print_special (num, info) + unsigned int num; + struct disassemble_info *info; +{ + /* Register names of registers 0-SPEC0_NUM-1. */ + static char *spec0_names[] = { + "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", + "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1", + "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc", + "cir", "cdr" + }; +#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0])) + + /* Register names of registers 128-128+SPEC128_NUM-1. */ + static char *spec128_names[] = { + "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr" + }; +#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0])) + + /* Register names of registers 160-160+SPEC160_NUM-1. */ + static char *spec160_names[] = { + "fpe", "inte", "fps", "sr163", "exop" + }; +#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0])) + + if (num < SPEC0_NUM) + (*info->fprintf_func) (info->stream, spec0_names[num]); + else if (num >= 128 && num < 128 + SPEC128_NUM) + (*info->fprintf_func) (info->stream, spec128_names[num-128]); + else if (num >= 160 && num < 160 + SPEC160_NUM) + (*info->fprintf_func) (info->stream, spec160_names[num-160]); + else + (*info->fprintf_func) (info->stream, "sr%d", num); +} + +/* Is an instruction with OPCODE a delayed branch? */ +static int +is_delayed_branch (opcode) + int opcode; +{ + return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1 + || opcode == 0xa4 || opcode == 0xa5 + || opcode == 0xb4 || opcode == 0xb5 + || opcode == 0xc4 || opcode == 0xc0 + || opcode == 0xac || opcode == 0xad + || opcode == 0xcc); +} + +/* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}. */ +static void +find_bytes_big (insn, insn0, insn8, insn16, insn24) + char *insn; + unsigned char *insn0; + unsigned char *insn8; + unsigned char *insn16; + unsigned char *insn24; +{ + *insn24 = insn[0]; + *insn16 = insn[1]; + *insn8 = insn[2]; + *insn0 = insn[3]; +} + +static void +find_bytes_little (insn, insn0, insn8, insn16, insn24) + char *insn; + unsigned char *insn0; + unsigned char *insn8; + unsigned char *insn16; + unsigned char *insn24; +{ + *insn24 = insn[3]; + *insn16 = insn[2]; + *insn8 = insn[1]; + *insn0 = insn[0]; +} + +typedef void (*find_byte_func_type) + PARAMS ((char *, unsigned char *, unsigned char *, + unsigned char *, unsigned char *)); + +/* Print one instruction from MEMADDR on INFO->STREAM. + Return the size of the instruction (always 4 on a29k). */ + +static int +print_insn (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + /* The raw instruction. */ + char insn[4]; + + /* The four bytes of the instruction. */ + unsigned char insn24, insn16, insn8, insn0; + + find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data; + + struct a29k_opcode CONST * opcode; + + { + int status = + (*info->read_memory_func) (memaddr, (bfd_byte *) &insn[0], 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + (*find_byte_func) (insn, &insn0, &insn8, &insn16, &insn24); + + printf ("%02x%02x%02x%02x ", insn24, insn16, insn8, insn0); + + /* Handle the nop (aseq 0x40,gr1,gr1) specially */ + if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) { + (*info->fprintf_func) (info->stream,"nop"); + return 4; + } + + /* The opcode is always in insn24. */ + for (opcode = &a29k_opcodes[0]; + opcode < &a29k_opcodes[num_opcodes]; + ++opcode) + { + if (((unsigned long) insn24 << 24) == opcode->opcode) + { + char *s; + + (*info->fprintf_func) (info->stream, "%s ", opcode->name); + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case 'a': + print_general (insn8, info); + break; + + case 'b': + print_general (insn0, info); + break; + + case 'c': + print_general (insn16, info); + break; + + case 'i': + (*info->fprintf_func) (info->stream, "%d", insn0); + break; + + case 'x': + (*info->fprintf_func) (info->stream, "0x%x", (insn16 << 8) + insn0); + break; + + case 'h': + /* This used to be %x for binutils. */ + (*info->fprintf_func) (info->stream, "0x%x", + (insn16 << 24) + (insn0 << 16)); + break; + + case 'X': + (*info->fprintf_func) (info->stream, "%d", + ((insn16 << 8) + insn0) | 0xffff0000); + break; + + case 'P': + /* This output looks just like absolute addressing, but + maybe that's OK (it's what the GDB m68k and EBMON + a29k disassemblers do). */ + /* All the shifting is to sign-extend it. p*/ + (*info->print_address_func) + (memaddr + + (((int)((insn16 << 10) + (insn0 << 2)) << 14) >> 14), + info); + break; + + case 'A': + (*info->print_address_func) + ((insn16 << 10) + (insn0 << 2), info); + break; + + case 'e': + (*info->fprintf_func) (info->stream, "%d", insn16 >> 7); + break; + + case 'n': + (*info->fprintf_func) (info->stream, "0x%x", insn16 & 0x7f); + break; + + case 'v': + (*info->fprintf_func) (info->stream, "0x%x", insn16); + break; + + case 's': + print_special (insn8, info); + break; + + case 'u': + (*info->fprintf_func) (info->stream, "%d", insn0 >> 7); + break; + + case 'r': + (*info->fprintf_func) (info->stream, "%d", (insn0 >> 4) & 7); + break; + + case 'I': + if ((insn16 & 3) != 0) + (*info->fprintf_func) (info->stream, "%d", insn16 & 3); + break; + + case 'd': + (*info->fprintf_func) (info->stream, "%d", (insn0 >> 2) & 3); + break; + + case 'f': + (*info->fprintf_func) (info->stream, "%d", insn0 & 3); + break; + + case 'F': + (*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15); + break; + + case 'C': + (*info->fprintf_func) (info->stream, "%d", insn16 & 3); + break; + + default: + (*info->fprintf_func) (info->stream, "%c", *s); + } + } + + /* Now we look for a const,consth pair of instructions, + in which case we try to print the symbolic address. */ + if (insn24 == 2) /* consth */ + { + int errcode; + char prev_insn[4]; + unsigned char prev_insn0, prev_insn8, prev_insn16, prev_insn24; + + errcode = (*info->read_memory_func) (memaddr - 4, + (bfd_byte *) &prev_insn[0], + 4, + info); + if (errcode == 0) + { + /* If it is a delayed branch, we need to look at the + instruction before the delayed brach to handle + things like + + const _foo + call _printf + consth _foo + */ + (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8, + &prev_insn16, &prev_insn24); + if (is_delayed_branch (prev_insn24)) + { + errcode = (*info->read_memory_func) + (memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info); + (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8, + &prev_insn16, &prev_insn24); + } + } + + /* If there was a problem reading memory, then assume + the previous instruction was not const. */ + if (errcode == 0) + { + /* Is it const to the same register? */ + if (prev_insn24 == 3 + && prev_insn8 == insn8) + { + (*info->fprintf_func) (info->stream, "\t; "); + (*info->print_address_func) + (((insn16 << 24) + (insn0 << 16) + + (prev_insn16 << 8) + (prev_insn0)), + info); + } + } + } + + return 4; + } + } + /* This used to be %8x for binutils. */ + (*info->fprintf_func) + (info->stream, ".word 0x%08x", + (insn24 << 24) + (insn16 << 16) + (insn8 << 8) + insn0); + return 4; +} + +/* Disassemble an big-endian a29k instruction. */ +int +print_insn_big_a29k (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + info->private_data = (PTR) find_bytes_big; + return print_insn (memaddr, info); +} + +/* Disassemble a little-endian a29k instruction. */ +int +print_insn_little_a29k (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + info->private_data = (PTR) find_bytes_little; + return print_insn (memaddr, info); +} diff --git a/opcodes/acinclude.m4 b/opcodes/acinclude.m4 new file mode 100644 index 0000000..3a47b1b --- /dev/null +++ b/opcodes/acinclude.m4 @@ -0,0 +1,24 @@ +sinclude(../bfd/acinclude.m4) + +dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4 +dnl The lines below arrange for aclocal not to bring libtool.m4 +dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake +dnl to add a definition of LIBTOOL to Makefile.in. +ifelse(yes,no,[ +AC_DEFUN([AM_PROG_LIBTOOL],) +AC_DEFUN([AM_DISABLE_SHARED],) +AC_SUBST(LIBTOOL) +]) + +dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4 +ifelse(yes,no,[ +AC_DEFUN([CY_WITH_NLS],) +AC_SUBST(INTLLIBS) +]) + +dnl AM_INSTALL_LIBBFD already included in bfd/acinclude.m4 +ifelse(yes,no,[ +AC_DEFUN([AM_INSTALL_LIBBFD],) +AC_SUBST(bfdlibdir) +AC_SUBST(bfdincludedir) +]) diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4 new file mode 100644 index 0000000..184bf36 --- /dev/null +++ b/opcodes/aclocal.m4 @@ -0,0 +1,185 @@ +dnl aclocal.m4 generated automatically by aclocal 1.4-p5 + +dnl Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. +dnl This file is free software; the Free Software Foundation +dnl gives unlimited permission to copy and/or distribute it, +dnl with or without modifications, as long as this notice is preserved. + +dnl This program is distributed in the hope that it will be useful, +dnl but WITHOUT ANY WARRANTY, to the extent permitted by law; without +dnl even the implied warranty of MERCHANTABILITY or FITNESS FOR A +dnl PARTICULAR PURPOSE. + +sinclude(../bfd/acinclude.m4) + +dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4 +dnl The lines below arrange for aclocal not to bring libtool.m4 +dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake +dnl to add a definition of LIBTOOL to Makefile.in. +ifelse(yes,no,[ +AC_DEFUN([AM_PROG_LIBTOOL],) +AC_DEFUN([AM_DISABLE_SHARED],) +AC_SUBST(LIBTOOL) +]) + +dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4 +ifelse(yes,no,[ +AC_DEFUN([CY_WITH_NLS],) +AC_SUBST(INTLLIBS) +]) + +dnl AM_INSTALL_LIBBFD already included in bfd/acinclude.m4 +ifelse(yes,no,[ +AC_DEFUN([AM_INSTALL_LIBBFD],) +AC_SUBST(bfdlibdir) +AC_SUBST(bfdincludedir) +]) + +# Do all the work for Automake. This macro actually does too much -- +# some checks are only needed if your package does certain things. +# But this isn't really a big deal. + +# serial 1 + +dnl Usage: +dnl AM_INIT_AUTOMAKE(package,version, [no-define]) + +AC_DEFUN([AM_INIT_AUTOMAKE], +[AC_REQUIRE([AC_PROG_INSTALL]) +PACKAGE=[$1] +AC_SUBST(PACKAGE) +VERSION=[$2] +AC_SUBST(VERSION) +dnl test to see if srcdir already configured +if test "`cd $srcdir && pwd`" != "`pwd`" && test -f $srcdir/config.status; then + AC_MSG_ERROR([source directory already configured; run "make distclean" there first]) +fi +ifelse([$3],, +AC_DEFINE_UNQUOTED(PACKAGE, "$PACKAGE", [Name of package]) +AC_DEFINE_UNQUOTED(VERSION, "$VERSION", [Version number of package])) +AC_REQUIRE([AM_SANITY_CHECK]) +AC_REQUIRE([AC_ARG_PROGRAM]) +dnl FIXME This is truly gross. +missing_dir=`cd $ac_aux_dir && pwd` +AM_MISSING_PROG(ACLOCAL, aclocal, $missing_dir) +AM_MISSING_PROG(AUTOCONF, autoconf, $missing_dir) +AM_MISSING_PROG(AUTOMAKE, automake, $missing_dir) +AM_MISSING_PROG(AUTOHEADER, autoheader, $missing_dir) +AM_MISSING_PROG(MAKEINFO, makeinfo, $missing_dir) +AC_REQUIRE([AC_PROG_MAKE_SET])]) + +# +# Check to make sure that the build environment is sane. +# + +AC_DEFUN([AM_SANITY_CHECK], +[AC_MSG_CHECKING([whether build environment is sane]) +# Just in case +sleep 1 +echo timestamp > conftestfile +# Do `set' in a subshell so we don't clobber the current shell's +# arguments. Must try -L first in case configure is actually a +# symlink; some systems play weird games with the mod time of symlinks +# (eg FreeBSD returns the mod time of the symlink's containing +# directory). +if ( + set X `ls -Lt $srcdir/configure conftestfile 2> /dev/null` + if test "[$]*" = "X"; then + # -L didn't work. + set X `ls -t $srcdir/configure conftestfile` + fi + if test "[$]*" != "X $srcdir/configure conftestfile" \ + && test "[$]*" != "X conftestfile $srcdir/configure"; then + + # If neither matched, then we have a broken ls. This can happen + # if, for instance, CONFIG_SHELL is bash and it inherits a + # broken ls alias from the environment. This has actually + # happened. Such a system could not be considered "sane". + AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken +alias in your environment]) + fi + + test "[$]2" = conftestfile + ) +then + # Ok. + : +else + AC_MSG_ERROR([newly created file is older than distributed files! +Check your system clock]) +fi +rm -f conftest* +AC_MSG_RESULT(yes)]) + +dnl AM_MISSING_PROG(NAME, PROGRAM, DIRECTORY) +dnl The program must properly implement --version. +AC_DEFUN([AM_MISSING_PROG], +[AC_MSG_CHECKING(for working $2) +# Run test in a subshell; some versions of sh will print an error if +# an executable is not found, even if stderr is redirected. +# Redirect stdin to placate older versions of autoconf. Sigh. +if ($2 --version) < /dev/null > /dev/null 2>&1; then + $1=$2 + AC_MSG_RESULT(found) +else + $1="$3/missing $2" + AC_MSG_RESULT(missing) +fi +AC_SUBST($1)]) + +# Like AC_CONFIG_HEADER, but automatically create stamp file. + +AC_DEFUN([AM_CONFIG_HEADER], +[AC_PREREQ([2.12]) +AC_CONFIG_HEADER([$1]) +dnl When config.status generates a header, we must update the stamp-h file. +dnl This file resides in the same directory as the config header +dnl that is generated. We must strip everything past the first ":", +dnl and everything past the last "/". +AC_OUTPUT_COMMANDS(changequote(<<,>>)dnl +ifelse(patsubst(<<$1>>, <<[^ ]>>, <<>>), <<>>, +<>CONFIG_HEADERS" || echo timestamp > patsubst(<<$1>>, <<^\([^:]*/\)?.*>>, <<\1>>)stamp-h<<>>dnl>>, +<>; do + case " <<$>>CONFIG_HEADERS " in + *" <<$>>am_file "*<<)>> + echo timestamp > `echo <<$>>am_file | sed -e 's%:.*%%' -e 's%[^/]*$%%'`stamp-h$am_indx + ;; + esac + am_indx=`expr "<<$>>am_indx" + 1` +done<<>>dnl>>) +changequote([,]))]) + +# Add --enable-maintainer-mode option to configure. +# From Jim Meyering + +# serial 1 + +AC_DEFUN([AM_MAINTAINER_MODE], +[AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles]) + dnl maintainer-mode is disabled by default + AC_ARG_ENABLE(maintainer-mode, +[ --enable-maintainer-mode enable make rules and dependencies not useful + (and sometimes confusing) to the casual installer], + USE_MAINTAINER_MODE=$enableval, + USE_MAINTAINER_MODE=no) + AC_MSG_RESULT($USE_MAINTAINER_MODE) + AM_CONDITIONAL(MAINTAINER_MODE, test $USE_MAINTAINER_MODE = yes) + MAINT=$MAINTAINER_MODE_TRUE + AC_SUBST(MAINT)dnl +] +) + +# Define a conditional. + +AC_DEFUN([AM_CONDITIONAL], +[AC_SUBST($1_TRUE) +AC_SUBST($1_FALSE) +if $2; then + $1_TRUE= + $1_FALSE='#' +else + $1_TRUE='#' + $1_FALSE= +fi]) + diff --git a/opcodes/alpha-dis.c b/opcodes/alpha-dis.c new file mode 100644 index 0000000..49b5f20 --- /dev/null +++ b/opcodes/alpha-dis.c @@ -0,0 +1,209 @@ +/* alpha-dis.c -- Disassemble Alpha AXP instructions + Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Richard Henderson , + patterned after the PPC opcode handling written by Ian Lance Taylor. + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/alpha.h" + +/* OSF register names. */ + +static const char * const osf_regnames[64] = { + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", + "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" +}; + +/* VMS register names. */ + +static const char * const vms_regnames[64] = { + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", + "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", + "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", + "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", + "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", + "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", + "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" +}; + +/* Disassemble Alpha instructions. */ + +int +print_insn_alpha (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; + const char * const * regnames; + const struct alpha_opcode *opcode, *opcode_end; + const unsigned char *opindex; + unsigned insn, op, isa_mask; + int need_comma; + + /* Initialize the majorop table the first time through */ + if (!opcode_index[0]) + { + opcode = alpha_opcodes; + opcode_end = opcode + alpha_num_opcodes; + + for (op = 0; op < AXP_NOPS; ++op) + { + opcode_index[op] = opcode; + while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) + ++opcode; + } + opcode_index[op] = opcode; + } + + if (info->flavour == bfd_target_evax_flavour) + regnames = vms_regnames; + else + regnames = osf_regnames; + + isa_mask = AXP_OPCODE_NOPAL; + switch (info->mach) + { + case bfd_mach_alpha_ev4: + isa_mask |= AXP_OPCODE_EV4; + break; + case bfd_mach_alpha_ev5: + isa_mask |= AXP_OPCODE_EV5; + break; + case bfd_mach_alpha_ev6: + isa_mask |= AXP_OPCODE_EV6; + break; + } + + /* Read the insn into a host word */ + { + bfd_byte buffer[4]; + int status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getl32 (buffer); + } + + /* Get the major opcode of the instruction. */ + op = AXP_OP (insn); + + /* Find the first match in the opcode table. */ + opcode_end = opcode_index[op + 1]; + for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) + { + if ((insn ^ opcode->opcode) & opcode->mask) + continue; + + if (!(opcode->flags & isa_mask)) + continue; + + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + { + int invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct alpha_operand *operand = alpha_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, &invalid); + } + if (invalid) + continue; + } + + /* The instruction is valid. */ + goto found; + } + + /* No instruction found */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + + return 4; + +found: + (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + + /* Now extract and print the operands. */ + need_comma = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct alpha_operand *operand = alpha_operands + *opindex; + int value; + + /* Operands that are marked FAKE are simply ignored. We + already made sure that the extract function considered + the instruction to be valid. */ + if ((operand->flags & AXP_OPERAND_FAKE) != 0) + continue; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, (int *) NULL); + else + { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if (operand->flags & AXP_OPERAND_SIGNED) + { + int signbit = 1 << (operand->bits - 1); + value = (value ^ signbit) - signbit; + } + } + + if (need_comma && + ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) + != AXP_OPERAND_PARENS)) + { + (*info->fprintf_func) (info->stream, ","); + } + if (operand->flags & AXP_OPERAND_PARENS) + (*info->fprintf_func) (info->stream, "("); + + /* Print the operand as directed by the flags. */ + if (operand->flags & AXP_OPERAND_IR) + (*info->fprintf_func) (info->stream, "%s", regnames[value]); + else if (operand->flags & AXP_OPERAND_FPR) + (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); + else if (operand->flags & AXP_OPERAND_RELATIVE) + (*info->print_address_func) (memaddr + 4 + value, info); + else if (operand->flags & AXP_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%d", value); + else + (*info->fprintf_func) (info->stream, "%#x", value); + + if (operand->flags & AXP_OPERAND_PARENS) + (*info->fprintf_func) (info->stream, ")"); + need_comma = 1; + } + + return 4; +} diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c new file mode 100644 index 0000000..6cf7d4c --- /dev/null +++ b/opcodes/alpha-opc.c @@ -0,0 +1,1554 @@ +/* alpha-opc.c -- Alpha AXP opcode list + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by Richard Henderson , + patterned after the PPC opcode handling written by Ian Lance Taylor. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/alpha.h" +#include "bfd.h" +#include "opintl.h" + +/* This file holds the Alpha AXP opcode table. The opcode table includes + almost all of the extended instruction mnemonics. This permits the + disassembler to use them, and simplifies the assembler logic, at the + cost of increasing the table size. The table is strictly constant + data, so the compiler should be able to put it in the text segment. + + This file also holds the operand table. All knowledge about inserting + and extracting operands from instructions is kept in this file. + + The information for the base instruction set was compiled from the + _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, + version 2. + + The information for the post-ev5 architecture extensions BWX, CIX and + MAX came from version 3 of this same document, which is also available + on-line at http://ftp.digital.com/pub/Digital/info/semiconductor + /literature/alphahb2.pdf + + The information for the EV4 PALcode instructions was compiled from + _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware + Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary + revision dated June 1994. + + The information for the EV5 PALcode instructions was compiled from + _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital + Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ + +/* Local insertion and extraction functions */ + +static unsigned insert_rba PARAMS((unsigned, int, const char **)); +static unsigned insert_rca PARAMS((unsigned, int, const char **)); +static unsigned insert_za PARAMS((unsigned, int, const char **)); +static unsigned insert_zb PARAMS((unsigned, int, const char **)); +static unsigned insert_zc PARAMS((unsigned, int, const char **)); +static unsigned insert_bdisp PARAMS((unsigned, int, const char **)); +static unsigned insert_jhint PARAMS((unsigned, int, const char **)); +static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **)); + +static int extract_rba PARAMS((unsigned, int *)); +static int extract_rca PARAMS((unsigned, int *)); +static int extract_za PARAMS((unsigned, int *)); +static int extract_zb PARAMS((unsigned, int *)); +static int extract_zc PARAMS((unsigned, int *)); +static int extract_bdisp PARAMS((unsigned, int *)); +static int extract_jhint PARAMS((unsigned, int *)); +static int extract_ev6hwjhint PARAMS((unsigned, int *)); + + +/* The operands table */ + +const struct alpha_operand alpha_operands[] = +{ + /* The fields are bits, shift, insert, extract, flags */ + /* The zero index is used to indicate end-of-list */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, 0 }, + + /* The plain integer register fields */ +#define RA (UNUSED + 1) + { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, +#define RB (RA + 1) + { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, +#define RC (RB + 1) + { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, + + /* The plain fp register fields */ +#define FA (RC + 1) + { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, +#define FB (FA + 1) + { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, +#define FC (FB + 1) + { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, + + /* The integer registers when they are ZERO */ +#define ZA (FC + 1) + { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, +#define ZB (ZA + 1) + { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, +#define ZC (ZB + 1) + { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, + + /* The RB field when it needs parentheses */ +#define PRB (ZC + 1) + { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, + + /* The RB field when it needs parentheses _and_ a preceding comma */ +#define CPRB (PRB + 1) + { 5, 16, 0, + AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, + + /* The RB field when it must be the same as the RA field */ +#define RBA (CPRB + 1) + { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, + + /* The RC field when it must be the same as the RB field */ +#define RCA (RBA + 1) + { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, + + /* The RC field when it can *default* to RA */ +#define DRC1 (RCA + 1) + { 5, 0, 0, + AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, + + /* The RC field when it can *default* to RB */ +#define DRC2 (DRC1 + 1) + { 5, 0, 0, + AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, + + /* The FC field when it can *default* to RA */ +#define DFC1 (DRC2 + 1) + { 5, 0, 0, + AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, + + /* The FC field when it can *default* to RB */ +#define DFC2 (DFC1 + 1) + { 5, 0, 0, + AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, + + /* The unsigned 8-bit literal of Operate format insns */ +#define LIT (DFC2 + 1) + { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The signed 16-bit displacement of Memory format insns. From here + we can't tell what relocation should be used, so don't use a default. */ +#define MDISP (LIT + 1) + { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, + + /* The signed "23-bit" aligned displacement of Branch format insns */ +#define BDISP (MDISP + 1) + { 21, 0, BFD_RELOC_23_PCREL_S2, + AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, + + /* The 26-bit PALcode function */ +#define PALFN (BDISP + 1) + { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ +#define JMPHINT (PALFN + 1) + { 14, 0, BFD_RELOC_ALPHA_HINT, + AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, + insert_jhint, extract_jhint }, + + /* The optional hint to RET/JSR_COROUTINE */ +#define RETHINT (JMPHINT + 1) + { 14, 0, -RETHINT, + AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, + + /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */ +#define EV4HWDISP (RETHINT + 1) +#define EV6HWDISP (EV4HWDISP) + { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, + + /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ +#define EV4HWINDEX (EV4HWDISP + 1) + { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns + that occur in DEC PALcode. */ +#define EV4EXTHWINDEX (EV4HWINDEX + 1) + { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ +#define EV5HWDISP (EV4EXTHWINDEX + 1) + { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, + + /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ +#define EV5HWINDEX (EV5HWDISP + 1) + { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 16-bit combined index/scoreboard mask for the ev6 + hw_m[ft]pr (pal19/pal1d) insns */ +#define EV6HWINDEX (EV5HWINDEX + 1) + { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */ +#define EV6HWJMPHINT (EV6HWINDEX+ 1) + { 8, 0, -EV6HWJMPHINT, + AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, + insert_ev6hwjhint, extract_ev6hwjhint } +}; + +const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); + +/* The RB field when it is the same as the RA field in the same insn. + This operand is marked fake. The insertion function just copies + the RA field into the RB field, and the extraction function just + checks that the fields are the same. */ + +/*ARGSUSED*/ +static unsigned +insert_rba(insn, value, errmsg) + unsigned insn; + int value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (((insn >> 21) & 0x1f) << 16); +} + +static int +extract_rba(insn, invalid) + unsigned insn; + int *invalid; +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + *invalid = 1; + return 0; +} + + +/* The same for the RC field */ + +/*ARGSUSED*/ +static unsigned +insert_rca(insn, value, errmsg) + unsigned insn; + int value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | ((insn >> 21) & 0x1f); +} + +static int +extract_rca(insn, invalid) + unsigned insn; + int *invalid; +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != (insn & 0x1f)) + *invalid = 1; + return 0; +} + + +/* Fake arguments in which the registers must be set to ZERO */ + +/*ARGSUSED*/ +static unsigned +insert_za(insn, value, errmsg) + unsigned insn; + int value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (31 << 21); +} + +static int +extract_za(insn, invalid) + unsigned insn; + int *invalid; +{ + if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) + *invalid = 1; + return 0; +} + +/*ARGSUSED*/ +static unsigned +insert_zb(insn, value, errmsg) + unsigned insn; + int value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (31 << 16); +} + +static int +extract_zb(insn, invalid) + unsigned insn; + int *invalid; +{ + if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) + *invalid = 1; + return 0; +} + +/*ARGSUSED*/ +static unsigned +insert_zc(insn, value, errmsg) + unsigned insn; + int value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | 31; +} + +static int +extract_zc(insn, invalid) + unsigned insn; + int *invalid; +{ + if (invalid != (int *) NULL && (insn & 0x1f) != 31) + *invalid = 1; + return 0; +} + + +/* The displacement field of a Branch format insn. */ + +static unsigned +insert_bdisp(insn, value, errmsg) + unsigned insn; + int value; + const char **errmsg; +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("branch operand unaligned"); + return insn | ((value / 4) & 0x1FFFFF); +} + +/*ARGSUSED*/ +static int +extract_bdisp(insn, invalid) + unsigned insn; + int *invalid ATTRIBUTE_UNUSED; +{ + return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); +} + + +/* The hint field of a JMP/JSR insn. */ + +static unsigned +insert_jhint(insn, value, errmsg) + unsigned insn; + int value; + const char **errmsg; +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("jump hint unaligned"); + return insn | ((value / 4) & 0x3FFF); +} + +/*ARGSUSED*/ +static int +extract_jhint(insn, invalid) + unsigned insn; + int *invalid ATTRIBUTE_UNUSED; +{ + return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); +} + +/* The hint field of an EV6 HW_JMP/JSR insn. */ + +static unsigned +insert_ev6hwjhint(insn, value, errmsg) + unsigned insn; + int value; + const char **errmsg; +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("jump hint unaligned"); + return insn | ((value / 4) & 0x1FFF); +} + +/*ARGSUSED*/ +static int +extract_ev6hwjhint(insn, invalid) + unsigned insn; + int *invalid ATTRIBUTE_UNUSED; +{ + return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); +} + + +/* Macros used to form opcodes */ + +/* The main opcode */ +#define OP(x) (((x) & 0x3F) << 26) +#define OP_MASK 0xFC000000 + +/* Branch format instructions */ +#define BRA_(oo) OP(oo) +#define BRA_MASK OP_MASK +#define BRA(oo) BRA_(oo), BRA_MASK + +/* Floating point format instructions */ +#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) +#define FP_MASK (OP_MASK | 0xFFE0) +#define FP(oo,fff) FP_(oo,fff), FP_MASK + +/* Memory format instructions */ +#define MEM_(oo) OP(oo) +#define MEM_MASK OP_MASK +#define MEM(oo) MEM_(oo), MEM_MASK + +/* Memory/Func Code format instructions */ +#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) +#define MFC_MASK (OP_MASK | 0xFFFF) +#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK + +/* Memory/Branch format instructions */ +#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) +#define MBR_MASK (OP_MASK | 0xC000) +#define MBR(oo,h) MBR_(oo,h), MBR_MASK + +/* Operate format instructions. The OPRL variant specifies a + literal second argument. */ +#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) +#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) +#define OPR_MASK (OP_MASK | 0x1FE0) +#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK +#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK + +/* Generic PALcode format instructions */ +#define PCD_(oo) OP(oo) +#define PCD_MASK OP_MASK +#define PCD(oo) PCD_(oo), PCD_MASK + +/* Specific PALcode instructions */ +#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) +#define SPCD_MASK 0xFFFFFFFF +#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK + +/* Hardware memory (hw_{ld,st}) instructions */ +#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) +#define EV4HWMEM_MASK (OP_MASK | 0xF000) +#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK + +#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) +#define EV5HWMEM_MASK (OP_MASK | 0xF800) +#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK + +#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) +#define EV6HWMEM_MASK (OP_MASK | 0xF000) +#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK + +#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) +#define EV6HWMBR_MASK (OP_MASK | 0xE000) +#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK + +/* Abbreviations for instruction subsets. */ +#define BASE AXP_OPCODE_BASE +#define EV4 AXP_OPCODE_EV4 +#define EV5 AXP_OPCODE_EV5 +#define EV6 AXP_OPCODE_EV6 +#define BWX AXP_OPCODE_BWX +#define CIX AXP_OPCODE_CIX +#define MAX AXP_OPCODE_MAX + +/* Common combinations of arguments */ +#define ARG_NONE { 0 } +#define ARG_BRA { RA, BDISP } +#define ARG_FBRA { FA, BDISP } +#define ARG_FP { FA, FB, DFC1 } +#define ARG_FPZ1 { ZA, FB, DFC1 } +#define ARG_MEM { RA, MDISP, PRB } +#define ARG_FMEM { FA, MDISP, PRB } +#define ARG_OPR { RA, RB, DRC1 } +#define ARG_OPRL { RA, LIT, DRC1 } +#define ARG_OPRZ1 { ZA, RB, DRC1 } +#define ARG_OPRLZ1 { ZA, LIT, RC } +#define ARG_PCD { PALFN } +#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } +#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } +#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } +#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK { OPERANDS } + + NAME is the name of the instruction. + + OPCODE is the instruction opcode. + + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + + OPERANDS is the list of operands. + + The preceding macros merge the text of the OPCODE and MASK fields. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. + + Otherwise, it is sorted by major opcode and minor function code. + + There are three classes of not-really-instructions in this table: + + ALIAS is another name for another instruction. Some of + these come from the Architecture Handbook, some + come from the original gas opcode tables. In all + cases, the functionality of the opcode is unchanged. + + PSEUDO a stylized code form endorsed by Chapter A.4 of the + Architecture Handbook. + + EXTRA a stylized code form found in the original gas tables. + + And two annotations: + + EV56 BUT opcodes that are officially introduced as of the ev56, + but with defined results on previous implementations. + + EV56 UNA opcodes that were introduced as of the ev56 with + presumably undefined results on previous implementations + that were not assigned to a particular extension. +*/ + +const struct alpha_opcode alpha_opcodes[] = { + { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, + { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, + { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, + { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, + { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, + { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, + { "call_pal", PCD(0x00), BASE, ARG_PCD }, + { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ + + { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ + { "lda", MEM(0x08), BASE, ARG_MEM }, + { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ + { "ldah", MEM(0x09), BASE, ARG_MEM }, + { "ldbu", MEM(0x0A), BWX, ARG_MEM }, + { "unop", MEM_(0x0B) | (30 << 16), + MEM_MASK, BASE, { ZA } }, /* pseudo */ + { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, + { "ldwu", MEM(0x0C), BWX, ARG_MEM }, + { "stw", MEM(0x0D), BWX, ARG_MEM }, + { "stb", MEM(0x0E), BWX, ARG_MEM }, + { "stq_u", MEM(0x0F), BASE, ARG_MEM }, + + { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ + { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, + { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, + { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, + { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, + { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, + { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, + { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, + { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, + { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, + { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, + { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, + { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, + { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, + { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, + { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, + { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, + { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, + { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, + { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, + { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, + { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, + { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, + { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, + { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, + { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, + { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, + { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, + { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, + { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, + { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, + { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, + { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, + { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, + { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, + { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, + { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, + { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, + { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, + { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, + { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, + { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, + { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, + { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, + { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, + + { "and", OPR(0x11,0x00), BASE, ARG_OPR }, + { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, + { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ + { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ + { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, + { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, + { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, + { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, + { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, + { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, + { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ + { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ + { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ + { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ + { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ + { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ + { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ + { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, + { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, + { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, + { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, + { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, + { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, + { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ + { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, + { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, + { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, + { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, + { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, + { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, + { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, + { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, + { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, + { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, + { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ + { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ + { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ + { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ + { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, + { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, + { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, + { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, + { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), + 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ + + { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, + { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, + { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, + { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, + { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, + { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, + { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, + { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, + { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, + { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, + { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, + { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, + { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, + { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, + { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, + { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, + { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, + { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, + { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, + { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, + { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, + { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, + { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, + { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, + { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, + { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, + { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, + { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, + { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, + { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, + { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, + { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, + { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, + { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, + { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, + { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, + { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, + { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, + { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, + { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, + { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, + { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, + { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, + { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, + { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, + { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, + { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, + { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, + { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, + { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, + { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, + { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, + + { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, + { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, + { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, + { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, + { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, + { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, + { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, + { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, + { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, + { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, + + { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, + { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, + { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, + { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, + { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, + { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, + { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, + { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, + { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, + { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, + { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, + { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, + { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, + { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, + { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, + { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, + { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, + { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, + { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, + { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, + { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, + { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, + { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, + { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, + { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, + { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, + { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, + { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, + { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, + { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, + { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, + { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, + { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, + { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, + { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, + { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, + { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, + { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, + { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, + { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, + { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, + { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, + { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, + { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, + { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, + { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, + { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, + { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, + { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, + { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, + { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, + + { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, + { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, + { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, + { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, + { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, + { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, + { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, + { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, + { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, + { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, + { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, + { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, + { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, + { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, + { "addf", FP(0x15,0x080), BASE, ARG_FP }, + { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ + { "subf", FP(0x15,0x081), BASE, ARG_FP }, + { "mulf", FP(0x15,0x082), BASE, ARG_FP }, + { "divf", FP(0x15,0x083), BASE, ARG_FP }, + { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, + { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, + { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, + { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, + { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, + { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, + { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, + { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, + { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, + { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, + { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, + { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, + { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, + { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, + { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, + { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, + { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, + { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, + { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, + { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, + { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, + { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, + { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, + { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, + { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, + { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, + { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, + { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, + { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, + { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, + { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, + { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, + { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, + { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, + { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, + { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, + { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, + { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, + { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, + { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, + { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, + { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, + { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, + { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, + { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, + { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, + { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, + { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, + { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, + { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, + { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ + { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, + { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, + { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, + { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, + { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, + { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, + { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, + { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, + { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, + { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, + { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, + { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, + { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, + { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, + { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, + { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, + { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, + { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, + { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, + { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, + { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, + { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, + { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, + { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, + { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, + { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, + { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, + { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, + { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, + { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, + { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, + { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, + { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, + { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, + { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, + { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, + { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, + { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, + + { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, + { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, + { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, + { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, + { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, + { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, + { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, + { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, + { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, + { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, + { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, + { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, + { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, + { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, + { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, + { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, + { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, + { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, + { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, + { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, + { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, + { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, + { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, + { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, + { "adds", FP(0x16,0x080), BASE, ARG_FP }, + { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ + { "subs", FP(0x16,0x081), BASE, ARG_FP }, + { "muls", FP(0x16,0x082), BASE, ARG_FP }, + { "divs", FP(0x16,0x083), BASE, ARG_FP }, + { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, + { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, + { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, + { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, + { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, + { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, + { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, + { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, + { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, + { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, + { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, + { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, + { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, + { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, + { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, + { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, + { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, + { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, + { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, + { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, + { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, + { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, + { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, + { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, + { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, + { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, + { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, + { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, + { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, + { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, + { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, + { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, + { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, + { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, + { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, + { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, + { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, + { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, + { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, + { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, + { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, + { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, + { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, + { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, + { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, + { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, + { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, + { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, + { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, + { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, + { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, + { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, + { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, + { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, + { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, + { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, + { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, + { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, + { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, + { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, + { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, + { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, + { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, + { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, + { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, + { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, + { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, + { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, + { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, + { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, + { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, + { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, + { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, + { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, + { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, + { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, + { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, + { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, + { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, + { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, + { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, + { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, + { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, + { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, + { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, + { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, + { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ + { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, + { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, + { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, + { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, + { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, + { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, + { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, + { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, + { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, + { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, + { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, + { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, + { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, + { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, + { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, + { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, + { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, + { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, + { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, + { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, + { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, + { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, + { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, + { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, + { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, + { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, + { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, + { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, + { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, + { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, + { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, + { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, + { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, + { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, + { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, + { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, + { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, + { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, + { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, + { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, + { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, + { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, + { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, + { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, + { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, + { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, + { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, + { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, + { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, + { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ + { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, + { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, + { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, + { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, + { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, + { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, + { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, + { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, + { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, + { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, + { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, + { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, + { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, + { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, + { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, + { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, + { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, + { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, + { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, + { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, + { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, + { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, + { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, + + { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, + { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ + { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ + { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ + { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ + { "cpys", FP(0x17,0x020), BASE, ARG_FP }, + { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ + { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, + { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, + { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, + { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, + { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, + { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, + { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, + { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, + { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, + { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, + { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, + { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, + { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, + + { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, + { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ + { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, + { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, + { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, + { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, + { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, + { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, + { "rc", MFC(0x18,0xE000), BASE, { RA } }, + { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ + { "rs", MFC(0x18,0xF000), BASE, { RA } }, + { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ + { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ + + { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, + { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, + { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, + { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, + { "pal19", PCD(0x19), BASE, ARG_PCD }, + + { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ + BASE, { ZA, CPRB } }, + { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, + { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, + { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ + 0xFFFFFFFF, BASE, { 0 } }, + { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, + { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ + { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, + + { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, + { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, + { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, + { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, + { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, + { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, + { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, + { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, + { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, + { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, + { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, + { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, + { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, + { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, + { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, + { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, + { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, + { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, + { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, + { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, + { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, + { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, + { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, + { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, + { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, + { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, + { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, + { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, + { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, + { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, + { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, + { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, + { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, + { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, + { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, + { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, + { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, + { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, + { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, + { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, + { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, + { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, + { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, + { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, + { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, + { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, + { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, + { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, + { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, + { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, + { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, + { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, + { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, + { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, + { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, + { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, + { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, + { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, + { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, + { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, + { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, + { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, + { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, + { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, + { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, + { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, + { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, + { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, + { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, + { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, + { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, + { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, + { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, + { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, + { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, + { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, + { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, + { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, + { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, + { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, + { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, + { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, + { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, + { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, + { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, + { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, + { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, + { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, + { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, + { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, + { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, + { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, + { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, + { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, + { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, + { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, + { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, + { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, + { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, + { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, + { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, + { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, + { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, + { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, + { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, + { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, + { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, + { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, + { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, + { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, + { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, + { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, + { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, + { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, + { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, + { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, + { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, + { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, + { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, + { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, + { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, + { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, + { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, + { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, + { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, + { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, + { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, + { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, + { "pal1b", PCD(0x1B), BASE, ARG_PCD }, + + { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, + { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, + { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, + { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, + { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, + { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, + { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, + { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, + { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, + { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, + { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, + { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, + { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, + { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, + { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, + { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, + { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, + { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, + { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, + { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, + { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, + { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, + { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, + { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, + { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, + { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, + { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, + { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, + + { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, + { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, + { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, + { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, + { "pal1d", PCD(0x1D), BASE, ARG_PCD }, + + { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, + { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, + { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, + { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, + { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ + { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, + { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, + { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ + { "pal1e", PCD(0x1E), BASE, ARG_PCD }, + + { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, + { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, + { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ + { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, + { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, + { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, + { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, + { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, + { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, + { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, + { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, + { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, + { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, + { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, + { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, + { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, + { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, + { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, + { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, + { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, + { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, + { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, + { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, + { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, + { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, + { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, + { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, + { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, + { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, + { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, + { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ + { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, + { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, + { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, + { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, + { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, + { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, + { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, + { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, + { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, + { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, + { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, + { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, + { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, + { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, + { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, + { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, + { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, + { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, + { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, + { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, + { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, + { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, + { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, + { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, + { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, + { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, + { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, + { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, + { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, + { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, + { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, + { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, + { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, + { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, + { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, + { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, + { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, + { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, + { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, + { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, + { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, + { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, + { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, + { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, + { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, + { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, + { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, + { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, + { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, + { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, + { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, + { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, + { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, + { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, + { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, + { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, + { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, + { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, + { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, + { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, + { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, + { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, + { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, + { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, + { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, + { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, + { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, + { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, + { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, + { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, + { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, + { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, + { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, + { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, + { "pal1f", PCD(0x1F), BASE, ARG_PCD }, + + { "ldf", MEM(0x20), BASE, ARG_FMEM }, + { "ldg", MEM(0x21), BASE, ARG_FMEM }, + { "lds", MEM(0x22), BASE, ARG_FMEM }, + { "ldt", MEM(0x23), BASE, ARG_FMEM }, + { "stf", MEM(0x24), BASE, ARG_FMEM }, + { "stg", MEM(0x25), BASE, ARG_FMEM }, + { "sts", MEM(0x26), BASE, ARG_FMEM }, + { "stt", MEM(0x27), BASE, ARG_FMEM }, + + { "ldl", MEM(0x28), BASE, ARG_MEM }, + { "ldq", MEM(0x29), BASE, ARG_MEM }, + { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, + { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, + { "stl", MEM(0x2C), BASE, ARG_MEM }, + { "stq", MEM(0x2D), BASE, ARG_MEM }, + { "stl_c", MEM(0x2E), BASE, ARG_MEM }, + { "stq_c", MEM(0x2F), BASE, ARG_MEM }, + + { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ + { "br", BRA(0x30), BASE, ARG_BRA }, + { "fbeq", BRA(0x31), BASE, ARG_FBRA }, + { "fblt", BRA(0x32), BASE, ARG_FBRA }, + { "fble", BRA(0x33), BASE, ARG_FBRA }, + { "bsr", BRA(0x34), BASE, ARG_BRA }, + { "fbne", BRA(0x35), BASE, ARG_FBRA }, + { "fbge", BRA(0x36), BASE, ARG_FBRA }, + { "fbgt", BRA(0x37), BASE, ARG_FBRA }, + { "blbc", BRA(0x38), BASE, ARG_BRA }, + { "beq", BRA(0x39), BASE, ARG_BRA }, + { "blt", BRA(0x3A), BASE, ARG_BRA }, + { "ble", BRA(0x3B), BASE, ARG_BRA }, + { "blbs", BRA(0x3C), BASE, ARG_BRA }, + { "bne", BRA(0x3D), BASE, ARG_BRA }, + { "bge", BRA(0x3E), BASE, ARG_BRA }, + { "bgt", BRA(0x3F), BASE, ARG_BRA }, +}; + +const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c new file mode 100644 index 0000000..194a75a --- /dev/null +++ b/opcodes/arc-dis.c @@ -0,0 +1,1246 @@ +/* Instruction printing code for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "ansidecl.h" +#include "libiberty.h" +#include "dis-asm.h" +#include "opcode/arc.h" +#include "elf-bfd.h" +#include "elf/arc.h" +#include +#include "opintl.h" + +#include +#include "arc-dis.h" +#include "arc-ext.h" + +#ifndef dbg +#define dbg (0) +#endif + +#define BIT(word,n) ((word) & (1 << n)) +#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) +#define OPCODE(word) (BITS ((word), 27, 31)) +#define FIELDA(word) (BITS ((word), 21, 26)) +#define FIELDB(word) (BITS ((word), 15, 20)) +#define FIELDC(word) (BITS ((word), 9, 14)) + +/* FIELD D is signed in all of its uses, so we make sure argument is + treated as signed for bit shifting purposes: */ +#define FIELDD(word) (BITS (((signed int)word), 0, 8)) + +#define PUT_NEXT_WORD_IN(a) \ + do \ + { \ + if (is_limm == 1 && !NEXT_WORD (1)) \ + mwerror (state, _("Illegal limm reference in last instruction!\n")); \ + a = state->words[1]; \ + } \ + while (0) + +#define CHECK_FLAG_COND_NULLIFY() \ + do \ + { \ + if (is_shimm == 0) \ + { \ + flag = BIT (state->words[0], 8); \ + state->nullifyMode = BITS (state->words[0], 5, 6); \ + cond = BITS (state->words[0], 0, 4); \ + } \ + } \ + while (0) + +#define CHECK_COND() \ + do \ + { \ + if (is_shimm == 0) \ + cond = BITS (state->words[0], 0, 4); \ + } \ + while (0) + +#define CHECK_FIELD(field) \ + do \ + { \ + if (field == 62) \ + { \ + is_limm++; \ + field##isReg = 0; \ + PUT_NEXT_WORD_IN (field); \ + limm_value = field; \ + } \ + else if (field > 60) \ + { \ + field##isReg = 0; \ + is_shimm++; \ + flag = (field == 61); \ + field = FIELDD (state->words[0]); \ + } \ + } \ + while (0) + +#define CHECK_FIELD_A() \ + do \ + { \ + fieldA = FIELDA (state->words[0]); \ + if (fieldA > 60) \ + { \ + fieldAisReg = 0; \ + fieldA = 0; \ + } \ + } \ + while (0) + +#define CHECK_FIELD_B() \ + do \ + { \ + fieldB = FIELDB (state->words[0]); \ + CHECK_FIELD (fieldB); \ + } \ + while (0) + +#define CHECK_FIELD_C() \ + do \ + { \ + fieldC = FIELDC (state->words[0]); \ + CHECK_FIELD (fieldC); \ + } \ + while (0) + +#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) +#define IS_REG(x) (field##x##isReg) +#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") +#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") +#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") +#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") +#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") +#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") +#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") +#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ + (IS_REG (x) ? cb1"%r"ca1 : \ + usesAuxReg ? cb"%a"ca : \ + IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) +#define WRITE_FORMAT_RB() strcat (formatString, "]") +#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) +#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); + +#define NEXT_WORD(x) (offset += 4, state->words[x]) + +#define add_target(x) (state->targets[state->tcnt++] = (x)) + +static char comment_prefix[] = "\t; "; + +static const char *core_reg_name PARAMS ((struct arcDisState *, int)); +static const char *aux_reg_name PARAMS ((struct arcDisState *, int)); +static const char *cond_code_name PARAMS ((struct arcDisState *, int)); +static const char *instruction_name + PARAMS ((struct arcDisState *, int, int, int *)); +static void mwerror PARAMS ((struct arcDisState *, const char *)); +static const char *post_address PARAMS ((struct arcDisState *, int)); +static void write_comments_ + PARAMS ((struct arcDisState *, int, int, long int)); +static void write_instr_name_ + PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int)); +static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *)); +static const char *_coreRegName PARAMS ((void *, int)); +static int decodeInstr PARAMS ((bfd_vma, disassemble_info *)); + +static const char * +core_reg_name (state, val) + struct arcDisState * state; + int val; +{ + if (state->coreRegName) + return (*state->coreRegName)(state->_this, val); + return 0; +} + +static const char * +aux_reg_name (state, val) + struct arcDisState * state; + int val; +{ + if (state->auxRegName) + return (*state->auxRegName)(state->_this, val); + return 0; +} + +static const char * +cond_code_name (state, val) + struct arcDisState * state; + int val; +{ + if (state->condCodeName) + return (*state->condCodeName)(state->_this, val); + return 0; +} + +static const char * +instruction_name (state, op1, op2, flags) + struct arcDisState * state; + int op1; + int op2; + int * flags; +{ + if (state->instName) + return (*state->instName)(state->_this, op1, op2, flags); + return 0; +} + +static void +mwerror (state, msg) + struct arcDisState * state; + const char * msg; +{ + if (state->err != 0) + (*state->err)(state->_this, (msg)); +} + +static const char * +post_address (state, addr) + struct arcDisState * state; + int addr; +{ + static char id[3 * ARRAY_SIZE (state->addresses)]; + int j, i = state->acnt; + + if (i < ((int) ARRAY_SIZE (state->addresses))) + { + state->addresses[i] = addr; + ++state->acnt; + j = i*3; + id[j+0] = '@'; + id[j+1] = '0'+i; + id[j+2] = 0; + + return id + j; + } + return ""; +} + +static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *, + ...)); + +static void +my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, + ...)) +{ + char *bp; + const char *p; + int size, leading_zero, regMap[2]; + long auxNum; + + VA_OPEN (ap, format); + VA_FIXEDARG (ap, struct arcDisState *, state); + VA_FIXEDARG (ap, char *, buf); + VA_FIXEDARG (ap, const char *, format); + + bp = buf; + *bp = 0; + p = format; + auxNum = -1; + regMap[0] = 0; + regMap[1] = 0; + + while (1) + switch (*p++) + { + case 0: + goto DOCOMM; /* (return) */ + default: + *bp++ = p[-1]; + break; + case '%': + size = 0; + leading_zero = 0; + RETRY: ; + switch (*p++) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + /* size. */ + size = p[-1] - '0'; + if (size == 0) + leading_zero = 1; /* e.g. %08x */ + while (*p >= '0' && *p <= '9') + { + size = size * 10 + *p - '0'; + p++; + } + goto RETRY; + } +#define inc_bp() bp = bp + strlen (bp) + + case 'h': + { + unsigned u = va_arg (ap, int); + + /* Hex. We can change the format to 0x%08x in + one place, here, if we wish. + We add underscores for easy reading. */ + if (u > 65536) + sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); + else + sprintf (bp, "0x%x", u); + inc_bp (); + } + break; + case 'X': case 'x': + { + int val = va_arg (ap, int); + + if (size != 0) + if (leading_zero) + sprintf (bp, "%0*x", size, val); + else + sprintf (bp, "%*x", size, val); + else + sprintf (bp, "%x", val); + inc_bp (); + } + break; + case 'd': + { + int val = va_arg (ap, int); + + if (size != 0) + sprintf (bp, "%*d", size, val); + else + sprintf (bp, "%d", val); + inc_bp (); + } + break; + case 'r': + { + /* Register. */ + int val = va_arg (ap, int); + +#define REG2NAME(num, name) case num: sprintf (bp, ""name); \ + regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; + + switch (val) + { + REG2NAME (26, "gp"); + REG2NAME (27, "fp"); + REG2NAME (28, "sp"); + REG2NAME (29, "ilink1"); + REG2NAME (30, "ilink2"); + REG2NAME (31, "blink"); + REG2NAME (60, "lp_count"); + default: + { + const char * ext; + + ext = core_reg_name (state, val); + if (ext) + sprintf (bp, "%s", ext); + else + sprintf (bp,"r%d",val); + } + break; + } + inc_bp (); + } break; + + case 'a': + { + /* Aux Register. */ + int val = va_arg (ap, int); + +#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; + + switch (val) + { + AUXREG2NAME (0x0, "status"); + AUXREG2NAME (0x1, "semaphore"); + AUXREG2NAME (0x2, "lp_start"); + AUXREG2NAME (0x3, "lp_end"); + AUXREG2NAME (0x4, "identity"); + AUXREG2NAME (0x5, "debug"); + default: + { + const char *ext; + + ext = aux_reg_name (state, val); + if (ext) + sprintf (bp, "%s", ext); + else + my_sprintf (state, bp, "%h", val); + } + break; + } + inc_bp (); + } + break; + + case 's': + { + sprintf (bp, "%s", va_arg (ap, char *)); + inc_bp (); + } + break; + + default: + fprintf (stderr, "?? format %c\n", p[-1]); + break; + } + } + + DOCOMM: *bp = 0; + VA_CLOSE (ap); +} + +static void +write_comments_(state, shimm, is_limm, limm_value) + struct arcDisState * state; + int shimm; + int is_limm; + long limm_value; +{ + if (state->commentBuffer != 0) + { + int i; + + if (is_limm) + { + const char *name = post_address (state, limm_value + shimm); + + if (*name != 0) + WRITE_COMMENT (name); + } + for (i = 0; i < state->commNum; i++) + { + if (i == 0) + strcpy (state->commentBuffer, comment_prefix); + else + strcat (state->commentBuffer, ", "); + strncat (state->commentBuffer, state->comm[i], + sizeof (state->commentBuffer)); + } + } +} + +#define write_comments2(x) write_comments_(state, x, is_limm, limm_value) +#define write_comments() write_comments2(0) + +static const char *condName[] = { + /* 0..15. */ + "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , + "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" +}; + +static void +write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) + struct arcDisState * state; + const char * instrName; + int cond; + int condCodeIsPartOfName; + int flag; + int signExtend; + int addrWriteBack; + int directMem; +{ + strcpy (state->instrBuffer, instrName); + + if (cond > 0) + { + const char *cc = 0; + + if (!condCodeIsPartOfName) + strcat (state->instrBuffer, "."); + + if (cond < 16) + cc = condName[cond]; + else + cc = cond_code_name (state, cond); + + if (!cc) + cc = "???"; + + strcat (state->instrBuffer, cc); + } + + if (flag) + strcat (state->instrBuffer, ".f"); + + switch (state->nullifyMode) + { + case BR_exec_always: + strcat (state->instrBuffer, ".d"); + break; + case BR_exec_when_jump: + strcat (state->instrBuffer, ".jd"); + break; + } + + if (signExtend) + strcat (state->instrBuffer, ".x"); + + if (addrWriteBack) + strcat (state->instrBuffer, ".a"); + + if (directMem) + strcat (state->instrBuffer, ".di"); +} + +#define write_instr_name() \ + do \ + { \ + write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ + flag, signExtend, addrWriteBack, directMem); \ + formatString[0] = '\0'; \ + } \ + while (0) + +enum { + op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, + op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, + op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, + op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 +}; + +extern disassemble_info tm_print_insn_info; + +static int +dsmOneArcInst (addr, state) + bfd_vma addr; + struct arcDisState * state; +{ + int condCodeIsPartOfName = 0; + int decodingClass; + const char * instrName; + int repeatsOp = 0; + int fieldAisReg = 1; + int fieldBisReg = 1; + int fieldCisReg = 1; + int fieldA; + int fieldB; + int fieldC = 0; + int flag = 0; + int cond = 0; + int is_shimm = 0; + int is_limm = 0; + long limm_value = 0; + int signExtend = 0; + int addrWriteBack = 0; + int directMem = 0; + int is_linked = 0; + int offset = 0; + int usesAuxReg = 0; + int flags; + int ignoreFirstOpd; + char formatString[60]; + + state->instructionLen = 4; + state->nullifyMode = BR_exec_when_no_jump; + state->opWidth = 12; + state->isBranch = 0; + + state->_mem_load = 0; + state->_ea_present = 0; + state->_load_len = 0; + state->ea_reg1 = no_reg; + state->ea_reg2 = no_reg; + state->_offset = 0; + + if (! NEXT_WORD (0)) + return 0; + + state->_opcode = OPCODE (state->words[0]); + instrName = 0; + decodingClass = 0; /* default! */ + repeatsOp = 0; + condCodeIsPartOfName=0; + state->commNum = 0; + state->tcnt = 0; + state->acnt = 0; + state->flow = noflow; + ignoreFirstOpd = 0; + + if (state->commentBuffer) + state->commentBuffer[0] = '\0'; + + switch (state->_opcode) + { + case op_LD0: + switch (BITS (state->words[0],1,2)) + { + case 0: + instrName = "ld"; + state->_load_len = 4; + break; + case 1: + instrName = "ldb"; + state->_load_len = 1; + break; + case 2: + instrName = "ldw"; + state->_load_len = 2; + break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = 5; + break; + + case op_LD1: + if (BIT (state->words[0],13)) + { + instrName = "lr"; + decodingClass = 10; + } + else + { + switch (BITS (state->words[0],10,11)) + { + case 0: + instrName = "ld"; + state->_load_len = 4; + break; + case 1: + instrName = "ldb"; + state->_load_len = 1; + break; + case 2: + instrName = "ldw"; + state->_load_len = 2; + break; + default: + instrName = "??? (1[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = 6; + } + break; + + case op_ST: + if (BIT (state->words[0],25)) + { + instrName = "sr"; + decodingClass = 8; + } + else + { + switch (BITS (state->words[0],22,23)) + { + case 0: + instrName = "st"; + break; + case 1: + instrName = "stb"; + break; + case 2: + instrName = "stw"; + break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = 7; + } + break; + + case op_3: + decodingClass = 1; /* default for opcode 3... */ + switch (FIELDC (state->words[0])) + { + case 0: + instrName = "flag"; + decodingClass = 2; + break; + case 1: + instrName = "asr"; + break; + case 2: + instrName = "lsr"; + break; + case 3: + instrName = "ror"; + break; + case 4: + instrName = "rrc"; + break; + case 5: + instrName = "sexb"; + break; + case 6: + instrName = "sexw"; + break; + case 7: + instrName = "extb"; + break; + case 8: + instrName = "extw"; + break; + case 0x3f: + { + decodingClass = 9; + switch( FIELDD (state->words[0]) ) + { + case 0: + instrName = "brk"; + break; + case 1: + instrName = "sleep"; + break; + case 2: + instrName = "swi"; + break; + default: + instrName = "???"; + state->flow=invalid_instr; + break; + } + } + break; + + /* ARC Extension Library Instructions + NOTE: We assume that extension codes are these instrs. */ + default: + instrName = instruction_name (state, + state->_opcode, + FIELDC (state->words[0]), + &flags); + if (!instrName) + { + instrName = "???"; + state->flow = invalid_instr; + } + if (flags & IGNORE_FIRST_OPD) + ignoreFirstOpd = 1; + break; + } + break; + + case op_BC: + instrName = "b"; + case op_BLC: + if (!instrName) + instrName = "bl"; + case op_LPC: + if (!instrName) + instrName = "lp"; + case op_JC: + if (!instrName) + { + if (BITS (state->words[0],9,9)) + { + instrName = "jl"; + is_linked = 1; + } + else + { + instrName = "j"; + is_linked = 0; + } + } + condCodeIsPartOfName = 1; + decodingClass = ((state->_opcode == op_JC) ? 4 : 3); + state->isBranch = 1; + break; + + case op_ADD: + case op_ADC: + case op_AND: + repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); + decodingClass = 0; + + switch (state->_opcode) + { + case op_ADD: + instrName = (repeatsOp ? "asl" : "add"); + break; + case op_ADC: + instrName = (repeatsOp ? "rlc" : "adc"); + break; + case op_AND: + instrName = (repeatsOp ? "mov" : "and"); + break; + } + break; + + case op_SUB: instrName = "sub"; + break; + case op_SBC: instrName = "sbc"; + break; + case op_OR: instrName = "or"; + break; + case op_BIC: instrName = "bic"; + break; + + case op_XOR: + if (state->words[0] == 0x7fffffff) + { + /* nop encoded as xor -1, -1, -1 */ + instrName = "nop"; + decodingClass = 9; + } + else + instrName = "xor"; + break; + + default: + instrName = instruction_name (state,state->_opcode,0,&flags); + /* if (instrName) printf("FLAGS=0x%x\n", flags); */ + if (!instrName) + { + instrName = "???"; + state->flow=invalid_instr; + } + if (flags & IGNORE_FIRST_OPD) + ignoreFirstOpd = 1; + break; + } + + fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ + flag = cond = is_shimm = is_limm = 0; + state->nullifyMode = BR_exec_when_no_jump; /* 0 */ + signExtend = addrWriteBack = directMem = 0; + usesAuxReg = 0; + + switch (decodingClass) + { + case 0: + CHECK_FIELD_A (); + CHECK_FIELD_B (); + if (!repeatsOp) + CHECK_FIELD_C (); + CHECK_FLAG_COND_NULLIFY (); + + write_instr_name (); + if (!ignoreFirstOpd) + { + WRITE_FORMAT_x (A); + WRITE_FORMAT_COMMA_x (B); + if (!repeatsOp) + WRITE_FORMAT_COMMA_x (C); + WRITE_NOP_COMMENT (); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); + } + else + { + WRITE_FORMAT_x (B); + if (!repeatsOp) + WRITE_FORMAT_COMMA_x (C); + my_sprintf (state, state->operandBuffer, formatString, + fieldB, fieldC); + } + write_comments (); + break; + + case 1: + CHECK_FIELD_A (); + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + + write_instr_name (); + if (!ignoreFirstOpd) + { + WRITE_FORMAT_x (A); + WRITE_FORMAT_COMMA_x (B); + WRITE_NOP_COMMENT (); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB); + } + else + { + WRITE_FORMAT_x (B); + my_sprintf (state, state->operandBuffer, formatString, fieldB); + } + write_comments (); + break; + + case 2: + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + flag = 0; /* this is the FLAG instruction -- it's redundant */ + + write_instr_name (); + WRITE_FORMAT_x (B); + my_sprintf (state, state->operandBuffer, formatString, fieldB); + write_comments (); + break; + + case 3: + fieldA = BITS (state->words[0],7,26) << 2; + fieldA = (fieldA << 10) >> 10; /* make it signed */ + fieldA += addr + 4; + CHECK_FLAG_COND_NULLIFY (); + flag = 0; + + write_instr_name (); + /* This address could be a label we know. Convert it. */ + if (state->_opcode != op_LPC /* LP */) + { + add_target (fieldA); /* For debugger. */ + state->flow = state->_opcode == op_BLC /* BL */ + ? direct_call + : direct_jump; + /* indirect calls are achieved by "lr blink,[status]; + lr dest<- func addr; j [dest]" */ + } + + strcat (formatString, "%s"); /* address/label name */ + my_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldA)); + write_comments (); + break; + + case 4: + /* For op_JC -- jump to address specified. + Also covers jump and link--bit 9 of the instr. word + selects whether linked, thus "is_linked" is set above. */ + fieldA = 0; + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + + if (!fieldBisReg) + { + fieldAisReg = 0; + fieldA = (fieldB >> 25) & 0x7F; /* flags */ + fieldB = (fieldB & 0xFFFFFF) << 2; + state->flow = is_linked ? direct_call : direct_jump; + add_target (fieldB); + /* screwy JLcc requires .jd mode to execute correctly + * but we pretend it is .nd (no delay slot). */ + if (is_linked && state->nullifyMode == BR_exec_when_jump) + state->nullifyMode = BR_exec_when_no_jump; + } + else + { + state->flow = is_linked ? indirect_call : indirect_jump; + /* We should also treat this as indirect call if NOT linked + * but the preceding instruction was a "lr blink,[status]" + * and we have a delay slot with "add blink,blink,2". + * For now we can't detect such. */ + state->register_for_indirect_jump = fieldB; + } + + write_instr_name (); + strcat (formatString, + IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ + if (fieldA != 0) + { + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x (A); + } + if (IS_REG (B)) + my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); + else + my_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldB), fieldA); + write_comments (); + break; + + case 5: + /* LD instruction. + B and C can be regs, or one (both?) can be limm. */ + CHECK_FIELD_A (); + CHECK_FIELD_B (); + CHECK_FIELD_C (); + if (dbg) + printf ("5:b reg %d %d c reg %d %d \n", + fieldBisReg,fieldB,fieldCisReg,fieldC); + state->_offset = 0; + state->_ea_present = 1; + if (fieldBisReg) + state->ea_reg1 = fieldB; + else + state->_offset += fieldB; + if (fieldCisReg) + state->ea_reg2 = fieldC; + else + state->_offset += fieldC; + state->_mem_load = 1; + + directMem = BIT (state->words[0],5); + addrWriteBack = BIT (state->words[0],3); + signExtend = BIT (state->words[0],0); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB(A); + if (fieldBisReg || fieldB != 0) + WRITE_FORMAT_x_COMMA (B); + else + fieldB = fieldC; + + WRITE_FORMAT_x_RB (C); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); + write_comments (); + break; + + case 6: + /* LD instruction. */ + CHECK_FIELD_B (); + CHECK_FIELD_A (); + fieldC = FIELDD (state->words[0]); + + if (dbg) + printf ("6:b reg %d %d c 0x%x \n", + fieldBisReg, fieldB, fieldC); + state->_ea_present = 1; + state->_offset = fieldC; + state->_mem_load = 1; + if (fieldBisReg) + state->ea_reg1 = fieldB; + /* field B is either a shimm (same as fieldC) or limm (different!) + Say ea is not present, so only one of us will do the name lookup. */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT (state->words[0],14); + addrWriteBack = BIT (state->words[0],12); + signExtend = BIT (state->words[0],9); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (A); + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB (B); + } + else + { + WRITE_FORMAT_x (B); + if (fieldC != 0 && !BIT (state->words[0],13)) + { + fieldCisReg = 0; + WRITE_FORMAT_COMMA_x_RB (C); + } + else + WRITE_FORMAT_RB (); + } + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); + write_comments (); + break; + + case 7: + /* ST instruction. */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + fieldA = FIELDD(state->words[0]); /* shimm */ + + /* [B,A offset] */ + if (dbg) printf("7:b reg %d %x off %x\n", + fieldBisReg,fieldB,fieldA); + state->_ea_present = 1; + state->_offset = fieldA; + if (fieldBisReg) + state->ea_reg1 = fieldB; + /* field B is either a shimm (same as fieldA) or limm (different!) + Say ea is not present, so only one of us will do the name lookup. + (for is_limm we do the name translation here). */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT(state->words[0],26); + addrWriteBack = BIT(state->words[0],24); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(C); + + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB(B); + } + else + { + WRITE_FORMAT_x(B); + if (fieldBisReg && fieldA != 0) + { + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x_RB(A); + } + else + WRITE_FORMAT_RB(); + } + my_sprintf (state, state->operandBuffer, formatString, + fieldC, fieldB, fieldA); + write_comments2(fieldA); + break; + case 8: + /* SR instruction */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(C); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x(B); + WRITE_FORMAT_RB(); + my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); + write_comments(); + break; + + case 9: + write_instr_name(); + state->operandBuffer[0] = '\0'; + break; + + case 10: + /* LR instruction */ + CHECK_FIELD_A(); + CHECK_FIELD_B(); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(A); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x(B); + WRITE_FORMAT_RB(); + my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + write_comments(); + break; + + case 11: + CHECK_COND(); + write_instr_name(); + state->operandBuffer[0] = '\0'; + break; + + default: + mwerror (state, "Bad decoding class in ARC disassembler"); + break; + } + + state->_cond = cond; + return state->instructionLen = offset; +} + + +/* Returns the name the user specified core extension register. */ +static const char * +_coreRegName(arg, regval) + void * arg ATTRIBUTE_UNUSED; + int regval; +{ + return arcExtMap_coreRegName (regval); +} + +/* Returns the name the user specified AUX extension register. */ +static const char * +_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) +{ + return arcExtMap_auxRegName(regval); +} + + +/* Returns the name the user specified condition code name. */ +static const char * +_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) +{ + return arcExtMap_condCodeName(regval); +} + +/* Returns the name the user specified extension instruction. */ +static const char * +_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) +{ + return arcExtMap_instName(majop, minop, flags); +} + +/* Decode an instruction returning the size of the instruction + in bytes or zero if unrecognized. */ +static int +decodeInstr (address, info) + bfd_vma address; /* Address of this instruction. */ + disassemble_info * info; +{ + int status; + bfd_byte buffer[4]; + struct arcDisState s; /* ARC Disassembler state */ + void *stream = info->stream; /* output stream */ + fprintf_ftype func = info->fprintf_func; + int bytes; + + memset (&s, 0, sizeof(struct arcDisState)); + + /* read first instruction */ + status = (*info->read_memory_func) (address, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, address, info); + return 0; + } + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[0] = bfd_getl32(buffer); + else + s.words[0] = bfd_getb32(buffer); + /* always read second word in case of limm */ + + /* we ignore the result since last insn may not have a limm */ + status = (*info->read_memory_func) (address + 4, buffer, 4, info); + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[1] = bfd_getl32(buffer); + else + s.words[1] = bfd_getb32(buffer); + + s._this = &s; + s.coreRegName = _coreRegName; + s.auxRegName = _auxRegName; + s.condCodeName = _condCodeName; + s.instName = _instName; + + /* disassemble */ + bytes = dsmOneArcInst(address, (void *)&s); + + /* display the disassembly instruction */ + (*func) (stream, "%08x ", s.words[0]); + (*func) (stream, " "); + + (*func) (stream, "%-10s ", s.instrBuffer); + + if (__TRANSLATION_REQUIRED(s)) + { + bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + (*info->print_address_func) ((bfd_vma) addr, info); + (*func) (stream, "\n"); + } + else + (*func) (stream, "%s",s.operandBuffer); + return s.instructionLen; +} + +/* Return the print_insn function to use. + Side effect: load (possibly empty) extension section */ + +disassembler_ftype +arc_get_disassembler (void *ptr) +{ + if (ptr) + build_ARC_extmap (ptr); + return decodeInstr; +} diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h new file mode 100644 index 0000000..04bfbbb --- /dev/null +++ b/opcodes/arc-dis.h @@ -0,0 +1,81 @@ +/* Disassembler structures definitions for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef ARCDIS_H +#define ARCDIS_H + +enum +{ + BR_exec_when_no_jump, + BR_exec_always, + BR_exec_when_jump +}; + +enum Flow +{ + noflow, + direct_jump, + direct_call, + indirect_jump, + indirect_call, + invalid_instr +}; + +enum { no_reg = 99 }; +enum { allOperandsSize = 256 }; + +struct arcDisState +{ + void *_this; + int instructionLen; + void (*err)(void*, const char*); + const char *(*coreRegName)(void*, int); + const char *(*auxRegName)(void*, int); + const char *(*condCodeName)(void*, int); + const char *(*instName)(void*, int, int, int*); + + unsigned char* instruction; + unsigned index; + const char *comm[6]; /* instr name, cond, NOP, 3 operands */ + int opWidth; + int targets[4]; + int addresses[4]; + /* Set as a side-effect of calling the disassembler. + Used only by the debugger. */ + enum Flow flow; + int register_for_indirect_jump; + int ea_reg1, ea_reg2, _offset; + int _cond, _opcode; + unsigned long words[2]; + char *commentBuffer; + char instrBuffer[40]; + char operandBuffer[allOperandsSize]; + char _ea_present; + char _mem_load; + char _load_len; + char nullifyMode; + unsigned char commNum; + unsigned char isBranch; + unsigned char tcnt; + unsigned char acnt; +}; + +#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) + +#endif diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c new file mode 100644 index 0000000..fd43d29 --- /dev/null +++ b/opcodes/arc-ext.c @@ -0,0 +1,260 @@ +/* ARC target-dependent stuff. Extension structure access functions + Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include +#include "bfd.h" +#include "arc-ext.h" +#include "libiberty.h" + +/* Extension structure */ +static struct arcExtMap arc_extension_map; + +/* Get the name of an extension instruction. */ + +const char * +arcExtMap_instName(int opcode, int minor, int *flags) +{ + if (opcode == 3) + { + /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ + if (minor < 0x09 || minor == 0x3f) + return 0; + else + opcode = 0x1f - 0x10 + minor - 0x09 + 1; + } + else + if (opcode < 0x10) + return 0; + else + opcode -= 0x10; + if (!arc_extension_map.instructions[opcode]) + return 0; + *flags = arc_extension_map.instructions[opcode]->flags; + return arc_extension_map.instructions[opcode]->name; +} + +/* Get the name of an extension core register. */ + +const char * +arcExtMap_coreRegName(int value) +{ + if (value < 32) + return 0; + return (const char *) arc_extension_map.coreRegisters[value-32]; +} + +/* Get the name of an extension condition code. */ + +const char * +arcExtMap_condCodeName(int value) +{ + if (value < 16) + return 0; + return (const char *) arc_extension_map.condCodes[value-16]; +} + +/* Get the name of an extension aux register. */ + +const char * +arcExtMap_auxRegName(long address) +{ + /* walk the list of aux reg names and find the name */ + struct ExtAuxRegister *r; + + for (r = arc_extension_map.auxRegisters; r; r = r->next) { + if (r->address == address) + return (const char *) r->name; + } + return 0; +} + +/* Recursively free auxilliary register strcture pointers until + the list is empty. */ + +static void +clean_aux_registers(struct ExtAuxRegister *r) +{ + if (r -> next) + { + clean_aux_registers( r->next); + free(r -> name); + free(r -> next); + r ->next = NULL; + } + else + free(r -> name); +} + +/* Free memory that has been allocated for the extensions. */ + +static void +cleanup_ext_map(void) +{ + struct ExtAuxRegister *r; + struct ExtInstruction *insn; + int i; + + /* clean aux reg structure */ + r = arc_extension_map.auxRegisters; + if (r) + { + (clean_aux_registers(r)); + free(r); + } + + /* clean instructions */ + for (i = 0; i < NUM_EXT_INST; i++) + { + insn = arc_extension_map.instructions[i]; + if (insn) + free(insn->name); + } + + /* clean core reg struct */ + for (i = 0; i < NUM_EXT_CORE; i++) + { + if (arc_extension_map.coreRegisters[i]) + free(arc_extension_map.coreRegisters[i]); + } + + for (i = 0; i < NUM_EXT_COND; i++) { + if (arc_extension_map.condCodes[i]) + free(arc_extension_map.condCodes[i]); + } + + memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); +} + +int +arcExtMap_add(void *base, unsigned long length) +{ + unsigned char *block = base; + unsigned char *p = block; + + /* Clean up and reset everything if needed. */ + cleanup_ext_map(); + + while (p && p < (block + length)) + { + /* p[0] == length of record + p[1] == type of record + For instructions: + p[2] = opcode + p[3] = minor opcode (if opcode == 3) + p[4] = flags + p[5]+ = name + For core regs and condition codes: + p[2] = value + p[3]+ = name + For aux regs: + p[2..5] = value + p[6]+ = name + (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ + + if (p[0] == 0) + return -1; + + switch (p[1]) + { + case EXT_INSTRUCTION: + { + char opcode = p[2]; + char minor = p[3]; + char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); + struct ExtInstruction * insn = + (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); + + if (opcode==3) + opcode = 0x1f - 0x10 + minor - 0x09 + 1; + else + opcode -= 0x10; + insn -> flags = (char) *(p+4); + strcpy(insn_name, (p+5)); + insn -> name = insn_name; + arc_extension_map.instructions[(int) opcode] = insn; + } + break; + + case EXT_CORE_REGISTER: + { + char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); + + strcpy(core_name, (p+3)); + arc_extension_map.coreRegisters[p[2]-32] = core_name; + } + break; + + case EXT_COND_CODE: + { + char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); + strcpy(cc_name, (p+3)); + arc_extension_map.condCodes[p[2]-16] = cc_name; + } + break; + + case EXT_AUX_REGISTER: + { + /* trickier -- need to store linked list to these */ + struct ExtAuxRegister *newAuxRegister = + (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); + char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); + + strcpy (aux_name, (p+6)); + newAuxRegister->name = aux_name; + newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5]; + newAuxRegister->next = arc_extension_map.auxRegisters; + arc_extension_map.auxRegisters = newAuxRegister; + } + break; + + default: + return -1; + + } + p += p[0]; /* move to next record */ + } + + return 0; +} + +/* Load hw extension descibed in .extArcMap ELF section. */ + +void +build_ARC_extmap (text_bfd) + bfd *text_bfd; +{ + char *arcExtMap; + bfd_size_type count; + asection *p; + + for (p = text_bfd->sections; p != NULL; p = p->next) + if (!strcmp (p->name, ".arcextmap")) + { + count = p->_raw_size; + arcExtMap = (char *) xmalloc (count); + if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count)) + { + arcExtMap_add ((PTR) arcExtMap, count); + break; + } + free ((PTR) arcExtMap); + } +} diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h new file mode 100644 index 0000000..bfe9750 --- /dev/null +++ b/opcodes/arc-ext.h @@ -0,0 +1,62 @@ +/* ARC target-dependent stuff. Extension data structures. + Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef ARCEXT_H +#define ARCEXT_H + +enum {EXT_INSTRUCTION = 0}; +enum {EXT_CORE_REGISTER = 1}; +enum {EXT_AUX_REGISTER = 2}; +enum {EXT_COND_CODE = 3}; + +enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)}; +enum {NUM_EXT_CORE = 59-32+1}; +enum {NUM_EXT_COND = 0x1f-0x10+1}; + +struct ExtInstruction +{ + char flags; + char *name; +}; + +struct ExtAuxRegister +{ + long address; + char *name; + struct ExtAuxRegister *next; +}; + +struct arcExtMap +{ + struct ExtAuxRegister *auxRegisters; + struct ExtInstruction *instructions[NUM_EXT_INST]; + unsigned char *coreRegisters[NUM_EXT_CORE]; + unsigned char *condCodes[NUM_EXT_COND]; +}; + +extern int arcExtMap_add(void*, unsigned long); +extern const char *arcExtMap_coreRegName(int); +extern const char *arcExtMap_auxRegName(long); +extern const char *arcExtMap_condCodeName(int); +extern const char *arcExtMap_instName(int, int, int*); +extern void build_ARC_extmap(bfd *); + +#define IGNORE_FIRST_OPD 1 + +#endif diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c new file mode 100644 index 0000000..b7afb86 --- /dev/null +++ b/opcodes/arc-opc.c @@ -0,0 +1,1818 @@ +/* Opcode table for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "opcode/arc.h" + +#define INSERT_FN(fn) \ +static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ + int, const struct arc_operand_value *, long, \ + const char **)) +#define EXTRACT_FN(fn) \ +static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ + int, const struct arc_operand_value **, int *)) + +INSERT_FN (insert_reg); +INSERT_FN (insert_shimmfinish); +INSERT_FN (insert_limmfinish); +INSERT_FN (insert_offset); +INSERT_FN (insert_base); +INSERT_FN (insert_st_syntax); +INSERT_FN (insert_ld_syntax); +INSERT_FN (insert_addr_wb); +INSERT_FN (insert_flag); +INSERT_FN (insert_nullify); +INSERT_FN (insert_flagfinish); +INSERT_FN (insert_cond); +INSERT_FN (insert_forcelimm); +INSERT_FN (insert_reladdr); +INSERT_FN (insert_absaddr); +INSERT_FN (insert_jumpflags); +INSERT_FN (insert_unopmacro); + +EXTRACT_FN (extract_reg); +EXTRACT_FN (extract_ld_offset); +EXTRACT_FN (extract_ld_syntax); +EXTRACT_FN (extract_st_offset); +EXTRACT_FN (extract_st_syntax); +EXTRACT_FN (extract_flag); +EXTRACT_FN (extract_cond); +EXTRACT_FN (extract_reladdr); +EXTRACT_FN (extract_jumpflags); +EXTRACT_FN (extract_unopmacro); + +enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; + +#define OPERANDS 3 + +enum operand ls_operand[OPERANDS]; + +#define LS_VALUE 0 +#define LS_DEST 0 +#define LS_BASE 1 +#define LS_OFFSET 2 + +/* Various types of ARC operands, including insn suffixes. */ + +/* Insn format values: + + 'a' REGA register A field + 'b' REGB register B field + 'c' REGC register C field + 'S' SHIMMFINISH finish inserting a shimm value + 'L' LIMMFINISH finish inserting a limm value + 'o' OFFSET offset in st insns + 'O' OFFSET offset in ld insns + '0' SYNTAX_ST_NE enforce store insn syntax, no errors + '1' SYNTAX_LD_NE enforce load insn syntax, no errors + '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only + '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only + 's' BASE base in st insn + 'f' FLAG F flag + 'F' FLAGFINISH finish inserting the F flag + 'G' FLAGINSN insert F flag in "flag" insn + 'n' DELAY N field (nullify field) + 'q' COND condition code field + 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm + 'B' BRANCH branch address (22 bit pc relative) + 'J' JUMP jump address (26 bit absolute) + 'j' JUMPFLAGS optional high order bits of 'J' + 'z' SIZE1 size field in ld a,[b,c] + 'Z' SIZE10 size field in ld a,[b,shimm] + 'y' SIZE22 size field in st c,[b,shimm] + 'x' SIGN0 sign extend field ld a,[b,c] + 'X' SIGN9 sign extend field ld a,[b,shimm] + 'w' ADDRESS3 write-back field in ld a,[b,c] + 'W' ADDRESS12 write-back field in ld a,[b,shimm] + 'v' ADDRESS24 write-back field in st c,[b,shimm] + 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] + 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] + 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] + 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros + + The following modifiers may appear between the % and char (eg: %.f): + + '.' MODDOT '.' prefix must be present + 'r' REG generic register value, for register table + 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] + + Fields are: + + CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ + +const struct arc_operand arc_operands[] = +{ +/* place holder (??? not sure if needed). */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, 0 }, + +/* register A or shimm/limm indicator. */ +#define REGA (UNUSED + 1) + { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, + +/* register B or shimm/limm indicator. */ +#define REGB (REGA + 1) + { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, + +/* register C or shimm/limm indicator. */ +#define REGC (REGB + 1) + { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, + +/* fake operand used to insert shimm value into most instructions. */ +#define SHIMMFINISH (REGC + 1) + { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, + +/* fake operand used to insert limm value into most instructions. */ +#define LIMMFINISH (SHIMMFINISH + 1) + { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, + +/* shimm operand when there is no reg indicator (st). */ +#define ST_OFFSET (LIMMFINISH + 1) + { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, + +/* shimm operand when there is no reg indicator (ld). */ +#define LD_OFFSET (ST_OFFSET + 1) + { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, + +/* operand for base. */ +#define BASE (LD_OFFSET + 1) + { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, + +/* 0 enforce syntax for st insns. */ +#define SYNTAX_ST_NE (BASE + 1) + { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, + +/* 1 enforce syntax for ld insns. */ +#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) + { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, + +/* 0 enforce syntax for st insns. */ +#define SYNTAX_ST (SYNTAX_LD_NE + 1) + { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, + +/* 0 enforce syntax for ld insns. */ +#define SYNTAX_LD (SYNTAX_ST + 1) + { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, + +/* flag update bit (insertion is defered until we know how). */ +#define FLAG (SYNTAX_LD + 1) + { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, + +/* fake utility operand to finish 'f' suffix handling. */ +#define FLAGFINISH (FLAG + 1) + { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, + +/* fake utility operand to set the 'f' flag for the "flag" insn. */ +#define FLAGINSN (FLAGFINISH + 1) + { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, + +/* branch delay types. */ +#define DELAY (FLAGINSN + 1) + { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, + +/* conditions. */ +#define COND (DELAY + 1) + { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, + +/* set `cond_p' to 1 to ensure a constant is treated as a limm. */ +#define FORCELIMM (COND + 1) + { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, + +/* branch address; b, bl, and lp insns. */ +#define BRANCH (FORCELIMM + 1) + { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, + +/* jump address; j insn (this is basically the same as 'L' except that the + value is right shifted by 2). */ +#define JUMP (BRANCH + 1) + { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, + +/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ +#define JUMPFLAGS (JUMP + 1) + { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, + +/* size field, stored in bit 1,2. */ +#define SIZE1 (JUMPFLAGS + 1) + { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* size field, stored in bit 10,11. */ +#define SIZE10 (SIZE1 + 1) + { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* size field, stored in bit 22,23. */ +#define SIZE22 (SIZE10 + 1) + { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* sign extend field, stored in bit 0. */ +#define SIGN0 (SIZE22 + 1) + { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* sign extend field, stored in bit 9. */ +#define SIGN9 (SIGN0 + 1) + { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* address write back, stored in bit 3. */ +#define ADDRESS3 (SIGN9 + 1) + { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, + +/* address write back, stored in bit 12. */ +#define ADDRESS12 (ADDRESS3 + 1) + { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, + +/* address write back, stored in bit 24. */ +#define ADDRESS24 (ADDRESS12 + 1) + { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, + +/* cache bypass, stored in bit 5. */ +#define CACHEBYPASS5 (ADDRESS24 + 1) + { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* cache bypass, stored in bit 14. */ +#define CACHEBYPASS14 (CACHEBYPASS5 + 1) + { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* cache bypass, stored in bit 26. */ +#define CACHEBYPASS26 (CACHEBYPASS14 + 1) + { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* unop macro, used to copy REGB to REGC. */ +#define UNOPMACRO (CACHEBYPASS26 + 1) + { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, + +/* '.' modifier ('.' required). */ +#define MODDOT (UNOPMACRO + 1) + { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, + +/* Dummy 'r' modifier for the register table. + It's called a "dummy" because there's no point in inserting an 'r' into all + the %a/%b/%c occurrences in the insn table. */ +#define REG (MODDOT + 1) + { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, + +/* Known auxiliary register modifier (stored in shimm field). */ +#define AUXREG (REG + 1) + { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, + +/* end of list place holder. */ + { 0, 0, 0, 0, 0, 0 } +}; + +/* Given a format letter, yields the index into `arc_operands'. + eg: arc_operand_map['a'] = REGA. */ +unsigned char arc_operand_map[256]; + +/* ARC instructions. + + Longer versions of insns must appear before shorter ones (if gas sees + "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is + junk). This isn't necessary for `ld' because of the trailing ']'. + + Instructions that are really macros based on other insns must appear + before the real insn so they're chosen when disassembling. Eg: The `mov' + insn is really the `and' insn. */ + +struct arc_opcode arc_opcodes[] = +{ + /* Base case instruction set (core versions 5-8) */ + + /* "mov" is really an "and". */ + { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, + /* "asl" is really an "add". */ + { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, + /* "lsl" is really an "add". */ + { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, + /* "nop" is really an "xor". */ + { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, + /* "rlc" is really an "adc". */ + { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, + { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, + { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, + { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, + { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, + { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, + { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, + { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, + { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, + { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, + /* %Q: force cond_p=1 -> no shimm values. This insn allows an + optional flags spec. */ + { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* This insn allows an optional flags spec. */ + { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* Put opcode 1 ld insns first so shimm gets prefered over limm. + "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, + { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, + { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, + { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, + { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, + { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, + { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, + { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, + { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, + { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, + { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, + /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, + { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } +}; + +const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); + +const struct arc_operand_value arc_reg_names[] = +{ + /* Core register set r0-r63. */ + + /* r0-r28 - general purpose registers. */ + { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, + { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, + { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, + { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, + { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, + { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, + { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, + { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, + { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, + { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink1", 29, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink2", 30, REG, 0 }, + /* Branch-link register. */ + { "blink", 31, REG, 0 }, + + /* r32-r59 reserved for extensions. */ + { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, + { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, + { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, + { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, + { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, + { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, + { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, + { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, + { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, + { "r59", 59, REG, 0 }, + + /* Loop count register (24 bits). */ + { "lp_count", 60, REG, 0 }, + /* Short immediate data indicator setting flags. */ + { "r61", 61, REG, ARC_REGISTER_READONLY }, + /* Long immediate data indicator setting flags. */ + { "r62", 62, REG, ARC_REGISTER_READONLY }, + /* Short immediate data indicator not setting flags. */ + { "r63", 63, REG, ARC_REGISTER_READONLY }, + + /* Small-data base register. */ + { "gp", 26, REG, 0 }, + /* Frame pointer. */ + { "fp", 27, REG, 0 }, + /* Stack pointer. */ + { "sp", 28, REG, 0 }, + + { "r29", 29, REG, 0 }, + { "r30", 30, REG, 0 }, + { "r31", 31, REG, 0 }, + { "r60", 60, REG, 0 }, + + /* Auxiliary register set. */ + + /* Auxiliary register address map: + 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation + 0xfffffeff-0x80000000 - customer limm allocation + 0x7fffffff-0x00000100 - ARC limm allocation + 0x000000ff-0x00000000 - ARC shimm allocation */ + + /* Base case auxiliary registers (shimm address). */ + { "status", 0x00, AUXREG, 0 }, + { "semaphore", 0x01, AUXREG, 0 }, + { "lp_start", 0x02, AUXREG, 0 }, + { "lp_end", 0x03, AUXREG, 0 }, + { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, + { "debug", 0x05, AUXREG, 0 }, +}; + +const int arc_reg_names_count = + sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); + +/* The suffix table. + Operands with the same name must be stored together. */ + +const struct arc_operand_value arc_suffixes[] = +{ + /* Entry 0 is special, default values aren't printed by the disassembler. */ + { "", 0, -1, 0 }, + + /* Base case condition codes. */ + { "al", 0, COND, 0 }, + { "ra", 0, COND, 0 }, + { "eq", 1, COND, 0 }, + { "z", 1, COND, 0 }, + { "ne", 2, COND, 0 }, + { "nz", 2, COND, 0 }, + { "pl", 3, COND, 0 }, + { "p", 3, COND, 0 }, + { "mi", 4, COND, 0 }, + { "n", 4, COND, 0 }, + { "cs", 5, COND, 0 }, + { "c", 5, COND, 0 }, + { "lo", 5, COND, 0 }, + { "cc", 6, COND, 0 }, + { "nc", 6, COND, 0 }, + { "hs", 6, COND, 0 }, + { "vs", 7, COND, 0 }, + { "v", 7, COND, 0 }, + { "vc", 8, COND, 0 }, + { "nv", 8, COND, 0 }, + { "gt", 9, COND, 0 }, + { "ge", 10, COND, 0 }, + { "lt", 11, COND, 0 }, + { "le", 12, COND, 0 }, + { "hi", 13, COND, 0 }, + { "ls", 14, COND, 0 }, + { "pnz", 15, COND, 0 }, + + /* Condition codes 16-31 reserved for extensions. */ + + { "f", 1, FLAG, 0 }, + + { "nd", ARC_DELAY_NONE, DELAY, 0 }, + { "d", ARC_DELAY_NORMAL, DELAY, 0 }, + { "jd", ARC_DELAY_JUMP, DELAY, 0 }, + + { "b", 1, SIZE1, 0 }, + { "b", 1, SIZE10, 0 }, + { "b", 1, SIZE22, 0 }, + { "w", 2, SIZE1, 0 }, + { "w", 2, SIZE10, 0 }, + { "w", 2, SIZE22, 0 }, + { "x", 1, SIGN0, 0 }, + { "x", 1, SIGN9, 0 }, + { "a", 1, ADDRESS3, 0 }, + { "a", 1, ADDRESS12, 0 }, + { "a", 1, ADDRESS24, 0 }, + + { "di", 1, CACHEBYPASS5, 0 }, + { "di", 1, CACHEBYPASS14, 0 }, + { "di", 1, CACHEBYPASS26, 0 }, +}; + +const int arc_suffixes_count = + sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); + +/* Indexed by first letter of opcode. Points to chain of opcodes with same + first letter. */ +static struct arc_opcode *opcode_map[26 + 1]; + +/* Indexed by insn code. Points to chain of opcodes with same insn code. */ +static struct arc_opcode *icode_map[32]; + +/* Configuration flags. */ + +/* Various ARC_HAVE_XXX bits. */ +static int cpu_type; + +/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ + +int +arc_get_opcode_mach (bfd_mach, big_p) + int bfd_mach, big_p; +{ + static int mach_type_map[] = + { + ARC_MACH_5, + ARC_MACH_6, + ARC_MACH_7, + ARC_MACH_8 + }; + return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); +} + +/* Initialize any tables that need it. + Must be called once at start up (or when first needed). + + FLAGS is a set of bits that say what version of the cpu we have, + and in particular at least (one of) ARC_MACH_XXX. */ + +void +arc_opcode_init_tables (flags) + int flags; +{ + static int init_p = 0; + + cpu_type = flags; + + /* We may be intentionally called more than once (for example gdb will call + us each time the user switches cpu). These tables only need to be init'd + once though. */ + if (!init_p) + { + register int i,n; + + memset (arc_operand_map, 0, sizeof (arc_operand_map)); + n = sizeof (arc_operands) / sizeof (arc_operands[0]); + for (i = 0; i < n; ++i) + arc_operand_map[arc_operands[i].fmt] = i; + + memset (opcode_map, 0, sizeof (opcode_map)); + memset (icode_map, 0, sizeof (icode_map)); + /* Scan the table backwards so macros appear at the front. */ + for (i = arc_opcodes_count - 1; i >= 0; --i) + { + int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); + int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); + + arc_opcodes[i].next_asm = opcode_map[opcode_hash]; + opcode_map[opcode_hash] = &arc_opcodes[i]; + + arc_opcodes[i].next_dis = icode_map[icode_hash]; + icode_map[icode_hash] = &arc_opcodes[i]; + } + + init_p = 1; + } +} + +/* Return non-zero if OPCODE is supported on the specified cpu. + Cpu selection is made when calling `arc_opcode_init_tables'. */ + +int +arc_opcode_supported (opcode) + const struct arc_opcode *opcode; +{ + if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) + return 1; + return 0; +} + +/* Return the first insn in the chain for assembling INSN. */ + +const struct arc_opcode * +arc_opcode_lookup_asm (insn) + const char *insn; +{ + return opcode_map[ARC_HASH_OPCODE (insn)]; +} + +/* Return the first insn in the chain for disassembling INSN. */ + +const struct arc_opcode * +arc_opcode_lookup_dis (insn) + unsigned int insn; +{ + return icode_map[ARC_HASH_ICODE (insn)]; +} + +/* Nonzero if we've seen an 'f' suffix (in certain insns). */ +static int flag_p; + +/* Nonzero if we've finished processing the 'f' suffix. */ +static int flagshimm_handled_p; + +/* Nonzero if we've seen a 'a' suffix (address writeback). */ +static int addrwb_p; + +/* Nonzero if we've seen a 'q' suffix (condition code). */ +static int cond_p; + +/* Nonzero if we've inserted a nullify condition. */ +static int nullify_p; + +/* The value of the a nullify condition we inserted. */ +static int nullify; + +/* Nonzero if we've inserted jumpflags. */ +static int jumpflags_p; + +/* Nonzero if we've inserted a shimm. */ +static int shimm_p; + +/* The value of the shimm we inserted (each insn only gets one but it can + appear multiple times). */ +static int shimm; + +/* Nonzero if we've inserted a limm (during assembly) or seen a limm + (during disassembly). */ +static int limm_p; + +/* The value of the limm we inserted. Each insn only gets one but it can + appear multiple times. */ +static long limm; + +/* Insertion functions. */ + +/* Called by the assembler before parsing an instruction. */ + +void +arc_opcode_init_insert () +{ + int i; + + for(i = 0; i < OPERANDS; i++) + ls_operand[i] = OP_NONE; + + flag_p = 0; + flagshimm_handled_p = 0; + cond_p = 0; + addrwb_p = 0; + shimm_p = 0; + limm_p = 0; + jumpflags_p = 0; + nullify_p = 0; + nullify = 0; /* the default is important. */ +} + +/* Called by the assembler to see if the insn has a limm operand. + Also called by the disassembler to see if the insn contains a limm. */ + +int +arc_opcode_limm_p (limmp) + long *limmp; +{ + if (limmp) + *limmp = limm; + return limm_p; +} + +/* Insert a value into a register field. + If REG is NULL, then this is actually a constant. + + We must also handle auxiliary registers for lr/sr insns. */ + +static arc_insn +insert_reg (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods; + const struct arc_operand_value *reg; + long value; + const char **errmsg; +{ + static char buf[100]; + enum operand op_type = OP_NONE; + + if (reg == NULL) + { + /* We have a constant that also requires a value stored in a register + field. Handle these by updating the register field and saving the + value for later handling by either %S (shimm) or %L (limm). */ + + /* Try to use a shimm value before a limm one. */ + if (ARC_SHIMM_CONST_P (value) + /* If we've seen a conditional suffix we have to use a limm. */ + && !cond_p + /* If we already have a shimm value that is different than ours + we have to use a limm. */ + && (!shimm_p || shimm == value)) + { + int marker; + + op_type = OP_SHIMM; + /* forget about shimm as dest mlm. */ + + if ('a' != operand->fmt) + { + shimm_p = 1; + shimm = value; + flagshimm_handled_p = 1; + marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; + } + else + { + /* don't request flag setting on shimm as dest. */ + marker = ARC_REG_SHIMM; + } + insn |= marker << operand->shift; + /* insn |= value & 511; - done later. */ + } + /* We have to use a limm. If we've already seen one they must match. */ + else if (!limm_p || limm == value) + { + op_type = OP_LIMM; + limm_p = 1; + limm = value; + insn |= ARC_REG_LIMM << operand->shift; + /* The constant is stored later. */ + } + else + { + *errmsg = "unable to fit different valued constants into instruction"; + } + } + else + { + /* We have to handle both normal and auxiliary registers. */ + + if (reg->type == AUXREG) + { + if (!(mods & ARC_MOD_AUXREG)) + *errmsg = "auxiliary register not allowed here"; + else + { + if ((insn & I(-1)) == I(2)) /* check for use validity. */ + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = "attempt to set readonly register"; + } + else + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = "attempt to read writeonly register"; + } + insn |= ARC_REG_SHIMM << operand->shift; + insn |= reg->value << arc_operands[reg->type].shift; + } + } + else + { + /* check for use validity. */ + if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = "attempt to set readonly register"; + } + if ('a' != operand->fmt) + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = "attempt to read writeonly register"; + } + /* We should never get an invalid register number here. */ + if ((unsigned int) reg->value > 60) + { + sprintf (buf, "invalid register number `%d'", reg->value); + *errmsg = buf; + } + insn |= reg->value << operand->shift; + op_type = OP_REG; + } + } + + switch (operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn & I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } + + return insn; +} + +/* Called when we see an 'f' flag. */ + +static arc_insn +insert_flag (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + /* We can't store anything in the insn until we've parsed the registers. + Just record the fact that we've got this flag. `insert_reg' will use it + to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ + flag_p = 1; + return insn; +} + +/* Called when we see an nullify condition. */ + +static arc_insn +insert_nullify (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value; + const char **errmsg ATTRIBUTE_UNUSED; +{ + nullify_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + nullify = value; + return insn; +} + +/* Called after completely building an insn to ensure the 'f' flag gets set + properly. This is needed because we don't know how to set this flag until + we've parsed the registers. */ + +static arc_insn +insert_flagfinish (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + if (flag_p && !flagshimm_handled_p) + { + if (shimm_p) + abort (); + flagshimm_handled_p = 1; + insn |= (1 << operand->shift); + } + return insn; +} + +/* Called when we see a conditional flag (eg: .eq). */ + +static arc_insn +insert_cond (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value; + const char **errmsg ATTRIBUTE_UNUSED; +{ + cond_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + return insn; +} + +/* Used in the "j" instruction to prevent constants from being interpreted as + shimm values (which the jump insn doesn't accept). This can also be used + to force the use of limm values in other situations (eg: ld r0,[foo] uses + this). + ??? The mechanism is sound. Access to it is a bit klunky right now. */ + +static arc_insn +insert_forcelimm (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + cond_p = 1; + return insn; +} + +static arc_insn +insert_addr_wb (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + addrwb_p = 1 << operand->shift; + return insn; +} + +static arc_insn +insert_base (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods; + const struct arc_operand_value *reg; + long value; + const char **errmsg; +{ + if (reg != NULL) + { + arc_insn myinsn; + myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; + insn |= B(myinsn); + ls_operand[LS_BASE] = OP_REG; + } + else if (ARC_SHIMM_CONST_P (value) && !cond_p) + { + if (shimm_p && value != shimm) + { + /* convert the previous shimm operand to a limm. */ + limm_p = 1; + limm = shimm; + insn &= ~C(-1); /* we know where the value is in insn. */ + insn |= C(ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + insn |= ARC_REG_SHIMM << operand->shift; + shimm_p = 1; + shimm = value; + ls_operand[LS_BASE] = OP_SHIMM; + } + else + { + if (limm_p && value != limm) + { + *errmsg = "too many long constants"; + return insn; + } + limm_p = 1; + limm = value; + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + + return insn; +} + +/* Used in ld/st insns to handle the offset field. We don't try to + match operand syntax here. we catch bad combinations later. */ + +static arc_insn +insert_offset (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods; + const struct arc_operand_value *reg; + long value; + const char **errmsg; +{ + long minval, maxval; + + if (reg != NULL) + { + arc_insn myinsn; + myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; + ls_operand[LS_OFFSET] = OP_REG; + if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */ + if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */ + insn |= C(myinsn); + } + else + { + /* This is *way* more general than necessary, but maybe some day it'll + be useful. */ + if (operand->flags & ARC_OPERAND_SIGNED) + { + minval = -(1 << (operand->bits - 1)); + maxval = (1 << (operand->bits - 1)) - 1; + } + else + { + minval = 0; + maxval = (1 << operand->bits) - 1; + } + if ((cond_p && !limm_p) || (value < minval || value > maxval)) + { + if (limm_p && value != limm) + { + *errmsg = "too many long constants"; + } + else + { + limm_p = 1; + limm = value; + if (operand->flags & ARC_OPERAND_STORE) + insn |= B(ARC_REG_LIMM); + if (operand->flags & ARC_OPERAND_LOAD) + insn |= C(ARC_REG_LIMM); + ls_operand[LS_OFFSET] = OP_LIMM; + } + } + else + { + if ((value < minval || value > maxval)) + *errmsg = "need too many limms"; + else if (shimm_p && value != shimm) + { + /* check for bad operand combinations before we lose info about them. */ + if ((insn & I(-1)) == I(1)) + { + *errmsg = "to many shimms in load"; + goto out; + } + if (limm_p && operand->flags & ARC_OPERAND_LOAD) + { + *errmsg = "too many long constants"; + goto out; + } + /* convert what we thought was a shimm to a limm. */ + limm_p = 1; + limm = shimm; + if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) + { + insn &= ~C(-1); + insn |= C(ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) + { + insn &= ~B(-1); + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + } + shimm = value; + shimm_p = 1; + ls_operand[LS_OFFSET] = OP_SHIMM; + } + } + out: + return insn; +} + +/* Used in st insns to do final disasemble syntax check. */ + +static long +extract_st_syntax (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ +#define ST_SYNTAX(V,B,O) \ +((ls_operand[LS_VALUE] == (V) && \ + ls_operand[LS_BASE] == (B) && \ + ls_operand[LS_OFFSET] == (O))) + + if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) + || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) + *invalid = 1; + return 0; +} + +int +arc_limm_fixup_adjust(insn) + arc_insn insn; +{ + int retval = 0; + + /* check for st shimm,[limm]. */ + if ((insn & (I(-1) | C(-1) | B(-1))) == + (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) + { + retval = insn & 0x1ff; + if (retval & 0x100) /* sign extend 9 bit offset. */ + retval |= ~0x1ff; + } + return -retval; /* negate offset for return. */ +} + +/* Used in st insns to do final syntax check. */ + +static arc_insn +insert_st_syntax (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) + { + /* change an illegal insn into a legal one, it's easier to + do it here than to try to handle it during operand scan. */ + limm_p = 1; + limm = shimm; + shimm_p = 0; + shimm = 0; + insn = insn & ~(C(-1) | 511); + insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; + ls_operand[LS_VALUE] = OP_LIMM; + } + + if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)) + { + /* try to salvage this syntax. */ + if (shimm & 0x1) /* odd shimms won't work. */ + { + if (limm_p) /* do we have a limm already? */ + { + *errmsg = "impossible store"; + } + limm_p = 1; + limm = shimm; + shimm = 0; + shimm_p = 0; + insn = insn & ~(B(-1) | 511); + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + else + { + shimm >>= 1; + insn = insn & ~511; + insn |= shimm; + ls_operand[LS_OFFSET] = OP_SHIMM; + } + } + if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) + { + limm += arc_limm_fixup_adjust(insn); + } + if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE) + || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) + *errmsg = "st operand error"; + if (addrwb_p) + { + if (ls_operand[LS_BASE] != OP_REG) + *errmsg = "address writeback not allowed"; + insn |= addrwb_p; + } + if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) + *errmsg = "store value must be zero"; + return insn; +} + +/* Used in ld insns to do final syntax check. */ + +static arc_insn +insert_ld_syntax (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg; +{ +#define LD_SYNTAX(D,B,O) \ +((ls_operand[LS_DEST] == (D) && \ + ls_operand[LS_BASE] == (B) && \ + ls_operand[LS_OFFSET] == (O))) + + int test = insn & I(-1); + + if (!(test == I(1))) + { + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM + || ls_operand[LS_OFFSET] == OP_SHIMM)) + *errmsg = "invalid load/shimm insn"; + } + if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) + || LD_SYNTAX(OP_REG,OP_REG,OP_REG) + || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) + || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) + *errmsg = "ld operand error"; + if (addrwb_p) + { + if (ls_operand[LS_BASE] != OP_REG) + *errmsg = "address writeback not allowed"; + insn |= addrwb_p; + } + return insn; +} + +/* Used in ld insns to do final syntax check. */ + +static long +extract_ld_syntax (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + int test = insn[0] & I(-1); + + if (!(test == I(1))) + { + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM + || ls_operand[LS_OFFSET] == OP_SHIMM)) + *invalid = 1; + } + if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1))) + || LD_SYNTAX(OP_REG,OP_REG,OP_REG) + || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0)) + || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) + *invalid = 1; + return 0; +} + +/* Called at the end of processing normal insns (eg: add) to insert a shimm + value (if present) into the insn. */ + +static arc_insn +insert_shimmfinish (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + if (shimm_p) + insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; + return insn; +} + +/* Called at the end of processing normal insns (eg: add) to insert a limm + value (if present) into the insn. + + Note that this function is only intended to handle instructions (with 4 byte + immediate operands). It is not intended to handle data. */ + +/* ??? Actually, there's nothing for us to do as we can't call frag_more, the + caller must do that. The extract fns take a pointer to two words. The + insert fns could be converted and then we could do something useful, but + then the reloc handlers would have to know to work on the second word of + a 2 word quantity. That's too much so we don't handle them. */ + +static arc_insn +insert_limmfinish (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ +#if 0 + if (limm_p) + ; /* nothing to do, gas does it. */ +#endif + return insn; +} + +static arc_insn +insert_jumpflags (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value; + const char **errmsg; +{ + if (!flag_p) + { + *errmsg = "jump flags, but no .f seen"; + } + if (!limm_p) + { + *errmsg = "jump flags, but no limm addr"; + } + if (limm & 0xfc000000) + { + *errmsg = "flag bits of jump address limm lost"; + } + if (limm & 0x03000000) + { + *errmsg = "attempt to set HR bits"; + } + if ((value & ((1 << operand->bits) - 1)) != value) + { + *errmsg = "bad jump flags value"; + } + jumpflags_p = 1; + limm = ((limm & ((1 << operand->shift) - 1)) + | ((value & ((1 << operand->bits) - 1)) << operand->shift)); + return insn; +} + +/* Called at the end of unary operand macros to copy the B field to C. */ + +static arc_insn +insert_unopmacro (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; + return insn; +} + +/* Insert a relative address for a branch insn (b, bl, or lp). */ + +static arc_insn +insert_reladdr (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value; + const char **errmsg; +{ + if (value & 3) + *errmsg = "branch address not on 4 byte boundary"; + insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; + return insn; +} + +/* Insert a limm value as a 26 bit address right shifted 2 into the insn. + + Note that this function is only intended to handle instructions (with 4 byte + immediate operands). It is not intended to handle data. */ + +/* ??? Actually, there's little for us to do as we can't call frag_more, the + caller must do that. The extract fns take a pointer to two words. The + insert fns could be converted and then we could do something useful, but + then the reloc handlers would have to know to work on the second word of + a 2 word quantity. That's too much so we don't handle them. + + We do check for correct usage of the nullify suffix, or we + set the default correctly, though. */ + +static arc_insn +insert_absaddr (insn, operand, mods, reg, value, errmsg) + arc_insn insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value *reg ATTRIBUTE_UNUSED; + long value ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if (limm_p) + { + /* if it is a jump and link, .jd must be specified. */ + if (insn & R(-1,9,1)) + { + if (!nullify_p) + { + insn |= 0x02 << 5; /* default nullify to .jd. */ + } + else + { + if (nullify != 0x02) + { + *errmsg = "must specify .jd or no nullify suffix"; + } + } + } + } + return insn; +} + +/* Extraction functions. + + The suffix extraction functions' return value is redundant since it can be + obtained from (*OPVAL)->value. However, the boolean suffixes don't have + a suffix table entry for the "false" case, so values of zero must be + obtained from the return value (*OPVAL == NULL). */ + +static const struct arc_operand_value *lookup_register (int type, long regno); + +/* Called by the disassembler before printing an instruction. */ + +void +arc_opcode_init_extract () +{ + arc_opcode_init_insert(); +} + +/* As we're extracting registers, keep an eye out for the 'f' indicator + (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, + like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. + + We must also handle auxiliary registers for lr/sr insns. They are just + constants with special names. */ + +static long +extract_reg (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods; + const struct arc_operand_value **opval; + int *invalid ATTRIBUTE_UNUSED; +{ + int regno; + long value; + enum operand op_type; + + /* Get the register number. */ + regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + + /* Is it a constant marker? */ + if (regno == ARC_REG_SHIMM) + { + op_type = OP_SHIMM; + /* always return zero if dest is a shimm mlm. */ + + if ('a' != operand->fmt) + { + value = *insn & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) + && (value & 256)) + value -= 512; + if (!flagshimm_handled_p) + flag_p = 0; + flagshimm_handled_p = 1; + } + else + { + value = 0; + } + } + else if (regno == ARC_REG_SHIMM_UPDATE) + { + op_type = OP_SHIMM; + + /* always return zero if dest is a shimm mlm. */ + + if ('a' != operand->fmt) + { + value = *insn & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + } + else + { + value = 0; + } + flag_p = 1; + flagshimm_handled_p = 1; + } + else if (regno == ARC_REG_LIMM) + { + op_type = OP_LIMM; + value = insn[1]; + limm_p = 1; + /* if this is a jump instruction (j,jl), show new pc correctly. */ + if (0x07 == ((*insn & I(-1)) >> 27)) + { + value = (value & 0xffffff); + } + } + /* It's a register, set OPVAL (that's the only way we distinguish registers + from constants here). */ + else + { + const struct arc_operand_value *reg = lookup_register (REG, regno); + op_type = OP_REG; + + if (reg == NULL) + abort (); + if (opval != NULL) + *opval = reg; + value = regno; + } + + /* If this field takes an auxiliary register, see if it's a known one. */ + if ((mods & ARC_MOD_AUXREG) + && ARC_REG_CONSTANT_P (regno)) + { + const struct arc_operand_value *reg = lookup_register (AUXREG, value); + + /* This is really a constant, but tell the caller it has a special + name. */ + if (reg != NULL && opval != NULL) + *opval = reg; + } + switch(operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn[0]& I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } + + return value; +} + +/* Return the value of the "flag update" field for shimm insns. + This value is actually stored in the register field. */ + +static long +extract_flag (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval; + int *invalid ATTRIBUTE_UNUSED; +{ + int f; + const struct arc_operand_value *val; + + if (flagshimm_handled_p) + f = flag_p != 0; + else + f = (*insn & (1 << operand->shift)) != 0; + + /* There is no text for zero values. */ + if (f == 0) + return 0; + flag_p = 1; + val = arc_opcode_lookup_suffix (operand, 1); + if (opval != NULL && val != NULL) + *opval = val; + return val->value; +} + +/* Extract the condition code (if it exists). + If we've seen a shimm value in this insn (meaning that the insn can't have + a condition code field), then we don't store anything in OPVAL and return + zero. */ + +static long +extract_cond (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval; + int *invalid ATTRIBUTE_UNUSED; +{ + long cond; + const struct arc_operand_value *val; + + if (flagshimm_handled_p) + return 0; + + cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + val = arc_opcode_lookup_suffix (operand, cond); + + /* Ignore NULL values of `val'. Several condition code values are + reserved for extensions. */ + if (opval != NULL && val != NULL) + *opval = val; + return cond; +} + +/* Extract a branch address. + We return the value as a real address (not right shifted by 2). */ + +static long +extract_reladdr (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + long addr; + + addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & ARC_OPERAND_SIGNED) + && (addr & (1 << (operand->bits - 1)))) + addr -= 1 << operand->bits; + return addr << 2; +} + +/* extract the flags bits from a j or jl long immediate. */ +static long +extract_jumpflags(insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + if (!flag_p || !limm_p) + *invalid = 1; + return ((flag_p && limm_p) + ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); +} + +/* extract st insn's offset. */ + +static long +extract_st_offset (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + int value = 0; + + if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + } + else + { + *invalid = 1; + } + return(value); +} + +/* extract ld insn's offset. */ + +static long +extract_ld_offset (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand; + int mods; + const struct arc_operand_value **opval; + int *invalid; +{ + int test = insn[0] & I(-1); + int value; + + if (test) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + return(value); + } + /* if it isn't in the insn, it's concealed behind reg 'c'. */ + return extract_reg (insn, &arc_operands[arc_operand_map['c']], + mods, opval, invalid); +} + +/* The only thing this does is set the `invalid' flag if B != C. + This is needed because the "mov" macro appears before it's real insn "and" + and we don't want the disassembler to confuse them. */ + +static long +extract_unopmacro (insn, operand, mods, opval, invalid) + arc_insn *insn; + const struct arc_operand *operand ATTRIBUTE_UNUSED; + int mods ATTRIBUTE_UNUSED; + const struct arc_operand_value **opval ATTRIBUTE_UNUSED; + int *invalid; +{ + /* This misses the case where B == ARC_REG_SHIMM_UPDATE && + C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get + printed as "and"s. */ + if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) + != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) + if (invalid != NULL) + *invalid = 1; + return 0; +} + +/* Utility for the extraction functions to return the index into + `arc_suffixes'. */ + +const struct arc_operand_value * +arc_opcode_lookup_suffix (type, value) + const struct arc_operand *type; + int value; +{ + register const struct arc_operand_value *v,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (type == &arc_operands[ext_oper->operand.type] + && value == ext_oper->operand.value) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } + + /* ??? This is a little slow and can be speeded up. */ + + for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) + if (type == &arc_operands[v->type] + && value == v->value) + return v; + return 0; +} + +static const struct arc_operand_value * +lookup_register (type, regno) + int type; + long regno; +{ + register const struct arc_operand_value *r,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (ext_oper->operand.type == type && ext_oper->operand.value == regno) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } + + if (type == REG) + return &arc_reg_names[regno]; + + /* ??? This is a little slow and can be speeded up. */ + + for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; + r < end; ++r) + if (type == r->type && regno == r->value) + return r; + return 0; +} + +int +arc_insn_is_j(insn) + arc_insn insn; +{ + return (insn & (I(-1))) == I(0x7); +} + +int +arc_insn_not_jl(insn) + arc_insn insn; +{ + return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) + != (I(0x7) | R(-1,9,1))); +} + +int +arc_operand_type(int opertype) +{ + switch (opertype) + { + case 0: + return(COND); + break; + case 1: + return(REG); + break; + case 2: + return(AUXREG); + break; + } + return -1; +} + +struct arc_operand_value * +get_ext_suffix(s) + char *s; +{ + struct arc_ext_operand_value *suffix = arc_ext_operands; + + while (suffix) + { + if ((COND == suffix->operand.type) + && !strcmp(s,suffix->operand.name)) + return(&suffix->operand); + suffix = suffix->next; + } + return NULL; +} + +int +arc_get_noshortcut_flag() +{ + return ARC_REGISTER_NOSHORT_CUT; +} diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c new file mode 100644 index 0000000..f3785f2 --- /dev/null +++ b/opcodes/arm-dis.c @@ -0,0 +1,1203 @@ +/* Instruction printing code for the ARM + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) + Modification by James G. Smith (jsmith@cygnus.co.uk) + +This file is part of libopcodes. + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 of the License, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#define DEFINE_TABLE +#include "arm-opc.h" +#include "coff/internal.h" +#include "libcoff.h" +#include "opintl.h" + +/* FIXME: This shouldn't be done here. */ +#include "elf-bfd.h" +#include "elf/internal.h" +#include "elf/arm.h" + +#ifndef streq +#define streq(a,b) (strcmp ((a), (b)) == 0) +#endif + +#ifndef strneq +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) +#endif + +#ifndef NUM_ELEM +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +#endif + +static char * arm_conditional[] = +{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; + +typedef struct +{ + const char * name; + const char * description; + const char * reg_names[16]; +} +arm_regname; + +static arm_regname regnames[] = +{ + { "raw" , "Select raw register names", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, + { "gcc", "Select register names used by GCC", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, + { "std", "Select register names used in ARM's ISA documentation", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, + { "apcs", "Select register names used in the APCS", + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, + { "atpcs", "Select register names used in the ATPCS", + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, + { "special-atpcs", "Select special register names used in the ATPCS", + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} +}; + +/* Default to GCC register name set. */ +static unsigned int regname_selected = 1; + +#define NUM_ARM_REGNAMES NUM_ELEM (regnames) +#define arm_regnames regnames[regname_selected].reg_names + +static boolean force_thumb = false; + +static char * arm_fp_const[] = +{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; + +static char * arm_shift[] = +{"lsl", "lsr", "asr", "ror"}; + +/* Forward declarations. */ +static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); +static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); +static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); +static void parse_disassembler_options PARAMS ((char *)); +static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); +int get_arm_regname_num_options (void); +int set_arm_regname_option (int option); +int get_arm_regnames (int option, const char **setname, + const char **setdescription, + const char ***register_names); + +/* Functions. */ +int +get_arm_regname_num_options () +{ + return NUM_ARM_REGNAMES; +} + +int +set_arm_regname_option (option) + int option; +{ + int old = regname_selected; + regname_selected = option; + return old; +} + +int +get_arm_regnames (option, setname, setdescription, register_names) + int option; + const char **setname; + const char **setdescription; + const char ***register_names; +{ + *setname = regnames[option].name; + *setdescription = regnames[option].description; + *register_names = regnames[option].reg_names; + return 16; +} + +static void +arm_decode_shift (given, func, stream) + long given; + fprintf_ftype func; + void * stream; +{ + func (stream, "%s", arm_regnames[given & 0xf]); + + if ((given & 0xff0) != 0) + { + if ((given & 0x10) == 0) + { + int amount = (given & 0xf80) >> 7; + int shift = (given & 0x60) >> 5; + + if (amount == 0) + { + if (shift == 3) + { + func (stream, ", rrx"); + return; + } + + amount = 32; + } + + func (stream, ", %s #%d", arm_shift[shift], amount); + } + else + func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], + arm_regnames[(given & 0xf00) >> 8]); + } +} + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (always 4 on ARM). */ + +static int +print_insn_arm (pc, info, given) + bfd_vma pc; + struct disassemble_info * info; + long given; +{ + struct arm_opcode * insn; + void * stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = arm_opcodes; insn->assembler; insn++) + { + if ((given & insn->mask) == insn->value) + { + char * c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'a': + if (((given & 0x000f0000) == 0x000f0000) + && ((given & 0x02000000) == 0)) + { + int offset = given & 0xfff; + + func (stream, "[pc"); + + if (given & 0x01000000) + { + if ((given & 0x00800000) == 0) + offset = - offset; + + /* Pre-indexed. */ + func (stream, ", #%d]", offset); + + offset += pc + 8; + + /* Cope with the possibility of write-back + being used. Probably a very dangerous thing + for the programmer to do, but who are we to + argue ? */ + if (given & 0x00200000) + func (stream, "!"); + } + else + { + /* Post indexed. */ + func (stream, "], #%d", offset); + + /* ie ignore the offset. */ + offset = pc + 8; + } + + func (stream, "\t; "); + info->print_address_func (offset, info); + } + else + { + func (stream, "[%s", + arm_regnames[(given >> 16) & 0xf]); + if ((given & 0x01000000) != 0) + { + if ((given & 0x02000000) == 0) + { + int offset = given & 0xfff; + if (offset) + func (stream, ", %s#%d", + (((given & 0x00800000) == 0) + ? "-" : ""), offset); + } + else + { + func (stream, ", %s", + (((given & 0x00800000) == 0) + ? "-" : "")); + arm_decode_shift (given, func, stream); + } + + func (stream, "]%s", + ((given & 0x00200000) != 0) ? "!" : ""); + } + else + { + if ((given & 0x02000000) == 0) + { + int offset = given & 0xfff; + if (offset) + func (stream, "], %s#%d", + (((given & 0x00800000) == 0) + ? "-" : ""), offset); + else + func (stream, "]"); + } + else + { + func (stream, "], %s", + (((given & 0x00800000) == 0) + ? "-" : "")); + arm_decode_shift (given, func, stream); + } + } + } + break; + + case 's': + if ((given & 0x004f0000) == 0x004f0000) + { + /* PC relative with immediate offset. */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + + if ((given & 0x00800000) == 0) + offset = -offset; + + func (stream, "[pc, #%d]\t; ", offset); + + (*info->print_address_func) + (offset + pc + 8, info); + } + else + { + func (stream, "[%s", + arm_regnames[(given >> 16) & 0xf]); + if ((given & 0x01000000) != 0) + { + /* Pre-indexed. */ + if ((given & 0x00400000) == 0x00400000) + { + /* Immediate. */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + if (offset) + func (stream, ", %s#%d", + (((given & 0x00800000) == 0) + ? "-" : ""), offset); + } + else + { + /* Register. */ + func (stream, ", %s%s", + (((given & 0x00800000) == 0) + ? "-" : ""), + arm_regnames[given & 0xf]); + } + + func (stream, "]%s", + ((given & 0x00200000) != 0) ? "!" : ""); + } + else + { + /* Post-indexed. */ + if ((given & 0x00400000) == 0x00400000) + { + /* Immediate. */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + if (offset) + func (stream, "], %s#%d", + (((given & 0x00800000) == 0) + ? "-" : ""), offset); + else + func (stream, "]"); + } + else + { + /* Register. */ + func (stream, "], %s%s", + (((given & 0x00800000) == 0) + ? "-" : ""), + arm_regnames[given & 0xf]); + } + } + } + break; + + case 'b': + (*info->print_address_func) + (BDISP (given) * 4 + pc + 8, info); + break; + + case 'c': + func (stream, "%s", + arm_conditional [(given >> 28) & 0xf]); + break; + + case 'm': + { + int started = 0; + int reg; + + func (stream, "{"); + for (reg = 0; reg < 16; reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + func (stream, "}"); + } + break; + + case 'o': + if ((given & 0x02000000) != 0) + { + int rotate = (given & 0xf00) >> 7; + int immed = (given & 0xff); + immed = (((immed << (32 - rotate)) + | (immed >> rotate)) & 0xffffffff); + func (stream, "#%d\t; 0x%x", immed, immed); + } + else + arm_decode_shift (given, func, stream); + break; + + case 'p': + if ((given & 0x0000f000) == 0x0000f000) + func (stream, "p"); + break; + + case 't': + if ((given & 0x01200000) == 0x00200000) + func (stream, "t"); + break; + + case 'A': + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + if ((given & 0x01000000) != 0) + { + int offset = given & 0xff; + if (offset) + func (stream, ", %s#%d]%s", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4, + ((given & 0x00200000) != 0 ? "!" : "")); + else + func (stream, "]"); + } + else + { + int offset = given & 0xff; + if (offset) + func (stream, "], %s#%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4); + else + func (stream, "]"); + } + break; + + case 'B': + /* Print ARM V5 BLX(1) address: pc+25 bits. */ + { + bfd_vma address; + bfd_vma offset = 0; + + if (given & 0x00800000) + /* Is signed, hi bits should be ones. */ + offset = (-1) ^ 0x00ffffff; + + /* Offset is (SignExtend(offset field)<<2). */ + offset += given & 0x00ffffff; + offset <<= 2; + address = offset + pc + 8; + + if (given & 0x01000000) + /* H bit allows addressing to 2-byte boundaries. */ + address += 2; + + info->print_address_func (address, info); + } + break; + + case 'I': + /* Print a Cirrus/DSP shift immediate. */ + /* Immediates are 7bit signed ints with bits 0..3 in + bits 0..3 of opcode and bits 4..6 in bits 5..7 + of opcode. */ + { + int imm; + + imm = (given & 0xf) | ((given & 0xe0) >> 1); + + /* Is ``imm'' a negative number? */ + if (imm & 0x40) + imm |= (-1 << 7); + + func (stream, "%d", imm); + } + + break; + + case 'C': + func (stream, "_"); + if (given & 0x80000) + func (stream, "f"); + if (given & 0x40000) + func (stream, "s"); + if (given & 0x20000) + func (stream, "x"); + if (given & 0x10000) + func (stream, "c"); + break; + + case 'F': + switch (given & 0x00408000) + { + case 0: + func (stream, "4"); + break; + case 0x8000: + func (stream, "1"); + break; + case 0x00400000: + func (stream, "2"); + break; + default: + func (stream, "3"); + } + break; + + case 'P': + switch (given & 0x00080080) + { + case 0: + func (stream, "s"); + break; + case 0x80: + func (stream, "d"); + break; + case 0x00080000: + func (stream, "e"); + break; + default: + func (stream, _("")); + break; + } + break; + case 'Q': + switch (given & 0x00408000) + { + case 0: + func (stream, "s"); + break; + case 0x8000: + func (stream, "d"); + break; + case 0x00400000: + func (stream, "e"); + break; + default: + func (stream, "p"); + break; + } + break; + case 'R': + switch (given & 0x60) + { + case 0: + break; + case 0x20: + func (stream, "p"); + break; + case 0x40: + func (stream, "m"); + break; + default: + func (stream, "z"); + break; + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%s", arm_regnames[reg]); + } + break; + case 'd': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%d", reg); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "0x%08x", reg); + + /* Some SWI instructions have special + meanings. */ + if ((given & 0x0fffffff) == 0x0FF00000) + func (stream, "\t; IMB"); + else if ((given & 0x0fffffff) == 0x0FF00001) + func (stream, "\t; IMBRange"); + } + break; + case 'X': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%01x", reg & 0xf); + } + break; + case 'f': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + if (reg > 7) + func (stream, "#%s", + arm_fp_const[reg & 7]); + else + func (stream, "f%d", reg); + } + break; + default: + abort (); + } + break; + + case 'y': + case 'z': + { + int single = *c == 'y'; + int regno; + + switch (bitstart) + { + case 4: /* Sm pair */ + func (stream, "{"); + /* Fall through. */ + case 0: /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; + } + break; + + case 1: /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + case 2: /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 7) & 1; + } + break; + + case 3: /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + + default: + abort (); + } + + func (stream, "%c%d", single ? 's' : 'd', regno); + + if (bitstart == 3) + { + int count = given & 0xff; + + if (single == 0) + count >>= 1; + + if (--count) + { + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); + } + + func (stream, "}"); + } + else if (bitstart == 4) + func (stream, ", %c%d}", single ? 's' : 'd', + regno + 1); + + break; + } + + case '`': + c++; + if ((given & (1 << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + case '?': + ++c; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c++); + else + func (stream, "%c", *++c); + break; + default: + abort (); + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + return 4; + } + } + abort (); +} + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ + +static int +print_insn_thumb (pc, info, given) + bfd_vma pc; + struct disassemble_info * info; + long given; +{ + struct thumb_opcode * insn; + void * stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = thumb_opcodes; insn->assembler; insn++) + { + if ((given & insn->mask) == insn->value) + { + char * c = insn->assembler; + + /* Special processing for Thumb 2 instruction BL sequence: */ + if (!*c) /* Check for empty (not NULL) assembler string. */ + { + long offset; + + info->bytes_per_chunk = 4; + info->bytes_per_line = 4; + + offset = BDISP23 (given); + offset = offset * 2 + pc + 4; + + if ((given & 0x10000000) == 0) + { + func (stream, "blx\t"); + offset &= 0xfffffffc; + } + else + func (stream, "bl\t"); + + info->print_address_func (offset, info); + return 4; + } + else + { + info->bytes_per_chunk = 2; + info->bytes_per_line = 4; + + given &= 0xffff; + + for (; *c; c++) + { + if (*c == '%') + { + int domaskpc = 0; + int domasklr = 0; + + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'S': + { + long reg; + + reg = (given >> 3) & 0x7; + if (given & (1 << 6)) + reg += 8; + + func (stream, "%s", arm_regnames[reg]); + } + break; + + case 'D': + { + long reg; + + reg = given & 0x7; + if (given & (1 << 7)) + reg += 8; + + func (stream, "%s", arm_regnames[reg]); + } + break; + + case 'T': + func (stream, "%s", + arm_conditional [(given >> 8) & 0xf]); + break; + + case 'N': + if (given & (1 << 8)) + domasklr = 1; + /* Fall through. */ + case 'O': + if (*c == 'O' && (given & (1 << 8))) + domaskpc = 1; + /* Fall through. */ + case 'M': + { + int started = 0; + int reg; + + func (stream, "{"); + + /* It would be nice if we could spot + ranges, and generate the rS-rE format: */ + for (reg = 0; (reg < 8); reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + + if (domasklr) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, arm_regnames[14] /* "lr" */); + } + + if (domaskpc) + { + if (started) + func (stream, ", "); + func (stream, arm_regnames[15] /* "pc" */); + } + + func (stream, "}"); + } + break; + + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + switch (*c) + { + case 'r': + func (stream, "%s", arm_regnames[reg]); + break; + + case 'd': + func (stream, "%d", reg); + break; + + case 'H': + func (stream, "%d", reg << 1); + break; + + case 'W': + func (stream, "%d", reg << 2); + break; + + case 'a': + /* PC-relative address -- the bottom two + bits of the address are dropped + before the calculation. */ + info->print_address_func + (((pc + 4) & ~3) + (reg << 2), info); + break; + + case 'x': + func (stream, "0x%04x", reg); + break; + + case 'I': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + func (stream, "%d", reg); + break; + + case 'B': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + (*info->print_address_func) + (reg * 2 + pc + 4, info); + break; + + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + + case '?': + ++c; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c++); + else + func (stream, "%c", *++c); + break; + + default: + abort (); + } + } + break; + + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + } + return 2; + } + } + + /* No match. */ + abort (); +} + +/* Parse an individual disassembler option. */ + +void +parse_arm_disassembler_option (option) + char * option; +{ + if (option == NULL) + return; + + if (strneq (option, "reg-names-", 10)) + { + int i; + + option += 10; + + for (i = NUM_ARM_REGNAMES; i--;) + if (streq (option, regnames[i].name)) + { + regname_selected = i; + break; + } + + if (i < 0) + fprintf (stderr, _("Unrecognised register name set: %s\n"), option); + } + else if (streq (option, "force-thumb")) + force_thumb = 1; + else if (streq (option, "no-force-thumb")) + force_thumb = 0; + else + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); + + return; +} + +/* Parse the string of disassembler options, spliting it at whitespaces. */ + +static void +parse_disassembler_options (options) + char * options; +{ + char * space; + + if (options == NULL) + return; + + do + { + space = strchr (options, ' '); + + if (space) + { + * space = '\0'; + parse_arm_disassembler_option (options); + * space = ' '; + options = space + 1; + } + else + parse_arm_disassembler_option (options); + } + while (space); +} + +/* NOTE: There are no checks in these routines that + the relevant number of data bytes exist. */ + +static int +print_insn (pc, info, little) + bfd_vma pc; + struct disassemble_info * info; + boolean little; +{ + unsigned char b[4]; + long given; + int status; + int is_thumb; + + if (info->disassembler_options) + { + parse_disassembler_options (info->disassembler_options); + + /* To avoid repeated parsing of these options, we remove them here. */ + info->disassembler_options = NULL; + } + + is_thumb = force_thumb; + + if (!is_thumb && info->symbols != NULL) + { + if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) + { + coff_symbol_type * cs; + + cs = coffsymbol (*info->symbols); + is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT + || cs->native->u.syment.n_sclass == C_THUMBSTAT + || cs->native->u.syment.n_sclass == C_THUMBLABEL + || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC + || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); + } + else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) + { + elf_symbol_type * es; + unsigned int type; + + es = *(elf_symbol_type **)(info->symbols); + type = ELF_ST_TYPE (es->internal_elf_sym.st_info); + + is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); + } + } + + info->bytes_per_chunk = 4; + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + + if (little) + { + status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); + if (status != 0 && is_thumb) + { + info->bytes_per_chunk = 2; + + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + } + + if (status != 0) + { + info->memory_error_func (status, pc, info); + return -1; + } + + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + } + else + { + status = info->read_memory_func + (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); + if (status != 0) + { + info->memory_error_func (status, pc, info); + return -1; + } + + if (is_thumb) + { + if (pc & 0x2) + { + given = (b[2] << 8) | b[3]; + + status = info->read_memory_func + ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); + if (status != 0) + { + info->memory_error_func (status, pc + 4, info); + return -1; + } + + given |= (b[0] << 24) | (b[1] << 16); + } + else + given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); + } + else + given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); + } + + if (info->flags & INSN_HAS_RELOC) + /* If the instruction has a reloc associated with it, then + the offset field in the instruction will actually be the + addend for the reloc. (We are using REL type relocs). + In such cases, we can ignore the pc when computing + addresses, since the addend is not currently pc-relative. */ + pc = 0; + + if (is_thumb) + status = print_insn_thumb (pc, info, given); + else + status = print_insn_arm (pc, info, given); + + return status; +} + +int +print_insn_big_arm (pc, info) + bfd_vma pc; + struct disassemble_info * info; +{ + return print_insn (pc, info, false); +} + +int +print_insn_little_arm (pc, info) + bfd_vma pc; + struct disassemble_info * info; +{ + return print_insn (pc, info, true); +} + +void +print_arm_disassembler_options (FILE * stream) +{ + int i; + + fprintf (stream, _("\n\ +The following ARM specific disassembler options are supported for use with\n\ +the -M switch:\n")); + + for (i = NUM_ARM_REGNAMES; i--;) + fprintf (stream, " reg-names-%s %*c%s\n", + regnames[i].name, + (int)(14 - strlen (regnames[i].name)), ' ', + regnames[i].description); + + fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); + fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); +} diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h new file mode 100644 index 0000000..85f611d --- /dev/null +++ b/opcodes/arm-opc.h @@ -0,0 +1,518 @@ +/* Opcode table for the ARM. + + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +struct arm_opcode { + unsigned long value, mask; /* recognise instruction if (op&mask)==value */ + char *assembler; /* how to disassemble this instruction */ +}; + +struct thumb_opcode +{ + unsigned short value, mask; /* recognise instruction if (op&mask)==value */ + char * assembler; /* how to disassemble this instruction */ +}; + +/* format of the assembler string : + + %% % + %d print the bitfield in decimal + %x print the bitfield in hex + %X print the bitfield as 1 hex digit without leading "0x" + %r print as an ARM register + %f print a floating point constant if >7 else a + floating point register + %y print a single precision VFP reg. + Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair + %z print a double precision VFP reg + Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list + %c print condition code (always bits 28-31) + %P print floating point precision in arithmetic insn + %Q print floating point precision in ldf/stf insn + %R print floating point rounding mode + %'c print specified char iff bit is one + %`c print specified char iff bit is zero + %?ab print a if bit is one else print b + %p print 'p' iff bits 12-15 are 15 + %t print 't' iff bit 21 set and bit 24 clear + %o print operand2 (immediate or register + shift) + %a print address for ldr/str instruction + %s print address for ldr/str halfword/signextend instruction + %b print branch destination + %B print arm BLX(1) destination + %A print address for ldc/stc/ldf/stf instruction + %m print register mask for ldm/stm instruction + %C print the PSR sub type. + %F print the COUNT field of a LFM/SFM instruction. +Thumb specific format options: + %D print Thumb register (bits 0..2 as high number if bit 7 set) + %S print Thumb register (bits 3..5 as high number if bit 6 set) + %I print bitfield as a signed decimal + (top bit of range being the sign bit) + %M print Thumb register mask + %N print Thumb register mask (with LR) + %O print Thumb register mask (with PC) + %T print Thumb condition code (always bits 8-11) + %I print cirrus signed shift immediate: bits 0..3|4..6 + %B print Thumb branch destination (signed displacement) + %W print (bitfield * 4) as a decimal + %H print (bitfield * 2) as a decimal + %a print (bitfield * 4) as a pc-rel offset + decoded symbol +*/ + +/* Note: There is a partial ordering in this table - it must be searched from + the top to obtain a correct match. */ + +static struct arm_opcode arm_opcodes[] = +{ + /* ARM instructions. */ + {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, + {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, + {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, + {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, + {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + + /* V5J instruction. */ + {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, + + /* XScale instructions. */ + {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, + {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, + {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, + {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, + {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, + {0xf450f000, 0xfc70f000, "pld\t%a"}, + + /* V5 Instructions. */ + {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {0xfa000000, 0xfe000000, "blx\t%B"}, + {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, + {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, + {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, + {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, + {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + + /* V5E "El Segundo" Instructions. */ + {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, + {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, + {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + + {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + + {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + + {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, + {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, + {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, + {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, + + {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, + {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, + + {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, + {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, + {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, + {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, + + {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + + /* ARM Instructions. */ + {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, + {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, + {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, + {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, + {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, + {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, + {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, + {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, + {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, + {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, + {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, + {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, + {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, + {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, + {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, + {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, + {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, + {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, + {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, + {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, + {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, + {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, + {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, + {0x06000010, 0x0e000010, "undefined"}, + {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, + {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, + {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, + {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, + {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, + + /* Floating point coprocessor (FPA) instructions */ + {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, + {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, + {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, + {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, + {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, + {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, + {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, + {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, + {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, + {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, + {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, + {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, + {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, + {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, + {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, + {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, + {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, + {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, + {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, + {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, + {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, + {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, + {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, + {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, + {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, + {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, + {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, + {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, + {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, + {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + + /* Floating point coprocessor (VFP) instructions */ + {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, + {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, + {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, + {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"}, + {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, + {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, + {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, + {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"}, + {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"}, + {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"}, + {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"}, + {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"}, + {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"}, + {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"}, + {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"}, + {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"}, + {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"}, + {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"}, + {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"}, + {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"}, + {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"}, + {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"}, + {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"}, + {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"}, + {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"}, + {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"}, + {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"}, + {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"}, + {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"}, + {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"}, + {0x0ef1fa10, 0x0fffffff, "fmstat%c"}, + {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, + {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, + {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, + {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, + {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, + {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, "}, + {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"}, + {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"}, + {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"}, + {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"}, + {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"}, + {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"}, + {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, + {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, + {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, + {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, + {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, + {0x0ee00a10, 0x0ff00fff, "fmxr%c\t, %12-15r"}, + {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"}, + {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"}, + {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"}, + {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"}, + {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"}, + {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"}, + {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"}, + {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"}, + {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"}, + {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"}, + {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"}, + {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"}, + {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"}, + {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"}, + {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"}, + {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"}, + {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"}, + {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"}, + {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"}, + {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"}, + {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"}, + {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"}, + {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"}, + {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"}, + + /* Cirrus coprocessor instructions. */ + {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, + {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, + {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, + {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, + {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, + {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, + {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, + {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, + {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, + {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, + {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"}, + {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"}, + {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"}, + {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"}, + {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, + {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, + {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, + {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, + {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, + {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, + {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, + {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, + {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, + {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, + {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, + {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, + {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, + {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, + {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, + {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, + {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, + {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, + {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, + {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, + {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, + {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, + {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, + {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, + {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, + {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, + {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, + {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, + {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + + /* Generic coprocessor instructions */ + {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, + {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, + + /* The rest. */ + {0x00000000, 0x00000000, "undefined instruction %0-31x"}, + {0x00000000, 0x00000000, 0} +}; + +#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ + +static struct thumb_opcode thumb_opcodes[] = +{ + /* Thumb instructions. */ + + /* ARM V5 ISA extends Thumb. */ + {0xbe00, 0xff00, "bkpt\t%0-7x"}, + {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ + /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb() + as an extension of the special processing there for Thumb BL. + BL and BLX(1) involve 2 successive 16-bit instructions, which must + always appear together in the correct order. So, the empty + string is put in this table, and the string interpreter takes + to mean it has a pair of BL-ish instructions. */ + {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, + /* Format 5 instructions do not update the PSR. */ + {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, + /* Format 4. */ + {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, + {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, + {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, + {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, + {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, + {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, + {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, + {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, + {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, + {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, + {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, + {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, + {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, + {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, + {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, + {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, + /* format 13 */ + {0xB000, 0xFF80, "add\tsp, #%0-6W"}, + {0xB080, 0xFF80, "sub\tsp, #%0-6W"}, + /* format 5 */ + {0x4700, 0xFF80, "bx\t%S"}, + {0x4400, 0xFF00, "add\t%D, %S"}, + {0x4500, 0xFF00, "cmp\t%D, %S"}, + {0x4600, 0xFF00, "mov\t%D, %S"}, + /* format 14 */ + {0xB400, 0xFE00, "push\t%N"}, + {0xBC00, 0xFE00, "pop\t%O"}, + /* format 2 */ + {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, + {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, + {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, + {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, + /* format 8 */ + {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, + {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, + {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"}, + /* format 7 */ + {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, + {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, + /* format 1 */ + {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, + {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, + {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, + /* format 3 */ + {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, + {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, + {0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, + {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, + /* format 6 */ + {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=" */ + /* format 9 */ + {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, + {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, + {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, + {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, + /* format 10 */ + {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, + {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, + /* format 11 */ + {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, + {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, + /* format 12 */ + {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, + {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, + /* format 15 */ + {0xC000, 0xF800, "stmia\t%8-10r!,%M"}, + {0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, + /* format 18 */ + {0xE000, 0xF800, "b\t%0-10B"}, + {0xE800, 0xF800, "undefined"}, + /* format 19 */ + {0xF000, 0xF800, ""}, /* special processing required in disassembler */ + {0xF800, 0xF800, "second half of BL instruction %0-15x"}, + /* format 16 */ + {0xD000, 0xFF00, "beq\t%0-7B"}, + {0xD100, 0xFF00, "bne\t%0-7B"}, + {0xD200, 0xFF00, "bcs\t%0-7B"}, + {0xD300, 0xFF00, "bcc\t%0-7B"}, + {0xD400, 0xFF00, "bmi\t%0-7B"}, + {0xD500, 0xFF00, "bpl\t%0-7B"}, + {0xD600, 0xFF00, "bvs\t%0-7B"}, + {0xD700, 0xFF00, "bvc\t%0-7B"}, + {0xD800, 0xFF00, "bhi\t%0-7B"}, + {0xD900, 0xFF00, "bls\t%0-7B"}, + {0xDA00, 0xFF00, "bge\t%0-7B"}, + {0xDB00, 0xFF00, "blt\t%0-7B"}, + {0xDC00, 0xFF00, "bgt\t%0-7B"}, + {0xDD00, 0xFF00, "ble\t%0-7B"}, + /* format 17 */ + {0xDE00, 0xFF00, "bal\t%0-7B"}, + {0xDF00, 0xFF00, "swi\t%0-7d"}, + /* format 9 */ + {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, + {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, + {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, + {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, + /* the rest */ + {0x0000, 0x0000, "undefined instruction %0-15x"}, + {0x0000, 0x0000, 0} +}; + +#define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \ + ^ 0x200000) - 0x200000) /* 23bit */ + diff --git a/opcodes/avr-dis.c b/opcodes/avr-dis.c new file mode 100644 index 0000000..4598cab --- /dev/null +++ b/opcodes/avr-dis.c @@ -0,0 +1,359 @@ +/* Disassemble AVR instructions. + Copyright 1999, 2000 Free Software Foundation, Inc. + + Contributed by Denis Chertykov + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opintl.h" + + +struct avr_opcodes_s +{ + char *name; + char *constraints; + char *opcode; + int insn_size; /* in words */ + int isa; + unsigned int bin_opcode; + unsigned int bin_mask; +}; + +#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ +{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0}, + +struct avr_opcodes_s avr_opcodes[] = +{ + #include "opcode/avr.h" + {NULL, NULL, NULL, 0, 0, 0, 0} +}; + +static int avr_operand PARAMS ((unsigned int, unsigned int, + unsigned int, int, char *, char *, int)); + +static int +avr_operand (insn, insn2, pc, constraint, buf, comment, regs) + unsigned int insn; + unsigned int insn2; + unsigned int pc; + int constraint; + char *buf; + char *comment; + int regs; +{ + int ok = 1; + + switch (constraint) + { + /* Any register operand. */ + case 'r': + if (regs) + insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */ + else + insn = (insn & 0x01f0) >> 4; /* destination register */ + + sprintf (buf, "r%d", insn); + break; + + case 'd': + if (regs) + sprintf (buf, "r%d", 16 + (insn & 0xf)); + else + sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4)); + break; + + case 'w': + sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3)); + break; + + case 'a': + if (regs) + sprintf (buf, "r%d", 16 + (insn & 7)); + else + sprintf (buf, "r%d", 16 + ((insn >> 4) & 7)); + break; + + case 'v': + if (regs) + sprintf (buf, "r%d", (insn & 0xf) * 2); + else + sprintf (buf, "r%d", ((insn & 0xf0) >> 3)); + break; + + case 'e': + { + char *xyz; + + switch (insn & 0x100f) + { + case 0x0000: xyz = "Z"; break; + case 0x1001: xyz = "Z+"; break; + case 0x1002: xyz = "-Z"; break; + case 0x0008: xyz = "Y"; break; + case 0x1009: xyz = "Y+"; break; + case 0x100a: xyz = "-Y"; break; + case 0x100c: xyz = "X"; break; + case 0x100d: xyz = "X+"; break; + case 0x100e: xyz = "-X"; break; + default: xyz = "??"; ok = 0; + } + sprintf (buf, xyz); + + if (AVR_UNDEF_P (insn)) + sprintf (comment, _("undefined")); + } + break; + + case 'z': + *buf++ = 'Z'; + if (insn & 0x1) + *buf++ = '+'; + *buf = '\0'; + if (AVR_UNDEF_P (insn)) + sprintf (comment, _("undefined")); + break; + + case 'b': + { + unsigned int x; + + x = (insn & 7); + x |= (insn >> 7) & (3 << 3); + x |= (insn >> 8) & (1 << 5); + + if (insn & 0x8) + *buf++ = 'Y'; + else + *buf++ = 'Z'; + sprintf (buf, "+%d", x); + sprintf (comment, "0x%02x", x); + } + break; + + case 'h': + sprintf (buf, "0x%x", + ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2); + break; + + case 'L': + { + int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2; + sprintf (buf, ".%+-8d", rel_addr); + sprintf (comment, "0x%x", pc + 2 + rel_addr); + } + break; + + case 'l': + { + int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2; + sprintf (buf, ".%+-8d", rel_addr); + sprintf (comment, "0x%x", pc + 2 + rel_addr); + } + break; + + case 'i': + sprintf (buf, "0x%04X", insn2); + break; + + case 'M': + sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf)); + sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf)); + break; + + case 'n': + sprintf (buf, "??"); + fprintf (stderr, _("Internal disassembler error")); + ok = 0; + break; + + case 'K': + { + unsigned int x; + + x = (insn & 0xf) | ((insn >> 2) & 0x30); + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 's': + sprintf (buf, "%d", insn & 7); + break; + + case 'S': + sprintf (buf, "%d", (insn >> 4) & 7); + break; + + case 'P': + { + unsigned int x; + x = (insn & 0xf); + x |= (insn >> 5) & 0x30; + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 'p': + { + unsigned int x; + + x = (insn >> 3) & 0x1f; + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case '?': + *buf = '\0'; + break; + + default: + sprintf (buf, "??"); + fprintf (stderr, _("unknown constraint `%c'"), constraint); + ok = 0; + } + + return ok; +} + +static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *)); + +static unsigned short +avrdis_opcode (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + bfd_byte buffer[2]; + int status; + status = info->read_memory_func(addr, buffer, 2, info); + if (status != 0) + { + info->memory_error_func(status, addr, info); + return -1; + } + return bfd_getl16 (buffer); +} + + +int +print_insn_avr(addr, info) + bfd_vma addr; + disassemble_info *info; +{ + unsigned int insn, insn2; + struct avr_opcodes_s *opcode; + void *stream = info->stream; + fprintf_ftype prin = info->fprintf_func; + static int initialized; + int cmd_len = 2; + int ok = 0; + char op1[20], op2[20], comment1[40], comment2[40]; + + if (!initialized) + { + initialized = 1; + + for (opcode = avr_opcodes; opcode->name; opcode++) + { + char * s; + unsigned int bin = 0; + unsigned int mask = 0; + + for (s = opcode->opcode; *s; ++s) + { + bin <<= 1; + mask <<= 1; + bin |= (*s == '1'); + mask |= (*s == '1' || *s == '0'); + } + assert (s - opcode->opcode == 16); + assert (opcode->bin_opcode == bin); + opcode->bin_mask = mask; + } + } + + insn = avrdis_opcode (addr, info); + + for (opcode = avr_opcodes; opcode->name; opcode++) + { + if ((insn & opcode->bin_mask) == opcode->bin_opcode) + break; + } + + /* Special case: disassemble `ldd r,b+0' as `ld r,b', and + `std b+0,r' as `st b,r' (next entry in the table). */ + + if (AVR_DISP0_P (insn)) + opcode++; + + op1[0] = 0; + op2[0] = 0; + comment1[0] = 0; + comment2[0] = 0; + + if (opcode->name) + { + char *op = opcode->constraints; + + insn2 = 0; + ok = 1; + + if (opcode->insn_size > 1) + { + insn2 = avrdis_opcode (addr + 2, info); + cmd_len = 4; + } + + if (*op && *op != '?') + { + int regs = REGISTER_P (*op); + + ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0); + + if (ok && *(++op) == ',') + ok = avr_operand (insn, insn2, addr, *(++op), op2, + *comment1 ? comment2 : comment1, regs); + } + } + + if (!ok) + { + /* Unknown opcode, or invalid combination of operands. */ + sprintf (op1, "0x%04x", insn); + op2[0] = 0; + sprintf (comment1, "????"); + comment2[0] = 0; + } + + (*prin) (stream, "%s", ok ? opcode->name : ".word"); + + if (*op1) + (*prin) (stream, "\t%s", op1); + + if (*op2) + (*prin) (stream, ", %s", op2); + + if (*comment1) + (*prin) (stream, "\t; %s", comment1); + + if (*comment2) + (*prin) (stream, " %s", comment2); + + return cmd_len; +} diff --git a/opcodes/cgen-asm.c b/opcodes/cgen-asm.c new file mode 100644 index 0000000..05b62bf --- /dev/null +++ b/opcodes/cgen-asm.c @@ -0,0 +1,373 @@ +/* CGEN generic assembler support code. + + Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "bfd.h" +#include "symcat.h" +#include "opcode/cgen.h" +#include "opintl.h" + +static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static void build_asm_hash_table PARAMS ((CGEN_CPU_DESC)); + +/* Set the cgen_parse_operand_fn callback. */ + +void +cgen_set_parse_operand_fn (cd, fn) + CGEN_CPU_DESC cd; + cgen_parse_operand_fn fn; +{ + cd->parse_operand_fn = fn; +} + +/* Called whenever starting to parse an insn. */ + +void +cgen_init_parse_operand (cd) + CGEN_CPU_DESC cd; +{ + /* This tells the callback to re-initialize. */ + (void) (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, NULL, NULL); +} + +/* Subroutine of build_asm_hash_table to add INSNS to the hash table. + + COUNT is the number of elements in INSNS. + ENTSIZE is sizeof (CGEN_IBASE) for the target. + ??? No longer used but leave in for now. + HTABLE points to the hash table. + HENTBUF is a pointer to sufficiently large buffer of hash entries. + The result is a pointer to the next entry to use. + + The table is scanned backwards as additions are made to the front of the + list and we want earlier ones to be prefered. */ + +static CGEN_INSN_LIST * +hash_insn_array (cd, insns, count, entsize, htable, hentbuf) + CGEN_CPU_DESC cd; + const CGEN_INSN *insns; + int count; + int entsize ATTRIBUTE_UNUSED; + CGEN_INSN_LIST **htable; + CGEN_INSN_LIST *hentbuf; +{ + int i; + + for (i = count - 1; i >= 0; --i, ++hentbuf) + { + unsigned int hash; + const CGEN_INSN *insn = &insns[i]; + + if (! (* cd->asm_hash_p) (insn)) + continue; + hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (insn)); + hentbuf->next = htable[hash]; + hentbuf->insn = insn; + htable[hash] = hentbuf; + } + + return hentbuf; +} + +/* Subroutine of build_asm_hash_table to add INSNS to the hash table. + This function is identical to hash_insn_array except the insns are + in a list. */ + +static CGEN_INSN_LIST * +hash_insn_list (cd, insns, htable, hentbuf) + CGEN_CPU_DESC cd; + const CGEN_INSN_LIST *insns; + CGEN_INSN_LIST **htable; + CGEN_INSN_LIST *hentbuf; +{ + const CGEN_INSN_LIST *ilist; + + for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) + { + unsigned int hash; + + if (! (* cd->asm_hash_p) (ilist->insn)) + continue; + hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (ilist->insn)); + hentbuf->next = htable[hash]; + hentbuf->insn = ilist->insn; + htable[hash] = hentbuf; + } + + return hentbuf; +} + +/* Build the assembler instruction hash table. */ + +static void +build_asm_hash_table (cd) + CGEN_CPU_DESC cd; +{ + int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); + CGEN_INSN_TABLE *insn_table = &cd->insn_table; + CGEN_INSN_TABLE *macro_insn_table = &cd->macro_insn_table; + unsigned int hash_size = cd->asm_hash_size; + CGEN_INSN_LIST *hash_entry_buf; + CGEN_INSN_LIST **asm_hash_table; + CGEN_INSN_LIST *asm_hash_table_entries; + + /* The space allocated for the hash table consists of two parts: + the hash table and the hash lists. */ + + asm_hash_table = (CGEN_INSN_LIST **) + xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); + memset (asm_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); + asm_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) + xmalloc (count * sizeof (CGEN_INSN_LIST)); + + /* Add compiled in insns. + Don't include the first one as it is a reserved entry. */ + /* ??? It was the end of all hash chains, and also the special + "invalid insn" marker. May be able to do it differently now. */ + + hash_entry_buf = hash_insn_array (cd, + insn_table->init_entries + 1, + insn_table->num_init_entries - 1, + insn_table->entry_size, + asm_hash_table, hash_entry_buf); + + /* Add compiled in macro-insns. */ + + hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, + macro_insn_table->num_init_entries, + macro_insn_table->entry_size, + asm_hash_table, hash_entry_buf); + + /* Add runtime added insns. + Later added insns will be prefered over earlier ones. */ + + hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, + asm_hash_table, hash_entry_buf); + + /* Add runtime added macro-insns. */ + + hash_insn_list (cd, macro_insn_table->new_entries, + asm_hash_table, hash_entry_buf); + + cd->asm_hash_table = asm_hash_table; + cd->asm_hash_table_entries = asm_hash_table_entries; +} + +/* Return the first entry in the hash list for INSN. */ + +CGEN_INSN_LIST * +cgen_asm_lookup_insn (cd, insn) + CGEN_CPU_DESC cd; + const char *insn; +{ + unsigned int hash; + + if (cd->asm_hash_table == NULL) + build_asm_hash_table (cd); + + hash = (* cd->asm_hash) (insn); + return cd->asm_hash_table[hash]; +} + +/* Keyword parser. + The result is NULL upon success or an error message. + If successful, *STRP is updated to point passed the keyword. + + ??? At present we have a static notion of how to pick out a keyword. + Later we can allow a target to customize this if necessary [say by + recording something in the keyword table]. */ + +const char * +cgen_parse_keyword (cd, strp, keyword_table, valuep) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + const char **strp; + CGEN_KEYWORD *keyword_table; + long *valuep; +{ + const CGEN_KEYWORD_ENTRY *ke; + char buf[256]; + const char *p,*start; + + if (keyword_table->name_hash_table == NULL) + (void) cgen_keyword_search_init (keyword_table, NULL); + + p = start = *strp; + + /* Allow any first character. This is to make life easier for + the fairly common case of suffixes, eg. 'ld.b.w', where the first + character of the suffix ('.') is special. */ + if (*p) + ++p; + + /* Allow letters, digits, and any special characters. */ + while (((p - start) < (int) sizeof (buf)) + && *p + && (ISALNUM (*p) || strchr (keyword_table->nonalpha_chars, *p))) + ++p; + + if (p - start >= (int) sizeof (buf)) + { + /* All non-empty CGEN keywords can fit into BUF. The only thing + we can match here is the empty keyword. */ + buf[0] = 0; + } + else + { + memcpy (buf, start, p - start); + buf[p - start] = 0; + } + + ke = cgen_keyword_lookup_name (keyword_table, buf); + + if (ke != NULL) + { + *valuep = ke->value; + /* Don't advance pointer if we recognized the null keyword. */ + if (ke->name[0] != 0) + *strp = p; + return NULL; + } + + return "unrecognized keyword/register name"; +} + +/* Parse a small signed integer parser. + ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. + Note that if the caller expects a bfd_vma result, it should call + cgen_parse_address. */ + +const char * +cgen_parse_signed_integer (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + bfd_vma value; + enum cgen_parse_operand_result result; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, + &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + *valuep = value; + return errmsg; +} + +/* Parse a small unsigned integer parser. + ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. + Note that if the caller expects a bfd_vma result, it should call + cgen_parse_address. */ + +const char * +cgen_parse_unsigned_integer (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + bfd_vma value; + enum cgen_parse_operand_result result; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, + &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + *valuep = value; + return errmsg; +} + +/* Address parser. */ + +const char * +cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + int opinfo; + enum cgen_parse_operand_result *resultp; + bfd_vma *valuep; +{ + bfd_vma value; + enum cgen_parse_operand_result result_type; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_ADDRESS, strp, opindex, opinfo, + &result_type, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + { + if (resultp != NULL) + *resultp = result_type; + *valuep = value; + } + return errmsg; +} + +/* Signed integer validation routine. */ + +const char * +cgen_validate_signed_integer (value, min, max) + long value, min, max; +{ + if (value < min || value > max) + { + static char buf[100]; + + /* xgettext:c-format */ + sprintf (buf, _("operand out of range (%ld not between %ld and %ld)"), + value, min, max); + return buf; + } + + return NULL; +} + +/* Unsigned integer validation routine. + Supplying `min' here may seem unnecessary, but we also want to handle + cases where min != 0 (and max > LONG_MAX). */ + +const char * +cgen_validate_unsigned_integer (value, min, max) + unsigned long value, min, max; +{ + if (value < min || value > max) + { + static char buf[100]; + + /* xgettext:c-format */ + sprintf (buf, _("operand out of range (%lu not between %lu and %lu)"), + value, min, max); + return buf; + } + + return NULL; +} diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in new file mode 100644 index 0000000..525177c --- /dev/null +++ b/opcodes/cgen-asm.in @@ -0,0 +1,455 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by @arch@_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +@arch@_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +@arch@_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! @arch@_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +@arch@_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! @arch@_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c new file mode 100644 index 0000000..881ee14 --- /dev/null +++ b/opcodes/cgen-dis.c @@ -0,0 +1,249 @@ +/* CGEN generic disassembler support code. + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "symcat.h" +#include "opcode/cgen.h" + +static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static void build_dis_hash_table PARAMS ((CGEN_CPU_DESC)); +static int count_decodable_bits PARAMS ((const CGEN_INSN *)); +static void add_insn_to_hash_chain PARAMS ((CGEN_INSN_LIST *, + const CGEN_INSN *, + CGEN_INSN_LIST **, + unsigned int)); + +/* Return the number of decodable bits in this insn. */ +static int +count_decodable_bits (insn) + const CGEN_INSN *insn; +{ + unsigned mask = CGEN_INSN_BASE_MASK (insn); + int bits = 0; + int m; + for (m = 1; m != 0; m <<= 1) + { + if (mask & m) + ++bits; + } + return bits; +} + +/* Add an instruction to the hash chain. */ +static void +add_insn_to_hash_chain (hentbuf, insn, htable, hash) + CGEN_INSN_LIST *hentbuf; + const CGEN_INSN *insn; + CGEN_INSN_LIST **htable; + unsigned int hash; +{ + CGEN_INSN_LIST *current_buf; + CGEN_INSN_LIST *previous_buf; + int insn_decodable_bits; + + /* Add insns sorted by the number of decodable bits, in decreasing order. + This ensures that any insn which is a special case of another will be + checked first. */ + insn_decodable_bits = count_decodable_bits (insn); + previous_buf = NULL; + for (current_buf = htable[hash]; current_buf != NULL; + current_buf = current_buf->next) + { + int current_decodable_bits = count_decodable_bits (current_buf->insn); + if (insn_decodable_bits >= current_decodable_bits) + break; + previous_buf = current_buf; + } + + /* Now insert the new insn. */ + hentbuf->insn = insn; + hentbuf->next = current_buf; + if (previous_buf == NULL) + htable[hash] = hentbuf; + else + previous_buf->next = hentbuf; +} + +/* Subroutine of build_dis_hash_table to add INSNS to the hash table. + + COUNT is the number of elements in INSNS. + ENTSIZE is sizeof (CGEN_IBASE) for the target. + ??? No longer used but leave in for now. + HTABLE points to the hash table. + HENTBUF is a pointer to sufficiently large buffer of hash entries. + The result is a pointer to the next entry to use. + + The table is scanned backwards as additions are made to the front of the + list and we want earlier ones to be prefered. */ + +static CGEN_INSN_LIST * +hash_insn_array (cd, insns, count, entsize, htable, hentbuf) + CGEN_CPU_DESC cd; + const CGEN_INSN * insns; + int count; + int entsize ATTRIBUTE_UNUSED; + CGEN_INSN_LIST ** htable; + CGEN_INSN_LIST * hentbuf; +{ + int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; + int i; + + for (i = count - 1; i >= 0; --i, ++hentbuf) + { + unsigned int hash; + char buf [4]; + unsigned long value; + const CGEN_INSN *insn = &insns[i]; + + if (! (* cd->dis_hash_p) (insn)) + continue; + + /* We don't know whether the target uses the buffer or the base insn + to hash on, so set both up. */ + + value = CGEN_INSN_BASE_VALUE (insn); + bfd_put_bits ((bfd_vma) value, + buf, + CGEN_INSN_MASK_BITSIZE (insn), + big_p); + hash = (* cd->dis_hash) (buf, value); + add_insn_to_hash_chain (hentbuf, insn, htable, hash); + } + + return hentbuf; +} + +/* Subroutine of build_dis_hash_table to add INSNS to the hash table. + This function is identical to hash_insn_array except the insns are + in a list. */ + +static CGEN_INSN_LIST * +hash_insn_list (cd, insns, htable, hentbuf) + CGEN_CPU_DESC cd; + const CGEN_INSN_LIST *insns; + CGEN_INSN_LIST **htable; + CGEN_INSN_LIST *hentbuf; +{ + int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; + const CGEN_INSN_LIST *ilist; + + for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) + { + unsigned int hash; + char buf[4]; + unsigned long value; + + if (! (* cd->dis_hash_p) (ilist->insn)) + continue; + + /* We don't know whether the target uses the buffer or the base insn + to hash on, so set both up. */ + + value = CGEN_INSN_BASE_VALUE (ilist->insn); + bfd_put_bits((bfd_vma) value, + buf, + CGEN_INSN_MASK_BITSIZE (ilist->insn), + big_p); + hash = (* cd->dis_hash) (buf, value); + add_insn_to_hash_chain (hentbuf, ilist->insn, htable, hash); + } + + return hentbuf; +} + +/* Build the disassembler instruction hash table. */ + +static void +build_dis_hash_table (cd) + CGEN_CPU_DESC cd; +{ + int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); + CGEN_INSN_TABLE *insn_table = & cd->insn_table; + CGEN_INSN_TABLE *macro_insn_table = & cd->macro_insn_table; + unsigned int hash_size = cd->dis_hash_size; + CGEN_INSN_LIST *hash_entry_buf; + CGEN_INSN_LIST **dis_hash_table; + CGEN_INSN_LIST *dis_hash_table_entries; + + /* The space allocated for the hash table consists of two parts: + the hash table and the hash lists. */ + + dis_hash_table = (CGEN_INSN_LIST **) + xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); + memset (dis_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); + dis_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) + xmalloc (count * sizeof (CGEN_INSN_LIST)); + + /* Add compiled in insns. + Don't include the first one as it is a reserved entry. */ + /* ??? It was the end of all hash chains, and also the special + "invalid insn" marker. May be able to do it differently now. */ + + hash_entry_buf = hash_insn_array (cd, + insn_table->init_entries + 1, + insn_table->num_init_entries - 1, + insn_table->entry_size, + dis_hash_table, hash_entry_buf); + + /* Add compiled in macro-insns. */ + + hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, + macro_insn_table->num_init_entries, + macro_insn_table->entry_size, + dis_hash_table, hash_entry_buf); + + /* Add runtime added insns. + Later added insns will be prefered over earlier ones. */ + + hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, + dis_hash_table, hash_entry_buf); + + /* Add runtime added macro-insns. */ + + hash_insn_list (cd, macro_insn_table->new_entries, + dis_hash_table, hash_entry_buf); + + cd->dis_hash_table = dis_hash_table; + cd->dis_hash_table_entries = dis_hash_table_entries; +} + +/* Return the first entry in the hash list for INSN. */ + +CGEN_INSN_LIST * +cgen_dis_lookup_insn (cd, buf, value) + CGEN_CPU_DESC cd; + const char * buf; + CGEN_INSN_INT value; +{ + unsigned int hash; + + if (cd->dis_hash_table == NULL) + build_dis_hash_table (cd); + + hash = (* cd->dis_hash) (buf, value); + + return cd->dis_hash_table[hash]; +} diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in new file mode 100644 index 0000000..7c59340 --- /dev/null +++ b/opcodes/cgen-dis.in @@ -0,0 +1,466 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + @arch@_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! @arch@_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_@arch@ (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_@arch@ +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + @arch@_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in new file mode 100644 index 0000000..d2bfd02 --- /dev/null +++ b/opcodes/cgen-ibld.in @@ -0,0 +1,540 @@ +/* Instruction building/extraction support for @arch@. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c new file mode 100644 index 0000000..06544ca --- /dev/null +++ b/opcodes/cgen-opc.c @@ -0,0 +1,650 @@ +/* CGEN generic opcode support. + + Copyright 1996, 1997, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "bfd.h" +#include "symcat.h" +#include "opcode/cgen.h" + +#ifdef HAVE_ALLOCA_H +#include +#endif + +static unsigned int hash_keyword_name + PARAMS ((const CGEN_KEYWORD *, const char *, int)); +static unsigned int hash_keyword_value + PARAMS ((const CGEN_KEYWORD *, unsigned int)); +static void build_keyword_hash_tables + PARAMS ((CGEN_KEYWORD *)); + +/* Return number of hash table entries to use for N elements. */ +#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) + +/* Look up *NAMEP in the keyword table KT. + The result is the keyword entry or NULL if not found. */ + +const CGEN_KEYWORD_ENTRY * +cgen_keyword_lookup_name (kt, name) + CGEN_KEYWORD *kt; + const char *name; +{ + const CGEN_KEYWORD_ENTRY *ke; + const char *p,*n; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)]; + + /* We do case insensitive comparisons. + If that ever becomes a problem, add an attribute that denotes + "do case sensitive comparisons". */ + + while (ke != NULL) + { + n = name; + p = ke->name; + + while (*p + && (*p == *n + || (ISALPHA (*p) && (TOLOWER (*p) == TOLOWER (*n))))) + ++n, ++p; + + if (!*p && !*n) + return ke; + + ke = ke->next_name; + } + + if (kt->null_entry) + return kt->null_entry; + return NULL; +} + +/* Look up VALUE in the keyword table KT. + The result is the keyword entry or NULL if not found. */ + +const CGEN_KEYWORD_ENTRY * +cgen_keyword_lookup_value (kt, value) + CGEN_KEYWORD *kt; + int value; +{ + const CGEN_KEYWORD_ENTRY *ke; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + ke = kt->value_hash_table[hash_keyword_value (kt, value)]; + + while (ke != NULL) + { + if (value == ke->value) + return ke; + ke = ke->next_value; + } + + return NULL; +} + +/* Add an entry to a keyword table. */ + +void +cgen_keyword_add (kt, ke) + CGEN_KEYWORD *kt; + CGEN_KEYWORD_ENTRY *ke; +{ + unsigned int hash; + size_t i; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + hash = hash_keyword_name (kt, ke->name, 0); + ke->next_name = kt->name_hash_table[hash]; + kt->name_hash_table[hash] = ke; + + hash = hash_keyword_value (kt, ke->value); + ke->next_value = kt->value_hash_table[hash]; + kt->value_hash_table[hash] = ke; + + if (ke->name[0] == 0) + kt->null_entry = ke; + + for (i = 1; i < strlen (ke->name); i++) + if (! ISALNUM (ke->name[i]) + && ! strchr (kt->nonalpha_chars, ke->name[i])) + { + size_t idx = strlen (kt->nonalpha_chars); + + /* If you hit this limit, please don't just + increase the size of the field, instead + look for a better algorithm. */ + if (idx >= sizeof (kt->nonalpha_chars) - 1) + abort (); + kt->nonalpha_chars[idx] = ke->name[i]; + kt->nonalpha_chars[idx+1] = 0; + } +} + +/* FIXME: Need function to return count of keywords. */ + +/* Initialize a keyword table search. + SPEC is a specification of what to search for. + A value of NULL means to find every keyword. + Currently NULL is the only acceptable value [further specification + deferred]. + The result is an opaque data item used to record the search status. + It is passed to each call to cgen_keyword_search_next. */ + +CGEN_KEYWORD_SEARCH +cgen_keyword_search_init (kt, spec) + CGEN_KEYWORD *kt; + const char *spec; +{ + CGEN_KEYWORD_SEARCH search; + + /* FIXME: Need to specify format of PARAMS. */ + if (spec != NULL) + abort (); + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + search.table = kt; + search.spec = spec; + search.current_hash = 0; + search.current_entry = NULL; + return search; +} + +/* Return the next keyword specified by SEARCH. + The result is the next entry or NULL if there are no more. */ + +const CGEN_KEYWORD_ENTRY * +cgen_keyword_search_next (search) + CGEN_KEYWORD_SEARCH *search; +{ + /* Has search finished? */ + if (search->current_hash == search->table->hash_table_size) + return NULL; + + /* Search in progress? */ + if (search->current_entry != NULL + /* Anything left on this hash chain? */ + && search->current_entry->next_name != NULL) + { + search->current_entry = search->current_entry->next_name; + return search->current_entry; + } + + /* Move to next hash chain [unless we haven't started yet]. */ + if (search->current_entry != NULL) + ++search->current_hash; + + while (search->current_hash < search->table->hash_table_size) + { + search->current_entry = search->table->name_hash_table[search->current_hash]; + if (search->current_entry != NULL) + return search->current_entry; + ++search->current_hash; + } + + return NULL; +} + +/* Return first entry in hash chain for NAME. + If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ + +static unsigned int +hash_keyword_name (kt, name, case_sensitive_p) + const CGEN_KEYWORD *kt; + const char *name; + int case_sensitive_p; +{ + unsigned int hash; + + if (case_sensitive_p) + for (hash = 0; *name; ++name) + hash = (hash * 97) + (unsigned char) *name; + else + for (hash = 0; *name; ++name) + hash = (hash * 97) + (unsigned char) TOLOWER (*name); + return hash % kt->hash_table_size; +} + +/* Return first entry in hash chain for VALUE. */ + +static unsigned int +hash_keyword_value (kt, value) + const CGEN_KEYWORD *kt; + unsigned int value; +{ + return value % kt->hash_table_size; +} + +/* Build a keyword table's hash tables. + We probably needn't build the value hash table for the assembler when + we're using the disassembler, but we keep things simple. */ + +static void +build_keyword_hash_tables (kt) + CGEN_KEYWORD *kt; +{ + int i; + /* Use the number of compiled in entries as an estimate for the + typical sized table [not too many added at runtime]. */ + unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); + + kt->hash_table_size = size; + kt->name_hash_table = (CGEN_KEYWORD_ENTRY **) + xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); + memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); + kt->value_hash_table = (CGEN_KEYWORD_ENTRY **) + xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); + memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); + + /* The table is scanned backwards as we want keywords appearing earlier to + be prefered over later ones. */ + for (i = kt->num_init_entries - 1; i >= 0; --i) + cgen_keyword_add (kt, &kt->init_entries[i]); +} + +/* Hardware support. */ + +/* Lookup a hardware element by its name. + Returns NULL if NAME is not supported by the currently selected + mach/isa. */ + +const CGEN_HW_ENTRY * +cgen_hw_lookup_by_name (cd, name) + CGEN_CPU_DESC cd; + const char *name; +{ + unsigned int i; + const CGEN_HW_ENTRY **hw = cd->hw_table.entries; + + for (i = 0; i < cd->hw_table.num_entries; ++i) + if (hw[i] && strcmp (name, hw[i]->name) == 0) + return hw[i]; + + return NULL; +} + +/* Lookup a hardware element by its number. + Hardware elements are enumerated, however it may be possible to add some + at runtime, thus HWNUM is not an enum type but rather an int. + Returns NULL if HWNUM is not supported by the currently selected mach. */ + +const CGEN_HW_ENTRY * +cgen_hw_lookup_by_num (cd, hwnum) + CGEN_CPU_DESC cd; + unsigned int hwnum; +{ + unsigned int i; + const CGEN_HW_ENTRY **hw = cd->hw_table.entries; + + /* ??? This can be speeded up. */ + for (i = 0; i < cd->hw_table.num_entries; ++i) + if (hw[i] && hwnum == hw[i]->type) + return hw[i]; + + return NULL; +} + +/* Operand support. */ + +/* Lookup an operand by its name. + Returns NULL if NAME is not supported by the currently selected + mach/isa. */ + +const CGEN_OPERAND * +cgen_operand_lookup_by_name (cd, name) + CGEN_CPU_DESC cd; + const char *name; +{ + unsigned int i; + const CGEN_OPERAND **op = cd->operand_table.entries; + + for (i = 0; i < cd->operand_table.num_entries; ++i) + if (op[i] && strcmp (name, op[i]->name) == 0) + return op[i]; + + return NULL; +} + +/* Lookup an operand by its number. + Operands are enumerated, however it may be possible to add some + at runtime, thus OPNUM is not an enum type but rather an int. + Returns NULL if OPNUM is not supported by the currently selected + mach/isa. */ + +const CGEN_OPERAND * +cgen_operand_lookup_by_num (cd, opnum) + CGEN_CPU_DESC cd; + int opnum; +{ + return cd->operand_table.entries[opnum]; +} + +/* Instruction support. */ + +/* Return number of instructions. This includes any added at runtime. */ + +int +cgen_insn_count (cd) + CGEN_CPU_DESC cd; +{ + int count = cd->insn_table.num_init_entries; + CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; + + for ( ; rt_insns != NULL; rt_insns = rt_insns->next) + ++count; + + return count; +} + +/* Return number of macro-instructions. + This includes any added at runtime. */ + +int +cgen_macro_insn_count (cd) + CGEN_CPU_DESC cd; +{ + int count = cd->macro_insn_table.num_init_entries; + CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; + + for ( ; rt_insns != NULL; rt_insns = rt_insns->next) + ++count; + + return count; +} + +/* Cover function to read and properly byteswap an insn value. */ + +CGEN_INSN_INT +cgen_get_insn_value (cd, buf, length) + CGEN_CPU_DESC cd; + unsigned char *buf; + int length; +{ + int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int insn_chunk_bitsize = cd->insn_chunk_bitsize; + CGEN_INSN_INT value = 0; + + if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) + { + /* We need to divide up the incoming value into insn_chunk_bitsize-length + segments, and endian-convert them, one at a time. */ + int i; + + /* Enforce divisibility. */ + if ((length % insn_chunk_bitsize) != 0) + abort (); + + for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ + { + int index; + bfd_vma this_value; + index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */ + this_value = bfd_get_bits (& buf[index / 8], insn_chunk_bitsize, big_p); + value = (value << insn_chunk_bitsize) | this_value; + } + } + else + { + value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); + } + + return value; +} + +/* Cover function to store an insn value properly byteswapped. */ + +void +cgen_put_insn_value (cd, buf, length, value) + CGEN_CPU_DESC cd; + unsigned char *buf; + int length; + CGEN_INSN_INT value; +{ + int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int insn_chunk_bitsize = cd->insn_chunk_bitsize; + + if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) + { + /* We need to divide up the incoming value into insn_chunk_bitsize-length + segments, and endian-convert them, one at a time. */ + int i; + + /* Enforce divisibility. */ + if ((length % insn_chunk_bitsize) != 0) + abort (); + + for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ + { + int index; + index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */ + bfd_put_bits ((bfd_vma) value, & buf[index / 8], insn_chunk_bitsize, big_p); + value >>= insn_chunk_bitsize; + } + } + else + { + bfd_put_bits ((bfd_vma) value, buf, length, big_p); + } +} + +/* Look up instruction INSN_*_VALUE and extract its fields. + INSN_INT_VALUE is used if CGEN_INT_INSN_P. + Otherwise INSN_BYTES_VALUE is used. + INSN, if non-null, is the insn table entry. + Otherwise INSN_*_VALUE is examined to compute it. + LENGTH is the bit length of INSN_*_VALUE if known, otherwise 0. + 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. + If INSN != NULL, LENGTH must be valid. + ALIAS_P is non-zero if alias insns are to be included in the search. + + The result is a pointer to the insn table entry, or NULL if the instruction + wasn't recognized. */ + +/* ??? Will need to be revisited for VLIW architectures. */ + +const CGEN_INSN * +cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, + alias_p) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_INSN_INT insn_int_value; + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value; + int length; + CGEN_FIELDS *fields; + int alias_p; +{ + unsigned char *buf; + CGEN_INSN_INT base_insn; + CGEN_EXTRACT_INFO ex_info; + CGEN_EXTRACT_INFO *info; + + if (cd->int_insn_p) + { + info = NULL; + buf = (unsigned char *) alloca (cd->max_insn_bitsize / 8); + cgen_put_insn_value (cd, buf, length, insn_int_value); + base_insn = insn_int_value; + } + else + { + info = &ex_info; + ex_info.dis_info = NULL; + ex_info.insn_bytes = insn_bytes_value; + ex_info.valid = -1; + buf = insn_bytes_value; + base_insn = cgen_get_insn_value (cd, buf, length); + } + + if (!insn) + { + const CGEN_INSN_LIST *insn_list; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = cgen_dis_lookup_insn (cd, buf, base_insn); + while (insn_list != NULL) + { + insn = insn_list->insn; + + if (alias_p + /* FIXME: Ensure ALIAS attribute always has same index. */ + || ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) + { + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the + extract handler. */ + if ((base_insn & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* ??? 0 is passed for `pc' */ + int elength = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, info, base_insn, fields, (bfd_vma) 0); + if (elength > 0) + { + /* sanity check */ + if (length != 0 && length != elength) + abort (); + return insn; + } + } + } + + insn_list = insn_list->next; + } + } + else + { + /* Sanity check: can't pass an alias insn if ! alias_p. */ + if (! alias_p + && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) + abort (); + /* Sanity check: length must be correct. */ + if (length != CGEN_INSN_BITSIZE (insn)) + abort (); + + /* ??? 0 is passed for `pc' */ + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, info, base_insn, fields, (bfd_vma) 0); + /* Sanity check: must succeed. + Could relax this later if it ever proves useful. */ + if (length == 0) + abort (); + return insn; + } + + return NULL; +} + +/* Fill in the operand instances used by INSN whose operands are FIELDS. + INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled + in. */ + +void +cgen_get_insn_operands (cd, insn, fields, indices) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const CGEN_FIELDS *fields; + int *indices; +{ + const CGEN_OPINST *opinst; + int i; + + if (insn->opinst == NULL) + abort (); + for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst) + { + enum cgen_operand_type op_type = opinst->op_type; + if (op_type == CGEN_OPERAND_NIL) + indices[i] = opinst->index; + else + indices[i] = (*cd->get_int_operand) (cd, op_type, fields); + } +} + +/* Cover function to cgen_get_insn_operands when either INSN or FIELDS + isn't known. + The INSN, INSN_*_VALUE, and LENGTH arguments are passed to + cgen_lookup_insn unchanged. + INSN_INT_VALUE is used if CGEN_INT_INSN_P. + Otherwise INSN_BYTES_VALUE is used. + + The result is the insn table entry or NULL if the instruction wasn't + recognized. */ + +const CGEN_INSN * +cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, + length, indices, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_INSN_INT insn_int_value; + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value; + int length; + int *indices; + CGEN_FIELDS *fields; +{ + /* Pass non-zero for ALIAS_P only if INSN != NULL. + If INSN == NULL, we want a real insn. */ + insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, + length, fields, insn != NULL); + if (! insn) + return NULL; + + cgen_get_insn_operands (cd, insn, fields, indices); + return insn; +} + +/* Allow signed overflow of instruction fields. */ +void +cgen_set_signed_overflow_ok (cd) + CGEN_CPU_DESC cd; +{ + cd->signed_overflow_ok_p = 1; +} + +/* Generate an error message if a signed field in an instruction overflows. */ +void +cgen_clear_signed_overflow_ok (cd) + CGEN_CPU_DESC cd; +{ + cd->signed_overflow_ok_p = 0; +} + +/* Will an error message be generated if a signed field in an instruction overflows ? */ +unsigned int +cgen_signed_overflow_ok_p (cd) + CGEN_CPU_DESC cd; +{ + return cd->signed_overflow_ok_p; +} diff --git a/opcodes/cgen.sh b/opcodes/cgen.sh new file mode 100644 index 0000000..a9483bd --- /dev/null +++ b/opcodes/cgen.sh @@ -0,0 +1,154 @@ +#! /bin/sh +# CGEN generic assembler support code. +# +# Copyright 2001 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils and GDB, the GNU debugger. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +# +# Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch], +# arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch]. +# +# Usage: +# cgen.sh action srcdir cgen cgendir cgenflags arch prefix options +# +# ACTION is currently always "opcodes". It exists to be consistent with the +# simulator. +# OPTIONS is comma separated list of options: +# - opinst - arch-opinst.c is being made, causes semantic analysis +# +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter (or other implementation) with gdb/binutils. +# Maybe we never will. + +# We want to behave like make, any error forces us to stop. +set -e + +action=$1 +srcdir=$2 +cgen=$3 +cgendir=$4 +cgenflags=$5 +arch=$6 +prefix=$7 +options=$8 + +# List of extra files to build. +# Values: opinst (only 1 extra file at present) +extrafiles=$9 + +rootdir=${srcdir}/.. + +# $arch is $6, as passed on the command line. +# $ARCH is the same argument but in all uppercase. +# Both forms are used in this script. + +lowercase='abcdefghijklmnopqrstuvwxyz' +uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"` + +extrafile_args="" +for ef in .. $extrafiles +do + case $ef in + ..) ;; + opinst) extrafile_args="-Q tmp-opinst.c1 $extrafile_args" ;; + esac +done + +case $action in +opcodes) + # Remove residual working files. + rm -f tmp-desc.h tmp-desc.h1 + rm -f tmp-desc.c tmp-desc.c1 + rm -f tmp-opc.h tmp-opc.h1 + rm -f tmp-opc.c tmp-opc.c1 + rm -f tmp-opinst.c tmp-opinst.c1 + rm -f tmp-ibld.h tmp-ibld.h1 + rm -f tmp-ibld.c tmp-ibld.in1 + rm -f tmp-asm.c tmp-asm.in1 + rm -f tmp-dis.c tmp-dis.in1 + + # Run CGEN. + ${cgen} -s ${cgendir}/cgen-opc.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${options}" \ + -m all \ + -a ${arch} \ + -H tmp-desc.h1 \ + -C tmp-desc.c1 \ + -O tmp-opc.h1 \ + -P tmp-opc.c1 \ + -L tmp-ibld.in1 \ + -A tmp-asm.in1 \ + -D tmp-dis.in1 \ + ${extrafile_args} + + # Customise generated files for the particular architecture. + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-desc.h1 > tmp-desc.h + ${rootdir}/move-if-change tmp-desc.h ${srcdir}/${prefix}-desc.h + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < tmp-desc.c1 > tmp-desc.c + ${rootdir}/move-if-change tmp-desc.c ${srcdir}/${prefix}-desc.c + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-opc.h1 > tmp-opc.h + ${rootdir}/move-if-change tmp-opc.h ${srcdir}/${prefix}-opc.h + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < tmp-opc.c1 > tmp-opc.c + ${rootdir}/move-if-change tmp-opc.c ${srcdir}/${prefix}-opc.c + + case $extrafiles in + *opinst*) + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < tmp-opinst.c1 >tmp-opinst.c + ${rootdir}/move-if-change tmp-opinst.c ${srcdir}/${prefix}-opinst.c + ;; + esac + + cat ${srcdir}/cgen-ibld.in tmp-ibld.in1 | \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > tmp-ibld.c + ${rootdir}/move-if-change tmp-ibld.c ${srcdir}/${prefix}-ibld.c + + sed -e "/ -- assembler routines/ r tmp-asm.in1" ${srcdir}/cgen-asm.in \ + | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > tmp-asm.c + ${rootdir}/move-if-change tmp-asm.c ${srcdir}/${prefix}-asm.c + + sed -e "/ -- disassembler routines/ r tmp-dis.in1" ${srcdir}/cgen-dis.in \ + | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > tmp-dis.c + ${rootdir}/move-if-change tmp-dis.c ${srcdir}/${prefix}-dis.c + + # Remove temporary files. + rm -f tmp-desc.h1 tmp-desc.c1 + rm -f tmp-opc.h1 tmp-opc.c1 + rm -f tmp-opinst.c1 + rm -f tmp-ibld.h1 tmp-ibld.in1 + rm -f tmp-asm.in1 tmp-dis.in1 + ;; + +*) + echo "$0: bad action: ${action}" >&2 + exit 1 + ;; + +esac + +exit 0 diff --git a/opcodes/config.in b/opcodes/config.in new file mode 100644 index 0000000..6355be0 --- /dev/null +++ b/opcodes/config.in @@ -0,0 +1,141 @@ +/* config.in. Generated automatically from configure.in by autoheader. */ + +/* Define if using alloca.c. */ +#undef C_ALLOCA + +/* Define to empty if the keyword does not work. */ +#undef const + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define if you have alloca, as a function or macro. */ +#undef HAVE_ALLOCA + +/* Define if you have and it should be used (not on Ultrix). */ +#undef HAVE_ALLOCA_H + +/* Define if you have a working `mmap' system call. */ +#undef HAVE_MMAP + +/* Define as __inline if that's what the C compiler calls it. */ +#undef inline + +/* Define to `long' if doesn't define. */ +#undef off_t + +/* Define if you need to in order for stat and other things to work. */ +#undef _POSIX_SOURCE + +/* Define to `unsigned' if doesn't define. */ +#undef size_t + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown + */ +#undef STACK_DIRECTION + +/* Define if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define if you have the __argz_count function. */ +#undef HAVE___ARGZ_COUNT + +/* Define if you have the __argz_next function. */ +#undef HAVE___ARGZ_NEXT + +/* Define if you have the __argz_stringify function. */ +#undef HAVE___ARGZ_STRINGIFY + +/* Define if you have the dcgettext function. */ +#undef HAVE_DCGETTEXT + +/* Define if you have the getcwd function. */ +#undef HAVE_GETCWD + +/* Define if you have the getpagesize function. */ +#undef HAVE_GETPAGESIZE + +/* Define if you have the munmap function. */ +#undef HAVE_MUNMAP + +/* Define if you have the putenv function. */ +#undef HAVE_PUTENV + +/* Define if you have the setenv function. */ +#undef HAVE_SETENV + +/* Define if you have the setlocale function. */ +#undef HAVE_SETLOCALE + +/* Define if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if you have the strcasecmp function. */ +#undef HAVE_STRCASECMP + +/* Define if you have the strchr function. */ +#undef HAVE_STRCHR + +/* Define if you have the header file. */ +#undef HAVE_ARGZ_H + +/* Define if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define if you have the header file. */ +#undef HAVE_LOCALE_H + +/* Define if you have the header file. */ +#undef HAVE_MALLOC_H + +/* Define if you have the header file. */ +#undef HAVE_NL_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PARAM_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_VALUES_H + +/* Name of package */ +#undef PACKAGE + +/* Version number of package */ +#undef VERSION + +/* Define if you have the stpcpy function */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES + +/* Define to 1 if NLS is requested */ +#undef ENABLE_NLS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + diff --git a/opcodes/configure b/opcodes/configure new file mode 100755 index 0000000..a83d43d --- /dev/null +++ b/opcodes/configure @@ -0,0 +1,5133 @@ +#! /bin/sh + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.13 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: +ac_help="$ac_help + --enable-shared[=PKGS] build shared libraries [default=no]" +ac_help="$ac_help + --enable-static[=PKGS] build static libraries [default=yes]" +ac_help="$ac_help + --enable-fast-install[=PKGS] optimize for fast installation [default=yes]" +ac_help="$ac_help + --with-gnu-ld assume the C compiler uses GNU ld [default=no]" +ac_help="$ac_help + --disable-libtool-lock avoid locking (might break parallel builds)" +ac_help="$ac_help + --with-pic try to use only PIC/non-PIC objects [default=use both]" +ac_help="$ac_help + --enable-targets alternative target configurations" +ac_help="$ac_help + --enable-commonbfdlib build shared BFD/opcodes/libiberty library" +ac_help="$ac_help + --enable-build-warnings Enable build-time compiler warnings if gcc is used" +ac_help="$ac_help + --enable-maintainer-mode enable make rules and dependencies not useful + (and sometimes confusing) to the casual installer" +ac_help="$ac_help + --install-libbfd controls installation of libbfd and related headers" +ac_help="$ac_help + --disable-nls do not use Native Language Support" +ac_help="$ac_help + --with-included-gettext use the GNU gettext library included here" +ac_help="$ac_help + --enable-cgen-maint[=dir] build cgen generated files" + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; 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then + echo "--enable and --with options recognized:$ac_help" + fi + exit 0 ;; + + -host | --host | --hos | --ho) + ac_prev=host ;; + -host=* | --host=* | --hos=* | --ho=*) + host="$ac_optarg" ;; + + -includedir | --includedir | --includedi | --included | --include \ + | --includ | --inclu | --incl | --inc) + ac_prev=includedir ;; + -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ + | --includ=* | --inclu=* | --incl=* | --inc=*) + includedir="$ac_optarg" ;; + + -infodir | --infodir | --infodi | --infod | --info | --inf) + ac_prev=infodir ;; + -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) + infodir="$ac_optarg" ;; + + -libdir | --libdir | --libdi | --libd) + ac_prev=libdir ;; + -libdir=* | --libdir=* | --libdi=* | --libd=*) + libdir="$ac_optarg" ;; + + -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ + | --libexe | --libex | --libe) + ac_prev=libexecdir ;; + -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ + | --libexe=* | --libex=* | --libe=*) + libexecdir="$ac_optarg" ;; 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+ + -program-transform-name | --program-transform-name \ + | --program-transform-nam | --program-transform-na \ + | --program-transform-n | --program-transform- \ + | --program-transform | --program-transfor \ + | --program-transfo | --program-transf \ + | --program-trans | --program-tran \ + | --progr-tra | --program-tr | --program-t) + ac_prev=program_transform_name ;; + -program-transform-name=* | --program-transform-name=* \ + | --program-transform-nam=* | --program-transform-na=* \ + | --program-transform-n=* | --program-transform-=* \ + | --program-transform=* | --program-transfor=* \ + | --program-transfo=* | --program-transf=* \ + | --program-trans=* | --program-tran=* \ + | --progr-tra=* | --program-tr=* | --program-t=*) + program_transform_name="$ac_optarg" ;; + + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + silent=yes ;; + + -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) + ac_prev=sbindir ;; + -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ + | --sbi=* | --sb=*) + sbindir="$ac_optarg" ;; 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+ + -target | --target | --targe | --targ | --tar | --ta | --t) + ac_prev=target ;; + -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) + target="$ac_optarg" ;; + + -v | -verbose | --verbose | --verbos | --verbo | --verb) + verbose=yes ;; + + -version | --version | --versio | --versi | --vers) + echo "configure generated by autoconf version 2.13" + exit 0 ;; + + -with-* | --with-*) + ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; } + fi + ac_package=`echo $ac_package| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "with_${ac_package}='$ac_optarg'" ;; + + -without-* | --without-*) + ac_package=`echo $ac_option|sed -e 's/-*without-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; } + fi + ac_package=`echo $ac_package| sed 's/-/_/g'` + eval "with_${ac_package}=no" ;; + + --x) + # Obsolete; use --with-x. + with_x=yes ;; + + -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ + | --x-incl | --x-inc | --x-in | --x-i) + ac_prev=x_includes ;; + -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ + | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) + x_includes="$ac_optarg" ;; + + -x-libraries | --x-libraries | --x-librarie | --x-librari \ + | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) + ac_prev=x_libraries ;; + -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ + | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) + x_libraries="$ac_optarg" ;; + + -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; } + ;; + + *) + if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then + echo "configure: warning: $ac_option: invalid host type" 1>&2 + fi + if test "x$nonopt" != xNONE; then + { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } + fi + nonopt="$ac_option" + ;; + + esac +done + +if test -n "$ac_prev"; then + { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; } +fi + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +# File descriptor usage: +# 0 standard input +# 1 file creation +# 2 errors and warnings +# 3 some systems may open it to /dev/tty +# 4 used on the Kubota Titan +# 6 checking for... messages and results +# 5 compiler messages saved in config.log +if test "$silent" = yes; then + exec 6>/dev/null +else + exec 6>&1 +fi +exec 5>./config.log + +echo "\ +This file contains any messages produced by compilers while +running configure, to aid debugging if configure makes a mistake. +" 1>&5 + +# Strip out --no-create and --no-recursion so they do not pile up. +# Also quote any args containing shell metacharacters. +ac_configure_args= +for ac_arg +do + case "$ac_arg" in + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) ;; + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;; + *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*) + ac_configure_args="$ac_configure_args '$ac_arg'" ;; + *) ac_configure_args="$ac_configure_args $ac_arg" ;; + esac +done + +# NLS nuisances. +# Only set these to C if already set. These must not be set unconditionally +# because not all systems understand e.g. LANG=C (notably SCO). +# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'! +# Non-C LC_CTYPE values break the ctype check. +if test "${LANG+set}" = set; then LANG=C; export LANG; fi +if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi +if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi +if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi + +# confdefs.h avoids OS command line length limits that DEFS can exceed. +rm -rf conftest* confdefs.h +# AIX cpp loses on an empty file, so make sure it contains at least a newline. +echo > confdefs.h + +# A filename unique to this package, relative to the directory that +# configure is in, which we can look for to find out if srcdir is correct. +ac_unique_file=z8k-dis.c + +# Find the source files, if location was not specified. +if test -z "$srcdir"; then + ac_srcdir_defaulted=yes + # Try the directory containing this script, then its parent. + ac_prog=$0 + ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'` + test "x$ac_confdir" = "x$ac_prog" && ac_confdir=. + srcdir=$ac_confdir + if test ! -r $srcdir/$ac_unique_file; then + srcdir=.. + fi +else + ac_srcdir_defaulted=no +fi +if test ! -r $srcdir/$ac_unique_file; then + if test "$ac_srcdir_defaulted" = yes; then + { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; } + else + { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; } + fi +fi +srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'` + +# Prefer explicitly selected file to automatically selected ones. +if test -z "$CONFIG_SITE"; then + if test "x$prefix" != xNONE; then + CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" + else + CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" + fi +fi +for ac_site_file in $CONFIG_SITE; do + if test -r "$ac_site_file"; then + echo "loading site script $ac_site_file" + . "$ac_site_file" + fi +done + +if test -r "$cache_file"; then + echo "loading cache $cache_file" + . $cache_file +else + echo "creating cache $cache_file" + > $cache_file +fi + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +ac_exeext= +ac_objext=o +if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then + # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu. + if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then + ac_n= ac_c=' +' ac_t=' ' + else + ac_n=-n ac_c= ac_t= + fi +else + ac_n= ac_c='\c' ac_t= +fi + +echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6 +echo "configure:554: checking for Cygwin environment" >&5 +if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_cygwin=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_cygwin=no +fi +rm -f conftest* +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_cygwin" 1>&6 +CYGWIN= +test "$ac_cv_cygwin" = yes && CYGWIN=yes +echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6 +echo "configure:587: checking for mingw32 environment" >&5 +if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_mingw32=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_mingw32=no +fi +rm -f conftest* +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_mingw32" 1>&6 +MINGW32= +test "$ac_cv_mingw32" = yes && MINGW32=yes + + +ac_aux_dir= +for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do + if test -f $ac_dir/install-sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f $ac_dir/install.sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { echo "configure: error: can not find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." 1>&2; exit 1; } +fi +ac_config_guess=$ac_aux_dir/config.guess +ac_config_sub=$ac_aux_dir/config.sub +ac_configure=$ac_aux_dir/configure # This should be Cygnus configure. + + +# Do some error checking and defaulting for the host and target type. +# The inputs are: +# configure --host=HOST --target=TARGET --build=BUILD NONOPT +# +# The rules are: +# 1. You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:664: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:685: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:703: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:728: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:758: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:809: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:841: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 852 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:857: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:883: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:888: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:916: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + +echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 +echo "configure:948: checking for POSIXized ISC" >&5 +if test -d /etc/conf/kconfig.d && + grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 +then + echo "$ac_t""yes" 1>&6 + ISC=yes # If later tests want to check for ISC. + cat >> confdefs.h <<\EOF +#define _POSIX_SOURCE 1 +EOF + + if test "$GCC" = yes; then + CC="$CC -posix" + else + CC="$CC -Xp" + fi +else + echo "$ac_t""no" 1>&6 + ISC= +fi + + +# We currently only use the version number for the name of any shared +# library. For user convenience, we always use the same version +# number that BFD is using. +BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${srcdir}/../bfd/configure.in` + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# ./install, which can be erroneously created by make from ./install.sh. +echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 +echo "configure:986: checking for a BSD compatible install" >&5 +if test -z "$INSTALL"; then +if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS=":" + for ac_dir in $PATH; do + # Account for people who put trailing slashes in PATH elements. + case "$ac_dir/" in + /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + if test -f $ac_dir/$ac_prog; then + if test $ac_prog = install && + grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + else + ac_cv_path_install="$ac_dir/$ac_prog -c" + break 2 + fi + fi + done + ;; + esac + done + IFS="$ac_save_IFS" + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL="$ac_cv_path_install" + else + # As a last resort, use the slow shell script. We don't cache a + # path for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the path is relative. + INSTALL="$ac_install_sh" + fi +fi +echo "$ac_t""$INSTALL" 1>&6 + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + +echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6 +echo "configure:1039: checking whether build environment is sane" >&5 +# Just in case +sleep 1 +echo timestamp > conftestfile +# Do `set' in a subshell so we don't clobber the current shell's +# arguments. Must try -L first in case configure is actually a +# symlink; some systems play weird games with the mod time of symlinks +# (eg FreeBSD returns the mod time of the symlink's containing +# directory). +if ( + set X `ls -Lt $srcdir/configure conftestfile 2> /dev/null` + if test "$*" = "X"; then + # -L didn't work. + set X `ls -t $srcdir/configure conftestfile` + fi + if test "$*" != "X $srcdir/configure conftestfile" \ + && test "$*" != "X conftestfile $srcdir/configure"; then + + # If neither matched, then we have a broken ls. This can happen + # if, for instance, CONFIG_SHELL is bash and it inherits a + # broken ls alias from the environment. This has actually + # happened. Such a system could not be considered "sane". + { echo "configure: error: ls -t appears to fail. Make sure there is not a broken +alias in your environment" 1>&2; exit 1; } + fi + + test "$2" = conftestfile + ) +then + # Ok. + : +else + { echo "configure: error: newly created file is older than distributed files! +Check your system clock" 1>&2; exit 1; } +fi +rm -f conftest* +echo "$ac_t""yes" 1>&6 +if test "$program_transform_name" = s,x,x,; then + program_transform_name= +else + # Double any \ or $. echo might interpret backslashes. + cat <<\EOF_SED > conftestsed +s,\\,\\\\,g; s,\$,$$,g +EOF_SED + program_transform_name="`echo $program_transform_name|sed -f conftestsed`" + rm -f conftestsed +fi +test "$program_prefix" != NONE && + program_transform_name="s,^,${program_prefix},; $program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s,\$\$,${program_suffix},; $program_transform_name" + +# sed with no file args requires a program. +test "$program_transform_name" = "" && program_transform_name="s,x,x," + +echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 +echo "configure:1096: checking whether ${MAKE-make} sets \${MAKE}" >&5 +set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftestmake <<\EOF +all: + @echo 'ac_maketemp="${MAKE}"' +EOF +# GNU make sometimes prints "make[1]: Entering...", which would confuse us. +eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=` +if test -n "$ac_maketemp"; then + eval ac_cv_prog_make_${ac_make}_set=yes +else + eval ac_cv_prog_make_${ac_make}_set=no +fi +rm -f conftestmake +fi +if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then + echo "$ac_t""yes" 1>&6 + SET_MAKE= +else + echo "$ac_t""no" 1>&6 + SET_MAKE="MAKE=${MAKE-make}" +fi + + +PACKAGE=opcodes + +VERSION=${BFD_VERSION} + +if test "`cd $srcdir && pwd`" != "`pwd`" && test -f $srcdir/config.status; then + { echo "configure: error: source directory already configured; run "make distclean" there first" 1>&2; exit 1; } +fi +cat >> confdefs.h <> confdefs.h <&6 +echo "configure:1142: checking for working aclocal" >&5 +# Run test in a subshell; some versions of sh will print an error if +# an executable is not found, even if stderr is redirected. +# Redirect stdin to placate older versions of autoconf. Sigh. +if (aclocal --version) < /dev/null > /dev/null 2>&1; then + ACLOCAL=aclocal + echo "$ac_t""found" 1>&6 +else + ACLOCAL="$missing_dir/missing aclocal" + echo "$ac_t""missing" 1>&6 +fi + +echo $ac_n "checking for working autoconf""... $ac_c" 1>&6 +echo "configure:1155: checking for working autoconf" >&5 +# Run test in a subshell; some versions of sh will print an error if +# an executable is not found, even if stderr is redirected. +# Redirect stdin to placate older versions of autoconf. Sigh. +if (autoconf --version) < /dev/null > /dev/null 2>&1; then + AUTOCONF=autoconf + echo "$ac_t""found" 1>&6 +else + AUTOCONF="$missing_dir/missing autoconf" + echo "$ac_t""missing" 1>&6 +fi + +echo $ac_n "checking for working automake""... $ac_c" 1>&6 +echo "configure:1168: checking for working automake" >&5 +# Run test in a subshell; some versions of sh will print an error if +# an executable is not found, even if stderr is redirected. +# Redirect stdin to placate older versions of autoconf. Sigh. +if (automake --version) < /dev/null > /dev/null 2>&1; then + AUTOMAKE=automake + echo "$ac_t""found" 1>&6 +else + AUTOMAKE="$missing_dir/missing automake" + echo "$ac_t""missing" 1>&6 +fi + +echo $ac_n "checking for working autoheader""... $ac_c" 1>&6 +echo "configure:1181: checking for working autoheader" >&5 +# Run test in a subshell; some versions of sh will print an error if +# an executable is not found, even if stderr is redirected. +# Redirect stdin to placate older versions of autoconf. Sigh. +if (autoheader --version) < /dev/null > /dev/null 2>&1; then + AUTOHEADER=autoheader + echo "$ac_t""found" 1>&6 +else + AUTOHEADER="$missing_dir/missing autoheader" + echo "$ac_t""missing" 1>&6 +fi + +echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6 +echo "configure:1194: checking for working makeinfo" >&5 +# Run test in a subshell; some versions of sh will print an error if +# an executable is not found, even if stderr is redirected. +# Redirect stdin to placate older versions of autoconf. Sigh. +if (makeinfo --version) < /dev/null > /dev/null 2>&1; then + MAKEINFO=makeinfo + echo "$ac_t""found" 1>&6 +else + MAKEINFO="$missing_dir/missing makeinfo" + echo "$ac_t""missing" 1>&6 +fi + + + +if test $host != $build; then + ac_tool_prefix=${host_alias}- +else + ac_tool_prefix= +fi + +# Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1217: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_AR" && ac_cv_prog_AR="ar" +fi +fi +AR="$ac_cv_prog_AR" +if test -n "$AR"; then + echo "$ac_t""$AR" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + + +# Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1249: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + +if test -z "$ac_cv_prog_RANLIB"; then +if test -n "$ac_tool_prefix"; then + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1281: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="ranlib" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +else + RANLIB=":" +fi +fi + + +# Check whether --enable-shared or --disable-shared was given. +if test "${enable_shared+set}" = set; then + enableval="$enable_shared" + p=${PACKAGE-default} +case $enableval in +yes) enable_shared=yes ;; +no) enable_shared=no ;; +*) + enable_shared=no + # Look at the argument we got. We use all the common list separators. + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:," + for pkg in $enableval; do + if test "X$pkg" = "X$p"; then + enable_shared=yes + fi + done + IFS="$ac_save_ifs" + ;; +esac +else + enable_shared=no +fi + + +# Check whether --enable-static or --disable-static was given. +if test "${enable_static+set}" = set; then + enableval="$enable_static" + p=${PACKAGE-default} +case $enableval in +yes) enable_static=yes ;; +no) enable_static=no ;; +*) + enable_static=no + # Look at the argument we got. We use all the common list separators. + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:," + for pkg in $enableval; do + if test "X$pkg" = "X$p"; then + enable_static=yes + fi + done + IFS="$ac_save_ifs" + ;; +esac +else + enable_static=yes +fi + +# Check whether --enable-fast-install or --disable-fast-install was given. +if test "${enable_fast_install+set}" = set; then + enableval="$enable_fast_install" + p=${PACKAGE-default} +case $enableval in +yes) enable_fast_install=yes ;; +no) enable_fast_install=no ;; +*) + enable_fast_install=no + # Look at the argument we got. We use all the common list separators. + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:," + for pkg in $enableval; do + if test "X$pkg" = "X$p"; then + enable_fast_install=yes + fi + done + IFS="$ac_save_ifs" + ;; +esac +else + enable_fast_install=yes +fi + +# Check whether --with-gnu-ld or --without-gnu-ld was given. +if test "${with_gnu_ld+set}" = set; then + withval="$with_gnu_ld" + test "$withval" = no || with_gnu_ld=yes +else + with_gnu_ld=no +fi + +ac_prog=ld +if test "$GCC" = yes; then + # Check if gcc -print-prog-name=ld gives a path. + echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6 +echo "configure:1396: checking for ld used by GCC" >&5 + case $host in + *-*-mingw*) + # gcc leaves a trailing carriage return which upsets mingw + ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; + *) + ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; + esac + case $ac_prog in + # Accept absolute paths. + [\\/]* | [A-Za-z]:[\\/]*) + re_direlt='/[^/][^/]*/\.\./' + # Canonicalize the path of ld + ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'` + while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do + ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"` + done + test -z "$LD" && LD="$ac_prog" + ;; + "") + # If it fails, then pretend we aren't using GCC. + ac_prog=ld + ;; + *) + # If it is relative, then search for the first ld in PATH. + with_gnu_ld=unknown + ;; + esac +elif test "$with_gnu_ld" = yes; then + echo $ac_n "checking for GNU ld""... $ac_c" 1>&6 +echo "configure:1426: checking for GNU ld" >&5 +else + echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6 +echo "configure:1429: checking for non-GNU ld" >&5 +fi +if eval "test \"`echo '$''{'lt_cv_path_LD'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -z "$LD"; then + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then + lt_cv_path_LD="$ac_dir/$ac_prog" + # Check to see if the program is GNU ld. I'd rather use --version, + # but apparently some GNU ld's only accept -v. + # Break only if it was the GNU/non-GNU ld that we prefer. + if "$lt_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then + test "$with_gnu_ld" != no && break + else + test "$with_gnu_ld" != yes && break + fi + fi + done + IFS="$ac_save_ifs" +else + lt_cv_path_LD="$LD" # Let the user override the test with a path. +fi +fi + +LD="$lt_cv_path_LD" +if test -n "$LD"; then + echo "$ac_t""$LD" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi +test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; } +echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6 +echo "configure:1464: checking if the linker ($LD) is GNU ld" >&5 +if eval "test \"`echo '$''{'lt_cv_prog_gnu_ld'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + # I'd rather use --version here, but apparently some GNU ld's only accept -v. +if $LD -v 2>&1 &5; then + lt_cv_prog_gnu_ld=yes +else + lt_cv_prog_gnu_ld=no +fi +fi + +echo "$ac_t""$lt_cv_prog_gnu_ld" 1>&6 +with_gnu_ld=$lt_cv_prog_gnu_ld + + +echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6 +echo "configure:1481: checking for $LD option to reload object files" >&5 +if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + lt_cv_ld_reload_flag='-r' +fi + +echo "$ac_t""$lt_cv_ld_reload_flag" 1>&6 +reload_flag=$lt_cv_ld_reload_flag +test -n "$reload_flag" && reload_flag=" $reload_flag" + +echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6 +echo "configure:1493: checking for BSD-compatible nm" >&5 +if eval "test \"`echo '$''{'lt_cv_path_NM'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$NM"; then + # Let the user override the test. + lt_cv_path_NM="$NM" +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}" + for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do + test -z "$ac_dir" && ac_dir=. + tmp_nm=$ac_dir/${ac_tool_prefix}nm + if test -f $tmp_nm || test -f $tmp_nm$ac_exeext ; then + # Check to see if the nm accepts a BSD-compat flag. + # Adding the `sed 1q' prevents false positives on HP-UX, which says: + # nm: unknown option "B" ignored + # Tru64's nm complains that /dev/null is an invalid object file + if ($tmp_nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep '(/dev/null|Invalid file or object type)' >/dev/null; then + lt_cv_path_NM="$tmp_nm -B" + break + elif ($tmp_nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then + lt_cv_path_NM="$tmp_nm -p" + break + else + lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but + continue # so that we can try to find one that supports BSD flags + fi + fi + done + IFS="$ac_save_ifs" + test -z "$lt_cv_path_NM" && lt_cv_path_NM=nm +fi +fi + +NM="$lt_cv_path_NM" +echo "$ac_t""$NM" 1>&6 + +echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6 +echo "configure:1531: checking whether ln -s works" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + rm -f conftestdata +if ln -s X conftestdata 2>/dev/null +then + rm -f conftestdata + ac_cv_prog_LN_S="ln -s" +else + ac_cv_prog_LN_S=ln +fi +fi +LN_S="$ac_cv_prog_LN_S" +if test "$ac_cv_prog_LN_S" = "ln -s"; then + echo "$ac_t""yes" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6 +echo "configure:1552: checking how to recognise dependant libraries" >&5 +if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + lt_cv_file_magic_cmd='$MAGIC_CMD' +lt_cv_file_magic_test_file= +lt_cv_deplibs_check_method='unknown' +# Need to set the preceding variable on all platforms that support +# interlibrary dependencies. +# 'none' -- dependencies not supported. +# `unknown' -- same as none, but documents that we really don't know. +# 'pass_all' -- all dependencies passed with no checks. +# 'test_compile' -- check by making test program. +# 'file_magic [regex]' -- check by looking for files in library path +# which responds to the $file_magic_cmd with a given egrep regex. +# If you have `file' or equivalent on your system and you're not sure +# whether `pass_all' will *always* work, you probably want this one. + +case $host_os in +aix*) + lt_cv_deplibs_check_method=pass_all + ;; + +beos*) + lt_cv_deplibs_check_method=pass_all + ;; + +bsdi4*) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' + lt_cv_file_magic_cmd='/usr/bin/file -L' + lt_cv_file_magic_test_file=/shlib/libc.so + ;; + +cygwin* | mingw* |pw32*) + lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?' + lt_cv_file_magic_cmd='$OBJDUMP -f' + ;; + +darwin* | rhapsody*) + lt_cv_deplibs_check_method='file_magic Mach-O dynamically linked shared library' + lt_cv_file_magic_cmd='/usr/bin/file -L' + case "$host_os" in + rhapsody* | darwin1.012) + lt_cv_file_magic_test_file='/System/Library/Frameworks/System.framework/System' + ;; + *) # Darwin 1.3 on + lt_cv_file_magic_test_file='/usr/lib/libSystem.dylib' + ;; + esac + ;; + +freebsd* ) + if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then + case $host_cpu in + i*86 ) + # Not sure whether the presence of OpenBSD here was a mistake. + # Let's accept both of them until this is cleared up. + lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` + ;; + esac + else + lt_cv_deplibs_check_method=pass_all + fi + ;; + +gnu*) + lt_cv_deplibs_check_method=pass_all + ;; + +hpux10.20*|hpux11*) + case $host_cpu in + hppa*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=/usr/lib/libc.sl + ;; + ia64*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so + ;; + esac + ;; + +irix5* | irix6*) + case $host_os in + irix5*) + # this will be overridden with pass_all, but let us keep it just in case + lt_cv_deplibs_check_method="file_magic ELF 32-bit MSB dynamic lib MIPS - version 1" + ;; + *) + case $LD in + *-32|*"-32 ") libmagic=32-bit;; + *-n32|*"-n32 ") libmagic=N32;; + *-64|*"-64 ") libmagic=64-bit;; + *) libmagic=never-match;; + esac + # this will be overridden with pass_all, but let us keep it just in case + lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1" + ;; + esac + lt_cv_file_magic_test_file=`echo /lib${libsuff}/libc.so*` + lt_cv_deplibs_check_method=pass_all + ;; + +# This must be Linux ELF. +linux-gnu*) + case $host_cpu in + alpha* | hppa* | i*86 | powerpc* | sparc* | ia64* ) + lt_cv_deplibs_check_method=pass_all ;; + *) + # glibc up to 2.1.1 does not perform some relocations on ARM + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;; + esac + lt_cv_file_magic_test_file=`echo /lib/libc.so* /lib/libc-*.so` + ;; + +netbsd*) + if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then + lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so\.[0-9]+\.[0-9]+$' + else + lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so$' + fi + ;; + +newsos6) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=/usr/lib/libnls.so + ;; + +osf3* | osf4* | osf5*) + # this will be overridden with pass_all, but let us keep it just in case + lt_cv_deplibs_check_method='file_magic COFF format alpha shared library' + lt_cv_file_magic_test_file=/shlib/libc.so + lt_cv_deplibs_check_method=pass_all + ;; + +sco3.2v5*) + lt_cv_deplibs_check_method=pass_all + ;; + +solaris*) + lt_cv_deplibs_check_method=pass_all + lt_cv_file_magic_test_file=/lib/libc.so + ;; + +sysv5uw[78]* | sysv4*uw2*) + lt_cv_deplibs_check_method=pass_all + ;; + +sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) + case $host_vendor in + ncr) + lt_cv_deplibs_check_method=pass_all + ;; + motorola) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` + ;; + esac + ;; +esac + +fi + +echo "$ac_t""$lt_cv_deplibs_check_method" 1>&6 +file_magic_cmd=$lt_cv_file_magic_cmd +deplibs_check_method=$lt_cv_deplibs_check_method + +echo $ac_n "checking for object suffix""... $ac_c" 1>&6 +echo "configure:1725: checking for object suffix" >&5 +if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + rm -f conftest* +echo 'int i = 1;' > conftest.$ac_ext +if { (eval echo configure:1731: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + for ac_file in conftest.*; do + case $ac_file in + *.c) ;; + *) ac_cv_objext=`echo $ac_file | sed -e s/conftest.//` ;; + esac + done +else + { echo "configure: error: installation or configuration problem; compiler does not work" 1>&2; exit 1; } +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_objext" 1>&6 +OBJEXT=$ac_cv_objext +ac_objext=$ac_cv_objext + + + +echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 +echo "configure:1751: checking for executable suffix" >&5 +if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$CYGWIN" = yes || test "$MINGW32" = yes; then + ac_cv_exeext=.exe +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.$ac_ext + ac_cv_exeext= + if { (eval echo configure:1761: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + for file in conftest.*; do + case $file in + *.c | *.o | *.obj) ;; + *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + else + { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; } + fi + rm -f conftest* + test x"${ac_cv_exeext}" = x && ac_cv_exeext=no +fi +fi + +EXEEXT="" +test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext} +echo "$ac_t""${ac_cv_exeext}" 1>&6 +ac_exeext=$EXEEXT + +# Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers! + +# Only perform the check for file, if the check method requires it +case $deplibs_check_method in +file_magic*) + if test "$file_magic_cmd" = '$MAGIC_CMD'; then + echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6 +echo "configure:1788: checking for ${ac_tool_prefix}file" >&5 +if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case $MAGIC_CMD in + /*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; + ?:/*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path. + ;; + *) + ac_save_MAGIC_CMD="$MAGIC_CMD" + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="/usr/bin:$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/${ac_tool_prefix}file; then + lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`" + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + egrep "$file_magic_regex" > /dev/null; then + : + else + cat <&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +EOF + fi ;; + esac + fi + break + fi + done + IFS="$ac_save_ifs" + MAGIC_CMD="$ac_save_MAGIC_CMD" + ;; +esac +fi + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + echo "$ac_t""$MAGIC_CMD" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$lt_cv_path_MAGIC_CMD"; then + if test -n "$ac_tool_prefix"; then + echo $ac_n "checking for file""... $ac_c" 1>&6 +echo "configure:1850: checking for file" >&5 +if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case $MAGIC_CMD in + /*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; + ?:/*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path. + ;; + *) + ac_save_MAGIC_CMD="$MAGIC_CMD" + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="/usr/bin:$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/file; then + lt_cv_path_MAGIC_CMD="$ac_dir/file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`" + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + egrep "$file_magic_regex" > /dev/null; then + : + else + cat <&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +EOF + fi ;; + esac + fi + break + fi + done + IFS="$ac_save_ifs" + MAGIC_CMD="$ac_save_MAGIC_CMD" + ;; +esac +fi + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + echo "$ac_t""$MAGIC_CMD" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + else + MAGIC_CMD=: + fi +fi + + fi + ;; +esac + +# Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1921: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + +if test -z "$ac_cv_prog_RANLIB"; then +if test -n "$ac_tool_prefix"; then + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1953: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="ranlib" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +else + RANLIB=":" +fi +fi + +# Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. +set dummy ${ac_tool_prefix}strip; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1988: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_STRIP="${ac_tool_prefix}strip" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +STRIP="$ac_cv_prog_STRIP" +if test -n "$STRIP"; then + echo "$ac_t""$STRIP" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + +if test -z "$ac_cv_prog_STRIP"; then +if test -n "$ac_tool_prefix"; then + # Extract the first word of "strip", so it can be a program name with args. +set dummy strip; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2020: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_STRIP="strip" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_STRIP" && ac_cv_prog_STRIP=":" +fi +fi +STRIP="$ac_cv_prog_STRIP" +if test -n "$STRIP"; then + echo "$ac_t""$STRIP" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +else + STRIP=":" +fi +fi + + +# Check for any special flags to pass to ltconfig. +libtool_flags="--cache-file=$cache_file" +test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared" +test "$enable_static" = no && libtool_flags="$libtool_flags --disable-static" +test "$enable_fast_install" = no && libtool_flags="$libtool_flags --disable-fast-install" +test "$GCC" = yes && libtool_flags="$libtool_flags --with-gcc" +test "$lt_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld" + + +# Check whether --enable-libtool-lock or --disable-libtool-lock was given. +if test "${enable_libtool_lock+set}" = set; then + enableval="$enable_libtool_lock" + : +fi + +test "x$enable_libtool_lock" = xno && libtool_flags="$libtool_flags --disable-lock" +test x"$silent" = xyes && libtool_flags="$libtool_flags --silent" + +# Check whether --with-pic or --without-pic was given. +if test "${with_pic+set}" = set; then + withval="$with_pic" + pic_mode="$withval" +else + pic_mode=default +fi + +test x"$pic_mode" = xyes && libtool_flags="$libtool_flags --prefer-pic" +test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic" + +# Some flags need to be propagated to the compiler or linker for good +# libtool support. +case $host in +*-*-irix6*) + # Find out which ABI we are using. + echo '#line 2087 "configure"' > conftest.$ac_ext + if { (eval echo configure:2088: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -32" + ;; + *N32*) + LD="${LD-ld} -n32" + ;; + *64-bit*) + LD="${LD-ld} -64" + ;; + esac + fi + rm -rf conftest* + ;; + +ia64-*-hpux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { (eval echo configure:2107: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + case "`/usr/bin/file conftest.o`" in + *ELF-32*) + HPUX_IA64_MODE="32" + ;; + *ELF-64*) + HPUX_IA64_MODE="64" + ;; + esac + fi + rm -rf conftest* + ;; + +*-*-sco3.2v5*) + # On SCO OpenServer 5, we need -belf to get full-featured binaries. + SAVE_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -belf" + echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6 +echo "configure:2125: checking whether the C compiler needs -belf" >&5 +if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + + ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + lt_cv_cc_needs_belf=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + lt_cv_cc_needs_belf=no +fi +rm -f conftest* + ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +fi + +echo "$ac_t""$lt_cv_cc_needs_belf" 1>&6 + if test x"$lt_cv_cc_needs_belf" != x"yes"; then + # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf + CFLAGS="$SAVE_CFLAGS" + fi + ;; + + +esac + + +# Save cache, so that ltconfig can load it +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set | grep ac_space) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + + +# Actually configure libtool. ac_aux_dir is where install-sh is found. +AR="$AR" LTCC="$CC" CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \ +MAGIC_CMD="$MAGIC_CMD" LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \ +LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" STRIP="$STRIP" \ +AS="$AS" DLLTOOL="$DLLTOOL" OBJDUMP="$OBJDUMP" \ +objext="$OBJEXT" exeext="$EXEEXT" reload_flag="$reload_flag" \ +deplibs_check_method="$deplibs_check_method" file_magic_cmd="$file_magic_cmd" \ +${CONFIG_SHELL-/bin/sh} $ac_aux_dir/ltconfig --no-reexec \ +$libtool_flags --no-verify --build="$build" $ac_aux_dir/ltmain.sh $host \ +|| { echo "configure: error: libtool configure failed" 1>&2; exit 1; } + +# Reload cache, that may have been modified by ltconfig +if test -r "$cache_file"; then + echo "loading cache $cache_file" + . $cache_file +else + echo "creating cache $cache_file" + > $cache_file +fi + + +# This can be used to rebuild libtool when needed +LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh $ac_aux_dir/ltcf-c.sh" + +# Always use our own libtool. +LIBTOOL='$(SHELL) $(top_builddir)/libtool' + +# Redirect the config.log output again, so that the ltconfig log is not +# clobbered by the next message. +exec 5>>./config.log + + + + + + + +# Check whether --enable-targets or --disable-targets was given. +if test "${enable_targets+set}" = set; then + enableval="$enable_targets" + case "${enableval}" in + yes | "") { echo "configure: error: enable-targets option must specify target names or 'all'" 1>&2; exit 1; } + ;; + no) enable_targets= ;; + *) enable_targets=$enableval ;; +esac +fi +# Check whether --enable-commonbfdlib or --disable-commonbfdlib was given. +if test "${enable_commonbfdlib+set}" = set; then + enableval="$enable_commonbfdlib" + case "${enableval}" in + yes) commonbfdlib=true ;; + no) commonbfdlib=false ;; + *) { echo "configure: error: bad value ${enableval} for opcodes commonbfdlib option" 1>&2; exit 1; } ;; +esac +fi + +build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +# Check whether --enable-build-warnings or --disable-build-warnings was given. +if test "${enable_build_warnings+set}" = set; then + enableval="$enable_build_warnings" + case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting warning flags = $build_warnings" 6>&1 +fi +fi +WARN_CFLAGS="" +if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then + WARN_CFLAGS="${build_warnings}" +fi + + + + + + +if test -z "$target" ; then + { echo "configure: error: Unrecognized target system type; please check config.sub." 1>&2; exit 1; } +fi + +echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 +echo "configure:2313: checking whether to enable maintainer-specific portions of Makefiles" >&5 + # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then + enableval="$enable_maintainer_mode" + USE_MAINTAINER_MODE=$enableval +else + USE_MAINTAINER_MODE=no +fi + + echo "$ac_t""$USE_MAINTAINER_MODE" 1>&6 + + +if test $USE_MAINTAINER_MODE = yes; then + MAINTAINER_MODE_TRUE= + MAINTAINER_MODE_FALSE='#' +else + MAINTAINER_MODE_TRUE='#' + MAINTAINER_MODE_FALSE= +fi + MAINT=$MAINTAINER_MODE_TRUE + + +echo $ac_n "checking whether to install libbfd""... $ac_c" 1>&6 +echo "configure:2336: checking whether to install libbfd" >&5 + # Check whether --enable-install-libbfd or --disable-install-libbfd was given. +if test "${enable_install_libbfd+set}" = set; then + enableval="$enable_install_libbfd" + install_libbfd_p=$enableval +else + if test "${host}" = "${target}" -o "$enable_shared" = "yes"; then + install_libbfd_p=yes + else + install_libbfd_p=no + fi +fi + + echo "$ac_t""$install_libbfd_p" 1>&6 + + +if test $install_libbfd_p = yes; then + INSTALL_LIBBFD_TRUE= + INSTALL_LIBBFD_FALSE='#' +else + INSTALL_LIBBFD_TRUE='#' + INSTALL_LIBBFD_FALSE= +fi + # libbfd.a is a host library containing target dependent code + bfdlibdir='$(libdir)' + bfdincludedir='$(includedir)' + if test "${host}" != "${target}"; then + bfdlibdir='$(exec_prefix)/$(host_alias)/$(target_alias)/lib' + bfdincludedir='$(exec_prefix)/$(host_alias)/$(target_alias)/include' + fi + + + + + + +echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 +echo "configure:2373: checking for executable suffix" >&5 +if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$CYGWIN" = yes || test "$MINGW32" = yes; then + ac_cv_exeext=.exe +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.$ac_ext + ac_cv_exeext= + if { (eval echo configure:2383: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + for file in conftest.*; do + case $file in + *.c | *.o | *.obj) ;; + *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + else + { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; } + fi + rm -f conftest* + test x"${ac_cv_exeext}" = x && ac_cv_exeext=no +fi +fi + +EXEEXT="" +test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext} +echo "$ac_t""${ac_cv_exeext}" 1>&6 +ac_exeext=$EXEEXT + + +# host-specific stuff: + +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2409: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2439: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2490: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:2522: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 2533 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:2538: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:2564: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:2569: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:2597: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + + +ALL_LINGUAS="fr sv tr es da de id" +echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 +echo "configure:2631: checking how to run the C preprocessor" >&5 +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then +if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + # This must be in double quotes, not single quotes, because CPP may get + # substituted into the Makefile and "${CC-cc}" will confuse make. + CPP="${CC-cc} -E" + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2652: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -E -traditional-cpp" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2669: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -nologo -E" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2686: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP=/lib/cpp +fi +rm -f conftest* +fi +rm -f conftest* +fi +rm -f conftest* + ac_cv_prog_CPP="$CPP" +fi + CPP="$ac_cv_prog_CPP" +else + ac_cv_prog_CPP="$CPP" +fi +echo "$ac_t""$CPP" 1>&6 + +# Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2713: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="ranlib" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 +echo "configure:2741: checking for ANSI C header files" >&5 +if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#include +#include +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2754: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + ac_cv_header_stdc=yes +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "memchr" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "free" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. +if test "$cross_compiling" = yes; then + : +else + cat > conftest.$ac_ext < +#define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int main () { int i; for (i = 0; i < 256; i++) +if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); +exit (0); } + +EOF +if { (eval echo configure:2821: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + : +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_header_stdc=no +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_header_stdc" 1>&6 +if test $ac_cv_header_stdc = yes; then + cat >> confdefs.h <<\EOF +#define STDC_HEADERS 1 +EOF + +fi + +echo $ac_n "checking for working const""... $ac_c" 1>&6 +echo "configure:2845: checking for working const" >&5 +if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <j = 5; +} +{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; +} + +; return 0; } +EOF +if { (eval echo configure:2899: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_const=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_const=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_c_const" 1>&6 +if test $ac_cv_c_const = no; then + cat >> confdefs.h <<\EOF +#define const +EOF + +fi + +echo $ac_n "checking for inline""... $ac_c" 1>&6 +echo "configure:2920: checking for inline" >&5 +if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_inline=no +for ac_kw in inline __inline__ __inline; do + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_inline=$ac_kw; break +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +done + +fi + +echo "$ac_t""$ac_cv_c_inline" 1>&6 +case "$ac_cv_c_inline" in + inline | yes) ;; + no) cat >> confdefs.h <<\EOF +#define inline +EOF + ;; + *) cat >> confdefs.h <&6 +echo "configure:2960: checking for off_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_off_t=yes +else + rm -rf conftest* + ac_cv_type_off_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_off_t" 1>&6 +if test $ac_cv_type_off_t = no; then + cat >> confdefs.h <<\EOF +#define off_t long +EOF + +fi + +echo $ac_n "checking for size_t""... $ac_c" 1>&6 +echo "configure:2993: checking for size_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_size_t=yes +else + rm -rf conftest* + ac_cv_type_size_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_size_t" 1>&6 +if test $ac_cv_type_size_t = no; then + cat >> confdefs.h <<\EOF +#define size_t unsigned +EOF + +fi + +# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works +# for constant arguments. Useless! +echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 +echo "configure:3028: checking for working alloca.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +char *p = alloca(2 * sizeof(int)); +; return 0; } +EOF +if { (eval echo configure:3040: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_header_alloca_h=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_alloca_h=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_header_alloca_h" 1>&6 +if test $ac_cv_header_alloca_h = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA_H 1 +EOF + +fi + +echo $ac_n "checking for alloca""... $ac_c" 1>&6 +echo "configure:3061: checking for alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +# define alloca _alloca +# else +# if HAVE_ALLOCA_H +# include +# else +# ifdef _AIX + #pragma alloca +# else +# ifndef alloca /* predefined by HP cc +Olibcalls */ +char *alloca (); +# endif +# endif +# endif +# endif +#endif + +int main() { +char *p = (char *) alloca(1); +; return 0; } +EOF +if { (eval echo configure:3094: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_func_alloca_works=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_func_alloca_works=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_func_alloca_works" 1>&6 +if test $ac_cv_func_alloca_works = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA 1 +EOF + +fi + +if test $ac_cv_func_alloca_works = no; then + # The SVR3 libPW and SVR4 libucb both contain incompatible functions + # that cause trouble. Some versions do not even contain alloca or + # contain a buggy version. If you still want to use their alloca, + # use ar to extract alloca.o from them instead of compiling alloca.c. + ALLOCA=alloca.${ac_objext} + cat >> confdefs.h <<\EOF +#define C_ALLOCA 1 +EOF + + +echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 +echo "configure:3126: checking whether alloca needs Cray hooks" >&5 +if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5 | + egrep "webecray" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_os_cray=yes +else + rm -rf conftest* + ac_cv_os_cray=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_os_cray" 1>&6 +if test $ac_cv_os_cray = yes; then +for ac_func in _getb67 GETB67 getb67; do + echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3156: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3184: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + cat >> confdefs.h <&6 +fi + +done +fi + +echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 +echo "configure:3211: checking stack direction for C alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_c_stack_direction=0 +else + cat > conftest.$ac_ext < addr) ? 1 : -1; +} +main () +{ + exit (find_stack_direction() < 0); +} +EOF +if { (eval echo configure:3238: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_stack_direction=1 +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_stack_direction=-1 +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_c_stack_direction" 1>&6 +cat >> confdefs.h <&6 +echo "configure:3263: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3273: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getpagesize +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3302: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3330: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + +echo $ac_n "checking for working mmap""... $ac_c" 1>&6 +echo "configure:3355: checking for working mmap" >&5 +if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_func_mmap_fixed_mapped=no +else + cat > conftest.$ac_ext < +#include +#include + +#if HAVE_SYS_TYPES_H +# include +#endif + +#if HAVE_STDLIB_H +# include +#endif + +#if HAVE_SYS_STAT_H +# include +#endif + +#if HAVE_UNISTD_H +# include +#endif + +/* This mess was copied from the GNU getpagesize.h. */ +#ifndef HAVE_GETPAGESIZE + +/* Assume that all systems that can run configure have sys/param.h. */ +# ifndef HAVE_SYS_PARAM_H +# define HAVE_SYS_PARAM_H 1 +# endif + +# ifdef _SC_PAGESIZE +# define getpagesize() sysconf(_SC_PAGESIZE) +# else /* no _SC_PAGESIZE */ +# ifdef HAVE_SYS_PARAM_H +# include +# ifdef EXEC_PAGESIZE +# define getpagesize() EXEC_PAGESIZE +# else /* no EXEC_PAGESIZE */ +# ifdef NBPG +# define getpagesize() NBPG * CLSIZE +# ifndef CLSIZE +# define CLSIZE 1 +# endif /* no CLSIZE */ +# else /* no NBPG */ +# ifdef NBPC +# define getpagesize() NBPC +# else /* no NBPC */ +# ifdef PAGESIZE +# define getpagesize() PAGESIZE +# endif /* PAGESIZE */ +# endif /* no NBPC */ +# endif /* no NBPG */ +# endif /* no EXEC_PAGESIZE */ +# else /* no HAVE_SYS_PARAM_H */ +# define getpagesize() 8192 /* punt totally */ +# endif /* no HAVE_SYS_PARAM_H */ +# endif /* no _SC_PAGESIZE */ + +#endif /* no HAVE_GETPAGESIZE */ + +#ifdef __cplusplus +extern "C" { void *malloc(unsigned); } +#else +char *malloc(); +#endif + +int +main() +{ + char *data, *data2, *data3; + int i, pagesize; + int fd; + + pagesize = getpagesize(); + + /* + * First, make a file with some known garbage in it. + */ + data = malloc(pagesize); + if (!data) + exit(1); + for (i = 0; i < pagesize; ++i) + *(data + i) = rand(); + umask(0); + fd = creat("conftestmmap", 0600); + if (fd < 0) + exit(1); + if (write(fd, data, pagesize) != pagesize) + exit(1); + close(fd); + + /* + * Next, try to mmap the file at a fixed address which + * already has something else allocated at it. If we can, + * also make sure that we see the same garbage. + */ + fd = open("conftestmmap", O_RDWR); + if (fd < 0) + exit(1); + data2 = malloc(2 * pagesize); + if (!data2) + exit(1); + data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1); + if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_FIXED, fd, 0L)) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data2 + i)) + exit(1); + + /* + * Finally, make sure that changes to the mapped area + * do not percolate back to the file as seen by read(). + * (This is a bug on some variants of i386 svr4.0.) + */ + for (i = 0; i < pagesize; ++i) + *(data2 + i) = *(data2 + i) + 1; + data3 = malloc(pagesize); + if (!data3) + exit(1); + if (read(fd, data3, pagesize) != pagesize) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data3 + i)) + exit(1); + close(fd); + unlink("conftestmmap"); + exit(0); +} + +EOF +if { (eval echo configure:3516: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_func_mmap_fixed_mapped=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_func_mmap_fixed_mapped=no +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6 +if test $ac_cv_func_mmap_fixed_mapped = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_MMAP 1 +EOF + +fi + + + for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \ +unistd.h values.h sys/param.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3544: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3554: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \ +__argz_count __argz_stringify __argz_next +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3584: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3612: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + + if test "${ac_cv_func_stpcpy+set}" != "set"; then + for ac_func in stpcpy +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3641: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3669: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + fi + if test "${ac_cv_func_stpcpy}" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_STPCPY 1 +EOF + + fi + + if test $ac_cv_header_locale_h = yes; then + echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 +echo "configure:3703: checking for LC_MESSAGES" >&5 +if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return LC_MESSAGES +; return 0; } +EOF +if { (eval echo configure:3715: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + am_cv_val_LC_MESSAGES=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + am_cv_val_LC_MESSAGES=no +fi +rm -f conftest* +fi + +echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6 + if test $am_cv_val_LC_MESSAGES = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_LC_MESSAGES 1 +EOF + + fi + fi + echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 +echo "configure:3736: checking whether NLS is requested" >&5 + # Check whether --enable-nls or --disable-nls was given. +if test "${enable_nls+set}" = set; then + enableval="$enable_nls" + USE_NLS=$enableval +else + USE_NLS=yes +fi + + echo "$ac_t""$USE_NLS" 1>&6 + + + USE_INCLUDED_LIBINTL=no + + if test "$USE_NLS" = "yes"; then + cat >> confdefs.h <<\EOF +#define ENABLE_NLS 1 +EOF + + echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 +echo "configure:3756: checking whether included gettext is requested" >&5 + # Check whether --with-included-gettext or --without-included-gettext was given. +if test "${with_included_gettext+set}" = set; then + withval="$with_included_gettext" + nls_cv_force_use_gnu_gettext=$withval +else + nls_cv_force_use_gnu_gettext=no +fi + + echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6 + + nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext" + if test "$nls_cv_force_use_gnu_gettext" != "yes"; then + nls_cv_header_intl= + nls_cv_header_libgt= + CATOBJEXT=NONE + + ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 +echo "configure:3775: checking for libintl.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3785: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 +echo "configure:3802: checking for gettext in libc" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return (int) gettext ("") +; return 0; } +EOF +if { (eval echo configure:3814: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libc=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libc=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 + + if test "$gt_cv_func_gettext_libc" != "yes"; then + echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 +echo "configure:3830: checking for bindtextdomain in -lintl" >&5 +ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lintl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 +echo "configure:3865: checking for gettext in libintl" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libintl=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libintl=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + fi + + if test "$gt_cv_func_gettext_libc" = "yes" \ + || test "$gt_cv_func_gettext_libintl" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_GETTEXT 1 +EOF + + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:3905: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + if test "$MSGFMT" != "no"; then + for ac_func in dcgettext +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3939: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3967: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:3994: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:4030: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + CATOBJEXT=.gmo + DATADIRNAME=share +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CATOBJEXT=.mo + DATADIRNAME=lib +fi +rm -f conftest* + INSTOBJEXT=.mo + fi + fi + +else + echo "$ac_t""no" 1>&6 +fi + + + + if test "$CATOBJEXT" = "NONE"; then + nls_cv_use_gnu_gettext=yes + fi + fi + + if test "$nls_cv_use_gnu_gettext" = "yes"; then + INTLOBJS="\$(GETTOBJS)" + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:4102: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:4136: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:4172: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + + USE_INCLUDED_LIBINTL=yes + CATOBJEXT=.gmo + INSTOBJEXT=.mo + DATADIRNAME=share + INTLDEPS='$(top_builddir)/../intl/libintl.a' + INTLLIBS=$INTLDEPS + LIBS=`echo $LIBS | sed -e 's/-lintl//'` + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + if test "$XGETTEXT" != ":"; then + if $XGETTEXT --omit-header /dev/null 2> /dev/null; then + : ; + else + echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6 + XGETTEXT=":" + fi + fi + + # We need to process the po/ directory. + POSUB=po + else + DATADIRNAME=share + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + # If this is used in GNU gettext we have to set USE_NLS to `yes' + # because some of the sources are only built for this goal. + if test "$PACKAGE" = gettext; then + USE_NLS=yes + USE_INCLUDED_LIBINTL=yes + fi + + for lang in $ALL_LINGUAS; do + GMOFILES="$GMOFILES $lang.gmo" + POFILES="$POFILES $lang.po" + done + + + + + + + + + + + + + + + if test "x$CATOBJEXT" != "x"; then + if test "x$ALL_LINGUAS" = "x"; then + LINGUAS= + else + echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 +echo "configure:4262: checking for catalogs to be installed" >&5 + NEW_LINGUAS= + for lang in ${LINGUAS=$ALL_LINGUAS}; do + case "$ALL_LINGUAS" in + *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;; + esac + done + LINGUAS=$NEW_LINGUAS + echo "$ac_t""$LINGUAS" 1>&6 + fi + + if test -n "$LINGUAS"; then + for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done + fi + fi + + if test $ac_cv_header_locale_h = yes; then + INCLUDE_LOCALE_H="#include " + else + INCLUDE_LOCALE_H="\ +/* The system does not provide the header . Take care yourself. */" + fi + + + if test -f $srcdir/po2tbl.sed.in; then + if test "$CATOBJEXT" = ".cat"; then + ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 +echo "configure:4290: checking for linux/version.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:4300: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + msgformat=linux +else + echo "$ac_t""no" 1>&6 +msgformat=xopen +fi + + + sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed + fi + sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \ + $srcdir/po2tbl.sed.in > po2tbl.sed + fi + + if test "$PACKAGE" = "gettext"; then + GT_NO="#NO#" + GT_YES= + else + GT_NO= + GT_YES="#YES#" + fi + + + + MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs" + + + l= + + + if test -f $srcdir/po/POTFILES.in; then + test -d po || mkdir po + if test "x$srcdir" != "x."; then + if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then + posrcprefix="$srcdir/" + else + posrcprefix="../$srcdir/" + fi + else + posrcprefix="../" + fi + rm -f po/POTFILES + sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \ + < $srcdir/po/POTFILES.in > po/POTFILES + fi + + +. ${srcdir}/../bfd/configure.host + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test -z "$CC_FOR_BUILD"; then + if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' + else + CC_FOR_BUILD=gcc + fi +fi + +# Also set EXEEXT_FOR_BUILD. +if test "x$cross_compiling" = "xno"; then + EXEEXT_FOR_BUILD='$(EXEEXT)' +else + echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6 +echo "configure:4378: checking for build system executable suffix" >&5 +if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.c + bfd_cv_build_exeext= + ${CC_FOR_BUILD} -o conftest conftest.c 1>&5 2>&5 + for file in conftest.*; do + case $file in + *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *) bfd_cv_build_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + rm -f conftest* + test x"${bfd_cv_build_exeext}" = x && bfd_cv_build_exeext=no +fi + +echo "$ac_t""$bfd_cv_build_exeext" 1>&6 + EXEEXT_FOR_BUILD="" + test x"${bfd_cv_build_exeext}" != xno && EXEEXT_FOR_BUILD=${bfd_cv_build_exeext} +fi + + + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# ./install, which can be erroneously created by make from ./install.sh. +echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 +echo "configure:4415: checking for a BSD compatible install" >&5 +if test -z "$INSTALL"; then +if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS=":" + for ac_dir in $PATH; do + # Account for people who put trailing slashes in PATH elements. + case "$ac_dir/" in + /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + if test -f $ac_dir/$ac_prog; then + if test $ac_prog = install && + grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + else + ac_cv_path_install="$ac_dir/$ac_prog -c" + break 2 + fi + fi + done + ;; + esac + done + IFS="$ac_save_IFS" + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL="$ac_cv_path_install" + else + # As a last resort, use the slow shell script. We don't cache a + # path for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the path is relative. + INSTALL="$ac_install_sh" + fi +fi +echo "$ac_t""$INSTALL" 1>&6 + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +for ac_hdr in string.h strings.h stdlib.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:4472: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:4482: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + +cgen_maint=no +cgendir='$(srcdir)/../cgen' + +# Check whether --enable-cgen-maint or --disable-cgen-maint was given. +if test "${enable_cgen_maint+set}" = set; then + enableval="$enable_cgen_maint" + case "${enableval}" in + yes) cgen_maint=yes ;; + no) cgen_maint=no ;; + *) + # argument is cgen install directory (not implemented yet). + # Having a `share' directory might be more appropriate for the .scm, + # .cpu, etc. files. + cgen_maint=yes + cgendir=${cgen_maint}/lib/cgen + ;; +esac +fi + + +if test x${cgen_maint} = xyes; then + CGEN_MAINT_TRUE= + CGEN_MAINT_FALSE='#' +else + CGEN_MAINT_TRUE='#' + CGEN_MAINT_FALSE= +fi + + +using_cgen=no + +# Horrible hacks to build DLLs on Windows. +WIN32LDFLAGS= +WIN32LIBADD= +case "${host}" in +*-*-cygwin*) + if test "$enable_shared" = "yes"; then + WIN32LDFLAGS="-no-undefined" + WIN32LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" + fi + ;; +esac + + + +# target-specific stuff: + +# Canonicalize the secondary target names. +if test -n "$enable_targets" ; then + for targ in `echo $enable_targets | sed 's/,/ /g'` + do + result=`$ac_config_sub $targ 2>/dev/null` + if test -n "$result" ; then + canon_targets="$canon_targets $result" + else + # Allow targets that config.sub doesn't recognize, like "all". + canon_targets="$canon_targets $targ" + fi + done +fi + +all_targets=false +selarchs= +for targ in $target $canon_targets +do + if test "x$targ" = "xall" ; then + all_targets=true + else + . $srcdir/../bfd/config.bfd + selarchs="$selarchs $targ_archs" + fi +done + +# Utility var, documents generic cgen support files. + +cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo" + +# We don't do any links based on the target system, just makefile config. + +if test x${all_targets} = xfalse ; then + + # Target architecture .o files. + ta= + + for arch in $selarchs + do + ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` + archdefs="$archdefs -DARCH_$ad" + case "$arch" in + bfd_a29k_arch) ta="$ta a29k-dis.lo" ;; + bfd_alliant_arch) ;; + bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; + bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arm_arch) ta="$ta arm-dis.lo" ;; + bfd_avr_arch) ta="$ta avr-dis.lo" ;; + bfd_convex_arch) ;; + bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo" ;; + bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; + bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; + bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; + bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; + bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; + bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; + bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; + bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; + bfd_i386_arch) ta="$ta i386-dis.lo" ;; + bfd_i860_arch) ta="$ta i860-dis.lo" ;; + bfd_i960_arch) ta="$ta i960-dis.lo" ;; + bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; + bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; + bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; + bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; + bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; + bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; + bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; + bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; + bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; + bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; + bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; + bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_pyramid_arch) ;; + bfd_romp_arch) ;; + bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; + bfd_sh_arch) + # We can't decide what we want just from the CPU family. + # We want SH5 support unless a specific version of sh is + # specified, as in sh3-elf, sh3b-linux-gnu, etc. + # Include it just for ELF targets, since the SH5 bfd:s are ELF only. + for t in $target $canon_targets; do + case $t in + all | sh64-* | sh-*-*elf* | shl-*-*elf* | shle-*-*elf* | \ + sh-*-linux* | shl-*-linux*) + ta="$ta sh64-dis.lo sh64-opc.lo" + archdefs="$archdefs -DINCLUDE_SHMEDIA" + break;; + esac; + done + ta="$ta sh-dis.lo" ;; + bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; + bfd_tahoe_arch) ;; + bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; + bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; + bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_vax_arch) ta="$ta vax-dis.lo" ;; + bfd_w65_arch) ta="$ta w65-dis.lo" ;; + bfd_we32k_arch) ;; + bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; + bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + + "") ;; + *) { echo "configure: error: *** unknown target architecture $arch" 1>&2; exit 1; } ;; + esac + done + + if test $using_cgen = yes ; then + ta="$ta $cgen_files" + fi + + # Weed out duplicate .o files. + f="" + for i in $ta ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + ta="$f" + + # And duplicate -D flags. + f="" + for i in $archdefs ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + archdefs="$f" + + BFD_MACHINES="$ta" + +else # all_targets is true + archdefs=-DARCH_all + BFD_MACHINES='$(ALL_MACHINES)' +fi + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set | grep ac_space) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +DEFS=-DHAVE_CONFIG_H + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS </dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.13" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir +ac_given_INSTALL="$INSTALL" + +trap 'rm -fr `echo "Makefile po/Makefile.in:po/Make-in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS < conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g +s%@CC@%$CC%g +s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g +s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g +s%@INSTALL_DATA@%$INSTALL_DATA%g +s%@PACKAGE@%$PACKAGE%g +s%@VERSION@%$VERSION%g +s%@ACLOCAL@%$ACLOCAL%g +s%@AUTOCONF@%$AUTOCONF%g +s%@AUTOMAKE@%$AUTOMAKE%g +s%@AUTOHEADER@%$AUTOHEADER%g +s%@MAKEINFO@%$MAKEINFO%g +s%@SET_MAKE@%$SET_MAKE%g +s%@AR@%$AR%g +s%@RANLIB@%$RANLIB%g +s%@LN_S@%$LN_S%g +s%@OBJEXT@%$OBJEXT%g +s%@EXEEXT@%$EXEEXT%g +s%@STRIP@%$STRIP%g +s%@LIBTOOL@%$LIBTOOL%g +s%@WARN_CFLAGS@%$WARN_CFLAGS%g +s%@MAINTAINER_MODE_TRUE@%$MAINTAINER_MODE_TRUE%g +s%@MAINTAINER_MODE_FALSE@%$MAINTAINER_MODE_FALSE%g +s%@MAINT@%$MAINT%g +s%@INSTALL_LIBBFD_TRUE@%$INSTALL_LIBBFD_TRUE%g +s%@INSTALL_LIBBFD_FALSE@%$INSTALL_LIBBFD_FALSE%g +s%@bfdlibdir@%$bfdlibdir%g +s%@bfdincludedir@%$bfdincludedir%g +s%@CPP@%$CPP%g +s%@ALLOCA@%$ALLOCA%g +s%@USE_NLS@%$USE_NLS%g +s%@MSGFMT@%$MSGFMT%g +s%@GMSGFMT@%$GMSGFMT%g +s%@XGETTEXT@%$XGETTEXT%g +s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g +s%@CATALOGS@%$CATALOGS%g +s%@CATOBJEXT@%$CATOBJEXT%g +s%@DATADIRNAME@%$DATADIRNAME%g +s%@GMOFILES@%$GMOFILES%g +s%@INSTOBJEXT@%$INSTOBJEXT%g +s%@INTLDEPS@%$INTLDEPS%g +s%@INTLLIBS@%$INTLLIBS%g +s%@INTLOBJS@%$INTLOBJS%g +s%@POFILES@%$POFILES%g +s%@POSUB@%$POSUB%g +s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g +s%@GT_NO@%$GT_NO%g +s%@GT_YES@%$GT_YES%g +s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g +s%@l@%$l%g +s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g +s%@EXEEXT_FOR_BUILD@%$EXEEXT_FOR_BUILD%g +s%@HDEFINES@%$HDEFINES%g +s%@CGEN_MAINT_TRUE@%$CGEN_MAINT_TRUE%g +s%@CGEN_MAINT_FALSE@%$CGEN_MAINT_FALSE%g +s%@cgendir@%$cgendir%g +s%@WIN32LDFLAGS@%$WIN32LDFLAGS%g +s%@WIN32LIBADD@%$WIN32LIBADD%g +s%@archdefs@%$archdefs%g +s%@BFD_MACHINES@%$BFD_MACHINES%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + case "$ac_given_INSTALL" in + [/$]*) INSTALL="$ac_given_INSTALL" ;; + *) INSTALL="$ac_dots$ac_given_INSTALL" ;; + esac + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +s%@INSTALL@%$INSTALL%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where +# NAME is the cpp macro being defined and VALUE is the value it is being given. +# +# ac_d sets the value in "#define NAME VALUE" lines. +ac_dA='s%^\([ ]*\)#\([ ]*define[ ][ ]*\)' +ac_dB='\([ ][ ]*\)[^ ]*%\1#\2' +ac_dC='\3' +ac_dD='%g' +# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE". +ac_uA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_uB='\([ ]\)%\1#\2define\3' +ac_uC=' ' +ac_uD='\4%g' +# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE". +ac_eA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_eB='$%\1#\2define\3' +ac_eC=' ' +ac_eD='%g' + +if test "${CONFIG_HEADERS+set}" != set; then +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +fi +for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + echo creating $ac_file + + rm -f conftest.frag conftest.in conftest.out + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + cat $ac_file_inputs > conftest.in + +EOF + +# Transform confdefs.h into a sed script conftest.vals that substitutes +# the proper values into config.h.in to produce config.h. And first: +# Protect against being on the right side of a sed subst in config.status. +# Protect against being in an unquoted here document in config.status. +rm -f conftest.vals +cat > conftest.hdr <<\EOF +s/[\\&%]/\\&/g +s%[\\$`]%\\&%g +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp +s%ac_d%ac_u%gp +s%ac_u%ac_e%gp +EOF +sed -n -f conftest.hdr confdefs.h > conftest.vals +rm -f conftest.hdr + +# This sed command replaces #undef with comments. This is necessary, for +# example, in the case of _POSIX_SOURCE, which is predefined and required +# on some systems where configure will not decide to define it. +cat >> conftest.vals <<\EOF +s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */% +EOF + +# Break up conftest.vals because some shells have a limit on +# the size of here documents, and old seds have small limits too. + +rm -f conftest.tail +while : +do + ac_lines=`grep -c . conftest.vals` + # grep -c gives empty output for an empty file on some AIX systems. + if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi + # Write a limited-size here document to conftest.frag. + echo ' cat > conftest.frag <> $CONFIG_STATUS + sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS + echo 'CEOF + sed -f conftest.frag conftest.in > conftest.out + rm -f conftest.in + mv conftest.out conftest.in +' >> $CONFIG_STATUS + sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail + rm -f conftest.vals + mv conftest.tail conftest.vals +done +rm -f conftest.vals + +cat >> $CONFIG_STATUS <<\EOF + rm -f conftest.frag conftest.h + echo "/* $ac_file. Generated automatically by configure. */" > conftest.h + cat conftest.in >> conftest.h + rm -f conftest.in + if cmp -s $ac_file conftest.h 2>/dev/null; then + echo "$ac_file is unchanged" + rm -f conftest.h + else + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + fi + rm -f $ac_file + mv conftest.h $ac_file + fi +fi; done + +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +test -z "$CONFIG_HEADERS" || echo timestamp > stamp-h +sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + diff --git a/opcodes/configure.in b/opcodes/configure.in new file mode 100644 index 0000000..96e5a6b --- /dev/null +++ b/opcodes/configure.in @@ -0,0 +1,282 @@ +dnl Process this file with autoconf to produce a configure script. +dnl + +AC_PREREQ(2.13) +AC_INIT(z8k-dis.c) + +AC_CANONICAL_SYSTEM +AC_ISC_POSIX + +# We currently only use the version number for the name of any shared +# library. For user convenience, we always use the same version +# number that BFD is using. +changequote(,)dnl +BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${srcdir}/../bfd/configure.in` +changequote([,])dnl + +AM_INIT_AUTOMAKE(opcodes, ${BFD_VERSION}) + +dnl These must be called before AM_PROG_LIBTOOL, because it may want +dnl to call AC_CHECK_PROG. +AC_CHECK_TOOL(AR, ar) +AC_CHECK_TOOL(RANLIB, ranlib, :) + +dnl Default to a non shared library. This may be overridden by the +dnl configure option --enable-shared. +AM_DISABLE_SHARED + +AM_PROG_LIBTOOL + +AC_ARG_ENABLE(targets, +[ --enable-targets alternative target configurations], +[case "${enableval}" in + yes | "") AC_ERROR(enable-targets option must specify target names or 'all') + ;; + no) enable_targets= ;; + *) enable_targets=$enableval ;; +esac])dnl +AC_ARG_ENABLE(commonbfdlib, +[ --enable-commonbfdlib build shared BFD/opcodes/libiberty library], +[case "${enableval}" in + yes) commonbfdlib=true ;; + no) commonbfdlib=false ;; + *) AC_MSG_ERROR([bad value ${enableval} for opcodes commonbfdlib option]) ;; +esac])dnl + +build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +AC_ARG_ENABLE(build-warnings, +[ --enable-build-warnings Enable build-time compiler warnings if gcc is used], +[case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting warning flags = $build_warnings" 6>&1 +fi])dnl +WARN_CFLAGS="" +if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then + WARN_CFLAGS="${build_warnings}" +fi +AC_SUBST(WARN_CFLAGS) + +AM_CONFIG_HEADER(config.h:config.in) + +if test -z "$target" ; then + AC_MSG_ERROR(Unrecognized target system type; please check config.sub.) +fi + +AM_MAINTAINER_MODE +AM_INSTALL_LIBBFD +AC_EXEEXT + +# host-specific stuff: + +AC_PROG_CC + +ALL_LINGUAS="fr sv tr es da de id" +CY_GNU_GETTEXT + +. ${srcdir}/../bfd/configure.host + +BFD_CC_FOR_BUILD + +AC_SUBST(HDEFINES) +AC_PROG_INSTALL + +AC_CHECK_HEADERS(string.h strings.h stdlib.h) + +cgen_maint=no +cgendir='$(srcdir)/../cgen' + +AC_ARG_ENABLE(cgen-maint, +[ --enable-cgen-maint[=dir] build cgen generated files], +[case "${enableval}" in + yes) cgen_maint=yes ;; + no) cgen_maint=no ;; + *) + # argument is cgen install directory (not implemented yet). + # Having a `share' directory might be more appropriate for the .scm, + # .cpu, etc. files. + cgen_maint=yes + cgendir=${cgen_maint}/lib/cgen + ;; +esac])dnl +AM_CONDITIONAL(CGEN_MAINT, test x${cgen_maint} = xyes) +AC_SUBST(cgendir) + +using_cgen=no + +# Horrible hacks to build DLLs on Windows. +WIN32LDFLAGS= +WIN32LIBADD= +case "${host}" in +*-*-cygwin*) + if test "$enable_shared" = "yes"; then + WIN32LDFLAGS="-no-undefined" + WIN32LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" + fi + ;; +esac +AC_SUBST(WIN32LDFLAGS) +AC_SUBST(WIN32LIBADD) + +# target-specific stuff: + +# Canonicalize the secondary target names. +if test -n "$enable_targets" ; then + for targ in `echo $enable_targets | sed 's/,/ /g'` + do + result=`$ac_config_sub $targ 2>/dev/null` + if test -n "$result" ; then + canon_targets="$canon_targets $result" + else + # Allow targets that config.sub doesn't recognize, like "all". + canon_targets="$canon_targets $targ" + fi + done +fi + +all_targets=false +selarchs= +for targ in $target $canon_targets +do + if test "x$targ" = "xall" ; then + all_targets=true + else + . $srcdir/../bfd/config.bfd + selarchs="$selarchs $targ_archs" + fi +done + +# Utility var, documents generic cgen support files. + +cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo" + +# We don't do any links based on the target system, just makefile config. + +if test x${all_targets} = xfalse ; then + + # Target architecture .o files. + ta= + + for arch in $selarchs + do + ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` + archdefs="$archdefs -DARCH_$ad" + case "$arch" in + bfd_a29k_arch) ta="$ta a29k-dis.lo" ;; + bfd_alliant_arch) ;; + bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; + bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arm_arch) ta="$ta arm-dis.lo" ;; + bfd_avr_arch) ta="$ta avr-dis.lo" ;; + bfd_convex_arch) ;; + bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo" ;; + bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; + bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; + bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; + bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; + bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; + bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; + bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; + bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; + bfd_i386_arch) ta="$ta i386-dis.lo" ;; + bfd_i860_arch) ta="$ta i860-dis.lo" ;; + bfd_i960_arch) ta="$ta i960-dis.lo" ;; + bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; + bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; + bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; + bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; + bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; + bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; + bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; + bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; + bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; + bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; + bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; + bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_pyramid_arch) ;; + bfd_romp_arch) ;; + bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; + bfd_sh_arch) + # We can't decide what we want just from the CPU family. + # We want SH5 support unless a specific version of sh is + # specified, as in sh3-elf, sh3b-linux-gnu, etc. + # Include it just for ELF targets, since the SH5 bfd:s are ELF only. + for t in $target $canon_targets; do + case $t in + all | sh64-* | sh-*-*elf* | shl-*-*elf* | shle-*-*elf* | \ + sh-*-linux* | shl-*-linux*) + ta="$ta sh64-dis.lo sh64-opc.lo" + archdefs="$archdefs -DINCLUDE_SHMEDIA" + break;; + esac; + done + ta="$ta sh-dis.lo" ;; + bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; + bfd_tahoe_arch) ;; + bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; + bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; + bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_vax_arch) ta="$ta vax-dis.lo" ;; + bfd_w65_arch) ta="$ta w65-dis.lo" ;; + bfd_we32k_arch) ;; + bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; + bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + + "") ;; + *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; + esac + done + + if test $using_cgen = yes ; then + ta="$ta $cgen_files" + fi + + # Weed out duplicate .o files. + f="" + for i in $ta ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + ta="$f" + + # And duplicate -D flags. + f="" + for i in $archdefs ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + archdefs="$f" + + BFD_MACHINES="$ta" + +else # all_targets is true + archdefs=-DARCH_all + BFD_MACHINES='$(ALL_MACHINES)' +fi + +AC_SUBST(archdefs) +AC_SUBST(BFD_MACHINES) + +AC_OUTPUT(Makefile po/Makefile.in:po/Make-in, +[sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile]) diff --git a/opcodes/cris-dis.c b/opcodes/cris-dis.c new file mode 100644 index 0000000..33806ee --- /dev/null +++ b/opcodes/cris-dis.c @@ -0,0 +1,1406 @@ +/* Disassembler code for CRIS. + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Written by Hans-Peter Nilsson. + +This file is part of the GNU binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opcode/cris.h" +#include "libiberty.h" + +/* No instruction will be disassembled longer than this. In theory, and + in silicon, address prefixes can be cascaded. In practice, cascading + is not used by GCC, and not supported by the assembler. */ +#ifndef MAX_BYTES_PER_CRIS_INSN +#define MAX_BYTES_PER_CRIS_INSN 8 +#endif + +/* Whether or not to decode prefixes, folding it into the following + instruction. FIXME: Make this optional later. */ +#ifndef PARSE_PREFIX +#define PARSE_PREFIX 1 +#endif + +/* Sometimes we prefix all registers with this character. */ +#define REGISTER_PREFIX_CHAR '$' + +/* Whether or not to trace the following sequence: + sub* X,r%d + bound* Y,r%d + adds.w [pc+r%d.w],pc + + This is the assembly form of a switch-statement in C. + The "sub is optional. If there is none, then X will be zero. + X is the value of the first case, + Y is the number of cases (including default). + + This results in case offsets printed on the form: + case N: -> case_address + where N is an estimation on the corresponding 'case' operand in C, + and case_address is where execution of that case continues after the + sequence presented above. + + The old style of output was to print the offsets as instructions, + which made it hard to follow "case"-constructs in the disassembly, + and caused a lot of annoying warnings about undefined instructions. + + FIXME: Make this optional later. */ +#ifndef TRACE_CASE +#define TRACE_CASE 1 +#endif + +/* Value of first element in switch. */ +static long case_offset = 0; + +/* How many more case-offsets to print. */ +static long case_offset_counter = 0; + +/* Number of case offsets. */ +static long no_of_case_offsets = 0; + +/* Candidate for next case_offset. */ +static long last_immediate = 0; + +static int number_of_bits PARAMS ((unsigned int)); +static char *format_hex PARAMS ((unsigned long, char *)); +static char *format_dec PARAMS ((long, char *, int)); +static char *format_reg PARAMS ((int, char *, boolean)); +static int cris_constraint PARAMS ((const char *, unsigned int, + unsigned int)); +static unsigned bytes_to_skip PARAMS ((unsigned int, + const struct cris_opcode *)); +static char *print_flags PARAMS ((unsigned int, char *)); +static void print_with_operands + PARAMS ((const struct cris_opcode *, unsigned int, unsigned char *, + bfd_vma, disassemble_info *, const struct cris_opcode *, + unsigned int, unsigned char *, boolean)); +static const struct cris_spec_reg *spec_reg_info PARAMS ((unsigned int)); +static int print_insn_cris_generic + PARAMS ((bfd_vma, disassemble_info *, boolean)); +static int print_insn_cris_with_register_prefix + PARAMS ((bfd_vma, disassemble_info *)); +static int print_insn_cris_without_register_prefix + PARAMS ((bfd_vma, disassemble_info *)); +static const struct cris_opcode *get_opcode_entry + PARAMS ((unsigned int, unsigned int)); + +/* Return the descriptor of a special register. + FIXME: Depend on a CPU-version specific argument when all machinery + is in place. */ + +static const struct cris_spec_reg * +spec_reg_info (sreg) + unsigned int sreg; +{ + int i; + for (i = 0; cris_spec_regs[i].name != NULL; i++) + { + if (cris_spec_regs[i].number == sreg) + return &cris_spec_regs[i]; + } + + return NULL; +} + +/* Return the number of bits in the argument. */ + +static int +number_of_bits (val) + unsigned int val; +{ + int bits; + + for (bits = 0; val != 0; val &= val - 1) + bits++; + + return bits; +} + +/* Get an entry in the opcode-table. */ + +static const struct cris_opcode * +get_opcode_entry (insn, prefix_insn) + unsigned int insn; + unsigned int prefix_insn; +{ + /* For non-prefixed insns, we keep a table of pointers, indexed by the + insn code. Each entry is initialized when found to be NULL. */ + static const struct cris_opcode **opc_table = NULL; + + const struct cris_opcode *max_matchedp = NULL; + const struct cris_opcode **prefix_opc_table = NULL; + + /* We hold a table for each prefix that need to be handled differently. */ + static const struct cris_opcode **dip_prefixes = NULL; + static const struct cris_opcode **bdapq_m1_prefixes = NULL; + static const struct cris_opcode **bdapq_m2_prefixes = NULL; + static const struct cris_opcode **bdapq_m4_prefixes = NULL; + static const struct cris_opcode **rest_prefixes = NULL; + + /* Allocate and clear the opcode-table. */ + if (opc_table == NULL) + { + opc_table = xmalloc (65536 * sizeof (opc_table[0])); + memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *)); + + dip_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0])); + + bdapq_m1_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0])); + + bdapq_m2_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0])); + + bdapq_m4_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0])); + + rest_prefixes + = xmalloc (65536 * sizeof (const struct cris_opcode **)); + memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0])); + } + + /* Get the right table if this is a prefix. + This code is connected to cris_constraints in that it knows what + prefixes play a role in recognition of patterns; the necessary + state is reflected by which table is used. If constraints + involving match or non-match of prefix insns are changed, then this + probably needs changing too. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + const struct cris_opcode *popcodep + = (opc_table[prefix_insn] != NULL + ? opc_table[prefix_insn] + : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX)); + + if (popcodep == NULL) + return NULL; + + if (popcodep->match == BDAP_QUICK_OPCODE) + { + /* Since some offsets are recognized with "push" macros, we + have to have different tables for them. */ + int offset = (prefix_insn & 255); + + if (offset > 127) + offset -= 256; + + switch (offset) + { + case -4: + prefix_opc_table = bdapq_m4_prefixes; + break; + + case -2: + prefix_opc_table = bdapq_m2_prefixes; + break; + + case -1: + prefix_opc_table = bdapq_m1_prefixes; + break; + + default: + prefix_opc_table = rest_prefixes; + break; + } + } + else if (popcodep->match == DIP_OPCODE) + /* We don't allow postincrement when the prefix is DIP, so use a + different table for DIP. */ + prefix_opc_table = dip_prefixes; + else + prefix_opc_table = rest_prefixes; + } + + if (prefix_insn != NO_CRIS_PREFIX + && prefix_opc_table[insn] != NULL) + max_matchedp = prefix_opc_table[insn]; + else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) + max_matchedp = opc_table[insn]; + else + { + const struct cris_opcode *opcodep; + int max_level_of_match = -1; + + for (opcodep = cris_opcodes; + opcodep->name != NULL; + opcodep++) + { + int level_of_match; + + /* We give a double lead for bits matching the template in + cris_opcodes. Not even, because then "move p8,r10" would + be given 2 bits lead over "clear.d r10". When there's a + tie, the first entry in the table wins. This is + deliberate, to avoid a more complicated recognition + formula. */ + if ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0 + && ((level_of_match + = cris_constraint (opcodep->args, + insn, + prefix_insn)) + >= 0) + && ((level_of_match + += 2 * number_of_bits (opcodep->match + | opcodep->lose)) + > max_level_of_match)) + { + max_matchedp = opcodep; + max_level_of_match = level_of_match; + + /* If there was a full match, never mind looking + further. */ + if (level_of_match >= 2 * 16) + break; + } + } + /* Fill in the new entry. + + If there are changes to the opcode-table involving prefixes, and + disassembly then does not work correctly, try removing the + else-clause below that fills in the prefix-table. If that + helps, you need to change the prefix_opc_table setting above, or + something related. */ + if (prefix_insn == NO_CRIS_PREFIX) + opc_table[insn] = max_matchedp; + else + prefix_opc_table[insn] = max_matchedp; + } + + return max_matchedp; +} + +/* Format number as hex with a leading "0x" into outbuffer. */ + +static char * +format_hex (number, outbuffer) + unsigned long number; + char *outbuffer; +{ + /* Obfuscate to avoid warning on 32-bit host, but properly truncate + negative numbers on >32-bit hosts. */ + if (sizeof (number) > 4) + number &= (1 << (sizeof (number) > 4 ? 32 : 1)) - 1; + + sprintf (outbuffer, "0x%lx", number); + + /* Save this value for the "case" support. */ + if (TRACE_CASE) + last_immediate = number; + + return outbuffer + strlen (outbuffer); +} + +/* Format number as decimal into outbuffer. Parameter signedp says + whether the number should be formatted as signed (!= 0) or + unsigned (== 0). */ + +static char * +format_dec (number, outbuffer, signedp) + long number; + char *outbuffer; + int signedp; +{ + last_immediate = number; + sprintf (outbuffer, signedp ? "%ld" : "%lu", number); + + return outbuffer + strlen (outbuffer); +} + +/* Format the name of the general register regno into outbuffer. */ + +static char * +format_reg (regno, outbuffer_start, with_reg_prefix) + int regno; + char *outbuffer_start; + boolean with_reg_prefix; +{ + char *outbuffer = outbuffer_start; + + if (with_reg_prefix) + *outbuffer++ = REGISTER_PREFIX_CHAR; + + switch (regno) + { + case 15: + strcpy (outbuffer, "pc"); + break; + + case 14: + strcpy (outbuffer, "sp"); + break; + + default: + sprintf (outbuffer, "r%d", regno); + break; + } + + return outbuffer_start + strlen (outbuffer_start); +} + +/* Return -1 if the constraints of a bitwise-matched instruction say + that there is no match. Otherwise return a nonnegative number + indicating the confidence in the match (higher is better). */ + +static int +cris_constraint (cs, insn, prefix_insn) + const char *cs; + unsigned int insn; + unsigned int prefix_insn; +{ + int retval = 0; + int tmp; + int prefix_ok = 0; + + const char *s; + for (s = cs; *s; s++) + switch (*s) + { + case '!': + /* Do not recognize "pop" if there's a prefix. */ + if (prefix_insn != NO_CRIS_PREFIX) + return -1; + break; + + case 'M': + /* Size modifier for "clear", i.e. special register 0, 4 or 8. + Check that it is one of them. Only special register 12 could + be mismatched, but checking for matches is more logical than + checking for mismatches when there are only a few cases. */ + tmp = ((insn >> 12) & 0xf); + if (tmp != 0 && tmp != 4 && tmp != 8) + return -1; + break; + + case 'm': + if ((insn & 0x30) == 0x30) + return -1; + break; + + case 'S': + /* A prefix operand without side-effect. */ + if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0) + { + prefix_ok = 1; + break; + } + else + return -1; + + case 's': + case 'y': + /* If this is a prefixed insn with postincrement (side-effect), + the prefix must not be DIP. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + if (insn & 0x400) + { + const struct cris_opcode *prefix_opcodep + = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX); + + if (prefix_opcodep->match == DIP_OPCODE) + return -1; + } + + prefix_ok = 1; + } + break; + + case 'B': + /* If we don't fall through, then the prefix is ok. */ + prefix_ok = 1; + + /* A "push" prefix. Check for valid "push" size. + In case of special register, it may be != 4. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + /* Match the prefix insn to BDAPQ. */ + const struct cris_opcode *prefix_opcodep + = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX); + + if (prefix_opcodep->match == BDAP_QUICK_OPCODE) + { + int pushsize = (prefix_insn & 255); + + if (pushsize > 127) + pushsize -= 256; + + if (s[1] == 'P') + { + unsigned int spec_reg = (insn >> 12) & 15; + const struct cris_spec_reg *sregp + = spec_reg_info (spec_reg); + + /* For a special-register, the "prefix size" must + match the size of the register. */ + if (sregp && sregp->reg_size == (unsigned int) -pushsize) + break; + } + else if (s[1] == 'R') + { + if ((insn & 0x30) == 0x20 && pushsize == -4) + break; + } + /* FIXME: Should abort here; next constraint letter + *must* be 'P' or 'R'. */ + } + } + return -1; + + case 'D': + retval = (((insn >> 12) & 15) == (insn & 15)); + if (!retval) + return -1; + else + retval += 4; + break; + + case 'P': + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* Since we match four bits, we will give a value of 4-1 = 3 + in a match. If there is a corresponding exact match of a + special register in another pattern, it will get a value of + 4, which will be higher. This should be correct in that an + exact pattern would match better than a general pattern. + + Note that there is a reason for not returning zero; the + pattern for "clear" is partly matched in the bit-pattern + (the two lower bits must be zero), while the bit-pattern + for a move from a special register is matched in the + register constraint. */ + + if (sregp != NULL) + { + retval += 3; + break; + } + else + return -1; + } + } + + if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok) + return -1; + + return retval; +} + +/* Return the length of an instruction. */ + +static unsigned +bytes_to_skip (insn, matchedp) + unsigned int insn; + const struct cris_opcode *matchedp; +{ + /* Each insn is a word plus "immediate" operands. */ + unsigned to_skip = 2; + const char *template = matchedp->args; + const char *s; + + for (s = template; *s; s++) + if (*s == 's' && (insn & 0x400) && (insn & 15) == 15) + { + /* Immediate via [pc+], so we have to check the size of the + operand. */ + int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3)); + + if (matchedp->imm_oprnd_size == SIZE_FIX_32) + to_skip += 4; + else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp == NULL) + return 2; + + /* PC is incremented by two, not one, for a byte. */ + to_skip += (sregp->reg_size + 1) & ~1; + } + else + to_skip += (mode_size + 1) & ~1; + } + else if (*s == 'b') + to_skip += 2; + + return to_skip; +} + +/* Print condition code flags. */ + +static char * +print_flags (insn, cp) + unsigned int insn; + char *cp; +{ + /* Use the v8 (Etrax 100) flag definitions for disassembly. + The differences with v0 (Etrax 1..4) vs. Svinto are: + v0 'd' <=> v8 'm' + v0 'e' <=> v8 'b'. */ + static const char fnames[] = "cvznxibm"; + + unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); + int i; + + for (i = 0; i < 8; i++) + if (flagbits & (1 << i)) + *cp++ = fnames[i]; + + return cp; +} + +/* Print out an insn with its operands, and update the info->insn_type + fields. The prefix_opcodep and the rest hold a prefix insn that is + supposed to be output as an address mode. */ + +static void +print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep, + prefix_insn, prefix_buffer, with_reg_prefix) + const struct cris_opcode *opcodep; + unsigned int insn; + unsigned char *buffer; + bfd_vma addr; + disassemble_info *info; + + /* If a prefix insn was before this insn (and is supposed to be + output as an address), here is a description of it. */ + const struct cris_opcode *prefix_opcodep; + unsigned int prefix_insn; + unsigned char *prefix_buffer; + boolean with_reg_prefix; +{ + /* Get a buffer of somewhat reasonable size where we store + intermediate parts of the insn. */ + char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2]; + char *tp = temp; + static const char mode_char[] = "bwd?"; + const char *s; + const char *cs; + + /* Print out the name first thing we do. */ + (*info->fprintf_func) (info->stream, "%s", opcodep->name); + + cs = opcodep->args; + s = cs; + + /* Ignore any prefix indicator. */ + if (*s == 'p') + s++; + + if (*s == 'm' || *s == 'M' || *s == 'z') + { + *tp++ = '.'; + + /* Get the size-letter. */ + *tp++ = *s == 'M' + ? (insn & 0x8000 ? 'd' + : insn & 0x4000 ? 'w' : 'b') + : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)]; + + /* Ignore the size and the space character that follows. */ + s += 2; + } + + /* Add a space if this isn't a long-branch, because for those will add + the condition part of the name later. */ + if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) + *tp++ = ' '; + + /* Fill in the insn-type if deducible from the name (and there's no + better way). */ + if (opcodep->name[0] == 'j') + { + if (strncmp (opcodep->name, "jsr", 3) == 0) + /* It's "jsr" or "jsrc". */ + info->insn_type = dis_jsr; + else + /* Any other jump-type insn is considered a branch. */ + info->insn_type = dis_branch; + } + + /* We might know some more fields right now. */ + info->branch_delay_insns = opcodep->delayed; + + /* Handle operands. */ + for (; *s; s++) + { + switch (*s) + { + case ',': + *tp++ = *s; + break; + + case '!': + /* Ignore at this point; used at earlier stages to avoid recognition + if there's a prefixes at something that in other ways looks like + a "pop". */ + break; + + case 'B': + /* This was the prefix that made this a "push". We've already + handled it by recognizing it, so signal that the prefix is + handled by setting it to NULL. */ + prefix_opcodep = NULL; + break; + + case 'D': + case 'r': + tp = format_reg (insn & 15, tp, with_reg_prefix); + break; + + case 'R': + tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix); + break; + + case 'y': + case 'S': + case 's': + /* Any "normal" memory operand. */ + if ((insn & 0x400) && (insn & 15) == 15) + { + /* We're looking at [pc+], i.e. we need to output an immediate + number, where the size can depend on different things. */ + long number; + int signedp + = ((*cs == 'z' && (insn & 0x20)) + || opcodep->match == BDAP_QUICK_OPCODE); + int nbytes; + + if (opcodep->imm_oprnd_size == SIZE_FIX_32) + nbytes = 4; + else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* A NULL return should have been as a non-match earlier, + so catch it as an internal error in the error-case + below. */ + if (sregp == NULL) + /* Whatever non-valid size. */ + nbytes = 42; + else + /* PC is always incremented by a multiple of two. */ + nbytes = (sregp->reg_size + 1) & ~1; + } + else + { + int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3)); + + if (mode_size == 1) + nbytes = 2; + else + nbytes = mode_size; + } + + switch (nbytes) + { + case 1: + number = buffer[2]; + if (signedp && number > 127) + number -= 256; + break; + + case 2: + number = buffer[2] + buffer[3] * 256; + if (signedp && number > 32767) + number -= 65536; + break; + + case 4: + number + = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + + buffer[5] * 0x1000000; + break; + + default: + strcpy (tp, "bug"); + tp += 3; + number = 42; + } + + if ((*cs == 'z' && (insn & 0x20)) + || (opcodep->match == BDAP_QUICK_OPCODE + && (nbytes <= 2 || buffer[1 + nbytes] == 0))) + tp = format_dec (number, tp, signedp); + else + { + unsigned int highbyte = (number >> 24) & 0xff; + + /* Either output this as an address or as a number. If it's + a dword with the same high-byte as the address of the + insn, assume it's an address, and also if it's a non-zero + non-0xff high-byte. If this is a jsr or a jump, then + it's definitely an address. */ + if (nbytes == 4 + && (highbyte == ((addr >> 24) & 0xff) + || (highbyte != 0 && highbyte != 0xff) + || info->insn_type == dis_branch + || info->insn_type == dis_jsr)) + { + /* Finish off and output previous formatted bytes. */ + *tp = 0; + tp = temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + + info->target = number; + } + else + tp = format_hex (number, tp); + } + } + else + { + /* Not an immediate number. Then this is a (possibly + prefixed) memory operand. */ + if (info->insn_type != dis_nonbranch) + { + int mode_size + = 1 << ((insn >> 4) + & (opcodep->args[0] == 'z' ? 1 : 3)); + int size; + info->insn_type = dis_dref; + info->flags |= CRIS_DIS_FLAG_MEMREF; + + if (opcodep->imm_oprnd_size == SIZE_FIX_32) + size = 4; + else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp == NULL) + size = 4; + else + size = sregp->reg_size; + } + else + size = mode_size; + + info->data_size = size; + } + + *tp++ = '['; + + if (prefix_opcodep + /* We don't match dip with a postincremented field + as a side-effect address mode. */ + && ((insn & 0x400) == 0 + || prefix_opcodep->match != DIP_OPCODE)) + { + if (insn & 0x400) + { + tp = format_reg (insn & 15, tp, with_reg_prefix); + *tp++ = '='; + } + + + /* We mainly ignore the prefix format string when the + address-mode syntax is output. */ + switch (prefix_opcodep->match) + { + case DIP_OPCODE: + /* It's [r], [r+] or [pc+]. */ + if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) + { + /* It's [pc+]. This cannot possibly be anything + but an address. */ + unsigned long number + = prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + + info->target = (bfd_vma) number; + + /* Finish off and output previous formatted + data. */ + *tp = 0; + tp = temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + } + else + { + /* For a memref in an address, we use target2. + In this case, target is zero. */ + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM); + + info->target2 = prefix_insn & 15; + + *tp++ = '['; + tp = format_reg (prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ = '+'; + *tp++ = ']'; + } + break; + + case BDAP_QUICK_OPCODE: + { + int number; + + number = prefix_buffer[0]; + if (number > 127) + number -= 256; + + /* Output "reg+num" or, if num < 0, "reg-num". */ + tp = format_reg ((prefix_insn >> 12) & 15, tp, + with_reg_prefix); + if (number >= 0) + *tp++ = '+'; + tp = format_dec (number, tp, 1); + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target = (prefix_insn >> 12) & 15; + info->target2 = (bfd_vma) number; + break; + } + + case BIAP_OPCODE: + /* Output "r+R.m". */ + tp = format_reg (prefix_insn & 15, tp, with_reg_prefix); + *tp++ = '+'; + tp = format_reg ((prefix_insn >> 12) & 15, tp, + with_reg_prefix); + *tp++ = '.'; + *tp++ = mode_char[(prefix_insn >> 4) & 3]; + + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + + | ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 + : ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); + + /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */ + if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f) + /* Then start interpreting data as offsets. */ + case_offset_counter = no_of_case_offsets; + break; + + case BDAP_INDIR_OPCODE: + /* Output "r+s.m", or, if "s" is [pc+], "r+s" or + "r-s". */ + tp = format_reg ((prefix_insn >> 12) & 15, tp, + with_reg_prefix); + + if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) + { + long number; + unsigned int nbytes; + + /* It's a value. Get its size. */ + int mode_size = 1 << ((prefix_insn >> 4) & 3); + + if (mode_size == 1) + nbytes = 2; + else + nbytes = mode_size; + + switch (nbytes) + { + case 1: + number = prefix_buffer[2]; + if (number > 127) + number -= 256; + break; + + case 2: + number = prefix_buffer[2] + prefix_buffer[3] * 256; + if (number > 32767) + number -= 65536; + break; + + case 4: + number + = prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + break; + + default: + strcpy (tp, "bug"); + tp += 3; + number = 42; + } + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target2 = (bfd_vma) number; + + /* If the size is dword, then assume it's an + address. */ + if (nbytes == 4) + { + /* Finish off and output previous formatted + bytes. */ + *tp++ = '+'; + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + } + else + { + if (number >= 0) + *tp++ = '+'; + tp = format_dec (number, tp, 1); + } + } + else + { + /* Output "r+[R].m" or "r+[R+].m". */ + *tp++ = '+'; + *tp++ = '['; + tp = format_reg (prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ = '+'; + *tp++ = ']'; + *tp++ = '.'; + *tp++ = mode_char[(prefix_insn >> 4) & 3]; + + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + + | (((prefix_insn >> 4) == 2) + ? 0 + : (((prefix_insn >> 4) & 3) == 1 + ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD + : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); + } + break; + + default: + (*info->fprintf_func) (info->stream, "?prefix-bug"); + } + + /* To mark that the prefix is used, reset it. */ + prefix_opcodep = NULL; + } + else + { + tp = format_reg (insn & 15, tp, with_reg_prefix); + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target = insn & 15; + + if (insn & 0x400) + *tp++ = '+'; + } + *tp++ = ']'; + } + break; + + case 'x': + tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix); + *tp++ = '.'; + *tp++ = mode_char[(insn >> 4) & 3]; + break; + + case 'I': + tp = format_dec (insn & 63, tp, 0); + break; + + case 'b': + { + int where = buffer[2] + buffer[3] * 256; + + if (where > 32767) + where -= 65536; + + where += addr + 4; + + if (insn == BA_PC_INCR_OPCODE) + info->insn_type = dis_branch; + else + info->insn_type = dis_condbranch; + + info->target = (bfd_vma) where; + + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s%s ", + temp, cris_cc_strings[insn >> 12]); + + (*info->print_address_func) ((bfd_vma) where, info); + } + break; + + case 'c': + tp = format_dec (insn & 31, tp, 0); + break; + + case 'C': + tp = format_dec (insn & 15, tp, 0); + break; + + case 'o': + { + long offset = insn & 0xfe; + + if (insn & 1) + offset |= ~0xff; + + if (opcodep->match == BA_QUICK_OPCODE) + info->insn_type = dis_branch; + else + info->insn_type = dis_condbranch; + + info->target = (bfd_vma) (addr + 2 + offset); + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) (addr + 2 + offset), info); + } + break; + + case 'O': + { + long number = buffer[0]; + + if (number > 127) + number = number - 256; + + tp = format_dec (number, tp, 1); + *tp++ = ','; + tp = format_reg ((insn >> 12) & 15, tp, with_reg_prefix); + } + break; + + case 'f': + tp = print_flags (insn, tp); + break; + + case 'i': + tp = format_dec ((insn & 32) ? (insn & 31) | ~31 : insn & 31, tp, 1); + break; + + case 'P': + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15); + + if (sregp->name == NULL) + /* Should have been caught as a non-match eariler. */ + *tp++ = '?'; + else + { + if (with_reg_prefix) + *tp++ = REGISTER_PREFIX_CHAR; + strcpy (tp, sregp->name); + tp += strlen (tp); + } + } + break; + + default: + strcpy (tp, "???"); + tp += 3; + } + } + + *tp = 0; + + if (prefix_opcodep) + (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")", + prefix_opcodep->name, prefix_opcodep->args); + + (*info->fprintf_func) (info->stream, "%s", temp); + + /* Get info for matching case-tables, if we don't have any active. + We assume that the last constant seen is used; either in the insn + itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */ + if (TRACE_CASE && case_offset_counter == 0) + { + if (strncmp (opcodep->name, "sub", 3) == 0) + case_offset = last_immediate; + + /* It could also be an "add", if there are negative case-values. */ + else if (strncmp (opcodep->name, "add", 3) == 0) + { + /* The first case is the negated operand to the add. */ + case_offset = -last_immediate; + } + /* A bound insn will tell us the number of cases. */ + else if (strncmp (opcodep->name, "bound", 5) == 0) + { + no_of_case_offsets = last_immediate + 1; + } + /* A jump or jsr or branch breaks the chain of insns for a + case-table, so assume default first-case again. */ + else if (info->insn_type == dis_jsr + || info->insn_type == dis_branch + || info->insn_type == dis_condbranch) + case_offset = 0; + } +} + + +/* Print the CRIS instruction at address memaddr on stream. Returns + length of the instruction, in bytes. Prefix register names with `$' if + WITH_REG_PREFIX. */ + +static int +print_insn_cris_generic (memaddr, info, with_reg_prefix) + bfd_vma memaddr; + disassemble_info *info; + boolean with_reg_prefix; +{ + int nbytes; + unsigned int insn; + const struct cris_opcode *matchedp; + int advance = 0; + + /* No instruction will be disassembled as longer than this number of + bytes; stacked prefixes will not be expanded. */ + unsigned char buffer[MAX_BYTES_PER_CRIS_INSN]; + unsigned char *bufp; + int status = 0; + bfd_vma addr; + + /* There will be an "out of range" error after the last instruction. + Reading pairs of bytes in decreasing number, we hope that we will get + at least the amount that we will consume. + + If we can't get any data, or we do not get enough data, we print + the error message. */ + + for (nbytes = MAX_BYTES_PER_CRIS_INSN; nbytes > 0; nbytes -= 2) + { + status = (*info->read_memory_func) (memaddr, buffer, nbytes, info); + if (status == 0) + break; + } + + /* If we did not get all we asked for, then clear the rest. + Hopefully this makes a reproducible result in case of errors. */ + if (nbytes != MAX_BYTES_PER_CRIS_INSN) + memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes); + + addr = memaddr; + bufp = buffer; + + /* Set some defaults for the insn info. */ + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->flags = 0; + info->target = 0; + info->target2 = 0; + + /* If we got any data, disassemble it. */ + if (nbytes != 0) + { + matchedp = NULL; + + insn = bufp[0] + bufp[1] * 256; + + /* If we're in a case-table, don't disassemble the offsets. */ + if (TRACE_CASE && case_offset_counter != 0) + { + info->insn_type = dis_noninsn; + advance += 2; + + /* If to print data as offsets, then shortcut here. */ + (*info->fprintf_func) (info->stream, "case %d%s: -> ", + case_offset + no_of_case_offsets + - case_offset_counter, + case_offset_counter == 1 ? "/default" : + ""); + + (*info->print_address_func) ((bfd_vma) + ((short) (insn) + + (long) (addr + - (no_of_case_offsets + - case_offset_counter) + * 2)), info); + case_offset_counter--; + + /* The default case start (without a "sub" or "add") must be + zero. */ + if (case_offset_counter == 0) + case_offset = 0; + } + else if (insn == 0) + { + /* We're often called to disassemble zeroes. While this is a + valid "bcc .+2" insn, it is also useless enough and enough + of a nuiscance that we will just output "bcc .+2" for it + and signal it as a noninsn. */ + (*info->fprintf_func) (info->stream, "bcc .+2"); + info->insn_type = dis_noninsn; + advance += 2; + } + else + { + const struct cris_opcode *prefix_opcodep = NULL; + unsigned char *prefix_buffer = bufp; + unsigned int prefix_insn = insn; + int prefix_size = 0; + + matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX); + + /* Check if we're supposed to write out prefixes as address + modes and if this was a prefix. */ + if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p') + { + /* If it's a prefix, put it into the prefix vars and get the + main insn. */ + prefix_size = bytes_to_skip (prefix_insn, matchedp); + prefix_opcodep = matchedp; + + insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256; + matchedp = get_opcode_entry (insn, prefix_insn); + + if (matchedp != NULL) + { + addr += prefix_size; + bufp += prefix_size; + advance += prefix_size; + } + else + { + /* The "main" insn wasn't valid, at least not when + prefixed. Put back things enough to output the + prefix insn only, as a normal insn. */ + matchedp = prefix_opcodep; + insn = prefix_insn; + prefix_opcodep = NULL; + } + } + + if (matchedp == NULL) + { + (*info->fprintf_func) (info->stream, "??0x%lx", insn); + advance += 2; + + info->insn_type = dis_noninsn; + } + else + { + advance += bytes_to_skip (insn, matchedp); + + /* The info_type and assorted fields will be set according + to the operands. */ + print_with_operands (matchedp, insn, bufp, addr, info, + prefix_opcodep, prefix_insn, + prefix_buffer, with_reg_prefix); + } + } + } + else + info->insn_type = dis_noninsn; + + /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error + status when reading that much, and the insn decoding indicated a + length exceeding what we read, there is an error. */ + if (status != 0 && (nbytes == 0 || advance > nbytes)) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Max supported insn size with one folded prefix insn. */ + info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN; + + /* I would like to set this to a fixed value larger than the actual + number of bytes to print in order to avoid spaces between bytes, + but objdump.c (2.9.1) does not like that, so we print 16-bit + chunks, which is the next choice. */ + info->bytes_per_chunk = 2; + + /* Printing bytes in order of increasing addresses makes sense, + especially on a little-endian target. + This is completely the opposite of what you think; setting this to + BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N + we want. */ + info->display_endian = BFD_ENDIAN_BIG; + + return advance; +} + +/* Disassemble, prefixing register names with `$'. */ + +static int +print_insn_cris_with_register_prefix (vma, info) + bfd_vma vma; + disassemble_info *info; +{ + return print_insn_cris_generic (vma, info, true); +} + +/* Disassemble, no prefixes on register names. */ + +static int +print_insn_cris_without_register_prefix (vma, info) + bfd_vma vma; + disassemble_info *info; +{ + return print_insn_cris_generic (vma, info, false); +} + +/* Return a disassembler-function that prints registers with a `$' prefix, + or one that prints registers without a prefix. */ + +disassembler_ftype +cris_get_disassembler (abfd) + bfd *abfd; +{ + /* If there's no bfd in sight, we return what is valid as input in all + contexts if fed back to the assembler: disassembly *with* register + prefix. */ + if (abfd == NULL || bfd_get_symbol_leading_char (abfd) == 0) + return print_insn_cris_with_register_prefix; + + return print_insn_cris_without_register_prefix; +} + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/opcodes/cris-opc.c b/opcodes/cris-opc.c new file mode 100644 index 0000000..4477193 --- /dev/null +++ b/opcodes/cris-opc.c @@ -0,0 +1,885 @@ +/* cris-opc.c -- Table of opcodes for the CRIS processor. + Copyright 2000 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. + Reorganized by Hans-Peter Nilsson. + +This file is part of GAS, GDB and the GNU binutils. + +GAS, GDB, and GNU binutils is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2, or (at your +option) any later version. + +GAS, GDB, and GNU binutils are distributed in the hope that they will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "opcode/cris.h" + +#ifndef NULL +#define NULL (0) +#endif + +const struct cris_spec_reg +cris_spec_regs[] = +{ + {"p0", 0, 1, 0, NULL}, + {"vr", 1, 1, 0, NULL}, + {"p1", 1, 1, 0, NULL}, + {"p2", 2, 1, cris_ver_warning, NULL}, + {"p3", 3, 1, cris_ver_warning, NULL}, + {"p4", 4, 2, 0, NULL}, + {"ccr", 5, 2, 0, NULL}, + {"p5", 5, 2, 0, NULL}, + {"dcr0",6, 2, cris_ver_v0_3, NULL}, + {"p6", 6, 2, cris_ver_v0_3, NULL}, + {"dcr1/mof", 7, 4, cris_ver_v10p, + "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, + {"dcr1/mof", 7, 2, cris_ver_v0_3, + "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, + {"mof", 7, 4, cris_ver_v10p, NULL}, + {"dcr1",7, 2, cris_ver_v0_3, NULL}, + {"p7", 7, 4, cris_ver_v10p, NULL}, + {"p7", 7, 2, cris_ver_v0_3, NULL}, + {"p8", 8, 4, 0, NULL}, + {"ibr", 9, 4, 0, NULL}, + {"p9", 9, 4, 0, NULL}, + {"irp", 10, 4, 0, NULL}, + {"p10", 10, 4, 0, NULL}, + {"srp", 11, 4, 0, NULL}, + {"p11", 11, 4, 0, NULL}, + /* For disassembly use only. Accept at assembly with a warning. */ + {"bar/dtp0", 12, 4, cris_ver_warning, + "Ambiguous register `bar/dtp0' specified"}, + {"bar", 12, 4, cris_ver_v8p, NULL}, + {"dtp0",12, 4, cris_ver_v0_3, NULL}, + {"p12", 12, 4, 0, NULL}, + /* For disassembly use only. Accept at assembly with a warning. */ + {"dccr/dtp1",13, 4, cris_ver_warning, + "Ambiguous register `dccr/dtp1' specified"}, + {"dccr",13, 4, cris_ver_v8p, NULL}, + {"dtp1",13, 4, cris_ver_v0_3, NULL}, + {"p13", 13, 4, 0, NULL}, + {"brp", 14, 4, cris_ver_v3p, NULL}, + {"p14", 14, 4, cris_ver_v3p, NULL}, + {"usp", 15, 4, cris_ver_v10p, NULL}, + {"p15", 15, 4, cris_ver_v10p, NULL}, + {NULL, 0, 0, cris_ver_version_all, NULL} +}; + +/* All CRIS opcodes are 16 bits. + + - The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + - The args component is a string containing characters symbolically + matching the operands of an instruction. Used for both assembly + and disassembly. + + Operand-matching characters: + B Not really an operand. It causes a "BDAP -size,SP" prefix to be + output for the PUSH alias-instructions and recognizes a + push-prefix at disassembly. Must be followed by a R or P letter. + ! Non-match pattern, will not match if there's a prefix insn. + b Non-matching operand, used for branches with 16-bit + displacement. Only recognized by the disassembler. + c 5-bit unsigned immediate in bits <4:0>. + C 4-bit unsigned immediate in bits <3:0>. + D General register in bits <15:12> and <3:0>. + f List of flags in bits <15:12> and <3:0>. + i 6-bit signed immediate in bits <5:0>. + I 6-bit unsigned immediate in bits <5:0>. + M Size modifier (B, W or D) for CLEAR instructions. + m Size modifier (B, W or D) in bits <5:4> + o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit + branch instructions. + O [-128..127] offset in bits <7:0>. Also matches a comma and a + general register after the expression. Used only for the BDAP + prefix insn. + P Special register in bits <15:12>. + p Indicates that the insn is a prefix insn. Must be first + character. + R General register in bits <15:12>. + r General register in bits <3:0>. + S Source operand in bit <10> and a prefix; a 3-operand prefix + without side-effect. + s Source operand in bits <10> and <3:0>, optionally with a + side-effect prefix. + x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>. + y Like 's' but do not allow an integer at assembly. + z Size modifier (B or W) in bit <4>. */ + + +/* Please note the order of the opcodes in this table is significant. + The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler might not recognize + them, or may indicate and internal error. + + The disassembler should not normally care about the order of the + opcodes, but will prefer an earlier alternative if the "match-score" + (see cris-dis.c) is computed as equal. + + It should not be significant for proper execution that this table is + in alphabetical order, but please follow that convention for an easy + overview. */ + +const struct cris_opcode +cris_opcodes[] = +{ + {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, + cris_abs_op}, + + {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, + cris_addi_op}, + + {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, + cris_quick_mode_add_sub_op}, + + {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, + cris_asr_op}, + + {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, + cris_asrq_op}, + + {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + /* FIXME: Should use branch #defines. */ + {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, + cris_sixteen_bit_offset_branch_op}, + + {"ba", + BA_QUICK_OPCODE, + 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bcc", + BRANCH_QUICK_OPCODE+CC_CC*0x1000, + 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bcs", + BRANCH_QUICK_OPCODE+CC_CS*0x1000, + 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bdap", + BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD, 0, + cris_bdap_prefix}, + + {"bdap", + BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, 0, + cris_quick_mode_bdap_prefix}, + + {"beq", + BRANCH_QUICK_OPCODE+CC_EQ*0x1000, + 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + /* This is deliberately put before "bext" to trump it, even though not + in alphabetical order. */ + {"bwf", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v10p, + cris_eight_bit_offset_branch_op}, + + {"bext", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v0_3, + cris_eight_bit_offset_branch_op}, + + {"bge", + BRANCH_QUICK_OPCODE+CC_GE*0x1000, + 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bgt", + BRANCH_QUICK_OPCODE+CC_GT*0x1000, + 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bhi", + BRANCH_QUICK_OPCODE+CC_HI*0x1000, + 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bhs", + BRANCH_QUICK_OPCODE+CC_HS*0x1000, + 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, 0, + cris_biap_prefix}, + + {"ble", + BRANCH_QUICK_OPCODE+CC_LE*0x1000, + 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"blo", + BRANCH_QUICK_OPCODE+CC_LO*0x1000, + 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bls", + BRANCH_QUICK_OPCODE+CC_LS*0x1000, + 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"blt", + BRANCH_QUICK_OPCODE+CC_LT*0x1000, + 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bmi", + BRANCH_QUICK_OPCODE+CC_MI*0x1000, + 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, + cris_ver_sim, + cris_not_implemented_op}, + + {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, + cris_ver_sim, + cris_not_implemented_op}, + + {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, + cris_ver_sim, + cris_not_implemented_op}, + + {"bne", + BRANCH_QUICK_OPCODE+CC_NE*0x1000, + 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_bound_op}, + {"bpl", + BRANCH_QUICK_OPCODE+CC_PL*0x1000, + 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, + cris_ver_v3p, + cris_break_op}, + + {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, + cris_ver_warning, + cris_not_implemented_op}, + + {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, + cris_ver_warning, + cris_not_implemented_op}, + + {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, + cris_ver_warning, + cris_not_implemented_op}, + + {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + {"bvc", + BRANCH_QUICK_OPCODE+CC_VC*0x1000, + 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bvs", + BRANCH_QUICK_OPCODE+CC_VS*0x1000, + 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, + cris_reg_mode_clear_op}, + + {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, + cris_clearf_di_op}, + + {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, + cris_clearf_di_op}, + + {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, 0, + cris_dip_prefix}, + + {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, + cris_not_implemented_op}, + + {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_reg_mode_jump_op}, + + {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, 0, + cris_none_reg_mode_jump_op}, + + {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, 0, + cris_none_reg_mode_jump_op}, + + {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_reg_mode_jump_op}, + + {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, 0, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, 0, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_reg_mode_jump_op}, + + {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, + cris_ver_v8p, + cris_none_reg_mode_jump_op}, + + {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jump", + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, 0, + cris_none_reg_mode_jump_op}, + + {"jump", + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, 0, + cris_none_reg_mode_jump_op}, + + {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, + cris_ver_v10p, + cris_none_reg_mode_jump_op}, + + {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, + cris_ver_v10p, + cris_none_reg_mode_jump_op}, + + {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, + cris_ver_v3p, + cris_not_implemented_op}, + + {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A30, 0x01c0, "s,P", 0, SIZE_SPEC_REG, 0, + cris_move_to_preg_op}, + + {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, + cris_move_reg_to_mem_movem_op}, + + {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, 0, + cris_move_reg_to_mem_movem_op}, + + {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, + cris_move_mem_to_reg_movem_op}, + + {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, 0, + cris_move_mem_to_reg_movem_op}, + + {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, + cris_ver_v10p, + cris_muls_op}, + + {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, + cris_ver_v10p, + cris_mulu_op}, + + {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + + {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, + cris_ver_v10p, + cris_not_implemented_op}, + + {"sa", + 0x0530+CC_A*0x1000, + 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"scc", + 0x0530+CC_CC*0x1000, + 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"scs", + 0x0530+CC_CS*0x1000, + 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"seq", + 0x0530+CC_EQ*0x1000, + 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + /* Need to have "swf" in front of "sext" so it is the one displayed in + disassembly. */ + {"swf", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v10p, + cris_scc_op}, + + {"sext", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v0_3, + cris_scc_op}, + + {"sge", + 0x0530+CC_GE*0x1000, + 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sgt", + 0x0530+CC_GT*0x1000, + 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"shi", + 0x0530+CC_HI*0x1000, + 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"shs", + 0x0530+CC_HS*0x1000, + 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sle", + 0x0530+CC_LE*0x1000, + 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"slo", + 0x0530+CC_LO*0x1000, + 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sls", + 0x0530+CC_LS*0x1000, + 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"slt", + 0x0530+CC_LT*0x1000, + 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"smi", + 0x0530+CC_MI*0x1000, + 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sne", + 0x0530+CC_NE*0x1000, + 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"spl", + 0x0530+CC_PL*0x1000, + 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, + cris_quick_mode_add_sub_op}, + + {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, 0, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"svc", + 0x0530+CC_VC*0x1000, + 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"svs", + 0x0530+CC_VS*0x1000, + 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + /* The insn "swapn" is the same as "not" and will be disassembled as + such, but the swap* family of mnmonics are generally v8-and-higher + only, so count it in. */ + {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, 0, + cris_reg_mode_test_op}, + + {"test", 0x0b80, 0xf040, "m s", 0, SIZE_FIELD, 0, + cris_none_reg_mode_clear_test_op}, + + {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, + cris_xor_op}, + + {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} +}; + +/* Condition-names, indexed by the CC_* numbers as found in cris.h. */ +const char * const +cris_cc_strings[] = +{ + "hs", + "lo", + "ne", + "eq", + "vc", + "vs", + "pl", + "mi", + "ls", + "hi", + "ge", + "lt", + "gt", + "le", + "a", + /* In v0, this would be "ext". */ + "wf", +}; + + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/opcodes/d10v-dis.c b/opcodes/d10v-dis.c new file mode 100644 index 0000000..433fd51 --- /dev/null +++ b/opcodes/d10v-dis.c @@ -0,0 +1,303 @@ +/* Disassemble D10V instructions. + Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/d10v.h" +#include "dis-asm.h" + +/* The PC wraps at 18 bits, except for the segment number, + so use this mask to keep the parts we want. */ +#define PC_MASK 0x0303FFFF + +static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr, + struct disassemble_info *info, int order)); +static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr, + struct disassemble_info *info)); +static void print_operand + PARAMS ((struct d10v_operand *, long unsigned int, struct d10v_opcode *, + bfd_vma, struct disassemble_info *)); + +int +print_insn_d10v (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + + status = insn & FM11; + switch (status) + { + case 0: + dis_2_short (insn, memaddr, info, 2); + break; + case FM01: + dis_2_short (insn, memaddr, info, 0); + break; + case FM10: + dis_2_short (insn, memaddr, info, 1); + break; + case FM11: + dis_long (insn, memaddr, info); + break; + } + return 4; +} + +static void +print_operand (oper, insn, op, memaddr, info) + struct d10v_operand *oper; + unsigned long insn; + struct d10v_opcode *op; + bfd_vma memaddr; + struct disassemble_info *info; +{ + int num, shift; + + if (oper->flags == OPERAND_ATMINUS) + { + (*info->fprintf_func) (info->stream, "@-"); + return; + } + if (oper->flags == OPERAND_MINUS) + { + (*info->fprintf_func) (info->stream, "-"); + return; + } + if (oper->flags == OPERAND_PLUS) + { + (*info->fprintf_func) (info->stream, "+"); + return; + } + if (oper->flags == OPERAND_ATSIGN) + { + (*info->fprintf_func) (info->stream, "@"); + return; + } + if (oper->flags == OPERAND_ATPAR) + { + (*info->fprintf_func) (info->stream, "@("); + return; + } + + shift = oper->shift; + + /* The LONG_L format shifts registers over by 15. */ + if (op->format == LONG_L && (oper->flags & OPERAND_REG)) + shift += 15; + + num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits)); + + if (oper->flags & OPERAND_REG) + { + int i; + int match = 0; + num += (oper->flags + & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)); + if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1)) + num += num ? OPERAND_ACC1 : OPERAND_ACC0; + for (i = 0; i < d10v_reg_name_cnt (); i++) + { + if (num == (d10v_predefined_registers[i].value & ~ OPERAND_SP)) + { + if (d10v_predefined_registers[i].pname) + (*info->fprintf_func) (info->stream, "%s", + d10v_predefined_registers[i].pname); + else + (*info->fprintf_func) (info->stream, "%s", + d10v_predefined_registers[i].name); + match = 1; + break; + } + } + if (match == 0) + { + /* This would only get executed if a register was not in the + register table. */ + if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1)) + (*info->fprintf_func) (info->stream, "a"); + else if (oper->flags & OPERAND_CONTROL) + (*info->fprintf_func) (info->stream, "cr"); + else if (oper->flags & OPERAND_REG) + (*info->fprintf_func) (info->stream, "r"); + (*info->fprintf_func) (info->stream, "%d", num & REGISTER_MASK); + } + } + else + { + /* Addresses are right-shifted by 2. */ + if (oper->flags & OPERAND_ADDR) + { + long max; + int neg = 0; + max = (1 << (oper->bits - 1)); + if (num & max) + { + num = -num & ((1 << oper->bits) - 1); + neg = 1; + } + num = num << 2; + if (info->flags & INSN_HAS_RELOC) + (*info->print_address_func) (num & PC_MASK, info); + else + { + if (neg) + (*info->print_address_func) ((memaddr - num) & PC_MASK, info); + else + (*info->print_address_func) ((memaddr + num) & PC_MASK, info); + } + } + else + { + if (oper->flags & OPERAND_SIGNED) + { + int max = (1 << (oper->bits - 1)); + if (num & max) + { + num = -num & ((1 << oper->bits) - 1); + (*info->fprintf_func) (info->stream, "-"); + } + } + (*info->fprintf_func) (info->stream, "0x%x", num); + } + } +} + +static void +dis_long (insn, memaddr, info) + unsigned long insn; + bfd_vma memaddr; + struct disassemble_info *info; +{ + int i; + struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes; + struct d10v_operand *oper; + int need_paren = 0; + int match = 0; + + while (op->name) + { + if ((op->format & LONG_OPCODE) && ((op->mask & insn) == (unsigned long) op->opcode)) + { + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + for (i = 0; op->operands[i]; i++) + { + oper = (struct d10v_operand *) &d10v_operands[op->operands[i]]; + if (oper->flags == OPERAND_ATPAR) + need_paren = 1; + print_operand (oper, insn, op, memaddr, info); + if (op->operands[i + 1] && oper->bits + && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS + && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS) + (*info->fprintf_func) (info->stream, ", "); + } + break; + } + op++; + } + + if (!match) + (*info->fprintf_func) (info->stream, ".long\t0x%08x", insn); + + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} + +static void +dis_2_short (insn, memaddr, info, order) + unsigned long insn; + bfd_vma memaddr; + struct disassemble_info *info; + int order; +{ + int i, j; + unsigned int ins[2]; + struct d10v_opcode *op; + int match, num_match = 0; + struct d10v_operand *oper; + int need_paren = 0; + + ins[0] = (insn & 0x3FFFFFFF) >> 15; + ins[1] = insn & 0x00007FFF; + + for (j = 0; j < 2; j++) + { + op = (struct d10v_opcode *) d10v_opcodes; + match = 0; + while (op->name) + { + if ((op->format & SHORT_OPCODE) + && ((op->mask & ins[j]) == (unsigned long) op->opcode)) + { + (*info->fprintf_func) (info->stream, "%s\t", op->name); + for (i = 0; op->operands[i]; i++) + { + oper = (struct d10v_operand *) &d10v_operands[op->operands[i]]; + if (oper->flags == OPERAND_ATPAR) + need_paren = 1; + print_operand (oper, ins[j], op, memaddr, info); + if (op->operands[i + 1] && oper->bits + && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS + && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS) + (*info->fprintf_func) (info->stream, ", "); + } + match = 1; + num_match++; + break; + } + op++; + } + if (!match) + (*info->fprintf_func) (info->stream, "unknown"); + + switch (order) + { + case 0: + (*info->fprintf_func) (info->stream, "\t->\t"); + order = -1; + break; + case 1: + (*info->fprintf_func) (info->stream, "\t<-\t"); + order = -1; + break; + case 2: + (*info->fprintf_func) (info->stream, "\t||\t"); + order = -1; + break; + default: + break; + } + } + + if (num_match == 0) + (*info->fprintf_func) (info->stream, ".long\t0x%08x", insn); + + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c new file mode 100644 index 0000000..b2ce10f --- /dev/null +++ b/opcodes/d10v-opc.c @@ -0,0 +1,349 @@ +/* d10v-opc.c -- D10V opcode list + Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/d10v.h" + + +/* The table is sorted. Suitable for searching by a binary search. */ +const struct pd_reg d10v_predefined_registers[] = +{ + { "a0", NULL, OPERAND_ACC0+0 }, + { "a1", NULL, OPERAND_ACC1+1 }, + { "bpc", NULL, OPERAND_CONTROL+3 }, + { "bpsw", NULL, OPERAND_CONTROL+1 }, + { "c", NULL, OPERAND_CFLAG+3 }, + { "cr0", "psw", OPERAND_CONTROL }, + { "cr1", "bpsw", OPERAND_CONTROL+1 }, + { "cr10", "mod_s", OPERAND_CONTROL+10 }, + { "cr11", "mod_e", OPERAND_CONTROL+11 }, + { "cr12", NULL, OPERAND_CONTROL+12 }, + { "cr13", NULL, OPERAND_CONTROL+13 }, + { "cr14", "iba", OPERAND_CONTROL+14 }, + { "cr15", NULL, OPERAND_CONTROL+15 }, + { "cr2", "pc", OPERAND_CONTROL+2 }, + { "cr3", "bpc", OPERAND_CONTROL+3 }, + { "cr4", "dpsw", OPERAND_CONTROL+4 }, + { "cr5", "dpc", OPERAND_CONTROL+5 }, + { "cr6", NULL, OPERAND_CONTROL+6 }, + { "cr7", "rpt_c", OPERAND_CONTROL+7 }, + { "cr8", "rpt_s", OPERAND_CONTROL+8 }, + { "cr9", "rpt_e", OPERAND_CONTROL+9 }, + { "dpc", NULL, OPERAND_CONTROL+5 }, + { "dpsw", NULL, OPERAND_CONTROL+4 }, + { "f0", NULL, OPERAND_FFLAG+0 }, + { "f1", NULL, OPERAND_FFLAG+1 }, + { "iba", NULL, OPERAND_CONTROL+14 }, + { "link", "r13", OPERAND_GPR+13 }, + { "mod_e", NULL, OPERAND_CONTROL+11 }, + { "mod_s", NULL, OPERAND_CONTROL+10 }, + { "pc", NULL, OPERAND_CONTROL+2 }, + { "psw", NULL, OPERAND_CONTROL+0 }, + { "r0", NULL, OPERAND_GPR+0 }, + { "r0-r1", NULL, OPERAND_GPR+0}, + { "r1", NULL, OPERAND_GPR+1 }, + { "r1", NULL, OPERAND_GPR+1 }, + { "r10", NULL, OPERAND_GPR+10 }, + { "r10-r11", NULL, OPERAND_GPR+10 }, + { "r11", NULL, OPERAND_GPR+11 }, + { "r12", NULL, OPERAND_GPR+12 }, + { "r12-r13", NULL, OPERAND_GPR+12 }, + { "r13", NULL, OPERAND_GPR+13 }, + { "r14", NULL, OPERAND_GPR+14 }, + { "r14-r15", NULL, OPERAND_GPR+14 }, + { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) }, + { "r2", NULL, OPERAND_GPR+2 }, + { "r2-r3", NULL, OPERAND_GPR+2 }, + { "r3", NULL, OPERAND_GPR+3 }, + { "r4", NULL, OPERAND_GPR+4 }, + { "r4-r5", NULL, OPERAND_GPR+4 }, + { "r5", NULL, OPERAND_GPR+5 }, + { "r6", NULL, OPERAND_GPR+6 }, + { "r6-r7", NULL, OPERAND_GPR+6 }, + { "r7", NULL, OPERAND_GPR+7 }, + { "r8", NULL, OPERAND_GPR+8 }, + { "r8-r9", NULL, OPERAND_GPR+8 }, + { "r9", NULL, OPERAND_GPR+9 }, + { "rpt_c", NULL, OPERAND_CONTROL+7 }, + { "rpt_e", NULL, OPERAND_CONTROL+9 }, + { "rpt_s", NULL, OPERAND_CONTROL+8 }, + { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) }, +}; + +int +d10v_reg_name_cnt() +{ + return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg)); +} + +const struct d10v_operand d10v_operands[] = +{ +#define UNUSED (0) + { 0, 0, 0 }, +#define RSRC (UNUSED + 1) + { 4, 1, OPERAND_GPR|OPERAND_REG }, +#define RSRC_SP (RSRC + 1) + { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG }, +#define RSRC_NOSP (RSRC_SP + 1) + { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG }, +#define RDST (RSRC_NOSP + 1) + { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG }, +#define ASRC (RDST + 1) + { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define ASRC0ONLY (ASRC + 1) + { 1, 4, OPERAND_ACC0|OPERAND_REG }, +#define ADST (ASRC0ONLY + 1) + { 1, 8, OPERAND_DEST|OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define RSRCE (ADST + 1) + { 4, 1, OPERAND_EVEN|OPERAND_GPR|OPERAND_REG }, +#define RDSTE (RSRCE + 1) + { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_GPR|OPERAND_REG }, +#define NUM16 (RDSTE + 1) + { 16, 0, OPERAND_NUM|OPERAND_SIGNED }, +#define NUM3 (NUM16 + 1) /* rac, rachi */ + { 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 }, +#define NUM4 (NUM3 + 1) + { 4, 1, OPERAND_NUM|OPERAND_SIGNED }, +#define UNUM4 (NUM4 + 1) + { 4, 1, OPERAND_NUM }, +#define UNUM4S (UNUM4 + 1) /* addi, slli, srai, srli, subi */ + { 4, 1, OPERAND_NUM|OPERAND_SHIFT }, +#define UNUM8 (UNUM4S + 1) /* repi */ + { 8, 16, OPERAND_NUM }, +#define UNUM16 (UNUM8 + 1) /* cmpui */ + { 16, 0, OPERAND_NUM }, +#define ANUM16 (UNUM16 + 1) + { 16, 0, OPERAND_ADDR|OPERAND_SIGNED }, +#define ANUM8 (ANUM16 + 1) + { 8, 0, OPERAND_ADDR|OPERAND_SIGNED }, +#define ASRC2 (ANUM8 + 1) + { 1, 8, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define RSRC2 (ASRC2 + 1) + { 4, 5, OPERAND_GPR|OPERAND_REG }, +#define RSRC2E (RSRC2 + 1) + { 4, 5, OPERAND_GPR|OPERAND_REG|OPERAND_EVEN }, +#define ASRC0 (RSRC2E + 1) + { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define ADST0 (ASRC0 + 1) + { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG|OPERAND_DEST }, +#define FFSRC (ADST0 + 1) + { 2, 1, OPERAND_REG | OPERAND_FFLAG }, +#define CFSRC (FFSRC + 1) + { 2, 1, OPERAND_REG | OPERAND_CFLAG }, +#define FDST (CFSRC + 1) + { 1, 5, OPERAND_REG | OPERAND_FFLAG | OPERAND_DEST}, +#define ATSIGN (FDST + 1) + { 0, 0, OPERAND_ATSIGN}, +#define ATPAR (ATSIGN + 1) /* "@(" */ + { 0, 0, OPERAND_ATPAR}, +#define PLUS (ATPAR + 1) /* postincrement */ + { 0, 0, OPERAND_PLUS}, +#define MINUS (PLUS + 1) /* postdecrement */ + { 0, 0, OPERAND_MINUS}, +#define ATMINUS (MINUS + 1) /* predecrement */ + { 0, 0, OPERAND_ATMINUS}, +#define CSRC (ATMINUS + 1) /* control register */ + { 4, 1, OPERAND_REG|OPERAND_CONTROL}, +#define CDST (CSRC + 1) /* control register */ + { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, +}; + +const struct d10v_opcode d10v_opcodes[] = { + { "abs", SHORT_2, 1, EITHER, PAR|WF0, 0x4607, 0x7e1f, { RDST } }, + { "abs", SHORT_2, 1, IU, PAR|WF0, 0x5607, 0x7eff, { ADST } }, + { "add", SHORT_2, 1, EITHER, PAR|WCAR, 0x0200, 0x7e01, { RDST, RSRC } }, + { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } }, + { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } }, + { "add2w", SHORT_2, 2, IU, PAR|WCAR, 0x1200, 0x7e23, { RDSTE, RSRCE } }, + { "add3", LONG_L, 1, MU, SEQ|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "addi", SHORT_2, 1, EITHER, PAR|WCAR, 0x201, 0x7e01, { RDST, UNUM4S } }, + { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, + { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } }, + { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "bl.s", SHORT_B, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } }, + { "bl.l", LONG_B, 3, MU, BRANCH_LINK|SEQ, 0x24800000, 0x3fff0000, { ANUM16 } }, + { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } }, + { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "bra.s", SHORT_B, 3, MU, ALONE|BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } }, + { "bra.l", LONG_B, 3, MU, BRANCH|SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, + { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "brf0f.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4a00, 0x7f00, { ANUM8 } }, + { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } }, + { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } }, + { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, + { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } }, + { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RDST, UNUM4 } }, + { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } }, + { "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, + { "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } }, + { "cmpeq", SHORT_2, 1, EITHER, PAR|WF0, 0x400, 0x7e01, { RSRC2, RSRC } }, + { "cmpeq", SHORT_2, 1, IU, PAR|WF0, 0x1403, 0x7eef, { ASRC2, ASRC } }, + { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "cmpeqi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x401, 0x7e01, { RSRC2, NUM4 } }, + { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "cmpi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x601, 0x7e01, { RSRC2, NUM4 } }, + { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } }, + { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } }, + { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } }, + { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } }, + { "dbt", SHORT_2, 5, MU, ALONE|PAR, 0x5f20, 0x7fff, { 0 } }, + { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, + { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } }, + { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } }, + { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } }, + { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } }, + { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } }, + { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } }, + { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } }, + { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } }, + { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } }, + { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } }, + { "jl", SHORT_2, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } }, + { "jmp", SHORT_2, 3, MU, ALONE|BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } }, + { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } }, + { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } }, + { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } }, + { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } }, + { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } }, + { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } }, + { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } }, + { "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } }, + { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "ldi.s", SHORT_2, 1, EITHER, PAR|RMEM, 0x4001, 0x7e01 , { RDST, NUM4 } }, + { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } }, + { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ldub", SHORT_2, 1, MU, PAR|RMEM, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "max", SHORT_2, 1, IU, PAR|WF0, 0x2600, 0x7e01, { RDST, RSRC } }, + { "max", SHORT_2, 1, IU, PAR|WF0, 0x3600, 0x7ee3, { ADST, RSRCE } }, + { "max", SHORT_2, 1, IU, PAR|WF0, 0x3602, 0x7eef, { ADST, ASRC } }, + { "min", SHORT_2, 1, IU, PAR|WF0, 0x2601, 0x7e01 , { RDST, RSRC } }, + { "min", SHORT_2, 1, IU, PAR|WF0, 0x3601, 0x7ee3 , { ADST, RSRCE } }, + { "min", SHORT_2, 1, IU, PAR|WF0, 0x3603, 0x7eef, { ADST, ASRC } }, + { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } }, + { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } }, + { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } }, + { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } }, + { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } }, + { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } }, + { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } }, + { "mvf0f", SHORT_2, 1, EITHER, PAR|RF0, 0x4400, 0x7e01, { RDST, RSRC } }, + { "mvf0t", SHORT_2, 1, EITHER, PAR|RF0, 0x4401, 0x7e01, { RDST, RSRC } }, + { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } }, + { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } }, + { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } }, + { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } }, + { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } }, + { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } }, + { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } }, + { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } }, + { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } }, + { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } }, + { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } }, + { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } }, + { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } }, + { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } }, + { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + /* Special case. sac&sachi must occur before rac&rachi because they have + intersecting masks! The masks for rac&rachi will match sac&sachi but + not the other way around. + */ + { "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } }, + { "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } }, + { "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } }, + { "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } }, + { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } }, + { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } }, + { "rtd", SHORT_2, 3, MU, ALONE|PAR, 0x5f60, 0x7fff, { 0 } }, + { "rte", SHORT_2, 3, MU, ALONE|PAR, 0x5f40, 0x7fff, { 0 } }, + { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } }, + { "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } }, + { "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } }, + { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } }, + { "sleep", SHORT_2, 1, MU, ALONE|PAR, 0x5fc0, 0x7fff, { 0 } }, + { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } }, + { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } }, + { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } }, + { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4S } }, + { "slx", SHORT_2, 1, IU, PAR|RF0, 0x460b, 0x7e1f, { RDST } }, + { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } }, + { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } }, + { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } }, + { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4S } }, + { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } }, + { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } }, + { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } }, + { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4S } }, + { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } }, + { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } }, + { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } }, + { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } }, + { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } }, + { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, + { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, + { "stop", SHORT_2, 1, MU, ALONE|PAR, 0x5fe0, 0x7fff, { 0 } }, + { "sub", SHORT_2, 1, EITHER, PAR|WCAR, 0x0, 0x7e01, { RDST, RSRC } }, + { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } }, + { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } }, + { "sub2w", SHORT_2, 1, IU, PAR|WCAR, 0x1000, 0x7e23, { RDSTE, RSRCE } }, + { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } }, + { "trap", SHORT_2, 5, MU, ALONE|BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } }, + { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "wait", SHORT_2, 1, MU, ALONE|PAR, 0x5f80, 0x7fff, { 0 } }, + { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } }, + { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { 0, 0, 0, 0, 0, 0, 0, { 0 } }, +}; + + diff --git a/opcodes/d30v-dis.c b/opcodes/d30v-dis.c new file mode 100644 index 0000000..c6c3f74 --- /dev/null +++ b/opcodes/d30v-dis.c @@ -0,0 +1,407 @@ +/* Disassemble D30V instructions. + Copyright 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/d30v.h" +#include "dis-asm.h" +#include "opintl.h" + +#define PC_MASK 0xFFFFFFFF + +static int lookup_opcode PARAMS ((struct d30v_insn *insn, long num, int is_long)); +static void print_insn PARAMS ((struct disassemble_info *info, bfd_vma memaddr, long long num, + struct d30v_insn *insn, int is_long, int show_ext)); +static int extract_value PARAMS ((long long num, struct d30v_operand *oper, int is_long)); + +int +print_insn_d30v (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status, result; + bfd_byte buffer[12]; + unsigned long in1, in2; + struct d30v_insn insn; + long long num; + + insn.form = (struct d30v_format *) NULL; + + info->bytes_per_line = 8; + info->bytes_per_chunk = 4; + info->display_endian = BFD_ENDIAN_BIG; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + in1 = bfd_getb32 (buffer); + + status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info); + if (status != 0) + { + info->bytes_per_line = 8; + if (!(result = lookup_opcode (&insn, in1, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%x", in1); + else + print_insn (info, memaddr, (long long) in1, &insn, 0, result); + return 4; + } + in2 = bfd_getb32 (buffer); + + if (in1 & in2 & FM01) + { + /* LONG instruction. */ + if (!(result = lookup_opcode (&insn, in1, 1))) + { + (*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2); + return 8; + } + num = (long long) in1 << 32 | in2; + print_insn (info, memaddr, num, &insn, 1, result); + } + else + { + num = in1; + if (!(result = lookup_opcode (&insn, in1, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%x", in1); + else + print_insn (info, memaddr, num, &insn, 0, result); + + switch (((in1 >> 31) << 1) | (in2 >> 31)) + { + case 0: + (*info->fprintf_func) (info->stream, "\t||\t"); + break; + case 1: + (*info->fprintf_func) (info->stream, "\t->\t"); + break; + case 2: + (*info->fprintf_func) (info->stream, "\t<-\t"); + default: + break; + } + + insn.form = (struct d30v_format *) NULL; + num = in2; + if (!(result = lookup_opcode (&insn, in2, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%x", in2); + else + print_insn (info, memaddr, num, &insn, 0, result); + } + return 8; +} + +/* Return 0 if lookup fails, + 1 if found and only one form, + 2 if found and there are short and long forms. */ + +static int +lookup_opcode (insn, num, is_long) + struct d30v_insn *insn; + long num; + int is_long; +{ + int i = 0, index; + struct d30v_format *f; + struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table; + int op1 = (num >> 25) & 0x7; + int op2 = (num >> 20) & 0x1f; + int mod = (num >> 18) & 0x3; + + /* Find the opcode. */ + do + { + if ((op->op1 == op1) && (op->op2 == op2)) + break; + op++; + } + while (op->name); + + if (!op || !op->name) + return 0; + + while (op->op1 == op1 && op->op2 == op2) + { + /* Scan through all the formats for the opcode. */ + index = op->format[i++]; + do + { + f = (struct d30v_format *) &d30v_format_table[index]; + while (f->form == index) + { + if ((!is_long || f->form >= LONG) && (f->modifier == mod)) + { + insn->form = f; + break; + } + f++; + } + if (insn->form) + break; + } + while ((index = op->format[i++]) != 0); + if (insn->form) + break; + op++; + i = 0; + } + if (insn->form == NULL) + return 0; + + insn->op = op; + insn->ecc = (num >> 28) & 0x7; + if (op->format[1]) + return 2; + else + return 1; +} + +static void +print_insn (info, memaddr, num, insn, is_long, show_ext) + struct disassemble_info *info; + bfd_vma memaddr; + long long num; + struct d30v_insn *insn; + int is_long; + int show_ext; +{ + int val, opnum, need_comma = 0; + struct d30v_operand *oper; + int i, match, opind = 0, need_paren = 0, found_control = 0; + + (*info->fprintf_func) (info->stream, "%s", insn->op->name); + + /* Check for CMP or CMPU. */ + if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME) + { + opind++; + val = + extract_value (num, + (struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]], + is_long); + (*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]); + } + + /* Add in ".s" or ".l". */ + if (show_ext == 2) + { + if (is_long) + (*info->fprintf_func) (info->stream, ".l"); + else + (*info->fprintf_func) (info->stream, ".s"); + } + + if (insn->ecc) + (*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]); + + (*info->fprintf_func) (info->stream, "\t"); + + while ((opnum = insn->form->operands[opind++]) != 0) + { + int bits; + oper = (struct d30v_operand *) &d30v_operand_table[opnum]; + bits = oper->bits; + if (oper->flags & OPERAND_SHIFT) + bits += 3; + + if (need_comma + && oper->flags != OPERAND_PLUS + && oper->flags != OPERAND_MINUS) + { + need_comma = 0; + (*info->fprintf_func) (info->stream, ", "); + } + + if (oper->flags == OPERAND_ATMINUS) + { + (*info->fprintf_func) (info->stream, "@-"); + continue; + } + if (oper->flags == OPERAND_MINUS) + { + (*info->fprintf_func) (info->stream, "-"); + continue; + } + if (oper->flags == OPERAND_PLUS) + { + (*info->fprintf_func) (info->stream, "+"); + continue; + } + if (oper->flags == OPERAND_ATSIGN) + { + (*info->fprintf_func) (info->stream, "@"); + continue; + } + if (oper->flags == OPERAND_ATPAR) + { + (*info->fprintf_func) (info->stream, "@("); + need_paren = 1; + continue; + } + + if (oper->flags == OPERAND_SPECIAL) + continue; + + val = extract_value (num, oper, is_long); + + if (oper->flags & OPERAND_REG) + { + match = 0; + if (oper->flags & OPERAND_CONTROL) + { + struct d30v_operand *oper3 = + (struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]]; + int id = extract_value (num, oper3, is_long); + found_control = 1; + switch (id) + { + case 0: + val |= OPERAND_CONTROL; + break; + case 1: + case 2: + val = OPERAND_CONTROL + MAX_CONTROL_REG + id; + break; + case 3: + val |= OPERAND_FLAG; + break; + default: + fprintf (stderr, "illegal id (%d)\n", id); + } + } + else if (oper->flags & OPERAND_ACC) + val |= OPERAND_ACC; + else if (oper->flags & OPERAND_FLAG) + val |= OPERAND_FLAG; + for (i = 0; i < reg_name_cnt (); i++) + { + if (val == pre_defined_registers[i].value) + { + if (pre_defined_registers[i].pname) + (*info->fprintf_func) + (info->stream, "%s", pre_defined_registers[i].pname); + else + (*info->fprintf_func) + (info->stream, "%s", pre_defined_registers[i].name); + match = 1; + break; + } + } + if (match == 0) + { + /* This would only get executed if a register was not in + the register table. */ + (*info->fprintf_func) + (info->stream, _(""), val & 0x3F); + } + } + /* repeati has a relocation, but its first argument is a plain + immediate. OTOH instructions like djsri have a pc-relative + delay target, but an absolute jump target. Therefore, a test + of insn->op->reloc_flag is not specific enough; we must test + if the actual operand we are handling now is pc-relative. */ + else if (oper->flags & OPERAND_PCREL) + { + int neg = 0; + + /* IMM6S3 is unsigned. */ + if (oper->flags & OPERAND_SIGNED || bits == 32) + { + long max; + max = (1 << (bits - 1)); + if (val & max) + { + if (bits == 32) + val = -val; + else + val = -val & ((1 << bits) - 1); + neg = 1; + } + } + if (neg) + { + (*info->fprintf_func) (info->stream, "-%x\t(", val); + (*info->print_address_func) ((memaddr - val) & PC_MASK, info); + (*info->fprintf_func) (info->stream, ")"); + } + else + { + (*info->fprintf_func) (info->stream, "%x\t(", val); + (*info->print_address_func) ((memaddr + val) & PC_MASK, info); + (*info->fprintf_func) (info->stream, ")"); + } + } + else if (insn->op->reloc_flag == RELOC_ABS) + { + (*info->print_address_func) (val, info); + } + else + { + if (oper->flags & OPERAND_SIGNED) + { + int max = (1 << (bits - 1)); + if (val & max) + { + val = -val; + if (bits < 32) + val &= ((1 << bits) - 1); + (*info->fprintf_func) (info->stream, "-"); + } + } + (*info->fprintf_func) (info->stream, "0x%x", val); + } + /* If there is another operand, then write a comma and space. */ + if (insn->form->operands[opind] && !(found_control && opind == 2)) + need_comma = 1; + } + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} + +static int +extract_value (num, oper, is_long) + long long num; + struct d30v_operand *oper; + int is_long; +{ + int val; + int shift = 12 - oper->position; + int mask = (0xFFFFFFFF >> (32 - oper->bits)); + + if (is_long) + { + if (oper->bits == 32) + { + /* Piece together 32-bit constant. */ + val = ((num & 0x3FFFF) + | ((num & 0xFF00000) >> 2) + | ((num & 0x3F00000000LL) >> 6)); + } + else + val = (num >> (32 + shift)) & mask; + } + else + val = (num >> shift) & mask; + + if (oper->flags & OPERAND_SHIFT) + val <<= 3; + + return val; +} diff --git a/opcodes/d30v-opc.c b/opcodes/d30v-opc.c new file mode 100644 index 0000000..6fe993a --- /dev/null +++ b/opcodes/d30v-opc.c @@ -0,0 +1,513 @@ +/* d30v-opc.c -- D30V opcode list + Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/d30v.h" + +/* This table is sorted. */ +/* If you add anything, it MUST be in alphabetical order */ +/* The first field is the name the assembler uses when looking */ +/* up orcodes. The second field is the name the disassembler will use. */ +/* This allows the assembler to assemble references to r63 (for example) */ +/* or "sp". The disassembler will always use the preferred form (sp) */ +const struct pd_reg pre_defined_registers[] = +{ + { "a0", NULL, OPERAND_ACC+0 }, + { "a1", NULL, OPERAND_ACC+1 }, + { "bpc", NULL, OPERAND_CONTROL+3 }, + { "bpsw", NULL, OPERAND_CONTROL+1 }, + { "c", "c", OPERAND_FLAG+7 }, + { "cr0", "psw", OPERAND_CONTROL }, + { "cr1", "bpsw", OPERAND_CONTROL+1 }, + { "cr10", "mod_s", OPERAND_CONTROL+10 }, + { "cr11", "mod_e", OPERAND_CONTROL+11 }, + { "cr12", NULL, OPERAND_CONTROL+12 }, + { "cr13", NULL, OPERAND_CONTROL+13 }, + { "cr14", "iba", OPERAND_CONTROL+14 }, + { "cr15", "eit_vb", OPERAND_CONTROL+15 }, + { "cr16", "int_s", OPERAND_CONTROL+16 }, + { "cr17", "int_m", OPERAND_CONTROL+17 }, + { "cr18", NULL, OPERAND_CONTROL+18 }, + { "cr19", NULL, OPERAND_CONTROL+19 }, + { "cr2", "pc", OPERAND_CONTROL+2 }, + { "cr20", NULL, OPERAND_CONTROL+20 }, + { "cr21", NULL, OPERAND_CONTROL+21 }, + { "cr22", NULL, OPERAND_CONTROL+22 }, + { "cr23", NULL, OPERAND_CONTROL+23 }, + { "cr24", NULL, OPERAND_CONTROL+24 }, + { "cr25", NULL, OPERAND_CONTROL+25 }, + { "cr26", NULL, OPERAND_CONTROL+26 }, + { "cr27", NULL, OPERAND_CONTROL+27 }, + { "cr28", NULL, OPERAND_CONTROL+28 }, + { "cr29", NULL, OPERAND_CONTROL+29 }, + { "cr3", "bpc", OPERAND_CONTROL+3 }, + { "cr30", NULL, OPERAND_CONTROL+30 }, + { "cr31", NULL, OPERAND_CONTROL+31 }, + { "cr32", NULL, OPERAND_CONTROL+32 }, + { "cr33", NULL, OPERAND_CONTROL+33 }, + { "cr34", NULL, OPERAND_CONTROL+34 }, + { "cr35", NULL, OPERAND_CONTROL+35 }, + { "cr36", NULL, OPERAND_CONTROL+36 }, + { "cr37", NULL, OPERAND_CONTROL+37 }, + { "cr38", NULL, OPERAND_CONTROL+38 }, + { "cr39", NULL, OPERAND_CONTROL+39 }, + { "cr4", "dpsw", OPERAND_CONTROL+4 }, + { "cr40", NULL, OPERAND_CONTROL+40 }, + { "cr41", NULL, OPERAND_CONTROL+41 }, + { "cr42", NULL, OPERAND_CONTROL+42 }, + { "cr43", NULL, OPERAND_CONTROL+43 }, + { "cr44", NULL, OPERAND_CONTROL+44 }, + { "cr45", NULL, OPERAND_CONTROL+45 }, + { "cr46", NULL, OPERAND_CONTROL+46 }, + { "cr47", NULL, OPERAND_CONTROL+47 }, + { "cr48", NULL, OPERAND_CONTROL+48 }, + { "cr49", NULL, OPERAND_CONTROL+49 }, + { "cr5","dpc", OPERAND_CONTROL+5 }, + { "cr50", NULL, OPERAND_CONTROL+50 }, + { "cr51", NULL, OPERAND_CONTROL+51 }, + { "cr52", NULL, OPERAND_CONTROL+52 }, + { "cr53", NULL, OPERAND_CONTROL+53 }, + { "cr54", NULL, OPERAND_CONTROL+54 }, + { "cr55", NULL, OPERAND_CONTROL+55 }, + { "cr56", NULL, OPERAND_CONTROL+56 }, + { "cr57", NULL, OPERAND_CONTROL+57 }, + { "cr58", NULL, OPERAND_CONTROL+58 }, + { "cr59", NULL, OPERAND_CONTROL+59 }, + { "cr6", NULL, OPERAND_CONTROL+6 }, + { "cr60", NULL, OPERAND_CONTROL+60 }, + { "cr61", NULL, OPERAND_CONTROL+61 }, + { "cr62", NULL, OPERAND_CONTROL+62 }, + { "cr63", NULL, OPERAND_CONTROL+63 }, + { "cr7", "rpt_c", OPERAND_CONTROL+7 }, + { "cr8", "rpt_s", OPERAND_CONTROL+8 }, + { "cr9", "rpt_e", OPERAND_CONTROL+9 }, + { "dpc", NULL, OPERAND_CONTROL+5 }, + { "dpsw", NULL, OPERAND_CONTROL+4 }, + { "eit_vb", NULL, OPERAND_CONTROL+15 }, + { "f0", NULL, OPERAND_FLAG+0 }, + { "f1", NULL, OPERAND_FLAG+1 }, + { "f2", NULL, OPERAND_FLAG+2 }, + { "f3", NULL, OPERAND_FLAG+3 }, + { "f4", "s", OPERAND_FLAG+4 }, + { "f5", "v", OPERAND_FLAG+5 }, + { "f6", "va", OPERAND_FLAG+6 }, + { "f7", "c", OPERAND_FLAG+7 }, + { "iba", NULL, OPERAND_CONTROL+14 }, + { "int_m", NULL, OPERAND_CONTROL+17 }, + { "int_s", NULL, OPERAND_CONTROL+16 }, + { "link", "r62", 62 }, + { "mod_e", NULL, OPERAND_CONTROL+11 }, + { "mod_s", NULL, OPERAND_CONTROL+10 }, + { "pc", NULL, OPERAND_CONTROL+2 }, + { "psw", NULL, OPERAND_CONTROL }, + { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 }, + { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 }, + { "r0", NULL, 0 }, + { "r1", NULL, 1 }, + { "r10", NULL, 10 }, + { "r11", NULL, 11 }, + { "r12", NULL, 12 }, + { "r13", NULL, 13 }, + { "r14", NULL, 14 }, + { "r15", NULL, 15 }, + { "r16", NULL, 16 }, + { "r17", NULL, 17 }, + { "r18", NULL, 18 }, + { "r19", NULL, 19 }, + { "r2", NULL, 2 }, + { "r20", NULL, 20 }, + { "r21", NULL, 21 }, + { "r22", NULL, 22 }, + { "r23", NULL, 23 }, + { "r24", NULL, 24 }, + { "r25", NULL, 25 }, + { "r26", NULL, 26 }, + { "r27", NULL, 27 }, + { "r28", NULL, 28 }, + { "r29", NULL, 29 }, + { "r3", NULL, 3 }, + { "r30", NULL, 30 }, + { "r31", NULL, 31 }, + { "r32", NULL, 32 }, + { "r33", NULL, 33 }, + { "r34", NULL, 34 }, + { "r35", NULL, 35 }, + { "r36", NULL, 36 }, + { "r37", NULL, 37 }, + { "r38", NULL, 38 }, + { "r39", NULL, 39 }, + { "r4", NULL, 4 }, + { "r40", NULL, 40 }, + { "r41", NULL, 41 }, + { "r42", NULL, 42 }, + { "r43", NULL, 43 }, + { "r44", NULL, 44 }, + { "r45", NULL, 45 }, + { "r46", NULL, 46 }, + { "r47", NULL, 47 }, + { "r48", NULL, 48 }, + { "r49", NULL, 49 }, + { "r5", NULL, 5 }, + { "r50", NULL, 50 }, + { "r51", NULL, 51 }, + { "r52", NULL, 52 }, + { "r53", NULL, 53 }, + { "r54", NULL, 54 }, + { "r55", NULL, 55 }, + { "r56", NULL, 56 }, + { "r57", NULL, 57 }, + { "r58", NULL, 58 }, + { "r59", NULL, 59 }, + { "r6", NULL, 6 }, + { "r60", NULL, 60 }, + { "r61", NULL, 61 }, + { "r62", "link", 62 }, + { "r63", "sp", 63 }, + { "r7", NULL, 7 }, + { "r8", NULL, 8 }, + { "r9", NULL, 9 }, + { "rpt_c", NULL, OPERAND_CONTROL+7 }, + { "rpt_e", NULL, OPERAND_CONTROL+9 }, + { "rpt_s", NULL, OPERAND_CONTROL+8 }, + { "s", NULL, OPERAND_FLAG+4 }, + { "sp", NULL, 63 }, + { "v", NULL, OPERAND_FLAG+5 }, + { "va", NULL, OPERAND_FLAG+6 }, +}; + +int +reg_name_cnt() +{ + return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); +} + +/* OPCODE TABLE */ +/* The format of this table is defined in opcode/d30v.h */ +const struct d30v_opcode d30v_opcode_table[] = { + { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, + { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 }, + { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 }, + { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 }, + { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 }, + { "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 }, + { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, + { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 }, + { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 }, + { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, + { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 }, + { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 }, + { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, + { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 }, + { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, + { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 }, + { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 }, + { "mvtacc", IALU2, 0xf, { SHORT_AR }, IU, 0, 0, 0 }, + { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 }, + { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 }, + { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 }, + { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 }, + { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 }, + { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 }, + { "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, + { "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, + { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 }, + { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 }, + { "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 }, + { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 }, + { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 }, + { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, + { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, + { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 }, + { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 }, + { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 }, + { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 }, + { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 }, + { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 }, + { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 }, + { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, FLAG_JSR, FLAG_SM | FLAG_LKR, 0 }, + { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 }, + { NULL, 0, 0, { 0 }, 0, 0, 0, 0 }, +}; + + +/* now define the operand types */ +/* format is length, bits, position, flags */ +const struct d30v_operand d30v_operand_table[] = +{ +#define UNUSED (0) + { 0, 0, 0, 0 }, +#define Ra (UNUSED + 1) + { 6, 6, 0, OPERAND_REG|OPERAND_DEST }, +#define Ra2 (Ra + 1) + { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG }, +#define Ra3 (Ra2 + 1) + { 6, 6, 0, OPERAND_REG }, +#define Rb (Ra3 + 1) + { 6, 6, 6, OPERAND_REG }, +#define Rb2 (Rb + 1) + { 6, 6, 6, OPERAND_REG|OPERAND_DEST }, +#define Rc (Rb2 + 1) + { 6, 6, 12, OPERAND_REG }, +#define Aa (Rc + 1) + { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, +#define Ab (Aa + 1) + { 6, 1, 6, OPERAND_ACC|OPERAND_REG }, +#define IMM5 (Ab + 1) + { 6, 5, 12, OPERAND_NUM }, +#define IMM5U (IMM5 + 1) + { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */ +#define IMM5S3 (IMM5U + 1) + { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */ +#define IMM6 (IMM5S3 + 1) + { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED }, +#define IMM6U (IMM6 + 1) + { 6, 6, 0, OPERAND_NUM }, +#define IMM6U2 (IMM6U + 1) + { 6, 6, 12, OPERAND_NUM }, +#define REL6S3 (IMM6U2 + 1) + { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL }, +#define REL12S3 (REL6S3 + 1) + { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL }, +#define IMM12S3 (REL12S3 + 1) + { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, +#define REL18S3 (IMM12S3 + 1) + { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL }, +#define IMM18S3 (REL18S3 + 1) + { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, +#define REL32 (IMM18S3 + 1) + { 32, 32, 0, OPERAND_NUM|OPERAND_PCREL }, +#define IMM32 (REL32 + 1) + { 32, 32, 0, OPERAND_NUM }, +#define Fa (IMM32 + 1) + { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST }, +#define Fb (Fa + 1) + { 6, 3, 6, OPERAND_REG | OPERAND_FLAG }, +#define Fc (Fb + 1) + { 6, 3, 12, OPERAND_REG | OPERAND_FLAG }, +#define ATSIGN (Fc + 1) + { 0, 0, 0, OPERAND_ATSIGN}, +#define ATPAR (ATSIGN + 1) /* "@(" */ + { 0, 0, 0, OPERAND_ATPAR}, +#define PLUS (ATPAR + 1) /* postincrement */ + { 0, 0, 0, OPERAND_PLUS}, +#define MINUS (PLUS + 1) /* postdecrement */ + { 0, 0, 0, OPERAND_MINUS}, +#define ATMINUS (MINUS + 1) /* predecrement */ + { 0, 0, 0, OPERAND_ATMINUS}, +#define Ca (ATMINUS + 1) /* control register */ + { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, +#define Cb (Ca + 1) /* control register */ + { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL}, +#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */ + { 3, 3, -3, OPERAND_NAME}, +#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */ + { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST}, +#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */ + { 6, 2, 12, OPERAND_SPECIAL}, +}; + +/* now we need to define the instruction formats */ +const struct d30v_format d30v_format_table[] = +{ + { 0, 0, { 0 } }, + { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ + { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ + { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ + { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ + { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ + { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */ + { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ + { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */ + { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ + { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */ + { SHORT_B1, 0, { Rc } }, /* Rc */ + { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */ + { SHORT_B2r, 2, { REL18S3 } }, /* rel18 */ + { SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */ + { SHORT_B3r, 0, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3r, 2, { Ra3, REL12S3 } }, /* Ra,rel12 */ + { SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */ + { SHORT_B3br, 1, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3br, 3, { Ra3, REL12S3 } }, /* Ra,rel12 */ + { SHORT_D1r, 0, { Ra, Rc } }, /* Ra,Rc */ + { SHORT_D1r, 2, { Ra, REL12S3 } }, /* Ra,rel12s3 */ + { SHORT_D2, 0, { REL6S3, Rc } }, /* rel6s3,Rc */ + { SHORT_D2, 2, { REL6S3, IMM12S3 } }, /* rel6s3,imm12s3 */ + { SHORT_D2r, 0, { REL6S3, Rc } }, /* rel6s3,Rc */ + { SHORT_D2r, 2, { REL6S3, REL12S3 } }, /* rel6s3,rel12s3 */ + { SHORT_D2Br, 0, { IMM6U, Rc } }, /* imm6u,Rc */ + { SHORT_D2Br, 2, { IMM6U, REL12S3 } }, /* imm6u,rel12s3 */ + { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */ + { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */ + { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */ + { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */ + { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */ + { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */ + { SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ + { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */ + { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ + { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */ + { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ + { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} }, /* CC Fa2,Rb,imm6 */ + { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */ + { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */ + { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ + { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ + { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ + { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */ + { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */ + { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */ + { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ + { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ + { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ + { SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */ + { SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */ + { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */ + { SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ + { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */ + { LONG_U, 2, { IMM32 } }, /* imm32 */ + { LONG_Ur, 2, { REL32 } }, /* rel32 */ + { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */ + { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ + { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ + { LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */ + { LONG_2r, 2, { Ra3, REL32 } }, /* Ra,rel32 */ + { LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */ + { LONG_2br, 3, { Ra3, REL32 } }, /* Ra,rel32 */ + { LONG_D, 2, { REL6S3, IMM32 } }, /* rel6s3,imm32 */ + { LONG_Dr, 2, { REL6S3, REL32 } }, /* rel6s3,rel32 */ + { LONG_Dbr, 2, { IMM6U, REL32 } }, /* imm6,rel32 */ + { 0, 0, { 0 } }, +}; + +const char *d30v_ecc_names[] = +{ + "al", + "tx", + "fx", + "xt", + "xf", + "tt", + "tf", + "res" +}; + +const char *d30v_cc_names[] = +{ + "eq", + "ne", + "gt", + "ge", + "lt", + "le", + "ps", + "ng", + NULL +}; diff --git a/opcodes/dep-in.sed b/opcodes/dep-in.sed new file mode 100644 index 0000000..e373d4c --- /dev/null +++ b/opcodes/dep-in.sed @@ -0,0 +1,22 @@ +:loop +/\\$/N +s/\\\n */ /g +t loop + +s!\.o:!.lo:! +s! @BFD_H@! $(BFD_H)!g +s!@INCDIR@!$(INCDIR)!g +s!@TOPDIR@/include!$(INCDIR)!g +s!@BFDDIR@!$(BFDDIR)!g +s!@TOPDIR@/bfd!$(BFDDIR)!g +s!@SRCDIR@/!!g + +s/\\\n */ /g + +s/ *$// +s/ */ /g +s/ *:/:/g +/:$/d + +s/\(.\{50\}[^ ]*\) /\1 \\\ + /g diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c new file mode 100644 index 0000000..8f846a9 --- /dev/null +++ b/opcodes/dis-buf.c @@ -0,0 +1,118 @@ +/* Disassemble from a buffer, for GNU. + Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000 + Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include +#include "opintl.h" + +/* Get LENGTH bytes from info's buffer, at target address memaddr. + Transfer them to myaddr. */ +int +buffer_read_memory (memaddr, myaddr, length, info) + bfd_vma memaddr; + bfd_byte *myaddr; + unsigned int length; + struct disassemble_info *info; +{ + unsigned int opb = info->octets_per_byte; + unsigned int end_addr_offset = length / opb; + unsigned int max_addr_offset = info->buffer_length / opb; + unsigned int octets = (memaddr - info->buffer_vma) * opb; + + if (memaddr < info->buffer_vma + || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset) + /* Out of bounds. Use EIO because GDB uses it. */ + return EIO; + memcpy (myaddr, info->buffer + octets, length); + + return 0; +} + +/* Print an error message. We can assume that this is in response to + an error return from buffer_read_memory. */ +void +perror_memory (status, memaddr, info) + int status; + bfd_vma memaddr; + struct disassemble_info *info; +{ + if (status != EIO) + /* Can't happen. */ + info->fprintf_func (info->stream, _("Unknown error %d\n"), status); + else + /* Actually, address between memaddr and memaddr + len was + out of bounds. */ + info->fprintf_func (info->stream, + _("Address 0x%x is out of bounds.\n"), memaddr); +} + +/* This could be in a separate file, to save miniscule amounts of space + in statically linked executables. */ + +/* Just print the address is hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ + +void +generic_print_address (addr, info) + bfd_vma addr; + struct disassemble_info *info; +{ + char buf[30]; + + sprintf_vma (buf, addr); + (*info->fprintf_func) (info->stream, "0x%s", buf); +} + +#if 0 +/* Just concatenate the address as hex. This is included for + completeness even though both GDB and objdump provide their own (to + print symbolic addresses). */ + +void generic_strcat_address PARAMS ((bfd_vma, char *, int)); + +void +generic_strcat_address (addr, buf, len) + bfd_vma addr; + char *buf; + int len; +{ + if (buf != (char *)NULL && len > 0) + { + char tmpBuf[30]; + + sprintf_vma (tmpBuf, addr); + if ((strlen (buf) + strlen (tmpBuf)) <= (unsigned int) len) + strcat (buf, tmpBuf); + else + strncat (buf, tmpBuf, (len - strlen(buf))); + } + return; +} +#endif + +/* Just return the given address. */ + +int +generic_symbol_at_address (addr, info) + bfd_vma addr ATTRIBUTE_UNUSED; + struct disassemble_info *info ATTRIBUTE_UNUSED; +{ + return 1; +} diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c new file mode 100644 index 0000000..bfb22c2 --- /dev/null +++ b/opcodes/disassemble.c @@ -0,0 +1,354 @@ +/* Select disassembly routine for specified architecture. + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" + +#ifdef ARCH_all +#define ARCH_a29k +#define ARCH_alpha +#define ARCH_arc +#define ARCH_arm +#define ARCH_avr +#define ARCH_cris +#define ARCH_d10v +#define ARCH_d30v +#define ARCH_dlx +#define ARCH_h8300 +#define ARCH_h8500 +#define ARCH_hppa +#define ARCH_i370 +#define ARCH_i386 +#define ARCH_i860 +#define ARCH_i960 +#define ARCH_ia64 +#define ARCH_fr30 +#define ARCH_m32r +#define ARCH_m68k +#define ARCH_m68hc11 +#define ARCH_m68hc12 +#define ARCH_m88k +#define ARCH_mcore +#define ARCH_mips +#define ARCH_mmix +#define ARCH_mn10200 +#define ARCH_mn10300 +#define ARCH_ns32k +#define ARCH_openrisc +#define ARCH_or32 +#define ARCH_pdp11 +#define ARCH_pj +#define ARCH_powerpc +#define ARCH_rs6000 +#define ARCH_s390 +#define ARCH_sh +#define ARCH_sparc +#define ARCH_tic30 +#define ARCH_tic54x +#define ARCH_tic80 +#define ARCH_v850 +#define ARCH_vax +#define ARCH_w65 +#define ARCH_xstormy16 +#define ARCH_z8k +#define INCLUDE_SHMEDIA +#endif + + +disassembler_ftype +disassembler (abfd) + bfd *abfd; +{ + enum bfd_architecture a = bfd_get_arch (abfd); + disassembler_ftype disassemble; + + switch (a) + { + /* If you add a case to this table, also add it to the + ARCH_all definition right above this function. */ +#ifdef ARCH_a29k + case bfd_arch_a29k: + /* As far as I know we only handle big-endian 29k objects. */ + disassemble = print_insn_big_a29k; + break; +#endif +#ifdef ARCH_alpha + case bfd_arch_alpha: + disassemble = print_insn_alpha; + break; +#endif +#ifdef ARCH_arc + case bfd_arch_arc: + { + disassemble = arc_get_disassembler (abfd); + break; + } +#endif +#ifdef ARCH_arm + case bfd_arch_arm: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_arm; + else + disassemble = print_insn_little_arm; + break; +#endif +#ifdef ARCH_avr + case bfd_arch_avr: + disassemble = print_insn_avr; + break; +#endif +#ifdef ARCH_cris + case bfd_arch_cris: + disassemble = cris_get_disassembler (abfd); + break; +#endif +#ifdef ARCH_d10v + case bfd_arch_d10v: + disassemble = print_insn_d10v; + break; +#endif +#ifdef ARCH_d30v + case bfd_arch_d30v: + disassemble = print_insn_d30v; + break; +#endif +#ifdef ARCH_dlx + case bfd_arch_dlx: + /* As far as I know we only handle big-endian DLX objects. */ + disassemble = print_insn_dlx; + break; +#endif +#ifdef ARCH_h8300 + case bfd_arch_h8300: + if (bfd_get_mach(abfd) == bfd_mach_h8300h) + disassemble = print_insn_h8300h; + else if (bfd_get_mach(abfd) == bfd_mach_h8300s) + disassemble = print_insn_h8300s; + else + disassemble = print_insn_h8300; + break; +#endif +#ifdef ARCH_h8500 + case bfd_arch_h8500: + disassemble = print_insn_h8500; + break; +#endif +#ifdef ARCH_hppa + case bfd_arch_hppa: + disassemble = print_insn_hppa; + break; +#endif +#ifdef ARCH_i370 + case bfd_arch_i370: + disassemble = print_insn_i370; + break; +#endif +#ifdef ARCH_i386 + case bfd_arch_i386: + disassemble = print_insn_i386; + break; +#endif +#ifdef ARCH_i860 + case bfd_arch_i860: + disassemble = print_insn_i860; + break; +#endif +#ifdef ARCH_i960 + case bfd_arch_i960: + disassemble = print_insn_i960; + break; +#endif +#ifdef ARCH_ia64 + case bfd_arch_ia64: + disassemble = print_insn_ia64; + break; +#endif +#ifdef ARCH_fr30 + case bfd_arch_fr30: + disassemble = print_insn_fr30; + break; +#endif +#ifdef ARCH_m32r + case bfd_arch_m32r: + disassemble = print_insn_m32r; + break; +#endif +#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) + case bfd_arch_m68hc11: + disassemble = print_insn_m68hc11; + break; + case bfd_arch_m68hc12: + disassemble = print_insn_m68hc12; + break; +#endif +#ifdef ARCH_m68k + case bfd_arch_m68k: + disassemble = print_insn_m68k; + break; +#endif +#ifdef ARCH_m88k + case bfd_arch_m88k: + disassemble = print_insn_m88k; + break; +#endif +#ifdef ARCH_ns32k + case bfd_arch_ns32k: + disassemble = print_insn_ns32k; + break; +#endif +#ifdef ARCH_mcore + case bfd_arch_mcore: + disassemble = print_insn_mcore; + break; +#endif +#ifdef ARCH_mips + case bfd_arch_mips: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_mips; + else + disassemble = print_insn_little_mips; + break; +#endif +#ifdef ARCH_mmix + case bfd_arch_mmix: + disassemble = print_insn_mmix; + break; +#endif +#ifdef ARCH_mn10200 + case bfd_arch_mn10200: + disassemble = print_insn_mn10200; + break; +#endif +#ifdef ARCH_mn10300 + case bfd_arch_mn10300: + disassemble = print_insn_mn10300; + break; +#endif +#ifdef ARCH_openrisc + case bfd_arch_openrisc: + disassemble = print_insn_openrisc; + break; +#endif +#ifdef ARCH_or32 + case bfd_arch_or32: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_or32; + else + disassemble = print_insn_little_or32; + break; +#endif +#ifdef ARCH_pdp11 + case bfd_arch_pdp11: + disassemble = print_insn_pdp11; + break; +#endif +#ifdef ARCH_pj + case bfd_arch_pj: + disassemble = print_insn_pj; + break; +#endif +#ifdef ARCH_powerpc + case bfd_arch_powerpc: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_powerpc; + else + disassemble = print_insn_little_powerpc; + break; +#endif +#ifdef ARCH_rs6000 + case bfd_arch_rs6000: + if (bfd_get_mach (abfd) == bfd_mach_ppc_620) + disassemble = print_insn_big_powerpc; + else + disassemble = print_insn_rs6000; + break; +#endif +#ifdef ARCH_s390 + case bfd_arch_s390: + disassemble = print_insn_s390; + break; +#endif +#ifdef ARCH_sh + case bfd_arch_sh: + disassemble = print_insn_sh; + break; +#endif +#ifdef ARCH_sparc + case bfd_arch_sparc: + disassemble = print_insn_sparc; + break; +#endif +#ifdef ARCH_tic30 + case bfd_arch_tic30: + disassemble = print_insn_tic30; + break; +#endif +#ifdef ARCH_tic54x + case bfd_arch_tic54x: + disassemble = print_insn_tic54x; + break; +#endif +#ifdef ARCH_tic80 + case bfd_arch_tic80: + disassemble = print_insn_tic80; + break; +#endif +#ifdef ARCH_v850 + case bfd_arch_v850: + disassemble = print_insn_v850; + break; +#endif +#ifdef ARCH_w65 + case bfd_arch_w65: + disassemble = print_insn_w65; + break; +#endif +#ifdef ARCH_xstormy16 + case bfd_arch_xstormy16: + disassemble = print_insn_xstormy16; + break; +#endif +#ifdef ARCH_z8k + case bfd_arch_z8k: + if (bfd_get_mach(abfd) == bfd_mach_z8001) + disassemble = print_insn_z8001; + else + disassemble = print_insn_z8002; + break; +#endif +#ifdef ARCH_vax + case bfd_arch_vax: + disassemble = print_insn_vax; + break; +#endif + default: + return 0; + } + return disassemble; +} + +void +disassembler_usage (stream) + FILE * stream ATTRIBUTE_UNUSED; +{ +#ifdef ARCH_arm + print_arm_disassembler_options (stream); +#endif + + return; +} diff --git a/opcodes/dlx-dis.c b/opcodes/dlx-dis.c new file mode 100644 index 0000000..8878b98 --- /dev/null +++ b/opcodes/dlx-dis.c @@ -0,0 +1,544 @@ +/* Instruction printing code for the DLX Microprocessor + Copyright 2002 Free Software Foundation, Inc. + Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/dlx.h" + +#define R_ERROR 0x1 +#define R_TYPE 0x2 +#define ILD_TYPE 0x3 +#define IST_TYPE 0x4 +#define IAL_TYPE 0x5 +#define IBR_TYPE 0x6 +#define IJ_TYPE 0x7 +#define IJR_TYPE 0x8 +#define NIL 0x9 + +#define OPC(x) ((x >> 26) & 0x3F) +#define FUNC(x) (x & 0x7FF) + +unsigned char opc, rs1, rs2, rd; +unsigned long imm26, imm16, func, current_insn_addr; + +static unsigned char dlx_get_opcode PARAMS ((unsigned long)); +static unsigned char dlx_get_rs1 PARAMS ((unsigned long)); +static unsigned char dlx_get_rs2 PARAMS ((unsigned long)); +static unsigned char dlx_get_rdR PARAMS ((unsigned long)); +static unsigned long dlx_get_func PARAMS ((unsigned long)); +static unsigned long dlx_get_imm16 PARAMS ((unsigned long)); +static unsigned long dlx_get_imm26 PARAMS ((unsigned long)); +static void operand_deliminator PARAMS ((struct disassemble_info *, char *)); +static unsigned char dlx_r_type PARAMS ((struct disassemble_info *)); +static unsigned char dlx_load_type PARAMS ((struct disassemble_info *)); +static unsigned char dlx_store_type PARAMS ((struct disassemble_info *)); +static unsigned char dlx_aluI_type PARAMS ((struct disassemble_info *)); +static unsigned char dlx_br_type PARAMS ((struct disassemble_info *)); +static unsigned char dlx_jmp_type PARAMS ((struct disassemble_info *)); +static unsigned char dlx_jr_type PARAMS ((struct disassemble_info *)); + +/* Print one instruction from MEMADDR on INFO->STREAM. + Return the size of the instruction (always 4 on dlx). */ + +static unsigned char +dlx_get_opcode (opcode) + unsigned long opcode; +{ + return (unsigned char) ((opcode >> 26) & 0x3F); +} + +static unsigned char +dlx_get_rs1 (opcode) + unsigned long opcode; +{ + return (unsigned char) ((opcode >> 21) & 0x1F); +} + +static unsigned char +dlx_get_rs2 (opcode) + unsigned long opcode; +{ + return (unsigned char) ((opcode >> 16) & 0x1F); +} + +static unsigned char +dlx_get_rdR (opcode) + unsigned long opcode; +{ + return (unsigned char) ((opcode >> 11) & 0x1F); +} + +static unsigned long +dlx_get_func (opcode) + unsigned long opcode; +{ + return (unsigned char) (opcode & 0x7FF); +} + +static unsigned long +dlx_get_imm16 (opcode) + unsigned long opcode; +{ + return (unsigned long) (opcode & 0xFFFF); +} + +static unsigned long +dlx_get_imm26 (opcode) + unsigned long opcode; +{ + return (unsigned long) (opcode & 0x03FFFFFF); +} + +/* Fill the opcode to the max length. */ +static void +operand_deliminator (info, ptr) + struct disassemble_info *info; + char *ptr; +{ + int difft = 8 - (int) strlen (ptr); + + while (difft > 0) + { + (*info->fprintf_func) (info->stream, "%c", ' '); + difft -= 1; + } +} + +/* Process the R-type opcode. */ +static unsigned char +dlx_r_type (info) + struct disassemble_info *info; +{ + unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */ + int r_opc_num = (sizeof r_opc) / (sizeof (char)); + struct _r_opcode + { + unsigned long func; + char *name; + } + dlx_r_opcode[] = + { + { NOPF, "nop" }, /* NOP */ + { ADDF, "add" }, /* Add */ + { ADDUF, "addu" }, /* Add Unsigned */ + { SUBF, "sub" }, /* SUB */ + { SUBUF, "subu" }, /* Sub Unsigned */ + { MULTF, "mult" }, /* MULTIPLY */ + { MULTUF, "multu" }, /* MULTIPLY Unsigned */ + { DIVF, "div" }, /* DIVIDE */ + { DIVUF, "divu" }, /* DIVIDE Unsigned */ + { ANDF, "and" }, /* AND */ + { ORF, "or" }, /* OR */ + { XORF, "xor" }, /* Exclusive OR */ + { SLLF, "sll" }, /* SHIFT LEFT LOGICAL */ + { SRAF, "sra" }, /* SHIFT RIGHT ARITHMETIC */ + { SRLF, "srl" }, /* SHIFT RIGHT LOGICAL */ + { SEQF, "seq" }, /* Set if equal */ + { SNEF, "sne" }, /* Set if not equal */ + { SLTF, "slt" }, /* Set if less */ + { SGTF, "sgt" }, /* Set if greater */ + { SLEF, "sle" }, /* Set if less or equal */ + { SGEF, "sge" }, /* Set if greater or equal */ + { SEQUF, "sequ" }, /* Set if equal */ + { SNEUF, "sneu" }, /* Set if not equal */ + { SLTUF, "sltu" }, /* Set if less */ + { SGTUF, "sgtu" }, /* Set if greater */ + { SLEUF, "sleu" }, /* Set if less or equal */ + { SGEUF, "sgeu" }, /* Set if greater or equal */ + { MVTSF, "mvts" }, /* Move to special register */ + { MVFSF, "mvfs" }, /* Move from special register */ + { BSWAPF, "bswap" }, /* Byte swap ?? */ + { LUTF, "lut" } /* ????????? ?? */ + }; + int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]); + int idx; + + for (idx = 0; idx < r_opc_num; idx++) + { + if (r_opc[idx] != opc) + continue; + else + break; + } + + if (idx == r_opc_num) + return NIL; + + for (idx = 0 ; idx < dlx_r_opcode_num; idx++) + if (dlx_r_opcode[idx].func == func) + { + (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name); + + if (func != NOPF) + { + /* This is not a nop. */ + operand_deliminator (info, dlx_r_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rd); + (*info->fprintf_func) (info->stream, "r%d", (int)rs1); + if (func != MVTSF && func != MVFSF) + (*info->fprintf_func) (info->stream, ",r%d", (int)rs2); + } + return (unsigned char) R_TYPE; + } + + return (unsigned char) R_ERROR; +} + +/* Process the memory read opcode. */ + +static unsigned char +dlx_load_type (info) + struct disassemble_info* info; +{ + struct _load_opcode + { + unsigned long opcode; + char *name; + } + dlx_load_opcode[] = + { + { OPC(LHIOP), "lhi" }, /* Load HI to register. */ + { OPC(LBOP), "lb" }, /* load byte sign extended. */ + { OPC(LBUOP), "lbu" }, /* load byte unsigned. */ + { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */ + { OPC(LHOP), "lh" }, /* load halfword sign extended. */ + { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */ + { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */ + { OPC(LWOP), "lw" }, /* load word. */ + { OPC(LSWOP), "ldstw" } /* load store word. */ + }; + int dlx_load_opcode_num = + (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_load_opcode_num; idx++) + if (dlx_load_opcode[idx].opcode == opc) + { + if (opc == OPC (LHIOP)) + { + (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name); + operand_deliminator (info, dlx_load_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); + (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16); + } + else + { + (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name); + operand_deliminator (info, dlx_load_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); + (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1); + } + + return (unsigned char) ILD_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the memory store opcode. */ + +static unsigned char +dlx_store_type (info) + struct disassemble_info* info; +{ + struct _store_opcode + { + unsigned long opcode; + char *name; + } + dlx_store_opcode[] = + { + { OPC(SBOP), "sb" }, /* Store byte. */ + { OPC(SHOP), "sh" }, /* Store halfword. */ + { OPC(SWOP), "sw" }, /* Store word. */ + }; + int dlx_store_opcode_num = + (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_store_opcode_num; idx++) + if (dlx_store_opcode[idx].opcode == opc) + { + (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name); + operand_deliminator (info, dlx_store_opcode[idx].name); + (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1); + (*info->fprintf_func) (info->stream, "r%d", (int)rs2); + return (unsigned char) IST_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the Arithmetic and Logical I-TYPE opcode. */ + +static unsigned char +dlx_aluI_type (info) + struct disassemble_info* info; +{ + struct _aluI_opcode + { + unsigned long opcode; + char *name; + } + dlx_aluI_opcode[] = + { + { OPC(ADDIOP), "addi" }, /* Store byte. */ + { OPC(ADDUIOP), "addui" }, /* Store halfword. */ + { OPC(SUBIOP), "subi" }, /* Store word. */ + { OPC(SUBUIOP), "subui" }, /* Store word. */ + { OPC(ANDIOP), "andi" }, /* Store word. */ + { OPC(ORIOP), "ori" }, /* Store word. */ + { OPC(XORIOP), "xori" }, /* Store word. */ + { OPC(SLLIOP), "slli" }, /* Store word. */ + { OPC(SRAIOP), "srai" }, /* Store word. */ + { OPC(SRLIOP), "srli" }, /* Store word. */ + { OPC(SEQIOP), "seqi" }, /* Store word. */ + { OPC(SNEIOP), "snei" }, /* Store word. */ + { OPC(SLTIOP), "slti" }, /* Store word. */ + { OPC(SGTIOP), "sgti" }, /* Store word. */ + { OPC(SLEIOP), "slei" }, /* Store word. */ + { OPC(SGEIOP), "sgei" }, /* Store word. */ + { OPC(SEQUIOP), "sequi" }, /* Store word. */ + { OPC(SNEUIOP), "sneui" }, /* Store word. */ + { OPC(SLTUIOP), "sltui" }, /* Store word. */ + { OPC(SGTUIOP), "sgtui" }, /* Store word. */ + { OPC(SLEUIOP), "sleui" }, /* Store word. */ + { OPC(SGEUIOP), "sgeui" }, /* Store word. */ +#if 0 + { OPC(MVTSOP), "mvts" }, /* Store word. */ + { OPC(MVFSOP), "mvfs" }, /* Store word. */ +#endif + }; + int dlx_aluI_opcode_num = + (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++) + if (dlx_aluI_opcode[idx].opcode == opc) + { + (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name); + operand_deliminator (info, dlx_aluI_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs1); + (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16); + + return (unsigned char) IAL_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the branch instruction. */ + +static unsigned char +dlx_br_type (info) + struct disassemble_info* info; +{ + struct _br_opcode + { + unsigned long opcode; + char *name; + } + dlx_br_opcode[] = + { + { OPC(BEQOP), "beqz" }, /* Store byte. */ + { OPC(BNEOP), "bnez" } /* Store halfword. */ + }; + int dlx_br_opcode_num = + (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_br_opcode_num; idx++) + if (dlx_br_opcode[idx].opcode == opc) + { + if (imm16 & 0x00008000) + imm16 |= 0xFFFF0000; + + imm16 += (current_insn_addr + 4); + (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name); + operand_deliminator (info, dlx_br_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs1); + (*info->fprintf_func) (info->stream, "0x%08x", (int)imm16); + + return (unsigned char) IBR_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the jump instruction. */ + +static unsigned char +dlx_jmp_type (info) + struct disassemble_info* info; +{ + struct _jmp_opcode + { + unsigned long opcode; + char *name; + } + dlx_jmp_opcode[] = + { + { OPC(JOP), "j" }, /* Store byte. */ + { OPC(JALOP), "jal" }, /* Store halfword. */ + { OPC(BREAKOP), "break" }, /* Store halfword. */ + { OPC(TRAPOP), "trap" }, /* Store halfword. */ + { OPC(RFEOP), "rfe" } /* Store halfword. */ + }; + int dlx_jmp_opcode_num = + (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++) + if (dlx_jmp_opcode[idx].opcode == opc) + { + if (imm26 & 0x02000000) + imm26 |= 0xFC000000; + + imm26 += (current_insn_addr + 4); + + (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name); + operand_deliminator (info, dlx_jmp_opcode[idx].name); + (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26); + + return (unsigned char) IJ_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the jump register instruction. */ + +static unsigned char +dlx_jr_type (info) + struct disassemble_info* info; +{ + struct _jr_opcode + { + unsigned long opcode; + char *name; + } + dlx_jr_opcode[] = { + { OPC(JROP), "jr" }, /* Store byte. */ + { OPC(JALROP), "jalr" } /* Store halfword. */ + }; + int dlx_jr_opcode_num = + (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_jr_opcode_num; idx++) + if (dlx_jr_opcode[idx].opcode == opc) + { + (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name); + operand_deliminator (info, dlx_jr_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d", (int)rs1); + return (unsigned char) IJR_TYPE; + } + + return (unsigned char) NIL; +} + +typedef unsigned char (* dlx_insn) PARAMS ((struct disassemble_info *)); + +/* This is the main DLX insn handling routine. */ + +int +print_insn_dlx (memaddr, info) + bfd_vma memaddr; + struct disassemble_info* info; +{ + bfd_byte buffer[4]; + int insn_idx; + unsigned long insn_word; + unsigned char rtn_code; + unsigned long dlx_insn_type[] = + { + (unsigned long) dlx_r_type, + (unsigned long) dlx_load_type, + (unsigned long) dlx_store_type, + (unsigned long) dlx_aluI_type, + (unsigned long) dlx_br_type, + (unsigned long) dlx_jmp_type, + (unsigned long) dlx_jr_type, + (unsigned long) NULL + }; + int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1; + int status = + (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info); + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Now decode the insn */ + insn_word = bfd_getb32 (buffer); + opc = dlx_get_opcode (insn_word); + rs1 = dlx_get_rs1 (insn_word); + rs2 = dlx_get_rs2 (insn_word); + rd = dlx_get_rdR (insn_word); + func = dlx_get_func (insn_word); + imm16= dlx_get_imm16 (insn_word); + imm26= dlx_get_imm26 (insn_word); + +#if 0 + printf ("print_insn_big_dlx: opc = 0x%02x\n" + " rs1 = 0x%02x\n" + " rs2 = 0x%02x\n" + " rd = 0x%02x\n" + " func = 0x%08x\n" + " imm16 = 0x%08x\n" + " imm26 = 0x%08x\n", + opc, rs1, rs2, rd, func, imm16, imm26); +#endif + + /* Scan through all the insn type and print the insn out. */ + rtn_code = 0; + current_insn_addr = (unsigned long) memaddr; + + for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++) + switch (((dlx_insn) (dlx_insn_type[insn_idx])) (info)) + { + /* Found the correct opcode */ + case R_TYPE: + case ILD_TYPE: + case IST_TYPE: + case IAL_TYPE: + case IBR_TYPE: + case IJ_TYPE: + case IJR_TYPE: + return 4; + + /* Wrong insn type check next one. */ + default: + case NIL: + continue; + + /* All rest of the return code are not recongnized, treat it as error */ + /* we should never get here, I hope! */ + case R_ERROR: + return -1; + } + + if (insn_idx == dlx_insn_type_num) + /* Well, does not recoganize this opcode. */ + (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode"); + + return 4; +} diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c new file mode 100644 index 0000000..be9c36c --- /dev/null +++ b/opcodes/fr30-asm.c @@ -0,0 +1,751 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +/* Handle register lists for LDMx and STMx. */ + +static int parse_register_number + PARAMS ((const char **)); +static const char * parse_register_list + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int)); +static const char * parse_low_register_list_ld + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi_register_list_ld + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_low_register_list_st + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi_register_list_st + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); + +static int +parse_register_number (strp) + const char **strp; +{ + int regno; + if (**strp < '0' || **strp > '9') + return -1; /* error. */ + regno = **strp - '0'; + ++*strp; + + if (**strp >= '0' && **strp <= '9') + { + regno = regno * 10 + (**strp - '0'); + ++*strp; + } + + return regno; +} + +static const char * +parse_register_list (cd, strp, opindex, valuep, high_low, load_store) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + const char **strp; + int opindex ATTRIBUTE_UNUSED; + unsigned long *valuep; + int high_low; /* 0 == high, 1 == low */ + int load_store; /* 0 == load, 1 == store */ +{ + int regno; + + *valuep = 0; + while (**strp && **strp != ')') + { + if (**strp != 'R' && **strp != 'r') + break; + ++*strp; + + regno = parse_register_number (strp); + if (regno == -1) + return "Register number is not valid"; + if (regno > 7 && !high_low) + return "Register must be between r0 and r7"; + if (regno < 8 && high_low) + return "Register must be between r8 and r15"; + + if (high_low) + regno -= 8; + + if (load_store) /* Mask is reversed for store. */ + *valuep |= 0x80 >> regno; + else + *valuep |= 1 << regno; + + if (**strp == ',') + { + if (*(*strp + 1) == ')') + break; + ++*strp; + } + } + + if (!*strp || **strp != ')') + return "Register list is not valid"; + + return NULL; +} + +static const char * +parse_low_register_list_ld (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 0/*load*/); +} + +static const char * +parse_hi_register_list_ld (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 0/*load*/); +} + +static const char * +parse_low_register_list_st (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 1/*store*/); +} + +static const char * +parse_hi_register_list_st (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 1/*store*/); +} + +/* -- */ + +const char * fr30_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +fr30_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case FR30_OPERAND_CRI : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRi); + break; + case FR30_OPERAND_CRJ : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRj); + break; + case FR30_OPERAND_R13 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r13, & junk); + break; + case FR30_OPERAND_R14 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r14, & junk); + break; + case FR30_OPERAND_R15 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r15, & junk); + break; + case FR30_OPERAND_RI : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ri); + break; + case FR30_OPERAND_RIC : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ric); + break; + case FR30_OPERAND_RJ : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Rj); + break; + case FR30_OPERAND_RJC : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Rjc); + break; + case FR30_OPERAND_RS1 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_dr_names, & fields->f_Rs1); + break; + case FR30_OPERAND_RS2 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_dr_names, & fields->f_Rs2); + break; + case FR30_OPERAND_CC : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_CC, &fields->f_cc); + break; + case FR30_OPERAND_CCC : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_CCC, &fields->f_ccc); + break; + case FR30_OPERAND_DIR10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR10, &fields->f_dir10); + break; + case FR30_OPERAND_DIR8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR8, &fields->f_dir8); + break; + case FR30_OPERAND_DIR9 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR9, &fields->f_dir9); + break; + case FR30_OPERAND_DISP10 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP10, &fields->f_disp10); + break; + case FR30_OPERAND_DISP8 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP8, &fields->f_disp8); + break; + case FR30_OPERAND_DISP9 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP9, &fields->f_disp9); + break; + case FR30_OPERAND_I20 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I20, &fields->f_i20); + break; + case FR30_OPERAND_I32 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I32, &fields->f_i32); + break; + case FR30_OPERAND_I8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I8, &fields->f_i8); + break; + case FR30_OPERAND_LABEL12 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL12, 0, NULL, & value); + fields->f_rel12 = value; + } + break; + case FR30_OPERAND_LABEL9 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL9, 0, NULL, & value); + fields->f_rel9 = value; + } + break; + case FR30_OPERAND_M4 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_M4, &fields->f_m4); + break; + case FR30_OPERAND_PS : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_ps, & junk); + break; + case FR30_OPERAND_REGLIST_HI_LD : + errmsg = parse_hi_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_HI_LD, &fields->f_reglist_hi_ld); + break; + case FR30_OPERAND_REGLIST_HI_ST : + errmsg = parse_hi_register_list_st (cd, strp, FR30_OPERAND_REGLIST_HI_ST, &fields->f_reglist_hi_st); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + errmsg = parse_low_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_LOW_LD, &fields->f_reglist_low_ld); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + errmsg = parse_low_register_list_st (cd, strp, FR30_OPERAND_REGLIST_LOW_ST, &fields->f_reglist_low_st); + break; + case FR30_OPERAND_S10 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_S10, &fields->f_s10); + break; + case FR30_OPERAND_U10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U10, &fields->f_u10); + break; + case FR30_OPERAND_U4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U4, &fields->f_u4); + break; + case FR30_OPERAND_U4C : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U4C, &fields->f_u4c); + break; + case FR30_OPERAND_U8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U8, &fields->f_u8); + break; + case FR30_OPERAND_UDISP6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_UDISP6, &fields->f_udisp6); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const fr30_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +fr30_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + fr30_cgen_init_opcode_table (cd); + fr30_cgen_init_ibld_table (cd); + cd->parse_handlers = & fr30_cgen_parse_handlers[0]; + cd->parse_operand = fr30_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by fr30_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +fr30_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! fr30_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +fr30_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! fr30_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c new file mode 100644 index 0000000..18963b9 --- /dev/null +++ b/opcodes/fr30-desc.c @@ -0,0 +1,1789 @@ +/* CPU data for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "fr30", MACH_FR30 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "fr30", ISA_FR30 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA fr30_cgen_isa_table[] = { + { "fr30", 16, 16, 16, 48 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH fr30_cgen_mach_table[] = { + { "fr30", "fr30", MACH_FR30, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 }, + { "ac", 13, {0, {0}}, 0, 0 }, + { "fp", 14, {0, {0}}, 0, 0 }, + { "sp", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_gr_names = +{ + & fr30_cgen_opval_gr_names_entries[0], + 19, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] = +{ + { "cr0", 0, {0, {0}}, 0, 0 }, + { "cr1", 1, {0, {0}}, 0, 0 }, + { "cr2", 2, {0, {0}}, 0, 0 }, + { "cr3", 3, {0, {0}}, 0, 0 }, + { "cr4", 4, {0, {0}}, 0, 0 }, + { "cr5", 5, {0, {0}}, 0, 0 }, + { "cr6", 6, {0, {0}}, 0, 0 }, + { "cr7", 7, {0, {0}}, 0, 0 }, + { "cr8", 8, {0, {0}}, 0, 0 }, + { "cr9", 9, {0, {0}}, 0, 0 }, + { "cr10", 10, {0, {0}}, 0, 0 }, + { "cr11", 11, {0, {0}}, 0, 0 }, + { "cr12", 12, {0, {0}}, 0, 0 }, + { "cr13", 13, {0, {0}}, 0, 0 }, + { "cr14", 14, {0, {0}}, 0, 0 }, + { "cr15", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_cr_names = +{ + & fr30_cgen_opval_cr_names_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] = +{ + { "tbr", 0, {0, {0}}, 0, 0 }, + { "rp", 1, {0, {0}}, 0, 0 }, + { "ssp", 2, {0, {0}}, 0, 0 }, + { "usp", 3, {0, {0}}, 0, 0 }, + { "mdh", 4, {0, {0}}, 0, 0 }, + { "mdl", 5, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_dr_names = +{ + & fr30_cgen_opval_dr_names_entries[0], + 6, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = +{ + { "ps", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_ps = +{ + & fr30_cgen_opval_h_ps_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = +{ + { "r13", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_r13 = +{ + & fr30_cgen_opval_h_r13_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = +{ + { "r14", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_r14 = +{ + & fr30_cgen_opval_h_r14_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = +{ + { "r15", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_r15 = +{ + & fr30_cgen_opval_h_r15_entries[0], + 1, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY fr30_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & fr30_cgen_ifld_table[0]; +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & fr30_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & fr30_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */ + +static void +fr30_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & fr30_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (fr30_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = fr30_cgen_rebuild_tables; + fr30_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +fr30_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +fr30_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h new file mode 100644 index 0000000..41de0bb --- /dev/null +++ b/opcodes/fr30-desc.h @@ -0,0 +1,273 @@ +/* CPU data header for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FR30_CPU_H +#define FR30_CPU_H + +#define CGEN_ARCH fr30 + +/* Given symbol S, return fr30_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) fr30##_cgen_##s +#else +#define CGEN_SYM(s) fr30/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_FR30BF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 6 + +#define CGEN_INT_INSN_P 0 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 + +/* Enums. */ + +/* Enum declaration for insn op1 enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_A, OP1_B + , OP1_C, OP1_D, OP1_E, OP1_F +} INSN_OP1; + +/* Enum declaration for insn op2 enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_A, OP2_B + , OP2_C, OP2_D, OP2_E, OP2_F +} INSN_OP2; + +/* Enum declaration for insn op3 enums. */ +typedef enum insn_op3 { + OP3_0, OP3_1, OP3_2, OP3_3 + , OP3_4, OP3_5, OP3_6, OP3_7 + , OP3_8, OP3_9, OP3_A, OP3_B + , OP3_C, OP3_D, OP3_E, OP3_F +} INSN_OP3; + +/* Enum declaration for insn op4 enums. */ +typedef enum insn_op4 { + OP4_0 +} INSN_OP4; + +/* Enum declaration for insn op5 enums. */ +typedef enum insn_op5 { + OP5_0, OP5_1 +} INSN_OP5; + +/* Enum declaration for insn cc enums. */ +typedef enum insn_cc { + CC_RA, CC_NO, CC_EQ, CC_NE + , CC_C, CC_NC, CC_N, CC_P + , CC_V, CC_NV, CC_LT, CC_GE + , CC_LE, CC_GT, CC_LS, CC_HI +} INSN_CC; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 + , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 + , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 + , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 + , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum cr_names { + H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 + , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 + , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 + , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 +} CR_NAMES; + +/* Enum declaration for . */ +typedef enum dr_names { + H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP + , H_DR_MDH, H_DR_MDL +} DR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_FR30, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_FR30, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld fr30_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for fr30 ifield types. */ +typedef enum ifield_type { + FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 + , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC + , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1 + , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ + , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4 + , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4 + , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6 + , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10 + , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9 + , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST + , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) FR30_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for fr30 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR + , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 + , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT + , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT + , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR + , HW_H_ILM, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for fr30 operand types. */ +typedef enum cgen_operand_type { + FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC + , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 + , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 + , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8 + , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 + , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 + , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9 + , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD + , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC + , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT + , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT + , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR + , FR30_OPERAND_ILM, FR30_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 49 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD fr30_cgen_opval_gr_names; +extern CGEN_KEYWORD fr30_cgen_opval_cr_names; +extern CGEN_KEYWORD fr30_cgen_opval_dr_names; +extern CGEN_KEYWORD fr30_cgen_opval_h_ps; +extern CGEN_KEYWORD fr30_cgen_opval_h_r13; +extern CGEN_KEYWORD fr30_cgen_opval_h_r14; +extern CGEN_KEYWORD fr30_cgen_opval_h_r15; + + + + +#endif /* FR30_CPU_H */ diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c new file mode 100644 index 0000000..7affa86 --- /dev/null +++ b/opcodes/fr30-dis.c @@ -0,0 +1,747 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + +/* -- dis.c */ +static void print_register_list + PARAMS ((PTR, long, long, int)); +static void print_hi_register_list_ld + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_low_register_list_ld + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_hi_register_list_st + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_low_register_list_st + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_m4 + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); + +static void +print_register_list (dis_info, value, offset, load_store) + PTR dis_info; + long value; + long offset; + int load_store; /* 0 == load, 1 == store */ +{ + disassemble_info *info = dis_info; + int mask; + int index = 0; + char* comma = ""; + + if (load_store) + mask = 0x80; + else + mask = 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "r%i", index + offset); + comma = ","; + } + + for (index = 1; index <= 7; ++index) + { + if (load_store) + mask >>= 1; + else + mask <<= 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset); + comma = ","; + } + } +} + +static void +print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + print_register_list (dis_info, value, 8, 0/*load*/); +} + +static void +print_low_register_list_ld (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + print_register_list (dis_info, value, 0, 0/*load*/); +} + +static void +print_hi_register_list_st (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + print_register_list (dis_info, value, 8, 1/*store*/); +} + +static void +print_low_register_list_st (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + print_register_list (dis_info, value, 0, 1/*store*/); +} + +static void +print_m4 (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "%ld", value); +} +/* -- */ + +void fr30_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case FR30_OPERAND_CRI : + print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0); + break; + case FR30_OPERAND_CRJ : + print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0); + break; + case FR30_OPERAND_R13 : + print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0); + break; + case FR30_OPERAND_R14 : + print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0); + break; + case FR30_OPERAND_R15 : + print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0); + break; + case FR30_OPERAND_RI : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0); + break; + case FR30_OPERAND_RIC : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0); + break; + case FR30_OPERAND_RJ : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0); + break; + case FR30_OPERAND_RJC : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0); + break; + case FR30_OPERAND_RS1 : + print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0); + break; + case FR30_OPERAND_RS2 : + print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0); + break; + case FR30_OPERAND_CC : + print_normal (cd, info, fields->f_cc, 0, pc, length); + break; + case FR30_OPERAND_CCC : + print_normal (cd, info, fields->f_ccc, 0|(1<f_dir10, 0, pc, length); + break; + case FR30_OPERAND_DIR8 : + print_normal (cd, info, fields->f_dir8, 0, pc, length); + break; + case FR30_OPERAND_DIR9 : + print_normal (cd, info, fields->f_dir9, 0, pc, length); + break; + case FR30_OPERAND_DISP10 : + print_normal (cd, info, fields->f_disp10, 0|(1<f_disp8, 0|(1<f_disp9, 0|(1<f_i20, 0|(1<f_i32, 0|(1<f_i8, 0|(1<f_rel12, 0|(1<f_rel9, 0|(1<f_m4, 0|(1<f_reglist_hi_ld, 0, pc, length); + break; + case FR30_OPERAND_REGLIST_HI_ST : + print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length); + break; + case FR30_OPERAND_S10 : + print_normal (cd, info, fields->f_s10, 0|(1<f_u10, 0|(1<f_u4, 0|(1<f_u4c, 0|(1<f_u8, 0|(1<f_udisp6, 0|(1<print_handlers = & fr30_cgen_print_handlers[0]; + cd->print_operand = fr30_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! fr30_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_fr30 (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_fr30 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + fr30_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c new file mode 100644 index 0000000..9637461 --- /dev/null +++ b/opcodes/fr30-ibld.c @@ -0,0 +1,1493 @@ +/* Instruction building/extraction support for fr30. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * fr30_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FR30_OPERAND_CRI : + errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_CRJ : + errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RIC : + errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RJ : + errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RJC : + errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RS1 : + errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RS2 : + errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_CC : + errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_CCC : + errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_DIR10 : + { + long value = fields->f_dir10; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); + } + break; + case FR30_OPERAND_DIR8 : + errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_DIR9 : + { + long value = fields->f_dir9; + value = ((unsigned int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); + } + break; + case FR30_OPERAND_DISP10 : + { + long value = fields->f_disp10; + value = ((int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp8, 0|(1<f_disp9; + value = ((int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<> (16)); + FLD (f_i20_16) = ((FLD (f_i20)) & (65535)); +} + errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer); + if (errmsg) + break; + } + break; + case FR30_OPERAND_I32 : + errmsg = insert_normal (cd, fields->f_i32, 0|(1<f_i8, 0, 0, 4, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_LABEL12 : + { + long value = fields->f_rel12; + value = ((int) (((value) - (((pc) + (2))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_rel9; + value = ((int) (((value) - (((pc) + (2))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_m4; + value = ((value) & (15)); + errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer); + } + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_REGLIST_HI_ST : + errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_S10 : + { + long value = fields->f_s10; + value = ((int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_u10; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); + } + break; + case FR30_OPERAND_U4 : + errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_U4C : + errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_U8 : + errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_UDISP6 : + { + long value = fields->f_udisp6; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer); + } + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int fr30_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FR30_OPERAND_CRI : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi); + break; + case FR30_OPERAND_CRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj); + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri); + break; + case FR30_OPERAND_RIC : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric); + break; + case FR30_OPERAND_RJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj); + break; + case FR30_OPERAND_RJC : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc); + break; + case FR30_OPERAND_RS1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1); + break; + case FR30_OPERAND_RS2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2); + break; + case FR30_OPERAND_CC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc); + break; + case FR30_OPERAND_CCC : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc); + break; + case FR30_OPERAND_DIR10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); + value = ((value) << (2)); + fields->f_dir10 = value; + } + break; + case FR30_OPERAND_DIR8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8); + break; + case FR30_OPERAND_DIR9 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); + value = ((value) << (1)); + fields->f_dir9 = value; + } + break; + case FR30_OPERAND_DISP10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp10 = value; + } + break; + case FR30_OPERAND_DISP8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp8); + break; + case FR30_OPERAND_DISP9 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp9 = value; + } + break; + case FR30_OPERAND_I20 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16); + if (length <= 0) break; +{ + FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16))); +} + } + break; + case FR30_OPERAND_I32 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_i32); + break; + case FR30_OPERAND_I8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8); + break; + case FR30_OPERAND_LABEL12 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel12 = value; + } + break; + case FR30_OPERAND_LABEL9 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel9 = value; + } + break; + case FR30_OPERAND_M4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value); + value = ((value) | (((-1) << (4)))); + fields->f_m4 = value; + } + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld); + break; + case FR30_OPERAND_REGLIST_HI_ST : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st); + break; + case FR30_OPERAND_S10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s10 = value; + } + break; + case FR30_OPERAND_U10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); + value = ((value) << (2)); + fields->f_u10 = value; + } + break; + case FR30_OPERAND_U4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4); + break; + case FR30_OPERAND_U4C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c); + break; + case FR30_OPERAND_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8); + break; + case FR30_OPERAND_UDISP6 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value); + value = ((value) << (2)); + fields->f_udisp6 = value; + } + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const fr30_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const fr30_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int fr30_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma fr30_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +fr30_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case FR30_OPERAND_CRI : + value = fields->f_CRi; + break; + case FR30_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FR30_OPERAND_R13 : + value = 0; + break; + case FR30_OPERAND_R14 : + value = 0; + break; + case FR30_OPERAND_R15 : + value = 0; + break; + case FR30_OPERAND_RI : + value = fields->f_Ri; + break; + case FR30_OPERAND_RIC : + value = fields->f_Ric; + break; + case FR30_OPERAND_RJ : + value = fields->f_Rj; + break; + case FR30_OPERAND_RJC : + value = fields->f_Rjc; + break; + case FR30_OPERAND_RS1 : + value = fields->f_Rs1; + break; + case FR30_OPERAND_RS2 : + value = fields->f_Rs2; + break; + case FR30_OPERAND_CC : + value = fields->f_cc; + break; + case FR30_OPERAND_CCC : + value = fields->f_ccc; + break; + case FR30_OPERAND_DIR10 : + value = fields->f_dir10; + break; + case FR30_OPERAND_DIR8 : + value = fields->f_dir8; + break; + case FR30_OPERAND_DIR9 : + value = fields->f_dir9; + break; + case FR30_OPERAND_DISP10 : + value = fields->f_disp10; + break; + case FR30_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case FR30_OPERAND_DISP9 : + value = fields->f_disp9; + break; + case FR30_OPERAND_I20 : + value = fields->f_i20; + break; + case FR30_OPERAND_I32 : + value = fields->f_i32; + break; + case FR30_OPERAND_I8 : + value = fields->f_i8; + break; + case FR30_OPERAND_LABEL12 : + value = fields->f_rel12; + break; + case FR30_OPERAND_LABEL9 : + value = fields->f_rel9; + break; + case FR30_OPERAND_M4 : + value = fields->f_m4; + break; + case FR30_OPERAND_PS : + value = 0; + break; + case FR30_OPERAND_REGLIST_HI_LD : + value = fields->f_reglist_hi_ld; + break; + case FR30_OPERAND_REGLIST_HI_ST : + value = fields->f_reglist_hi_st; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + value = fields->f_reglist_low_ld; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + value = fields->f_reglist_low_st; + break; + case FR30_OPERAND_S10 : + value = fields->f_s10; + break; + case FR30_OPERAND_U10 : + value = fields->f_u10; + break; + case FR30_OPERAND_U4 : + value = fields->f_u4; + break; + case FR30_OPERAND_U4C : + value = fields->f_u4c; + break; + case FR30_OPERAND_U8 : + value = fields->f_u8; + break; + case FR30_OPERAND_UDISP6 : + value = fields->f_udisp6; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +fr30_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case FR30_OPERAND_CRI : + value = fields->f_CRi; + break; + case FR30_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FR30_OPERAND_R13 : + value = 0; + break; + case FR30_OPERAND_R14 : + value = 0; + break; + case FR30_OPERAND_R15 : + value = 0; + break; + case FR30_OPERAND_RI : + value = fields->f_Ri; + break; + case FR30_OPERAND_RIC : + value = fields->f_Ric; + break; + case FR30_OPERAND_RJ : + value = fields->f_Rj; + break; + case FR30_OPERAND_RJC : + value = fields->f_Rjc; + break; + case FR30_OPERAND_RS1 : + value = fields->f_Rs1; + break; + case FR30_OPERAND_RS2 : + value = fields->f_Rs2; + break; + case FR30_OPERAND_CC : + value = fields->f_cc; + break; + case FR30_OPERAND_CCC : + value = fields->f_ccc; + break; + case FR30_OPERAND_DIR10 : + value = fields->f_dir10; + break; + case FR30_OPERAND_DIR8 : + value = fields->f_dir8; + break; + case FR30_OPERAND_DIR9 : + value = fields->f_dir9; + break; + case FR30_OPERAND_DISP10 : + value = fields->f_disp10; + break; + case FR30_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case FR30_OPERAND_DISP9 : + value = fields->f_disp9; + break; + case FR30_OPERAND_I20 : + value = fields->f_i20; + break; + case FR30_OPERAND_I32 : + value = fields->f_i32; + break; + case FR30_OPERAND_I8 : + value = fields->f_i8; + break; + case FR30_OPERAND_LABEL12 : + value = fields->f_rel12; + break; + case FR30_OPERAND_LABEL9 : + value = fields->f_rel9; + break; + case FR30_OPERAND_M4 : + value = fields->f_m4; + break; + case FR30_OPERAND_PS : + value = 0; + break; + case FR30_OPERAND_REGLIST_HI_LD : + value = fields->f_reglist_hi_ld; + break; + case FR30_OPERAND_REGLIST_HI_ST : + value = fields->f_reglist_hi_st; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + value = fields->f_reglist_low_ld; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + value = fields->f_reglist_low_st; + break; + case FR30_OPERAND_S10 : + value = fields->f_s10; + break; + case FR30_OPERAND_U10 : + value = fields->f_u10; + break; + case FR30_OPERAND_U4 : + value = fields->f_u4; + break; + case FR30_OPERAND_U4C : + value = fields->f_u4c; + break; + case FR30_OPERAND_U8 : + value = fields->f_u8; + break; + case FR30_OPERAND_UDISP6 : + value = fields->f_udisp6; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void fr30_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void fr30_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +fr30_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case FR30_OPERAND_CRI : + fields->f_CRi = value; + break; + case FR30_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + fields->f_Ri = value; + break; + case FR30_OPERAND_RIC : + fields->f_Ric = value; + break; + case FR30_OPERAND_RJ : + fields->f_Rj = value; + break; + case FR30_OPERAND_RJC : + fields->f_Rjc = value; + break; + case FR30_OPERAND_RS1 : + fields->f_Rs1 = value; + break; + case FR30_OPERAND_RS2 : + fields->f_Rs2 = value; + break; + case FR30_OPERAND_CC : + fields->f_cc = value; + break; + case FR30_OPERAND_CCC : + fields->f_ccc = value; + break; + case FR30_OPERAND_DIR10 : + fields->f_dir10 = value; + break; + case FR30_OPERAND_DIR8 : + fields->f_dir8 = value; + break; + case FR30_OPERAND_DIR9 : + fields->f_dir9 = value; + break; + case FR30_OPERAND_DISP10 : + fields->f_disp10 = value; + break; + case FR30_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case FR30_OPERAND_DISP9 : + fields->f_disp9 = value; + break; + case FR30_OPERAND_I20 : + fields->f_i20 = value; + break; + case FR30_OPERAND_I32 : + fields->f_i32 = value; + break; + case FR30_OPERAND_I8 : + fields->f_i8 = value; + break; + case FR30_OPERAND_LABEL12 : + fields->f_rel12 = value; + break; + case FR30_OPERAND_LABEL9 : + fields->f_rel9 = value; + break; + case FR30_OPERAND_M4 : + fields->f_m4 = value; + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + fields->f_reglist_hi_ld = value; + break; + case FR30_OPERAND_REGLIST_HI_ST : + fields->f_reglist_hi_st = value; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + fields->f_reglist_low_ld = value; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + fields->f_reglist_low_st = value; + break; + case FR30_OPERAND_S10 : + fields->f_s10 = value; + break; + case FR30_OPERAND_U10 : + fields->f_u10 = value; + break; + case FR30_OPERAND_U4 : + fields->f_u4 = value; + break; + case FR30_OPERAND_U4C : + fields->f_u4c = value; + break; + case FR30_OPERAND_U8 : + fields->f_u8 = value; + break; + case FR30_OPERAND_UDISP6 : + fields->f_udisp6 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +fr30_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case FR30_OPERAND_CRI : + fields->f_CRi = value; + break; + case FR30_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + fields->f_Ri = value; + break; + case FR30_OPERAND_RIC : + fields->f_Ric = value; + break; + case FR30_OPERAND_RJ : + fields->f_Rj = value; + break; + case FR30_OPERAND_RJC : + fields->f_Rjc = value; + break; + case FR30_OPERAND_RS1 : + fields->f_Rs1 = value; + break; + case FR30_OPERAND_RS2 : + fields->f_Rs2 = value; + break; + case FR30_OPERAND_CC : + fields->f_cc = value; + break; + case FR30_OPERAND_CCC : + fields->f_ccc = value; + break; + case FR30_OPERAND_DIR10 : + fields->f_dir10 = value; + break; + case FR30_OPERAND_DIR8 : + fields->f_dir8 = value; + break; + case FR30_OPERAND_DIR9 : + fields->f_dir9 = value; + break; + case FR30_OPERAND_DISP10 : + fields->f_disp10 = value; + break; + case FR30_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case FR30_OPERAND_DISP9 : + fields->f_disp9 = value; + break; + case FR30_OPERAND_I20 : + fields->f_i20 = value; + break; + case FR30_OPERAND_I32 : + fields->f_i32 = value; + break; + case FR30_OPERAND_I8 : + fields->f_i8 = value; + break; + case FR30_OPERAND_LABEL12 : + fields->f_rel12 = value; + break; + case FR30_OPERAND_LABEL9 : + fields->f_rel9 = value; + break; + case FR30_OPERAND_M4 : + fields->f_m4 = value; + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + fields->f_reglist_hi_ld = value; + break; + case FR30_OPERAND_REGLIST_HI_ST : + fields->f_reglist_hi_st = value; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + fields->f_reglist_low_ld = value; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + fields->f_reglist_low_st = value; + break; + case FR30_OPERAND_S10 : + fields->f_s10 = value; + break; + case FR30_OPERAND_U10 : + fields->f_u10 = value; + break; + case FR30_OPERAND_U4 : + fields->f_u4 = value; + break; + case FR30_OPERAND_U4C : + fields->f_u4c = value; + break; + case FR30_OPERAND_U8 : + fields->f_u8 = value; + break; + case FR30_OPERAND_UDISP6 : + fields->f_udisp6 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +fr30_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & fr30_cgen_insert_handlers[0]; + cd->extract_handlers = & fr30_cgen_extract_handlers[0]; + + cd->insert_operand = fr30_cgen_insert_operand; + cd->extract_operand = fr30_cgen_extract_operand; + + cd->get_int_operand = fr30_cgen_get_int_operand; + cd->set_int_operand = fr30_cgen_set_int_operand; + cd->get_vma_operand = fr30_cgen_get_vma_operand; + cd->set_vma_operand = fr30_cgen_set_vma_operand; +} diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c new file mode 100644 index 0000000..b47cbcd --- /dev/null +++ b/opcodes/fr30-opc.c @@ -0,0 +1,1397 @@ +/* Instruction opcode table for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & fr30_cgen_ifld_table[FR30_##f] +#else +#define F(f) & fr30_cgen_ifld_table[FR30_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RJ) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U4) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add2 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_M4) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div0s = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div3 = { + 16, 16, 0xffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_OP4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi8 = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi20 = { + 16, 32, 0xff00, { { F (F_OP1) }, { F (F_I20) }, { F (F_OP2) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi32 = { + 16, 48, 0xfff0, { { F (F_OP1) }, { F (F_I32) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr14 = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP10) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr14uh = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP9) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr14ub = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP8) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr15 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_UDISP6) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr15dr = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RS2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movdr = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS1) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_call = { + 16, 16, 0xf800, { { F (F_OP1) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_int = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_brad = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_CC) }, { F (F_REL9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dmovr13 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dmovr13h = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dmovr13b = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_copop = { + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_copld = { + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RJC) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_copst = { + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_RIC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addsp = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldm0 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_LD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldm1 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_LD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stm0 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_ST) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stm1 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_ST) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_enter = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U10) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FR30_OPERAND_##op +#else +#define OPERAND(op) FR30_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xa600 } + }, +/* add $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xa400 } + }, +/* add2 $m4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, + & ifmt_add2, { 0xa500 } + }, +/* addc $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xa700 } + }, +/* addn $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xa200 } + }, +/* addn $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xa000 } + }, +/* addn2 $m4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, + & ifmt_add2, { 0xa100 } + }, +/* sub $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xac00 } + }, +/* subc $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xad00 } + }, +/* subn $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xae00 } + }, +/* cmp $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xaa00 } + }, +/* cmp $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xa800 } + }, +/* cmp2 $m4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, + & ifmt_add2, { 0xa900 } + }, +/* and $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x8200 } + }, +/* or $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x9200 } + }, +/* eor $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x9a00 } + }, +/* and $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x8400 } + }, +/* andh $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x8500 } + }, +/* andb $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x8600 } + }, +/* or $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9400 } + }, +/* orh $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9500 } + }, +/* orb $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9600 } + }, +/* eor $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9c00 } + }, +/* eorh $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9d00 } + }, +/* eorb $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9e00 } + }, +/* bandl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8000 } + }, +/* borl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9000 } + }, +/* beorl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9800 } + }, +/* bandh $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8100 } + }, +/* borh $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9100 } + }, +/* beorh $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9900 } + }, +/* btstl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8800 } + }, +/* btsth $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8900 } + }, +/* mul $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xaf00 } + }, +/* mulu $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xab00 } + }, +/* mulh $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xbf00 } + }, +/* muluh $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xbb00 } + }, +/* div0s $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9740 } + }, +/* div0u $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9750 } + }, +/* div1 $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9760 } + }, +/* div2 $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9770 } + }, +/* div3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f60 } + }, +/* div4s */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f70 } + }, +/* lsl $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xb600 } + }, +/* lsl $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb400 } + }, +/* lsl2 $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb500 } + }, +/* lsr $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xb200 } + }, +/* lsr $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb000 } + }, +/* lsr2 $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb100 } + }, +/* asr $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xba00 } + }, +/* asr $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb800 } + }, +/* asr2 $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb900 } + }, +/* ldi:8 $i8,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } }, + & ifmt_ldi8, { 0xc000 } + }, +/* ldi:20 $i20,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } }, + & ifmt_ldi20, { 0x9b00 } + }, +/* ldi:32 $i32,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } }, + & ifmt_ldi32, { 0x9f80 } + }, +/* ld @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x400 } + }, +/* lduh @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x500 } + }, +/* ldub @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x600 } + }, +/* ld @($R13,$Rj),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, + & ifmt_add, { 0x0 } + }, +/* lduh @($R13,$Rj),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, + & ifmt_add, { 0x100 } + }, +/* ldub @($R13,$Rj),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, + & ifmt_add, { 0x200 } + }, +/* ld @($R14,$disp10),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } }, + & ifmt_ldr14, { 0x2000 } + }, +/* lduh @($R14,$disp9),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } }, + & ifmt_ldr14uh, { 0x4000 } + }, +/* ldub @($R14,$disp8),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } }, + & ifmt_ldr14ub, { 0x6000 } + }, +/* ld @($R15,$udisp6),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } }, + & ifmt_ldr15, { 0x300 } + }, +/* ld @$R15+,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } }, + & ifmt_div0s, { 0x700 } + }, +/* ld @$R15+,$Rs2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } }, + & ifmt_ldr15dr, { 0x780 } + }, +/* ld @$R15+,$ps */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } }, + & ifmt_div3, { 0x790 } + }, +/* st $Ri,@$Rj */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, + & ifmt_add, { 0x1400 } + }, +/* sth $Ri,@$Rj */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, + & ifmt_add, { 0x1500 } + }, +/* stb $Ri,@$Rj */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, + & ifmt_add, { 0x1600 } + }, +/* st $Ri,@($R13,$Rj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, + & ifmt_add, { 0x1000 } + }, +/* sth $Ri,@($R13,$Rj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, + & ifmt_add, { 0x1100 } + }, +/* stb $Ri,@($R13,$Rj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, + & ifmt_add, { 0x1200 } + }, +/* st $Ri,@($R14,$disp10) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } }, + & ifmt_ldr14, { 0x3000 } + }, +/* sth $Ri,@($R14,$disp9) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } }, + & ifmt_ldr14uh, { 0x5000 } + }, +/* stb $Ri,@($R14,$disp8) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } }, + & ifmt_ldr14ub, { 0x7000 } + }, +/* st $Ri,@($R15,$udisp6) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } }, + & ifmt_ldr15, { 0x1300 } + }, +/* st $Ri,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } }, + & ifmt_div0s, { 0x1700 } + }, +/* st $Rs2,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } }, + & ifmt_ldr15dr, { 0x1780 } + }, +/* st $ps,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } }, + & ifmt_div3, { 0x1790 } + }, +/* mov $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x8b00 } + }, +/* mov $Rs1,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } }, + & ifmt_movdr, { 0xb700 } + }, +/* mov $ps,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } }, + & ifmt_div0s, { 0x1710 } + }, +/* mov $Ri,$Rs1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } }, + & ifmt_movdr, { 0xb300 } + }, +/* mov $Ri,$ps */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } }, + & ifmt_div0s, { 0x710 } + }, +/* jmp @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9700 } + }, +/* jmp:d @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9f00 } + }, +/* call @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9710 } + }, +/* call:d @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9f10 } + }, +/* call $label12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL12), 0 } }, + & ifmt_call, { 0xd000 } + }, +/* call:d $label12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL12), 0 } }, + & ifmt_call, { 0xd800 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9720 } + }, +/* ret:d */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f20 } + }, +/* int $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x1f00 } + }, +/* inte */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f30 } + }, +/* reti */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9730 } + }, +/* bra:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf000 } + }, +/* bra $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe000 } + }, +/* bno:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf100 } + }, +/* bno $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe100 } + }, +/* beq:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf200 } + }, +/* beq $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe200 } + }, +/* bne:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf300 } + }, +/* bne $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe300 } + }, +/* bc:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf400 } + }, +/* bc $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe400 } + }, +/* bnc:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf500 } + }, +/* bnc $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe500 } + }, +/* bn:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf600 } + }, +/* bn $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe600 } + }, +/* bp:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf700 } + }, +/* bp $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe700 } + }, +/* bv:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf800 } + }, +/* bv $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe800 } + }, +/* bnv:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf900 } + }, +/* bnv $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe900 } + }, +/* blt:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfa00 } + }, +/* blt $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xea00 } + }, +/* bge:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfb00 } + }, +/* bge $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xeb00 } + }, +/* ble:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfc00 } + }, +/* ble $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xec00 } + }, +/* bgt:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfd00 } + }, +/* bgt $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xed00 } + }, +/* bls:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfe00 } + }, +/* bls $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xee00 } + }, +/* bhi:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xff00 } + }, +/* bhi $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xef00 } + }, +/* dmov $R13,@$dir10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } }, + & ifmt_dmovr13, { 0x1800 } + }, +/* dmovh $R13,@$dir9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } }, + & ifmt_dmovr13h, { 0x1900 } + }, +/* dmovb $R13,@$dir8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } }, + & ifmt_dmovr13b, { 0x1a00 } + }, +/* dmov @$R13+,@$dir10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } }, + & ifmt_dmovr13, { 0x1c00 } + }, +/* dmovh @$R13+,@$dir9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } }, + & ifmt_dmovr13h, { 0x1d00 } + }, +/* dmovb @$R13+,@$dir8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } }, + & ifmt_dmovr13b, { 0x1e00 } + }, +/* dmov @$R15+,@$dir10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } }, + & ifmt_dmovr13, { 0x1b00 } + }, +/* dmov @$dir10,$R13 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } }, + & ifmt_dmovr13, { 0x800 } + }, +/* dmovh @$dir9,$R13 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } }, + & ifmt_dmovr13h, { 0x900 } + }, +/* dmovb @$dir8,$R13 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } }, + & ifmt_dmovr13b, { 0xa00 } + }, +/* dmov @$dir10,@$R13+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } }, + & ifmt_dmovr13, { 0xc00 } + }, +/* dmovh @$dir9,@$R13+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } }, + & ifmt_dmovr13h, { 0xd00 } + }, +/* dmovb @$dir8,@$R13+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } }, + & ifmt_dmovr13b, { 0xe00 } + }, +/* dmov @$dir10,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } }, + & ifmt_dmovr13, { 0xb00 } + }, +/* ldres @$Ri+,$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } }, + & ifmt_addi, { 0xbc00 } + }, +/* stres $u4,@$Ri+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } }, + & ifmt_addi, { 0xbd00 } + }, +/* copop $u4c,$ccc,$CRj,$CRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } }, + & ifmt_copop, { 0x9fc0 } + }, +/* copld $u4c,$ccc,$Rjc,$CRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } }, + & ifmt_copld, { 0x9fd0 } + }, +/* copst $u4c,$ccc,$CRj,$Ric */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } }, + & ifmt_copst, { 0x9fe0 } + }, +/* copsv $u4c,$ccc,$CRj,$Ric */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } }, + & ifmt_copst, { 0x9ff0 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9fa0 } + }, +/* andccr $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x8300 } + }, +/* orccr $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x9300 } + }, +/* stilm $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x8700 } + }, +/* addsp $s10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (S10), 0 } }, + & ifmt_addsp, { 0xa300 } + }, +/* extsb $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9780 } + }, +/* extub $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9790 } + }, +/* extsh $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x97a0 } + }, +/* extuh $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x97b0 } + }, +/* ldm0 ($reglist_low_ld) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } }, + & ifmt_ldm0, { 0x8c00 } + }, +/* ldm1 ($reglist_hi_ld) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } }, + & ifmt_ldm1, { 0x8d00 } + }, +/* stm0 ($reglist_low_st) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } }, + & ifmt_stm0, { 0x8e00 } + }, +/* stm1 ($reglist_hi_st) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } }, + & ifmt_stm1, { 0x8f00 } + }, +/* enter $u10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U10), 0 } }, + & ifmt_enter, { 0xf00 } + }, +/* leave */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f90 } + }, +/* xchb @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x8a00 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & fr30_cgen_ifld_table[FR30_##f] +#else +#define F(f) & fr30_cgen_ifld_table[FR30_/**/f] +#endif +static const CGEN_IFMT ifmt_ldi8m = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi20m = { + 16, 32, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RI) }, { F (F_I20) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi32m = { + 16, 48, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { F (F_I32) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FR30_OPERAND_##op +#else +#define OPERAND(op) FR30_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE fr30_cgen_macro_insn_table[] = +{ +/* ldi8 $i8,$Ri */ + { + -1, "ldi8m", "ldi8", 16, + { 0|A(NO_DIS)|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & fr30_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + fr30_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h new file mode 100644 index 0000000..2b89a90 --- /dev/null +++ b/opcodes/fr30-opc.h @@ -0,0 +1,151 @@ +/* Instruction opcode header for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FR30_OPC_H +#define FR30_OPC_H + +/* -- opc.h */ + +/* ??? This can be improved upon. */ +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 16 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4) + +/* -- */ +/* Enum declaration for fr30 instruction types. */ +typedef enum cgen_insn_type { + FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2 + , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2 + , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP + , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR + , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB + , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM + , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL + , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH + , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU + , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U + , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S + , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR + , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI + , FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32 + , FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13 + , FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH + , FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR + , FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB + , FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14 + , FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR + , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR + , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP + , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL + , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RET_D, FR30_INSN_INT + , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRAD, FR30_INSN_BRA + , FR30_INSN_BNOD, FR30_INSN_BNO, FR30_INSN_BEQD, FR30_INSN_BEQ + , FR30_INSN_BNED, FR30_INSN_BNE, FR30_INSN_BCD, FR30_INSN_BC + , FR30_INSN_BNCD, FR30_INSN_BNC, FR30_INSN_BND, FR30_INSN_BN + , FR30_INSN_BPD, FR30_INSN_BP, FR30_INSN_BVD, FR30_INSN_BV + , FR30_INSN_BNVD, FR30_INSN_BNV, FR30_INSN_BLTD, FR30_INSN_BLT + , FR30_INSN_BGED, FR30_INSN_BGE, FR30_INSN_BLED, FR30_INSN_BLE + , FR30_INSN_BGTD, FR30_INSN_BGT, FR30_INSN_BLSD, FR30_INSN_BLS + , FR30_INSN_BHID, FR30_INSN_BHI, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H + , FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB + , FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B + , FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD + , FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD + , FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR + , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB + , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0 + , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER + , FR30_INSN_LEAVE, FR30_INSN_XCHB +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID FR30_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) FR30_INSN_XCHB + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_op1; + long f_op2; + long f_op3; + long f_op4; + long f_op5; + long f_cc; + long f_ccc; + long f_Rj; + long f_Ri; + long f_Rs1; + long f_Rs2; + long f_Rjc; + long f_Ric; + long f_CRj; + long f_CRi; + long f_u4; + long f_u4c; + long f_i4; + long f_m4; + long f_u8; + long f_i8; + long f_i20_4; + long f_i20_16; + long f_i20; + long f_i32; + long f_udisp6; + long f_disp8; + long f_disp9; + long f_disp10; + long f_s10; + long f_u10; + long f_rel9; + long f_dir8; + long f_dir9; + long f_dir10; + long f_rel12; + long f_reglist_hi_st; + long f_reglist_low_st; + long f_reglist_hi_ld; + long f_reglist_low_ld; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* FR30_OPC_H */ diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c new file mode 100644 index 0000000..c521c77 --- /dev/null +++ b/opcodes/h8300-dis.c @@ -0,0 +1,435 @@ +/* Disassemble h8300 instructions. + Copyright 1993, 1994, 1996, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DEFINE_TABLE + +#include "sysdep.h" +#define h8_opcodes h8ops +#include "opcode/h8300.h" +#include "dis-asm.h" +#include "opintl.h" + +static void bfd_h8_disassemble_init PARAMS ((void)); +static unsigned int bfd_h8_disassemble + PARAMS ((bfd_vma, disassemble_info *, int)); + +/* Run through the opcodes and sort them into order to make them easy + to disassemble. */ +static void +bfd_h8_disassemble_init () +{ + unsigned int i; + struct h8_opcode *p; + + for (p = h8_opcodes; p->name; p++) + { + int n1 = 0; + int n2 = 0; + + if ((int) p->data.nib[0] < 16) + n1 = (int) p->data.nib[0]; + else + n1 = 0; + + if ((int) p->data.nib[1] < 16) + n2 = (int) p->data.nib[1]; + else + n2 = 0; + + /* Just make sure there are an even number of nibbles in it, and + that the count is the same as the length. */ + for (i = 0; p->data.nib[i] != E; i++) + ; + + if (i & 1) + abort (); + + p->length = i / 2; + } +} + +static unsigned int +bfd_h8_disassemble (addr, info, mode) + bfd_vma addr; + disassemble_info *info; + int mode; +{ + /* Find the first entry in the table for this opcode. */ + static CONST char *regnames[] = + { + "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h", + "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l" + }; + static CONST char *wregnames[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" + }; + static CONST char *lregnames[] = + { + "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", + "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" + }; + int rs = 0; + int rd = 0; + int rdisp = 0; + int abs = 0; + int bit = 0; + int plen = 0; + static boolean init = 0; + struct h8_opcode *q; + char CONST **pregnames = mode != 0 ? lregnames : wregnames; + int status; + int l; + unsigned char data[20]; + void *stream = info->stream; + fprintf_ftype fprintf = info->fprintf_func; + + if (!init) + { + bfd_h8_disassemble_init (); + init = 1; + } + + status = info->read_memory_func (addr, data, 2, info); + if (status != 0) + { + info->memory_error_func (status, addr, info); + return -1; + } + + for (l = 2; status == 0 && l < 10; l += 2) + status = info->read_memory_func (addr + l, data + l, 2, info); + + /* Find the exact opcode/arg combo. */ + for (q = h8_opcodes; q->name; q++) + { + op_type *nib = q->data.nib; + unsigned int len = 0; + + while (1) + { + op_type looking_for = *nib; + int thisnib = data[len >> 1]; + + thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); + + if (looking_for < 16 && looking_for >= 0) + { + if (looking_for != thisnib) + goto fail; + } + else + { + if ((int) looking_for & (int) B31) + { + if (!(((int) thisnib & 0x8) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B31); + } + + if ((int) looking_for & (int) B30) + { + if (!(((int) thisnib & 0x8) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B30); + } + + if (looking_for & DBIT) + { + /* Exclude adds/subs by looking at bit 0 and 2, and + make sure the operand size, either w or l, + matches by looking at bit 1. */ + if ((looking_for & 7) != (thisnib & 7)) + goto fail; + + abs = (thisnib & 0x8) ? 2 : 1; + } + else if (looking_for & (REG | IND | INC | DEC)) + { + if (looking_for & SRC) + rs = thisnib; + else + rd = thisnib; + } + else if (looking_for & L_16) + { + abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; + plen = 16; + } + else if (looking_for & ABSJMP) + { + abs = (data[1] << 16) | (data[2] << 8) | (data[3]); + } + else if (looking_for & MEMIND) + { + abs = data[1]; + } + else if (looking_for & L_32) + { + int i = len >> 1; + + abs = (data[i] << 24) + | (data[i + 1] << 16) + | (data[i + 2] << 8) + | (data[i + 3]); + + plen = 32; + } + else if (looking_for & L_24) + { + int i = len >> 1; + + abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); + plen = 24; + } + else if (looking_for & IGNORE) + { + ; + } + else if (looking_for & DISPREG) + { + rdisp = thisnib; + } + else if (looking_for & KBIT) + { + switch (thisnib) + { + case 9: + abs = 4; + break; + case 8: + abs = 2; + break; + case 0: + abs = 1; + break; + default: + goto fail; + } + } + else if (looking_for & L_8) + { + plen = 8; + abs = data[len >> 1]; + } + else if (looking_for & L_3) + { + bit = thisnib & 0x7; + } + else if (looking_for & L_2) + { + plen = 2; + abs = thisnib & 0x3; + } + else if (looking_for & MACREG) + { + abs = (thisnib == 3); + } + else if (looking_for == E) + { + int i; + + for (i = 0; i < q->length; i++) + fprintf (stream, "%02x ", data[i]); + + for (; i < 6; i++) + fprintf (stream, " "); + + fprintf (stream, "%s\t", q->name); + + /* Gross. Disgusting. */ + if (strcmp (q->name, "ldm.l") == 0) + { + int count, high; + + count = (data[1] >> 4) & 0x3; + high = data[3] & 0x7; + + fprintf (stream, "@sp+,er%d-er%d", high - count, high); + return q->length; + } + + if (strcmp (q->name, "stm.l") == 0) + { + int count, low; + + count = (data[1] >> 4) & 0x3; + low = data[3] & 0x7; + + fprintf (stream, "er%d-er%d,@-sp", low, low + count); + return q->length; + } + + /* Fill in the args. */ + { + op_type *args = q->args.nib; + int hadone = 0; + + while (*args != E) + { + int x = *args; + + if (hadone) + fprintf (stream, ","); + + if (x & L_3) + { + fprintf (stream, "#0x%x", (unsigned) bit); + } + else if (x & (IMM | KBIT | DBIT)) + { + /* Bletch. For shal #2,er0 and friends. */ + if (*(args + 1) & SRC_IN_DST) + abs = 2; + + fprintf (stream, "#0x%x", (unsigned) abs); + } + else if (x & REG) + { + int rn = (x & DST) ? rd : rs; + + switch (x & SIZE) + { + case L_8: + fprintf (stream, "%s", regnames[rn]); + break; + case L_16: + fprintf (stream, "%s", wregnames[rn]); + break; + case L_P: + case L_32: + fprintf (stream, "%s", lregnames[rn]); + break; + } + } + else if (x & MACREG) + { + fprintf (stream, "mac%c", abs ? 'l' : 'h'); + } + else if (x & INC) + { + fprintf (stream, "@%s+", pregnames[rs]); + } + else if (x & DEC) + { + fprintf (stream, "@-%s", pregnames[rd]); + } + else if (x & IND) + { + int rn = (x & DST) ? rd : rs; + fprintf (stream, "@%s", pregnames[rn]); + } + else if (x & ABS8MEM) + { + fprintf (stream, "@0x%x:8", (unsigned) abs); + } + else if (x & (ABS | ABSJMP)) + { + fprintf (stream, "@0x%x:%d", (unsigned) abs, plen); + } + else if (x & MEMIND) + { + fprintf (stream, "@@%d (%x)", abs, abs); + } + else if (x & PCREL) + { + if (x & L_16) + { + abs += 2; + fprintf (stream, + ".%s%d (%x)", + (short) abs > 0 ? "+" : "", + (short) abs, addr + (short) abs + 2); + } + else + { + fprintf (stream, + ".%s%d (%x)", + (char) abs > 0 ? "+" : "", + (char) abs, addr + (char) abs + 2); + } + } + else if (x & DISP) + { + fprintf (stream, "@(0x%x:%d,%s)", + abs, plen, pregnames[rdisp]); + } + else if (x & CCR) + { + fprintf (stream, "ccr"); + } + else if (x & EXR) + { + fprintf (stream, "exr"); + } + else + /* xgettext:c-format */ + fprintf (stream, _("Hmmmm %x"), x); + + hadone = 1; + args++; + } + } + + return q->length; + } + else + /* xgettext:c-format */ + fprintf (stream, _("Don't understand %x \n"), looking_for); + } + + len++; + nib++; + } + + fail: + ; + } + + /* Fell off the end. */ + fprintf (stream, "%02x %02x .word\tH'%x,H'%x", + data[0], data[1], + data[0], data[1]); + return 2; +} + +int +print_insn_h8300 (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + return bfd_h8_disassemble (addr, info, 0); +} + +int +print_insn_h8300h (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + return bfd_h8_disassemble (addr, info, 1); +} + +int +print_insn_h8300s (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + return bfd_h8_disassemble (addr, info, 2); +} diff --git a/opcodes/h8500-dis.c b/opcodes/h8500-dis.c new file mode 100644 index 0000000..6237182 --- /dev/null +++ b/opcodes/h8500-dis.c @@ -0,0 +1,352 @@ +/* Disassemble h8500 instructions. + Copyright 1993, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#define DISASSEMBLER_TABLE +#define DEFINE_TABLE + +#include "sysdep.h" +#include "h8500-opc.h" +#include "dis-asm.h" +#include "opintl.h" + +/* Maximum length of an instruction. */ +#define MAXLEN 8 + +#include + +static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (info, addr) + struct disassemble_info *info; + bfd_byte *addr; +{ + int status; + struct private *priv = (struct private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} + +static char *crname[] = { "sr", "ccr", "*", "br", "ep", "dp", "*", "tp" }; + +int +print_insn_h8500 (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + h8500_opcode_info *opcode; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + struct private priv; + bfd_byte *buffer = priv.the_buffer; + + info->private_data = (PTR) & priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = addr; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + if (0) + { + static int one; + + if (!one) + { + one = 1; + for (opcode = h8500_table; opcode->name; opcode++) + { + if ((opcode->bytes[0].contents & 0x8) == 0) + printf ("%s\n", opcode->name); + } + } + } + + /* Run down the table to find the one which matches. */ + for (opcode = h8500_table; opcode->name; opcode++) + { + int byte; + int rn = 0; + int rd = 0; + int rs = 0; + int disp = 0; + int abs = 0; + int imm = 0; + int pcrel = 0; + int qim = 0; + int i; + int cr = 0; + + for (byte = 0; byte < opcode->length; byte++) + { + FETCH_DATA (info, buffer + byte + 1); + if ((buffer[byte] & opcode->bytes[byte].mask) + != (opcode->bytes[byte].contents)) + { + goto next; + } + else + { + /* Extract any info parts. */ + switch (opcode->bytes[byte].insert) + { + case 0: + case FP: + break; + default: + /* xgettext:c-format */ + func (stream, _("can't cope with insert %d\n"), + opcode->bytes[byte].insert); + break; + case RN: + rn = buffer[byte] & 0x7; + break; + case RS: + rs = buffer[byte] & 0x7; + break; + case CRB: + cr = buffer[byte] & 0x7; + if (cr == 0) + goto next; + break; + case CRW: + cr = buffer[byte] & 0x7; + if (cr != 0) + goto next; + break; + case DISP16: + FETCH_DATA (info, buffer + byte + 2); + disp = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case FPIND_D8: + case DISP8: + disp = ((char) (buffer[byte])); + break; + case RD: + case RDIND: + rd = buffer[byte] & 0x7; + break; + case ABS24: + FETCH_DATA (info, buffer + byte + 3); + abs = + (buffer[byte] << 16) + | (buffer[byte + 1] << 8) + | (buffer[byte + 2]); + break; + case ABS16: + FETCH_DATA (info, buffer + byte + 2); + abs = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case ABS8: + abs = (buffer[byte]); + break; + case IMM16: + FETCH_DATA (info, buffer + byte + 2); + imm = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case IMM4: + imm = (buffer[byte]) & 0xf; + break; + case IMM8: + case RLIST: + imm = (buffer[byte]); + break; + case PCREL16: + FETCH_DATA (info, buffer + byte + 2); + pcrel = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case PCREL8: + pcrel = (buffer[byte]); + break; + case QIM: + switch (buffer[byte] & 0x7) + { + case 0: + qim = 1; + break; + case 1: + qim = 2; + break; + case 4: + qim = -1; + break; + case 5: + qim = -2; + break; + } + break; + + } + } + } + /* We get here when all the masks have passed so we can output + the operands. */ + FETCH_DATA (info, buffer + opcode->length); + for (i = 0; i < opcode->length; i++) + { + (func) (stream, "%02x ", buffer[i]); + } + for (; i < 6; i++) + { + (func) (stream, " "); + } + (func) (stream, "%s\t", opcode->name); + for (i = 0; i < opcode->nargs; i++) + { + if (i) + (func) (stream, ","); + switch (opcode->arg_type[i]) + { + case FP: + func (stream, "fp"); + break; + case RNIND_D16: + func (stream, "@(0x%x:16,r%d)", disp, rn); + break; + case RNIND_D8: + func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn); + break; + case RDIND_D16: + func (stream, "@(0x%x:16,r%d)", disp, rd); + break; + case RDIND_D8: + func (stream, "@(0x%x:8 (%d), r%d)", disp & 0xff, disp, rd); + break; + case FPIND_D8: + func (stream, "@(0x%x:8 (%d), fp)", disp & 0xff, disp, rn); + break; + case CRB: + case CRW: + func (stream, "%s", crname[cr]); + break; + case RN: + func (stream, "r%d", rn); + break; + case RD: + func (stream, "r%d", rd); + break; + case RS: + func (stream, "r%d", rs); + break; + case RNDEC: + func (stream, "@-r%d", rn); + break; + case RNINC: + func (stream, "@r%d+", rn); + break; + case RNIND: + func (stream, "@r%d", rn); + break; + case RDIND: + func (stream, "@r%d", rd); + break; + case SPINC: + func (stream, "@sp+"); + break; + case SPDEC: + func (stream, "@-sp"); + break; + case ABS24: + func (stream, "@0x%0x:24", abs); + break; + case ABS16: + func (stream, "@0x%0x:16", abs & 0xffff); + break; + case ABS8: + func (stream, "@0x%0x:8", abs & 0xff); + break; + case IMM16: + func (stream, "#0x%0x:16", imm & 0xffff); + break; + case RLIST: + { + int i; + int nc = 0; + func (stream, "("); + for (i = 0; i < 8; i++) + { + if (imm & (1 << i)) + { + func (stream, "r%d", i); + if (nc) + func (stream, ","); + nc = 1; + } + } + func (stream, ")"); + } + break; + case IMM8: + func (stream, "#0x%0x:8", imm & 0xff); + break; + case PCREL16: + func (stream, "0x%0x:16", + (pcrel + addr + opcode->length) & 0xffff); + break; + case PCREL8: + func (stream, "#0x%0x:8", + ((char) pcrel + addr + opcode->length) & 0xffff); + break; + case QIM: + func (stream, "#%d:q", qim); + break; + case IMM4: + func (stream, "#%d:4", imm); + break; + } + } + return opcode->length; + next: + ; + } + + /* Couldn't understand anything. */ + /* xgettext:c-format */ + func (stream, _("%02x\t\t*unknown*"), buffer[0]); + return 1; +} diff --git a/opcodes/h8500-opc.h b/opcodes/h8500-opc.h new file mode 100644 index 0000000..13ee7fb --- /dev/null +++ b/opcodes/h8500-opc.h @@ -0,0 +1,3858 @@ +/* Instruction opcode header for Hitachi 8500. + +Copyright 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +typedef enum +{ + GR0,GR1,GR2,GR3,GR4,GR5,GR6,GR7, + GPR0, GPR1, GPR2, GPR3, GPR4, GPR5, GPR6, GPR7, + GCCR, GPC, + GSEGC, GSEGD, GSEGE, GSEGT,GLAST +} gdbreg_type; +#define O_XORC 1 +#define O_XOR 2 +#define O_XCH 3 +#define O_UNLK 4 +#define O_TST 5 +#define O_TRAPA 6 +#define O_TRAP_VS 7 +#define O_TAS 8 +#define O_SWAP 9 +#define O_SUBX 10 +#define O_SUBS 11 +#define O_SUB 12 +#define O_STM 13 +#define O_STC 14 +#define O_SLEEP 15 +#define O_SHLR 16 +#define O_SHLL 17 +#define O_SHAR 18 +#define O_SHAL 19 +#define O_SCB_NE 20 +#define O_SCB_F 21 +#define O_SCB_EQ 22 +#define O_RTS 23 +#define O_RTD 24 +#define O_ROTXR 25 +#define O_ROTXL 26 +#define O_ROTR 27 +#define O_ROTL 28 +#define O_PRTS 29 +#define O_PRTD 30 +#define O_PJSR 31 +#define O_PJMP 32 +#define O_ORC 33 +#define O_OR 34 +#define O_NOT 35 +#define O_NOP 36 +#define O_NEG 37 +#define O_MULXU 38 +#define O_MOVTPE 39 +#define O_MOVFPE 40 +#define O_MOV 41 +#define O_LINK 42 +#define O_LDM 43 +#define O_LDC 44 +#define O_JSR 45 +#define O_JMP 46 +#define O_EXTU 47 +#define O_EXTS 48 +#define O_DSUB 49 +#define O_DIVXU 50 +#define O_DADD 51 +#define O_CMP 52 +#define O_CLR 53 +#define O_BVS 54 +#define O_BVC 55 +#define O_BTST 56 +#define O_BT 57 +#define O_BSR 58 +#define O_BSET 59 +#define O_BRN 60 +#define O_BRA 61 +#define O_BPT 62 +#define O_BPL 63 +#define O_BNOT 64 +#define O_BNE 65 +#define O_BMI 66 +#define O_BLT 67 +#define O_BLS 68 +#define O_BLO 69 +#define O_BLE 70 +#define O_BHS 71 +#define O_BHI 72 +#define O_BGT 73 +#define O_BGE 74 +#define O_BF 75 +#define O_BEQ 76 +#define O_BCS 77 +#define O_BCLR 78 +#define O_BCC 79 +#define O_ANDC 80 +#define O_AND 81 +#define O_ADDX 82 +#define O_ADDS 83 +#define O_ADD 84 +#define O_BYTE 128 +#define O_WORD 0x000 +#define O_UNSZ 0x000 +#define FPIND_D8 10 +#define RDIND_D16 11 +#define RDIND_D8 12 +#define SPDEC 13 +#define RDIND 14 +#define RN 15 +#define RNIND_D8 16 +#define RNIND_D16 17 +#define RNDEC 18 +#define RNINC 19 +#define RNIND 20 +#define SPINC 21 +#define ABS16 22 +#define ABS24 23 +#define PCREL16 24 +#define PCREL8 25 +#define ABS8 26 +#define CRB 27 +#define CR 28 +#define CRW 29 +#define DISP16 30 +#define DISP8 31 +#define FP 32 +#define IMM16 33 +#define IMM4 34 +#define IMM8 35 +#define RLIST 36 +#define QIM 37 +#define RD 38 +#define RS 39 +#define SP 40 +typedef enum { AC_BAD, AC_EI, AC_RI, AC_D, AC_,AC_ERR, AC_X,AC_B, AC_EE,AC_RR,AC_IE, + AC_RE,AC_E, AC_I, AC_ER,AC_IRR, AC_IR, AC_RER, AC_ERE,AC_EIE } addr_class_type; +typedef struct { + short int idx; + char flags,src1,src2,dst; + unsigned char flavor; + char *name; + int nargs; + int arg_type[2]; + int length; + struct { unsigned char contents;unsigned char mask; char insert; } bytes[6]; +} h8500_opcode_info; +h8500_opcode_info h8500_table[] +#ifdef ASSEMBLER_TABLE +#ifdef DEFINE_TABLE +={ +/* +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS16},6, {{0x1d,0xff, }, + {0x00,0x00,ABS16 }, + {0x00,0x00, }, + {0x07,0xff, }, + {0x00,0x00,IMM16 },{0x00,0x00, }}},*/ + +{1,'s','E','C','C',O_XORC|O_WORD,"xorc.w",2,{IMM16,CRW},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x68,0xf8,CRW }}}, +{2,'s','E','C','C',O_XORC|O_BYTE,"xorc.b",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x68,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x60,0xf8,RD }}}, +{6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, +{7,'-','X','!','!',O_XCH|O_UNSZ,"xch",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, +{8,'-','B','!','!',O_UNLK|O_UNSZ,"unlk",1,{FP,0},1, {{0x0f,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x16,0xff, }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x16,0xff, }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x16,0xff, }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x16,0xff, }}}, +{12,'-','I','!','!',O_TRAPA|O_UNSZ,"trapa",1,{IMM4,0},2, {{0x08,0xff, },{0x10,0xf0,IMM4 }}}, +{13,'-','B','!','!',O_TRAP_VS|O_UNSZ,"trap/vs",0,{0,0},1, {{0x09,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x17,0xff, }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RN,0},2, {{0xa0,0xf8,RN },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{IMM8,0},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{ABS8,0},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{ABS16,0},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x17,0xff, }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x17,0xff, }}}, +{16,'m','D','!','D',O_SWAP|O_BYTE,"swap.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x10,0xff, }}}, +{17,'m','D','!','D',O_SWAP|O_UNSZ,"swap",1,{RD,0},2, {{0xa0,0xf8,RD },{0x10,0xff, }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb0,0xf8,RD }}}, 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},{0x00,0x00,ABS16 },{0x00,0x00, },{0x14,0xff, }}}, +{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x14,0xff, }}}, +{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x14,0xff, }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0xa8,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x90,0xf8,RS }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{IMM8,RD},4, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS8,RD},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS16,RD},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{IMM8,RD},4, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{ABS8,RD},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{ABS16,RD},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x00,0xff, },{0x80,0xf8,RD }}}, +{85,'m','S','!','E',O_MOV|O_WORD,"mov:s.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{86,'m','S','!','E',O_MOV|O_BYTE,"mov:s.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, +{87,'m','S','!','E',O_MOV|O_UNSZ,"mov:s",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{88,'m','E','!','D',O_MOV|O_WORD,"mov:l.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{89,'m','E','!','D',O_MOV|O_BYTE,"mov:l.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, +{90,'m','E','!','D',O_MOV|O_UNSZ,"mov:l",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{91,'m','I','!','D',O_MOV|O_WORD,"mov:i.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{92,'m','I','!','D',O_MOV|O_UNSZ,"mov:i", 2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D8},5,{{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D16},6,{{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, + +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS8},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND},3, {{0xd8,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNDEC},3, {{0xb8,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNINC},3, {{0xc8,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND_D8},4, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,ABS8},4, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,ABS16},5, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND_D16},5, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{96,'m','S','!','E',O_MOV|O_WORD,"mov:f.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{96,'m','E','!','D',O_MOV|O_WORD,"mov:f.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{97,'m','S','!','E',O_MOV|O_BYTE,"mov:f.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{97,'m','E','!','D',O_MOV|O_BYTE,"mov:f.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{98,'m','S','!','E',O_MOV|O_UNSZ,"mov:f",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{98,'m','E','!','D',O_MOV|O_UNSZ,"mov:f",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{99,'m','I','!','D',O_MOV|O_BYTE,"mov:e.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{100,'m','I','!','D',O_MOV|O_UNSZ,"mov:e",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{101,'m','I','!','D',O_MOV|O_WORD,"mov.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, + +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, +{102,'m','I','!','D',O_MOV|O_BYTE,"mov.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS8},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +/*{103,'m','I','!','D',O_MOV|O_UNSZ,"mov",2,{IMM8,RD},2, {{0x58,0xf8,RD },{0x00,0x00,IMM8 }}},*/ +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND},3, {{0xd8,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNINC},3, {{0xc8,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNDEC},3, {{0xb8,0xf8,RN },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{103,'m','I','!','D',O_MOV|O_UNSZ,"mov",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,ABS8},4, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x90,0xf8,RS }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND_D8},4, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x80,0xf8,RD }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,ABS16},5, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND_D16},5, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x06,0xff, },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x07,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM8},2, {{0x17,0xff, },{0x00,0x00,IMM8 }}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM16},3, {{0x1f,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{105,'-','E','!','C',O_LDM|O_UNSZ,"ldm",2,{SPINC,RLIST},2, {{0x02,0xff, },{0x00,0x00,RLIST }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RN,CRW},2, {{0xa8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND,CRW},2, {{0xd8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNINC,CRW},2, {{0xc8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNDEC,CRW},2, {{0xb8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{ABS8,CRW},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND_D8,CRW},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{IMM16,CRW},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{ABS16,CRW},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND_D16,CRW},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRW }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS8,CRB},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS16,CRB},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RN,CRW},2, {{0xa8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNINC,CRW},2, {{0xc8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNDEC,CRW},2, {{0xb8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND,CRW},2, {{0xd8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS8,CRW},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS8,CRB},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{IMM8,CRB},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND_D8,CRW},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, 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},{0x00,0x00, },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND_D16},6,{{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{125,'a','D','I','!',O_CMP|O_BYTE,"cmp:e.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, +{126,'a','D','I','!',O_CMP|O_UNSZ,"cmp:e",2,{IMM8,RD},2, {{0x48,0xf8,RD },{0x00,0x00,IMM8 }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND_D16},6,{{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','D','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,ABS8},4, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,ABS16},5, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x04,0xff, },{0x00,0x00,IMM8 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM8,RD},2, {{0x48,0xf8,RD },{0x00,0x00,IMM8 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x70,0xf8,RD }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,ABS8},5, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,ABS16},6, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x05,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS8,0},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS16,0},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{IMM16,0},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x13,0xff, }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x13,0xff, }}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x13,0xff, }}}, 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+{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RN},2, {{0xa8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNIND},2, {{0xd8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNDEC},2, {{0xb8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNINC},2, {{0xc8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RN},2, {{0xa0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNINC},2, {{0xc0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNIND},2, {{0xd0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNDEC},2, {{0xb0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{IMM8,RD},3, {{0x04,0xff, },{0x00,0x00,IMM8 },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,ABS8},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{ABS8,RD},3, {{0x05,0xff, },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,ABS16},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{ABS16,RD},4, {{0x15,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RN},2, {{0xa8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNDEC},2, {{0xb8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND},2, {{0xd8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNINC},2, {{0xc8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,ABS8},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{ABS8,RD},3, {{0x0d,0xff, },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{ABS16,RD},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{IMM16,RD},4, {{0x0c,0xff, },{0x00,0x00,IMM16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,ABS16},4, {{0x1d,0xff, },{0x00,0x00,ABS16 },{0x00,0x00, },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00, },{0x20,0xf8,RD }}}, +0,0,0} +#endif +; +#endif +#ifdef DISASSEMBLER_TABLE +#ifdef DEFINE_TABLE +={ +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RN},2, {{0xa0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNDEC},2, {{0xb0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNINC},2, {{0xc0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND},2, {{0xd0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x30,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x30,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x60,0xf8,RD }}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x30,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x16,0xff,0}}}, +{6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff,0}}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x30,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x16,0xff,0}}}, +{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x30,0xf8,RD }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff,0}}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x30,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x16,0xff,0}}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff,0}}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x30,0xf8,RD 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{{0x04,0xff,0},{0x00,0x00,IMM8 },{0xb0,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x16,0xff,0}}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x17,0xff,0}}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x30,0xf8,RD }}}, +{22,'-','E','D','D',O_SUBS|O_BYTE,"subs.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x38,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x98,0xf8,CRB }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xb0,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x16,0xff,0}}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x17,0xff,0}}}, +{12,'-','I','!','!',O_TRAPA|O_UNSZ,"trapa",1,{IMM4,0},2, {{0x08,0xff,0},{0x10,0xf0,IMM4 }}}, +{13,'-','B','!','!',O_TRAP_VS|O_UNSZ,"trap/vs",0,{0,0},1, {{0x09,0xff,0}}}, +{24,'a','E','D','D',O_SUB|O_WORD,"sub.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x30,0xf8,RD }}}, +{21,'-','E','D','D',O_SUBS|O_WORD,"subs.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x38,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x60,0xf8,RD }}}, +{1,'s','E','C','C',O_XORC|O_WORD,"xorc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x68,0xf8,CRW }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xb0,0xf8,RD }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x16,0xff,0}}}, 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{{0x06,0xff,0},{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, +{46,'-','B','S','S',O_SCB_EQ|O_UNSZ,"scb/eq",2,{RS,PCREL8},3, {{0x07,0xff,0},{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, +{41,'h','E','!','E',O_SHAL|O_WORD,"shal.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x18,0xff,0}}}, +{52,'h','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1e,0xff,0}}}, +{41,'h','E','!','E',O_SHAL|O_WORD,"shal.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x18,0xff,0}}}, +{52,'h','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1e,0xff,0}}}, +{49,'h','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1f,0xff,0}}}, +{48,'-','B','!','!',O_RTD|O_UNSZ,"rtd",1,{IMM16,0},3, {{0x14,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{48,'-','B','!','!',O_RTD|O_UNSZ,"rtd",1,{IMM8,0},2, {{0x14,0xff,0},{0x00,0x00,IMM8 }}}, +{42,'h','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x18,0xff,0}}}, +{53,'h','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1e,0xff,0}}}, +{50,'h','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1f,0xff,0}}}, +{47,'-','B','!','!',O_RTS|O_UNSZ,"rts",0,{0,0},1, {{0x19,0xff,0}}}, +{41,'h','E','!','E',O_SHAL|O_WORD,"shal.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x18,0xff,0}}}, +{52,'h','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1e,0xff,0}}}, +{49,'h','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1f,0xff,0}}}, +{99,'m','I','!','D',O_MOV|O_BYTE,"mov:e.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{97,'m','E','!','D',O_MOV|O_BYTE,"mov:f.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{96,'m','E','!','D',O_MOV|O_WORD,"mov:f.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{97,'m','S','!','E',O_MOV|O_BYTE,"mov:f.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{96,'m','S','!','E',O_MOV|O_WORD,"mov:f.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1d,0xff,0}}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, +{91,'m','I','!','D',O_MOV|O_WORD,"mov:i.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{89,'m','E','!','D',O_MOV|O_BYTE,"mov:l.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, +{88,'m','E','!','D',O_MOV|O_WORD,"mov:l.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{86,'m','S','!','E',O_MOV|O_BYTE,"mov:s.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, +{85,'m','S','!','E',O_MOV|O_WORD,"mov:s.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xa8,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1c,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x40,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xa8,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x40,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x15,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x40,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1c,0xff,0}}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x14,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x40,0xf8,RD }}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1c,0xff,0}}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x15,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x40,0xf8,RD }}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1d,0xff,0}}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x15,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1d,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x40,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1d,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x40,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1d,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{63,'-','J','!','!',O_PJSR|O_UNSZ,"pjsr",1,{ABS24,0},4, {{0x03,0xff,0},{0x00,0x00,ABS24 },{0x00,0x00,0},{0x00,0x00,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x40,0xf8,RD }}}, +{66,'s','I','C','C',O_ORC|O_BYTE,"orc.b",2,{IMM8,CRB},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x48,0xf8,CRB }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x14,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x1c,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x40,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x15,0xff,0}}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x15,0xff,0}}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{74,'-','!','!','!',O_NOP|O_UNSZ,"nop",0,{0,0},1, {{0x00,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{65,'s','I','C','C',O_ORC|O_WORD,"orc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x48,0xf8,CRW }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1d,0xff,0}}}, +{64,'-','J','!','!',O_PJMP|O_UNSZ,"pjmp",1,{RDIND,0},2, {{0x11,0xff,0},{0xc0,0xf8,RDIND }}}, +{63,'-','J','!','!',O_PJSR|O_UNSZ,"pjsr",1,{RDIND,0},2, {{0x11,0xff,0},{0xc8,0xf8,RDIND }}}, +{62,'-','B','!','!',O_PRTD|O_UNSZ,"prtd",1,{IMM8,0},3, {{0x11,0xff,0},{0x14,0xff,0},{0x00,0x00,IMM8 }}}, +{61,'-','B','!','!',O_PRTS|O_UNSZ,"prts",0,{0,0},2, {{0x11,0xff,0},{0x19,0xff,0}}}, +{62,'-','B','!','!',O_PRTD|O_UNSZ,"prtd",1,{IMM16,0},4, {{0x11,0xff,0},{0x1c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{64,'-','J','!','!',O_PJMP|O_UNSZ,"pjmp",1,{ABS24,0},4, {{0x13,0xff,0},{0x00,0x00,ABS24 },{0x00,0x00,0},{0x00,0x00,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1c,0xff,0}}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1c,0xff,0}}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1c,0xff,0}}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1c,0xff,0}}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1c,0xff,0}}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x00,0xff,0},{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS8},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x00,0xff,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{IMM8,RD},4, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS8,RD},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1d,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1d,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1d,0xff,0}}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x1d,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x1d,0xff,0}}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNDEC},4, {{0xb8,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + + +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNINC},4, {{0xc8,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNIND},4, {{0xd8,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, + + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS8},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,ABS8},5, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + + +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS16,RD},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x00,0xff,0},{0x80,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS16},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x00,0xff,0},{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS16},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,ABS16},6, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{125,'a','D','I','!',O_CMP|O_BYTE,"cmp:e.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, +{120,'a','D','I','!',O_CMP|O_WORD,"cmp:i.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb8,0xf8,RD }}}, +{119,'s','D','!','!',O_DADD|O_UNSZ,"dadd",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff,0},{0xa0,0xf8,RD }}}, +{115,'s','D','!','!',O_DSUB|O_UNSZ,"dsub",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff,0},{0xb0,0xf8,RD }}}, +{113,'s','D','!','D',O_EXTS|O_BYTE,"exts.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x11,0xff,0}}}, +{111,'s','D','!','D',O_EXTU|O_BYTE,"extu.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x12,0xff,0}}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x88,0xf8,CRB }}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{ABS16,0},3, {{0x10,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0}}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND,0},2, {{0x11,0xff,0},{0xd0,0xf8,RD }}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND,0},2, {{0x11,0xff,0},{0xd8,0xf8,RD }}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D8,0},3, {{0x11,0xff,0},{0xe0,0xf8,RDIND_D8 },{0x00,0x00,0}}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D8,0},3, {{0x11,0xff,0},{0xe8,0xf8,RDIND_D8 },{0x00,0x00,0}}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D16,0},4, {{0x11,0xff,0},{0xf0,0xf8,RDIND_D16 },{0x00,0x00,0},{0x00,0x00,0}}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D16,0},4, {{0x11,0xff,0},{0xf8,0xf8,RDIND_D16 },{0x00,0x00,0},{0x00,0x00,0}}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{ABS16,0},3, {{0x18,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0}}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS16,CRB},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{IMM8,CRB},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS8,CRB},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{105,'-','E','!','C',O_LDM|O_UNSZ,"ldm",2,{SPINC,RLIST},2, {{0x02,0xff,0},{0x00,0x00,RLIST }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS8},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x88,0xf8,CRW }}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS16},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM16},3, {{0x1f,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM8},2, {{0x17,0xff,0},{0x00,0x00,IMM8 }}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,RN},2, {{0xa0,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{140,'b','E','I','E',O_BTST|O_BYTE,"btst.b",2,{IMM4,RN},2, {{0xa0,0xf8,RN },{0xf0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,RN},2, {{0xa0,0xf8,RN },{0x48,0xf8,RS }}}, +{140,'b','E','S','E',O_BTST|O_BYTE,"btst.b",2,{RS,RN},2, {{0xa0,0xf8,RN },{0x78,0xf8,RS }}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x13,0xff,0}}}, +{148,'b','E','I','E',O_BSET|O_WORD,"bset.w",2,{IMM4,RN},2, {{0xa8,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{139,'b','E','I','E',O_BTST|O_WORD,"btst.w",2,{IMM4,RN},2, {{0xa8,0xf8,RN },{0xf0,0xf0,IMM4 }}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x13,0xff,0}}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x13,0xff,0}}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x13,0xff,0}}}, +{139,'b','E','S','E',O_BTST|O_WORD,"btst.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x78,0xf8,RS }}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x13,0xff,0}}}, +{140,'b','E','I','E',O_BTST|O_BYTE,"btst.b",2,{IMM4,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xf0,0xf0,IMM4 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},{0xa0,0xf8,RD }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x20,0xf8,RD }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{209,'s','I','S','S',O_ANDC|O_WORD,"andc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x58,0xf8,CRW }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{161,'b','E','I','E',O_BNOT|O_WORD,"bnot.w",2,{IMM4,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xe0,0xf0,IMM4 }}}, +{221,'a','I','E','E',O_ADD|O_WORD,"add:q.w",2,{QIM,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x28,0xf8,RD }}}, +{157,'-','!','!','!',O_BPT|O_UNSZ,"bpt",0,{0,0},1, {{0x0b,0xff,0}}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xd0,0xf0,IMM4 }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x50,0xf8,RD }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x58,0xf8,RS }}}, +{161,'b','E','S','E',O_BNOT|O_WORD,"bnot.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x68,0xf8,RS }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xa0,0xf8,RD }}}, +{204,'b','E','I','E',O_BCLR|O_BYTE,"bclr.b",2,{IMM4,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xd0,0xf0,IMM4 }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x20,0xf8,RD }}}, +{219,'-','E','D','D',O_ADDS|O_BYTE,"adds.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{213,'m','E','D','D',O_AND|O_BYTE,"and.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{204,'b','E','S','E',O_BCLR|O_BYTE,"bclr.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x58,0xf8,RS }}}, +{216,'a','E','D','D',O_ADDX|O_BYTE,"addx.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xd0,0xf0,IMM4 }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x58,0xf8,RS }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{155,'-','B','!','!',O_BRA|O_BYTE,"bra.b",1,{PCREL8,0},2, {{0x20,0xff,0},{0x00,0x00,PCREL8 }}}, +{162,'b','E','I','E',O_BNOT|O_BYTE,"bnot.b",2,{IMM4,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xe0,0xf0,IMM4 }}}, +{222,'a','I','E','E',O_ADD|O_BYTE,"add:q.b",2,{QIM,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x08,0xf8,QIM }}}, +{162,'b','E','S','E',O_BNOT|O_BYTE,"bnot.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x68,0xf8,RS }}}, +{161,'b','E','I','E',O_BNOT|O_WORD,"bnot.w",2,{IMM4,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xe0,0xf0,IMM4 }}}, +{221,'a','I','E','E',O_ADD|O_WORD,"add:q.w",2,{QIM,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x08,0xf8,QIM }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x20,0xf8,RD }}}, +{161,'b','E','S','E',O_BNOT|O_WORD,"bnot.w",2,{RS,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x68,0xf8,RS }}}, +{152,'-','B','!','!',O_BRN|O_BYTE,"brn.b",1,{PCREL8,0},2, {{0x21,0xff,0},{0x00,0x00,PCREL8 }}}, +{186,'-','B','!','!',O_BHI|O_BYTE,"bhi.b",1,{PCREL8,0},2, {{0x22,0xff,0},{0x00,0x00,PCREL8 }}}, +{174,'-','B','!','!',O_BLS|O_BYTE,"bls.b",1,{PCREL8,0},2, {{0x23,0xff,0},{0x00,0x00,PCREL8 }}}, +{207,'-','B','!','!',O_BCC|O_BYTE,"bcc.b",1,{PCREL8,0},2, {{0x24,0xff,0},{0x00,0x00,PCREL8 }}}, +{201,'-','B','!','!',O_BCS|O_BYTE,"bcs.b",1,{PCREL8,0},2, {{0x25,0xff,0},{0x00,0x00,PCREL8 }}}, +{165,'-','B','!','!',O_BNE|O_BYTE,"bne.b",1,{PCREL8,0},2, {{0x26,0xff,0},{0x00,0x00,PCREL8 }}}, +{198,'-','B','!','!',O_BEQ|O_BYTE,"beq.b",1,{PCREL8,0},2, {{0x27,0xff,0},{0x00,0x00,PCREL8 }}}, +{159,'-','B','!','!',O_BPL|O_BYTE,"bpl.b",1,{PCREL8,0},2, {{0x2a,0xff,0},{0x00,0x00,PCREL8 }}}, +{168,'-','B','!','!',O_BMI|O_BYTE,"bmi.b",1,{PCREL8,0},2, {{0x2b,0xff,0},{0x00,0x00,PCREL8 }}}, +{192,'-','B','!','!',O_BGE|O_BYTE,"bge.b",1,{PCREL8,0},2, {{0x2c,0xff,0},{0x00,0x00,PCREL8 }}}, +{171,'-','B','!','!',O_BLT|O_BYTE,"blt.b",1,{PCREL8,0},2, {{0x2d,0xff,0},{0x00,0x00,PCREL8 }}}, +{189,'-','B','!','!',O_BGT|O_BYTE,"bgt.b",1,{PCREL8,0},2, {{0x2e,0xff,0},{0x00,0x00,PCREL8 }}}, +{180,'-','B','!','!',O_BLE|O_BYTE,"ble.b",1,{PCREL8,0},2, {{0x2f,0xff,0},{0x00,0x00,PCREL8 }}}, +{154,'-','B','!','!',O_BRA|O_WORD,"bra.w",1,{PCREL16,0},3, {{0x30,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{151,'-','B','!','!',O_BRN|O_WORD,"brn.w",1,{PCREL16,0},3, {{0x31,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{185,'-','B','!','!',O_BHI|O_WORD,"bhi.w",1,{PCREL16,0},3, {{0x32,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{173,'-','B','!','!',O_BLS|O_WORD,"bls.w",1,{PCREL16,0},3, {{0x33,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{206,'-','B','!','!',O_BCC|O_WORD,"bcc.w",1,{PCREL16,0},3, {{0x34,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{200,'-','B','!','!',O_BCS|O_WORD,"bcs.w",1,{PCREL16,0},3, {{0x35,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{164,'-','B','!','!',O_BNE|O_WORD,"bne.w",1,{PCREL16,0},3, {{0x36,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{197,'-','B','!','!',O_BEQ|O_WORD,"beq.w",1,{PCREL16,0},3, {{0x37,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{158,'-','B','!','!',O_BPL|O_WORD,"bpl.w",1,{PCREL16,0},3, {{0x3a,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{167,'-','B','!','!',O_BMI|O_WORD,"bmi.w",1,{PCREL16,0},3, {{0x3b,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{191,'-','B','!','!',O_BGE|O_WORD,"bge.w",1,{PCREL16,0},3, {{0x3c,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{170,'-','B','!','!',O_BLT|O_WORD,"blt.w",1,{PCREL16,0},3, {{0x3d,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{188,'-','B','!','!',O_BGT|O_WORD,"bgt.w",1,{PCREL16,0},3, {{0x3e,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{179,'-','B','!','!',O_BLE|O_WORD,"ble.w",1,{PCREL16,0},3, {{0x3f,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +/* +RN,RD 'm','E','D','D' +CRB,RN 's','C','!','E' +RN,RD 'm','E','D','D' +RNDEC,RD 'm','E','D','D' +CRB,RNDEC 's','C','!','E' +RNDEC,RD 'm','E','D','D' +RNINC,RD 'm','E','D','D' +CRB,RNINC 's','C','!','E' +RNINC,RD 'm','E','D','D' +RNIND,RD 'm','E','D','D' +CRB,RNIND 's','C','!','E' +RNIND,RD 'm','E','D','D' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD 'm','E','D','D' +CRB,RNIND_D8 's','C','!','E' +RNIND_D8,RD 'm','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,RD 'm','E','D','D' +CRB,RNIND_D16 's','C','!','E' +RNIND_D16,RD 'm','E','D','D' +RN,RD 'm','E','D','D' +RNDEC,RD 'm','E','D','D' +RNIND,RD 'm','E','D','D' +RNINC,RD 'm','E','D','D' +RNIND_D8,RD 'm','E','D','D' +ABS8,RD 'm','E','D','D' +IMM16,RD 'm','E','D','D' +ABS16,RD 'm','E','D','D' +RNIND_D16,RD 'm','E','D','D' +RN,RD 'a','E','D','D' +RS,RD '-','X','!','!' +RN,0 'a','E','!','!' +RS,RD '-','X','!','!' +RN,0 'a','E','!','!' +RNDEC,RD 'a','E','D','D' +RNDEC,0 'a','E','!','!' +RNDEC,RD 'a','E','D','D' +RNDEC,0 'a','E','!','!' +RNINC,RD 'a','E','D','D' +RNINC,0 'a','E','!','!' +RNINC,0 'a','E','!','!' +RNIND,RD 'a','E','D','D' +RNIND,0 'a','E','!','!' +RNIND,RD 'a','E','D','D' +RNIND,0 'a','E','!','!' +RNIND_D8,0 'a','E','!','!' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,0 'a','E','!','!' +RNIND_D16,0 'a','E','!','!' +RNIND_D16,RD 'a','E','D','D' +RN,0 'a','E','!','!' +RNIND,0 'a','E','!','!' +RNDEC,0 'a','E','!','!' +RNINC,0 'a','E','!','!' +ABS8,0 'a','E','!','!' +RNIND_D8,0 'a','E','!','!' +RD,0 'm','D','!','D' +ABS16,0 'a','E','!','!' +RNIND_D16,0 'a','E','!','!' +RN,0 's','E','!','E' +RN,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +RNDEC,0 's','E','!','E' +RNDEC,RD 'a','E','D','D' +RNINC,0 's','E','!','E' +RNINC,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +RNIND,0 's','E','!','E' +RNIND,RD 'a','E','D','D' +RNIND_D8,0 's','E','!','E' +RN,0 's','E','!','E' +RNIND,0 's','E','!','E' +RNINC,0 's','E','!','E' +RNDEC,0 's','E','!','E' +IMM8,0 's','E','!','E' +ABS8,0 's','E','!','E' +RNIND_D8,0 's','E','!','E' +ABS16,0 's','E','!','E' +RNIND_D16,0 's','E','!','E' +RNIND_D8,RD '-','E','D','D' +RD,0 'm','D','!','D' +RNIND_D16,RD '-','E','D','D' +RNIND_D16,0 's','E','!','E' +IMM16,0 'a','E','!','!' +RN,RD '-','E','D','D' +RN,RD 'a','E','D','D' +RN,RD '-','E','D','D' +RNDEC,RD '-','E','D','D' +RNDEC,RD 'a','E','D','D' +RNDEC,RD '-','E','D','D' +RNINC,RD '-','E','D','D' +RNINC,RD 'a','E','D','D' +RNINC,RD '-','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD '-','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,RD '-','E','D','D' +RN,RD 'a','E','D','D' +RNDEC,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' 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+PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RNDEC 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +RS,RNDEC 'b','E','S','E' +RNDEC,0 'c','!','!','E' +IMM4,RNINC 'b','E','I','E' +RS,RNINC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +RS,RNINC 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +RNIND_D8,0 'c','!','!','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM16,0 'c','!','!','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +ABS8,0 'c','!','!','E' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +ABS16,0 'c','!','!','E' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +ABS16,0 'c','!','!','E' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RN 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,ABS16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RS,ABS16 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNDEC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +RN,0 'c','!','!','E' +IMM4,RNDEC 'b','E','I','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +RS,RNINC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +RS,RNINC 'b','E','S','E' +RNINC,0 'c','!','!','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RNIND,0 'c','!','!','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +PCREL8,0 '-','B','!','!' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +IMM4,RN 'b','E','I','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +IMM4,RNDEC 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +IMM4,ABS16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RS,ABS16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +IMM4,RN 'b','E','I','E' +IMM4,RN 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +QIM,RN 'a','I','E','E' +RN,RD '-','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RN,RD 'a','E','D','D' +RN,RD 'm','E','D','D' +RS,RN 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +RN,RD 'a','E','D','D' +IMM4,RN 'b','E','I','E' +IMM4,RN 'b','E','I','E' +QIM,RN 'a','I','E','E' +RN,RD 'a','E','D','D' +RN,RD '-','E','D','D' +RN,RD 'm','E','D','D' +RS,RN 'b','E','S','E' +RS,RN 'b','E','S','E' +RN,RD 'a','E','D','D' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNDEC 'b','E','I','E' +QIM,RNDEC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +RNDEC,RD '-','E','D','D' +RNDEC,RD 'm','E','D','D' +RS,RNDEC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +RNDEC,RD 'a','E','D','D' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNDEC 'b','E','I','E' +QIM,RNDEC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +RNDEC,RD '-','E','D','D' +RNDEC,RD 'm','E','D','D' +RS,RNDEC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +RNDEC,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNINC,RD 'm','E','D','D' +IMM4,RNINC 'b','E','I','E' +RS,RN 'b','E','S','E' +RS,RNIND 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +IMM4,RN 'b','E','I','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNINC,RD '-','E','D','D' +RS,RNINC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +QIM,RNINC 'a','I','E','E' +RS,RNINC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNINC,RD 'a','E','D','D' +IMM4,RNINC 'b','E','I','E' +RNINC,RD 'a','E','D','D' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RNINC 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +IMM4,RNIND 'b','E','I','E' +PCREL8,0 '-','B','!','!' +RNINC,RD 'a','E','D','D' +PCREL16,0 '-','B','!','!' +RNINC,RD '-','E','D','D' +RS,RNINC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNINC,RD 'm','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +QIM,RNINC 'a','I','E','E' +QIM,RNIND 'a','I','E','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNIND,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNIND,RD 'm','E','D','D' +RS,RNIND 'b','E','S','E' +RS,RNIND 'b','E','S','E' +RNIND,RD 'a','E','D','D' +IMM4,RNIND 'b','E','I','E' +IMM4,RNIND 'b','E','I','E' +QIM,RNIND 'a','I','E','E' +RNIND,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +RNIND,RD 'm','E','D','D' +RS,RNIND 'b','E','S','E' +RS,RNIND 'b','E','S','E' +RNIND,RD 'a','E','D','D' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,RNIND_D8 'b','E','I','E' +QIM,RNIND_D8 'a','I','E','E' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD '-','E','D','D' +RNIND_D8,RD 'm','E','D','D' +RS,RNIND_D8 'b','E','S','E' +RS,RNIND_D8 'b','E','S','E' +RNIND_D8,RD 'a','E','D','D' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,RNIND_D8 'b','E','I','E' +QIM,RNIND_D8 'a','I','E','E' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD '-','E','D','D' +RNIND_D8,RD 'm','E','D','D' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +QIM,RNIND_D16 'a','I','E','E' +RS,RNIND_D16 'b','E','S','E' +RS,RN 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +IMM4,RN 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,ABS16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RS,ABS16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +RNIND_D16,RD 'a','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +IMM8,CRB 's','I','S','S' +IMM16,CRW 's','I','S','S' +RNIND_D8,RD 'a','E','D','D' +IMM4,RNIND_D16 'b','E','I','E' +RNIND_D16,RD '-','E','D','D' +RNIND_D16,RD 'm','E','D','D' +RS,RNIND_D16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +IMM4,RNIND_D16 'b','E','I','E' +QIM,RNIND_D16 'a','I','E','E' +RNIND_D16,RD '-','E','D','D' +RNIND_D16,RD 'm','E','D','D' +RS,RNIND_D16 'b','E','S','E' +RS,RNIND_D16 'b','E','S','E' +RNIND_D16,RD 'a','E','D','D' +IMM8,RD 'a','E','D','D' +IMM8,RD '-','E','D','D' +IMM8,RD 'm','E','D','D' +IMM8,CRB 's','I','S','S' +IMM8,RD 'a','E','D','D' +RN,RD 'm','E','D','D' +RNDEC,RD 'm','E','D','D' +RNINC,RD 'm','E','D','D' +RNIND,RD 'm','E','D','D' +ABS8,RD 'm','E','D','D' +RNIND_D8,RD 'm','E','D','D' +IMM16,RD 'm','E','D','D' +ABS16,RD 'm','E','D','D' +RNIND_D16,RD 'm','E','D','D' +IMM4,ABS8 'b','E','I','E' +IMM4,ABS8 'b','E','I','E' +QIM,ABS8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +ABS8,RD '-','E','D','D' +ABS8,RD 'm','E','D','D' +RS,ABS8 'b','E','S','E' +RS,ABS8 'b','E','S','E' +ABS8,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +IMM16,RD '-','E','D','D' +IMM16,RD 'm','E','D','D' +IMM16,CRW 's','I','S','S' +IMM16,RD 'a','E','D','D' +IMM4,ABS8 'b','E','I','E' +QIM,ABS8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +ABS8,RD '-','E','D','D' +RN,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +RNDEC,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +0,0 '-','!','!','!' +IMM4,ABS8 'b','E','I','E' +ABS8,RD 'm','E','D','D' +RS,ABS8 'b','E','S','E' +RS,ABS8 'b','E','S','E' +ABS8,RD 'a','E','D','D' +IMM4,ABS16 'b','E','I','E' +ABS16,RD 'a','E','D','D' +ABS16,RD '-','E','D','D' +ABS16,RD 'm','E','D','D' +RS,ABS16 'b','E','S','E' +ABS16,RD 'a','E','D','D' +IMM4,ABS16 'b','E','I','E' +ABS16,RD '-','E','D','D' +ABS16,RD 'm','E','D','D' +RS,ABS16 'b','E','S','E' +ABS16,RD 'a','E','D','D' +PCREL8,0 '-','B','!','!' +RN,RD '-','E','D','D' +RNIND,RD '-','E','D','D' +RNINC,RD '-','E','D','D' +RNDEC,RD '-','E','D','D' +ABS8,RD '-','E','D','D' +RNIND_D8,RD '-','E','D','D' +ABS16,RD '-','E','D','D' +IMM16,RD '-','E','D','D' +RNIND_D16,RD '-','E','D','D' +IMM4,ABS16 'b','E','I','E' +QIM,ABS16 'a','I','E','E' +RS,ABS16 'b','E','S','E' +IMM4,ABS16 'b','E','I','E' +QIM,ABS16 'a','I','E','E' +ABS16,RD 'a','E','D','D' +RS,ABS16 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +QIM,RN 'a','I','E','E' +QIM,RNDEC 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +QIM,RNIND 'a','I','E','E' +QIM,ABS8 'a','I','E','E' +QIM,RNIND_D8 'a','I','E','E' +QIM,ABS16 'a','I','E','E' +QIM,RNIND_D16 'a','I','E','E' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RN,RD 'a','E','D','D' +RNDEC,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +QIM,RN 'a','I','E','E' +QIM,RNIND 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +QIM,RNDEC 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +RNIND,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +QIM,ABS8 'a','I','E','E' +QIM,RNIND_D8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +QIM,RNIND_D16 'a','I','E','E' +IMM16,RD 'a','E','D','D' +QIM,ABS16 'a','I','E','E' +RNIND_D16,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +QIM,RN 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +QIM,RNIND 'a','I','E','E' +RNINC,RD 'a','E','D','D' +QIM,RNDEC 'a','I','E','E' +RNIND,RD 'a','E','D','D' +QIM,RNIND_D8 'a','I','E','E' +IMM8,RD 'a','E','D','D' +QIM,ABS8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +QIM,RNIND_D16 'a','I','E','E' +QIM,ABS16 'a','I','E','E' +ABS16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +QIM,RN 'a','I','E','E' +QIM,RNDEC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +QIM,RNIND 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +QIM,ABS8 'a','I','E','E' +QIM,RNIND_D8 'a','I','E','E' +RNIND_D8,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +QIM,RNIND_D16 'a','I','E','E' +IMM16,RD 'a','E','D','D' +QIM,ABS16 'a','I','E','E' +RNIND_D16,RD 'a','E','D','D' +*/ +{0,0,0,0,0,0,"",0,{0,0},0,{}}} +#endif +; +#endif diff --git a/opcodes/hppa-dis.c b/opcodes/hppa-dis.c new file mode 100644 index 0000000..d9ab9dd --- /dev/null +++ b/opcodes/hppa-dis.c @@ -0,0 +1,1201 @@ +/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c. + Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. + + Contributed by the Center for Software Science at the + University of Utah (pa-gdb-bugs@cs.utah.edu). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "libhppa.h" +#include "opcode/hppa.h" + +/* Integer register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const reg_names[] = + {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", + "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1", + "sp", "r31"}; + +/* Floating point register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const fp_reg_names[] = + {"fpsr", "fpe2", "fpe4", "fpe6", + "fr4", "fr5", "fr6", "fr7", "fr8", + "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", + "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"}; + +typedef unsigned int CORE_ADDR; + +/* Get at various relevent fields of an instruction word. */ + +#define MASK_5 0x1f +#define MASK_10 0x3ff +#define MASK_11 0x7ff +#define MASK_14 0x3fff +#define MASK_16 0xffff +#define MASK_21 0x1fffff + +/* These macros get bit fields using HP's numbering (MSB = 0) */ + +#define GET_FIELD(X, FROM, TO) \ + ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) + +#define GET_BIT(X, WHICH) \ + GET_FIELD (X, WHICH, WHICH) + +/* Some of these have been converted to 2-d arrays because they + consume less storage this way. If the maintenance becomes a + problem, convert them back to const 1-d pointer arrays. */ +static const char *const control_reg[] = { + "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", + "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", + "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr", + "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3", + "tr4", "tr5", "tr6", "tr7" +}; + +static const char *const compare_cond_names[] = { + "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od", + ",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev" +}; +static const char *const compare_cond_64_names[] = { + "", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od", + ",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev" +}; +static const char *const cmpib_cond_64_names[] = { + ",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>" +}; +static const char *const add_cond_names[] = { + "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od", + ",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev" +}; +static const char *const add_cond_64_names[] = { + "", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od", + ",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev" +}; +static const char *const wide_add_cond_names[] = { + "", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=", + ",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>" +}; +static const char *const logical_cond_names[] = { + "", ",=", ",<", ",<=", 0, 0, 0, ",od", + ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"}; +static const char *const logical_cond_64_names[] = { + "", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od", + ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"}; +static const char *const unit_cond_names[] = { + "", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc", + ",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc" +}; +static const char *const unit_cond_64_names[] = { + "", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc", + ",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc" +}; +static const char *const shift_cond_names[] = { + "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev" +}; +static const char *const shift_cond_64_names[] = { + "", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev" +}; +static const char *const bb_cond_64_names[] = { + ",*<", ",*>=" +}; +static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"}; +static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"}; +static const char *const short_bytes_compl_names[] = { + "", ",b,m", ",e", ",e,m" +}; +static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"}; +static const char *const float_comp_names[] = +{ + ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>", + ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>", + ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<", + ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true" +}; +static const char *const signed_unsigned_names[] = {",u", ",s"}; +static const char *const mix_half_names[] = {",l", ",r"}; +static const char *const saturation_names[] = {",us", ",ss", 0, ""}; +static const char *const read_write_names[] = {",r", ",w"}; +static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" }; + +/* For a bunch of different instructions form an index into a + completer name table. */ +#define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ + GET_FIELD (insn, 18, 18) << 1) + +#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ + (GET_FIELD ((insn), 19, 19) ? 8 : 0)) + +static void fput_reg PARAMS ((unsigned int, disassemble_info *)); +static void fput_fp_reg PARAMS ((unsigned int, disassemble_info *)); +static void fput_fp_reg_r PARAMS ((unsigned int, disassemble_info *)); +static void fput_creg PARAMS ((unsigned int, disassemble_info *)); +static void fput_const PARAMS ((unsigned int, disassemble_info *)); +static int extract_3 PARAMS ((unsigned int)); +static int extract_5_load PARAMS ((unsigned int)); +static int extract_5_store PARAMS ((unsigned int)); +static unsigned extract_5r_store PARAMS ((unsigned int)); +static unsigned extract_5R_store PARAMS ((unsigned int)); +static unsigned extract_10U_store PARAMS ((unsigned int)); +static unsigned extract_5Q_store PARAMS ((unsigned int)); +static int extract_11 PARAMS ((unsigned int)); +static int extract_14 PARAMS ((unsigned int)); +static int extract_16 PARAMS ((unsigned int)); +static int extract_21 PARAMS ((unsigned int)); +static int extract_12 PARAMS ((unsigned int)); +static int extract_17 PARAMS ((unsigned int)); +static int extract_22 PARAMS ((unsigned int)); + +/* Utility function to print registers. Put these first, so gcc's function + inlining can do its stuff. */ + +#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR) + +static void +fput_reg (reg, info) + unsigned reg; + disassemble_info *info; +{ + (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0"); +} + +static void +fput_fp_reg (reg, info) + unsigned reg; + disassemble_info *info; +{ + (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0"); +} + +static void +fput_fp_reg_r (reg, info) + unsigned reg; + disassemble_info *info; +{ + /* Special case floating point exception registers. */ + if (reg < 4) + (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1); + else + (*info->fprintf_func) (info->stream, "%sR", reg ? fp_reg_names[reg] + : "fr0"); +} + +static void +fput_creg (reg, info) + unsigned reg; + disassemble_info *info; +{ + (*info->fprintf_func) (info->stream, control_reg[reg]); +} + +/* Print constants with sign. */ + +static void +fput_const (num, info) + unsigned num; + disassemble_info *info; +{ + if ((int)num < 0) + (*info->fprintf_func) (info->stream, "-%x", -(int)num); + else + (*info->fprintf_func) (info->stream, "%x", num); +} + +/* Routines to extract various sized constants out of hppa + instructions. */ + +/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */ +static int +extract_3 (word) + unsigned word; +{ + return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17); +} + +static int +extract_5_load (word) + unsigned word; +{ + return low_sign_extend (word >> 16 & MASK_5, 5); +} + +/* Extract the immediate field from a st{bhw}s instruction. */ +static int +extract_5_store (word) + unsigned word; +{ + return low_sign_extend (word & MASK_5, 5); +} + +/* Extract the immediate field from a break instruction. */ +static unsigned +extract_5r_store (word) + unsigned word; +{ + return (word & MASK_5); +} + +/* Extract the immediate field from a {sr}sm instruction. */ +static unsigned +extract_5R_store (word) + unsigned word; +{ + return (word >> 16 & MASK_5); +} + +/* Extract the 10 bit immediate field from a {sr}sm instruction. */ +static unsigned +extract_10U_store (word) + unsigned word; +{ + return (word >> 16 & MASK_10); +} + +/* Extract the immediate field from a bb instruction. */ +static unsigned +extract_5Q_store (word) + unsigned word; +{ + return (word >> 21 & MASK_5); +} + +/* Extract an 11 bit immediate field. */ +static int +extract_11 (word) + unsigned word; +{ + return low_sign_extend (word & MASK_11, 11); +} + +/* Extract a 14 bit immediate field. */ +static int +extract_14 (word) + unsigned word; +{ + return low_sign_extend (word & MASK_14, 14); +} + +/* Extract a 16 bit immediate field (PA2.0 wide only). */ +static int +extract_16 (word) + unsigned word; +{ + int m15, m0, m1; + m0 = GET_BIT (word, 16); + m1 = GET_BIT (word, 17); + m15 = GET_BIT (word, 31); + word = (word >> 1) & 0x1fff; + word = word | (m15 << 15) | ((m15 ^ m0) << 14) | ((m15 ^ m1) << 13); + return sign_extend (word, 16); +} + +/* Extract a 21 bit constant. */ + +static int +extract_21 (word) + unsigned word; +{ + int val; + + word &= MASK_21; + word <<= 11; + val = GET_FIELD (word, 20, 20); + val <<= 11; + val |= GET_FIELD (word, 9, 19); + val <<= 2; + val |= GET_FIELD (word, 5, 6); + val <<= 5; + val |= GET_FIELD (word, 0, 4); + val <<= 2; + val |= GET_FIELD (word, 7, 8); + return sign_extend (val, 21) << 11; +} + +/* Extract a 12 bit constant from branch instructions. */ + +static int +extract_12 (word) + unsigned word; +{ + return sign_extend (GET_FIELD (word, 19, 28) | + GET_FIELD (word, 29, 29) << 10 | + (word & 0x1) << 11, 12) << 2; +} + +/* Extract a 17 bit constant from branch instructions, returning the + 19 bit signed value. */ + +static int +extract_17 (word) + unsigned word; +{ + return sign_extend (GET_FIELD (word, 19, 28) | + GET_FIELD (word, 29, 29) << 10 | + GET_FIELD (word, 11, 15) << 11 | + (word & 0x1) << 16, 17) << 2; +} + +static int +extract_22 (word) + unsigned word; +{ + return sign_extend (GET_FIELD (word, 19, 28) | + GET_FIELD (word, 29, 29) << 10 | + GET_FIELD (word, 11, 15) << 11 | + GET_FIELD (word, 6, 10) << 16 | + (word & 0x1) << 21, 22) << 2; +} + +/* Print one instruction. */ +int +print_insn_hppa (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + bfd_byte buffer[4]; + unsigned int insn, i; + + { + int status = + (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + insn = bfd_getb32 (buffer); + + for (i = 0; i < NUMOPCODES; ++i) + { + const struct pa_opcode *opcode = &pa_opcodes[i]; + if ((insn & opcode->mask) == opcode->match) + { + register const char *s; +#ifndef BFD64 + if (opcode->arch == pa20w) + continue; +#endif + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + if (!strchr ("cfCY?-+nHNZFIuv", opcode->args[0])) + (*info->fprintf_func) (info->stream, " "); + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case 'x': + fput_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'a': + case 'b': + fput_reg (GET_FIELD (insn, 6, 10), info); + break; + case '^': + fput_creg (GET_FIELD (insn, 6, 10), info); + break; + case 't': + fput_reg (GET_FIELD (insn, 27, 31), info); + break; + + /* Handle floating point registers. */ + case 'f': + switch (*++s) + { + case 't': + fput_fp_reg (GET_FIELD (insn, 27, 31), info); + break; + case 'T': + if (GET_FIELD (insn, 25, 25)) + fput_fp_reg_r (GET_FIELD (insn, 27, 31), info); + else + fput_fp_reg (GET_FIELD (insn, 27, 31), info); + break; + case 'a': + if (GET_FIELD (insn, 25, 25)) + fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); + else + fput_fp_reg (GET_FIELD (insn, 6, 10), info); + break; + + /* 'fA' will not generate a space before the regsiter + name. Normally that is fine. Except that it + causes problems with xmpyu which has no FP format + completer. */ + case 'X': + fputs_filtered (" ", info); + + /* FALLTHRU */ + + case 'A': + if (GET_FIELD (insn, 24, 24)) + fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); + else + fput_fp_reg (GET_FIELD (insn, 6, 10), info); + + break; + case 'b': + if (GET_FIELD (insn, 25, 25)) + fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); + else + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'B': + if (GET_FIELD (insn, 19, 19)) + fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); + else + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'C': + { + int reg = GET_FIELD (insn, 21, 22); + reg |= GET_FIELD (insn, 16, 18) << 2; + if (GET_FIELD (insn, 23, 23) != 0) + fput_fp_reg_r (reg, info); + else + fput_fp_reg (reg, info); + break; + } + case 'i': + { + int reg = GET_FIELD (insn, 6, 10); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'j': + { + int reg = GET_FIELD (insn, 11, 15); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'k': + { + int reg = GET_FIELD (insn, 27, 31); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'l': + { + int reg = GET_FIELD (insn, 21, 25); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'm': + { + int reg = GET_FIELD (insn, 16, 20); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + + /* 'fe' will not generate a space before the register + name. Normally that is fine. Except that it + causes problems with fstw fe,y(b) which has no FP + format completer. */ + case 'E': + fputs_filtered (" ", info); + + /* FALLTHRU */ + + case 'e': + if (GET_FIELD (insn, 30, 30)) + fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); + else + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'x': + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + } + break; + + case '5': + fput_const (extract_5_load (insn), info); + break; + case 's': + (*info->fprintf_func) (info->stream, + "sr%d", GET_FIELD (insn, 16, 17)); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn)); + break; + + /* Handle completers. */ + case 'c': + switch (*++s) + { + case 'x': + (*info->fprintf_func) (info->stream, "%s", + index_compl_names[GET_COMPL (insn)]); + break; + case 'X': + (*info->fprintf_func) (info->stream, "%s ", + index_compl_names[GET_COMPL (insn)]); + break; + case 'm': + (*info->fprintf_func) (info->stream, "%s", + short_ldst_compl_names[GET_COMPL (insn)]); + break; + case 'M': + (*info->fprintf_func) (info->stream, "%s ", + short_ldst_compl_names[GET_COMPL (insn)]); + break; + case 'A': + (*info->fprintf_func) (info->stream, "%s ", + short_bytes_compl_names[GET_COMPL (insn)]); + break; + case 's': + (*info->fprintf_func) (info->stream, "%s", + short_bytes_compl_names[GET_COMPL (insn)]); + break; + case 'c': + case 'C': + switch (GET_FIELD (insn, 20, 21)) + { + case 1: + (*info->fprintf_func) (info->stream, ",bc "); + break; + case 2: + (*info->fprintf_func) (info->stream, ",sl "); + break; + default: + (*info->fprintf_func) (info->stream, " "); + } + break; + case 'd': + switch (GET_FIELD (insn, 20, 21)) + { + case 1: + (*info->fprintf_func) (info->stream, ",co "); + break; + default: + (*info->fprintf_func) (info->stream, " "); + } + break; + case 'o': + (*info->fprintf_func) (info->stream, ",o"); + break; + case 'g': + (*info->fprintf_func) (info->stream, ",gate"); + break; + case 'p': + (*info->fprintf_func) (info->stream, ",l,push"); + break; + case 'P': + (*info->fprintf_func) (info->stream, ",pop"); + break; + case 'l': + case 'L': + (*info->fprintf_func) (info->stream, ",l"); + break; + case 'w': + (*info->fprintf_func) (info->stream, "%s ", + read_write_names[GET_FIELD (insn, 25, 25)]); + break; + case 'W': + (*info->fprintf_func) (info->stream, ",w"); + break; + case 'r': + if (GET_FIELD (insn, 23, 26) == 5) + (*info->fprintf_func) (info->stream, ",r"); + break; + case 'Z': + if (GET_FIELD (insn, 26, 26)) + (*info->fprintf_func) (info->stream, ",m "); + else + (*info->fprintf_func) (info->stream, " "); + break; + case 'i': + if (GET_FIELD (insn, 25, 25)) + (*info->fprintf_func) (info->stream, ",i"); + break; + case 'z': + if (!GET_FIELD (insn, 21, 21)) + (*info->fprintf_func) (info->stream, ",z"); + break; + case 'a': + (*info->fprintf_func) + (info->stream, "%s", add_compl_names[GET_FIELD + (insn, 20, 21)]); + break; + case 'Y': + (*info->fprintf_func) + (info->stream, ",dc%s", add_compl_names[GET_FIELD + (insn, 20, 21)]); + break; + case 'y': + (*info->fprintf_func) + (info->stream, ",c%s", add_compl_names[GET_FIELD + (insn, 20, 21)]); + break; + case 'v': + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 't': + (*info->fprintf_func) (info->stream, ",tc"); + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 'B': + (*info->fprintf_func) (info->stream, ",db"); + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 'b': + (*info->fprintf_func) (info->stream, ",b"); + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 'T': + if (GET_FIELD (insn, 25, 25)) + (*info->fprintf_func) (info->stream, ",tc"); + break; + case 'S': + /* EXTRD/W has a following condition. */ + if (*(s + 1) == '?') + (*info->fprintf_func) + (info->stream, "%s", signed_unsigned_names[GET_FIELD + (insn, 21, 21)]); + else + (*info->fprintf_func) + (info->stream, "%s ", signed_unsigned_names[GET_FIELD + (insn, 21, 21)]); + break; + case 'h': + (*info->fprintf_func) + (info->stream, "%s", mix_half_names[GET_FIELD + (insn, 17, 17)]); + break; + case 'H': + (*info->fprintf_func) + (info->stream, "%s ", saturation_names[GET_FIELD + (insn, 24, 25)]); + break; + case '*': + (*info->fprintf_func) + (info->stream, ",%d%d%d%d ", + GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21), + GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25)); + break; + + case 'q': + { + int m, a; + + m = GET_FIELD (insn, 28, 28); + a = GET_FIELD (insn, 29, 29); + + if (m && !a) + fputs_filtered (",ma ", info); + else if (m && a) + fputs_filtered (",mb ", info); + else + fputs_filtered (" ", info); + break; + } + + case 'J': + { + int opc = GET_FIELD (insn, 0, 5); + + if (opc == 0x16 || opc == 0x1e) + { + if (GET_FIELD (insn, 29, 29) == 0) + fputs_filtered (",ma ", info); + else + fputs_filtered (",mb ", info); + } + else + fputs_filtered (" ", info); + break; + } + + case 'e': + { + int opc = GET_FIELD (insn, 0, 5); + + if (opc == 0x13 || opc == 0x1b) + { + if (GET_FIELD (insn, 18, 18) == 1) + fputs_filtered (",mb ", info); + else + fputs_filtered (",ma ", info); + } + else if (opc == 0x17 || opc == 0x1f) + { + if (GET_FIELD (insn, 31, 31) == 1) + fputs_filtered (",ma ", info); + else + fputs_filtered (",mb ", info); + } + else + fputs_filtered (" ", info); + + break; + } + } + break; + + /* Handle conditions. */ + case '?': + { + s++; + switch (*s) + { + case 'f': + (*info->fprintf_func) (info->stream, "%s ", + float_comp_names[GET_FIELD + (insn, 27, 31)]); + break; + + /* these four conditions are for the set of instructions + which distinguish true/false conditions by opcode + rather than by the 'f' bit (sigh): comb, comib, + addb, addib */ + case 't': + fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)], + info); + break; + case 'n': + fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 4, 4) * 8], info); + break; + case 'N': + fputs_filtered (compare_cond_64_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 2, 2) * 8], info); + break; + case 'Q': + fputs_filtered (cmpib_cond_64_names[GET_FIELD (insn, 16, 18)], + info); + break; + case '@': + fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 4, 4) * 8], info); + break; + case 's': + (*info->fprintf_func) (info->stream, "%s ", + compare_cond_names[GET_COND (insn)]); + break; + case 'S': + (*info->fprintf_func) (info->stream, "%s ", + compare_cond_64_names[GET_COND (insn)]); + break; + case 'a': + (*info->fprintf_func) (info->stream, "%s ", + add_cond_names[GET_COND (insn)]); + break; + case 'A': + (*info->fprintf_func) (info->stream, "%s ", + add_cond_64_names[GET_COND (insn)]); + break; + case 'd': + (*info->fprintf_func) (info->stream, "%s", + add_cond_names[GET_FIELD (insn, 16, 18)]); + break; + + case 'W': + (*info->fprintf_func) + (info->stream, "%s", + wide_add_cond_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 4, 4) * 8]); + break; + + case 'l': + (*info->fprintf_func) (info->stream, "%s ", + logical_cond_names[GET_COND (insn)]); + break; + case 'L': + (*info->fprintf_func) (info->stream, "%s ", + logical_cond_64_names[GET_COND (insn)]); + break; + case 'u': + (*info->fprintf_func) (info->stream, "%s ", + unit_cond_names[GET_COND (insn)]); + break; + case 'U': + (*info->fprintf_func) (info->stream, "%s ", + unit_cond_64_names[GET_COND (insn)]); + break; + case 'y': + case 'x': + case 'b': + (*info->fprintf_func) + (info->stream, "%s", + shift_cond_names[GET_FIELD (insn, 16, 18)]); + + /* If the next character in args is 'n', it will handle + putting out the space. */ + if (s[1] != 'n') + (*info->fprintf_func) (info->stream, " "); + break; + case 'X': + (*info->fprintf_func) (info->stream, "%s ", + shift_cond_64_names[GET_FIELD (insn, 16, 18)]); + break; + case 'B': + (*info->fprintf_func) + (info->stream, "%s", + bb_cond_64_names[GET_FIELD (insn, 16, 16)]); + + /* If the next character in args is 'n', it will handle + putting out the space. */ + if (s[1] != 'n') + (*info->fprintf_func) (info->stream, " "); + break; + } + break; + } + + case 'V': + fput_const (extract_5_store (insn), info); + break; + case 'r': + fput_const (extract_5r_store (insn), info); + break; + case 'R': + fput_const (extract_5R_store (insn), info); + break; + case 'U': + fput_const (extract_10U_store (insn), info); + break; + case 'B': + case 'Q': + fput_const (extract_5Q_store (insn), info); + break; + case 'i': + fput_const (extract_11 (insn), info); + break; + case 'j': + fput_const (extract_14 (insn), info); + break; + case 'k': + fput_const (extract_21 (insn), info); + break; + case '<': + case 'l': + /* 16-bit long disp., PA2.0 wide only. */ + fput_const (extract_16 (insn), info); + break; + case 'n': + if (insn & 0x2) + (*info->fprintf_func) (info->stream, ",n "); + else + (*info->fprintf_func) (info->stream, " "); + break; + case 'N': + if ((insn & 0x20) && s[1]) + (*info->fprintf_func) (info->stream, ",n "); + else if (insn & 0x20) + (*info->fprintf_func) (info->stream, ",n"); + else if (s[1]) + (*info->fprintf_func) (info->stream, " "); + break; + case 'w': + (*info->print_address_func) (memaddr + 8 + extract_12 (insn), + info); + break; + case 'W': + /* 17 bit PC-relative branch. */ + (*info->print_address_func) ((memaddr + 8 + + extract_17 (insn)), + info); + break; + case 'z': + /* 17 bit displacement. This is an offset from a register + so it gets disasssembled as just a number, not any sort + of address. */ + fput_const (extract_17 (insn), info); + break; + + case 'Z': + /* addil %r1 implicit output. */ + (*info->fprintf_func) (info->stream, "%%r1"); + break; + + case 'Y': + /* be,l %sr0,%r31 implicit output. */ + (*info->fprintf_func) (info->stream, "%%sr0,%%r31"); + break; + + case '@': + (*info->fprintf_func) (info->stream, "0"); + break; + + case '.': + (*info->fprintf_func) (info->stream, "%d", + GET_FIELD (insn, 24, 25)); + break; + case '*': + (*info->fprintf_func) (info->stream, "%d", + GET_FIELD (insn, 22, 25)); + break; + case '!': + (*info->fprintf_func) (info->stream, "%%sar"); + break; + case 'p': + (*info->fprintf_func) (info->stream, "%d", + 31 - GET_FIELD (insn, 22, 26)); + break; + case '~': + { + int num; + num = GET_FIELD (insn, 20, 20) << 5; + num |= GET_FIELD (insn, 22, 26); + (*info->fprintf_func) (info->stream, "%d", 63 - num); + break; + } + case 'P': + (*info->fprintf_func) (info->stream, "%d", + GET_FIELD (insn, 22, 26)); + break; + case 'q': + { + int num; + num = GET_FIELD (insn, 20, 20) << 5; + num |= GET_FIELD (insn, 22, 26); + (*info->fprintf_func) (info->stream, "%d", num); + break; + } + case 'T': + (*info->fprintf_func) (info->stream, "%d", + 32 - GET_FIELD (insn, 27, 31)); + break; + case '%': + { + int num; + num = (GET_FIELD (insn, 23, 23) + 1) * 32; + num -= GET_FIELD (insn, 27, 31); + (*info->fprintf_func) (info->stream, "%d", num); + break; + } + case '|': + { + int num; + num = (GET_FIELD (insn, 19, 19) + 1) * 32; + num -= GET_FIELD (insn, 27, 31); + (*info->fprintf_func) (info->stream, "%d", num); + break; + } + case '$': + fput_const (GET_FIELD (insn, 20, 28), info); + break; + case 'A': + fput_const (GET_FIELD (insn, 6, 18), info); + break; + case 'D': + fput_const (GET_FIELD (insn, 6, 31), info); + break; + case 'v': + (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25)); + break; + case 'O': + fput_const ((GET_FIELD (insn, 6,20) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case 'o': + fput_const (GET_FIELD (insn, 6, 20), info); + break; + case '2': + fput_const ((GET_FIELD (insn, 6, 22) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case '1': + fput_const ((GET_FIELD (insn, 11, 20) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case '0': + fput_const ((GET_FIELD (insn, 16, 20) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case 'u': + (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25)); + break; + case 'F': + /* if no destination completer and not before a completer + for fcmp, need a space here */ + if (s[1] == 'G' || s[1] == '?') + fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)], + info); + else + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[GET_FIELD + (insn, 19, 20)]); + break; + case 'G': + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[GET_FIELD (insn, + 17, 18)]); + break; + case 'H': + if (GET_FIELD (insn, 26, 26) == 1) + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[0]); + else + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[1]); + break; + case 'I': + /* if no destination completer and not before a completer + for fcmp, need a space here */ + if (s[1] == '?') + fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)], + info); + else + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[GET_FIELD + (insn, 20, 20)]); + break; + + case 'J': + fput_const (extract_14 (insn), info); + break; + + case '#': + { + int sign = GET_FIELD (insn, 31, 31); + int imm10 = GET_FIELD (insn, 18, 27); + int disp; + + if (sign) + disp = (-1 << 10) | imm10; + else + disp = imm10; + + disp <<= 3; + fput_const (disp, info); + break; + } + case 'K': + case 'd': + { + int sign = GET_FIELD (insn, 31, 31); + int imm11 = GET_FIELD (insn, 18, 28); + int disp; + + if (sign) + disp = (-1 << 11) | imm11; + else + disp = imm11; + + disp <<= 2; + fput_const (disp, info); + break; + } + + case '>': + case 'y': + { + /* 16-bit long disp., PA2.0 wide only. */ + int disp = extract_16 (insn); + disp &= ~3; + fput_const (disp, info); + break; + } + + case '&': + { + /* 16-bit long disp., PA2.0 wide only. */ + int disp = extract_16 (insn); + disp &= ~7; + fput_const (disp, info); + break; + } + + /* ?!? FIXME */ + case '_': + case '{': + fputs_filtered ("Disassembler botch.\n", info); + break; + + case 'm': + { + int y = GET_FIELD (insn, 16, 18); + + if (y != 1) + fput_const ((y ^ 1) - 1, info); + } + break; + + case 'h': + { + int cbit; + + cbit = GET_FIELD (insn, 16, 18); + + if (cbit > 0) + (*info->fprintf_func) (info->stream, ",%d", cbit - 1); + break; + } + + case '=': + { + int cond = GET_FIELD (insn, 27, 31); + + if (cond == 0) + fputs_filtered (" ", info); + else if (cond == 1) + fputs_filtered ("acc ", info); + else if (cond == 2) + fputs_filtered ("rej ", info); + else if (cond == 5) + fputs_filtered ("acc8 ", info); + else if (cond == 6) + fputs_filtered ("rej8 ", info); + else if (cond == 9) + fputs_filtered ("acc6 ", info); + else if (cond == 13) + fputs_filtered ("acc4 ", info); + else if (cond == 17) + fputs_filtered ("acc2 ", info); + break; + } + + case 'X': + (*info->print_address_func) ((memaddr + 8 + + extract_22 (insn)), + info); + break; + case 'L': + fputs_filtered (",%r2", info); + break; + default: + (*info->fprintf_func) (info->stream, "%c", *s); + break; + } + } + return sizeof(insn); + } + } + (*info->fprintf_func) (info->stream, "#%8x", insn); + return sizeof(insn); +} diff --git a/opcodes/i370-dis.c b/opcodes/i370-dis.c new file mode 100644 index 0000000..51c0ff1 --- /dev/null +++ b/opcodes/i370-dis.c @@ -0,0 +1,166 @@ + +/* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions + Copyright 1994, 2000 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support by Linas Vepstas + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/i370.h" + +/* This file provides several disassembler functions, all of which use + the disassembler interface defined in dis-asm.h. +*/ + +int +print_insn_i370 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + bfd_byte buffer[8]; + int status; + i370_insn_t insn; + const struct i370_opcode *opcode; + const struct i370_opcode *opcode_end; + + status = (*info->read_memory_func) (memaddr, buffer, 6, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Cast the bytes into the insn (in a host-endian indep way) */ + insn.i[0] = (buffer[0] << 24) & 0xff000000; + insn.i[0] |= (buffer[1] << 16) & 0xff0000; + insn.i[0] |= (buffer[2] << 8) & 0xff00; + insn.i[0] |= buffer[3] & 0xff; + insn.i[1] = (buffer[4] << 24) & 0xff000000; + insn.i[1] |= (buffer[5] << 16) & 0xff0000; + + /* Find the first match in the opcode table. We could speed this up + a bit by doing a binary search on the major opcode. */ + opcode_end = i370_opcodes + i370_num_opcodes; + for (opcode = i370_opcodes; opcode < opcode_end; opcode++) + { + const unsigned char *opindex; + const struct i370_operand *operand; + i370_insn_t masked; + int invalid; + + /* Mask off operands, and look for a match ... */ + masked = insn; + if (2 == opcode->len) + { + masked.i[0] >>= 16; + masked.i[0] &= 0xffff; + } + masked.i[0] &= opcode->mask.i[0]; + if (masked.i[0] != opcode->opcode.i[0]) continue; + + if (6 == opcode->len) + { + masked.i[1] &= opcode->mask.i[1]; + if (masked.i[1] != opcode->opcode.i[1]) continue; + } + + /* Found a match. adjust a tad */ + if (2 == opcode->len) + { + insn.i[0] >>= 16; + insn.i[0] &= 0xffff; + } + + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = i370_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, &invalid); + } + if (invalid) continue; + + /* The instruction is valid. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + + /* Now extract and print the operands. */ + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + long value; + + operand = i370_operands + *opindex; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, (int *) NULL); + else + { + value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1); + } + + /* Print the operand as directed by the flags. */ + if ((operand->flags & I370_OPERAND_OPTIONAL) != 0) + { + if (value) + (*info->fprintf_func) (info->stream, "(r%ld)", value); + } + else if ((operand->flags & I370_OPERAND_SBASE) != 0) + { + (*info->fprintf_func) (info->stream, "(r%ld)", value); + } + else if ((operand->flags & I370_OPERAND_INDEX) != 0) + { + if (value) + (*info->fprintf_func) (info->stream, "(r%ld,", value); + else + (*info->fprintf_func) (info->stream, "(,"); + } + else if ((operand->flags & I370_OPERAND_LENGTH) != 0) + { + (*info->fprintf_func) (info->stream, "(%ld,", value); + } + else if ((operand->flags & I370_OPERAND_BASE) != 0) + (*info->fprintf_func) (info->stream, "r%ld)", value); + else if ((operand->flags & I370_OPERAND_GPR) != 0) + (*info->fprintf_func) (info->stream, "r%ld,", value); + else if ((operand->flags & I370_OPERAND_FPR) != 0) + (*info->fprintf_func) (info->stream, "f%ld,", value); + else if ((operand->flags & I370_OPERAND_RELATIVE) != 0) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, " %ld, ", value); + + } + + return opcode->len; + + } + + + /* We could not find a match. */ + (*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]); + + return 2; +} diff --git a/opcodes/i370-opc.c b/opcodes/i370-opc.c new file mode 100644 index 0000000..376dd0e --- /dev/null +++ b/opcodes/i370-opc.c @@ -0,0 +1,959 @@ +/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list + Copyright 1994, 1999, 2000, 2001 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support by Linas Vepstas 1998, 1999 + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/i370.h" + +/* This file holds the i370 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* Local insertion and extraction functions. */ +static i370_insn_t insert_ss_b2 PARAMS (( i370_insn_t, long, const char **)); +static i370_insn_t insert_ss_d2 PARAMS (( i370_insn_t, long, const char **)); +static i370_insn_t insert_rxf_r3 PARAMS (( i370_insn_t, long, const char **)); +static long extract_ss_b2 PARAMS (( i370_insn_t, int *)); +static long extract_ss_d2 PARAMS (( i370_insn_t, int *)); +static long extract_rxf_r3 PARAMS (( i370_insn_t, int *)); + + +/* The operands table. + The fields are bits, shift, insert, extract, flags, name. + The types: + I370_OPERAND_GPR register, must name a register, must be present + I370_OPERAND_RELATIVE displacement or legnth field, must be present + I370_OPERAND_BASE base register; if present, must name a register + if absent, should take value of zero + I370_OPERAND_INDEX index register; if present, must name a register + if absent, should take value of zero + I370_OPERAND_OPTIONAL other optional operand (usuall reg?) +*/ + +const struct i370_operand i370_operands[] = +{ + /* The zero index is used to indicate the end of the list of + operands. */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, "unused" }, + + /* The R1 register field in an RR form instruction. */ +#define RR_R1 (UNUSED + 1) +#define RR_R1_MASK (0xf << 4) + { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" }, + + /* The R2 register field in an RR form instruction. */ +#define RR_R2 (RR_R1 + 1) +#define RR_R2_MASK (0xf) + { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" }, + + /* The I field in an RR form SVC-style instruction. */ +#define RR_I (RR_R2 + 1) +#define RR_I_MASK (0xff) + { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" }, + + /* The R1 register field in an RRE form instruction. */ +#define RRE_R1 (RR_I + 1) +#define RRE_R1_MASK (0xf << 4) + { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" }, + + /* The R2 register field in an RRE form instruction. */ +#define RRE_R2 (RRE_R1 + 1) +#define RRE_R2_MASK (0xf) + { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" }, + + /* The R1 register field in an RRF form instruction. */ +#define RRF_R1 (RRE_R2 + 1) +#define RRF_R1_MASK (0xf << 4) + { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" }, + + /* The R2 register field in an RRF form instruction. */ +#define RRF_R2 (RRF_R1 + 1) +#define RRF_R2_MASK (0xf) + { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" }, + + /* The R3 register field in an RRF form instruction. */ +#define RRF_R3 (RRF_R2 + 1) +#define RRF_R3_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" }, + + /* The R1 register field in an RX or RS form instruction. */ +#define RX_R1 (RRF_R3 + 1) +#define RX_R1_MASK (0xf << 20) + { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" }, + + /* The X2 index field in an RX form instruction. */ +#define RX_X2 (RX_R1 + 1) +#define RX_X2_MASK (0xf << 16) + { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"}, + + /* The B2 base field in an RX form instruction. */ +#define RX_B2 (RX_X2 + 1) +#define RX_B2_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"}, + + /* The D2 displacement field in an RX form instruction. */ +#define RX_D2 (RX_B2 + 1) +#define RX_D2_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"}, + + /* The R3 register field in an RXF form instruction. */ +#define RXF_R3 (RX_D2 + 1) +#define RXF_R3_MASK (0xf << 12) + { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" }, + + /* The D2 displacement field in an RS form instruction. */ +#define RS_D2 (RXF_R3 + 1) +#define RS_D2_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"}, + + /* The R3 register field in an RS form instruction. */ +#define RS_R3 (RS_D2 + 1) +#define RS_R3_MASK (0xf << 16) + { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" }, + + /* The B2 base field in an RS form instruction. */ +#define RS_B2 (RS_R3 + 1) +#define RS_B2_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"}, + + /* The optional B2 base field in an RS form instruction. */ + /* Note that this field will almost always be absent */ +#define RS_B2_OPT (RS_B2 + 1) +#define RS_B2_OPT_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"}, + + /* The R1 register field in an RSI form instruction. */ +#define RSI_R1 (RS_B2_OPT + 1) +#define RSI_R1_MASK (0xf << 20) + { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" }, + + /* The R3 register field in an RSI form instruction. */ +#define RSI_R3 (RSI_R1 + 1) +#define RSI_R3_MASK (0xf << 16) + { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" }, + + /* The I2 immediate field in an RSI form instruction. */ +#define RSI_I2 (RSI_R3 + 1) +#define RSI_I2_MASK (0xffff) + { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" }, + + /* The R1 register field in an RI form instruction. */ +#define RI_R1 (RSI_I2 + 1) +#define RI_R1_MASK (0xf << 20) + { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" }, + + /* The I2 immediate field in an RI form instruction. */ +#define RI_I2 (RI_R1 + 1) +#define RI_I2_MASK (0xffff) + { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" }, + + /* The I2 index field in an SI form instruction. */ +#define SI_I2 (RI_I2 + 1) +#define SI_I2_MASK (0xff << 16) + { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"}, + + /* The B1 base register field in an SI form instruction. */ +#define SI_B1 (SI_I2 + 1) +#define SI_B1_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" }, + + /* The D1 displacement field in an SI form instruction. */ +#define SI_D1 (SI_B1 + 1) +#define SI_D1_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" }, + + /* The B2 base register field in an S form instruction. */ +#define S_B2 (SI_D1 + 1) +#define S_B2_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" }, + + /* The D2 displacement field in an S form instruction. */ +#define S_D2 (S_B2 + 1) +#define S_D2_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" }, + + /* The L length field in an SS form instruction. */ +#define SS_L (S_D2 + 1) +#define SS_L_MASK (0xffff<<16) + { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" }, + + /* The B1 base register field in an SS form instruction. */ +#define SS_B1 (SS_L + 1) +#define SS_B1_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" }, + + /* The D1 displacement field in an SS form instruction. */ +#define SS_D1 (SS_B1 + 1) +#define SS_D1_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" }, + + /* The B2 base register field in an SS form instruction. */ +#define SS_B2 (SS_D1 + 1) +#define SS_B2_MASK (0xf << 12) + { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" }, + + /* The D2 displacement field in an SS form instruction. */ +#define SS_D2 (SS_B2 + 1) +#define SS_D2_MASK (0xfff) + { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" }, + + +}; + +/* The functions used to insert and extract complicated operands. */ + +/*ARGSUSED*/ +static i370_insn_t +insert_ss_b2 (insn, value, errmsg) + i370_insn_t insn; + long value; + const char **errmsg ATTRIBUTE_UNUSED; +{ + insn.i[1] |= (value & 0xf) << 28; + return insn; +} + +static i370_insn_t +insert_ss_d2 (insn, value, errmsg) + i370_insn_t insn; + long value; + const char **errmsg ATTRIBUTE_UNUSED; +{ + insn.i[1] |= (value & 0xfff) << 16; + return insn; +} + +static i370_insn_t +insert_rxf_r3 (insn, value, errmsg) + i370_insn_t insn; + long value; + const char **errmsg ATTRIBUTE_UNUSED; +{ + insn.i[1] |= (value & 0xf) << 28; + return insn; +} + +static long +extract_ss_b2 (insn, invalid) + i370_insn_t insn; + int *invalid ATTRIBUTE_UNUSED; +{ + return (insn.i[1] >>28) & 0xf; +} + +static long +extract_ss_d2 (insn, invalid) + i370_insn_t insn; + int *invalid ATTRIBUTE_UNUSED; +{ + return (insn.i[1] >>16) & 0xfff; +} + +static long +extract_rxf_r3 (insn, invalid) + i370_insn_t insn; + int *invalid ATTRIBUTE_UNUSED; +{ + return (insn.i[1] >>28) & 0xf; +} + + +/* Macros used to form opcodes. */ + +/* The short-instruction opcode. */ +#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8) +#define OPS_MASK OPS (0xff) + +/* the extended instruction opcode */ +#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24) +#define XOPS_MASK XOPS (0xff) + +/* the S instruction opcode */ +#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16) +#define SOPS_MASK SOPS (0xffff) + +/* the E instruction opcode */ +#define EOPS(x) (((unsigned short)(x)) & 0xffff) +#define EOPS_MASK EOPS (0xffff) + +/* the RI instruction opcode */ +#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \ + ((((unsigned short)(x)) & 0x00f) << 16)) +#define ROPS_MASK ROPS (0xfff) + +/* --------------------------------------------------------- */ +/* An E form instruction. */ +#define E(op) (EOPS (op)) +#define E_MASK E (0xffff) + +/* An RR form instruction. */ +#define RR(op, r1, r2) \ + (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) | \ + ((((unsigned short)(r2)) & 0xf) )) + +#define RR_MASK RR (0xff, 0x0, 0x0) + +/* An SVC-style instruction. */ +#define SVC(op, i) \ + (OPS (op) | (((unsigned short)(i)) & 0xff)) + +#define SVC_MASK SVC (0xff, 0x0) + +/* An RRE form instruction. */ +#define RRE(op, r1, r2) \ + (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) | \ + ((((unsigned short)(r2)) & 0xf) )) + +#define RRE_MASK RRE (0xffff, 0x0, 0x0) + +/* An RRF form instruction. */ +#define RRF(op, r3, r1, r2) \ + (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) | \ + ((((unsigned short)(r1)) & 0xf) << 4) | \ + ((((unsigned short)(r2)) & 0xf) )) + +#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0) + +/* An RX form instruction. */ +#define RX(op, r1, x2, b2, d2) \ + (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ + ((((unsigned short)(x2)) & 0xf) << 16) | \ + ((((unsigned short)(b2)) & 0xf) << 12) | \ + ((((unsigned short)(d2)) & 0xfff))) + +#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0) + +/* An RXE form instruction high word. */ +#define RXEH(op, r1, x2, b2, d2) \ + (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ + ((((unsigned short)(x2)) & 0xf) << 16) | \ + ((((unsigned short)(b2)) & 0xf) << 12) | \ + ((((unsigned short)(d2)) & 0xfff))) + +#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0) + +/* An RXE form instruction low word. */ +#define RXEL(op) \ + ((((unsigned short)(op)) & 0xff) << 16 ) + +#define RXEL_MASK RXEL (0xff) + +/* An RXF form instruction high word. */ +#define RXFH(op, r1, x2, b2, d2) \ + (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ + ((((unsigned short)(x2)) & 0xf) << 16) | \ + ((((unsigned short)(b2)) & 0xf) << 12) | \ + ((((unsigned short)(d2)) & 0xfff))) + +#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0) + +/* An RXF form instruction low word. */ +#define RXFL(op, r3) \ + (((((unsigned short)(r3)) & 0xf) << 28 ) | \ + ((((unsigned short)(op)) & 0xff) << 16 )) + +#define RXFL_MASK RXFL (0xff, 0) + +/* An RS form instruction. */ +#define RS(op, r1, b3, b2, d2) \ + (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ + ((((unsigned short)(b3)) & 0xf) << 16) | \ + ((((unsigned short)(b2)) & 0xf) << 12) | \ + ((((unsigned short)(d2)) & 0xfff))) + +#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0) + +/* An RSI form instruction. */ +#define RSI(op, r1, r3, i2) \ + (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ + ((((unsigned short)(r3)) & 0xf) << 16) | \ + ((((unsigned short)(i2)) & 0xffff))) + +#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0) + +/* An RI form instruction. */ +#define RI(op, r1, i2) \ + (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ + ((((unsigned short)(i2)) & 0xffff))) + +#define RI_MASK RI (0xfff, 0x0, 0x0) + +/* An SI form instruction. */ +#define SI(op, i2, b1, d1) \ + (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) | \ + ((((unsigned short)(b1)) & 0xf) << 12) | \ + ((((unsigned short)(d1)) & 0xfff))) + +#define SI_MASK SI (0xff, 0x0, 0x0, 0x0) + +/* An S form instruction. */ +#define S(op, b2, d2) \ + (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \ + ((((unsigned short)(d2)) & 0xfff))) + +#define S_MASK S (0xffff, 0x0, 0x0) + +/* An SS form instruction high word. */ +#define SSH(op, l, b1, d1) \ + (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) | \ + ((((unsigned short)(b1)) & 0xf) << 12) | \ + ((((unsigned short)(d1)) & 0xfff))) + +/* An SS form instruction low word. */ +#define SSL(b2, d2) \ + ( ((((unsigned short)(b1)) & 0xf) << 28) | \ + ((((unsigned short)(d1)) & 0xfff) << 16 )) + +#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0) + +/* An SSE form instruction high word. */ +#define SSEH(op, b1, d1) \ + (SOPS(op) | ((((unsigned short)(b1)) & 0xf) << 12) | \ + ((((unsigned short)(d1)) & 0xfff))) + +/* An SSE form instruction low word. */ +#define SSEL(b2, d2) \ + ( ((((unsigned short)(b1)) & 0xf) << 28) | \ + ((((unsigned short)(d1)) & 0xfff) << 16 )) + +#define SSE_MASK SSEH (0xffff, 0x0, 0x0) + + +/* Smaller names for the flags so each entry in the opcodes table will + fit on a single line. These flags are set up so that e.g. IXA means + the insn is supported on the 370/XA or newer architecture. + Note that 370 or older obsolete insn's are not supported ... + */ +#define IBF I370_OPCODE_ESA390_BF +#define IBS I370_OPCODE_ESA390_BS +#define ICK I370_OPCODE_ESA390_CK +#define ICM I370_OPCODE_ESA390_CM +#define IFX I370_OPCODE_ESA390_FX +#define IHX I370_OPCODE_ESA390_HX +#define IIR I370_OPCODE_ESA390_IR +#define IMI I370_OPCODE_ESA390_MI +#define IPC I370_OPCODE_ESA390_PC +#define IPL I370_OPCODE_ESA390_PL +#define IQR I370_OPCODE_ESA390_QR +#define IRP I370_OPCODE_ESA390_RP +#define ISA I370_OPCODE_ESA390_SA +#define ISG I370_OPCODE_ESA390_SG +#define ISR I370_OPCODE_ESA390_SR +#define ITR I370_OPCODE_ESA390_SR +#define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390 +#define IESA I390 | I370_OPCODE_ESA370 +#define IXA IESA | I370_OPCODE_370_XA +#define I370 IXA | I370_OPCODE_370 +#define I360 I370 | I370_OPCODE_360 + + +/* The opcode table. + + The format of the opcode table is: + + NAME LEN OPCODE_HI OPCODE_LO MASK_HI MASK_LO FLAGS { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + FLAGS are flags indicated what processors support the instruction. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct i370_opcode i370_opcodes[] = { + +/* E form instructions */ +{ "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} }, + +{ "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} }, +{ "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} }, + +/* RR form instructions */ +{ "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, +{ "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, +{ "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, +{ "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} }, +{ "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, + +/* unusual RR formats */ +{ "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} }, + +/* RRE form instructions */ +{ "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} }, +{ "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} }, +{ "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} }, +{ "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, +{ "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} }, +{ "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} }, +{ "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, +{ "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} }, +{ "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} }, +{ "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, +{ "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, +{ "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, +{ "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, + +/* RRF form instructions */ +{ "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, + +/* RX form instructions */ +{ "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, + +/* RXE form instructions */ +{ "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, + +/* RXF form instructions */ +{ "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, +{ "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, +{ "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, +{ "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, + +/* RS form instructions */ +{ "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, + +/* RS form instructions with blank R3 and optional B2 (shift left/right) */ +{ "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, + +/* RSI form instructions */ +{ "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, +{ "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, + +/* RI form instructions */ +{ "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, + +/* SI form instructions */ +{ "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, +{ "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, +{ "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, + +/* S form instructions */ +{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} }, +{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} }, +{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} }, +{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} }, +{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, + +/* SS form instructions */ +{ "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, + +/* SSE form instructions */ +{ "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, +{ "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, +{ "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, +{ "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, + +/* */ +}; + +const int i370_num_opcodes = + sizeof (i370_opcodes) / sizeof (i370_opcodes[0]); + +/* The macro table. This is only used by the assembler. */ + +const struct i370_macro i370_macros[] = { +{ "b", 1, I370, "bc 15,%0" }, +{ "br", 1, I370, "bcr 15,%0" }, + +{ "nop", 1, I370, "bc 0,%0" }, +{ "nopr", 1, I370, "bcr 0,%0" }, + +{ "bh", 1, I370, "bc 2,%0" }, +{ "bhr", 1, I370, "bcr 2,%0" }, +{ "bl", 1, I370, "bc 4,%0" }, +{ "blr", 1, I370, "bcr 4,%0" }, +{ "be", 1, I370, "bc 8,%0" }, +{ "ber", 1, I370, "bcr 8,%0" }, + +{ "bnh", 1, I370, "bc 13,%0" }, +{ "bnhr", 1, I370, "bcr 13,%0" }, +{ "bnl", 1, I370, "bc 11,%0" }, +{ "bnlr", 1, I370, "bcr 11,%0" }, +{ "bne", 1, I370, "bc 7,%0" }, +{ "bner", 1, I370, "bcr 7,%0" }, + +{ "bp", 1, I370, "bc 2,%0" }, +{ "bpr", 1, I370, "bcr 2,%0" }, +{ "bm", 1, I370, "bc 4,%0" }, +{ "bmr", 1, I370, "bcr 4,%0" }, +{ "bz", 1, I370, "bc 8,%0" }, +{ "bzr", 1, I370, "bcr 8,%0" }, +{ "bo", 1, I370, "bc 1,%0" }, +{ "bor", 1, I370, "bcr 1,%0" }, + +{ "bnp", 1, I370, "bc 13,%0" }, +{ "bnpr", 1, I370, "bcr 13,%0" }, +{ "bnm", 1, I370, "bc 11,%0" }, +{ "bnmr", 1, I370, "bcr 11,%0" }, +{ "bnz", 1, I370, "bc 7,%0" }, +{ "bnzr", 1, I370, "bcr 7,%0" }, +{ "bno", 1, I370, "bc 14,%0" }, +{ "bnor", 1, I370, "bcr 14,%0" }, + +{ "sync", 0, I370, "bcr 15,0" }, + +}; + +const int i370_num_macros = + sizeof (i370_macros) / sizeof (i370_macros[0]); diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c new file mode 100644 index 0000000..d2271d8 --- /dev/null +++ b/opcodes/i386-dis.c @@ -0,0 +1,4144 @@ +/* Print i386 instructions for GDB, the GNU debugger. + Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2001 + Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) + * July 1988 + * modified by John Hassey (hassey@dg-rtp.dg.com) + * x86-64 support added by Jan Hubicka (jh@suse.cz) + */ + +/* + * The main tables describing the instructions is essentially a copy + * of the "Opcode Map" chapter (Appendix A) of the Intel 80386 + * Programmers Manual. Usually, there is a capital letter, followed + * by a small letter. The capital letter tell the addressing mode, + * and the small letter tells about the operand size. Refer to + * the Intel manual for details. + */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opintl.h" + +#define MAXLEN 20 + +#include + +#ifndef UNIXWARE_COMPAT +/* Set non-zero for broken, compatible instructions. Set to zero for + non-broken opcodes. */ +#define UNIXWARE_COMPAT 1 +#endif + +static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); +static void ckprefix PARAMS ((void)); +static const char *prefix_name PARAMS ((int, int)); +static int print_insn PARAMS ((bfd_vma, disassemble_info *)); +static void dofloat PARAMS ((int)); +static void OP_ST PARAMS ((int, int)); +static void OP_STi PARAMS ((int, int)); +static int putop PARAMS ((const char *, int)); +static void oappend PARAMS ((const char *)); +static void append_seg PARAMS ((void)); +static void OP_indirE PARAMS ((int, int)); +static void print_operand_value PARAMS ((char *, int, bfd_vma)); +static void OP_E PARAMS ((int, int)); +static void OP_G PARAMS ((int, int)); +static bfd_vma get64 PARAMS ((void)); +static bfd_signed_vma get32 PARAMS ((void)); +static bfd_signed_vma get32s PARAMS ((void)); +static int get16 PARAMS ((void)); +static void set_op PARAMS ((bfd_vma, int)); +static void OP_REG PARAMS ((int, int)); +static void OP_IMREG PARAMS ((int, int)); +static void OP_I PARAMS ((int, int)); +static void OP_I64 PARAMS ((int, int)); +static void OP_sI PARAMS ((int, int)); +static void OP_J PARAMS ((int, int)); +static void OP_SEG PARAMS ((int, int)); +static void OP_DIR PARAMS ((int, int)); +static void OP_OFF PARAMS ((int, int)); +static void OP_OFF64 PARAMS ((int, int)); +static void ptr_reg PARAMS ((int, int)); +static void OP_ESreg PARAMS ((int, int)); +static void OP_DSreg PARAMS ((int, int)); +static void OP_C PARAMS ((int, int)); +static void OP_D PARAMS ((int, int)); +static void OP_T PARAMS ((int, int)); +static void OP_Rd PARAMS ((int, int)); +static void OP_MMX PARAMS ((int, int)); +static void OP_XMM PARAMS ((int, int)); +static void OP_EM PARAMS ((int, int)); +static void OP_EX PARAMS ((int, int)); +static void OP_MS PARAMS ((int, int)); +static void OP_XS PARAMS ((int, int)); +static void OP_3DNowSuffix PARAMS ((int, int)); +static void OP_SIMD_Suffix PARAMS ((int, int)); +static void SIMD_Fixup PARAMS ((int, int)); +static void BadOp PARAMS ((void)); + +struct dis_private { + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + int orig_sizeflag; + jmp_buf bailout; +}; + +/* The opcode for the fwait instruction, which we treat as a prefix + when we can. */ +#define FWAIT_OPCODE (0x9b) + +/* Set to 1 for 64bit mode disassembly. */ +static int mode_64bit; + +/* Flags for the prefixes for the current instruction. See below. */ +static int prefixes; + +/* REX prefix the current instruction. See below. */ +static int rex; +/* Bits of REX we've already used. */ +static int rex_used; +#define REX_MODE64 8 +#define REX_EXTX 4 +#define REX_EXTY 2 +#define REX_EXTZ 1 +/* Mark parts used in the REX prefix. When we are testing for + empty prefix (for 8bit register REX extension), just mask it + out. Otherwise test for REX bit is excuse for existence of REX + only in case value is nonzero. */ +#define USED_REX(value) \ + { \ + if (value) \ + rex_used |= (rex & value) ? (value) | 0x40 : 0; \ + else \ + rex_used |= 0x40; \ + } + +/* Flags for prefixes which we somehow handled when printing the + current instruction. */ +static int used_prefixes; + +/* Flags stored in PREFIXES. */ +#define PREFIX_REPZ 1 +#define PREFIX_REPNZ 2 +#define PREFIX_LOCK 4 +#define PREFIX_CS 8 +#define PREFIX_SS 0x10 +#define PREFIX_DS 0x20 +#define PREFIX_ES 0x40 +#define PREFIX_FS 0x80 +#define PREFIX_GS 0x100 +#define PREFIX_DATA 0x200 +#define PREFIX_ADDR 0x400 +#define PREFIX_FWAIT 0x800 + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (info, addr) + struct disassemble_info *info; + bfd_byte *addr; +{ + int status; + struct dis_private *priv = (struct dis_private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + /* If we did manage to read at least one byte, then + print_insn_i386 will do something sensible. Otherwise, print + an error. We do that here because this is where we know + STATUS. */ + if (priv->max_fetched == priv->the_buffer) + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} + +#define XX NULL, 0 + +#define Eb OP_E, b_mode +#define Ev OP_E, v_mode +#define Ed OP_E, d_mode +#define indirEb OP_indirE, b_mode +#define indirEv OP_indirE, v_mode +#define Ew OP_E, w_mode +#define Ma OP_E, v_mode +#define M OP_E, 0 /* lea, lgdt, etc. */ +#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ +#define Gb OP_G, b_mode +#define Gv OP_G, v_mode +#define Gd OP_G, d_mode +#define Gw OP_G, w_mode +#define Rd OP_Rd, d_mode +#define Rm OP_Rd, m_mode +#define Ib OP_I, b_mode +#define sIb OP_sI, b_mode /* sign extened byte */ +#define Iv OP_I, v_mode +#define Iq OP_I, q_mode +#define Iv64 OP_I64, v_mode +#define Iw OP_I, w_mode +#define Jb OP_J, b_mode +#define Jv OP_J, v_mode +#define Cm OP_C, m_mode +#define Dm OP_D, m_mode +#define Td OP_T, d_mode + +#define RMeAX OP_REG, eAX_reg +#define RMeBX OP_REG, eBX_reg +#define RMeCX OP_REG, eCX_reg +#define RMeDX OP_REG, eDX_reg +#define RMeSP OP_REG, eSP_reg +#define RMeBP OP_REG, eBP_reg +#define RMeSI OP_REG, eSI_reg +#define RMeDI OP_REG, eDI_reg +#define RMrAX OP_REG, rAX_reg +#define RMrBX OP_REG, rBX_reg +#define RMrCX OP_REG, rCX_reg +#define RMrDX OP_REG, rDX_reg +#define RMrSP OP_REG, rSP_reg +#define RMrBP OP_REG, rBP_reg +#define RMrSI OP_REG, rSI_reg +#define RMrDI OP_REG, rDI_reg +#define RMAL OP_REG, al_reg +#define RMAL OP_REG, al_reg +#define RMCL OP_REG, cl_reg +#define RMDL OP_REG, dl_reg +#define RMBL OP_REG, bl_reg +#define RMAH OP_REG, ah_reg +#define RMCH OP_REG, ch_reg +#define RMDH OP_REG, dh_reg +#define RMBH OP_REG, bh_reg +#define RMAX OP_REG, ax_reg +#define RMDX OP_REG, dx_reg + +#define eAX OP_IMREG, eAX_reg +#define eBX OP_IMREG, eBX_reg +#define eCX OP_IMREG, eCX_reg +#define eDX OP_IMREG, eDX_reg +#define eSP OP_IMREG, eSP_reg +#define eBP OP_IMREG, eBP_reg +#define eSI OP_IMREG, eSI_reg +#define eDI OP_IMREG, eDI_reg +#define AL OP_IMREG, al_reg +#define AL OP_IMREG, al_reg +#define CL OP_IMREG, cl_reg +#define DL OP_IMREG, dl_reg +#define BL OP_IMREG, bl_reg +#define AH OP_IMREG, ah_reg +#define CH OP_IMREG, ch_reg +#define DH OP_IMREG, dh_reg +#define BH OP_IMREG, bh_reg +#define AX OP_IMREG, ax_reg +#define DX OP_IMREG, dx_reg +#define indirDX OP_IMREG, indir_dx_reg + +#define Sw OP_SEG, w_mode +#define Ap OP_DIR, 0 +#define Ob OP_OFF, b_mode +#define Ob64 OP_OFF64, b_mode +#define Ov OP_OFF, v_mode +#define Ov64 OP_OFF64, v_mode +#define Xb OP_DSreg, eSI_reg +#define Xv OP_DSreg, eSI_reg +#define Yb OP_ESreg, eDI_reg +#define Yv OP_ESreg, eDI_reg +#define DSBX OP_DSreg, eBX_reg + +#define es OP_REG, es_reg +#define ss OP_REG, ss_reg +#define cs OP_REG, cs_reg +#define ds OP_REG, ds_reg +#define fs OP_REG, fs_reg +#define gs OP_REG, gs_reg + +#define MX OP_MMX, 0 +#define XM OP_XMM, 0 +#define EM OP_EM, v_mode +#define EX OP_EX, v_mode +#define MS OP_MS, v_mode +#define XS OP_XS, v_mode +#define None OP_E, 0 +#define OPSUF OP_3DNowSuffix, 0 +#define OPSIMD OP_SIMD_Suffix, 0 + +#define cond_jump_flag NULL, cond_jump_mode +#define loop_jcxz_flag NULL, loop_jcxz_mode + +/* bits in sizeflag */ +#define SUFFIX_ALWAYS 4 +#define AFLAG 2 +#define DFLAG 1 + +#define b_mode 1 /* byte operand */ +#define v_mode 2 /* operand size depends on prefixes */ +#define w_mode 3 /* word operand */ +#define d_mode 4 /* double word operand */ +#define q_mode 5 /* quad word operand */ +#define x_mode 6 +#define m_mode 7 /* d_mode in 32bit, q_mode in 64bit mode. */ +#define cond_jump_mode 8 +#define loop_jcxz_mode 9 + +#define es_reg 100 +#define cs_reg 101 +#define ss_reg 102 +#define ds_reg 103 +#define fs_reg 104 +#define gs_reg 105 + +#define eAX_reg 108 +#define eCX_reg 109 +#define eDX_reg 110 +#define eBX_reg 111 +#define eSP_reg 112 +#define eBP_reg 113 +#define eSI_reg 114 +#define eDI_reg 115 + +#define al_reg 116 +#define cl_reg 117 +#define dl_reg 118 +#define bl_reg 119 +#define ah_reg 120 +#define ch_reg 121 +#define dh_reg 122 +#define bh_reg 123 + +#define ax_reg 124 +#define cx_reg 125 +#define dx_reg 126 +#define bx_reg 127 +#define sp_reg 128 +#define bp_reg 129 +#define si_reg 130 +#define di_reg 131 + +#define rAX_reg 132 +#define rCX_reg 133 +#define rDX_reg 134 +#define rBX_reg 135 +#define rSP_reg 136 +#define rBP_reg 137 +#define rSI_reg 138 +#define rDI_reg 139 + +#define indir_dx_reg 150 + +#define FLOATCODE 1 +#define USE_GROUPS 2 +#define USE_PREFIX_USER_TABLE 3 +#define X86_64_SPECIAL 4 + +#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0 + +#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0 +#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0 +#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0 +#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0 +#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0 +#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0 +#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0 +#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0 +#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0 +#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0 +#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0 +#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0 +#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0 +#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0 +#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0 +#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0 +#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0 +#define GRP10 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0 +#define GRP11 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0 +#define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0 +#define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0 +#define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0 +#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0 + +#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0 +#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0 +#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0 +#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0 +#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0 +#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0 +#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0 +#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0 +#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0 +#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0 +#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0 +#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0 +#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0 +#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0 +#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0 +#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0 +#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0 +#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0 +#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0 +#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0 +#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0 +#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0 +#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0 +#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0 +#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0 +#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0 +#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0 + +#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 + +typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag)); + +struct dis386 { + const char *name; + op_rtn op1; + int bytemode1; + op_rtn op2; + int bytemode2; + op_rtn op3; + int bytemode3; +}; + +/* Upper case letters in the instruction names here are macros. + 'A' => print 'b' if no register operands or suffix_always is true + 'B' => print 'b' if suffix_always is true + 'E' => print 'e' if 32-bit form of jcxz + 'F' => print 'w' or 'l' depending on address size prefix (loop insns) + 'H' => print ",pt" or ",pn" branch hint + 'L' => print 'l' if suffix_always is true + 'N' => print 'n' if instruction has no wait "prefix" + 'O' => print 'd', or 'o' + 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, + . or suffix_always is true. print 'q' if rex prefix is present. + 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always + . is true + 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode) + 'S' => print 'w', 'l' or 'q' if suffix_always is true + 'T' => print 'q' in 64bit mode and behave as 'P' otherwise + 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise + 'X' => print 's', 'd' depending on data16 prefix (for XMM) + 'W' => print 'b' or 'w' ("w" or "de" in intel mode) + 'Y' => 'q' if instruction has an REX 64bit overwrite prefix + + Many of the above letters print nothing in Intel mode. See "putop" + for the details. + + Braces '{' and '}', and vertical bars '|', indicate alternative + mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel + modes. In cases where there are only two alternatives, the X86_64 + instruction is reserved, and "(bad)" is printed. +*/ + +static const struct dis386 dis386[] = { + /* 00 */ + { "addB", Eb, Gb, XX }, + { "addS", Ev, Gv, XX }, + { "addB", Gb, Eb, XX }, + { "addS", Gv, Ev, XX }, + { "addB", AL, Ib, XX }, + { "addS", eAX, Iv, XX }, + { "push{T|}", es, XX, XX }, + { "pop{T|}", es, XX, XX }, + /* 08 */ + { "orB", Eb, Gb, XX }, + { "orS", Ev, Gv, XX }, + { "orB", Gb, Eb, XX }, + { "orS", Gv, Ev, XX }, + { "orB", AL, Ib, XX }, + { "orS", eAX, Iv, XX }, + { "push{T|}", cs, XX, XX }, + { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */ + /* 10 */ + { "adcB", Eb, Gb, XX }, + { "adcS", Ev, Gv, XX }, + { "adcB", Gb, Eb, XX }, + { "adcS", Gv, Ev, XX }, + { "adcB", AL, Ib, XX }, + { "adcS", eAX, Iv, XX }, + { "push{T|}", ss, XX, XX }, + { "popT|}", ss, XX, XX }, + /* 18 */ + { "sbbB", Eb, Gb, XX }, + { "sbbS", Ev, Gv, XX }, + { "sbbB", Gb, Eb, XX }, + { "sbbS", Gv, Ev, XX }, + { "sbbB", AL, Ib, XX }, + { "sbbS", eAX, Iv, XX }, + { "push{T|}", ds, XX, XX }, + { "pop{T|}", ds, XX, XX }, + /* 20 */ + { "andB", Eb, Gb, XX }, + { "andS", Ev, Gv, XX }, + { "andB", Gb, Eb, XX }, + { "andS", Gv, Ev, XX }, + { "andB", AL, Ib, XX }, + { "andS", eAX, Iv, XX }, + { "(bad)", XX, XX, XX }, /* SEG ES prefix */ + { "daa{|}", XX, XX, XX }, + /* 28 */ + { "subB", Eb, Gb, XX }, + { "subS", Ev, Gv, XX }, + { "subB", Gb, Eb, XX }, + { "subS", Gv, Ev, XX }, + { "subB", AL, Ib, XX }, + { "subS", eAX, Iv, XX }, + { "(bad)", XX, XX, XX }, /* SEG CS prefix */ + { "das{|}", XX, XX, XX }, + /* 30 */ + { "xorB", Eb, Gb, XX }, + { "xorS", Ev, Gv, XX }, + { "xorB", Gb, Eb, XX }, + { "xorS", Gv, Ev, XX }, + { "xorB", AL, Ib, XX }, + { "xorS", eAX, Iv, XX }, + { "(bad)", XX, XX, XX }, /* SEG SS prefix */ + { "aaa{|}", XX, XX, XX }, + /* 38 */ + { "cmpB", Eb, Gb, XX }, + { "cmpS", Ev, Gv, XX }, + { "cmpB", Gb, Eb, XX }, + { "cmpS", Gv, Ev, XX }, + { "cmpB", AL, Ib, XX }, + { "cmpS", eAX, Iv, XX }, + { "(bad)", XX, XX, XX }, /* SEG DS prefix */ + { "aas{|}", XX, XX, XX }, + /* 40 */ + { "inc{S|}", RMeAX, XX, XX }, + { "inc{S|}", RMeCX, XX, XX }, + { "inc{S|}", RMeDX, XX, XX }, + { "inc{S|}", RMeBX, XX, XX }, + { "inc{S|}", RMeSP, XX, XX }, + { "inc{S|}", RMeBP, XX, XX }, + { "inc{S|}", RMeSI, XX, XX }, + { "inc{S|}", RMeDI, XX, XX }, + /* 48 */ + { "dec{S|}", RMeAX, XX, XX }, + { "dec{S|}", RMeCX, XX, XX }, + { "dec{S|}", RMeDX, XX, XX }, + { "dec{S|}", RMeBX, XX, XX }, + { "dec{S|}", RMeSP, XX, XX }, + { "dec{S|}", RMeBP, XX, XX }, + { "dec{S|}", RMeSI, XX, XX }, + { "dec{S|}", RMeDI, XX, XX }, + /* 50 */ + { "pushS", RMrAX, XX, XX }, + { "pushS", RMrCX, XX, XX }, + { "pushS", RMrDX, XX, XX }, + { "pushS", RMrBX, XX, XX }, + { "pushS", RMrSP, XX, XX }, + { "pushS", RMrBP, XX, XX }, + { "pushS", RMrSI, XX, XX }, + { "pushS", RMrDI, XX, XX }, + /* 58 */ + { "popS", RMrAX, XX, XX }, + { "popS", RMrCX, XX, XX }, + { "popS", RMrDX, XX, XX }, + { "popS", RMrBX, XX, XX }, + { "popS", RMrSP, XX, XX }, + { "popS", RMrBP, XX, XX }, + { "popS", RMrSI, XX, XX }, + { "popS", RMrDI, XX, XX }, + /* 60 */ + { "pusha{P|}", XX, XX, XX }, + { "popa{P|}", XX, XX, XX }, + { "bound{S|}", Gv, Ma, XX }, + { X86_64_0 }, + { "(bad)", XX, XX, XX }, /* seg fs */ + { "(bad)", XX, XX, XX }, /* seg gs */ + { "(bad)", XX, XX, XX }, /* op size prefix */ + { "(bad)", XX, XX, XX }, /* adr size prefix */ + /* 68 */ + { "pushT", Iq, XX, XX }, + { "imulS", Gv, Ev, Iv }, + { "pushT", sIb, XX, XX }, + { "imulS", Gv, Ev, sIb }, + { "ins{b||b|}", Yb, indirDX, XX }, + { "ins{R||R|}", Yv, indirDX, XX }, + { "outs{b||b|}", indirDX, Xb, XX }, + { "outs{R||R|}", indirDX, Xv, XX }, + /* 70 */ + { "joH", Jb, XX, cond_jump_flag }, + { "jnoH", Jb, XX, cond_jump_flag }, + { "jbH", Jb, XX, cond_jump_flag }, + { "jaeH", Jb, XX, cond_jump_flag }, + { "jeH", Jb, XX, cond_jump_flag }, + { "jneH", Jb, XX, cond_jump_flag }, + { "jbeH", Jb, XX, cond_jump_flag }, + { "jaH", Jb, XX, cond_jump_flag }, + /* 78 */ + { "jsH", Jb, XX, cond_jump_flag }, + { "jnsH", Jb, XX, cond_jump_flag }, + { "jpH", Jb, XX, cond_jump_flag }, + { "jnpH", Jb, XX, cond_jump_flag }, + { "jlH", Jb, XX, cond_jump_flag }, + { "jgeH", Jb, XX, cond_jump_flag }, + { "jleH", Jb, XX, cond_jump_flag }, + { "jgH", Jb, XX, cond_jump_flag }, + /* 80 */ + { GRP1b }, + { GRP1S }, + { "(bad)", XX, XX, XX }, + { GRP1Ss }, + { "testB", Eb, Gb, XX }, + { "testS", Ev, Gv, XX }, + { "xchgB", Eb, Gb, XX }, + { "xchgS", Ev, Gv, XX }, + /* 88 */ + { "movB", Eb, Gb, XX }, + { "movS", Ev, Gv, XX }, + { "movB", Gb, Eb, XX }, + { "movS", Gv, Ev, XX }, + { "movQ", Ev, Sw, XX }, + { "leaS", Gv, M, XX }, + { "movQ", Sw, Ev, XX }, + { "popU", Ev, XX, XX }, + /* 90 */ + { "nop", XX, XX, XX }, + /* FIXME: NOP with REPz prefix is called PAUSE. */ + { "xchgS", RMeCX, eAX, XX }, + { "xchgS", RMeDX, eAX, XX }, + { "xchgS", RMeBX, eAX, XX }, + { "xchgS", RMeSP, eAX, XX }, + { "xchgS", RMeBP, eAX, XX }, + { "xchgS", RMeSI, eAX, XX }, + { "xchgS", RMeDI, eAX, XX }, + /* 98 */ + { "cW{tR||tR|}", XX, XX, XX }, + { "cR{tO||tO|}", XX, XX, XX }, + { "lcall{T|}", Ap, XX, XX }, + { "(bad)", XX, XX, XX }, /* fwait */ + { "pushfT", XX, XX, XX }, + { "popfT", XX, XX, XX }, + { "sahf{|}", XX, XX, XX }, + { "lahf{|}", XX, XX, XX }, + /* a0 */ + { "movB", AL, Ob64, XX }, + { "movS", eAX, Ov64, XX }, + { "movB", Ob64, AL, XX }, + { "movS", Ov64, eAX, XX }, + { "movs{b||b|}", Yb, Xb, XX }, + { "movs{R||R|}", Yv, Xv, XX }, + { "cmps{b||b|}", Xb, Yb, XX }, + { "cmps{R||R|}", Xv, Yv, XX }, + /* a8 */ + { "testB", AL, Ib, XX }, + { "testS", eAX, Iv, XX }, + { "stosB", Yb, AL, XX }, + { "stosS", Yv, eAX, XX }, + { "lodsB", AL, Xb, XX }, + { "lodsS", eAX, Xv, XX }, + { "scasB", AL, Yb, XX }, + { "scasS", eAX, Yv, XX }, + /* b0 */ + { "movB", RMAL, Ib, XX }, + { "movB", RMCL, Ib, XX }, + { "movB", RMDL, Ib, XX }, + { "movB", RMBL, Ib, XX }, + { "movB", RMAH, Ib, XX }, + { "movB", RMCH, Ib, XX }, + { "movB", RMDH, Ib, XX }, + { "movB", RMBH, Ib, XX }, + /* b8 */ + { "movS", RMeAX, Iv64, XX }, + { "movS", RMeCX, Iv64, XX }, + { "movS", RMeDX, Iv64, XX }, + { "movS", RMeBX, Iv64, XX }, + { "movS", RMeSP, Iv64, XX }, + { "movS", RMeBP, Iv64, XX }, + { "movS", RMeSI, Iv64, XX }, + { "movS", RMeDI, Iv64, XX }, + /* c0 */ + { GRP2b }, + { GRP2S }, + { "retT", Iw, XX, XX }, + { "retT", XX, XX, XX }, + { "les{S|}", Gv, Mp, XX }, + { "ldsS", Gv, Mp, XX }, + { "movA", Eb, Ib, XX }, + { "movQ", Ev, Iv, XX }, + /* c8 */ + { "enterT", Iw, Ib, XX }, + { "leaveT", XX, XX, XX }, + { "lretP", Iw, XX, XX }, + { "lretP", XX, XX, XX }, + { "int3", XX, XX, XX }, + { "int", Ib, XX, XX }, + { "into{|}", XX, XX, XX }, + { "iretP", XX, XX, XX }, + /* d0 */ + { GRP2b_one }, + { GRP2S_one }, + { GRP2b_cl }, + { GRP2S_cl }, + { "aam{|}", sIb, XX, XX }, + { "aad{|}", sIb, XX, XX }, + { "(bad)", XX, XX, XX }, + { "xlat", DSBX, XX, XX }, + /* d8 */ + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + /* e0 */ + { "loopneFH", Jb, XX, loop_jcxz_flag }, + { "loopeFH", Jb, XX, loop_jcxz_flag }, + { "loopFH", Jb, XX, loop_jcxz_flag }, + { "jEcxzH", Jb, XX, loop_jcxz_flag }, + { "inB", AL, Ib, XX }, + { "inS", eAX, Ib, XX }, + { "outB", Ib, AL, XX }, + { "outS", Ib, eAX, XX }, + /* e8 */ + { "callT", Jv, XX, XX }, + { "jmpT", Jv, XX, XX }, + { "ljmp{T|}", Ap, XX, XX }, + { "jmp", Jb, XX, XX }, + { "inB", AL, indirDX, XX }, + { "inS", eAX, indirDX, XX }, + { "outB", indirDX, AL, XX }, + { "outS", indirDX, eAX, XX }, + /* f0 */ + { "(bad)", XX, XX, XX }, /* lock prefix */ + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, /* repne */ + { "(bad)", XX, XX, XX }, /* repz */ + { "hlt", XX, XX, XX }, + { "cmc", XX, XX, XX }, + { GRP3b }, + { GRP3S }, + /* f8 */ + { "clc", XX, XX, XX }, + { "stc", XX, XX, XX }, + { "cli", XX, XX, XX }, + { "sti", XX, XX, XX }, + { "cld", XX, XX, XX }, + { "std", XX, XX, XX }, + { GRP4 }, + { GRP5 }, +}; + +static const struct dis386 dis386_twobyte[] = { + /* 00 */ + { GRP6 }, + { GRP7 }, + { "larS", Gv, Ew, XX }, + { "lslS", Gv, Ew, XX }, + { "(bad)", XX, XX, XX }, + { "syscall", XX, XX, XX }, + { "clts", XX, XX, XX }, + { "sysretP", XX, XX, XX }, + /* 08 */ + { "invd", XX, XX, XX }, + { "wbinvd", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "ud2a", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { GRPAMD }, + { "femms", XX, XX, XX }, + { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix. */ + /* 10 */ + { PREGRP8 }, + { PREGRP9 }, + { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ + { "movlpX", EX, XM, SIMD_Fixup, 'h' }, + { "unpcklpX", XM, EX, XX }, + { "unpckhpX", XM, EX, XX }, + { "movhpX", XM, EX, SIMD_Fixup, 'l' }, + { "movhpX", EX, XM, SIMD_Fixup, 'l' }, + /* 18 */ + { GRP14 }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + /* 20 */ + { "movL", Rm, Cm, XX }, + { "movL", Rm, Dm, XX }, + { "movL", Cm, Rm, XX }, + { "movL", Dm, Rm, XX }, + { "movL", Rd, Td, XX }, + { "(bad)", XX, XX, XX }, + { "movL", Td, Rd, XX }, + { "(bad)", XX, XX, XX }, + /* 28 */ + { "movapX", XM, EX, XX }, + { "movapX", EX, XM, XX }, + { PREGRP2 }, + { "movntpX", Ev, XM, XX }, + { PREGRP4 }, + { PREGRP3 }, + { "ucomisX", XM,EX, XX }, + { "comisX", XM,EX, XX }, + /* 30 */ + { "wrmsr", XX, XX, XX }, + { "rdtsc", XX, XX, XX }, + { "rdmsr", XX, XX, XX }, + { "rdpmc", XX, XX, XX }, + { "sysenter", XX, XX, XX }, + { "sysexit", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + /* 38 */ + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + /* 40 */ + { "cmovo", Gv, Ev, XX }, + { "cmovno", Gv, Ev, XX }, + { "cmovb", Gv, Ev, XX }, + { "cmovae", Gv, Ev, XX }, + { "cmove", Gv, Ev, XX }, + { "cmovne", Gv, Ev, XX }, + { "cmovbe", Gv, Ev, XX }, + { "cmova", Gv, Ev, XX }, + /* 48 */ + { "cmovs", Gv, Ev, XX }, + { "cmovns", Gv, Ev, XX }, + { "cmovp", Gv, Ev, XX }, + { "cmovnp", Gv, Ev, XX }, + { "cmovl", Gv, Ev, XX }, + { "cmovge", Gv, Ev, XX }, + { "cmovle", Gv, Ev, XX }, + { "cmovg", Gv, Ev, XX }, + /* 50 */ + { "movmskpX", Gd, XS, XX }, + { PREGRP13 }, + { PREGRP12 }, + { PREGRP11 }, + { "andpX", XM, EX, XX }, + { "andnpX", XM, EX, XX }, + { "orpX", XM, EX, XX }, + { "xorpX", XM, EX, XX }, + /* 58 */ + { PREGRP0 }, + { PREGRP10 }, + { PREGRP17 }, + { PREGRP16 }, + { PREGRP14 }, + { PREGRP7 }, + { PREGRP5 }, + { PREGRP6 }, + /* 60 */ + { "punpcklbw", MX, EM, XX }, + { "punpcklwd", MX, EM, XX }, + { "punpckldq", MX, EM, XX }, + { "packsswb", MX, EM, XX }, + { "pcmpgtb", MX, EM, XX }, + { "pcmpgtw", MX, EM, XX }, + { "pcmpgtd", MX, EM, XX }, + { "packuswb", MX, EM, XX }, + /* 68 */ + { "punpckhbw", MX, EM, XX }, + { "punpckhwd", MX, EM, XX }, + { "punpckhdq", MX, EM, XX }, + { "packssdw", MX, EM, XX }, + { PREGRP26 }, + { PREGRP24 }, + { "movd", MX, Ed, XX }, + { PREGRP19 }, + /* 70 */ + { PREGRP22 }, + { GRP10 }, + { GRP11 }, + { GRP12 }, + { "pcmpeqb", MX, EM, XX }, + { "pcmpeqw", MX, EM, XX }, + { "pcmpeqd", MX, EM, XX }, + { "emms", XX, XX, XX }, + /* 78 */ + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { PREGRP23 }, + { PREGRP20 }, + /* 80 */ + { "joH", Jv, XX, cond_jump_flag }, + { "jnoH", Jv, XX, cond_jump_flag }, + { "jbH", Jv, XX, cond_jump_flag }, + { "jaeH", Jv, XX, cond_jump_flag }, + { "jeH", Jv, XX, cond_jump_flag }, + { "jneH", Jv, XX, cond_jump_flag }, + { "jbeH", Jv, XX, cond_jump_flag }, + { "jaH", Jv, XX, cond_jump_flag }, + /* 88 */ + { "jsH", Jv, XX, cond_jump_flag }, + { "jnsH", Jv, XX, cond_jump_flag }, + { "jpH", Jv, XX, cond_jump_flag }, + { "jnpH", Jv, XX, cond_jump_flag }, + { "jlH", Jv, XX, cond_jump_flag }, + { "jgeH", Jv, XX, cond_jump_flag }, + { "jleH", Jv, XX, cond_jump_flag }, + { "jgH", Jv, XX, cond_jump_flag }, + /* 90 */ + { "seto", Eb, XX, XX }, + { "setno", Eb, XX, XX }, + { "setb", Eb, XX, XX }, + { "setae", Eb, XX, XX }, + { "sete", Eb, XX, XX }, + { "setne", Eb, XX, XX }, + { "setbe", Eb, XX, XX }, + { "seta", Eb, XX, XX }, + /* 98 */ + { "sets", Eb, XX, XX }, + { "setns", Eb, XX, XX }, + { "setp", Eb, XX, XX }, + { "setnp", Eb, XX, XX }, + { "setl", Eb, XX, XX }, + { "setge", Eb, XX, XX }, + { "setle", Eb, XX, XX }, + { "setg", Eb, XX, XX }, + /* a0 */ + { "pushT", fs, XX, XX }, + { "popT", fs, XX, XX }, + { "cpuid", XX, XX, XX }, + { "btS", Ev, Gv, XX }, + { "shldS", Ev, Gv, Ib }, + { "shldS", Ev, Gv, CL }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + /* a8 */ + { "pushT", gs, XX, XX }, + { "popT", gs, XX, XX }, + { "rsm", XX, XX, XX }, + { "btsS", Ev, Gv, XX }, + { "shrdS", Ev, Gv, Ib }, + { "shrdS", Ev, Gv, CL }, + { GRP13 }, + { "imulS", Gv, Ev, XX }, + /* b0 */ + { "cmpxchgB", Eb, Gb, XX }, + { "cmpxchgS", Ev, Gv, XX }, + { "lssS", Gv, Mp, XX }, + { "btrS", Ev, Gv, XX }, + { "lfsS", Gv, Mp, XX }, + { "lgsS", Gv, Mp, XX }, + { "movz{bR|x|bR|x}", Gv, Eb, XX }, + { "movz{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movzww ! */ + /* b8 */ + { "(bad)", XX, XX, XX }, + { "ud2b", XX, XX, XX }, + { GRP8 }, + { "btcS", Ev, Gv, XX }, + { "bsfS", Gv, Ev, XX }, + { "bsrS", Gv, Ev, XX }, + { "movs{bR|x|bR|x}", Gv, Eb, XX }, + { "movs{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movsww ! */ + /* c0 */ + { "xaddB", Eb, Gb, XX }, + { "xaddS", Ev, Gv, XX }, + { PREGRP1 }, + { "movntiS", Ev, Gv, XX }, + { "pinsrw", MX, Ed, Ib }, + { "pextrw", Gd, MS, Ib }, + { "shufpX", XM, EX, Ib }, + { GRP9 }, + /* c8 */ + { "bswap", RMeAX, XX, XX }, + { "bswap", RMeCX, XX, XX }, + { "bswap", RMeDX, XX, XX }, + { "bswap", RMeBX, XX, XX }, + { "bswap", RMeSP, XX, XX }, + { "bswap", RMeBP, XX, XX }, + { "bswap", RMeSI, XX, XX }, + { "bswap", RMeDI, XX, XX }, + /* d0 */ + { "(bad)", XX, XX, XX }, + { "psrlw", MX, EM, XX }, + { "psrld", MX, EM, XX }, + { "psrlq", MX, EM, XX }, + { "paddq", MX, EM, XX }, + { "pmullw", MX, EM, XX }, + { PREGRP21 }, + { "pmovmskb", Gd, MS, XX }, + /* d8 */ + { "psubusb", MX, EM, XX }, + { "psubusw", MX, EM, XX }, + { "pminub", MX, EM, XX }, + { "pand", MX, EM, XX }, + { "paddusb", MX, EM, XX }, + { "paddusw", MX, EM, XX }, + { "pmaxub", MX, EM, XX }, + { "pandn", MX, EM, XX }, + /* e0 */ + { "pavgb", MX, EM, XX }, + { "psraw", MX, EM, XX }, + { "psrad", MX, EM, XX }, + { "pavgw", MX, EM, XX }, + { "pmulhuw", MX, EM, XX }, + { "pmulhw", MX, EM, XX }, + { PREGRP15 }, + { PREGRP25 }, + /* e8 */ + { "psubsb", MX, EM, XX }, + { "psubsw", MX, EM, XX }, + { "pminsw", MX, EM, XX }, + { "por", MX, EM, XX }, + { "paddsb", MX, EM, XX }, + { "paddsw", MX, EM, XX }, + { "pmaxsw", MX, EM, XX }, + { "pxor", MX, EM, XX }, + /* f0 */ + { "(bad)", XX, XX, XX }, + { "psllw", MX, EM, XX }, + { "pslld", MX, EM, XX }, + { "psllq", MX, EM, XX }, + { "pmuludq", MX, EM, XX }, + { "pmaddwd", MX, EM, XX }, + { "psadbw", MX, EM, XX }, + { PREGRP18 }, + /* f8 */ + { "psubb", MX, EM, XX }, + { "psubw", MX, EM, XX }, + { "psubd", MX, EM, XX }, + { "psubq", MX, EM, XX }, + { "paddb", MX, EM, XX }, + { "paddw", MX, EM, XX }, + { "paddd", MX, EM, XX }, + { "(bad)", XX, XX, XX } +}; + +static const unsigned char onebyte_has_modrm[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ + /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ + /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ + /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ + /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ + /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ + /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ + /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ + /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +static const unsigned char twobyte_has_modrm[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ + /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ + /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ + /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ + /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ + /* a0 */ 0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* af */ + /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ + /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ + /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ + /* f0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +static const unsigned char twobyte_uses_SSE_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */ + /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +static char obuf[100]; +static char *obufp; +static char scratchbuf[100]; +static unsigned char *start_codep; +static unsigned char *insn_codep; +static unsigned char *codep; +static disassemble_info *the_info; +static int mod; +static int rm; +static int reg; +static unsigned char need_modrm; + +/* If we are accessing mod/rm/reg without need_modrm set, then the + values are stale. Hitting this abort likely indicates that you + need to update onebyte_has_modrm or twobyte_has_modrm. */ +#define MODRM_CHECK if (!need_modrm) abort () + +static const char **names64; +static const char **names32; +static const char **names16; +static const char **names8; +static const char **names8rex; +static const char **names_seg; +static const char **index16; + +static const char *intel_names64[] = { + "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" +}; +static const char *intel_names32[] = { + "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", + "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" +}; +static const char *intel_names16[] = { + "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", + "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" +}; +static const char *intel_names8[] = { + "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", +}; +static const char *intel_names8rex[] = { + "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", + "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" +}; +static const char *intel_names_seg[] = { + "es", "cs", "ss", "ds", "fs", "gs", "?", "?", +}; +static const char *intel_index16[] = { + "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" +}; + +static const char *att_names64[] = { + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" +}; +static const char *att_names32[] = { + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", + "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" +}; +static const char *att_names16[] = { + "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", + "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" +}; +static const char *att_names8[] = { + "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", +}; +static const char *att_names8rex[] = { + "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", + "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" +}; +static const char *att_names_seg[] = { + "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", +}; +static const char *att_index16[] = { + "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" +}; + +static const struct dis386 grps[][8] = { + /* GRP1b */ + { + { "addA", Eb, Ib, XX }, + { "orA", Eb, Ib, XX }, + { "adcA", Eb, Ib, XX }, + { "sbbA", Eb, Ib, XX }, + { "andA", Eb, Ib, XX }, + { "subA", Eb, Ib, XX }, + { "xorA", Eb, Ib, XX }, + { "cmpA", Eb, Ib, XX } + }, + /* GRP1S */ + { + { "addQ", Ev, Iv, XX }, + { "orQ", Ev, Iv, XX }, + { "adcQ", Ev, Iv, XX }, + { "sbbQ", Ev, Iv, XX }, + { "andQ", Ev, Iv, XX }, + { "subQ", Ev, Iv, XX }, + { "xorQ", Ev, Iv, XX }, + { "cmpQ", Ev, Iv, XX } + }, + /* GRP1Ss */ + { + { "addQ", Ev, sIb, XX }, + { "orQ", Ev, sIb, XX }, + { "adcQ", Ev, sIb, XX }, + { "sbbQ", Ev, sIb, XX }, + { "andQ", Ev, sIb, XX }, + { "subQ", Ev, sIb, XX }, + { "xorQ", Ev, sIb, XX }, + { "cmpQ", Ev, sIb, XX } + }, + /* GRP2b */ + { + { "rolA", Eb, Ib, XX }, + { "rorA", Eb, Ib, XX }, + { "rclA", Eb, Ib, XX }, + { "rcrA", Eb, Ib, XX }, + { "shlA", Eb, Ib, XX }, + { "shrA", Eb, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "sarA", Eb, Ib, XX }, + }, + /* GRP2S */ + { + { "rolQ", Ev, Ib, XX }, + { "rorQ", Ev, Ib, XX }, + { "rclQ", Ev, Ib, XX }, + { "rcrQ", Ev, Ib, XX }, + { "shlQ", Ev, Ib, XX }, + { "shrQ", Ev, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "sarQ", Ev, Ib, XX }, + }, + /* GRP2b_one */ + { + { "rolA", Eb, XX, XX }, + { "rorA", Eb, XX, XX }, + { "rclA", Eb, XX, XX }, + { "rcrA", Eb, XX, XX }, + { "shlA", Eb, XX, XX }, + { "shrA", Eb, XX, XX }, + { "(bad)", XX, XX, XX }, + { "sarA", Eb, XX, XX }, + }, + /* GRP2S_one */ + { + { "rolQ", Ev, XX, XX }, + { "rorQ", Ev, XX, XX }, + { "rclQ", Ev, XX, XX }, + { "rcrQ", Ev, XX, XX }, + { "shlQ", Ev, XX, XX }, + { "shrQ", Ev, XX, XX }, + { "(bad)", XX, XX, XX}, + { "sarQ", Ev, XX, XX }, + }, + /* GRP2b_cl */ + { + { "rolA", Eb, CL, XX }, + { "rorA", Eb, CL, XX }, + { "rclA", Eb, CL, XX }, + { "rcrA", Eb, CL, XX }, + { "shlA", Eb, CL, XX }, + { "shrA", Eb, CL, XX }, + { "(bad)", XX, XX, XX }, + { "sarA", Eb, CL, XX }, + }, + /* GRP2S_cl */ + { + { "rolQ", Ev, CL, XX }, + { "rorQ", Ev, CL, XX }, + { "rclQ", Ev, CL, XX }, + { "rcrQ", Ev, CL, XX }, + { "shlQ", Ev, CL, XX }, + { "shrQ", Ev, CL, XX }, + { "(bad)", XX, XX, XX }, + { "sarQ", Ev, CL, XX } + }, + /* GRP3b */ + { + { "testA", Eb, Ib, XX }, + { "(bad)", Eb, XX, XX }, + { "notA", Eb, XX, XX }, + { "negA", Eb, XX, XX }, + { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */ + { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */ + { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */ + { "idivA", Eb, XX, XX } /* and idiv for consistency. */ + }, + /* GRP3S */ + { + { "testQ", Ev, Iv, XX }, + { "(bad)", XX, XX, XX }, + { "notQ", Ev, XX, XX }, + { "negQ", Ev, XX, XX }, + { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */ + { "imulQ", Ev, XX, XX }, + { "divQ", Ev, XX, XX }, + { "idivQ", Ev, XX, XX }, + }, + /* GRP4 */ + { + { "incA", Eb, XX, XX }, + { "decA", Eb, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + }, + /* GRP5 */ + { + { "incQ", Ev, XX, XX }, + { "decQ", Ev, XX, XX }, + { "callT", indirEv, XX, XX }, + { "lcallT", indirEv, XX, XX }, + { "jmpT", indirEv, XX, XX }, + { "ljmpT", indirEv, XX, XX }, + { "pushU", Ev, XX, XX }, + { "(bad)", XX, XX, XX }, + }, + /* GRP6 */ + { + { "sldtQ", Ev, XX, XX }, + { "strQ", Ev, XX, XX }, + { "lldt", Ew, XX, XX }, + { "ltr", Ew, XX, XX }, + { "verr", Ew, XX, XX }, + { "verw", Ew, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX } + }, + /* GRP7 */ + { + { "sgdtQ", M, XX, XX }, + { "sidtQ", M, XX, XX }, + { "lgdtQ", M, XX, XX }, + { "lidtQ", M, XX, XX }, + { "smswQ", Ev, XX, XX }, + { "(bad)", XX, XX, XX }, + { "lmsw", Ew, XX, XX }, + { "invlpg", Ew, XX, XX }, + }, + /* GRP8 */ + { + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "btQ", Ev, Ib, XX }, + { "btsQ", Ev, Ib, XX }, + { "btrQ", Ev, Ib, XX }, + { "btcQ", Ev, Ib, XX }, + }, + /* GRP9 */ + { + { "(bad)", XX, XX, XX }, + { "cmpxchg8b", Ev, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + }, + /* GRP10 */ + { + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "psrlw", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "psraw", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "psllw", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + }, + /* GRP11 */ + { + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "psrld", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "psrad", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "pslld", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + }, + /* GRP12 */ + { + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "psrlq", MS, Ib, XX }, + { "psrldq", MS, Ib, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "psllq", MS, Ib, XX }, + { "pslldq", MS, Ib, XX }, + }, + /* GRP13 */ + { + { "fxsave", Ev, XX, XX }, + { "fxrstor", Ev, XX, XX }, + { "ldmxcsr", Ev, XX, XX }, + { "stmxcsr", Ev, XX, XX }, + { "(bad)", XX, XX, XX }, + { "lfence", None, XX, XX }, + { "mfence", None, XX, XX }, + { "sfence", None, XX, XX }, + /* FIXME: the sfence with memory operand is clflush! */ + }, + /* GRP14 */ + { + { "prefetchnta", Ev, XX, XX }, + { "prefetcht0", Ev, XX, XX }, + { "prefetcht1", Ev, XX, XX }, + { "prefetcht2", Ev, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + }, + /* GRPAMD */ + { + { "prefetch", Eb, XX, XX }, + { "prefetchw", Eb, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + } +}; + +static const struct dis386 prefix_user_table[][4] = { + /* PREGRP0 */ + { + { "addps", XM, EX, XX }, + { "addss", XM, EX, XX }, + { "addpd", XM, EX, XX }, + { "addsd", XM, EX, XX }, + }, + /* PREGRP1 */ + { + { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX. */ + { "", XM, EX, OPSIMD }, + { "", XM, EX, OPSIMD }, + { "", XM, EX, OPSIMD }, + }, + /* PREGRP2 */ + { + { "cvtpi2ps", XM, EM, XX }, + { "cvtsi2ssY", XM, Ev, XX }, + { "cvtpi2pd", XM, EM, XX }, + { "cvtsi2sdY", XM, Ev, XX }, + }, + /* PREGRP3 */ + { + { "cvtps2pi", MX, EX, XX }, + { "cvtss2siY", Gv, EX, XX }, + { "cvtpd2pi", MX, EX, XX }, + { "cvtsd2siY", Gv, EX, XX }, + }, + /* PREGRP4 */ + { + { "cvttps2pi", MX, EX, XX }, + { "cvttss2siY", Gv, EX, XX }, + { "cvttpd2pi", MX, EX, XX }, + { "cvttsd2siY", Gv, EX, XX }, + }, + /* PREGRP5 */ + { + { "divps", XM, EX, XX }, + { "divss", XM, EX, XX }, + { "divpd", XM, EX, XX }, + { "divsd", XM, EX, XX }, + }, + /* PREGRP6 */ + { + { "maxps", XM, EX, XX }, + { "maxss", XM, EX, XX }, + { "maxpd", XM, EX, XX }, + { "maxsd", XM, EX, XX }, + }, + /* PREGRP7 */ + { + { "minps", XM, EX, XX }, + { "minss", XM, EX, XX }, + { "minpd", XM, EX, XX }, + { "minsd", XM, EX, XX }, + }, + /* PREGRP8 */ + { + { "movups", XM, EX, XX }, + { "movss", XM, EX, XX }, + { "movupd", XM, EX, XX }, + { "movsd", XM, EX, XX }, + }, + /* PREGRP9 */ + { + { "movups", EX, XM, XX }, + { "movss", EX, XM, XX }, + { "movupd", EX, XM, XX }, + { "movsd", EX, XM, XX }, + }, + /* PREGRP10 */ + { + { "mulps", XM, EX, XX }, + { "mulss", XM, EX, XX }, + { "mulpd", XM, EX, XX }, + { "mulsd", XM, EX, XX }, + }, + /* PREGRP11 */ + { + { "rcpps", XM, EX, XX }, + { "rcpss", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP12 */ + { + { "rsqrtps", XM, EX, XX }, + { "rsqrtss", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP13 */ + { + { "sqrtps", XM, EX, XX }, + { "sqrtss", XM, EX, XX }, + { "sqrtpd", XM, EX, XX }, + { "sqrtsd", XM, EX, XX }, + }, + /* PREGRP14 */ + { + { "subps", XM, EX, XX }, + { "subss", XM, EX, XX }, + { "subpd", XM, EX, XX }, + { "subsd", XM, EX, XX }, + }, + /* PREGRP15 */ + { + { "(bad)", XM, EX, XX }, + { "cvtdq2pd", XM, EX, XX }, + { "cvttpd2dq", XM, EX, XX }, + { "cvtpd2dq", XM, EX, XX }, + }, + /* PREGRP16 */ + { + { "cvtdq2ps", XM, EX, XX }, + { "cvttps2dq",XM, EX, XX }, + { "cvtps2dq",XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP17 */ + { + { "cvtps2pd", XM, EX, XX }, + { "cvtss2sd", XM, EX, XX }, + { "cvtpd2ps", XM, EX, XX }, + { "cvtsd2ss", XM, EX, XX }, + }, + /* PREGRP18 */ + { + { "maskmovq", MX, MS, XX }, + { "(bad)", XM, EX, XX }, + { "maskmovdqu", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP19 */ + { + { "movq", MX, EM, XX }, + { "movdqu", XM, EX, XX }, + { "movdqa", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP20 */ + { + { "movq", EM, MX, XX }, + { "movdqu", EX, XM, XX }, + { "movdqa", EX, XM, XX }, + { "(bad)", EX, XM, XX }, + }, + /* PREGRP21 */ + { + { "(bad)", EX, XM, XX }, + { "movq2dq", XM, MS, XX }, + { "movq", EX, XM, XX }, + { "movdq2q", MX, XS, XX }, + }, + /* PREGRP22 */ + { + { "pshufw", MX, EM, Ib }, + { "pshufhw", XM, EX, Ib }, + { "pshufd", XM, EX, Ib }, + { "pshuflw", XM, EX, Ib }, + }, + /* PREGRP23 */ + { + { "movd", Ed, MX, XX }, + { "movq", XM, EX, XX }, + { "movd", Ed, XM, XX }, + { "(bad)", Ed, XM, XX }, + }, + /* PREGRP24 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "punpckhqdq", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP25 */ + { + { "movntq", Ev, MX, XX }, + { "(bad)", Ev, XM, XX }, + { "movntdq", Ev, XM, XX }, + { "(bad)", Ev, XM, XX }, + }, + /* PREGRP26 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "punpcklqdq", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, +}; + +static const struct dis386 x86_64_table[][2] = { + { + { "arpl", Ew, Gw, XX }, + { "movs{||lq|xd}", Gv, Ed, XX }, + }, +}; + +#define INTERNAL_DISASSEMBLER_ERROR _("") + +static void +ckprefix () +{ + int newrex; + rex = 0; + prefixes = 0; + used_prefixes = 0; + rex_used = 0; + while (1) + { + FETCH_DATA (the_info, codep + 1); + newrex = 0; + switch (*codep) + { + /* REX prefixes family. */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + if (mode_64bit) + newrex = *codep; + else + return; + break; + case 0xf3: + prefixes |= PREFIX_REPZ; + break; + case 0xf2: + prefixes |= PREFIX_REPNZ; + break; + case 0xf0: + prefixes |= PREFIX_LOCK; + break; + case 0x2e: + prefixes |= PREFIX_CS; + break; + case 0x36: + prefixes |= PREFIX_SS; + break; + case 0x3e: + prefixes |= PREFIX_DS; + break; + case 0x26: + prefixes |= PREFIX_ES; + break; + case 0x64: + prefixes |= PREFIX_FS; + break; + case 0x65: + prefixes |= PREFIX_GS; + break; + case 0x66: + prefixes |= PREFIX_DATA; + break; + case 0x67: + prefixes |= PREFIX_ADDR; + break; + case FWAIT_OPCODE: + /* fwait is really an instruction. If there are prefixes + before the fwait, they belong to the fwait, *not* to the + following instruction. */ + if (prefixes) + { + prefixes |= PREFIX_FWAIT; + codep++; + return; + } + prefixes = PREFIX_FWAIT; + break; + default: + return; + } + /* Rex is ignored when followed by another prefix. */ + if (rex) + { + oappend (prefix_name (rex, 0)); + oappend (" "); + } + rex = newrex; + codep++; + } +} + +/* Return the name of the prefix byte PREF, or NULL if PREF is not a + prefix byte. */ + +static const char * +prefix_name (pref, sizeflag) + int pref; + int sizeflag; +{ + switch (pref) + { + /* REX prefixes family. */ + case 0x40: + return "rex"; + case 0x41: + return "rexZ"; + case 0x42: + return "rexY"; + case 0x43: + return "rexYZ"; + case 0x44: + return "rexX"; + case 0x45: + return "rexXZ"; + case 0x46: + return "rexXY"; + case 0x47: + return "rexXYZ"; + case 0x48: + return "rex64"; + case 0x49: + return "rex64Z"; + case 0x4a: + return "rex64Y"; + case 0x4b: + return "rex64YZ"; + case 0x4c: + return "rex64X"; + case 0x4d: + return "rex64XZ"; + case 0x4e: + return "rex64XY"; + case 0x4f: + return "rex64XYZ"; + case 0xf3: + return "repz"; + case 0xf2: + return "repnz"; + case 0xf0: + return "lock"; + case 0x2e: + return "cs"; + case 0x36: + return "ss"; + case 0x3e: + return "ds"; + case 0x26: + return "es"; + case 0x64: + return "fs"; + case 0x65: + return "gs"; + case 0x66: + return (sizeflag & DFLAG) ? "data16" : "data32"; + case 0x67: + if (mode_64bit) + return (sizeflag & AFLAG) ? "addr32" : "addr64"; + else + return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32"; + case FWAIT_OPCODE: + return "fwait"; + default: + return NULL; + } +} + +static char op1out[100], op2out[100], op3out[100]; +static int op_ad, op_index[3]; +static bfd_vma op_address[3]; +static bfd_vma op_riprel[3]; +static bfd_vma start_pc; + +/* + * On the 386's of 1988, the maximum length of an instruction is 15 bytes. + * (see topic "Redundant prefixes" in the "Differences from 8086" + * section of the "Virtual 8086 Mode" chapter.) + * 'pc' should be the address of this instruction, it will + * be used to print the target address if this is a relative jump or call + * The function returns the length of this instruction in bytes. + */ + +static char intel_syntax; +static char open_char; +static char close_char; +static char separator_char; +static char scale_char; + +/* Here for backwards compatibility. When gdb stops using + print_insn_i386_att and print_insn_i386_intel these functions can + disappear, and print_insn_i386 be merged into print_insn. */ +int +print_insn_i386_att (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + intel_syntax = 0; + + return print_insn (pc, info); +} + +int +print_insn_i386_intel (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + intel_syntax = 1; + + return print_insn (pc, info); +} + +int +print_insn_i386 (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + intel_syntax = -1; + + return print_insn (pc, info); +} + +static int +print_insn (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + const struct dis386 *dp; + int i; + int two_source_ops; + char *first, *second, *third; + int needcomma; + unsigned char uses_SSE_prefix; + int sizeflag; + const char *p; + struct dis_private priv; + + mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax + || info->mach == bfd_mach_x86_64); + + if (intel_syntax == -1) + intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax + || info->mach == bfd_mach_x86_64_intel_syntax); + + if (info->mach == bfd_mach_i386_i386 + || info->mach == bfd_mach_x86_64 + || info->mach == bfd_mach_i386_i386_intel_syntax + || info->mach == bfd_mach_x86_64_intel_syntax) + priv.orig_sizeflag = AFLAG | DFLAG; + else if (info->mach == bfd_mach_i386_i8086) + priv.orig_sizeflag = 0; + else + abort (); + + for (p = info->disassembler_options; p != NULL; ) + { + if (strncmp (p, "x86-64", 6) == 0) + { + mode_64bit = 1; + priv.orig_sizeflag = AFLAG | DFLAG; + } + else if (strncmp (p, "i386", 4) == 0) + { + mode_64bit = 0; + priv.orig_sizeflag = AFLAG | DFLAG; + } + else if (strncmp (p, "i8086", 5) == 0) + { + mode_64bit = 0; + priv.orig_sizeflag = 0; + } + else if (strncmp (p, "intel", 5) == 0) + { + intel_syntax = 1; + } + else if (strncmp (p, "att", 3) == 0) + { + intel_syntax = 0; + } + else if (strncmp (p, "addr", 4) == 0) + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~AFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= AFLAG; + } + else if (strncmp (p, "data", 4) == 0) + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~DFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= DFLAG; + } + else if (strncmp (p, "suffix", 6) == 0) + priv.orig_sizeflag |= SUFFIX_ALWAYS; + + p = strchr (p, ','); + if (p != NULL) + p++; + } + + if (intel_syntax) + { + names64 = intel_names64; + names32 = intel_names32; + names16 = intel_names16; + names8 = intel_names8; + names8rex = intel_names8rex; + names_seg = intel_names_seg; + index16 = intel_index16; + open_char = '['; + close_char = ']'; + separator_char = '+'; + scale_char = '*'; + } + else + { + names64 = att_names64; + names32 = att_names32; + names16 = att_names16; + names8 = att_names8; + names8rex = att_names8rex; + names_seg = att_names_seg; + index16 = att_index16; + open_char = '('; + close_char = ')'; + separator_char = ','; + scale_char = ','; + } + + /* The output looks better if we put 7 bytes on a line, since that + puts most long word instructions on a single line. */ + info->bytes_per_line = 7; + + info->private_data = (PTR) &priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = pc; + + obuf[0] = 0; + op1out[0] = 0; + op2out[0] = 0; + op3out[0] = 0; + + op_index[0] = op_index[1] = op_index[2] = -1; + + the_info = info; + start_pc = pc; + start_codep = priv.the_buffer; + codep = priv.the_buffer; + + if (setjmp (priv.bailout) != 0) + { + const char *name; + + /* Getting here means we tried for data but didn't get it. That + means we have an incomplete instruction of some sort. Just + print the first byte as a prefix or a .byte pseudo-op. */ + if (codep > priv.the_buffer) + { + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); + if (name != NULL) + (*info->fprintf_func) (info->stream, "%s", name); + else + { + /* Just print the first byte as a .byte instruction. */ + (*info->fprintf_func) (info->stream, ".byte 0x%x", + (unsigned int) priv.the_buffer[0]); + } + + return 1; + } + + return -1; + } + + obufp = obuf; + ckprefix (); + + insn_codep = codep; + sizeflag = priv.orig_sizeflag; + + FETCH_DATA (info, codep + 1); + two_source_ops = (*codep == 0x62) || (*codep == 0xc8); + + if ((prefixes & PREFIX_FWAIT) + && ((*codep < 0xd8) || (*codep > 0xdf))) + { + const char *name; + + /* fwait not followed by floating point instruction. Print the + first prefix, which is probably fwait itself. */ + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); + if (name == NULL) + name = INTERNAL_DISASSEMBLER_ERROR; + (*info->fprintf_func) (info->stream, "%s", name); + return 1; + } + + if (*codep == 0x0f) + { + FETCH_DATA (info, codep + 2); + dp = &dis386_twobyte[*++codep]; + need_modrm = twobyte_has_modrm[*codep]; + uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep]; + } + else + { + dp = &dis386[*codep]; + need_modrm = onebyte_has_modrm[*codep]; + uses_SSE_prefix = 0; + } + codep++; + + if (!uses_SSE_prefix && (prefixes & PREFIX_REPZ)) + { + oappend ("repz "); + used_prefixes |= PREFIX_REPZ; + } + if (!uses_SSE_prefix && (prefixes & PREFIX_REPNZ)) + { + oappend ("repnz "); + used_prefixes |= PREFIX_REPNZ; + } + if (prefixes & PREFIX_LOCK) + { + oappend ("lock "); + used_prefixes |= PREFIX_LOCK; + } + + if (prefixes & PREFIX_ADDR) + { + sizeflag ^= AFLAG; + if (dp->bytemode3 != loop_jcxz_mode || intel_syntax) + { + if ((sizeflag & AFLAG) || mode_64bit) + oappend ("addr32 "); + else + oappend ("addr16 "); + used_prefixes |= PREFIX_ADDR; + } + } + + if (!uses_SSE_prefix && (prefixes & PREFIX_DATA)) + { + sizeflag ^= DFLAG; + if (dp->bytemode3 == cond_jump_mode + && dp->bytemode1 == v_mode + && !intel_syntax) + { + if (sizeflag & DFLAG) + oappend ("data32 "); + else + oappend ("data16 "); + used_prefixes |= PREFIX_DATA; + } + } + + if (need_modrm) + { + FETCH_DATA (info, codep + 1); + mod = (*codep >> 6) & 3; + reg = (*codep >> 3) & 7; + rm = *codep & 7; + } + + if (dp->name == NULL && dp->bytemode1 == FLOATCODE) + { + dofloat (sizeflag); + } + else + { + int index; + if (dp->name == NULL) + { + switch (dp->bytemode1) + { + case USE_GROUPS: + dp = &grps[dp->bytemode2][reg]; + break; + + case USE_PREFIX_USER_TABLE: + index = 0; + used_prefixes |= (prefixes & PREFIX_REPZ); + if (prefixes & PREFIX_REPZ) + index = 1; + else + { + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + index = 2; + else + { + used_prefixes |= (prefixes & PREFIX_REPNZ); + if (prefixes & PREFIX_REPNZ) + index = 3; + } + } + dp = &prefix_user_table[dp->bytemode2][index]; + break; + + case X86_64_SPECIAL: + dp = &x86_64_table[dp->bytemode2][mode_64bit]; + break; + + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + } + + if (putop (dp->name, sizeflag) == 0) + { + obufp = op1out; + op_ad = 2; + if (dp->op1) + (*dp->op1) (dp->bytemode1, sizeflag); + + obufp = op2out; + op_ad = 1; + if (dp->op2) + (*dp->op2) (dp->bytemode2, sizeflag); + + obufp = op3out; + op_ad = 0; + if (dp->op3) + (*dp->op3) (dp->bytemode3, sizeflag); + } + } + + /* See if any prefixes were not used. If so, print the first one + separately. If we don't do this, we'll wind up printing an + instruction stream which does not precisely correspond to the + bytes we are disassembling. */ + if ((prefixes & ~used_prefixes) != 0) + { + const char *name; + + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); + if (name == NULL) + name = INTERNAL_DISASSEMBLER_ERROR; + (*info->fprintf_func) (info->stream, "%s", name); + return 1; + } + if (rex & ~rex_used) + { + const char *name; + name = prefix_name (rex | 0x40, priv.orig_sizeflag); + if (name == NULL) + name = INTERNAL_DISASSEMBLER_ERROR; + (*info->fprintf_func) (info->stream, "%s ", name); + } + + obufp = obuf + strlen (obuf); + for (i = strlen (obuf); i < 6; i++) + oappend (" "); + oappend (" "); + (*info->fprintf_func) (info->stream, "%s", obuf); + + /* The enter and bound instructions are printed with operands in the same + order as the intel book; everything else is printed in reverse order. */ + if (intel_syntax || two_source_ops) + { + first = op1out; + second = op2out; + third = op3out; + op_ad = op_index[0]; + op_index[0] = op_index[2]; + op_index[2] = op_ad; + } + else + { + first = op3out; + second = op2out; + third = op1out; + } + needcomma = 0; + if (*first) + { + if (op_index[0] != -1 && !op_riprel[0]) + (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info); + else + (*info->fprintf_func) (info->stream, "%s", first); + needcomma = 1; + } + if (*second) + { + if (needcomma) + (*info->fprintf_func) (info->stream, ","); + if (op_index[1] != -1 && !op_riprel[1]) + (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info); + else + (*info->fprintf_func) (info->stream, "%s", second); + needcomma = 1; + } + if (*third) + { + if (needcomma) + (*info->fprintf_func) (info->stream, ","); + if (op_index[2] != -1 && !op_riprel[2]) + (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info); + else + (*info->fprintf_func) (info->stream, "%s", third); + } + for (i = 0; i < 3; i++) + if (op_index[i] != -1 && op_riprel[i]) + { + (*info->fprintf_func) (info->stream, " # "); + (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep + + op_address[op_index[i]]), info); + } + return codep - priv.the_buffer; +} + +static const char *float_mem[] = { + /* d8 */ + "fadd{s||s|}", + "fmul{s||s|}", + "fcom{s||s|}", + "fcomp{s||s|}", + "fsub{s||s|}", + "fsubr{s||s|}", + "fdiv{s||s|}", + "fdivr{s||s|}", + /* d9 */ + "fld{s||s|}", + "(bad)", + "fst{s||s|}", + "fstp{s||s|}", + "fldenv", + "fldcw", + "fNstenv", + "fNstcw", + /* da */ + "fiadd{l||l|}", + "fimul{l||l|}", + "ficom{l||l|}", + "ficomp{l||l|}", + "fisub{l||l|}", + "fisubr{l||l|}", + "fidiv{l||l|}", + "fidivr{l||l|}", + /* db */ + "fild{l||l|}", + "(bad)", + "fist{l||l|}", + "fistp{l||l|}", + "(bad)", + "fld{t||t|}", + "(bad)", + "fstp{t||t|}", + /* dc */ + "fadd{l||l|}", + "fmul{l||l|}", + "fcom{l||l|}", + "fcomp{l||l|}", + "fsub{l||l|}", + "fsubr{l||l|}", + "fdiv{l||l|}", + "fdivr{l||l|}", + /* dd */ + "fld{l||l|}", + "(bad)", + "fst{l||l|}", + "fstp{l||l|}", + "frstor", + "(bad)", + "fNsave", + "fNstsw", + /* de */ + "fiadd", + "fimul", + "ficom", + "ficomp", + "fisub", + "fisubr", + "fidiv", + "fidivr", + /* df */ + "fild", + "(bad)", + "fist", + "fistp", + "fbld", + "fild{ll||ll|}", + "fbstp", + "fistpll", +}; + +#define ST OP_ST, 0 +#define STi OP_STi, 0 + +#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0 +#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0 +#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0 +#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0 +#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0 +#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0 +#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0 +#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0 +#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0 + +static const struct dis386 float_reg[][8] = { + /* d8 */ + { + { "fadd", ST, STi, XX }, + { "fmul", ST, STi, XX }, + { "fcom", STi, XX, XX }, + { "fcomp", STi, XX, XX }, + { "fsub", ST, STi, XX }, + { "fsubr", ST, STi, XX }, + { "fdiv", ST, STi, XX }, + { "fdivr", ST, STi, XX }, + }, + /* d9 */ + { + { "fld", STi, XX, XX }, + { "fxch", STi, XX, XX }, + { FGRPd9_2 }, + { "(bad)", XX, XX, XX }, + { FGRPd9_4 }, + { FGRPd9_5 }, + { FGRPd9_6 }, + { FGRPd9_7 }, + }, + /* da */ + { + { "fcmovb", ST, STi, XX }, + { "fcmove", ST, STi, XX }, + { "fcmovbe",ST, STi, XX }, + { "fcmovu", ST, STi, XX }, + { "(bad)", XX, XX, XX }, + { FGRPda_5 }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + }, + /* db */ + { + { "fcmovnb",ST, STi, XX }, + { "fcmovne",ST, STi, XX }, + { "fcmovnbe",ST, STi, XX }, + { "fcmovnu",ST, STi, XX }, + { FGRPdb_4 }, + { "fucomi", ST, STi, XX }, + { "fcomi", ST, STi, XX }, + { "(bad)", XX, XX, XX }, + }, + /* dc */ + { + { "fadd", STi, ST, XX }, + { "fmul", STi, ST, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, +#if UNIXWARE_COMPAT + { "fsub", STi, ST, XX }, + { "fsubr", STi, ST, XX }, + { "fdiv", STi, ST, XX }, + { "fdivr", STi, ST, XX }, +#else + { "fsubr", STi, ST, XX }, + { "fsub", STi, ST, XX }, + { "fdivr", STi, ST, XX }, + { "fdiv", STi, ST, XX }, +#endif + }, + /* dd */ + { + { "ffree", STi, XX, XX }, + { "(bad)", XX, XX, XX }, + { "fst", STi, XX, XX }, + { "fstp", STi, XX, XX }, + { "fucom", STi, XX, XX }, + { "fucomp", STi, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + }, + /* de */ + { + { "faddp", STi, ST, XX }, + { "fmulp", STi, ST, XX }, + { "(bad)", XX, XX, XX }, + { FGRPde_3 }, +#if UNIXWARE_COMPAT + { "fsubp", STi, ST, XX }, + { "fsubrp", STi, ST, XX }, + { "fdivp", STi, ST, XX }, + { "fdivrp", STi, ST, XX }, +#else + { "fsubrp", STi, ST, XX }, + { "fsubp", STi, ST, XX }, + { "fdivrp", STi, ST, XX }, + { "fdivp", STi, ST, XX }, +#endif + }, + /* df */ + { + { "ffreep", STi, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { "(bad)", XX, XX, XX }, + { FGRPdf_4 }, + { "fucomip",ST, STi, XX }, + { "fcomip", ST, STi, XX }, + { "(bad)", XX, XX, XX }, + }, +}; + +static char *fgrps[][8] = { + /* d9_2 0 */ + { + "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* d9_4 1 */ + { + "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", + }, + + /* d9_5 2 */ + { + "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", + }, + + /* d9_6 3 */ + { + "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", + }, + + /* d9_7 4 */ + { + "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", + }, + + /* da_5 5 */ + { + "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* db_4 6 */ + { + "feni(287 only)","fdisi(287 only)","fNclex","fNinit", + "fNsetpm(287 only)","(bad)","(bad)","(bad)", + }, + + /* de_3 7 */ + { + "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* df_4 8 */ + { + "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, +}; + +static void +dofloat (sizeflag) + int sizeflag; +{ + const struct dis386 *dp; + unsigned char floatop; + + floatop = codep[-1]; + + if (mod != 3) + { + putop (float_mem[(floatop - 0xd8) * 8 + reg], sizeflag); + obufp = op1out; + if (floatop == 0xdb) + OP_E (x_mode, sizeflag); + else if (floatop == 0xdd) + OP_E (d_mode, sizeflag); + else + OP_E (v_mode, sizeflag); + return; + } + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + dp = &float_reg[floatop - 0xd8][reg]; + if (dp->name == NULL) + { + putop (fgrps[dp->bytemode1][rm], sizeflag); + + /* Instruction fnstsw is only one with strange arg. */ + if (floatop == 0xdf && codep[-1] == 0xe0) + strcpy (op1out, names16[0]); + } + else + { + putop (dp->name, sizeflag); + + obufp = op1out; + if (dp->op1) + (*dp->op1) (dp->bytemode1, sizeflag); + obufp = op2out; + if (dp->op2) + (*dp->op2) (dp->bytemode2, sizeflag); + } +} + +static void +OP_ST (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + oappend ("%st"); +} + +static void +OP_STi (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + sprintf (scratchbuf, "%%st(%d)", rm); + oappend (scratchbuf + intel_syntax); +} + +/* Capital letters in template are macros. */ +static int +putop (template, sizeflag) + const char *template; + int sizeflag; +{ + const char *p; + int alt; + + for (p = template; *p; p++) + { + switch (*p) + { + default: + *obufp++ = *p; + break; + case '{': + alt = 0; + if (intel_syntax) + alt += 1; + if (mode_64bit) + alt += 2; + while (alt != 0) + { + while (*++p != '|') + { + if (*p == '}') + { + /* Alternative not valid. */ + strcpy (obuf, "(bad)"); + obufp = obuf + 5; + return 1; + } + else if (*p == '\0') + abort (); + } + alt--; + } + break; + case '|': + while (*++p != '}') + { + if (*p == '\0') + abort (); + } + break; + case '}': + break; + case 'A': + if (intel_syntax) + break; + if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + *obufp++ = 'b'; + break; + case 'B': + if (intel_syntax) + break; + if (sizeflag & SUFFIX_ALWAYS) + *obufp++ = 'b'; + break; + case 'E': /* For jcxz/jecxz */ + if (mode_64bit) + { + if (sizeflag & AFLAG) + *obufp++ = 'r'; + else + *obufp++ = 'e'; + } + else + if (sizeflag & AFLAG) + *obufp++ = 'e'; + used_prefixes |= (prefixes & PREFIX_ADDR); + break; + case 'F': + if (intel_syntax) + break; + if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) + { + if (sizeflag & AFLAG) + *obufp++ = mode_64bit ? 'q' : 'l'; + else + *obufp++ = mode_64bit ? 'l' : 'w'; + used_prefixes |= (prefixes & PREFIX_ADDR); + } + break; + case 'H': + if (intel_syntax) + break; + if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS + || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) + { + used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); + *obufp++ = ','; + *obufp++ = 'p'; + if (prefixes & PREFIX_DS) + *obufp++ = 't'; + else + *obufp++ = 'n'; + } + break; + case 'L': + if (intel_syntax) + break; + if (sizeflag & SUFFIX_ALWAYS) + *obufp++ = 'l'; + break; + case 'N': + if ((prefixes & PREFIX_FWAIT) == 0) + *obufp++ = 'n'; + else + used_prefixes |= PREFIX_FWAIT; + break; + case 'O': + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + *obufp++ = 'o'; + else + *obufp++ = 'd'; + break; + case 'T': + if (intel_syntax) + break; + if (mode_64bit) + { + *obufp++ = 'q'; + break; + } + /* Fall through. */ + case 'P': + if (intel_syntax) + break; + if ((prefixes & PREFIX_DATA) + || (rex & REX_MODE64) + || (sizeflag & SUFFIX_ALWAYS)) + { + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + break; + case 'U': + if (intel_syntax) + break; + if (mode_64bit) + { + *obufp++ = 'q'; + break; + } + /* Fall through. */ + case 'Q': + if (intel_syntax) + break; + USED_REX (REX_MODE64); + if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + { + if (rex & REX_MODE64) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + break; + case 'R': + USED_REX (REX_MODE64); + if (intel_syntax) + { + if (rex & REX_MODE64) + { + *obufp++ = 'q'; + *obufp++ = 't'; + } + else if (sizeflag & DFLAG) + { + *obufp++ = 'd'; + *obufp++ = 'q'; + } + else + { + *obufp++ = 'w'; + *obufp++ = 'd'; + } + } + else + { + if (rex & REX_MODE64) + *obufp++ = 'q'; + else if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + } + if (!(rex & REX_MODE64)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 'S': + if (intel_syntax) + break; + if (sizeflag & SUFFIX_ALWAYS) + { + if (rex & REX_MODE64) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + break; + case 'X': + if (prefixes & PREFIX_DATA) + *obufp++ = 'd'; + else + *obufp++ = 's'; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 'Y': + if (intel_syntax) + break; + if (rex & REX_MODE64) + { + USED_REX (REX_MODE64); + *obufp++ = 'q'; + } + break; + /* implicit operand size 'l' for i386 or 'q' for x86-64 */ + case 'W': + /* operand size flag for cwtl, cbtw */ + USED_REX (0); + if (rex) + *obufp++ = 'l'; + else if (sizeflag & DFLAG) + *obufp++ = 'w'; + else + *obufp++ = 'b'; + if (intel_syntax) + { + if (rex) + { + *obufp++ = 'q'; + *obufp++ = 'e'; + } + if (sizeflag & DFLAG) + { + *obufp++ = 'd'; + *obufp++ = 'e'; + } + else + { + *obufp++ = 'w'; + } + } + if (!rex) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + } + } + *obufp = 0; + return 0; +} + +static void +oappend (s) + const char *s; +{ + strcpy (obufp, s); + obufp += strlen (s); +} + +static void +append_seg () +{ + if (prefixes & PREFIX_CS) + { + used_prefixes |= PREFIX_CS; + oappend ("%cs:" + intel_syntax); + } + if (prefixes & PREFIX_DS) + { + used_prefixes |= PREFIX_DS; + oappend ("%ds:" + intel_syntax); + } + if (prefixes & PREFIX_SS) + { + used_prefixes |= PREFIX_SS; + oappend ("%ss:" + intel_syntax); + } + if (prefixes & PREFIX_ES) + { + used_prefixes |= PREFIX_ES; + oappend ("%es:" + intel_syntax); + } + if (prefixes & PREFIX_FS) + { + used_prefixes |= PREFIX_FS; + oappend ("%fs:" + intel_syntax); + } + if (prefixes & PREFIX_GS) + { + used_prefixes |= PREFIX_GS; + oappend ("%gs:" + intel_syntax); + } +} + +static void +OP_indirE (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + if (!intel_syntax) + oappend ("*"); + OP_E (bytemode, sizeflag); +} + +static void +print_operand_value (buf, hex, disp) + char *buf; + int hex; + bfd_vma disp; +{ + if (mode_64bit) + { + if (hex) + { + char tmp[30]; + int i; + buf[0] = '0'; + buf[1] = 'x'; + sprintf_vma (tmp, disp); + for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); + strcpy (buf + 2, tmp + i); + } + else + { + bfd_signed_vma v = disp; + char tmp[30]; + int i; + if (v < 0) + { + *(buf++) = '-'; + v = -disp; + /* Check for possible overflow on 0x8000000000000000. */ + if (v < 0) + { + strcpy (buf, "9223372036854775808"); + return; + } + } + if (!v) + { + strcpy (buf, "0"); + return; + } + + i = 0; + tmp[29] = 0; + while (v) + { + tmp[28 - i] = (v % 10) + '0'; + v /= 10; + i++; + } + strcpy (buf, tmp + 29 - i); + } + } + else + { + if (hex) + sprintf (buf, "0x%x", (unsigned int) disp); + else + sprintf (buf, "%d", (int) disp); + } +} + +static void +OP_E (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + bfd_vma disp; + int add = 0; + int riprel = 0; + USED_REX (REX_EXTZ); + if (rex & REX_EXTZ) + add += 8; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + if (mod == 3) + { + switch (bytemode) + { + case b_mode: + USED_REX (0); + if (rex) + oappend (names8rex[rm + add]); + else + oappend (names8[rm + add]); + break; + case w_mode: + oappend (names16[rm + add]); + break; + case d_mode: + oappend (names32[rm + add]); + break; + case q_mode: + oappend (names64[rm + add]); + break; + case m_mode: + if (mode_64bit) + oappend (names64[rm + add]); + else + oappend (names32[rm + add]); + break; + case v_mode: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + oappend (names64[rm + add]); + else if (sizeflag & DFLAG) + oappend (names32[rm + add]); + else + oappend (names16[rm + add]); + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 0: + if (!(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */) + && !(codep[-2] == 0xAE && codep[-1] == 0xF0 /* mfence */) + && !(codep[-2] == 0xAE && codep[-1] == 0xe8 /* lfence */)) + BadOp (); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */ + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + return; + } + + disp = 0; + append_seg (); + + if ((sizeflag & AFLAG) || mode_64bit) /* 32 bit address mode */ + { + int havesib; + int havebase; + int base; + int index = 0; + int scale = 0; + + havesib = 0; + havebase = 1; + base = rm; + + if (base == 4) + { + havesib = 1; + FETCH_DATA (the_info, codep + 1); + scale = (*codep >> 6) & 3; + index = (*codep >> 3) & 7; + base = *codep & 7; + USED_REX (REX_EXTY); + USED_REX (REX_EXTZ); + if (rex & REX_EXTY) + index += 8; + if (rex & REX_EXTZ) + base += 8; + codep++; + } + + switch (mod) + { + case 0: + if ((base & 7) == 5) + { + havebase = 0; + if (mode_64bit && !havesib && (sizeflag & AFLAG)) + riprel = 1; + disp = get32s (); + } + break; + case 1: + FETCH_DATA (the_info, codep + 1); + disp = *codep++; + if ((disp & 0x80) != 0) + disp -= 0x100; + break; + case 2: + disp = get32s (); + break; + } + + if (!intel_syntax) + if (mod != 0 || (base & 7) == 5) + { + print_operand_value (scratchbuf, !riprel, disp); + oappend (scratchbuf); + if (riprel) + { + set_op (disp, 1); + oappend ("(%rip)"); + } + } + + if (havebase || (havesib && (index != 4 || scale != 0))) + { + if (intel_syntax) + { + switch (bytemode) + { + case b_mode: + oappend ("BYTE PTR "); + break; + case w_mode: + oappend ("WORD PTR "); + break; + case v_mode: + oappend ("DWORD PTR "); + break; + case d_mode: + oappend ("QWORD PTR "); + break; + case m_mode: + if (mode_64bit) + oappend ("DWORD PTR "); + else + oappend ("QWORD PTR "); + break; + case x_mode: + oappend ("XWORD PTR "); + break; + default: + break; + } + } + *obufp++ = open_char; + if (intel_syntax && riprel) + oappend ("rip + "); + *obufp = '\0'; + USED_REX (REX_EXTZ); + if (!havesib && (rex & REX_EXTZ)) + base += 8; + if (havebase) + oappend (mode_64bit && (sizeflag & AFLAG) + ? names64[base] : names32[base]); + if (havesib) + { + if (index != 4) + { + if (intel_syntax) + { + if (havebase) + { + *obufp++ = separator_char; + *obufp = '\0'; + } + sprintf (scratchbuf, "%s", + mode_64bit && (sizeflag & AFLAG) + ? names64[index] : names32[index]); + } + else + sprintf (scratchbuf, ",%s", + mode_64bit && (sizeflag & AFLAG) + ? names64[index] : names32[index]); + oappend (scratchbuf); + } + if (!intel_syntax + || (intel_syntax + && bytemode != b_mode + && bytemode != w_mode + && bytemode != v_mode)) + { + *obufp++ = scale_char; + *obufp = '\0'; + sprintf (scratchbuf, "%d", 1 << scale); + oappend (scratchbuf); + } + } + if (intel_syntax) + if (mod != 0 || (base & 7) == 5) + { + /* Don't print zero displacements. */ + if (disp != 0) + { + if ((bfd_signed_vma) disp > 0) + { + *obufp++ = '+'; + *obufp = '\0'; + } + + print_operand_value (scratchbuf, 0, disp); + oappend (scratchbuf); + } + } + + *obufp++ = close_char; + *obufp = '\0'; + } + else if (intel_syntax) + { + if (mod != 0 || (base & 7) == 5) + { + if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS)) + ; + else + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + print_operand_value (scratchbuf, 1, disp); + oappend (scratchbuf); + } + } + } + else + { /* 16 bit address mode */ + switch (mod) + { + case 0: + if ((rm & 7) == 6) + { + disp = get16 (); + if ((disp & 0x8000) != 0) + disp -= 0x10000; + } + break; + case 1: + FETCH_DATA (the_info, codep + 1); + disp = *codep++; + if ((disp & 0x80) != 0) + disp -= 0x100; + break; + case 2: + disp = get16 (); + if ((disp & 0x8000) != 0) + disp -= 0x10000; + break; + } + + if (!intel_syntax) + if (mod != 0 || (rm & 7) == 6) + { + print_operand_value (scratchbuf, 0, disp); + oappend (scratchbuf); + } + + if (mod != 0 || (rm & 7) != 6) + { + *obufp++ = open_char; + *obufp = '\0'; + oappend (index16[rm + add]); + *obufp++ = close_char; + *obufp = '\0'; + } + } +} + +static void +OP_G (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + int add = 0; + USED_REX (REX_EXTX); + if (rex & REX_EXTX) + add += 8; + switch (bytemode) + { + case b_mode: + USED_REX (0); + if (rex) + oappend (names8rex[reg + add]); + else + oappend (names8[reg + add]); + break; + case w_mode: + oappend (names16[reg + add]); + break; + case d_mode: + oappend (names32[reg + add]); + break; + case q_mode: + oappend (names64[reg + add]); + break; + case v_mode: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + oappend (names64[reg + add]); + else if (sizeflag & DFLAG) + oappend (names32[reg + add]); + else + oappend (names16[reg + add]); + used_prefixes |= (prefixes & PREFIX_DATA); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } +} + +static bfd_vma +get64 () +{ + bfd_vma x; +#ifdef BFD64 + unsigned int a; + unsigned int b; + + FETCH_DATA (the_info, codep + 8); + a = *codep++ & 0xff; + a |= (*codep++ & 0xff) << 8; + a |= (*codep++ & 0xff) << 16; + a |= (*codep++ & 0xff) << 24; + b = *codep++ & 0xff; + b |= (*codep++ & 0xff) << 8; + b |= (*codep++ & 0xff) << 16; + b |= (*codep++ & 0xff) << 24; + x = a + ((bfd_vma) b << 32); +#else + abort (); + x = 0; +#endif + return x; +} + +static bfd_signed_vma +get32 () +{ + bfd_signed_vma x = 0; + + FETCH_DATA (the_info, codep + 4); + x = *codep++ & (bfd_signed_vma) 0xff; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; + return x; +} + +static bfd_signed_vma +get32s () +{ + bfd_signed_vma x = 0; + + FETCH_DATA (the_info, codep + 4); + x = *codep++ & (bfd_signed_vma) 0xff; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; + + x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); + + return x; +} + +static int +get16 () +{ + int x = 0; + + FETCH_DATA (the_info, codep + 2); + x = *codep++ & 0xff; + x |= (*codep++ & 0xff) << 8; + return x; +} + +static void +set_op (op, riprel) + bfd_vma op; + int riprel; +{ + op_index[op_ad] = op_ad; + if (mode_64bit) + { + op_address[op_ad] = op; + op_riprel[op_ad] = riprel; + } + else + { + /* Mask to get a 32-bit address. */ + op_address[op_ad] = op & 0xffffffff; + op_riprel[op_ad] = riprel & 0xffffffff; + } +} + +static void +OP_REG (code, sizeflag) + int code; + int sizeflag; +{ + const char *s; + int add = 0; + USED_REX (REX_EXTZ); + if (rex & REX_EXTZ) + add = 8; + + switch (code) + { + case indir_dx_reg: + if (intel_syntax) + s = "[dx]"; + else + s = "(%dx)"; + break; + case ax_reg: case cx_reg: case dx_reg: case bx_reg: + case sp_reg: case bp_reg: case si_reg: case di_reg: + s = names16[code - ax_reg + add]; + break; + case es_reg: case ss_reg: case cs_reg: + case ds_reg: case fs_reg: case gs_reg: + s = names_seg[code - es_reg + add]; + break; + case al_reg: case ah_reg: case cl_reg: case ch_reg: + case dl_reg: case dh_reg: case bl_reg: case bh_reg: + USED_REX (0); + if (rex) + s = names8rex[code - al_reg + add]; + else + s = names8[code - al_reg]; + break; + case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: + case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: + if (mode_64bit) + { + s = names64[code - rAX_reg + add]; + break; + } + code += eAX_reg - rAX_reg; + /* Fall through. */ + case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: + case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + s = names64[code - eAX_reg + add]; + else if (sizeflag & DFLAG) + s = names32[code - eAX_reg + add]; + else + s = names16[code - eAX_reg + add]; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + default: + s = INTERNAL_DISASSEMBLER_ERROR; + break; + } + oappend (s); +} + +static void +OP_IMREG (code, sizeflag) + int code; + int sizeflag; +{ + const char *s; + + switch (code) + { + case indir_dx_reg: + if (intel_syntax) + s = "[dx]"; + else + s = "(%dx)"; + break; + case ax_reg: case cx_reg: case dx_reg: case bx_reg: + case sp_reg: case bp_reg: case si_reg: case di_reg: + s = names16[code - ax_reg]; + break; + case es_reg: case ss_reg: case cs_reg: + case ds_reg: case fs_reg: case gs_reg: + s = names_seg[code - es_reg]; + break; + case al_reg: case ah_reg: case cl_reg: case ch_reg: + case dl_reg: case dh_reg: case bl_reg: case bh_reg: + USED_REX (0); + if (rex) + s = names8rex[code - al_reg]; + else + s = names8[code - al_reg]; + break; + case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: + case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + s = names64[code - eAX_reg]; + else if (sizeflag & DFLAG) + s = names32[code - eAX_reg]; + else + s = names16[code - eAX_reg]; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + default: + s = INTERNAL_DISASSEMBLER_ERROR; + break; + } + oappend (s); +} + +static void +OP_I (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + bfd_signed_vma op; + bfd_signed_vma mask = -1; + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + op = *codep++; + mask = 0xff; + break; + case q_mode: + if (mode_64bit) + { + op = get32s (); + break; + } + /* Fall through. */ + case v_mode: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + op = get32s (); + else if (sizeflag & DFLAG) + { + op = get32 (); + mask = 0xffffffff; + } + else + { + op = get16 (); + mask = 0xfffff; + } + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case w_mode: + mask = 0xfffff; + op = get16 (); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + + op &= mask; + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, op); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; +} + +static void +OP_I64 (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + bfd_signed_vma op; + bfd_signed_vma mask = -1; + + if (!mode_64bit) + { + OP_I (bytemode, sizeflag); + return; + } + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + op = *codep++; + mask = 0xff; + break; + case v_mode: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + op = get64 (); + else if (sizeflag & DFLAG) + { + op = get32 (); + mask = 0xffffffff; + } + else + { + op = get16 (); + mask = 0xfffff; + } + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case w_mode: + mask = 0xfffff; + op = get16 (); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + + op &= mask; + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, op); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; +} + +static void +OP_sI (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + bfd_signed_vma op; + bfd_signed_vma mask = -1; + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + op = *codep++; + if ((op & 0x80) != 0) + op -= 0x100; + mask = 0xffffffff; + break; + case v_mode: + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + op = get32s (); + else if (sizeflag & DFLAG) + { + op = get32s (); + mask = 0xffffffff; + } + else + { + mask = 0xffffffff; + op = get16 (); + if ((op & 0x8000) != 0) + op -= 0x10000; + } + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case w_mode: + op = get16 (); + mask = 0xffffffff; + if ((op & 0x8000) != 0) + op -= 0x10000; + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, op); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_J (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + bfd_vma disp; + bfd_vma mask = -1; + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + disp = *codep++; + if ((disp & 0x80) != 0) + disp -= 0x100; + break; + case v_mode: + if (sizeflag & DFLAG) + disp = get32s (); + else + { + disp = get16 (); + /* For some reason, a data16 prefix on a jump instruction + means that the pc is masked to 16 bits after the + displacement is added! */ + mask = 0xffff; + } + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + disp = (start_pc + codep - start_codep + disp) & mask; + set_op (disp, 0); + print_operand_value (scratchbuf, 1, disp); + oappend (scratchbuf); +} + +static void +OP_SEG (dummy, sizeflag) + int dummy ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + oappend (names_seg[reg]); +} + +static void +OP_DIR (dummy, sizeflag) + int dummy ATTRIBUTE_UNUSED; + int sizeflag; +{ + int seg, offset; + + if (sizeflag & DFLAG) + { + offset = get32 (); + seg = get16 (); + } + else + { + offset = get16 (); + seg = get16 (); + } + used_prefixes |= (prefixes & PREFIX_DATA); + if (intel_syntax) + sprintf (scratchbuf, "0x%x,0x%x", seg, offset); + else + sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); + oappend (scratchbuf); +} + +static void +OP_OFF (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag; +{ + bfd_vma off; + + append_seg (); + + if ((sizeflag & AFLAG) || mode_64bit) + off = get32 (); + else + off = get16 (); + + if (intel_syntax) + { + if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + } + print_operand_value (scratchbuf, 1, off); + oappend (scratchbuf); +} + +static void +OP_OFF64 (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + bfd_vma off; + + if (!mode_64bit) + { + OP_OFF (bytemode, sizeflag); + return; + } + + append_seg (); + + off = get64 (); + + if (intel_syntax) + { + if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + } + print_operand_value (scratchbuf, 1, off); + oappend (scratchbuf); +} + +static void +ptr_reg (code, sizeflag) + int code; + int sizeflag; +{ + const char *s; + if (intel_syntax) + oappend ("["); + else + oappend ("("); + + USED_REX (REX_MODE64); + if (rex & REX_MODE64) + { + if (!(sizeflag & AFLAG)) + s = names32[code - eAX_reg]; + else + s = names64[code - eAX_reg]; + } + else if (sizeflag & AFLAG) + s = names32[code - eAX_reg]; + else + s = names16[code - eAX_reg]; + oappend (s); + if (intel_syntax) + oappend ("]"); + else + oappend (")"); +} + +static void +OP_ESreg (code, sizeflag) + int code; + int sizeflag; +{ + oappend ("%es:" + intel_syntax); + ptr_reg (code, sizeflag); +} + +static void +OP_DSreg (code, sizeflag) + int code; + int sizeflag; +{ + if ((prefixes + & (PREFIX_CS + | PREFIX_DS + | PREFIX_SS + | PREFIX_ES + | PREFIX_FS + | PREFIX_GS)) == 0) + prefixes |= PREFIX_DS; + append_seg (); + ptr_reg (code, sizeflag); +} + +static void +OP_C (dummy, sizeflag) + int dummy ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + int add = 0; + USED_REX (REX_EXTX); + if (rex & REX_EXTX) + add = 8; + sprintf (scratchbuf, "%%cr%d", reg + add); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_D (dummy, sizeflag) + int dummy ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + int add = 0; + USED_REX (REX_EXTX); + if (rex & REX_EXTX) + add = 8; + if (intel_syntax) + sprintf (scratchbuf, "db%d", reg + add); + else + sprintf (scratchbuf, "%%db%d", reg + add); + oappend (scratchbuf); +} + +static void +OP_T (dummy, sizeflag) + int dummy ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + sprintf (scratchbuf, "%%tr%d", reg); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_Rd (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + if (mod == 3) + OP_E (bytemode, sizeflag); + else + BadOp (); +} + +static void +OP_MMX (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + int add = 0; + USED_REX (REX_EXTX); + if (rex & REX_EXTX) + add = 8; + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + sprintf (scratchbuf, "%%xmm%d", reg + add); + else + sprintf (scratchbuf, "%%mm%d", reg + add); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_XMM (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + int add = 0; + USED_REX (REX_EXTX); + if (rex & REX_EXTX) + add = 8; + sprintf (scratchbuf, "%%xmm%d", reg + add); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_EM (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + int add = 0; + if (mod != 3) + { + OP_E (bytemode, sizeflag); + return; + } + USED_REX (REX_EXTZ); + if (rex & REX_EXTZ) + add = 8; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + sprintf (scratchbuf, "%%xmm%d", rm + add); + else + sprintf (scratchbuf, "%%mm%d", rm + add); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_EX (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + int add = 0; + if (mod != 3) + { + OP_E (bytemode, sizeflag); + return; + } + USED_REX (REX_EXTZ); + if (rex & REX_EXTZ) + add = 8; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + sprintf (scratchbuf, "%%xmm%d", rm + add); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_MS (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + if (mod == 3) + OP_EM (bytemode, sizeflag); + else + BadOp (); +} + +static void +OP_XS (bytemode, sizeflag) + int bytemode; + int sizeflag; +{ + if (mod == 3) + OP_EX (bytemode, sizeflag); + else + BadOp (); +} + +static const char *Suffix3DNow[] = { +/* 00 */ NULL, NULL, NULL, NULL, +/* 04 */ NULL, NULL, NULL, NULL, +/* 08 */ NULL, NULL, NULL, NULL, +/* 0C */ "pi2fw", "pi2fd", NULL, NULL, +/* 10 */ NULL, NULL, NULL, NULL, +/* 14 */ NULL, NULL, NULL, NULL, +/* 18 */ NULL, NULL, NULL, NULL, +/* 1C */ "pf2iw", "pf2id", NULL, NULL, +/* 20 */ NULL, NULL, NULL, NULL, +/* 24 */ NULL, NULL, NULL, NULL, +/* 28 */ NULL, NULL, NULL, NULL, +/* 2C */ NULL, NULL, NULL, NULL, +/* 30 */ NULL, NULL, NULL, NULL, +/* 34 */ NULL, NULL, NULL, NULL, +/* 38 */ NULL, NULL, NULL, NULL, +/* 3C */ NULL, NULL, NULL, NULL, +/* 40 */ NULL, NULL, NULL, NULL, +/* 44 */ NULL, NULL, NULL, NULL, +/* 48 */ NULL, NULL, NULL, NULL, +/* 4C */ NULL, NULL, NULL, NULL, +/* 50 */ NULL, NULL, NULL, NULL, +/* 54 */ NULL, NULL, NULL, NULL, +/* 58 */ NULL, NULL, NULL, NULL, +/* 5C */ NULL, NULL, NULL, NULL, +/* 60 */ NULL, NULL, NULL, NULL, +/* 64 */ NULL, NULL, NULL, NULL, +/* 68 */ NULL, NULL, NULL, NULL, +/* 6C */ NULL, NULL, NULL, NULL, +/* 70 */ NULL, NULL, NULL, NULL, +/* 74 */ NULL, NULL, NULL, NULL, +/* 78 */ NULL, NULL, NULL, NULL, +/* 7C */ NULL, NULL, NULL, NULL, +/* 80 */ NULL, NULL, NULL, NULL, +/* 84 */ NULL, NULL, NULL, NULL, +/* 88 */ NULL, NULL, "pfnacc", NULL, +/* 8C */ NULL, NULL, "pfpnacc", NULL, +/* 90 */ "pfcmpge", NULL, NULL, NULL, +/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", +/* 98 */ NULL, NULL, "pfsub", NULL, +/* 9C */ NULL, NULL, "pfadd", NULL, +/* A0 */ "pfcmpgt", NULL, NULL, NULL, +/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", +/* A8 */ NULL, NULL, "pfsubr", NULL, +/* AC */ NULL, NULL, "pfacc", NULL, +/* B0 */ "pfcmpeq", NULL, NULL, NULL, +/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw", +/* B8 */ NULL, NULL, NULL, "pswapd", +/* BC */ NULL, NULL, NULL, "pavgusb", +/* C0 */ NULL, NULL, NULL, NULL, +/* C4 */ NULL, NULL, NULL, NULL, +/* C8 */ NULL, NULL, NULL, NULL, +/* CC */ NULL, NULL, NULL, NULL, +/* D0 */ NULL, NULL, NULL, NULL, +/* D4 */ NULL, NULL, NULL, NULL, +/* D8 */ NULL, NULL, NULL, NULL, +/* DC */ NULL, NULL, NULL, NULL, +/* E0 */ NULL, NULL, NULL, NULL, +/* E4 */ NULL, NULL, NULL, NULL, +/* E8 */ NULL, NULL, NULL, NULL, +/* EC */ NULL, NULL, NULL, NULL, +/* F0 */ NULL, NULL, NULL, NULL, +/* F4 */ NULL, NULL, NULL, NULL, +/* F8 */ NULL, NULL, NULL, NULL, +/* FC */ NULL, NULL, NULL, NULL, +}; + +static void +OP_3DNowSuffix (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + const char *mnemonic; + + FETCH_DATA (the_info, codep + 1); + /* AMD 3DNow! instructions are specified by an opcode suffix in the + place where an 8-bit immediate would normally go. ie. the last + byte of the instruction. */ + obufp = obuf + strlen (obuf); + mnemonic = Suffix3DNow[*codep++ & 0xff]; + if (mnemonic) + oappend (mnemonic); + else + { + /* Since a variable sized modrm/sib chunk is between the start + of the opcode (0x0f0f) and the opcode suffix, we need to do + all the modrm processing first, and don't know until now that + we have a bad opcode. This necessitates some cleaning up. */ + op1out[0] = '\0'; + op2out[0] = '\0'; + BadOp (); + } +} + +static const char *simd_cmp_op[] = { + "eq", + "lt", + "le", + "unord", + "neq", + "nlt", + "nle", + "ord" +}; + +static void +OP_SIMD_Suffix (bytemode, sizeflag) + int bytemode ATTRIBUTE_UNUSED; + int sizeflag ATTRIBUTE_UNUSED; +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + obufp = obuf + strlen (obuf); + cmp_type = *codep++ & 0xff; + if (cmp_type < 8) + { + char suffix1 = 'p', suffix2 = 's'; + used_prefixes |= (prefixes & PREFIX_REPZ); + if (prefixes & PREFIX_REPZ) + suffix1 = 's'; + else + { + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + suffix2 = 'd'; + else + { + used_prefixes |= (prefixes & PREFIX_REPNZ); + if (prefixes & PREFIX_REPNZ) + suffix1 = 's', suffix2 = 'd'; + } + } + sprintf (scratchbuf, "cmp%s%c%c", + simd_cmp_op[cmp_type], suffix1, suffix2); + used_prefixes |= (prefixes & PREFIX_REPZ); + oappend (scratchbuf); + } + else + { + /* We have a bad extension byte. Clean up. */ + op1out[0] = '\0'; + op2out[0] = '\0'; + BadOp (); + } +} + +static void +SIMD_Fixup (extrachar, sizeflag) + int extrachar; + int sizeflag ATTRIBUTE_UNUSED; +{ + /* Change movlps/movhps to movhlps/movlhps for 2 register operand + forms of these instructions. */ + if (mod == 3) + { + char *p = obuf + strlen (obuf); + *(p + 1) = '\0'; + *p = *(p - 1); + *(p - 1) = *(p - 2); + *(p - 2) = *(p - 3); + *(p - 3) = extrachar; + } +} + +static void +BadOp (void) +{ + /* Throw away prefixes and 1st. opcode byte. */ + codep = insn_codep + 1; + oappend ("(bad)"); +} diff --git a/opcodes/i860-dis.c b/opcodes/i860-dis.c new file mode 100644 index 0000000..ba183ab --- /dev/null +++ b/opcodes/i860-dis.c @@ -0,0 +1,288 @@ +/* Disassembler for the i860. + Copyright 2000 Free Software Foundation, Inc. + + Contributed by Jason Eckhardt . + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "dis-asm.h" +#include "opcode/i860.h" + +/* Later we should probably choose the prefix based on which OS flavor. */ +#define I860_REG_PREFIX "%" + +/* Integer register names (encoded as 0..31 in the instruction). */ +static const char *const grnames[] = + {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; + +/* FP register names (encoded as 0..31 in the instruction). */ +static const char *const frnames[] = + {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; + +/* Control/status register names (encoded as 0..5 in the instruction). */ +static const char *const crnames[] = + {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""}; + + +/* Prototypes. */ +static int sign_ext PARAMS((unsigned int, int)); +static void print_br_address PARAMS((disassemble_info *, bfd_vma, long)); + + +/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */ +#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \ + || (op) == 0x34 || (op) == 0x35 \ + || (op) == 0x38 || (op) == 0x39 \ + || (op) == 0x3c || (op) == 0x3d \ + || (op) == 0x33 || (op) == 0x37 \ + || (op) == 0x3b || (op) == 0x3f) + + +/* Sign extend N-bit number. */ +static int +sign_ext (x, n) + unsigned int x; + int n; +{ + int t; + t = x >> (n - 1); + t = ((-t) << n) | x; + return t; +} + + +/* Print a PC-relative branch offset. VAL is the sign extended value + from the branch instruction. */ +static void +print_br_address (info, memaddr, val) + disassemble_info *info; + bfd_vma memaddr; + long val; +{ + + long adj = (long)memaddr + 4 + (val << 2); + + (*info->fprintf_func) (info->stream, "0x%08x", adj); + + /* Attempt to obtain a symbol for the target address. */ + + if (info->print_address_func && adj != 0) + { + (*info->fprintf_func) (info->stream, "\t// "); + (*info->print_address_func) (adj, info); + } +} + + +/* Print one instruction. */ +int +print_insn_i860 (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + bfd_byte buff[4]; + unsigned int insn, i; + int status; + const struct i860_opcode *opcode = 0; + + status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Note that i860 instructions are always accessed as little endian + data, regardless of the endian mode of the i860. */ + insn = bfd_getl32 (buff); + + status = 0; + i = 0; + while (i860_opcodes[i].name != NULL) + { + opcode = &i860_opcodes[i]; + if ((insn & opcode->match) == opcode->match + && (insn & opcode->lose) == 0) + { + status = 1; + break; + } + ++i; + } + + if (status == 0) + { + /* Instruction not in opcode table. */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + } + else + { + const char *s; + int val; + + /* If this a flop and its dual bit is set, prefix with 'd.'. */ + if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200)) + (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + + for (s = opcode->args; *s; s++) + { + switch (*s) + { + /* Integer register (src1). */ + case '1': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 11) & 0x1f]); + break; + + /* Integer register (src2). */ + case '2': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 21) & 0x1f]); + break; + + /* Integer destination register. */ + case 'd': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 16) & 0x1f]); + break; + + /* Floating-point register (src1). */ + case 'e': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 11) & 0x1f]); + break; + + /* Floating-point register (src2). */ + case 'f': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 21) & 0x1f]); + break; + + /* Floating-point destination register. */ + case 'g': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 16) & 0x1f]); + break; + + /* Control register. */ + case 'c': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + crnames[(insn >> 21) & 0x7]); + break; + + /* 16-bit immediate (sign extend, except for bitwise ops). */ + case 'i': + if (BITWISE_OP ((insn & 0xfc000000) >> 26)) + (*info->fprintf_func) (info->stream, "0x%04x", + (unsigned int) (insn & 0xffff)); + else + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^0, ld.b). */ + case 'I': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^1, ld.s). */ + case 'J': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffe), 16)); + break; + + /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */ + case 'K': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffc), 16)); + break; + + /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */ + case 'L': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff8), 16)); + break; + + /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */ + case 'M': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff0), 16)); + break; + + /* 5-bit immediate (zero extend). */ + case '5': + (*info->fprintf_func) (info->stream, "%d", + ((insn >> 11) & 0x1f)); + break; + + /* Split 16 bit immediate (20..16:10..0). */ + case 's': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^0, st.b). */ + case 'S': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^1, st.s). */ + case 'T': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fe); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^2, st.l). */ + case 'U': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fc); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* 26-bit PC relative immediate (lbroff). */ + case 'l': + val = sign_ext ((insn & 0x03ffffff), 26); + print_br_address (info, memaddr, val); + break; + + /* 16-bit PC relative immediate (sbroff). */ + case 'r': + val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); + print_br_address (info, memaddr, val); + break; + + default: + (*info->fprintf_func) (info->stream, "%c", *s); + break; + } + } + } + + return sizeof (insn); +} + diff --git a/opcodes/i960-dis.c b/opcodes/i960-dis.c new file mode 100644 index 0000000..9210d02 --- /dev/null +++ b/opcodes/i960-dis.c @@ -0,0 +1,956 @@ +/* Disassemble i80960 instructions. + Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to the +Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" + +static const char *const reg_names[] = { +/* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7", +/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", +/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", +/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", +/* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3" +}; + + +static FILE *stream; /* Output goes here */ +static struct disassemble_info *info; +static void print_addr PARAMS ((bfd_vma)); +static void ctrl PARAMS ((bfd_vma, unsigned long, unsigned long)); +static void cobr PARAMS ((bfd_vma, unsigned long, unsigned long)); +static void reg PARAMS ((unsigned long)); +static int mem PARAMS ((bfd_vma, unsigned long, unsigned long, int)); +static void ea PARAMS ((bfd_vma, int, const char *, const char *, int, unsigned int)); +static void dstop PARAMS ((int, int, int)); +static void regop PARAMS ((int, int, int, int)); +static void invalid PARAMS ((int)); +static int pinsn PARAMS ((bfd_vma, unsigned long, unsigned long)); +static void put_abs PARAMS ((unsigned long, unsigned long)); + + +/* Print the i960 instruction at address 'memaddr' in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_i960 (memaddr, info_arg) + bfd_vma memaddr; + struct disassemble_info *info_arg; +{ + unsigned int word1, word2 = 0xdeadbeef; + bfd_byte buffer[8]; + int status; + + info = info_arg; + stream = info->stream; + + /* Read word1. Only read word2 if the instruction + needs it, to prevent reading past the end of a section. */ + + status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + word1 = bfd_getl32 (buffer); + + /* Divide instruction set into classes based on high 4 bits of opcode. */ + switch ( (word1 >> 28) & 0xf ) + { + default: + break; + case 0x8: + case 0x9: + case 0xa: + case 0xb: + case 0xc: + /* Read word2. */ + status = (*info->read_memory_func) + (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + word2 = bfd_getl32 (buffer + 4); + break; + } + + return pinsn( memaddr, word1, word2 ); +} + +#define IN_GDB + +/***************************************************************************** + * All code below this point should be identical with that of + * the disassembler in gdmp960. + + A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it + just ain't so. -kingdon, 31 Mar 93 + *****************************************************************************/ + +struct tabent { + char *name; + short numops; +}; + +struct sparse_tabent { + int opcode; + char *name; + short numops; +}; + +static int +pinsn (memaddr, word1, word2) + bfd_vma memaddr; + unsigned long word1, word2; +{ + int instr_len; + + instr_len = 4; + put_abs (word1, word2); + + /* Divide instruction set into classes based on high 4 bits of opcode. */ + switch ((word1 >> 28) & 0xf) + { + case 0x0: + case 0x1: + ctrl (memaddr, word1, word2); + break; + case 0x2: + case 0x3: + cobr (memaddr, word1, word2); + break; + case 0x5: + case 0x6: + case 0x7: + reg (word1); + break; + case 0x8: + case 0x9: + case 0xa: + case 0xb: + case 0xc: + instr_len = mem (memaddr, word1, word2, 0); + break; + default: + /* Invalid instruction, print as data word. */ + invalid (word1); + break; + } + return instr_len; +} + +/* CTRL format.. */ + +static void +ctrl (memaddr, word1, word2) + bfd_vma memaddr; + unsigned long word1; + unsigned long word2 ATTRIBUTE_UNUSED; +{ + int i; + static const struct tabent ctrl_tab[] = { + { NULL, 0, }, /* 0x00 */ + { NULL, 0, }, /* 0x01 */ + { NULL, 0, }, /* 0x02 */ + { NULL, 0, }, /* 0x03 */ + { NULL, 0, }, /* 0x04 */ + { NULL, 0, }, /* 0x05 */ + { NULL, 0, }, /* 0x06 */ + { NULL, 0, }, /* 0x07 */ + { "b", 1, }, /* 0x08 */ + { "call", 1, }, /* 0x09 */ + { "ret", 0, }, /* 0x0a */ + { "bal", 1, }, /* 0x0b */ + { NULL, 0, }, /* 0x0c */ + { NULL, 0, }, /* 0x0d */ + { NULL, 0, }, /* 0x0e */ + { NULL, 0, }, /* 0x0f */ + { "bno", 1, }, /* 0x10 */ + { "bg", 1, }, /* 0x11 */ + { "be", 1, }, /* 0x12 */ + { "bge", 1, }, /* 0x13 */ + { "bl", 1, }, /* 0x14 */ + { "bne", 1, }, /* 0x15 */ + { "ble", 1, }, /* 0x16 */ + { "bo", 1, }, /* 0x17 */ + { "faultno", 0, }, /* 0x18 */ + { "faultg", 0, }, /* 0x19 */ + { "faulte", 0, }, /* 0x1a */ + { "faultge", 0, }, /* 0x1b */ + { "faultl", 0, }, /* 0x1c */ + { "faultne", 0, }, /* 0x1d */ + { "faultle", 0, }, /* 0x1e */ + { "faulto", 0, }, /* 0x1f */ + }; + + i = (word1 >> 24) & 0xff; + if ((ctrl_tab[i].name == NULL) || ((word1 & 1) != 0)) + { + invalid (word1); + return; + } + + (*info->fprintf_func) (stream, ctrl_tab[i].name); + if (word1 & 2) + /* Predicts branch not taken. */ + (*info->fprintf_func) (stream, ".f"); + + if (ctrl_tab[i].numops == 1) + { + /* Extract displacement and convert to address. */ + word1 &= 0x00ffffff; + + if (word1 & 0x00800000) + { + /* Sign bit is set. */ + word1 |= (-1 & ~0xffffff); /* Sign extend. */ + } + + (*info->fprintf_func) (stream, "\t"); + print_addr (word1 + memaddr); + } +} + +/* COBR format. */ + +static void +cobr (memaddr, word1, word2) + bfd_vma memaddr; + unsigned long word1; + unsigned long word2 ATTRIBUTE_UNUSED; +{ + int src1; + int src2; + int i; + + static const struct tabent cobr_tab[] = { + { "testno", 1, }, /* 0x20 */ + { "testg", 1, }, /* 0x21 */ + { "teste", 1, }, /* 0x22 */ + { "testge", 1, }, /* 0x23 */ + { "testl", 1, }, /* 0x24 */ + { "testne", 1, }, /* 0x25 */ + { "testle", 1, }, /* 0x26 */ + { "testo", 1, }, /* 0x27 */ + { NULL, 0, }, /* 0x28 */ + { NULL, 0, }, /* 0x29 */ + { NULL, 0, }, /* 0x2a */ + { NULL, 0, }, /* 0x2b */ + { NULL, 0, }, /* 0x2c */ + { NULL, 0, }, /* 0x2d */ + { NULL, 0, }, /* 0x2e */ + { NULL, 0, }, /* 0x2f */ + { "bbc", 3, }, /* 0x30 */ + { "cmpobg", 3, }, /* 0x31 */ + { "cmpobe", 3, }, /* 0x32 */ + { "cmpobge",3, }, /* 0x33 */ + { "cmpobl", 3, }, /* 0x34 */ + { "cmpobne",3, }, /* 0x35 */ + { "cmpoble",3, }, /* 0x36 */ + { "bbs", 3, }, /* 0x37 */ + { "cmpibno",3, }, /* 0x38 */ + { "cmpibg", 3, }, /* 0x39 */ + { "cmpibe", 3, }, /* 0x3a */ + { "cmpibge",3, }, /* 0x3b */ + { "cmpibl", 3, }, /* 0x3c */ + { "cmpibne",3, }, /* 0x3d */ + { "cmpible",3, }, /* 0x3e */ + { "cmpibo", 3, }, /* 0x3f */ + }; + + i = ((word1 >> 24) & 0xff) - 0x20; + if (cobr_tab[i].name == NULL) + { + invalid (word1); + return; + } + + (*info->fprintf_func) (stream, cobr_tab[i].name); + + /* Predicts branch not taken. */ + if (word1 & 2) + (*info->fprintf_func) (stream, ".f"); + + (*info->fprintf_func) (stream, "\t"); + + src1 = (word1 >> 19) & 0x1f; + src2 = (word1 >> 14) & 0x1f; + + if (word1 & 0x02000) + /* M1 is 1 */ + (*info->fprintf_func) (stream, "%d", src1); + else + (*info->fprintf_func) (stream, reg_names[src1]); + + if (cobr_tab[i].numops > 1) + { + if (word1 & 1) + /* S2 is 1. */ + (*info->fprintf_func) (stream, ",sf%d,", src2); + else + /* S1 is 0. */ + (*info->fprintf_func) (stream, ",%s,", reg_names[src2]); + + /* Extract displacement and convert to address. */ + word1 &= 0x00001ffc; + if (word1 & 0x00001000) + /* Negative displacement. */ + word1 |= (-1 & ~0x1fff); /* Sign extend. */ + + print_addr (memaddr + word1); + } +} + +/* MEM format. */ +/* Returns instruction length: 4 or 8. */ + +static int +mem (memaddr, word1, word2, noprint) + bfd_vma memaddr; + unsigned long word1, word2; + int noprint; /* If TRUE, return instruction length, but + don't output any text. */ +{ + int i, j; + int len; + int mode; + int offset; + const char *reg1, *reg2, *reg3; + + /* This lookup table is too sparse to make it worth typing in, but not + so large as to make a sparse array necessary. We create the table + at runtime. */ + + /* NOTE: In this table, the meaning of 'numops' is: + 1: single operand + 2: 2 operands, load instruction + -2: 2 operands, store instruction. */ + static struct tabent *mem_tab; + /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ +#define MEM_MIN 0x80 +#define MEM_MAX 0xcf +#define MEM_SIZ ( * sizeof(struct tabent)) + + static const struct sparse_tabent mem_init[] = { + { 0x80, "ldob", 2 }, + { 0x82, "stob", -2 }, + { 0x84, "bx", 1 }, + { 0x85, "balx", 2 }, + { 0x86, "callx", 1 }, + { 0x88, "ldos", 2 }, + { 0x8a, "stos", -2 }, + { 0x8c, "lda", 2 }, + { 0x90, "ld", 2 }, + { 0x92, "st", -2 }, + { 0x98, "ldl", 2 }, + { 0x9a, "stl", -2 }, + { 0xa0, "ldt", 2 }, + { 0xa2, "stt", -2 }, + { 0xac, "dcinva", 1 }, + { 0xb0, "ldq", 2 }, + { 0xb2, "stq", -2 }, + { 0xc0, "ldib", 2 }, + { 0xc2, "stib", -2 }, + { 0xc8, "ldis", 2 }, + { 0xca, "stis", -2 }, + { 0, NULL, 0 } + }; + static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1]; + + if (mem_tab == NULL) + { + mem_tab = mem_tab_buf; + + for (i = 0; mem_init[i].opcode != 0; i++) + { + j = mem_init[i].opcode - MEM_MIN; + mem_tab[j].name = mem_init[i].name; + mem_tab[j].numops = mem_init[i].numops; + } + } + + i = ((word1 >> 24) & 0xff) - MEM_MIN; + mode = (word1 >> 10) & 0xf; + + if ((mem_tab[i].name != NULL) /* Valid instruction */ + && ((mode == 5) || (mode >= 12))) + /* With 32-bit displacement. */ + len = 8; + else + len = 4; + + if (noprint) + return len; + + if ((mem_tab[i].name == NULL) || (mode == 6)) + { + invalid (word1); + return len; + } + + (*info->fprintf_func) (stream, "%s\t", mem_tab[i].name); + + reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */ + reg2 = reg_names[ (word1 >> 14) & 0x1f ]; + reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */ + offset = word1 & 0xfff; /* MEMA only */ + + switch (mem_tab[i].numops) + { + case 2: /* LOAD INSTRUCTION */ + if (mode & 4) + { /* MEMB FORMAT */ + ea (memaddr, mode, reg2, reg3, word1, word2); + (*info->fprintf_func) (stream, ",%s", reg1); + } + else + { /* MEMA FORMAT */ + (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); + + if (mode & 8) + (*info->fprintf_func) (stream, "(%s)", reg2); + + (*info->fprintf_func)(stream, ",%s", reg1); + } + break; + + case -2: /* STORE INSTRUCTION */ + if (mode & 4) + { + /* MEMB FORMAT */ + (*info->fprintf_func) (stream, "%s,", reg1); + ea (memaddr, mode, reg2, reg3, word1, word2); + } + else + { + /* MEMA FORMAT */ + (*info->fprintf_func) (stream, "%s,0x%x", reg1, (unsigned) offset); + + if (mode & 8) + (*info->fprintf_func) (stream, "(%s)", reg2); + } + break; + + case 1: /* BX/CALLX INSTRUCTION */ + if (mode & 4) + { + /* MEMB FORMAT */ + ea (memaddr, mode, reg2, reg3, word1, word2); + } + else + { + /* MEMA FORMAT */ + (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); + if (mode & 8) + (*info->fprintf_func) (stream, "(%s)", reg2); + } + break; + } + + return len; +} + +/* REG format. */ + +static void +reg (word1) + unsigned long word1; +{ + int i, j; + int opcode; + int fp; + int m1, m2, m3; + int s1, s2; + int src, src2, dst; + char *mnemp; + + /* This lookup table is too sparse to make it worth typing in, but not + so large as to make a sparse array necessary. We create the table + at runtime. */ + + /* NOTE: In this table, the meaning of 'numops' is: + 1: single operand, which is NOT a destination. + -1: single operand, which IS a destination. + 2: 2 operands, the 2nd of which is NOT a destination. + -2: 2 operands, the 2nd of which IS a destination. + 3: 3 operands + + If an opcode mnemonic begins with "F", it is a floating-point + opcode (the "F" is not printed). */ + + static struct tabent *reg_tab; + static const struct sparse_tabent reg_init[] = + { +#define REG_MIN 0x580 + { 0x580, "notbit", 3 }, + { 0x581, "and", 3 }, + { 0x582, "andnot", 3 }, + { 0x583, "setbit", 3 }, + { 0x584, "notand", 3 }, + { 0x586, "xor", 3 }, + { 0x587, "or", 3 }, + { 0x588, "nor", 3 }, + { 0x589, "xnor", 3 }, + { 0x58a, "not", -2 }, + { 0x58b, "ornot", 3 }, + { 0x58c, "clrbit", 3 }, + { 0x58d, "notor", 3 }, + { 0x58e, "nand", 3 }, + { 0x58f, "alterbit", 3 }, + { 0x590, "addo", 3 }, + { 0x591, "addi", 3 }, + { 0x592, "subo", 3 }, + { 0x593, "subi", 3 }, + { 0x594, "cmpob", 2 }, + { 0x595, "cmpib", 2 }, + { 0x596, "cmpos", 2 }, + { 0x597, "cmpis", 2 }, + { 0x598, "shro", 3 }, + { 0x59a, "shrdi", 3 }, + { 0x59b, "shri", 3 }, + { 0x59c, "shlo", 3 }, + { 0x59d, "rotate", 3 }, + { 0x59e, "shli", 3 }, + { 0x5a0, "cmpo", 2 }, + { 0x5a1, "cmpi", 2 }, + { 0x5a2, "concmpo", 2 }, + { 0x5a3, "concmpi", 2 }, + { 0x5a4, "cmpinco", 3 }, + { 0x5a5, "cmpinci", 3 }, + { 0x5a6, "cmpdeco", 3 }, + { 0x5a7, "cmpdeci", 3 }, + { 0x5ac, "scanbyte", 2 }, + { 0x5ad, "bswap", -2 }, + { 0x5ae, "chkbit", 2 }, + { 0x5b0, "addc", 3 }, + { 0x5b2, "subc", 3 }, + { 0x5b4, "intdis", 0 }, + { 0x5b5, "inten", 0 }, + { 0x5cc, "mov", -2 }, + { 0x5d8, "eshro", 3 }, + { 0x5dc, "movl", -2 }, + { 0x5ec, "movt", -2 }, + { 0x5fc, "movq", -2 }, + { 0x600, "synmov", 2 }, + { 0x601, "synmovl", 2 }, + { 0x602, "synmovq", 2 }, + { 0x603, "cmpstr", 3 }, + { 0x604, "movqstr", 3 }, + { 0x605, "movstr", 3 }, + { 0x610, "atmod", 3 }, + { 0x612, "atadd", 3 }, + { 0x613, "inspacc", -2 }, + { 0x614, "ldphy", -2 }, + { 0x615, "synld", -2 }, + { 0x617, "fill", 3 }, + { 0x630, "sdma", 3 }, + { 0x631, "udma", 0 }, + { 0x640, "spanbit", -2 }, + { 0x641, "scanbit", -2 }, + { 0x642, "daddc", 3 }, + { 0x643, "dsubc", 3 }, + { 0x644, "dmovt", -2 }, + { 0x645, "modac", 3 }, + { 0x646, "condrec", -2 }, + { 0x650, "modify", 3 }, + { 0x651, "extract", 3 }, + { 0x654, "modtc", 3 }, + { 0x655, "modpc", 3 }, + { 0x656, "receive", -2 }, + { 0x658, "intctl", -2 }, + { 0x659, "sysctl", 3 }, + { 0x65b, "icctl", 3 }, + { 0x65c, "dcctl", 3 }, + { 0x65d, "halt", 0 }, + { 0x660, "calls", 1 }, + { 0x662, "send", 3 }, + { 0x663, "sendserv", 1 }, + { 0x664, "resumprcs", 1 }, + { 0x665, "schedprcs", 1 }, + { 0x666, "saveprcs", 0 }, + { 0x668, "condwait", 1 }, + { 0x669, "wait", 1 }, + { 0x66a, "signal", 1 }, + { 0x66b, "mark", 0 }, + { 0x66c, "fmark", 0 }, + { 0x66d, "flushreg", 0 }, + { 0x66f, "syncf", 0 }, + { 0x670, "emul", 3 }, + { 0x671, "ediv", 3 }, + { 0x673, "ldtime", -1 }, + { 0x674, "Fcvtir", -2 }, + { 0x675, "Fcvtilr", -2 }, + { 0x676, "Fscalerl", 3 }, + { 0x677, "Fscaler", 3 }, + { 0x680, "Fatanr", 3 }, + { 0x681, "Flogepr", 3 }, + { 0x682, "Flogr", 3 }, + { 0x683, "Fremr", 3 }, + { 0x684, "Fcmpor", 2 }, + { 0x685, "Fcmpr", 2 }, + { 0x688, "Fsqrtr", -2 }, + { 0x689, "Fexpr", -2 }, + { 0x68a, "Flogbnr", -2 }, + { 0x68b, "Froundr", -2 }, + { 0x68c, "Fsinr", -2 }, + { 0x68d, "Fcosr", -2 }, + { 0x68e, "Ftanr", -2 }, + { 0x68f, "Fclassr", 1 }, + { 0x690, "Fatanrl", 3 }, + { 0x691, "Flogeprl", 3 }, + { 0x692, "Flogrl", 3 }, + { 0x693, "Fremrl", 3 }, + { 0x694, "Fcmporl", 2 }, + { 0x695, "Fcmprl", 2 }, + { 0x698, "Fsqrtrl", -2 }, + { 0x699, "Fexprl", -2 }, + { 0x69a, "Flogbnrl", -2 }, + { 0x69b, "Froundrl", -2 }, + { 0x69c, "Fsinrl", -2 }, + { 0x69d, "Fcosrl", -2 }, + { 0x69e, "Ftanrl", -2 }, + { 0x69f, "Fclassrl", 1 }, + { 0x6c0, "Fcvtri", -2 }, + { 0x6c1, "Fcvtril", -2 }, + { 0x6c2, "Fcvtzri", -2 }, + { 0x6c3, "Fcvtzril", -2 }, + { 0x6c9, "Fmovr", -2 }, + { 0x6d9, "Fmovrl", -2 }, + { 0x6e1, "Fmovre", -2 }, + { 0x6e2, "Fcpysre", 3 }, + { 0x6e3, "Fcpyrsre", 3 }, + { 0x701, "mulo", 3 }, + { 0x708, "remo", 3 }, + { 0x70b, "divo", 3 }, + { 0x741, "muli", 3 }, + { 0x748, "remi", 3 }, + { 0x749, "modi", 3 }, + { 0x74b, "divi", 3 }, + { 0x780, "addono", 3 }, + { 0x781, "addino", 3 }, + { 0x782, "subono", 3 }, + { 0x783, "subino", 3 }, + { 0x784, "selno", 3 }, + { 0x78b, "Fdivr", 3 }, + { 0x78c, "Fmulr", 3 }, + { 0x78d, "Fsubr", 3 }, + { 0x78f, "Faddr", 3 }, + { 0x790, "addog", 3 }, + { 0x791, "addig", 3 }, + { 0x792, "subog", 3 }, + { 0x793, "subig", 3 }, + { 0x794, "selg", 3 }, + { 0x79b, "Fdivrl", 3 }, + { 0x79c, "Fmulrl", 3 }, + { 0x79d, "Fsubrl", 3 }, + { 0x79f, "Faddrl", 3 }, + { 0x7a0, "addoe", 3 }, + { 0x7a1, "addie", 3 }, + { 0x7a2, "suboe", 3 }, + { 0x7a3, "subie", 3 }, + { 0x7a4, "sele", 3 }, + { 0x7b0, "addoge", 3 }, + { 0x7b1, "addige", 3 }, + { 0x7b2, "suboge", 3 }, + { 0x7b3, "subige", 3 }, + { 0x7b4, "selge", 3 }, + { 0x7c0, "addol", 3 }, + { 0x7c1, "addil", 3 }, + { 0x7c2, "subol", 3 }, + { 0x7c3, "subil", 3 }, + { 0x7c4, "sell", 3 }, + { 0x7d0, "addone", 3 }, + { 0x7d1, "addine", 3 }, + { 0x7d2, "subone", 3 }, + { 0x7d3, "subine", 3 }, + { 0x7d4, "selne", 3 }, + { 0x7e0, "addole", 3 }, + { 0x7e1, "addile", 3 }, + { 0x7e2, "subole", 3 }, + { 0x7e3, "subile", 3 }, + { 0x7e4, "selle", 3 }, + { 0x7f0, "addoo", 3 }, + { 0x7f1, "addio", 3 }, + { 0x7f2, "suboo", 3 }, + { 0x7f3, "subio", 3 }, + { 0x7f4, "selo", 3 }, +#define REG_MAX 0x7f4 + { 0, NULL, 0 } + }; + static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1]; + + if (reg_tab == NULL) + { + reg_tab = reg_tab_buf; + + for (i = 0; reg_init[i].opcode != 0; i++) + { + j = reg_init[i].opcode - REG_MIN; + reg_tab[j].name = reg_init[i].name; + reg_tab[j].numops = reg_init[i].numops; + } + } + + opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf); + i = opcode - REG_MIN; + + if ((opcodeREG_MAX) || (reg_tab[i].name==NULL)) + { + invalid (word1); + return; + } + + mnemp = reg_tab[i].name; + if (*mnemp == 'F') + { + fp = 1; + mnemp++; + } + else + { + fp = 0; + } + + (*info->fprintf_func) (stream, mnemp); + + s1 = (word1 >> 5) & 1; + s2 = (word1 >> 6) & 1; + m1 = (word1 >> 11) & 1; + m2 = (word1 >> 12) & 1; + m3 = (word1 >> 13) & 1; + src = word1 & 0x1f; + src2 = (word1 >> 14) & 0x1f; + dst = (word1 >> 19) & 0x1f; + + if (reg_tab[i].numops != 0) + { + (*info->fprintf_func) (stream, "\t"); + + switch (reg_tab[i].numops) + { + case 1: + regop (m1, s1, src, fp); + break; + case -1: + dstop (m3, dst, fp); + break; + case 2: + regop (m1, s1, src, fp); + (*info->fprintf_func) (stream, ","); + regop (m2, s2, src2, fp); + break; + case -2: + regop (m1, s1, src, fp); + (*info->fprintf_func) (stream, ","); + dstop (m3, dst, fp); + break; + case 3: + regop (m1, s1, src, fp); + (*info->fprintf_func) (stream, ","); + regop (m2, s2, src2, fp); + (*info->fprintf_func) (stream, ","); + dstop (m3, dst, fp); + break; + } + } +} + +/* Print out effective address for memb instructions. */ + +static void +ea (memaddr, mode, reg2, reg3, word1, word2) + bfd_vma memaddr; + int mode; + const char *reg2; + const char *reg3; + int word1; + unsigned int word2; +{ + int scale; + static const int scale_tab[] = { 1, 2, 4, 8, 16 }; + + scale = (word1 >> 7) & 0x07; + + if ((scale > 4) || (((word1 >> 5) & 0x03) != 0)) + { + invalid (word1); + return; + } + scale = scale_tab[scale]; + + switch (mode) + { + case 4: /* (reg) */ + (*info->fprintf_func)( stream, "(%s)", reg2 ); + break; + case 5: /* displ+8(ip) */ + print_addr (word2 + 8 + memaddr); + break; + case 7: /* (reg)[index*scale] */ + if (scale == 1) + (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3); + else + (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale); + break; + case 12: /* displacement */ + print_addr ((bfd_vma) word2); + break; + case 13: /* displ(reg) */ + print_addr ((bfd_vma) word2); + (*info->fprintf_func) (stream, "(%s)", reg2); + break; + case 14: /* displ[index*scale] */ + print_addr ((bfd_vma) word2); + if (scale == 1) + (*info->fprintf_func) (stream, "[%s]", reg3); + else + (*info->fprintf_func) (stream, "[%s*%d]", reg3, scale); + break; + case 15: /* displ(reg)[index*scale] */ + print_addr ((bfd_vma) word2); + if (scale == 1) + (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3); + else + (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale); + break; + default: + invalid (word1); + return; + } +} + + +/* Register Instruction Operand. */ + +static void +regop (mode, spec, reg, fp) + int mode, spec, reg, fp; +{ + if (fp) + { + /* Floating point instruction. */ + if (mode == 1) + { + /* FP operand. */ + switch (reg) + { + case 0: (*info->fprintf_func) (stream, "fp0"); + break; + case 1: (*info->fprintf_func) (stream, "fp1"); + break; + case 2: (*info->fprintf_func) (stream, "fp2"); + break; + case 3: (*info->fprintf_func) (stream, "fp3"); + break; + case 16: (*info->fprintf_func) (stream, "0f0.0"); + break; + case 22: (*info->fprintf_func) (stream, "0f1.0"); + break; + default: (*info->fprintf_func) (stream, "?"); + break; + } + } + else + { + /* Non-FP register. */ + (*info->fprintf_func) (stream, reg_names[reg]); + } + } + else + { + /* Not floating point. */ + if (mode == 1) + { + /* Literal. */ + (*info->fprintf_func) (stream, "%d", reg); + } + else + { + /* Register. */ + if (spec == 0) + (*info->fprintf_func) (stream, reg_names[reg]); + else + (*info->fprintf_func) (stream, "sf%d", reg); + } + } +} + +/* Register Instruction Destination Operand. */ + +static void +dstop (mode, reg, fp) + int mode, reg, fp; +{ + /* 'dst' operand can't be a literal. On non-FP instructions, register + mode is assumed and "m3" acts as if were "s3"; on FP-instructions, + sf registers are not allowed so m3 acts normally. */ + if (fp) + regop (mode, 0, reg, fp); + else + regop (0, mode, reg, fp); +} + +static void +invalid (word1) + int word1; +{ + (*info->fprintf_func) (stream, ".word\t0x%08x", (unsigned) word1); +} + +static void +print_addr (a) + bfd_vma a; +{ + (*info->print_address_func) (a, info); +} + +static void +put_abs (word1, word2) + unsigned long word1 ATTRIBUTE_UNUSED; + unsigned long word2 ATTRIBUTE_UNUSED; +{ +#ifdef IN_GDB + return; +#else + int len; + + switch ((word1 >> 28) & 0xf) + { + case 0x8: + case 0x9: + case 0xa: + case 0xb: + case 0xc: + /* MEM format instruction. */ + len = mem (0, word1, word2, 1); + break; + default: + len = 4; + break; + } + + if (len == 8) + (*info->fprintf_func) (stream, "%08x %08x\t", word1, word2); + else + (*info->fprintf_func) (stream, "%08x \t", word1); +#endif +} diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c new file mode 100644 index 0000000..45f60eb --- /dev/null +++ b/opcodes/ia64-asmtab.c @@ -0,0 +1,7436 @@ +/* This file is automatically generated by ia64-gen. Do not edit! */ +static const char *ia64_strings[] = { + "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", + "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", + "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1", + "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1", + "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit", + "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm", + "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4", + "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin", + "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for", + "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax", + "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma", + "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc", + "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge", + "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc", + "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe", + "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs", + "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2", + "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt", + "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz", + "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1", + "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1", + "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe", + "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2", + "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi", + "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf", + "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt", + "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8", + "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync", + "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc", + "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w", + "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma", + "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4", +}; + +static const struct ia64_dependency +dependencies[] = { + { "ALAT", 0, 0, 0, -1, NULL, }, + { "AR[BSP]", 26, 0, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, + { "AR[CCV]", 26, 0, 2, 32, NULL, }, + { "AR[EC]", 26, 0, 2, 66, NULL, }, + { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, + { "AR[ITC]", 26, 0, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, + { "AR[LC]", 26, 0, 2, 65, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 0, 64, NULL, }, + { "AR[RNAT]", 26, 0, 2, 19, NULL, }, + { "AR[RSC]", 26, 0, 2, 16, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, + { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 0, -1, NULL, }, + { "CPUID#", 7, 0, 5, -1, NULL, }, + { "CR[CMCV]", 27, 0, 3, 74, NULL, }, + { "CR[DCR]", 27, 0, 3, 0, NULL, }, + { "CR[EOI]", 27, 0, 7, 67, "SC Section 10.8.3.4", }, + { "CR[GPTA]", 27, 0, 3, 9, NULL, }, + { "CR[IFA]", 27, 0, 1, 20, NULL, }, + { "CR[IFA]", 27, 0, 3, 20, NULL, }, + { "CR[IFS]", 27, 0, 3, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IHA]", 27, 0, 3, 25, NULL, }, + { "CR[IIM]", 27, 0, 3, 24, NULL, }, + { "CR[IIP]", 27, 0, 3, 19, NULL, }, + { "CR[IIP]", 27, 0, 1, 19, NULL, }, + { "CR[IIPA]", 27, 0, 3, 22, NULL, }, + { "CR[IPSR]", 27, 0, 3, 16, NULL, }, + { "CR[IPSR]", 27, 0, 1, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, }, + { "CR[ISR]", 27, 0, 3, 17, NULL, }, + { "CR[ITIR]", 27, 0, 3, 21, NULL, }, + { "CR[ITIR]", 27, 0, 1, 21, NULL, }, + { "CR[ITM]", 27, 0, 3, 1, NULL, }, + { "CR[ITV]", 27, 0, 3, 72, NULL, }, + { "CR[IVA]", 27, 0, 4, 2, NULL, }, + { "CR[IVR]", 27, 0, 7, 65, "SC Section 10.8.3.2", }, + { "CR[LID]", 27, 0, 7, 64, "SC Section 10.8.3.1", }, + { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, }, + { "CR[PMV]", 27, 0, 3, 73, NULL, }, + { "CR[PTA]", 27, 0, 3, 8, NULL, }, + { "CR[TPR]", 27, 0, 3, 66, NULL, }, + { "CR[TPR]", 27, 0, 7, 66, "SC Section 10.8.3.3", }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, }, + { "DBR#", 11, 0, 2, -1, NULL, }, + { "DBR#", 11, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC", 0, 0, 0, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 0, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, }, + { "GR0", 14, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, }, + { "IBR#", 16, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 3, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "IP", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 0, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "memory", 0, 0, 0, -1, NULL, }, + { "MSR#", 18, 0, 5, -1, NULL, }, + { "PKR#", 19, 0, 3, -1, NULL, }, + { "PKR#", 19, 0, 0, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 7, -1, "SC+3 Section 12.1.1", }, + { "PMD#", 21, 0, 2, -1, NULL, }, + { "PR0", 0, 0, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 0, -1, NULL, }, + { "PSR.ac", 28, 0, 1, 3, NULL, }, + { "PSR.ac", 28, 0, 3, 3, NULL, }, + { "PSR.ac", 28, 0, 2, 3, NULL, }, + { "PSR.be", 28, 0, 1, 1, NULL, }, + { "PSR.be", 28, 0, 3, 1, NULL, }, + { "PSR.be", 28, 0, 2, 1, NULL, }, + { "PSR.bn", 28, 0, 2, 44, NULL, }, + { "PSR.cpl", 28, 0, 1, 32, NULL, }, + { "PSR.da", 28, 0, 3, 38, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.db", 28, 0, 2, 24, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.dd", 28, 0, 3, 39, NULL, }, + { "PSR.dfh", 28, 0, 3, 19, NULL, }, + { "PSR.dfh", 28, 0, 2, 19, NULL, }, + { "PSR.dfl", 28, 0, 3, 18, NULL, }, + { "PSR.dfl", 28, 0, 2, 18, NULL, }, + { "PSR.di", 28, 0, 3, 22, NULL, }, + { "PSR.di", 28, 0, 2, 22, NULL, }, + { "PSR.dt", 28, 0, 3, 17, NULL, }, + { "PSR.dt", 28, 0, 2, 17, NULL, }, + { "PSR.ed", 28, 0, 3, 43, NULL, }, + { "PSR.i", 28, 0, 2, 14, NULL, }, + { "PSR.i", 28, 0, 3, 14, NULL, }, + { "PSR.ia", 28, 0, 0, 14, NULL, }, + { "PSR.ic", 28, 0, 2, 13, NULL, }, + { "PSR.ic", 28, 0, 3, 13, NULL, }, + { "PSR.id", 28, 0, 0, 14, NULL, }, + { "PSR.is", 28, 0, 0, 14, NULL, }, + { "PSR.it", 28, 0, 3, 14, NULL, }, + { "PSR.lp", 28, 0, 2, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.mc", 28, 0, 0, 35, NULL, }, + { "PSR.mfh", 28, 0, 2, 5, NULL, }, + { "PSR.mfl", 28, 0, 2, 4, NULL, }, + { "PSR.pk", 28, 0, 3, 15, NULL, }, + { "PSR.pk", 28, 0, 2, 15, NULL, }, + { "PSR.pp", 28, 0, 2, 21, NULL, }, + { "PSR.ri", 28, 0, 0, 41, NULL, }, + { "PSR.rt", 28, 0, 2, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.si", 28, 0, 2, 23, NULL, }, + { "PSR.si", 28, 0, 3, 23, NULL, }, + { "PSR.sp", 28, 0, 2, 20, NULL, }, + { "PSR.sp", 28, 0, 3, 20, NULL, }, + { "PSR.ss", 28, 0, 3, 40, NULL, }, + { "PSR.tb", 28, 0, 3, 26, NULL, }, + { "PSR.tb", 28, 0, 2, 26, NULL, }, + { "PSR.up", 28, 0, 2, 2, NULL, }, + { "RR#", 25, 0, 3, -1, NULL, }, + { "RR#", 25, 0, 2, -1, NULL, }, + { "RSE", 29, 0, 2, -1, NULL, }, + { "ALAT", 0, 1, 0, -1, NULL, }, + { "AR[BSP]", 26, 1, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, + { "AR[CCV]", 26, 1, 2, 32, NULL, }, + { "AR[EC]", 26, 1, 2, 66, NULL, }, + { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, + { "AR[ITC]", 26, 1, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, + { "AR[LC]", 26, 1, 2, 65, NULL, }, + { "AR[PFS]", 26, 1, 0, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[RNAT]", 26, 1, 2, 19, NULL, }, + { "AR[RSC]", 26, 1, 2, 16, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, }, + { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, + { "CFM", 6, 1, 2, -1, NULL, }, + { "CPUID#", 7, 1, 0, -1, NULL, }, + { "CR[CMCV]", 27, 1, 2, 74, NULL, }, + { "CR[DCR]", 27, 1, 2, 0, NULL, }, + { "CR[EOI]", 27, 1, 7, 67, "SC Section 10.8.3.4", }, + { "CR[GPTA]", 27, 1, 2, 9, NULL, }, + { "CR[IFA]", 27, 1, 2, 20, NULL, }, + { "CR[IFS]", 27, 1, 2, 23, NULL, }, + { "CR[IHA]", 27, 1, 2, 25, NULL, }, + { "CR[IIM]", 27, 1, 2, 24, NULL, }, + { "CR[IIP]", 27, 1, 2, 19, NULL, }, + { "CR[IIPA]", 27, 1, 2, 22, NULL, }, + { "CR[IPSR]", 27, 1, 2, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, }, + { "CR[ISR]", 27, 1, 2, 17, NULL, }, + { "CR[ITIR]", 27, 1, 2, 21, NULL, }, + { "CR[ITM]", 27, 1, 2, 1, NULL, }, + { "CR[ITV]", 27, 1, 2, 72, NULL, }, + { "CR[IVA]", 27, 1, 2, 2, NULL, }, + { "CR[IVR]", 27, 1, 7, 65, "SC", }, + { "CR[LID]", 27, 1, 7, 64, "SC", }, + { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, }, + { "CR[PMV]", 27, 1, 2, 73, NULL, }, + { "CR[PTA]", 27, 1, 2, 8, NULL, }, + { "CR[TPR]", 27, 1, 2, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, }, + { "DBR#", 11, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 0, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 0, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, }, + { "GR0", 14, 1, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, }, + { "IBR#", 16, 1, 2, -1, NULL, }, + { "InService*", 17, 1, 7, -1, "SC", }, + { "IP", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 0, -1, NULL, }, + { "memory", 0, 1, 0, -1, NULL, }, + { "MSR#", 18, 1, 7, -1, "SC", }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 2, -1, NULL, }, + { "PMC#", 20, 1, 2, -1, NULL, }, + { "PMD#", 21, 1, 2, -1, NULL, }, + { "PR0", 0, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PSR.ac", 28, 1, 2, 3, NULL, }, + { "PSR.be", 28, 1, 2, 1, NULL, }, + { "PSR.bn", 28, 1, 2, 44, NULL, }, + { "PSR.cpl", 28, 1, 2, 32, NULL, }, + { "PSR.da", 28, 1, 2, 38, NULL, }, + { "PSR.db", 28, 1, 2, 24, NULL, }, + { "PSR.dd", 28, 1, 2, 39, NULL, }, + { "PSR.dfh", 28, 1, 2, 19, NULL, }, + { "PSR.dfl", 28, 1, 2, 18, NULL, }, + { "PSR.di", 28, 1, 2, 22, NULL, }, + { "PSR.dt", 28, 1, 2, 17, NULL, }, + { "PSR.ed", 28, 1, 2, 43, NULL, }, + { "PSR.i", 28, 1, 2, 14, NULL, }, + { "PSR.ia", 28, 1, 2, 14, NULL, }, + { "PSR.ic", 28, 1, 2, 13, NULL, }, + { "PSR.id", 28, 1, 2, 14, NULL, }, + { "PSR.is", 28, 1, 2, 14, NULL, }, + { "PSR.it", 28, 1, 2, 14, NULL, }, + { "PSR.lp", 28, 1, 2, 25, NULL, }, + { "PSR.mc", 28, 1, 2, 35, NULL, }, + { "PSR.mfh", 28, 1, 0, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfl", 28, 1, 0, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.pk", 28, 1, 2, 15, NULL, }, + { "PSR.pp", 28, 1, 2, 21, NULL, }, + { "PSR.ri", 28, 1, 2, 41, NULL, }, + { "PSR.rt", 28, 1, 2, 27, NULL, }, + { "PSR.si", 28, 1, 2, 23, NULL, }, + { "PSR.sp", 28, 1, 2, 20, NULL, }, + { "PSR.ss", 28, 1, 2, 40, NULL, }, + { "PSR.tb", 28, 1, 2, 26, NULL, }, + { "PSR.up", 28, 1, 2, 2, NULL, }, + { "RR#", 25, 1, 2, -1, NULL, }, + { "RSE", 29, 1, 2, -1, NULL, }, + { "PR63", 24, 2, 6, -1, NULL, }, +}; + +static const short dep0[] = { + 88, 252, 2131, 2297, +}; + +static const short dep1[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, + 20605, +}; + +static const short dep2[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2317, 2318, 2321, + 2322, 2325, 2326, +}; + +static const short dep3[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, 4127, 20605, +}; + +static const short dep4[] = { + 88, 252, 22637, 22638, 22640, 22641, 22643, 22644, 22646, 22794, 22797, 22798, + 22801, 22802, 22805, 22806, +}; + +static const short dep5[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep6[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2315, 2317, 2319, + 2321, 2323, 2325, +}; + +static const short dep7[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2315, + 2318, 2319, 2322, 2323, 2326, 4127, 20605, +}; + +static const short dep8[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2316, 2318, 2320, + 2322, 2324, 2326, +}; + +static const short dep9[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2316, + 2317, 2320, 2321, 2324, 2325, 4127, 20605, +}; + +static const short dep10[] = { + 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2315, 2316, 2317, + 2318, 2319, 2320, 2321, 2322, 2323, 2324, 2325, 2326, +}; + +static const short dep11[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2315, + 2316, 2317, 2318, 2319, 2320, 2321, 2322, 2323, 2324, 2325, 2326, 4127, 20605, + +}; + +static const short dep12[] = { + 88, 252, 2364, +}; + +static const short dep13[] = { + 32, 33, 88, 148, 166, 167, 252, 2074, 2075, 2157, 2159, 2160, 2162, 2163, + 2165, 2166, 4127, +}; + +static const short dep14[] = { + 88, 147, 252, 295, 2364, 28844, 28987, +}; + +static const short dep15[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, + 23, 24, 25, 32, 33, 88, 136, 148, 166, 167, 252, 295, 2074, 2075, 2157, 2159, + 2160, 2162, 2163, 2165, 2166, 4127, 28844, 28987, +}; + +static const short dep16[] = { + 1, 4, 32, 88, 126, 174, 177, 211, 252, 282, 2364, 28844, 28987, +}; + +static const short dep17[] = { + 1, 18, 20, 30, 32, 33, 88, 148, 150, 151, 166, 167, 174, 177, 211, 252, 282, + 2074, 2075, 2157, 2159, 2160, 2162, 2163, 2165, 2166, 4127, 28844, 28987, + +}; + +static const short dep18[] = { + 1, 32, 43, 88, 174, 211, 218, 252, 28844, 28987, +}; + +static const short dep19[] = { + 1, 30, 32, 33, 88, 145, 166, 174, 211, 218, 252, 4127, 28844, 28987, +}; + +static const short dep20[] = { + 32, 88, 211, 252, +}; + +static const short dep21[] = { + 88, 166, 211, 252, +}; + +static const short dep22[] = { + 1, 32, 88, 120, 121, 123, 124, 125, 126, 127, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 142, 143, 144, 145, 146, 147, 148, 151, 152, 153, + 154, 155, 156, 157, 158, 161, 162, 163, 164, 165, 166, 167, 168, 169, 174, + 211, 252, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, + 292, 293, 294, 295, 296, 297, 298, 300, 301, 303, 304, 305, 306, 307, 308, + 309, 310, 311, 312, 313, 28844, 28987, +}; + +static const short dep23[] = { + 1, 30, 32, 33, 42, 43, 47, 50, 64, 88, 126, 166, 174, 211, 252, 279, 280, + 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, + 296, 297, 298, 300, 301, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, + 313, 4127, 28844, 28987, +}; + +static const short dep24[] = { + 88, 125, 252, 281, +}; + +static const short dep25[] = { + 88, 126, 166, 252, 281, +}; + +static const short dep26[] = { + 88, 126, 252, 282, +}; + +static const short dep27[] = { + 18, 19, 88, 89, 92, 96, 99, 126, 148, 166, 252, 282, +}; + +static const short dep28[] = { + 32, 33, 88, 166, 252, 2157, 2159, 2160, 2162, 2163, 2165, 2166, 4127, +}; + +static const short dep29[] = { + 1, 18, 32, 88, 174, 199, 200, 211, 252, 2074, 2255, 2258, 2364, 28844, 28987, + +}; + +static const short dep30[] = { + 1, 4, 30, 32, 33, 88, 126, 148, 166, 167, 174, 199, 201, 211, 252, 2074, 2075, + 2157, 2159, 2160, 2162, 2163, 2165, 2166, 2256, 2258, 4127, 28844, 28987, + +}; + +static const short dep31[] = { + 88, 252, +}; + +static const short dep32[] = { + 88, 166, 252, 2074, 2076, +}; + +static const short dep33[] = { + 32, 33, 88, 148, 166, 167, 252, 2157, 2159, 2160, 2162, 2163, 2165, 2166, + 4127, +}; + +static const short dep34[] = { + 4, 29, 30, 31, 88, 116, 117, 177, 211, 252, 277, 278, 2364, +}; + +static const short dep35[] = { + 4, 29, 32, 33, 88, 148, 166, 167, 177, 211, 252, 277, 278, 316, 2157, 2159, + 2160, 2162, 2163, 2165, 2166, 4127, +}; + +static const short dep36[] = { + 17, 88, 198, 252, 2364, +}; + +static const short dep37[] = { + 17, 32, 33, 88, 148, 166, 167, 198, 252, 2157, 2159, 2160, 2162, 2163, 2165, + 2166, 4127, +}; + +static const short dep38[] = { + 4, 17, 29, 30, 31, 88, 116, 117, 177, 198, 211, 252, 277, 278, 2364, +}; + +static const short dep39[] = { + 4, 17, 29, 32, 33, 88, 148, 166, 167, 177, 198, 211, 252, 277, 278, 316, 2157, + 2159, 2160, 2162, 2163, 2165, 2166, 4127, +}; + +static const short dep40[] = { + 1, 4, 30, 32, 33, 88, 126, 148, 166, 167, 174, 199, 201, 211, 252, 2157, 2159, + 2160, 2162, 2163, 2165, 2166, 2256, 2258, 4127, 28844, 28987, +}; + +static const short dep41[] = { + 88, 166, 252, +}; + +static const short dep42[] = { + 9, 88, 182, 183, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep43[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep44[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2127, 2295, + 18585, 18586, 18731, 18732, 18734, 18735, 22637, 22638, 22639, 22641, 22642, + 22644, 22645, 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep45[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, + 18733, 18734, 18736, 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep46[] = { + 10, 88, 185, 186, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep47[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep48[] = { + 11, 88, 188, 189, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep49[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep50[] = { + 12, 88, 191, 192, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, + 22802, 22805, 22806, +}; + +static const short dep51[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, + 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep52[] = { + 9, 88, 182, 183, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep53[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep54[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2127, 2295, + 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep55[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, + 18733, 18734, 18736, +}; + +static const short dep56[] = { + 10, 88, 185, 186, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep57[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep58[] = { + 11, 88, 188, 189, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep59[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep60[] = { + 12, 88, 191, 192, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + +}; + +static const short dep61[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep62[] = { + 88, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep63[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, + 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep64[] = { + 5, 88, 178, 252, +}; + +static const short dep65[] = { + 5, 32, 33, 88, 166, 178, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep66[] = { + 5, 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep67[] = { + 6, 88, 179, 252, +}; + +static const short dep68[] = { + 5, 32, 33, 88, 166, 179, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep69[] = { + 7, 88, 180, 252, +}; + +static const short dep70[] = { + 5, 32, 33, 88, 166, 180, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep71[] = { + 8, 88, 181, 252, +}; + +static const short dep72[] = { + 5, 32, 33, 88, 166, 181, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep73[] = { + 9, 88, 183, 184, 252, +}; + +static const short dep74[] = { + 32, 33, 88, 166, 183, 184, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep75[] = { + 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep76[] = { + 10, 88, 186, 187, 252, +}; + +static const short dep77[] = { + 32, 33, 88, 166, 186, 187, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep78[] = { + 11, 88, 189, 190, 252, +}; + +static const short dep79[] = { + 32, 33, 88, 166, 189, 190, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep80[] = { + 12, 88, 192, 193, 252, +}; + +static const short dep81[] = { + 32, 33, 88, 166, 192, 193, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep82[] = { + 9, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep83[] = { + 9, 10, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep84[] = { + 9, 11, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep85[] = { + 9, 12, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep86[] = { + 9, 88, 182, 183, 252, +}; + +static const short dep87[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep88[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, +}; + +static const short dep89[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep90[] = { + 10, 88, 185, 186, 252, +}; + +static const short dep91[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep92[] = { + 11, 88, 188, 189, 252, +}; + +static const short dep93[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep94[] = { + 12, 88, 191, 192, 252, +}; + +static const short dep95[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep96[] = { + 9, 88, 182, 183, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep97[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep98[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2157, 2158, + 2159, 2161, 2162, 2164, 2165, 2314, 2317, 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep99[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2314, 2317, 2318, 2321, 2322, + 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep100[] = { + 10, 88, 185, 186, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep101[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep102[] = { + 11, 88, 188, 189, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep103[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep104[] = { + 12, 88, 191, 192, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, +}; + +static const short dep105[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep106[] = { + 9, 88, 182, 183, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep107[] = { + 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep108[] = { + 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 22637, 22638, + 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, 22802, 22805, + 22806, +}; + +static const short dep109[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, + 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 4127, 16516, 16518, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep110[] = { + 10, 88, 185, 186, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep111[] = { + 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep112[] = { + 11, 88, 188, 189, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep113[] = { + 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep114[] = { + 12, 88, 191, 192, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, + 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep115[] = { + 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, + 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + +}; + +static const short dep116[] = { + 88, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, 2318, 2321, + 2322, 2325, 2326, +}; + +static const short dep117[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2314, 2317, + 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, +}; + +static const short dep118[] = { + 88, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, + 22801, 22802, 22805, 22806, +}; + +static const short dep119[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 4127, 16516, + 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, +}; + +static const short dep120[] = { + 13, 14, 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, + 4127, 16516, 16518, 18731, 18733, 18734, 18736, +}; + +static const short dep121[] = { + 32, 33, 88, 148, 166, 167, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 4127, 20605, +}; + +static const short dep122[] = { + 88, 252, 2075, 2076, 2256, 2257, +}; + +static const short dep123[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2255, 2257, + 4127, 20605, +}; + +static const short dep124[] = { + 32, 33, 88, 166, 252, 2074, 2076, 2157, 2158, 2161, 2164, 2297, 4127, 20605, + +}; + +static const short dep125[] = { + 88, 252, 14446, 14448, 14449, 14451, 14452, 14454, 14605, 14606, 14609, 14610, + 14613, 14614, +}; + +static const short dep126[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 4127, 14605, 14606, 14609, 14610, + 14613, 14614, 20605, 24685, 24686, 24689, 24692, +}; + +static const short dep127[] = { + 88, 113, 115, 116, 118, 252, 273, 274, 277, 278, +}; + +static const short dep128[] = { + 32, 33, 88, 166, 252, 273, 274, 277, 278, 4127, 24685, 24686, 24689, 24692, + +}; + +static const short dep129[] = { + 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep130[] = { + 32, 33, 88, 110, 113, 116, 166, 252, 2297, 4127, 20605, 24685, +}; + +static const short dep131[] = { + 4, 17, 19, 20, 88, 177, 198, 201, 252, 2073, 2254, +}; + +static const short dep132[] = { + 32, 33, 88, 166, 177, 198, 200, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2254, 4127, 20605, +}; + +static const short dep133[] = { + 4, 17, 18, 19, 32, 33, 88, 166, 252, 2073, 2157, 2158, 2161, 2164, 2297, 4127, + 20605, +}; + +static const short dep134[] = { + 0, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep135[] = { + 0, 88, 173, 252, +}; + +static const short dep136[] = { + 0, 32, 33, 88, 148, 166, 167, 173, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep137[] = { + 32, 33, 88, 166, 173, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep138[] = { + 2, 21, 88, 175, 202, 252, 28844, 28987, +}; + +static const short dep139[] = { + 1, 2, 21, 22, 88, 160, 161, 166, 175, 202, 252, 28844, 28987, +}; + +static const short dep140[] = { + 1, 21, 22, 30, 32, 33, 88, 160, 161, 166, 175, 202, 252, 4127, 28844, 28987, + +}; + +static const short dep141[] = { + 0, 32, 33, 88, 166, 173, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep142[] = { + 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 88, 174, 175, + 176, 178, 179, 180, 181, 183, 184, 186, 187, 189, 190, 192, 193, 194, 195, + 196, 202, 203, 204, 252, 2064, 2073, 2245, 2254, 28844, 28987, +}; + +static const short dep143[] = { + 22, 32, 33, 88, 126, 166, 174, 175, 176, 178, 179, 180, 181, 183, 184, 186, + 187, 189, 190, 192, 193, 194, 195, 196, 202, 203, 204, 252, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 2245, 2254, 4127, 20605, 28844, 28987, +}; + +static const short dep144[] = { + 88, 252, 14455, 14457, 14458, 14460, 14489, 14490, 14505, 14615, 14616, 14636, + 14637, 14639, 14640, 14649, +}; + +static const short dep145[] = { + 32, 33, 88, 165, 166, 252, 2157, 2158, 2161, 2164, 4127, 14615, 14616, 14636, + 14637, 14639, 14640, 14649, +}; + +static const short dep146[] = { + 14455, 14457, 14458, 14460, 14489, 14490, 14505, 14615, 14616, 14636, 14637, + 14639, 14640, 14649, +}; + +static const short dep147[] = { + 165, 14615, 14616, 14636, 14637, 14639, 14640, 14649, +}; + +static const short dep148[] = { + 88, 252, 14456, 14457, 14459, 14460, 14468, 14469, 14470, 14471, 14472, 14473, + 14474, 14475, 14477, 14480, 14481, 14489, 14490, 14491, 14492, 14493, 14498, + 14499, 14500, 14501, 14505, 14615, 14616, 14622, 14623, 14624, 14625, 14627, + 14629, 14636, 14637, 14639, 14640, 14641, 14642, 14645, 14646, 14649, +}; + +static const short dep149[] = { + 32, 33, 64, 88, 126, 166, 252, 2157, 2158, 2161, 2164, 4127, 14615, 14616, + 14622, 14623, 14624, 14625, 14627, 14629, 14636, 14637, 14639, 14640, 14641, + 14642, 14645, 14646, 14649, +}; + +static const short dep150[] = { + 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 32, 33, 88, 126, + 163, 166, 252, 2064, 2073, 2157, 2158, 2161, 2164, 2297, 4127, 20605, 28844, + +}; + +static const short dep151[] = { + 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, + 56, 57, 59, 61, 62, 63, 64, 85, 87, 88, 213, 214, 215, 216, 217, 218, 219, + 220, 221, 222, 223, 225, 226, 227, 228, 229, 231, 233, 234, 235, 251, 252, + 2108, 2280, +}; + +static const short dep152[] = { + 32, 33, 87, 88, 126, 145, 166, 213, 214, 215, 216, 217, 218, 219, 220, 221, + 222, 223, 225, 226, 227, 228, 229, 231, 233, 234, 235, 251, 252, 2129, 2130, + 2131, 2157, 2158, 2161, 2164, 2280, 4127, 20605, +}; + +static const short dep153[] = { + 51, 86, 88, 224, 251, 252, 2131, 2297, +}; + +static const short dep154[] = { + 32, 33, 35, 36, 38, 40, 41, 43, 44, 45, 46, 48, 49, 52, 53, 55, 56, 57, 58, + 59, 61, 62, 63, 85, 86, 88, 126, 145, 166, 224, 251, 252, 2099, 2108, 2157, + 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep155[] = { + 2, 21, 33, 88, 175, 202, 211, 252, 2131, 2297, 28844, 28987, +}; + +static const short dep156[] = { + 2, 18, 19, 21, 22, 30, 32, 33, 88, 160, 161, 166, 175, 202, 211, 252, 2297, + 4127, 20605, 28844, 28987, +}; + +static const short dep157[] = { + 88, 120, 121, 123, 124, 128, 129, 132, 133, 134, 135, 136, 137, 138, 139, + 141, 144, 145, 149, 150, 153, 154, 155, 156, 157, 159, 160, 162, 163, 164, + 165, 167, 168, 169, 252, 279, 280, 284, 286, 287, 288, 289, 291, 293, 297, + 300, 301, 303, 304, 305, 306, 308, 309, 310, 312, 313, +}; + +static const short dep158[] = { + 32, 33, 64, 88, 126, 166, 252, 279, 280, 284, 286, 287, 288, 289, 291, 293, + 297, 300, 301, 303, 304, 305, 306, 308, 309, 310, 312, 313, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep159[] = { + 88, 119, 121, 122, 124, 153, 154, 169, 252, 279, 280, 300, 301, 303, 304, + 313, +}; + +static const short dep160[] = { + 32, 33, 88, 165, 166, 252, 279, 280, 300, 301, 303, 304, 313, 2129, 2130, + 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep161[] = { + 32, 33, 88, 121, 124, 126, 129, 130, 133, 135, 137, 139, 141, 142, 144, 148, + 149, 151, 152, 153, 154, 156, 157, 159, 161, 162, 164, 166, 168, 169, 252, + 2157, 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep162[] = { + 32, 33, 88, 121, 124, 153, 154, 166, 169, 252, 2157, 2158, 2161, 2164, 2297, + 4127, 20605, +}; + +static const short dep163[] = { + 32, 33, 67, 68, 73, 75, 88, 102, 126, 155, 166, 170, 252, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep164[] = { + 32, 33, 67, 68, 73, 75, 88, 102, 126, 127, 128, 130, 131, 155, 166, 170, 252, + 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep165[] = { + 68, 69, 88, 92, 93, 239, 240, 252, 254, 255, +}; + +static const short dep166[] = { + 32, 33, 39, 54, 69, 71, 77, 88, 90, 93, 126, 145, 166, 170, 239, 240, 252, + 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep167[] = { + 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 126, 145, 166, 170, 239, 240, + 252, 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep168[] = { + 88, 252, 12458, 12459, 12602, +}; + +static const short dep169[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 12602, 20605, +}; + +static const short dep170[] = { + 88, 252, 6210, 6211, 6381, +}; + +static const short dep171[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6381, 20605, +}; + +static const short dep172[] = { + 88, 252, 6228, 6394, +}; + +static const short dep173[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6394, 20605, +}; + +static const short dep174[] = { + 88, 252, 6246, 6247, 6248, 6249, 6405, 6407, 8454, +}; + +static const short dep175[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6249, 6406, 6407, 8295, 8453, 20605, +}; + +static const short dep176[] = { + 88, 252, 6250, 6251, 6408, +}; + +static const short dep177[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6408, 20605, +}; + +static const short dep178[] = { + 88, 252, 6252, 6409, +}; + +static const short dep179[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 6409, 20605, +}; + +static const short dep180[] = { + 88, 252, 10341, 10500, +}; + +static const short dep181[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, + 10500, 20605, +}; + +static const short dep182[] = { + 68, 69, 73, 74, 88, 92, 93, 239, 240, 242, 243, 252, 254, 255, +}; + +static const short dep183[] = { + 32, 33, 39, 54, 69, 71, 74, 77, 88, 90, 93, 126, 145, 166, 170, 239, 240, + 242, 244, 252, 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + +}; + +static const short dep184[] = { + 68, 69, 88, 92, 93, 95, 96, 239, 240, 252, 254, 255, 256, 257, +}; + +static const short dep185[] = { + 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 126, 145, 166, 170, 239, 240, + 252, 254, 255, 256, 257, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + +}; + +static const short dep186[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 12459, 20605, +}; + +static const short dep187[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6210, 20605, +}; + +static const short dep188[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6228, 20605, +}; + +static const short dep189[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6248, 8294, 20605, +}; + +static const short dep190[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 6250, 20605, +}; + +static const short dep191[] = { + 32, 33, 88, 126, 165, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 6251, 6252, 20605, +}; + +static const short dep192[] = { + 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 10341, 20605, +}; + +static const short dep193[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, + 6178, 20605, +}; + +static const short dep194[] = { + 68, 70, 71, 88, 89, 90, 91, 238, 239, 252, 253, 254, +}; + +static const short dep195[] = { + 32, 33, 69, 70, 74, 76, 88, 91, 93, 95, 98, 126, 166, 170, 238, 240, 252, + 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep196[] = { + 68, 70, 71, 72, 88, 89, 90, 91, 94, 238, 239, 241, 252, 253, 254, +}; + +static const short dep197[] = { + 32, 33, 69, 70, 72, 74, 76, 88, 91, 93, 94, 95, 98, 126, 166, 170, 238, 240, + 241, 252, 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + +}; + +static const short dep198[] = { + 68, 70, 71, 75, 76, 77, 88, 89, 90, 91, 238, 239, 244, 245, 252, 253, 254, + +}; + +static const short dep199[] = { + 32, 33, 69, 70, 74, 76, 88, 91, 93, 126, 166, 170, 238, 240, 243, 245, 252, + 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep200[] = { + 68, 70, 71, 88, 89, 90, 91, 97, 98, 99, 238, 239, 252, 253, 254, 257, 258, + +}; + +static const short dep201[] = { + 32, 33, 69, 70, 88, 91, 93, 95, 98, 126, 166, 170, 238, 240, 252, 253, 255, + 256, 258, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep202[] = { + 32, 33, 38, 62, 88, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 20605, +}; + +static const short dep203[] = { + 32, 33, 88, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 20605, +}; + +static const short dep204[] = { + 32, 33, 68, 73, 75, 88, 126, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep205[] = { + 32, 33, 88, 148, 166, 167, 252, 2126, 2127, 2128, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 4127, 16516, 16518, 20605, +}; + +static const short dep206[] = { + 32, 33, 68, 73, 75, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 4127, 20605, +}; + +static const short dep207[] = { + 32, 33, 69, 70, 88, 91, 126, 166, 238, 240, 252, 253, 255, 2129, 2130, 2131, + 2157, 2158, 2161, 2164, 4127, 20605, +}; + +static const short dep208[] = { + 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, + 4127, 20605, +}; + +static const short dep209[] = { + 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 140, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2297, 4127, 20605, +}; + +static const short dep210[] = { + 0, 88, 173, 252, 2131, 2297, +}; + +static const short dep211[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2297, 4127, 20605, +}; + +static const short dep212[] = { + 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, + 128, 130, 131, 138, 140, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep213[] = { + 23, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 20605, +}; + +static const short dep214[] = { + 0, 88, 173, 252, 2297, 26706, +}; + +static const short dep215[] = { + 0, 88, 100, 173, 252, 259, +}; + +static const short dep216[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 4127, 20605, +}; + +static const short dep217[] = { + 0, 23, 88, 100, 173, 204, 252, 259, +}; + +static const short dep218[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 204, 252, 259, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 4127, 20605, +}; + +static const short dep219[] = { + 0, 88, 100, 173, 252, 259, 2131, 2297, +}; + +static const short dep220[] = { + 0, 3, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, + 128, 130, 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep221[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep222[] = { + 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2297, 4127, + 16516, 16518, 20605, +}; + +static const short dep223[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2297, 4127, 20605, +}; + +static const short dep224[] = { + 0, 23, 88, 100, 173, 204, 252, 259, 2131, 2297, +}; + +static const short dep225[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 173, 204, 252, 259, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep226[] = { + 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, 130, + 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2295, + 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep227[] = { + 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 140, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep228[] = { + 0, 88, 173, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep229[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, + 130, 131, 138, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, 2158, 2161, + 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep230[] = { + 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, + 128, 130, 131, 138, 140, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, + 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, + +}; + +static const short dep231[] = { + 0, 88, 173, 252, 2128, 2295, 18585, 18586, 18731, 18732, 18734, 18735, +}; + +static const short dep232[] = { + 32, 33, 67, 88, 126, 140, 166, 252, 2157, 2158, 2161, 2164, 4127, +}; + +static const short dep233[] = { + 32, 33, 67, 88, 126, 127, 131, 140, 166, 252, 2157, 2158, 2161, 2164, 4127, + +}; + +static const short dep234[] = { + 32, 33, 67, 88, 126, 140, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, + 2297, 4127, 20605, +}; + +static const short dep235[] = { + 32, 33, 67, 88, 126, 127, 131, 140, 166, 252, 2129, 2130, 2131, 2157, 2158, + 2161, 2164, 2297, 4127, 20605, +}; + +static const short dep236[] = { + 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2295, 4127, + 16516, 16518, 18731, 18733, 18734, 18736, 20605, +}; + +static const short dep237[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, + 88, 174, 175, 176, 177, 178, 179, 180, 181, 183, 184, 186, 187, 189, 190, + 192, 193, 194, 195, 196, 198, 201, 202, 203, 204, 252, 2064, 2073, 2131, 2245, + 2254, 2297, 28844, 28987, +}; + +static const short dep238[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, + 32, 33, 88, 126, 163, 166, 174, 175, 176, 177, 178, 179, 180, 181, 183, 184, + 186, 187, 189, 190, 192, 193, 194, 195, 196, 198, 200, 202, 203, 204, 252, + 2064, 2073, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2245, 2254, 2297, 4127, + 20605, 28844, 28987, +}; + +#define NELS(X) (sizeof(X)/sizeof(X[0])) +static const struct ia64_opcode_dependency +op_dependencies[] = { + { NELS(dep1), dep1, NELS(dep0), dep0, }, + { NELS(dep3), dep3, NELS(dep2), dep2, }, + { NELS(dep5), dep5, NELS(dep4), dep4, }, + { NELS(dep7), dep7, NELS(dep6), dep6, }, + { NELS(dep9), dep9, NELS(dep8), dep8, }, + { NELS(dep11), dep11, NELS(dep10), dep10, }, + { NELS(dep13), dep13, NELS(dep12), dep12, }, + { NELS(dep15), dep15, NELS(dep14), dep14, }, + { NELS(dep17), dep17, NELS(dep16), dep16, }, + { NELS(dep19), dep19, NELS(dep18), dep18, }, + { NELS(dep21), dep21, NELS(dep20), dep20, }, + { NELS(dep23), dep23, NELS(dep22), dep22, }, + { NELS(dep25), dep25, NELS(dep24), dep24, }, + { NELS(dep27), dep27, NELS(dep26), dep26, }, + { NELS(dep28), dep28, NELS(dep12), dep12, }, + { NELS(dep30), dep30, NELS(dep29), dep29, }, + { NELS(dep32), dep32, NELS(dep31), dep31, }, + { NELS(dep33), dep33, NELS(dep12), dep12, }, + { NELS(dep35), dep35, NELS(dep34), dep34, }, + { NELS(dep37), dep37, NELS(dep36), dep36, }, + { NELS(dep39), dep39, NELS(dep38), dep38, }, + { NELS(dep40), dep40, NELS(dep29), dep29, }, + { NELS(dep41), dep41, NELS(dep31), dep31, }, + { NELS(dep43), dep43, NELS(dep42), dep42, }, + { NELS(dep45), dep45, NELS(dep44), dep44, }, + { NELS(dep47), dep47, NELS(dep46), dep46, }, + { NELS(dep49), dep49, NELS(dep48), dep48, }, + { NELS(dep51), dep51, NELS(dep50), dep50, }, + { NELS(dep53), dep53, NELS(dep52), dep52, }, + { NELS(dep55), dep55, NELS(dep54), dep54, }, + { NELS(dep57), dep57, NELS(dep56), dep56, }, + { NELS(dep59), dep59, NELS(dep58), dep58, }, + { NELS(dep61), dep61, NELS(dep60), dep60, }, + { NELS(dep63), dep63, NELS(dep62), dep62, }, + { NELS(dep65), dep65, NELS(dep64), dep64, }, + { NELS(dep66), dep66, NELS(dep31), dep31, }, + { NELS(dep68), dep68, NELS(dep67), dep67, }, + { NELS(dep70), dep70, NELS(dep69), dep69, }, + { NELS(dep72), dep72, NELS(dep71), dep71, }, + { NELS(dep74), dep74, NELS(dep73), dep73, }, + { NELS(dep75), dep75, NELS(dep31), dep31, }, + { NELS(dep77), dep77, NELS(dep76), dep76, }, + { NELS(dep79), dep79, NELS(dep78), dep78, }, + { NELS(dep81), dep81, NELS(dep80), dep80, }, + { NELS(dep82), dep82, NELS(dep31), dep31, }, + { NELS(dep83), dep83, NELS(dep31), dep31, }, + { NELS(dep84), dep84, NELS(dep31), dep31, }, + { NELS(dep85), dep85, NELS(dep31), dep31, }, + { NELS(dep87), dep87, NELS(dep86), dep86, }, + { NELS(dep89), dep89, NELS(dep88), dep88, }, + { NELS(dep91), dep91, NELS(dep90), dep90, }, + { NELS(dep93), dep93, NELS(dep92), dep92, }, + { NELS(dep95), dep95, NELS(dep94), dep94, }, + { NELS(dep97), dep97, NELS(dep96), dep96, }, + { NELS(dep99), dep99, NELS(dep98), dep98, }, + { NELS(dep101), dep101, NELS(dep100), dep100, }, + { NELS(dep103), dep103, NELS(dep102), dep102, }, + { NELS(dep105), dep105, NELS(dep104), dep104, }, + { NELS(dep107), dep107, NELS(dep106), dep106, }, + { NELS(dep109), dep109, NELS(dep108), dep108, }, + { NELS(dep111), dep111, NELS(dep110), dep110, }, + { NELS(dep113), dep113, NELS(dep112), dep112, }, + { NELS(dep115), dep115, NELS(dep114), dep114, }, + { NELS(dep117), dep117, NELS(dep116), dep116, }, + { NELS(dep119), dep119, NELS(dep118), dep118, }, + { NELS(dep120), dep120, NELS(dep62), dep62, }, + { NELS(dep121), dep121, NELS(dep31), dep31, }, + { NELS(dep123), dep123, NELS(dep122), dep122, }, + { NELS(dep124), dep124, NELS(dep0), dep0, }, + { NELS(dep126), dep126, NELS(dep125), dep125, }, + { NELS(dep128), dep128, NELS(dep127), dep127, }, + { NELS(dep129), dep129, NELS(dep0), dep0, }, + { NELS(dep130), dep130, NELS(dep0), dep0, }, + { NELS(dep132), dep132, NELS(dep131), dep131, }, + { NELS(dep133), dep133, NELS(dep0), dep0, }, + { NELS(dep134), dep134, NELS(dep31), dep31, }, + { NELS(dep136), dep136, NELS(dep135), dep135, }, + { NELS(dep137), dep137, NELS(dep135), dep135, }, + { NELS(dep139), dep139, NELS(dep138), dep138, }, + { NELS(dep140), dep140, NELS(dep138), dep138, }, + { NELS(dep141), dep141, NELS(dep135), dep135, }, + { NELS(dep143), dep143, NELS(dep142), dep142, }, + { NELS(dep145), dep145, NELS(dep144), dep144, }, + { NELS(dep147), dep147, NELS(dep146), dep146, }, + { NELS(dep149), dep149, NELS(dep148), dep148, }, + { NELS(dep150), dep150, NELS(dep0), dep0, }, + { NELS(dep152), dep152, NELS(dep151), dep151, }, + { NELS(dep154), dep154, NELS(dep153), dep153, }, + { NELS(dep156), dep156, NELS(dep155), dep155, }, + { NELS(dep158), dep158, NELS(dep157), dep157, }, + { NELS(dep160), dep160, NELS(dep159), dep159, }, + { NELS(dep161), dep161, NELS(dep0), dep0, }, + { NELS(dep162), dep162, NELS(dep0), dep0, }, + { NELS(dep163), dep163, NELS(dep0), dep0, }, + { NELS(dep164), dep164, NELS(dep31), dep31, }, + { NELS(dep166), dep166, NELS(dep165), dep165, }, + { NELS(dep167), dep167, NELS(dep165), dep165, }, + { NELS(dep169), dep169, NELS(dep168), dep168, }, + { NELS(dep171), dep171, NELS(dep170), dep170, }, + { NELS(dep173), dep173, NELS(dep172), dep172, }, + { NELS(dep175), dep175, NELS(dep174), dep174, }, + { NELS(dep177), dep177, NELS(dep176), dep176, }, + { NELS(dep179), dep179, NELS(dep178), dep178, }, + { NELS(dep181), dep181, NELS(dep180), dep180, }, + { NELS(dep183), dep183, NELS(dep182), dep182, }, + { NELS(dep185), dep185, NELS(dep184), dep184, }, + { NELS(dep186), dep186, NELS(dep0), dep0, }, + { NELS(dep187), dep187, NELS(dep0), dep0, }, + { NELS(dep188), dep188, NELS(dep0), dep0, }, + { NELS(dep189), dep189, NELS(dep0), dep0, }, + { NELS(dep190), dep190, NELS(dep0), dep0, }, + { NELS(dep191), dep191, NELS(dep0), dep0, }, + { NELS(dep192), dep192, NELS(dep0), dep0, }, + { NELS(dep193), dep193, NELS(dep0), dep0, }, + { NELS(dep195), dep195, NELS(dep194), dep194, }, + { NELS(dep197), dep197, NELS(dep196), dep196, }, + { NELS(dep199), dep199, NELS(dep198), dep198, }, + { NELS(dep201), dep201, NELS(dep200), dep200, }, + { NELS(dep202), dep202, NELS(dep0), dep0, }, + { NELS(dep203), dep203, NELS(dep0), dep0, }, + { NELS(dep204), dep204, NELS(dep0), dep0, }, + { NELS(dep205), dep205, NELS(dep31), dep31, }, + { NELS(dep206), dep206, NELS(dep31), dep31, }, + { NELS(dep207), dep207, NELS(dep194), dep194, }, + { NELS(dep208), dep208, NELS(dep0), dep0, }, + { NELS(dep209), dep209, NELS(dep0), dep0, }, + { NELS(dep211), dep211, NELS(dep210), dep210, }, + { NELS(dep212), dep212, NELS(dep210), dep210, }, + { NELS(dep213), dep213, NELS(dep0), dep0, }, + { NELS(dep211), dep211, NELS(dep214), dep214, }, + { NELS(dep216), dep216, NELS(dep215), dep215, }, + { NELS(dep218), dep218, NELS(dep217), dep217, }, + { NELS(dep220), dep220, NELS(dep219), dep219, }, + { NELS(dep221), dep221, NELS(dep219), dep219, }, + { NELS(dep222), dep222, NELS(dep0), dep0, }, + { NELS(dep223), dep223, NELS(dep219), dep219, }, + { NELS(dep225), dep225, NELS(dep224), dep224, }, + { NELS(dep226), dep226, NELS(dep62), dep62, }, + { NELS(dep227), dep227, NELS(dep62), dep62, }, + { NELS(dep229), dep229, NELS(dep228), dep228, }, + { NELS(dep230), dep230, NELS(dep228), dep228, }, + { NELS(dep229), dep229, NELS(dep231), dep231, }, + { NELS(dep232), dep232, NELS(dep31), dep31, }, + { NELS(dep233), dep233, NELS(dep31), dep31, }, + { NELS(dep234), dep234, NELS(dep0), dep0, }, + { NELS(dep235), dep235, NELS(dep0), dep0, }, + { NELS(dep236), dep236, NELS(dep62), dep62, }, + { 0, NULL, 0, NULL, }, + { NELS(dep238), dep238, NELS(dep237), dep237, }, +}; + +static const struct ia64_completer_table +completer_table[] = { + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 88 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 449, -1, 0, 1, 6 }, + { 0x0, 0x0, 0, 512, -1, 0, 1, 17 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 611, -1, 0, 1, 17 }, + { 0x0, 0x0, 0, 1815, -1, 0, 1, 10 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, + { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, 1991, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 122 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 44 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 78 }, + { 0x0, 0x0, 0, 1855, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2034, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1859, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, 1861, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2043, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2046, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2068, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2071, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, + { 0x0, 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0x3, 221, 396, 1206, 32, 1, 127 }, + { 0x3, 0x3, 221, 397, 1215, 32, 1, 127 }, + { 0x3, 0x3, 221, 398, 1224, 32, 1, 127 }, + { 0x3, 0x3, 221, 399, 1233, 32, 1, 127 }, + { 0x3, 0x3, 221, 400, 1242, 32, 1, 127 }, + { 0x3, 0x3, 221, 401, 1251, 32, 1, 127 }, + { 0x3, 0x3, 221, 402, 1260, 32, 1, 127 }, + { 0x3, 0x3, 221, 403, 1269, 32, 1, 127 }, + { 0x3, 0x3, 221, 404, 1278, 32, 1, 127 }, + { 0x3, 0x3, 221, 405, 1288, 32, 1, 127 }, + { 0x3, 0x3, 221, 406, 1298, 32, 1, 127 }, + { 0x3, 0x3, 221, 419, 1311, 32, 1, 140 }, + { 0x3, 0x3, 221, 420, 1317, 32, 1, 140 }, + { 0x3, 0x3, 221, 421, 1323, 32, 1, 140 }, + { 0x3, 0x3, 221, 422, 1329, 32, 1, 140 }, + { 0x3, 0x3, 221, 423, 1335, 32, 1, 140 }, + { 0x3, 0x3, 221, 424, 1341, 32, 1, 140 }, + { 0x3, 0x3, 221, 425, 1347, 32, 1, 140 }, + { 0x3, 0x3, 221, 426, 1353, 32, 1, 140 }, + { 0x3, 0x3, 221, 427, 1359, 32, 1, 140 }, + { 0x3, 0x3, 221, 428, 1365, 32, 1, 140 }, + { 0x3, 0x3, 221, 429, 1371, 32, 1, 140 }, + { 0x3, 0x3, 221, 430, 1377, 32, 1, 140 }, + { 0x3, 0x3, 221, 431, 1383, 32, 1, 140 }, + { 0x3, 0x3, 221, 432, 1389, 32, 1, 140 }, + { 0x3, 0x3, 221, 433, 1395, 32, 1, 140 }, + { 0x3, 0x3, 221, 434, 1401, 32, 1, 140 }, + { 0x3, 0x3, 221, 435, 1407, 32, 1, 140 }, + { 0x3, 0x3, 221, 436, 1413, 32, 1, 140 }, + { 0x1, 0x1, 222, -1, -1, 28, 1, 33 }, + { 0x1, 0x1, 222, -1, -1, 28, 1, 33 }, + { 0x0, 0x0, 229, 804, -1, 0, 1, 134 }, + { 0x0, 0x0, 229, 805, -1, 0, 1, 146 }, + { 0x1, 0x1, 230, -1, 1704, 33, 1, 131 }, + { 0x1, 0x1, 230, -1, 1707, 33, 1, 136 }, + { 0x0, 0x0, 230, -1, 1709, 0, 1, 130 }, + { 0x0, 0x0, 230, -1, 1710, 0, 1, 130 }, + { 0x0, 0x0, 231, 738, 816, 0, 0, -1 }, + { 0x0, 0x0, 231, 739, 824, 0, 0, -1 }, + { 0x0, 0x0, 231, 740, 820, 0, 0, -1 }, + { 0x1, 0x1, 231, 741, 475, 33, 1, 6 }, + { 0x8000001, 0x8000001, 231, 742, 483, 6, 1, 7 }, + { 0x1, 0x1, 231, 743, 479, 33, 1, 6 }, + { 0x0, 0x0, 231, 744, 828, 0, 0, -1 }, + { 0x1, 0x1, 231, 745, 495, 33, 1, 8 }, + { 0x0, 0x0, 231, 746, 832, 0, 0, -1 }, + { 0x1, 0x1, 231, 747, 507, 33, 1, 15 }, + { 0x0, 0x0, 231, 748, 837, 0, 0, -1 }, + { 0x0, 0x0, 231, 749, 841, 0, 0, -1 }, + { 0x1, 0x1, 231, 750, 530, 33, 1, 17 }, + { 0x1, 0x1, 231, 751, 534, 33, 1, 17 }, + { 0x0, 0x0, 231, 752, 845, 0, 0, -1 }, + { 0x0, 0x0, 231, 753, 849, 0, 0, -1 }, + { 0x1, 0x1, 231, 754, 554, 33, 1, 18 }, + { 0x8000001, 0x8000001, 231, 755, 558, 6, 1, 18 }, + { 0x0, 0x0, 231, 756, 853, 0, 0, -1 }, + { 0x1, 0x1, 231, 757, 570, 33, 1, 19 }, + { 0x0, 0x0, 231, 758, 857, 0, 0, -1 }, + { 0x0, 0x0, 231, 759, 861, 0, 0, -1 }, + { 0x1, 0x1, 231, 760, 590, 33, 1, 20 }, + { 0x8000001, 0x8000001, 231, 761, 594, 6, 1, 20 }, + { 0x0, 0x0, 231, 762, 865, 0, 0, -1 }, + { 0x1, 0x1, 231, 763, 606, 33, 1, 21 }, + { 0x0, 0x0, 231, 764, 870, 0, 0, -1 }, + { 0x0, 0x0, 231, 765, 874, 0, 0, -1 }, + { 0x1, 0x1, 231, 766, 629, 33, 1, 17 }, + { 0x1, 0x1, 231, 767, 633, 33, 1, 17 }, + { 0x0, 0x0, 231, 768, 878, 0, 0, -1 }, + { 0x1, 0x1, 231, 769, 645, 33, 1, 21 }, + { 0x0, 0x0, 232, 2300, 815, 0, 0, -1 }, + { 0x0, 0x0, 232, 2301, 823, 0, 0, -1 }, + { 0x0, 0x0, 232, 2302, 819, 0, 0, -1 }, + { 0x0, 0x0, 232, 2303, 474, 0, 1, 6 }, + { 0x1, 0x1, 232, 2304, 482, 6, 1, 7 }, + { 0x0, 0x0, 232, 2305, 478, 0, 1, 6 }, + { 0x0, 0x0, 232, 2306, 827, 0, 0, -1 }, + { 0x0, 0x0, 232, 2307, 494, 0, 1, 8 }, + { 0x0, 0x0, 232, 2308, 831, 0, 0, -1 }, + { 0x0, 0x0, 232, 2309, 506, 0, 1, 15 }, + { 0x0, 0x0, 232, 2310, 836, 0, 0, -1 }, + { 0x0, 0x0, 232, 2311, 840, 0, 0, -1 }, + { 0x0, 0x0, 232, 2312, 529, 0, 1, 17 }, + { 0x0, 0x0, 232, 2313, 533, 0, 1, 17 }, + { 0x0, 0x0, 232, 2314, 844, 0, 0, -1 }, + { 0x0, 0x0, 232, 2315, 848, 0, 0, -1 }, + { 0x0, 0x0, 232, 2316, 553, 0, 1, 18 }, + { 0x1, 0x1, 232, 2317, 557, 6, 1, 18 }, + { 0x0, 0x0, 232, 2318, 852, 0, 0, -1 }, + { 0x0, 0x0, 232, 2319, 569, 0, 1, 19 }, + { 0x0, 0x0, 232, 2320, 856, 0, 0, -1 }, + { 0x0, 0x0, 232, 2321, 860, 0, 0, -1 }, + { 0x0, 0x0, 232, 2322, 589, 0, 1, 20 }, + { 0x1, 0x1, 232, 2323, 593, 6, 1, 20 }, + { 0x0, 0x0, 232, 2324, 864, 0, 0, -1 }, + { 0x0, 0x0, 232, 2325, 605, 0, 1, 21 }, + { 0x0, 0x0, 232, 2326, 869, 0, 0, -1 }, + { 0x0, 0x0, 232, 2327, 873, 0, 0, -1 }, + { 0x0, 0x0, 232, 2328, 628, 0, 1, 17 }, + { 0x0, 0x0, 232, 2329, 632, 0, 1, 17 }, + { 0x0, 0x0, 232, 2330, 877, 0, 0, -1 }, + { 0x0, 0x0, 232, 2331, 644, 0, 1, 21 }, + { 0x1, 0x1, 232, 770, 964, 27, 1, 16 }, + { 0x0, 0x0, 232, 771, 962, 0, 1, 16 }, + { 0x0, 0x0, 232, 1012, 966, 0, 1, 22 }, + { 0x0, 0x1, 232, 974, 972, 20, 1, 67 }, + { 0x0, 0x0, 232, 108, 970, 0, 1, 67 }, + { 0x1, 0x1, 235, -1, -1, 29, 1, 0 }, + { 0x0, 0x0, 235, -1, -1, 0, 1, 0 }, + { 0x1, 0x1, 235, 2472, -1, 27, 1, 0 }, + { 0x1, 0x1, 235, 2473, -1, 27, 1, 0 }, + { 0x1, 0x1, 235, 2474, -1, 27, 1, 0 }, + { 0x1, 0x1, 235, 2475, -1, 27, 1, 0 }, + { 0x0, 0x0, 256, -1, 1929, 0, 0, -1 }, + { 0x0, 0x0, 256, -1, 1931, 0, 0, -1 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x0, 0x0, 256, -1, 1970, 0, 0, -1 }, + { 0x0, 0x0, 256, -1, 1972, 0, 0, -1 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 29 }, + { 0x0, 0x0, 258, 22, -1, 0, 1, 0 }, + { 0x0, 0x0, 258, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 258, -1, -1, 0, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x0, 0x0, 258, 176, -1, 0, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 64 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 64 }, + { 0x0, 0x0, 259, -1, 1905, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1907, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1909, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1911, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 49 }, + { 0x0, 0x0, 259, -1, 1913, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1915, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x0, 0x0, 259, -1, 1917, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1919, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1921, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1923, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 49 }, + { 0x0, 0x0, 259, -1, 1925, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 1927, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 259, 329, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, 387, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, 333, -1, 12, 1, 2 }, + { 0x1, 0x1, 259, 391, -1, 12, 1, 2 }, + { 0x0, 0x0, 260, -1, 1912, 0, 0, -1 }, + { 0x9, 0x9, 260, -1, 2442, 33, 1, 49 }, + { 0x0, 0x0, 260, 1162, 1961, 0, 0, -1 }, + { 0x3, 0x3, 260, 1163, -1, 27, 1, 49 }, + { 0x0, 0x0, 264, 2369, -1, 0, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 265, -1, -1, 27, 1, 0 }, + { 0x1, 0x1, 266, 2468, -1, 28, 1, 0 }, + { 0x1, 0x1, 266, 2469, -1, 28, 1, 0 }, + { 0x1, 0x1, 266, 2470, -1, 28, 1, 0 }, + { 0x1, 0x1, 266, 2471, -1, 28, 1, 0 }, + { 0x1, 0x1, 267, -1, -1, 27, 1, 93 }, + { 0x1, 0x1, 267, -1, -1, 27, 1, 93 }, + { 0x0, 0x0, 267, -1, 813, 0, 0, -1 }, + { 0x0, 0x0, 268, 2481, 2346, 0, 0, -1 }, + { 0x0, 0x0, 268, 2482, 2348, 0, 0, -1 }, + { 0x0, 0x0, 269, -1, 2347, 0, 0, -1 }, + { 0x0, 0x0, 269, -1, 2349, 0, 0, -1 }, + { 0x0, 0x0, 270, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 270, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 275, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 279, -1, 1935, 0, 1, 29 }, + { 0x0, 0x0, 280, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 280, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 280, 1723, 2459, 0, 1, 1 }, + { 0x0, 0x0, 280, -1, 388, 0, 0, -1 }, + { 0x0, 0x0, 280, 1725, 2461, 0, 1, 1 }, + { 0x0, 0x0, 280, -1, 392, 0, 0, -1 }, +}; + +static const struct ia64_main_table +main_table[] = { + { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 1, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 2, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 23, 62, 25, 0, 0 }, 0x0, 3, }, + { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 4, }, + { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 5, }, + { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 6, }, + { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 7, }, + { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 8, }, + { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 9, }, + { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 10, }, + { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 11, }, + { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 12, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 814, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 680, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 681, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1843, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1844, }, + { 14, 4, 1, 0x0000002000000000ull, 0x000001ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 437, }, + { 14, 4, 1, 0x0000002000000000ull, 0x000001ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 438, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 835, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 682, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 683, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 2479, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 2480, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 445, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 446, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 443, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 444, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 439, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 440, }, + { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 393, }, + { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 806, }, + { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 949, }, + { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 1038, }, + { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 2483, }, + { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 64, 0, 0, 0, 0 }, 0x0, 15, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 868, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 684, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 685, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 14, 81, 0, 0, 0 }, 0x0, 441, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 14, 81, 0, 0, 0 }, 0x40, 442, }, + { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 15, 76, 0, 0, 0 }, 0x20, 2365, }, + { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 80, 76, 0, 0, 0 }, 0x20, 2366, }, + { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 216, }, + { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1848, }, + { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 23, 80, 0, 0, 0 }, 0x0, 218, }, + { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 17, 80, 0, 0, 0 }, 0x0, 219, }, + { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1849, }, + { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 18, 79, 0, 0, 0 }, 0x0, 1850, }, + { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1851, }, + { 25, 4, 0, 0x0000000020000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 17, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 1014, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 990, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 918, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 897, }, + { 26, 1, 2, 0x0000018200000000ull, 0x000001fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 1146, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 919, }, + { 26, 1, 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0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 1036, }, + { 277, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 989, }, + { 278, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 211, }, + { 278, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 212, }, + { 281, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 213, }, + { 282, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 214, }, + { 283, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 215, }, +}; + +static const char dis_table[] = { +0xa0, 0xc2, 0x60, 0xa0, 0x2c, 0x80, 0xa0, 0x2a, 0x80, 0xa0, 0x1a, 0x70, +0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x31, 0x48, 0x24, +0x31, 0x40, 0x90, 0x28, 0x24, 0x31, 0x38, 0x24, 0x31, 0x30, 0x90, 0x50, +0x90, 0x28, 0x24, 0x31, 0x20, 0x24, 0x31, 0x18, 0x90, 0x28, 0x24, 0x31, +0x10, 0x24, 0x31, 0x08, 0xa8, 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0x00, 0x80, 0xe5, +0x21, 0xfb, 0x00, 0x37, 0xf8, 0xe5, 0x21, 0xf5, 0x00, 0x37, 0xe0, 0xcb, +0x61, 0x0d, 0x00, 0x85, 0x34, 0x39, 0x90, 0x48, 0xcb, 0xa1, 0x0c, 0xc0, +0x85, 0x34, 0x38, 0xcb, 0xa1, 0x0c, 0x80, 0x85, 0x34, 0x37, 0x91, 0x00, +0x90, 0x80, 0x90, 0x40, 0xe5, 0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, +0x01, 0x80, 0x30, 0x07, 0x90, 0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, +0xe5, 0x20, 0x00, 0x00, 0x30, 0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, +0xed, 0x00, 0x37, 0xae, 0xe5, 0x21, 0xee, 0x40, 0x37, 0xc4, 0x90, 0x40, +0xe5, 0x21, 0xe3, 0x80, 0x37, 0x88, 0xe5, 0x21, 0xe4, 0xc0, 0x37, 0x9e, +0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x21, 0x48, 0x90, 0x80, 0x90, 0x40, +0xe5, 0x22, 0x19, 0x00, 0x38, 0x62, 0xe5, 0x22, 0x17, 0x80, 0x38, 0x68, +0x90, 0x40, 0xe5, 0x22, 0x11, 0x00, 0x38, 0x42, 0xe5, 0x22, 0x0f, 0x80, +0x38, 0x48, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, +0x08, 0x00, 0x38, 0x2c, 0xe5, 0x22, 0x02, 0x00, 0x38, 0x14, 0xcb, 0x61, +0x0b, 0x00, 0x85, 0x34, 0x30, 0x90, 0x40, 0xe5, 0x21, 0xfc, 0x00, 0x37, +0xfc, 0xe5, 0x21, 0xf6, 0x00, 0x37, 0xe4, 0x90, 0x48, 0xcb, 0xa1, 0x0a, +0x80, 0x85, 0x34, 0x2e, 0xcb, 0xa1, 0x0a, 0xc0, 0x85, 0x34, 0x2f, 0x10, +0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xf0, 0x80, 0x37, 0xc0, 0xe5, +0x21, 0xef, 0x00, 0x37, 0xc8, 0x90, 0x40, 0xe5, 0x21, 0xe7, 0x00, 0x37, +0x9a, 0xe5, 0x21, 0xe5, 0x80, 0x37, 0xa2, +}; + +static const struct ia64_dis_names ia64_dis_names[] = { +{ 0x51, 40, 0, 9 }, +{ 0x31, 40, 1, 19 }, +{ 0x11, 41, 0, 18 }, +{ 0x29, 40, 0, 11 }, +{ 0x19, 40, 1, 23 }, +{ 0x9, 41, 0, 22 }, +{ 0x15, 40, 0, 13 }, +{ 0xd, 40, 1, 27 }, +{ 0x5, 41, 0, 26 }, +{ 0xb, 40, 0, 15 }, +{ 0x7, 40, 1, 31 }, +{ 0x3, 41, 0, 30 }, +{ 0x51, 38, 1, 57 }, +{ 0x50, 38, 0, 33 }, +{ 0xd1, 38, 1, 56 }, +{ 0xd0, 38, 0, 32 }, +{ 0x31, 38, 1, 67 }, +{ 0x30, 38, 1, 43 }, +{ 0x11, 39, 1, 66 }, +{ 0x10, 39, 0, 42 }, +{ 0x71, 38, 1, 65 }, +{ 0x70, 38, 1, 41 }, +{ 0x31, 39, 1, 64 }, +{ 0x30, 39, 0, 40 }, +{ 0x29, 38, 1, 59 }, +{ 0x28, 38, 0, 35 }, +{ 0x69, 38, 1, 58 }, +{ 0x68, 38, 0, 34 }, +{ 0x19, 38, 1, 71 }, +{ 0x18, 38, 1, 47 }, +{ 0x9, 39, 1, 70 }, +{ 0x8, 39, 0, 46 }, +{ 0x39, 38, 1, 69 }, +{ 0x38, 38, 1, 45 }, +{ 0x19, 39, 1, 68 }, +{ 0x18, 39, 0, 44 }, +{ 0x15, 38, 1, 61 }, +{ 0x14, 38, 0, 37 }, +{ 0x35, 38, 1, 60 }, +{ 0x34, 38, 0, 36 }, +{ 0xd, 38, 1, 75 }, +{ 0xc, 38, 1, 51 }, +{ 0x5, 39, 1, 74 }, +{ 0x4, 39, 0, 50 }, +{ 0x1d, 38, 1, 73 }, +{ 0x1c, 38, 1, 49 }, +{ 0xd, 39, 1, 72 }, +{ 0xc, 39, 0, 48 }, +{ 0xb, 38, 1, 63 }, +{ 0xa, 38, 0, 39 }, +{ 0x1b, 38, 1, 62 }, +{ 0x1a, 38, 0, 38 }, +{ 0x7, 38, 1, 79 }, +{ 0x6, 38, 1, 55 }, +{ 0x3, 39, 1, 78 }, +{ 0x2, 39, 0, 54 }, +{ 0xf, 38, 1, 77 }, +{ 0xe, 38, 1, 53 }, +{ 0x7, 39, 1, 76 }, +{ 0x6, 39, 0, 52 }, +{ 0x8, 37, 0, 81 }, +{ 0x18, 37, 0, 80 }, +{ 0x1, 37, 1, 85 }, +{ 0x2, 37, 0, 84 }, +{ 0x3, 37, 1, 83 }, +{ 0x4, 37, 0, 82 }, +{ 0x1, 284, 0, 86 }, +{ 0x20, 237, 0, 96 }, +{ 0x220, 237, 0, 92 }, +{ 0x1220, 237, 0, 89 }, +{ 0xa20, 237, 0, 90 }, +{ 0x620, 237, 0, 91 }, +{ 0x120, 237, 0, 93 }, +{ 0xa0, 237, 0, 94 }, +{ 0x60, 237, 0, 95 }, +{ 0x10, 237, 0, 100 }, +{ 0x90, 237, 0, 97 }, +{ 0x50, 237, 0, 98 }, +{ 0x30, 237, 0, 99 }, +{ 0x8, 237, 0, 101 }, +{ 0x4, 237, 0, 102 }, +{ 0x2, 237, 0, 103 }, +{ 0x1, 237, 0, 104 }, +{ 0x1, 357, 0, 106 }, +{ 0x3, 357, 0, 105 }, +{ 0x2, 363, 0, 107 }, +{ 0x1, 363, 0, 108 }, +{ 0x2, 359, 0, 109 }, +{ 0x1, 359, 0, 110 }, +{ 0x2, 361, 0, 111 }, +{ 0x1, 361, 0, 112 }, +{ 0x2, 365, 0, 113 }, +{ 0x1, 365, 0, 114 }, +{ 0x1, 216, 0, 141 }, +{ 0x5, 216, 0, 139 }, +{ 0x3, 216, 0, 140 }, +{ 0x140, 225, 0, 117 }, +{ 0x540, 225, 0, 115 }, +{ 0x340, 225, 0, 116 }, +{ 0xc0, 225, 0, 129 }, +{ 0x2c0, 225, 0, 127 }, +{ 0x1c0, 225, 0, 128 }, +{ 0x20, 225, 0, 144 }, +{ 0xa0, 225, 0, 142 }, +{ 0x60, 225, 0, 143 }, +{ 0x10, 225, 0, 156 }, +{ 0x50, 225, 0, 154 }, +{ 0x30, 225, 0, 155 }, +{ 0x8, 225, 0, 168 }, +{ 0x28, 225, 0, 166 }, +{ 0x18, 225, 0, 167 }, +{ 0x4, 225, 0, 178 }, +{ 0x2, 225, 0, 179 }, +{ 0x1, 225, 0, 180 }, +{ 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+{ 0x1b, 18, 0, 1821 }, +{ 0x7, 18, 1, 1838 }, +{ 0x3, 19, 0, 1837 }, +{ 0xf, 18, 1, 1836 }, +{ 0x7, 19, 0, 1835 }, +{ 0x1, 31, 0, 1839 }, +{ 0x1, 103, 0, 1840 }, +{ 0x2, 44, 0, 1841 }, +{ 0x1, 44, 0, 1842 }, +{ 0x1, 335, 0, 1843 }, +{ 0x2, 51, 0, 1844 }, +{ 0x1, 51, 0, 1845 }, +{ 0x1, 96, 0, 1846 }, +{ 0x51, 16, 0, 1848 }, +{ 0xd1, 16, 0, 1847 }, +{ 0x31, 16, 1, 1858 }, +{ 0x11, 17, 0, 1857 }, +{ 0x71, 16, 1, 1856 }, +{ 0x31, 17, 0, 1855 }, +{ 0x29, 16, 0, 1850 }, +{ 0x69, 16, 0, 1849 }, +{ 0x19, 16, 1, 1862 }, +{ 0x9, 17, 0, 1861 }, +{ 0x39, 16, 1, 1860 }, +{ 0x19, 17, 0, 1859 }, +{ 0x15, 16, 0, 1852 }, +{ 0x35, 16, 0, 1851 }, +{ 0xd, 16, 1, 1866 }, +{ 0x5, 17, 0, 1865 }, +{ 0x1d, 16, 1, 1864 }, +{ 0xd, 17, 0, 1863 }, +{ 0xb, 16, 0, 1854 }, +{ 0x1b, 16, 0, 1853 }, +{ 0x7, 16, 1, 1870 }, +{ 0x3, 17, 0, 1869 }, +{ 0xf, 16, 1, 1868 }, +{ 0x7, 17, 0, 1867 }, +{ 0xa20, 14, 0, 1872 }, +{ 0x1a20, 14, 0, 1871 }, +{ 0x620, 14, 1, 1882 }, +{ 0x220, 15, 0, 1881 }, +{ 0xe20, 14, 1, 1880 }, +{ 0x620, 15, 0, 1879 }, +{ 0x520, 14, 0, 1874 }, +{ 0xd20, 14, 0, 1873 }, +{ 0x320, 14, 1, 1886 }, +{ 0x120, 15, 0, 1885 }, +{ 0x720, 14, 1, 1884 }, +{ 0x320, 15, 0, 1883 }, +{ 0x2a0, 14, 0, 1876 }, +{ 0x6a0, 14, 0, 1875 }, +{ 0x1a0, 14, 1, 1890 }, +{ 0xa0, 15, 0, 1889 }, +{ 0x3a0, 14, 1, 1888 }, +{ 0x1a0, 15, 0, 1887 }, +{ 0x160, 14, 0, 1878 }, +{ 0x360, 14, 0, 1877 }, +{ 0xe0, 14, 1, 1894 }, +{ 0x60, 15, 0, 1893 }, +{ 0x1e0, 14, 1, 1892 }, +{ 0xe0, 15, 0, 1891 }, +{ 0x51, 14, 1, 1920 }, +{ 0x50, 14, 0, 1896 }, +{ 0xd1, 14, 1, 1919 }, +{ 0xd0, 14, 0, 1895 }, +{ 0x31, 14, 1, 1930 }, +{ 0x30, 14, 1, 1906 }, +{ 0x11, 15, 1, 1929 }, +{ 0x10, 15, 0, 1905 }, +{ 0x71, 14, 1, 1928 }, +{ 0x70, 14, 1, 1904 }, +{ 0x31, 15, 1, 1927 }, +{ 0x30, 15, 0, 1903 }, +{ 0x29, 14, 1, 1922 }, +{ 0x28, 14, 0, 1898 }, +{ 0x69, 14, 1, 1921 }, +{ 0x68, 14, 0, 1897 }, +{ 0x19, 14, 1, 1934 }, +{ 0x18, 14, 1, 1910 }, +{ 0x9, 15, 1, 1933 }, +{ 0x8, 15, 0, 1909 }, +{ 0x39, 14, 1, 1932 }, +{ 0x38, 14, 1, 1908 }, +{ 0x19, 15, 1, 1931 }, +{ 0x18, 15, 0, 1907 }, +{ 0x15, 14, 1, 1924 }, +{ 0x14, 14, 0, 1900 }, +{ 0x35, 14, 1, 1923 }, +{ 0x34, 14, 0, 1899 }, +{ 0xd, 14, 1, 1938 }, +{ 0xc, 14, 1, 1914 }, +{ 0x5, 15, 1, 1937 }, +{ 0x4, 15, 0, 1913 }, +{ 0x1d, 14, 1, 1936 }, +{ 0x1c, 14, 1, 1912 }, +{ 0xd, 15, 1, 1935 }, +{ 0xc, 15, 0, 1911 }, +{ 0xb, 14, 1, 1926 }, +{ 0xa, 14, 0, 1902 }, +{ 0x1b, 14, 1, 1925 }, +{ 0x1a, 14, 0, 1901 }, +{ 0x7, 14, 1, 1942 }, +{ 0x6, 14, 1, 1918 }, +{ 0x3, 15, 1, 1941 }, +{ 0x2, 15, 0, 1917 }, +{ 0xf, 14, 1, 1940 }, +{ 0xe, 14, 1, 1916 }, +{ 0x7, 15, 1, 1939 }, +{ 0x6, 15, 0, 1915 }, +{ 0x8, 13, 0, 1944 }, +{ 0x18, 13, 0, 1943 }, +{ 0x1, 13, 1, 1948 }, +{ 0x2, 13, 0, 1947 }, +{ 0x3, 13, 1, 1946 }, +{ 0x4, 13, 0, 1945 }, +{ 0x1, 84, 1, 2024 }, +{ 0x1, 85, 1, 2023 }, +{ 0x1, 86, 1, 2022 }, +{ 0x1, 87, 1, 2021 }, +{ 0x39, 40, 1, 21 }, +{ 0x19, 41, 0, 20 }, +{ 0x3, 84, 1, 2020 }, +{ 0x3, 85, 1, 2019 }, +{ 0x3, 86, 1, 2018 }, +{ 0x3, 87, 1, 2017 }, +{ 0x69, 40, 0, 10 }, +{ 0x14, 79, 1, 2014 }, +{ 0xa, 83, 1, 2013 }, +{ 0xd1, 40, 0, 8 }, +{ 0x34, 79, 1, 1950 }, +{ 0xe, 91, 0, 1949 }, +{ 0xc, 79, 1, 2094 }, +{ 0x6, 83, 0, 2093 }, +{ 0x2, 79, 1, 1956 }, +{ 0x2, 82, 0, 1955 }, +{ 0x12, 79, 1, 1954 }, +{ 0x6, 82, 0, 1953 }, +{ 0xa, 79, 1, 2016 }, +{ 0x5, 83, 1, 2015 }, +{ 0x71, 40, 1, 17 }, +{ 0x31, 41, 0, 16 }, +{ 0x1a, 79, 1, 1952 }, +{ 0x7, 91, 0, 1951 }, +{ 0x6, 79, 1, 2096 }, +{ 0x3, 83, 0, 2095 }, +{ 0x1, 79, 1, 2104 }, +{ 0x1, 80, 1, 2103 }, +{ 0x1, 81, 1, 2102 }, +{ 0x1, 82, 0, 2101 }, +{ 0x3, 79, 1, 2100 }, +{ 0x3, 80, 1, 2099 }, +{ 0x3, 81, 1, 2098 }, +{ 0x3, 82, 0, 2097 }, +{ 0x8, 60, 1, 2036 }, +{ 0x2, 63, 1, 2033 }, +{ 0x1, 65, 1, 2035 }, +{ 0x1, 66, 1, 2034 }, +{ 0xf, 40, 1, 29 }, +{ 0x7, 41, 0, 28 }, +{ 0x18, 60, 1, 2032 }, +{ 0x6, 63, 1, 2029 }, +{ 0x3, 65, 1, 2031 }, +{ 0x3, 66, 1, 2030 }, +{ 0x1b, 40, 0, 14 }, +{ 0x14, 60, 1, 2026 }, +{ 0xa, 64, 1, 2025 }, +{ 0x35, 40, 0, 12 }, +{ 0x34, 60, 1, 1958 }, +{ 0xe, 70, 0, 1957 }, +{ 0xc, 60, 1, 2106 }, +{ 0x6, 64, 0, 2105 }, +{ 0x2, 60, 1, 1964 }, +{ 0x4, 63, 0, 1963 }, +{ 0x12, 60, 1, 1962 }, +{ 0xc, 63, 0, 1961 }, +{ 0xa, 60, 1, 2028 }, +{ 0x5, 64, 1, 2027 }, +{ 0x1d, 40, 1, 25 }, +{ 0xd, 41, 0, 24 }, +{ 0x1a, 60, 1, 1960 }, +{ 0x7, 70, 0, 1959 }, +{ 0x6, 60, 1, 2108 }, +{ 0x3, 64, 0, 2107 }, +{ 0x1, 60, 1, 2116 }, +{ 0x1, 61, 1, 2115 }, +{ 0x1, 62, 1, 2114 }, +{ 0x1, 63, 0, 2113 }, +{ 0x3, 60, 1, 2112 }, +{ 0x3, 61, 1, 2111 }, +{ 0x3, 62, 1, 2110 }, +{ 0x3, 63, 0, 2109 }, +{ 0x28, 76, 1, 2040 }, +{ 0x44, 77, 1, 2037 }, +{ 0x88, 77, 1, 2039 }, +{ 0x28, 78, 0, 2038 }, +{ 0x68, 76, 1, 1968 }, +{ 0x188, 77, 1, 1967 }, +{ 0x38, 89, 1, 1966 }, +{ 0x38, 90, 0, 1965 }, +{ 0x18, 76, 1, 2120 }, +{ 0x14, 77, 1, 2117 }, +{ 0x28, 77, 1, 2119 }, +{ 0x18, 78, 0, 2118 }, +{ 0x14, 76, 1, 2044 }, +{ 0x24, 77, 1, 2043 }, +{ 0x48, 77, 1, 2041 }, +{ 0x14, 78, 0, 2042 }, +{ 0x34, 76, 1, 1972 }, +{ 0x64, 77, 1, 1971 }, +{ 0x1c, 89, 1, 1970 }, +{ 0x1c, 90, 0, 1969 }, +{ 0xc, 76, 1, 2124 }, +{ 0xc, 77, 1, 2123 }, +{ 0x18, 77, 1, 2121 }, +{ 0xc, 78, 0, 2122 }, +{ 0xa, 76, 1, 2048 }, +{ 0x11, 77, 1, 2045 }, +{ 0x22, 77, 1, 2047 }, +{ 0xa, 78, 0, 2046 }, +{ 0x1a, 76, 1, 1976 }, +{ 0x62, 77, 1, 1975 }, +{ 0xe, 89, 1, 1974 }, +{ 0xe, 90, 0, 1973 }, +{ 0x6, 76, 1, 2128 }, +{ 0x5, 77, 1, 2125 }, +{ 0xa, 77, 1, 2127 }, +{ 0x6, 78, 0, 2126 }, +{ 0x5, 76, 1, 2052 }, +{ 0x9, 77, 1, 2051 }, +{ 0x12, 77, 1, 2049 }, +{ 0x5, 78, 0, 2050 }, +{ 0xd, 76, 1, 1980 }, +{ 0x19, 77, 1, 1979 }, +{ 0x7, 89, 1, 1978 }, +{ 0x7, 90, 0, 1977 }, +{ 0x3, 76, 1, 2132 }, +{ 0x3, 77, 1, 2131 }, +{ 0x6, 77, 1, 2129 }, +{ 0x3, 78, 0, 2130 }, +{ 0x28, 57, 1, 2056 }, +{ 0x44, 58, 1, 2053 }, +{ 0x88, 58, 1, 2055 }, +{ 0x28, 59, 0, 2054 }, +{ 0x68, 57, 1, 1984 }, +{ 0x188, 58, 1, 1983 }, +{ 0x38, 68, 1, 1982 }, +{ 0x38, 69, 0, 1981 }, +{ 0x18, 57, 1, 2136 }, +{ 0x14, 58, 1, 2133 }, +{ 0x28, 58, 1, 2135 }, +{ 0x18, 59, 0, 2134 }, +{ 0x14, 57, 1, 2060 }, +{ 0x24, 58, 1, 2059 }, +{ 0x48, 58, 1, 2057 }, +{ 0x14, 59, 0, 2058 }, +{ 0x34, 57, 1, 1988 }, +{ 0x64, 58, 1, 1987 }, +{ 0x1c, 68, 1, 1986 }, +{ 0x1c, 69, 0, 1985 }, +{ 0xc, 57, 1, 2140 }, +{ 0xc, 58, 1, 2139 }, +{ 0x18, 58, 1, 2137 }, +{ 0xc, 59, 0, 2138 }, +{ 0xa, 57, 1, 2064 }, +{ 0x11, 58, 1, 2061 }, +{ 0x22, 58, 1, 2063 }, +{ 0xa, 59, 0, 2062 }, +{ 0x1a, 57, 1, 1992 }, +{ 0x62, 58, 1, 1991 }, +{ 0xe, 68, 1, 1990 }, +{ 0xe, 69, 0, 1989 }, +{ 0x6, 57, 1, 2144 }, +{ 0x5, 58, 1, 2141 }, +{ 0xa, 58, 1, 2143 }, +{ 0x6, 59, 0, 2142 }, +{ 0x5, 57, 1, 2068 }, +{ 0x9, 58, 1, 2067 }, +{ 0x12, 58, 1, 2065 }, +{ 0x5, 59, 0, 2066 }, +{ 0xd, 57, 1, 1996 }, +{ 0x19, 58, 1, 1995 }, +{ 0x7, 68, 1, 1994 }, +{ 0x7, 69, 0, 1993 }, +{ 0x3, 57, 1, 2148 }, +{ 0x3, 58, 1, 2147 }, +{ 0x6, 58, 1, 2145 }, +{ 0x3, 59, 0, 2146 }, +{ 0x8, 71, 1, 2080 }, +{ 0x2, 72, 1, 2079 }, +{ 0x2, 73, 1, 2078 }, +{ 0x2, 74, 0, 2077 }, +{ 0x18, 71, 1, 2076 }, +{ 0x6, 72, 1, 2075 }, +{ 0x6, 73, 1, 2074 }, +{ 0x6, 74, 0, 2073 }, +{ 0x14, 71, 1, 2070 }, +{ 0xa, 75, 0, 2069 }, +{ 0x34, 71, 1, 1998 }, +{ 0xe, 88, 0, 1997 }, +{ 0xc, 71, 1, 2150 }, +{ 0x6, 75, 0, 2149 }, +{ 0x2, 71, 1, 2004 }, +{ 0x4, 74, 0, 2003 }, +{ 0x12, 71, 1, 2002 }, +{ 0xc, 74, 0, 2001 }, +{ 0xa, 71, 1, 2072 }, +{ 0x5, 75, 0, 2071 }, +{ 0x1a, 71, 1, 2000 }, +{ 0x7, 88, 0, 1999 }, +{ 0x6, 71, 1, 2152 }, +{ 0x3, 75, 0, 2151 }, +{ 0x1, 71, 1, 2160 }, +{ 0x1, 72, 1, 2159 }, +{ 0x1, 73, 1, 2158 }, +{ 0x1, 74, 0, 2157 }, +{ 0x3, 71, 1, 2156 }, +{ 0x3, 72, 1, 2155 }, +{ 0x3, 73, 1, 2154 }, +{ 0x3, 74, 0, 2153 }, +{ 0x8, 52, 1, 2092 }, +{ 0x2, 53, 1, 2091 }, +{ 0x2, 54, 1, 2090 }, +{ 0x2, 55, 0, 2089 }, +{ 0x18, 52, 1, 2088 }, +{ 0x6, 53, 1, 2087 }, +{ 0x6, 54, 1, 2086 }, +{ 0x6, 55, 0, 2085 }, +{ 0x14, 52, 1, 2082 }, +{ 0xa, 56, 0, 2081 }, +{ 0x34, 52, 1, 2006 }, +{ 0xe, 67, 0, 2005 }, +{ 0xc, 52, 1, 2162 }, +{ 0x6, 56, 0, 2161 }, +{ 0x2, 52, 1, 2012 }, +{ 0x4, 55, 0, 2011 }, +{ 0x12, 52, 1, 2010 }, +{ 0xc, 55, 0, 2009 }, +{ 0xa, 52, 1, 2084 }, +{ 0x5, 56, 0, 2083 }, +{ 0x1a, 52, 1, 2008 }, +{ 0x7, 67, 0, 2007 }, +{ 0x6, 52, 1, 2164 }, +{ 0x3, 56, 0, 2163 }, +{ 0x1, 52, 1, 2172 }, +{ 0x1, 53, 1, 2171 }, +{ 0x1, 54, 1, 2170 }, +{ 0x1, 55, 0, 2169 }, +{ 0x3, 52, 1, 2168 }, +{ 0x3, 53, 1, 2167 }, +{ 0x3, 54, 1, 2166 }, +{ 0x3, 55, 0, 2165 }, +{ 0x1, 4, 0, 2173 }, +{ 0x1, 245, 0, 2174 }, +{ 0x1, 327, 0, 2175 }, +{ 0x1, 322, 0, 2176 }, +{ 0x2, 306, 0, 2177 }, +{ 0x1, 306, 0, 2180 }, +{ 0x2, 305, 0, 2178 }, +{ 0x1, 305, 0, 2181 }, +{ 0x2, 304, 0, 2179 }, +{ 0x1, 304, 0, 2182 }, +{ 0x1, 303, 0, 2183 }, +{ 0x1, 302, 0, 2184 }, +{ 0x2, 301, 0, 2185 }, +{ 0x1, 301, 0, 2187 }, +{ 0x2, 300, 0, 2186 }, +{ 0x1, 300, 0, 2188 }, +{ 0x1, 330, 0, 2195 }, +{ 0x8, 329, 0, 2189 }, +{ 0x4, 329, 0, 2191 }, +{ 0x2, 329, 0, 2193 }, +{ 0x1, 329, 0, 2196 }, +{ 0x8, 328, 0, 2190 }, +{ 0x4, 328, 0, 2192 }, +{ 0x2, 328, 0, 2194 }, +{ 0x1, 328, 0, 2197 }, +{ 0x1, 299, 0, 2204 }, +{ 0x8, 298, 0, 2198 }, +{ 0x4, 298, 0, 2200 }, +{ 0x2, 298, 0, 2202 }, +{ 0x1, 298, 0, 2205 }, +{ 0x8, 297, 0, 2199 }, +{ 0x4, 297, 0, 2201 }, +{ 0x2, 297, 1, 2203 }, +{ 0x4, 106, 0, 1249 }, +{ 0x1, 297, 0, 2206 }, +{ 0x1, 6, 0, 2207 }, +{ 0x1, 7, 0, 2208 }, +{ 0x1, 244, 0, 2209 }, +{ 0x1, 243, 0, 2210 }, +{ 0x1, 393, 0, 2211 }, +{ 0x1, 294, 0, 2212 }, +{ 0x1, 12, 0, 2213 }, +{ 0x1, 10, 0, 2214 }, +{ 0x1, 368, 0, 2215 }, +{ 0x1, 342, 0, 2216 }, +{ 0x1, 341, 0, 2217 }, +{ 0x1, 392, 0, 2218 }, +{ 0x1, 293, 0, 2219 }, +{ 0x1, 11, 0, 2220 }, +{ 0x1, 9, 0, 2221 }, +{ 0x1, 5, 0, 2222 }, +{ 0x1, 367, 0, 2223 }, +{ 0x1, 366, 0, 2224 }, +{ 0x1, 1, 0, 2225 }, +{ 0x1, 0, 0, 2226 }, +}; + diff --git a/opcodes/ia64-asmtab.h b/opcodes/ia64-asmtab.h new file mode 100644 index 0000000..822007a --- /dev/null +++ b/opcodes/ia64-asmtab.h @@ -0,0 +1,148 @@ +/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Bob Manson of Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef IA64_ASMTAB_H +#define IA64_ASMTAB_H + +#include "opcode/ia64.h" + +/* The primary opcode table is made up of the following: */ +struct ia64_main_table +{ + /* The entry in the string table that corresponds to the name of this + opcode. */ + unsigned short name_index; + + /* The type of opcode; corresponds to the TYPE field in + struct ia64_opcode. */ + unsigned char opcode_type; + + /* The number of outputs for this opcode. */ + unsigned char num_outputs; + + /* The base insn value for this opcode. It may be modified by completers. */ + ia64_insn opcode; + + /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ + ia64_insn mask; + + /* The operands of this instruction. Corresponds to the OPERANDS field + in struct ia64_opcode. */ + unsigned char operands[5]; + + /* The flags for this instruction. Corresponds to the FLAGS field in + struct ia64_opcode. */ + short flags; + + /* The tree of completers for this instruction; this is an offset into + completer_table. */ + short completers; +}; + +/* Each instruction has a set of possible "completers", or additional + suffixes that can alter the instruction's behavior, and which has + potentially different dependencies. + + The completer entries modify certain bits in the instruction opcode. + Which bits are to be modified are marked by the BITS, MASK and + OFFSET fields. The completer entry may also note dependencies for the + opcode. + + These completers are arranged in a DAG; the pointers are indexes + into the completer_table array. The completer DAG is searched by + find_completer () and ia64_find_matching_opcode (). + + Note that each completer needs to be applied in turn, so that if we + have the instruction + cmp.lt.unc + the completer entries for both "lt" and "unc" would need to be applied + to the opcode's value. + + Some instructions do not require any completers; these contain an + empty completer entry. Instructions that require a completer do + not contain an empty entry. + + Terminal completers (those completers that validly complete an + instruction) are marked by having the TERMINAL_COMPLETER flag set. + + Only dependencies listed in the terminal completer for an opcode are + considered to apply to that opcode instance. */ + +struct ia64_completer_table +{ + /* The bit value that this completer sets. */ + unsigned int bits; + + /* And its mask. 1s are bits that are to be modified in the + instruction. */ + unsigned int mask; + + /* The entry in the string table that corresponds to the name of this + completer. */ + unsigned short name_index; + + /* An alternative completer, or -1 if this is the end of the chain. */ + short alternative; + + /* A pointer to the DAG of completers that can potentially follow + this one, or -1. */ + short subentries; + + /* The bit offset in the instruction where BITS and MASK should be + applied. */ + unsigned char offset : 7; + + unsigned char terminal_completer : 1; + + /* Index into the dependency list table */ + short dependencies; +}; + +/* This contains sufficient information for the disassembler to resolve + the complete name of the original instruction. */ +struct ia64_dis_names +{ + /* COMPLETER_INDEX represents the tree of completers that make up + the instruction. The LSB represents the top of the tree for the + specified instruction. + + A 0 bit indicates to go to the next alternate completer via the + alternative field; a 1 bit indicates that the current completer + is part of the instruction, and to go down the subentries index. + We know we've reached the final completer when we run out of 1 + bits. + + There is always at least one 1 bit. */ + unsigned int completer_index : 20; + + /* The index in the main_table[] array for the instruction. */ + unsigned short insn_index : 11; + + /* If set, the next entry in this table is an alternate possibility + for this instruction encoding. Which one to use is determined by + the instruction type and other factors (see opcode_verify ()). */ + unsigned int next_flag : 1; + + /* The disassembly priority of this entry among instructions. */ + unsigned short priority; +}; + +#endif diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c new file mode 100644 index 0000000..f9add91 --- /dev/null +++ b/opcodes/ia64-dis.c @@ -0,0 +1,273 @@ +/* ia64-dis.c -- Disassemble ia64 instructions + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include + +#include "dis-asm.h" +#include "opcode/ia64.h" + +#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) + +/* Disassemble ia64 instruction. */ + +/* Return the instruction type for OPCODE found in unit UNIT. */ + +static enum ia64_insn_type +unit_to_type (ia64_insn opcode, enum ia64_unit unit) +{ + enum ia64_insn_type type; + int op; + + op = IA64_OP (opcode); + + if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) + { + type = IA64_TYPE_A; + } + else + { + switch (unit) + { + case IA64_UNIT_I: + type = IA64_TYPE_I; break; + case IA64_UNIT_M: + type = IA64_TYPE_M; break; + case IA64_UNIT_B: + type = IA64_TYPE_B; break; + case IA64_UNIT_F: + type = IA64_TYPE_F; break; + case IA64_UNIT_L: + case IA64_UNIT_X: + type = IA64_TYPE_X; break; + default: + type = -1; + } + } + return type; +} + +int +print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) +{ + ia64_insn t0, t1, slot[3], template, s_bit, insn; + int slotnum, j, status, need_comma, retval, slot_multiplier; + const struct ia64_operand *odesc; + const struct ia64_opcode *idesc; + const char *err, *str, *tname; + BFD_HOST_U_64_BIT value; + bfd_byte bundle[16]; + enum ia64_unit unit; + char regname[16]; + + if (info->bytes_per_line == 0) + info->bytes_per_line = 6; + info->display_endian = info->endian; + + slot_multiplier = info->bytes_per_line; + retval = slot_multiplier; + + slotnum = (((long) memaddr) & 0xf) / slot_multiplier; + if (slotnum > 2) + return -1; + + memaddr -= (memaddr & 0xf); + status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* bundles are always in little-endian byte order */ + t0 = bfd_getl64 (bundle); + t1 = bfd_getl64 (bundle + 8); + s_bit = t0 & 1; + template = (t0 >> 1) & 0xf; + slot[0] = (t0 >> 5) & 0x1ffffffffffLL; + slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); + slot[2] = (t1 >> 23) & 0x1ffffffffffLL; + + tname = ia64_templ_desc[template].name; + if (slotnum == 0) + (*info->fprintf_func) (info->stream, "[%s] ", tname); + else + (*info->fprintf_func) (info->stream, " ", tname); + + unit = ia64_templ_desc[template].exec_unit[slotnum]; + + if (template == 2 && slotnum == 1) + { + /* skip L slot in MLI template: */ + slotnum = 2; + retval += slot_multiplier; + } + + insn = slot[slotnum]; + + if (unit == IA64_UNIT_NIL) + goto decoding_failed; + + idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); + if (idesc == NULL) + goto decoding_failed; + + /* print predicate, if any: */ + + if ((idesc->flags & IA64_OPCODE_NO_PRED) + || (insn & 0x3f) == 0) + (*info->fprintf_func) (info->stream, " "); + else + (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); + + /* now the actual instruction: */ + + (*info->fprintf_func) (info->stream, "%s", idesc->name); + if (idesc->operands[0]) + (*info->fprintf_func) (info->stream, " "); + + need_comma = 0; + for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) + { + odesc = elf64_ia64_operands + idesc->operands[j]; + + if (need_comma) + (*info->fprintf_func) (info->stream, ","); + + if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) + { + /* special case of 64 bit immediate load: */ + value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) + | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) + | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) + { + /* 62-bit immediate for nop.x/break.x */ + value = ((slot[1] & 0x1ffffffffffLL) << 21) + | (((insn >> 36) & 0x1) << 20) + | ((insn >> 6) & 0xfffff); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) + { + /* 60-bit immedate for long branches. */ + value = (((insn >> 13) & 0xfffff) + | (((insn >> 36) & 1) << 59) + | (slot[1] << 20)) << 4; + } + else + { + err = (*odesc->extract) (odesc, insn, &value); + if (err) + { + (*info->fprintf_func) (info->stream, "%s", err); + goto done; + } + } + + switch (odesc->class) + { + case IA64_OPND_CLASS_CST: + (*info->fprintf_func) (info->stream, "%s", odesc->str); + break; + + case IA64_OPND_CLASS_REG: + if (odesc->str[0] == 'a' && odesc->str[1] == 'r') + { + switch (value) + { + case 0: case 1: case 2: case 3: + case 4: case 5: case 6: case 7: + sprintf (regname, "ar.k%u", (unsigned int) value); + break; + case 16: strcpy (regname, "ar.rsc"); break; + case 17: strcpy (regname, "ar.bsp"); break; + case 18: strcpy (regname, "ar.bspstore"); break; + case 19: strcpy (regname, "ar.rnat"); break; + case 32: strcpy (regname, "ar.ccv"); break; + case 36: strcpy (regname, "ar.unat"); break; + case 40: strcpy (regname, "ar.fpsr"); break; + case 44: strcpy (regname, "ar.itc"); break; + case 64: strcpy (regname, "ar.pfs"); break; + case 65: strcpy (regname, "ar.lc"); break; + case 66: strcpy (regname, "ar.ec"); break; + default: + sprintf (regname, "ar%u", (unsigned int) value); + break; + } + (*info->fprintf_func) (info->stream, "%s", regname); + } + else + (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_IND: + (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_ABS: + str = 0; + if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) + switch (value) + { + case 0x0: str = "@brcst"; break; + case 0x8: str = "@mix"; break; + case 0x9: str = "@shuf"; break; + case 0xa: str = "@alt"; break; + case 0xb: str = "@rev"; break; + } + + if (str) + (*info->fprintf_func) (info->stream, "%s", str); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) + (*info->fprintf_func) (info->stream, "%lld", value); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) + (*info->fprintf_func) (info->stream, "%llu", value); + else + (*info->fprintf_func) (info->stream, "0x%llx", value); + break; + + case IA64_OPND_CLASS_REL: + (*info->print_address_func) (memaddr + value, info); + break; + } + + need_comma = 1; + if (j + 1 == idesc->num_outputs) + { + (*info->fprintf_func) (info->stream, "="); + need_comma = 0; + } + } + if (slotnum + 1 == ia64_templ_desc[template].group_boundary + || ((slotnum == 2) && s_bit)) + (*info->fprintf_func) (info->stream, ";;"); + + done: + ia64_free_opcode ((struct ia64_opcode *)idesc); + failed: + if (slotnum == 2) + retval += 16 - 3*slot_multiplier; + return retval; + + decoding_failed: + (*info->fprintf_func) (info->stream, " data8 %#011llx", insn); + goto failed; +} diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c new file mode 100644 index 0000000..6443c7c --- /dev/null +++ b/opcodes/ia64-gen.c @@ -0,0 +1,2789 @@ +/* ia64-gen.c -- Generate a shrunk set of opcode tables + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. + Written by Bob Manson, Cygnus Solutions, + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* While the ia64-opc-* set of opcode tables are easy to maintain, + they waste a tremendous amount of space. ia64-gen rearranges the + instructions into a directed acyclic graph (DAG) of instruction opcodes and + their possible completers, as well as compacting the set of strings used. + + The disassembler table consists of a state machine that does + branching based on the bits of the opcode being disassembled. The + state encodings have been chosen to minimize the amount of space + required. + + The resource table is constructed based on some text dependency tables, + which are also easier to maintain than the final representation. + +*/ + +#include + +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "sysdep.h" +#include "ia64-opc.h" +#include "ia64-opc-a.c" +#include "ia64-opc-i.c" +#include "ia64-opc-m.c" +#include "ia64-opc-b.c" +#include "ia64-opc-f.c" +#include "ia64-opc-x.c" +#include "ia64-opc-d.c" + +int debug = 0; + +#define tmalloc(X) (X *) xmalloc (sizeof (X)) + +/* The main opcode table entry. Each entry is a unique combination of + name and flags (no two entries in the table compare as being equal + via opcodes_eq). */ +struct main_entry +{ + /* The base name of this opcode. The names of its completers are + appended to it to generate the full instruction name. */ + struct string_entry *name; + /* The base opcode entry. Which one to use is a fairly arbitrary choice; + it uses the first one passed to add_opcode_entry. */ + struct ia64_opcode *opcode; + /* The list of completers that can be applied to this opcode. */ + struct completer_entry *completers; + /* Next entry in the chain. */ + struct main_entry *next; + /* Index in the main table. */ + int main_index; +} *maintable, **ordered_table; +int otlen = 0; +int ottotlen = 0; +int opcode_count = 0; + +/* The set of possible completers for an opcode. */ +struct completer_entry +{ + /* This entry's index in the ia64_completer_table[] array. */ + int num; + + /* The name of the completer. */ + struct string_entry *name; + + /* This entry's parent. */ + struct completer_entry *parent; + + /* Set if this is a terminal completer (occurs at the end of an + opcode). */ + int is_terminal; + + /* An alternative completer. */ + struct completer_entry *alternative; + + /* Additional completers that can be appended to this one. */ + struct completer_entry *addl_entries; + + /* Before compute_completer_bits () is invoked, this contains the actual + instruction opcode for this combination of opcode and completers. + Afterwards, it contains those bits that are different from its + parent opcode. */ + ia64_insn bits; + + /* Bits set to 1 correspond to those bits in this completer's opcode + that are different from its parent completer's opcode (or from + the base opcode if the entry is the root of the opcode's completer + list). This field is filled in by compute_completer_bits (). */ + ia64_insn mask; + + /* Index into the opcode dependency list, or -1 if none. */ + int dependencies; + + /* Remember the order encountered in the opcode tables. */ + int order; +}; + +/* One entry in the disassembler name table. */ +struct disent +{ + /* The index into the ia64_name_dis array for this entry. */ + int ournum; + + /* The index into the main_table[] array. */ + int insn; + + /* The disassmbly priority of this entry. */ + int priority; + + /* The completer_index value for this entry. */ + int completer_index; + + /* How many other entries share this decode. */ + int nextcnt; + + /* The next entry sharing the same decode. */ + struct disent *nexte; + + /* The next entry in the name list. */ + struct disent *next_ent; +} *disinsntable = NULL; + +/* A state machine that will eventually be used to generate the + disassembler table. */ +struct bittree +{ + struct disent *disent; + struct bittree *bits[3]; /* 0, 1, and X (don't care) */ + int bits_to_skip; + int skip_flag; +} *bittree; + +/* The string table contains all opcodes and completers sorted in + alphabetical order. */ + +/* One entry in the string table. */ +struct string_entry +{ + /* The index in the ia64_strings[] array for this entry. */ + int num; + /* And the string. */ + char *s; +} **string_table = NULL; +int strtablen = 0; +int strtabtotlen = 0; + + +/* resource dependency entries */ +struct rdep +{ + char *name; /* resource name */ + unsigned + mode:2, /* RAW, WAW, or WAR */ + semantics:3; /* dependency semantics */ + char *extra; /* additional semantics info */ + int nchks; + int total_chks; /* total #of terminal insns */ + int *chks; /* insn classes which read (RAW), write + (WAW), or write (WAR) this rsrc */ + int *chknotes; /* dependency notes for each class */ + int nregs; + int total_regs; /* total #of terminal insns */ + int *regs; /* insn class which write (RAW), write2 + (WAW), or read (WAR) this rsrc */ + int *regnotes; /* dependency notes for each class */ + + int waw_special; /* special WAW dependency note */ +} **rdeps = NULL; + +static int rdepslen = 0; +static int rdepstotlen = 0; + +/* array of all instruction classes */ +struct iclass +{ + char *name; /* instruction class name */ + int is_class; /* is a class, not a terminal */ + int nsubs; + int *subs; /* other classes within this class */ + int nxsubs; + int xsubs[4]; /* exclusions */ + char *comment; /* optional comment */ + int note; /* optional note */ + int terminal_resolved; /* did we match this with anything? */ + int orphan; /* detect class orphans */ +} **ics = NULL; + +static int iclen = 0; +static int ictotlen = 0; + +/* an opcode dependency (chk/reg pair of dependency lists) */ +struct opdep +{ + int chk; /* index into dlists */ + int reg; /* index into dlists */ +} **opdeps; + +static int opdeplen = 0; +static int opdeptotlen = 0; + +/* a generic list of dependencies w/notes encoded. these may be shared. */ +struct deplist +{ + int len; + unsigned short *deps; +} **dlists; + +static int dlistlen = 0; +static int dlisttotlen = 0; + +/* add NAME to the resource table, where TYPE is RAW or WAW */ +static struct rdep * +insert_resource (const char *name, enum ia64_dependency_mode type) +{ + if (rdepslen == rdepstotlen) + { + rdepstotlen += 20; + rdeps = (struct rdep **) + xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); + } + rdeps[rdepslen] = tmalloc(struct rdep); + memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); + rdeps[rdepslen]->name = xstrdup (name); + rdeps[rdepslen]->mode = type; + rdeps[rdepslen]->waw_special = 0; + + return rdeps[rdepslen++]; +} + +/* are the lists of dependency indexes equivalent? */ +static int +deplist_equals (struct deplist *d1, struct deplist *d2) +{ + int i; + + if (d1->len != d2->len) + return 0; + + for (i=0;i < d1->len;i++) + { + if (d1->deps[i] != d2->deps[i]) + return 0; + } + + return 1; +} + +/* add the list of dependencies to the list of dependency lists */ +static short +insert_deplist(int count, unsigned short *deps) +{ + /* sort the list, then see if an equivalent list exists already. + this results in a much smaller set of dependency lists + */ + struct deplist *list; + char set[0x10000]; + int i; + + memset ((void *)set, 0, sizeof(set)); + for (i=0;i < count;i++) + set[deps[i]] = 1; + count = 0; + for (i=0;i < (int)sizeof(set);i++) + if (set[i]) + ++count; + + list = tmalloc(struct deplist); + list->len = count; + list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count); + for (i=0, count=0;i < (int)sizeof(set);i++) + { + if (set[i]) + { + list->deps[count++] = i; + } + } + + /* does this list exist already? */ + for (i=0;i < dlistlen;i++) + { + if (deplist_equals (list, dlists[i])) + { + free (list->deps); + free (list); + return i; + } + } + + if (dlistlen == dlisttotlen) + { + dlisttotlen += 20; + dlists = (struct deplist **) + xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); + } + dlists[dlistlen] = list; + + return dlistlen++; +} + +/* add the given pair of dependency lists to the opcode dependency list */ +static short +insert_dependencies (int nchks, unsigned short *chks, + int nregs, unsigned short *regs) +{ + struct opdep *pair; + int i; + int regind = -1; + int chkind = -1; + + if (nregs > 0) + regind = insert_deplist (nregs, regs); + if (nchks > 0) + chkind = insert_deplist (nchks, chks); + + for (i=0;i < opdeplen;i++) + { + if (opdeps[i]->chk == chkind + && opdeps[i]->reg == regind) + return i; + } + pair = tmalloc(struct opdep); + pair->chk = chkind; + pair->reg = regind; + + if (opdeplen == opdeptotlen) + { + opdeptotlen += 20; + opdeps = (struct opdep **) + xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); + } + opdeps[opdeplen] = pair; + + return opdeplen++; +} + +static void +mark_used (struct iclass *ic, int clear_terminals) +{ + int i; + + ic->orphan = 0; + if (clear_terminals) + ic->terminal_resolved = 1; + + for (i=0;i < ic->nsubs;i++) + { + mark_used (ics[ic->subs[i]], clear_terminals); + } + for (i=0;i < ic->nxsubs;i++) + { + mark_used (ics[ic->xsubs[i]], clear_terminals); + } +} + +/* look up an instruction class; if CREATE make a new one if none found; + returns the index into the insn class array */ +static int +fetch_insn_class(const char *full_name, int create) +{ + char *name; + char *notestr; + char *xsect; + char *comment; + int i, note = 0; + int ind; + int is_class = 0; + + if (strncmp (full_name, "IC:", 3) == 0) + { + name = xstrdup (full_name + 3); + is_class = 1; + } + else + name = xstrdup (full_name); + + if ((xsect = strchr(name, '\\')) != NULL) + is_class = 1; + if ((comment = strchr(name, '[')) != NULL) + is_class = 1; + if ((notestr = strchr(name, '+')) != NULL) + is_class = 1; + + /* If it is a composite class, then ignore comments and notes that come after + the '\\', since they don't apply to the part we are decoding now. */ + if (xsect) + { + if (comment > xsect) + comment = 0; + if (notestr > xsect) + notestr = 0; + } + + if (notestr) + { + char *nextnotestr; + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + fprintf (stderr, "Warning: multiple note %s not handled\n", + notestr); + } + } + + /* If it's a composite class, leave the notes and comments in place so that + we have a unique name for the composite class. Otherwise, we remove + them. */ + if (!xsect) + { + if (notestr) + *notestr = 0; + if (comment) + *comment = 0; + } + + for (i=0;i < iclen;i++) + if (strcmp(name, ics[i]->name) == 0 + && ((comment == NULL && ics[i]->comment == NULL) + || (comment != NULL && ics[i]->comment != NULL + && strncmp (ics[i]->comment, comment, + strlen (ics[i]->comment)) == 0)) + && note == ics[i]->note) + return i; + + if (!create) + return -1; + + /* doesn't exist, so make a new one */ + if (iclen == ictotlen) + { + ictotlen += 20; + ics = (struct iclass **) + xrealloc(ics, (ictotlen)*sizeof(struct iclass *)); + } + ind = iclen++; + ics[ind] = tmalloc(struct iclass); + memset((void *)ics[ind], 0, sizeof(struct iclass)); + ics[ind]->name = xstrdup(name); + ics[ind]->is_class = is_class; + ics[ind]->orphan = 1; + + if (comment) + { + ics[ind]->comment = xstrdup (comment + 1); + ics[ind]->comment[strlen(ics[ind]->comment)-1] = 0; + } + if (notestr) + ics[ind]->note = note; + + /* if it's a composite class, there's a comment or note, look for an + existing class or terminal with the same name. */ + if ((xsect || comment || notestr) && is_class) + { + /* First, populate with the class we're based on. */ + char *subname = name; + if (xsect) + *xsect = 0; + else if (comment) + *comment = 0; + else if (notestr) + *notestr = 0; + ics[ind]->nsubs = 1; + ics[ind]->subs = tmalloc(int); + ics[ind]->subs[0] = fetch_insn_class (subname, 1);; + } + + while (xsect) + { + char *subname = xsect + 1; + xsect = strchr (subname, '\\'); + if (xsect) + *xsect = 0; + ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1); + ics[ind]->nxsubs++; + } + free (name); + + return ind; +} + +/* for sorting a class's sub-class list only; make sure classes appear before + terminals */ +static int +sub_compare (const void *e1, const void *e2) +{ + struct iclass *ic1 = ics[*(int *)e1]; + struct iclass *ic2 = ics[*(int *)e2]; + + if (ic1->is_class) + { + if (!ic2->is_class) + return -1; + } + else if (ic2->is_class) + return 1; + + return strcmp (ic1->name, ic2->name); +} + +static void +load_insn_classes() +{ + FILE *fp = fopen("ia64-ic.tbl", "r"); + char buf[2048]; + + if (fp == NULL){ + fprintf (stderr, "Can't find ia64-ic.tbl for reading\n"); + exit(1); + } + + /* discard first line */ + fgets (buf, sizeof(buf), fp); + + while (!feof(fp)) + { + int iclass; + char *name; + char *tmp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (ISSPACE (buf[strlen(buf)-1])) + buf[strlen(buf)-1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort (); + } + *tmp++ = '\0'; + + iclass = fetch_insn_class(name, 1); + ics[iclass]->is_class = 1; + + if (strcmp (name, "none") == 0) + { + ics[iclass]->is_class = 0; + ics[iclass]->terminal_resolved = 1; + continue; + } + + /* for this class, record all sub-classes */ + while (*tmp) + { + char *subname; + int sub; + + while (*tmp && ISSPACE (*tmp)) + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort(); + } + subname = tmp; + while (*tmp && *tmp != ',') + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort(); + } + if (*tmp == ',') + *tmp++ = '\0'; + + ics[iclass]->subs = (int *) + xrealloc((void *)ics[iclass]->subs, + (ics[iclass]->nsubs+1)*sizeof(int)); + + sub = fetch_insn_class(subname, 1); + ics[iclass]->subs = (int *) + xrealloc(ics[iclass]->subs, (ics[iclass]->nsubs+1)*sizeof(int)); + ics[iclass]->subs[ics[iclass]->nsubs++] = sub; + } + /* make sure classes come before terminals */ + qsort ((void *)ics[iclass]->subs, + ics[iclass]->nsubs, sizeof(int), sub_compare); + } + fclose(fp); + + if (debug) + { + printf ("%d classes\n", iclen); + } +} + +/* extract the insn classes from the given line */ +static void +parse_resource_users(ref, usersp, nusersp, notesp) + char *ref; + int **usersp; + int *nusersp; + int **notesp; +{ + int c; + char *line = xstrdup (ref); + char *tmp = line; + int *users = *usersp; + int count = *nusersp; + int *notes = *notesp; + + c = *tmp; + while (c != 0) + { + char *notestr; + int note; + char *xsect; + int iclass; + int create = 0; + char *name; + + while (ISSPACE (*tmp)) + ++tmp; + name = tmp; + while (*tmp && *tmp != ',') + ++tmp; + c = *tmp; + *tmp++ = '\0'; + + xsect = strchr(name, '\\'); + if ((notestr = strstr(name, "+")) != NULL) + { + char *nextnotestr; + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + /* note 13 always implies note 1 */ + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + fprintf (stderr, "Warning: multiple note %s not handled\n", + notestr); + } + if (!xsect) + *notestr = '\0'; + } + else + note = 0; + + /* All classes are created when the insn class table is parsed; + Individual instructions might not appear until the dependency tables + are read. Only create new classes if it's *not* an insn class, + or if it's a composite class (which wouldn't necessarily be in the IC + table). + */ + if (strncmp(name, "IC:", 3) != 0 || xsect != NULL) + create = 1; + + iclass = fetch_insn_class(name, create); + if (iclass != -1) + { + users = (int *) + xrealloc ((void *)users,(count+1)*sizeof(int)); + notes = (int *) + xrealloc ((void *)notes,(count+1)*sizeof(int)); + notes[count] = note; + users[count++] = iclass; + mark_used (ics[iclass], 0); + } + else + { + if (debug) + printf("Class %s not found\n", name); + } + } + /* update the return values */ + *usersp = users; + *nusersp = count; + *notesp = notes; + + free (line); +} + +static int +parse_semantics (char *sem) +{ + if (strcmp (sem, "none") == 0) + return IA64_DVS_NONE; + else if (strcmp (sem, "implied") == 0) + return IA64_DVS_IMPLIED; + else if (strcmp (sem, "impliedF") == 0) + return IA64_DVS_IMPLIEDF; + else if (strcmp (sem, "data") == 0) + return IA64_DVS_DATA; + else if (strcmp (sem, "instr") == 0) + return IA64_DVS_INSTR; + else if (strcmp (sem, "specific") == 0) + return IA64_DVS_SPECIFIC; + else if (strcmp (sem, "stop") == 0) + return IA64_DVS_STOP; + else + return IA64_DVS_OTHER; +} + +static void +add_dep (const char *name, const char *chk, const char *reg, + int semantics, int mode, char *extra, int flag) +{ + struct rdep *rs; + + rs = insert_resource (name, mode); + parse_resource_users (chk, &rs->chks, &rs->nchks, + &rs->chknotes); + parse_resource_users (reg, &rs->regs, &rs->nregs, + &rs->regnotes); + rs->semantics = semantics; + rs->extra = extra; + rs->waw_special = flag; +} + +static void +load_depfile (const char *filename, enum ia64_dependency_mode mode) +{ + FILE *fp = fopen(filename, "r"); + char buf[1024]; + + if (fp == NULL){ + fprintf (stderr, "Can't find %s for reading\n", filename); + exit(1); + } + + fgets(buf, sizeof(buf), fp); + while (!feof(fp)) + { + char *name, *tmp; + int semantics; + char *extra; + char *regp, *chkp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (ISSPACE (buf[strlen(buf)-1])) + buf[strlen(buf)-1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + ++tmp; + *tmp++ = '\0'; + + while (ISSPACE (*tmp)) + ++tmp; + regp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (ISSPACE (*tmp)) + ++tmp; + chkp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (ISSPACE (*tmp)) + ++tmp; + semantics = parse_semantics (tmp); + extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; + + /* For WAW entries, if the chks and regs differ, we need to enter the + entries in both positions so that the tables will be parsed properly, + without a lot of extra work */ + if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + add_dep (name, regp, chkp, semantics, mode, extra, 1); + } + else + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + } + } + fclose(fp); +} + +static void +load_dependencies() +{ + load_depfile ("ia64-raw.tbl", IA64_DV_RAW); + load_depfile ("ia64-waw.tbl", IA64_DV_WAW); + load_depfile ("ia64-war.tbl", IA64_DV_WAR); + + if (debug) + printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); +} + +/* is the given operand an indirect register file operand? */ +static int +irf_operand (int op, const char *field) +{ + if (!field) + { + return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 + || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 + || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 + || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; + } + else + { + return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) + || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) + || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) + || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) + || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) + || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) + || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) + || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))); + } +} + +/* handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and + mov_um insn classes */ +static int +in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field) +{ + int plain_mov = strcmp (idesc->name, "mov") == 0; + + if (!format) + return 0; + + switch (ic->name[4]) + { + default: + abort (); + case 'a': + { + int i = strcmp (idesc->name, "mov.i") == 0; + int m = strcmp (idesc->name, "mov.m") == 0; + int i2627 = i && idesc->operands[0] == IA64_OPND_AR3; + int i28 = i && idesc->operands[1] == IA64_OPND_AR3; + int m2930 = m && idesc->operands[0] == IA64_OPND_AR3; + int m31 = m && idesc->operands[1] == IA64_OPND_AR3; + int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3; + int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3; + + /* IC:mov ar */ + if (i2627) + return strstr (format, "I26") || strstr (format, "I27"); + if (i28) + return strstr (format, "I28") != NULL; + if (m2930) + return strstr (format, "M29") || strstr (format, "M30"); + if (m31) + return strstr (format, "M31") != NULL; + if (pseudo0 || pseudo1) + return 1; + } + break; + case 'b': + { + int i21 = idesc->operands[0] == IA64_OPND_B1; + int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2; + if (i22) + return strstr (format, "I22") != NULL; + if (i21) + return strstr (format, "I21") != NULL; + } + break; + case 'c': + { + int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3; + int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3; + if (m32) + return strstr (format, "M32") != NULL; + if (m33) + return strstr (format, "M33") != NULL; + } + break; + case 'i': + if (ic->name[5] == 'n') + { + int m42 = plain_mov && irf_operand (idesc->operands[0], field); + int m43 = plain_mov && irf_operand (idesc->operands[1], field); + if (m42) + return strstr (format, "M42") != NULL; + if (m43) + return strstr (format, "M43") != NULL; + } + else if (ic->name[5] == 'p') + { + return idesc->operands[1] == IA64_OPND_IP; + } + else + abort (); + break; + case 'p': + if (ic->name[5] == 'r') + { + int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR; + int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR; + int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT; + if (i23) + return strstr (format, "I23") != NULL; + if (i24) + return strstr (format, "I24") != NULL; + if (i25) + return strstr (format, "I25") != NULL; + } + else if (ic->name[5] == 's') + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + else + abort (); + break; + case 'u': + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + break; + } + return 0; +} + + +/* is the given opcode in the given insn class? */ +static int +in_iclass(struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field, int *notep) +{ + int i; + int resolved = 0; + + if (ic->comment) + { + if (!strncmp (ic->comment, "Format", 6)) + { + /* assume that the first format seen is the most restrictive, and + only keep a later one if it looks like it's more restrictive. */ + if (format) + { + if (strlen (ic->comment) < strlen (format)) + { + fprintf (stderr, "Warning: most recent format '%s'\n" + "appears more restrictive than '%s'\n", + ic->comment, format); + format = ic->comment; + } + } + else + format = ic->comment; + } + else if (!strncmp (ic->comment, "Field", 5)) + { + if (field) + fprintf (stderr, "Overlapping field %s->%s\n", + ic->comment, field); + field = ic->comment; + } + } + + /* an insn class matches anything that is the same followed by completers, + except when the absence and presence of completers constitutes different + instructions */ + if (ic->nsubs == 0 && ic->nxsubs == 0) + { + int is_mov = strncmp (idesc->name, "mov", 3) == 0; + int plain_mov = strcmp (idesc->name, "mov") == 0; + int len = strlen(ic->name); + + resolved = ((strncmp (ic->name, idesc->name, len) == 0) + && (idesc->name[len] == '\0' + || idesc->name[len] == '.')); + + /* all break and nop variations must match exactly */ + if (resolved && + (strcmp (ic->name, "break") == 0 + || strcmp (ic->name, "nop") == 0)) + resolved = strcmp (ic->name, idesc->name) == 0; + + /* assume restrictions in the FORMAT/FIELD negate resolution, + unless specifically allowed by clauses in this block */ + if (resolved && field) + { + /* check Field(sf)==sN against opcode sN */ + if (strstr(field, "(sf)==") != NULL) + { + char *sf; + if ((sf = strstr (idesc->name, ".s")) != 0) + { + resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; + } + } + /* check Field(lftype)==XXX */ + else if (strstr (field, "(lftype)") != NULL) + { + if (strstr (idesc->name, "fault") != NULL) + resolved = strstr (field, "fault") != NULL; + else + resolved = strstr (field, "fault") == NULL; + } + /* handle Field(ctype)==XXX */ + else if (strstr (field, "(ctype)") != NULL) + { + if (strstr (idesc->name, "or.andcm")) + resolved = strstr (field, "or.andcm") != NULL; + else if (strstr (idesc->name, "and.orcm")) + resolved = strstr (field, "and.orcm") != NULL; + else if (strstr (idesc->name, "orcm")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "or")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "andcm")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "and")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "unc")) + resolved = strstr (field, "unc") != NULL; + else + resolved = strcmp (field, "Field(ctype)==") == 0; + } + } + if (resolved && format) + { + if (strncmp (idesc->name, "dep", 3) == 0 + && strstr (format, "I13") != NULL) + resolved = idesc->operands[1] == IA64_OPND_IMM8; + else if (strncmp (idesc->name, "chk", 3) == 0 + && strstr (format, "M21") != NULL) + resolved = idesc->operands[0] == IA64_OPND_F2; + else if (strncmp (idesc->name, "lfetch", 6) == 0) + resolved = (strstr (format, "M14 M15") != NULL + && (idesc->operands[1] == IA64_OPND_R2 + || idesc->operands[1] == IA64_OPND_IMM9b)); + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B5") != NULL) + resolved = idesc->operands[1] == IA64_OPND_B2; + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B3") != NULL) + resolved = idesc->operands[1] == IA64_OPND_TGT25c; + else if (strncmp (idesc->name, "brp", 3) == 0 + && strstr (format, "B7") != NULL) + resolved = idesc->operands[0] == IA64_OPND_B2; + else if (strcmp (ic->name, "invala") == 0) + resolved = strcmp (idesc->name, ic->name) == 0; + else if (strncmp (idesc->name, "st", 2) == 0 + && strstr (format, "M5") != NULL) + resolved = idesc->flags & IA64_OPCODE_POSTINC; + else + resolved = 0; + } + + /* misc brl variations ('.cond' is optional); + plain brl matches brl.cond */ + if (!resolved + && (strcmp (idesc->name, "brl") == 0 + || strncmp (idesc->name, "brl.", 4) == 0) + && strcmp (ic->name, "brl.cond") == 0) + { + resolved = 1; + } + + /* misc br variations ('.cond' is optional) */ + if (!resolved + && (strcmp (idesc->name, "br") == 0 + || strncmp (idesc->name, "br.", 3) == 0) + && strcmp (ic->name, "br.cond") == 0) + { + if (format) + resolved = (strstr (format, "B4") != NULL + && idesc->operands[0] == IA64_OPND_B2) + || (strstr (format, "B1") != NULL + && idesc->operands[0] == IA64_OPND_TGT25c); + else + resolved = 1; + } + + /* probe variations */ + if (!resolved && strncmp (idesc->name, "probe", 5) == 0) + { + resolved = strcmp (ic->name, "probe") == 0 + && !((strstr (idesc->name, "fault") != NULL) + ^ (format && strstr (format, "M40") != NULL)); + } + /* mov variations */ + if (!resolved && is_mov) + { + if (plain_mov) + { + /* mov alias for fmerge */ + if (strcmp (ic->name, "fmerge") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_F1 + && idesc->operands[1] == IA64_OPND_F3; + } + /* mov alias for adds (r3 or imm14) */ + else if (strcmp (ic->name, "adds") == 0) + { + resolved = (idesc->operands[0] == IA64_OPND_R1 + && (idesc->operands[1] == IA64_OPND_R3 + || (idesc->operands[1] == IA64_OPND_IMM14))); + } + /* mov alias for addl */ + else if (strcmp (ic->name, "addl") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_R1 + && idesc->operands[1] == IA64_OPND_IMM22; + } + } + /* some variants of mov and mov.[im] */ + if (!resolved && strncmp (ic->name, "mov_", 4) == 0) + { + resolved = in_iclass_mov_x (idesc, ic, format, field); + } + } + + /* keep track of this so we can flag any insn classes which aren't + mapped onto at least one real insn */ + if (resolved) + { + ic->terminal_resolved = 1; + } + } + else for (i=0;i < ic->nsubs;i++) + { + if (in_iclass(idesc, ics[ic->subs[i]], format, field, notep)) + { + int j; + for (j=0;j < ic->nxsubs;j++) + { + if (in_iclass(idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) + return 0; + } + if (debug > 1) + printf ("%s is in IC %s\n", + idesc->name, ic->name); + resolved = 1; + break; + } + } + + /* If it's in this IC, add the IC note (if any) to the insn */ + if (resolved) + { + if (ic->note && notep) + { + if (*notep && *notep != ic->note) + { + fprintf (stderr, "Warning: overwriting note %d with note %d" + "(IC:%s)\n", + *notep, ic->note, ic->name); + } + *notep = ic->note; + } + } + + return resolved; +} + + +static int +lookup_regindex (const char *name, int specifier) +{ + switch (specifier) + { + case IA64_RS_ARX: + if (strstr (name, "[RSC]")) + return 16; + if (strstr (name, "[BSP]")) + return 17; + else if (strstr (name, "[BSPSTORE]")) + return 18; + else if (strstr (name, "[RNAT]")) + return 19; + else if (strstr (name, "[CCV]")) + return 32; + else if (strstr (name, "[ITC]")) + return 44; + else if (strstr (name, "[PFS]")) + return 64; + else if (strstr (name, "[LC]")) + return 65; + else if (strstr (name, "[EC]")) + return 66; + abort (); + case IA64_RS_CRX: + if (strstr (name, "[DCR]")) + return 0; + else if (strstr (name, "[ITM]")) + return 1; + else if (strstr (name, "[IVA]")) + return 2; + else if (strstr (name, "[PTA]")) + return 8; + else if (strstr (name, "[GPTA]")) + return 9; + else if (strstr (name, "[IPSR]")) + return 16; + else if (strstr (name, "[ISR]")) + return 17; + else if (strstr (name, "[IIP]")) + return 19; + else if (strstr (name, "[IFA]")) + return 20; + else if (strstr (name, "[ITIR]")) + return 21; + else if (strstr (name, "[IIPA]")) + return 22; + else if (strstr (name, "[IFS]")) + return 23; + else if (strstr (name, "[IIM]")) + return 24; + else if (strstr (name, "[IHA]")) + return 25; + else if (strstr (name, "[LID]")) + return 64; + else if (strstr (name, "[IVR]")) + return 65; + else if (strstr (name, "[TPR]")) + return 66; + else if (strstr (name, "[EOI]")) + return 67; + else if (strstr (name, "[ITV]")) + return 72; + else if (strstr (name, "[PMV]")) + return 73; + else if (strstr (name, "[CMCV]")) + return 74; + abort (); + case IA64_RS_PSR: + if (strstr (name, ".be")) + return 1; + else if (strstr (name, ".up")) + return 2; + else if (strstr (name, ".ac")) + return 3; + else if (strstr (name, ".mfl")) + return 4; + else if (strstr (name, ".mfh")) + return 5; + else if (strstr (name, ".ic")) + return 13; + else if (strstr (name, ".i")) + return 14; + else if (strstr (name, ".pk")) + return 15; + else if (strstr (name, ".dt")) + return 17; + else if (strstr (name, ".dfl")) + return 18; + else if (strstr (name, ".dfh")) + return 19; + else if (strstr (name, ".sp")) + return 20; + else if (strstr (name, ".pp")) + return 21; + else if (strstr (name, ".di")) + return 22; + else if (strstr (name, ".si")) + return 23; + else if (strstr (name, ".db")) + return 24; + else if (strstr (name, ".lp")) + return 25; + else if (strstr (name, ".tb")) + return 26; + else if (strstr (name, ".rt")) + return 27; + else if (strstr (name, ".cpl")) + return 32; + else if (strstr (name, ".rs")) + return 34; + else if (strstr (name, ".mc")) + return 35; + else if (strstr (name, ".it")) + return 36; + else if (strstr (name, ".id")) + return 37; + else if (strstr (name, ".da")) + return 38; + else if (strstr (name, ".dd")) + return 39; + else if (strstr (name, ".ss")) + return 40; + else if (strstr (name, ".ri")) + return 41; + else if (strstr (name, ".ed")) + return 43; + else if (strstr (name, ".bn")) + return 44; + else if (strstr (name, ".ia")) + return 45; + else + abort (); + default: + break; + } + return REG_NONE; +} + +static int +lookup_specifier (const char *name) +{ + if (strchr (name, '%')) + { + if (strstr (name, "AR[K%]") != NULL) + return IA64_RS_AR_K; + if (strstr (name, "AR[UNAT]") != NULL) + return IA64_RS_AR_UNAT; + if (strstr (name, "AR%, % in 8") != NULL) + return IA64_RS_AR; + if (strstr (name, "AR%, % in 48") != NULL) + return IA64_RS_ARb; + if (strstr (name, "BR%") != NULL) + return IA64_RS_BR; + if (strstr (name, "CR[IRR%]") != NULL) + return IA64_RS_CR_IRR; + if (strstr (name, "CR[LRR%]") != NULL) + return IA64_RS_CR_LRR; + if (strstr (name, "CR%") != NULL) + return IA64_RS_CR; + if (strstr (name, "FR%, % in 0") != NULL) + return IA64_RS_FR; + if (strstr (name, "FR%, % in 2") != NULL) + return IA64_RS_FRb; + if (strstr (name, "GR%") != NULL) + return IA64_RS_GR; + if (strstr (name, "PR%, % in 1 ") != NULL) + return IA64_RS_PR; + if (strstr (name, "PR%, % in 16 ") != NULL) + return IA64_RS_PRr; + + fprintf (stderr, "Warning! Don't know how to specify %% dependency %s\n", + name); + } + else if (strchr (name, '#')) + { + if (strstr (name, "CPUID#") != NULL) + return IA64_RS_CPUID; + if (strstr (name, "DBR#") != NULL) + return IA64_RS_DBR; + if (strstr (name, "IBR#") != NULL) + return IA64_RS_IBR; + if (strstr (name, "MSR#") != NULL) + return IA64_RS_MSR; + if (strstr (name, "PKR#") != NULL) + return IA64_RS_PKR; + if (strstr (name, "PMC#") != NULL) + return IA64_RS_PMC; + if (strstr (name, "PMD#") != NULL) + return IA64_RS_PMD; + if (strstr (name, "RR#") != NULL) + return IA64_RS_RR; + + fprintf (stderr, "Warning! Don't know how to specify # dependency %s\n", + name); + } + else if (strncmp (name, "AR[FPSR]", 8) == 0) + return IA64_RS_AR_FPSR; + else if (strncmp (name, "AR[", 3) == 0) + return IA64_RS_ARX; + else if (strncmp (name, "CR[", 3) == 0) + return IA64_RS_CRX; + else if (strncmp (name, "PSR.", 4) == 0) + return IA64_RS_PSR; + else if (strcmp (name, "InService*") == 0) + return IA64_RS_INSERVICE; + else if (strcmp (name, "GR0") == 0) + return IA64_RS_GR0; + else if (strcmp (name, "CFM") == 0) + return IA64_RS_CFM; + else if (strcmp (name, "PR63") == 0) + return IA64_RS_PR63; + else if (strcmp (name, "RSE") == 0) + return IA64_RS_RSE; + + return IA64_RS_ANY; +} + +void +print_dependency_table () +{ + int i, j; + + if (debug) + { + for (i=0;i < iclen;i++) + { + if (ics[i]->is_class) + { + if (!ics[i]->nsubs) + { + fprintf (stderr, "Warning: IC:%s", ics[i]->name); + if (ics[i]->comment) + fprintf (stderr, "[%s]", ics[i]->comment); + fprintf (stderr, " has no terminals or sub-classes\n"); + } + } + else + { + if (!ics[i]->terminal_resolved && !ics[i]->orphan) + { + fprintf(stderr, "Warning: no insns mapped directly to " + "terminal IC %s", ics[i]->name); + if (ics[i]->comment) + fprintf(stderr, "[%s] ", ics[i]->comment); + fprintf(stderr, "\n"); + } + } + } + + for (i=0;i < iclen;i++) + { + if (ics[i]->orphan) + { + mark_used (ics[i], 1); + fprintf (stderr, "Warning: class %s is defined but not used\n", + ics[i]->name); + } + } + + if (debug > 1) for (i=0;i < rdepslen;i++) + { + static const char *mode_str[] = { "RAW", "WAW", "WAR" }; + if (rdeps[i]->total_chks == 0) + { + fprintf (stderr, "Warning: rsrc %s (%s) has no chks%s\n", + rdeps[i]->name, mode_str[rdeps[i]->mode], + rdeps[i]->total_regs ? "" : " or regs"); + } + else if (rdeps[i]->total_regs == 0) + { + fprintf (stderr, "Warning: rsrc %s (%s) has no regs\n", + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } + } + } + + /* the dependencies themselves */ + printf ("static const struct ia64_dependency\ndependencies[] = {\n"); + for (i=0;i < rdepslen;i++) + { + /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual + resource used */ + int specifier = lookup_specifier (rdeps[i]->name); + int regindex = lookup_regindex (rdeps[i]->name, specifier); + + printf (" { \"%s\", %d, %d, %d, %d, ", + rdeps[i]->name, specifier, + (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); + if (rdeps[i]->semantics == IA64_DVS_OTHER) + printf ("\"%s\", ", rdeps[i]->extra); + else + printf ("NULL, "); + printf("},\n"); + } + printf ("};\n\n"); + + /* and dependency lists */ + for (i=0;i < dlistlen;i++) + { + int len = 2; + printf ("static const short dep%d[] = {\n ", i); + for (j=0;j < dlists[i]->len; j++) + { + len += printf ("%d, ", dlists[i]->deps[j]); + if (len > 75) + { + printf("\n "); + len = 2; + } + } + printf ("\n};\n\n"); + } + + /* and opcode dependency list */ + printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); + printf ("static const struct ia64_opcode_dependency\n"); + printf ("op_dependencies[] = {\n"); + for (i=0;i < opdeplen;i++) + { + printf (" { "); + if (opdeps[i]->chk == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); + if (opdeps[i]->reg == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); + printf ("},\n"); + } + printf ("};\n\n"); +} + + +/* Add STR to the string table. */ + +static struct string_entry * +insert_string (str) + char *str; +{ + int start = 0, end = strtablen; + int i, x; + + if (strtablen == strtabtotlen) + { + strtabtotlen += 20; + string_table = (struct string_entry **) + xrealloc (string_table, + sizeof (struct string_entry **) * strtabtotlen); + } + + if (strtablen == 0) + { + strtablen = 1; + string_table[0] = tmalloc (struct string_entry); + string_table[0]->s = xstrdup (str); + string_table[0]->num = 0; + return string_table[0]; + } + + if (strcmp (str, string_table[strtablen - 1]->s) > 0) + { + i = end; + } + else if (strcmp (str, string_table[0]->s) < 0) + { + i = 0; + } + else + { + while (1) + { + int c; + + i = (start + end) / 2; + c = strcmp (str, string_table[i]->s); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return string_table[i]; + } + else + { + start = i + 1; + } + if (start > end) + { + break; + } + } + } + for (; i > 0 && i < strtablen; i--) + { + if (strcmp (str, string_table[i - 1]->s) > 0) + { + break; + } + } + for (; i < strtablen; i++) + { + if (strcmp (str, string_table[i]->s) < 0) + { + break; + } + } + for (x = strtablen - 1; x >= i; x--) + { + string_table[x + 1] = string_table[x]; + string_table[x + 1]->num = x + 1; + } + string_table[i] = tmalloc (struct string_entry); + string_table[i]->s = xstrdup (str); + string_table[i]->num = i; + strtablen++; + return string_table[i]; +} + +struct bittree * +make_bittree_entry () +{ + struct bittree *res = tmalloc (struct bittree); + + res->disent = NULL; + res->bits[0] = NULL; + res->bits[1] = NULL; + res->bits[2] = NULL; + res->skip_flag = 0; + res->bits_to_skip = 0; + return res; +} + +struct disent * +add_dis_table_ent (which, insn, order, completer_index) + struct disent *which; + int insn; + int order; + int completer_index; +{ + int ci = 0; + struct disent *ent; + + if (which != NULL) + { + ent = which; + + ent->nextcnt++; + while (ent->nexte != NULL) + { + ent = ent->nexte; + } + ent = (ent->nexte = tmalloc (struct disent)); + } + else + { + ent = tmalloc (struct disent); + ent->next_ent = disinsntable; + disinsntable = ent; + which = ent; + } + ent->nextcnt = 0; + ent->nexte = NULL; + ent->insn = insn; + ent->priority = order; + + while (completer_index != 1) + { + ci = (ci << 1) | (completer_index & 1); + completer_index >>= 1; + } + ent->completer_index = ci; + return which; +} + +void +finish_distable () +{ + struct disent *ent = disinsntable; + struct disent *prev = ent; + + ent->ournum = 32768; + while ((ent = ent->next_ent) != NULL) + { + ent->ournum = prev->ournum + prev->nextcnt + 1; + prev = ent; + } +} + +void +insert_bit_table_ent (curr_ent, bit, opcode, mask, + opcodenum, order, completer_index) + struct bittree *curr_ent; + int bit; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + int order; + int completer_index; +{ + ia64_insn m; + int b; + struct bittree *next; + + if (bit == -1) + { + struct disent *nent = add_dis_table_ent (curr_ent->disent, + opcodenum, order, + completer_index); + curr_ent->disent = nent; + return; + } + + m = ((ia64_insn) 1) << bit; + + if (mask & m) + { + b = (opcode & m) ? 1 : 0; + } + else + { + b = 2; + } + next = curr_ent->bits[b]; + if (next == NULL) + { + next = make_bittree_entry (); + curr_ent->bits[b] = next; + } + insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, + completer_index); +} + +void +add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) + struct bittree *first; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + struct completer_entry *ent; + int completer_index; +{ + if (completer_index & (1 << 20)) + { + abort (); + } + + while (ent != NULL) + { + ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; + add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, + (completer_index << 1) | 1); + if (ent->is_terminal) + { + insert_bit_table_ent (bittree, 40, newopcode, mask, + opcodenum, opcode_count - ent->order - 1, + (completer_index << 1) | 1); + } + completer_index <<= 1; + ent = ent->alternative; + } +} + +/* This optimization pass combines multiple "don't care" nodes. */ +void +compact_distree (ent) + struct bittree *ent; +{ +#define IS_SKIP(ent) \ + ((ent->bits[2] !=NULL) \ + && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0)) + + int bitcnt = 0; + struct bittree *nent = ent; + int x; + + while (IS_SKIP (nent)) + { + bitcnt++; + nent = nent->bits[2]; + } + + if (bitcnt) + { + struct bittree *next = ent->bits[2]; + + ent->bits[0] = nent->bits[0]; + ent->bits[1] = nent->bits[1]; + ent->bits[2] = nent->bits[2]; + ent->disent = nent->disent; + ent->skip_flag = 1; + ent->bits_to_skip = bitcnt; + while (next != nent) + { + struct bittree *b = next; + next = next->bits[2]; + free (b); + } + free (nent); + } + + for (x = 0; x < 3; x++) + { + struct bittree *i = ent->bits[x]; + if (i != NULL) + { + compact_distree (i); + } + } +} + +static unsigned char *insn_list; +static int insn_list_len = 0; +static int tot_insn_list_len = 0; + +/* Generate the disassembler state machine corresponding to the tree + in ENT. */ +void +gen_dis_table (ent) + struct bittree *ent; +{ + int x; + int our_offset = insn_list_len; + int bitsused = 5; + int totbits = bitsused; + int needed_bytes; + int zero_count = 0; + int zero_dest = 0; /* initialize this with 0 to keep gcc quiet... */ + + /* If this is a terminal entry, there's no point in skipping any + bits. */ + if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && + ent->bits[2] == NULL) + { + if (ent->disent == NULL) + { + abort (); + } + else + { + ent->skip_flag = 0; + } + } + + /* Calculate the amount of space needed for this entry, or at least + a conservatively large approximation. */ + if (ent->skip_flag) + { + totbits += 5; + } + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL) + { + totbits += 16; + } + } + + if (ent->disent != NULL) + { + if (ent->bits[2] != NULL) + { + abort (); + } + totbits += 16; + } + + /* Now allocate the space. */ + needed_bytes = (totbits + 7) / 8; + if ((needed_bytes + insn_list_len) > tot_insn_list_len) + { + tot_insn_list_len += 256; + insn_list = (char *) xrealloc (insn_list, tot_insn_list_len); + } + our_offset = insn_list_len; + insn_list_len += needed_bytes; + memset (insn_list + our_offset, 0, needed_bytes); + + /* Encode the skip entry by setting bit 6 set in the state op field, + and store the # of bits to skip immediately after. */ + if (ent->skip_flag) + { + bitsused += 5; + insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf); + insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6); + } + +#define IS_ONLY_IFZERO(ENT) \ + ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \ + && (ENT)->disent == NULL && (ENT)->skip_flag == 0) + + /* Store an "if (bit is zero)" instruction by setting bit 7 in the + state op field. */ + + if (ent->bits[0] != NULL) + { + struct bittree *nent = ent->bits[0]; + zero_count = 0; + + insn_list[our_offset] |= 0x80; + + /* We can encode sequences of multiple "if (bit is zero)" tests + by storing the # of zero bits to check in the lower 3 bits of + the instruction. However, this only applies if the state + solely tests for a zero bit. */ + + if (IS_ONLY_IFZERO (ent)) + { + while (IS_ONLY_IFZERO (nent) && zero_count < 7) + { + nent = nent->bits[0]; + zero_count++; + } + + insn_list[our_offset + 0] |= zero_count; + } + zero_dest = insn_list_len; + gen_dis_table (nent); + } + + /* Now store the remaining tests. We also handle a sole "termination + entry" by storing it as an "any bit" test. */ + + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL)) + { + struct bittree *i = ent->bits[x]; + int idest; + int currbits = 15; + + if (i != NULL) + { + /* If the instruction being branched to only consists of + a termination entry, use the termination entry as the + place to branch to instead. */ + if (i->bits[0] == NULL && i->bits[1] == NULL + && i->bits[2] == NULL && i->disent != NULL) + { + idest = i->disent->ournum; + i = NULL; + } + else + { + idest = insn_list_len - our_offset; + } + } + else + { + idest = ent->disent->ournum; + } + + /* If the destination offset for the if (bit is 1) test is less + than 256 bytes away, we can store it as 8-bits instead of 16; + the instruction has bit 5 set for the 16-bit address, and bit + 4 for the 8-bit address. Since we've already allocated 16 + bits for the address we need to deallocate the space. + + Note that branchings within the table are relative, and + there are no branches that branch past our instruction yet + so we do not need to adjust any other offsets. */ + + if (x == 1) + { + if (idest <= 256) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 7; + totbits -= 8; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x10; + idest--; + } + else + { + insn_list[our_offset] |= 0x20; + } + } + else + { + /* An instruction which solely consists of a termination + marker and whose disassembly name index is < 4096 + can be stored in 16 bits. The encoding is slightly + odd; the upper 4 bits of the instruction are 0x3, and + bit 3 loses its normal meaning. */ + + if (ent->bits[0] == NULL && ent->bits[1] == NULL + && ent->bits[2] == NULL && ent->skip_flag == 0 + && ent->disent != NULL + && ent->disent->ournum < (32768 + 4096)) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 11; + totbits -= 5; + bitsused--; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x30; + idest &= ~32768; + } + else + { + insn_list[our_offset] |= 0x08; + } + } + if (debug) + { + int id = idest; + + if (i == NULL) + { + id |= 32768; + } + else if (! (id & 32768)) + { + id += our_offset; + } + if (x == 1) + { + printf ("%d: if (1) goto %d\n", our_offset, id); + } + else + { + printf ("%d: try %d\n", our_offset, id); + } + } + + /* Store the address of the entry being branched to. */ + while (currbits >= 0) + { + char *byte = insn_list + our_offset + bitsused / 8; + + if (idest & (1 << currbits)) + { + *byte |= (1 << (7 - (bitsused % 8))); + } + bitsused++; + currbits--; + } + + /* Now generate the states for the entry being branched to. */ + if (i != NULL) + { + gen_dis_table (i); + } + + } + } + if (debug) + { + if (ent->skip_flag) + { + printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); + } + + if (ent->bits[0] != NULL) + { + printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, + zero_dest); + } + } + if (bitsused != totbits) + { + abort (); + } +} + +void +print_dis_table () +{ + int x; + struct disent *cent = disinsntable; + + printf ("static const char dis_table[] = {\n"); + for (x = 0; x < insn_list_len; x++) + { + if ((x > 0) && ((x % 12) == 0)) + { + printf ("\n"); + } + printf ("0x%02x, ", insn_list[x]); + } + printf ("\n};\n\n"); + + printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n"); + while (cent != NULL) + { + struct disent *ent = cent; + + while (ent != NULL) + { + printf ("{ 0x%x, %d, %d, %d },\n", ent->completer_index, + ent->insn, (ent->nexte != NULL ? 1 : 0), + ent->priority); + ent = ent->nexte; + } + cent = cent->next_ent; + } + printf ("};\n\n"); +} + +void +generate_disassembler () +{ + int i; + + bittree = make_bittree_entry (); + + for (i=0; i < otlen;i++) + { + struct main_entry *ptr = ordered_table[i]; + + if (ptr->opcode->type != IA64_TYPE_DYN) + { + add_dis_entry (bittree, + ptr->opcode->opcode, ptr->opcode->mask, + ptr->main_index, + ptr->completers, 1); + } + } + + compact_distree (bittree); + finish_distable (); + gen_dis_table (bittree); + + print_dis_table (); +} + +void +print_string_table () +{ + int x; + char lbuf[80], buf[80]; + int blen = 0; + + printf ("static const char *ia64_strings[] = {\n"); + lbuf[0] = '\0'; + for (x = 0; x < strtablen; x++) + { + int len; + + if (strlen (string_table[x]->s) > 75) + { + abort (); + } + sprintf (buf, " \"%s\",", string_table[x]->s); + len = strlen (buf); + if ((blen + len) > 75) + { + printf (" %s\n", lbuf); + lbuf[0] = '\0'; + blen = 0; + } + strcat (lbuf, buf); + blen += len; + } + if (blen > 0) + { + printf (" %s\n", lbuf); + } + printf ("};\n\n"); +} + +static struct completer_entry **glist; +static int glistlen = 0; +static int glisttotlen = 0; + +/* If the completer trees ENT1 and ENT2 are equal, return 1. */ + +int +completer_entries_eq (ent1, ent2) + struct completer_entry *ent1, *ent2; +{ + while (ent1 != NULL && ent2 != NULL) + { + if (ent1->name->num != ent2->name->num + || ent1->bits != ent2->bits + || ent1->mask != ent2->mask + || ent1->is_terminal != ent2->is_terminal + || ent1->dependencies != ent2->dependencies + || ent1->order != ent2->order) + { + return 0; + } + if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) + { + return 0; + } + ent1 = ent1->alternative; + ent2 = ent2->alternative; + } + return ent1 == ent2; +} + +/* Insert ENT into the global list of completers and return it. If an + equivalent entry (according to completer_entries_eq) already exists, + it is returned instead. */ +struct completer_entry * +insert_gclist (ent) + struct completer_entry *ent; +{ + if (ent != NULL) + { + int i; + int x; + int start = 0, end; + + ent->addl_entries = insert_gclist (ent->addl_entries); + ent->alternative = insert_gclist (ent->alternative); + + i = glistlen / 2; + end = glistlen; + + if (glisttotlen == glistlen) + { + glisttotlen += 20; + glist = (struct completer_entry **) + xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); + } + + if (glistlen == 0) + { + glist[0] = ent; + glistlen = 1; + return ent; + } + + if (ent->name->num < glist[0]->name->num) + { + i = 0; + } + else if (ent->name->num > glist[end - 1]->name->num) + { + i = end; + } + else + { + int c; + + while (1) + { + i = (start + end) / 2; + c = ent->name->num - glist[i]->name->num; + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + while (i > 0 + && ent->name->num == glist[i - 1]->name->num) + { + i--; + } + break; + } + else + { + start = i + 1; + } + if (start > end) + { + break; + } + } + if (c == 0) + { + while (i < glistlen) + { + if (ent->name->num != glist[i]->name->num) + { + break; + } + if (completer_entries_eq (ent, glist[i])) + { + return glist[i]; + } + i++; + } + } + } + for (; i > 0 && i < glistlen; i--) + { + if (ent->name->num >= glist[i - 1]->name->num) + { + break; + } + } + for (; i < glistlen; i++) + { + if (ent->name->num < glist[i]->name->num) + { + break; + } + } + for (x = glistlen - 1; x >= i; x--) + { + glist[x + 1] = glist[x]; + } + glist[i] = ent; + glistlen++; + } + return ent; +} + +static int +get_prefix_len (name) + const char *name; +{ + char *c; + + if (name[0] == '\0') + { + return 0; + } + + c = strchr (name, '.'); + if (c != NULL) + { + return c - name; + } + else + { + return strlen (name); + } +} + +static void +compute_completer_bits (ment, ent) + struct main_entry *ment; + struct completer_entry *ent; +{ + while (ent != NULL) + { + compute_completer_bits (ment, ent->addl_entries); + + if (ent->is_terminal) + { + ia64_insn mask = 0; + ia64_insn our_bits = ent->bits; + struct completer_entry *p = ent->parent; + ia64_insn p_bits; + int x; + + while (p != NULL && ! p->is_terminal) + { + p = p->parent; + } + + if (p != NULL) + { + p_bits = p->bits; + } + else + { + p_bits = ment->opcode->opcode; + } + + for (x = 0; x < 64; x++) + { + ia64_insn m = ((ia64_insn) 1) << x; + if ((p_bits & m) != (our_bits & m)) + { + mask |= m; + } + else + { + our_bits &= ~m; + } + } + ent->bits = our_bits; + ent->mask = mask; + } + else + { + ent->bits = 0; + ent->mask = 0; + } + + ent = ent->alternative; + } +} + +/* Find identical completer trees that are used in different + instructions and collapse their entries. */ +void +collapse_redundant_completers () +{ + struct main_entry *ptr; + int x; + + for (ptr = maintable; ptr != NULL; ptr = ptr->next) + { + if (ptr->completers == NULL) + { + abort (); + } + compute_completer_bits (ptr, ptr->completers); + ptr->completers = insert_gclist (ptr->completers); + } + + /* The table has been finalized, now number the indexes. */ + for (x = 0; x < glistlen; x++) + { + glist[x]->num = x; + } +} + + +/* attach two lists of dependencies to each opcode. + 1) all resources which, when already marked in use, conflict with this + opcode (chks) + 2) all resources which must be marked in use when this opcode is used + (regs) +*/ +int +insert_opcode_dependencies (opc, cmp) + struct ia64_opcode *opc; + struct completer_entry *cmp ATTRIBUTE_UNUSED; +{ + /* note all resources which point to this opcode. rfi has the most chks + (79) and cmpxchng has the most regs (54) so 100 here should be enough */ + int i; + int nregs = 0; + unsigned short regs[256]; + int nchks = 0; + unsigned short chks[256]; + /* flag insns for which no class matched; there should be none */ + int no_class_found = 1; + + for (i=0;i < rdepslen;i++) + { + struct rdep *rs = rdeps[i]; + int j; + + if (strcmp (opc->name, "cmp.eq.and") == 0 + && strncmp (rs->name, "PR%", 3) == 0 + && rs->mode == 1) + no_class_found = 99; + + for (j=0; j < rs->nregs;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->regnotes[j] != 0 + && ic_note != rs->regnotes[j] + && !(ic_note == 11 && rs->regnotes[j] == 1)) + fprintf (stderr, "Warning: IC note %d in opcode %s (IC:%s)" + " conflicts with resource %s note %d\n", + ic_note, opc->name, ics[rs->regs[j]]->name, + rs->name, rs->regnotes[j]); + /* Instruction class notes override resource notes. + So far, only note 11 applies to an IC instead of a resource, + and note 11 implies note 1. + */ + if (ic_note) + regs[nregs++] = RDEP(ic_note, i); + else + regs[nregs++] = RDEP(rs->regnotes[j], i); + no_class_found = 0; + ++rs->total_regs; + } + } + for (j=0;j < rs->nchks;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->chknotes[j] != 0 + && ic_note != rs->chknotes[j] + && !(ic_note == 11 && rs->chknotes[j] == 1)) + fprintf (stderr, "Warning: IC note %d for opcode %s (IC:%s)" + " conflicts with resource %s note %d\n", + ic_note, opc->name, ics[rs->chks[j]]->name, + rs->name, rs->chknotes[j]); + if (ic_note) + chks[nchks++] = RDEP(ic_note, i); + else + chks[nchks++] = RDEP(rs->chknotes[j], i); + no_class_found = 0; + ++rs->total_chks; + } + } + } + + if (no_class_found) + fprintf (stderr, "Warning: opcode %s has no class (ops %d %d %d)\n", + opc->name, + opc->operands[0], opc->operands[1], opc->operands[2]); + + return insert_dependencies (nchks, chks, nregs, regs); +} + +void +insert_completer_entry (opc, tabent, order) + struct ia64_opcode *opc; + struct main_entry *tabent; + int order; +{ + struct completer_entry **ptr = &tabent->completers; + struct completer_entry *parent = NULL; + char pcopy[129], *prefix; + int at_end = 0; + + if (strlen (opc->name) > 128) + { + abort (); + } + strcpy (pcopy, opc->name); + prefix = pcopy + get_prefix_len (pcopy); + if (prefix[0] != '\0') + { + prefix++; + } + + while (! at_end) + { + int need_new_ent = 1; + int plen = get_prefix_len (prefix); + struct string_entry *sent; + + at_end = (prefix[plen] == '\0'); + prefix[plen] = '\0'; + sent = insert_string (prefix); + + while (*ptr != NULL) + { + int cmpres = sent->num - (*ptr)->name->num; + + if (cmpres == 0) + { + need_new_ent = 0; + break; + } + else + { + ptr = &((*ptr)->alternative); + } + } + if (need_new_ent) + { + struct completer_entry *nent = tmalloc (struct completer_entry); + nent->name = sent; + nent->parent = parent; + nent->addl_entries = NULL; + nent->alternative = *ptr; + *ptr = nent; + nent->is_terminal = 0; + nent->dependencies = -1; + } + + if (! at_end) + { + parent = *ptr; + ptr = &((*ptr)->addl_entries); + prefix += plen + 1; + } + } + + if ((*ptr)->is_terminal) + { + abort (); + } + + (*ptr)->is_terminal = 1; + (*ptr)->mask = (ia64_insn)-1; + (*ptr)->bits = opc->opcode; + (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); + (*ptr)->order = order; +} + +void +print_completer_entry (ent) + struct completer_entry *ent; +{ + int moffset = 0; + ia64_insn mask = ent->mask, bits = ent->bits; + + if (mask != 0) + { + while (! (mask & 1)) + { + moffset++; + mask = mask >> 1; + bits = bits >> 1; + } + if (bits & 0xffffffff00000000LL) + { + abort (); + } + } + + printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", + (int)bits, + (int)mask, + ent->name->num, + ent->alternative != NULL ? ent->alternative->num : -1, + ent->addl_entries != NULL ? ent->addl_entries->num : -1, + moffset, + ent->is_terminal ? 1 : 0, + ent->dependencies); +} + +void +print_completer_table () +{ + int x; + + printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); + for (x = 0; x < glistlen; x++) + { + print_completer_entry (glist[x]); + } + printf ("};\n\n"); +} + +int +opcodes_eq (opc1, opc2) + struct ia64_opcode *opc1; + struct ia64_opcode *opc2; +{ + int x; + int plen1, plen2; + + if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) + || (opc1->num_outputs != opc2->num_outputs) + || (opc1->flags != opc2->flags)) + { + return 0; + } + for (x = 0; x < 5; x++) + { + if (opc1->operands[x] != opc2->operands[x]) + { + return 0; + } + } + plen1 = get_prefix_len (opc1->name); + plen2 = get_prefix_len (opc2->name); + if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) + { + return 1; + } + return 0; +} + +void +add_opcode_entry (opc) + struct ia64_opcode *opc; +{ + struct main_entry **place; + struct string_entry *name; + char prefix[129]; + int found_it = 0; + + if (strlen (opc->name) > 128) + { + abort (); + } + place = &maintable; + strcpy (prefix, opc->name); + prefix[get_prefix_len (prefix)] = '\0'; + name = insert_string (prefix); + + /* Walk the list of opcode table entries. If it's a new + instruction, allocate and fill in a new entry. Note + the main table is alphabetical by opcode name. */ + + while (*place != NULL) + { + if ((*place)->name->num == name->num + && opcodes_eq ((*place)->opcode, opc)) + { + found_it = 1; + break; + } + if ((*place)->name->num > name->num) + { + break; + } + place = &((*place)->next); + } + if (! found_it) + { + struct main_entry *nent = tmalloc (struct main_entry); + + nent->name = name; + nent->opcode = opc; + nent->next = *place; + nent->completers = 0; + *place = nent; + + if (otlen == ottotlen) + { + ottotlen += 20; + ordered_table = (struct main_entry **) + xrealloc (ordered_table, sizeof (struct main_entry *) * ottotlen); + } + ordered_table[otlen++] = nent; + } + + insert_completer_entry (opc, *place, opcode_count++); +} + +void +print_main_table () +{ + struct main_entry *ptr = maintable; + int index = 0; + + printf ("static const struct ia64_main_table\nmain_table[] = {\n"); + while (ptr != NULL) + { + printf (" { %d, %d, %d, 0x", + ptr->name->num, + ptr->opcode->type, + ptr->opcode->num_outputs); + fprintf_vma (stdout, ptr->opcode->opcode); + printf ("ull, 0x"); + fprintf_vma (stdout, ptr->opcode->mask); + printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", + ptr->opcode->operands[0], + ptr->opcode->operands[1], + ptr->opcode->operands[2], + ptr->opcode->operands[3], + ptr->opcode->operands[4], + ptr->opcode->flags, + ptr->completers->num); + + ptr->main_index = index++; + + ptr = ptr->next; + } + printf ("};\n\n"); +} + +void +shrink (table) + struct ia64_opcode *table; +{ + int curr_opcode; + + for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) + { + add_opcode_entry (table + curr_opcode); + } +} + +int +main (argc, argv) + int argc; + char **argv ATTRIBUTE_UNUSED; +{ + if (argc > 1) + { + debug = 1; + } + + load_insn_classes(); + load_dependencies(); + + shrink (ia64_opcodes_a); + shrink (ia64_opcodes_b); + shrink (ia64_opcodes_f); + shrink (ia64_opcodes_i); + shrink (ia64_opcodes_m); + shrink (ia64_opcodes_x); + shrink (ia64_opcodes_d); + + collapse_redundant_completers (); + + printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); + print_string_table (); + print_dependency_table (); + print_completer_table (); + print_main_table (); + + generate_disassembler (); + + exit (0); +} diff --git a/opcodes/ia64-ic.tbl b/opcodes/ia64-ic.tbl new file mode 100644 index 0000000..115a276 --- /dev/null +++ b/opcodes/ia64-ic.tbl @@ -0,0 +1,234 @@ +Class; Events/Instructions +all; IC:predicatable-instructions, IC:unpredicatable-instructions +branches; IC:indirect-brs, IC:ip-rel-brs +cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e +chk-a; chk.a.clr, chk.a.nc +cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8 +czx; czx1, czx2 +fcmp-s0; fcmp[Field(sf)==s0] +fcmp-s1; fcmp[Field(sf)==s1] +fcmp-s2; fcmp[Field(sf)==s2] +fcmp-s3; fcmp[Field(sf)==s3] +fetchadd; fetchadd4, fetchadd8 +fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub +fp-arith-s0; IC:fp-arith[Field(sf)==s0] +fp-arith-s1; IC:fp-arith[Field(sf)==s1] +fp-arith-s2; IC:fp-arith[Field(sf)==s2] +fp-arith-s3; IC:fp-arith[Field(sf)==s3] +fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma +fpcmp-s0; fpcmp[Field(sf)==s0] +fpcmp-s1; fpcmp[Field(sf)==s1] +fpcmp-s2; fpcmp[Field(sf)==s2] +fpcmp-s3; fpcmp[Field(sf)==s3] +fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf +fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf +gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat +gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt +gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl +indirect-brp; brp[Format in {B7}] +indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret +invala-all; invala[Format in {M24}], invala.e +ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop +ld; ld1, ld2, ld4, ld8, ld8.fill +ld-a; ld1.a, ld2.a, ld4.a, ld8.a +ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}] +ld-c; IC:ld-c-nc, IC:ld-c-clr +ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq +ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq +ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc +ld-s; ld1.s, ld2.s, ld4.s, ld8.s +ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa +ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill +ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a +ldf-c; IC:ldf-c-nc, IC:ldf-c-clr +ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr +ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc +ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s +ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa +ldfp; ldfps, ldfpd, ldfp8 +ldfp-a; ldfps.a, ldfpd.a, ldfp8.a +ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr +ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr +ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc +ldfp-s; ldfps.s, ldfpd.s, ldfp8.s +ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa +lfetch-all; lfetch +lfetch-fault; lfetch[Field(lftype)==fault] +lfetch-nofault; lfetch[Field(lftype)==] +lfetch-postinc; lfetch[Format in {M14 M15}] +mem-readers; IC:mem-readers-fp, IC:mem-readers-int +mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c +mem-readers-fp; IC:ldf, IC:ldfp +mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld +mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa +mem-writers; IC:mem-writers-fp, IC:mem-writers-int +mem-writers-fp; IC:stf +mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st +mix; mix1, mix2, mix4 +mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop +mod-sched-brs-counted; br.cexit, br.cloop, br.ctop +mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM +mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP] +mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE] +mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV] +mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC] +mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR] +mov-from-AR-I; mov_ar[Format in {I28}] +mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] +mov-from-AR-IM; mov_ar[Format in {I28 M31}] +mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC] +mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC] +mov-from-AR-M; mov_ar[Format in {M31}] +mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] +mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] +mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] +mov-from-AR-rv; IC:none +mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] +mov-from-BR; mov_br[Format in {I22}] +mov-from-CR; mov_cr[Format in {M33}] +mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV] +mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR] +mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI] +mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA] +mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA] +mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS] +mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA] +mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM] +mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP] +mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA] +mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR] +mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR] +mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR] +mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM] +mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV] +mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA] +mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR] +mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID] +mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}] +mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV] +mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA] +mov-from-CR-rv; IC:none +mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR] +mov-from-IND; mov_indirect[Format in {M43}] +mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid] +mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr] +mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr] +mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr] +mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr] +mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc] +mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd] +mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}] +mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr] +mov-from-PR; mov_pr[Format in {I25}] +mov-from-PSR; mov_psr[Format in {M36}] +mov-from-PSR-um; mov_um[Format in {M36}] +mov-ip; mov_ip[Format in {I25}] +mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I +mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP] +mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE] +mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV] +mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC] +mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR] +mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}] +mov-to-AR-I; mov_ar[Format in {I26 I27}] +mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] +mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}] +mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC] +mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC] +mov-to-AR-M; mov_ar[Format in {M29 M30}] +mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] +mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] +mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] +mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] +mov-to-BR; mov_br[Format in {I21}] +mov-to-CR; mov_cr[Format in {M32}] +mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV] +mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR] +mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI] +mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA] +mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA] +mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS] +mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA] +mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM] +mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP] +mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA] +mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR] +mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR] +mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR] +mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM] +mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV] +mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA] +mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR] +mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID] +mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}] +mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV] +mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA] +mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR] +mov-to-IND; mov_indirect[Format in {M42}] +mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid] +mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr] +mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr] +mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr] +mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr] +mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc] +mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd] +mov-to-IND-priv; IC:mov-to-IND +mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr] +mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg +mov-to-PR-allreg; mov_pr[Format in {I23}] +mov-to-PR-rotreg; mov_pr[Format in {I24}] +mov-to-PSR-l; mov_psr[Format in {M35}] +mov-to-PSR-um; mov_um[Format in {M35}] +mux; mux1, mux2 +none; - +pack; pack2, pack4 +padd; padd1, padd2, padd4 +pavg; pavg1, pavg2 +pavgsub; pavgsub1, pavgsub2 +pcmp; pcmp1, pcmp2, pcmp4 +pmax; pmax1, pmax2 +pmin; pmin1, pmin2 +pmpy; pmpy2 +pmpyshr; pmpyshr2 +pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-gen-writers-fp; fclass, fcmp +pr-gen-writers-int; cmp, cmp4, tbit, tnat +pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==] +pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==] +pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, nop.b, IC:ReservedBQP +pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt +pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11 +pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11 +pr-writers; IC:pr-writers-int, IC:pr-writers-fp +pr-writers-fp; IC:pr-norm-writers-fp, IC:pr-unc-writers-fp +pr-writers-int; IC:pr-norm-writers-int, IC:pr-unc-writers-int, IC:pr-and-writers, IC:pr-or-writers +predicatable-instructions; IC:mov-from-PR, IC:mov-to-PR, IC:pr-readers-br, IC:pr-readers-nobr-nomovpr +priv-ops; IC:mov-to-IND-priv, bsw, itc.i, itc.d, itr.i, itr.d, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-PSR-l, IC:mov-from-PSR, IC:mov-from-IND-priv, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, rfi, rsm, ssm, tak, tpa +probe-all; IC:probe-fault, IC:probe-nofault +probe-fault; probe[Format in {M40}] +probe-nofault; probe[Format in {M38 M39}] +psad; psad1 +pshl; pshl2, pshl4 +pshladd; pshladd2 +pshr; pshr2, pshr4 +pshradd; pshradd2 +psub; psub1, psub2, psub4 +ReservedBQP; -+15 +ReservedQP; -+16 +rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi +rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi +st; st1, st2, st4, st8, st8.spill +st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}] +stf; stfs, stfd, stfe, stf8, stf.spill +sxt; sxt1, sxt2, sxt4 +sys-mask-writers-partial; rsm, ssm +unpack; unpack1, unpack2, unpack4 +unpredicatable-instructions; alloc, br.cloop, br.ctop, br.cexit, br.ia, brp, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi +user-mask-writers-partial; rum, sum +xchg; xchg1, xchg2, xchg4, xchg8 +zxt; zxt1, zxt2, zxt4 diff --git a/opcodes/ia64-opc-a.c b/opcodes/ia64-opc-a.c new file mode 100644 index 0000000..27d7637 --- /dev/null +++ b/opcodes/ia64-opc-a.c @@ -0,0 +1,412 @@ +/* ia64-opc-a.c -- IA-64 `A' opcode table. + Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define A IA64_TYPE_A, 1 +#define A2 IA64_TYPE_A, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ + (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ + (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) +#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) +#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mImm14 bImm14 (-1) +#define mR3a bR3a (-1) +#define mR3b bR3b (-1) +#define mTa bTa (-1) +#define mTb bTb (-1) +#define mVe bVe (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX4 bX4 (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) +#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ + (mOp | mX2a | mVe) +#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ + (mOp | mX2a | mVe | mR3a) +#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \ + (mOp | mX2a | mVe | mImm14) +#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ + (mOp | mX2a | mVe | mX4) +#define OpX2aVeX4X2b(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ + (mOp | mX2a | mVe | mX4 | mX2b) +#define OpX2TbTaC(a,b,c,d,e) \ + (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ + (mOp | mX2 | mTb | mTa | mC) +#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ + (mOp | mX2 | mTa | mC) +#define OpX2aZaZbX4(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ + (mOp | mX2a | mZa | mZb | mX4) +#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ + (mOp | mX2a | mZa | mZb | mX4 | mX2b) + +struct ia64_opcode ia64_opcodes_a[] = + { + /* A-type instruction encodings (sorted according to major opcode) */ + + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}}, + {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}}, + {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}}, + {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}}, + {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}}, + {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO}, + {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}}, + {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}}, + {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}}, + {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}}, + {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}}, + {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}}, + {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}}, + {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}}, + {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}}, + {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}}, + {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}}, + {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}}, + {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}}, + {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}}, + {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}}, + {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}}, + {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}}, + {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}}, + {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}}, + {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}}, + {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}}, + {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}}, + {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}}, + {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}}, + {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}}, + {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}}, + {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}}, + {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}}, + {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}}, + {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}}, + {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}}, + {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}}, + {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}}, + + {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO}, + {"addl", A, Op (9), {R1, IMM22, R3_2}}, + + {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}}, + {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}}, + {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}}, + {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}}, + {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}}, + {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}}, + {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}}, + {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}}, + {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}}, + {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}}, + {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}}, + {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}}, + {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}}, + {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}}, + {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}}, + {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}}, + {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}}, + {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}}, + {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}}, + {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}}, + {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, + {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, + {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, + {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO}, + {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + + {0} + }; + +#undef A +#undef A2 +#undef bC +#undef bImm14 +#undef bR3a +#undef bR3b +#undef bTa +#undef bTb +#undef bVe +#undef bX +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX4 +#undef bZa +#undef bZb +#undef mC +#undef mImm14 +#undef mR3a +#undef mR3b +#undef mTa +#undef mTb +#undef mVe +#undef mX +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX4 +#undef mZa +#undef mZb +#undef OpR3a +#undef OpR3b +#undef OpX2aVe +#undef OpX2aVeImm14 +#undef OpX2aVeX4 +#undef OpX2aVeX4X2b +#undef OpX2TbTaC +#undef OpX2TaC +#undef OpX2aZaZbX4 +#undef OpX2aZaZbX4X2b diff --git a/opcodes/ia64-opc-b.c b/opcodes/ia64-opc-b.c new file mode 100644 index 0000000..9772b37 --- /dev/null +++ b/opcodes/ia64-opc-b.c @@ -0,0 +1,489 @@ +/* ia64-opc-b.c -- IA-64 `B' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define B0 IA64_TYPE_B, 0 +#define B IA64_TYPE_B, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mIh bIh (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mWha bWha (-1) +#define mWhb bWhb (-1) +#define mX6 bX6 (-1) + +#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) +#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD) +#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) +#define OpIhWhb(a,b,c) \ + (bOp (a) | bIh (b) | bWhb (c)), \ + (mOp | mIh | mWhb) +#define OpX6IhWhb(a,b,c,d) \ + (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ + (mOp | mX6 | mIh | mWhb) + +struct ia64_opcode ia64_opcodes_b[] = + { + /* B-type instruction encodings (sorted according to major opcode) */ + +#define BR(a,b) \ + B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2} + {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO}, + {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, + {"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO}, + {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO}, + {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, + {"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO}, + {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO}, + {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, + {"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO}, + {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO}, + {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, + {"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO}, + {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, + {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, + {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, + {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, + {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, + {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, + {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, + {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, + {"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS}, + {"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS}, + {"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS}, + {"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS}, + {"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS}, + {"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS}, + {"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS}, + {"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS}, + {"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS}, + {"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS}, + {"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS}, + {"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS}, + {"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS}, + {"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS}, + {"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS}, + {"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS}, + {"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS}, + {"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS}, + {"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS}, + {"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS}, + {"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS}, + {"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS}, + {"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS}, + {"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS}, +#undef BR + + {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS}, + {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV}, + {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV}, + {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED}, + + {"break.b", B0, OpX6 (0, 0x00), {IMMU21}}, + + {"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}}, + {"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}}, + {"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}}, + {"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}}, + {"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}}, + {"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}}, + {"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}}, + {"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}}, + {"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}}, + {"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}}, + {"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}}, + {"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}}, + {"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}}, + {"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}}, + {"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}}, + +#define BRP(a,b,c) \ + B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED + {"brp.sptk", BRP (0x10, 0, 0)}, + {"brp.dptk", BRP (0x10, 0, 2)}, + {"brp.sptk.imp", BRP (0x10, 1, 0)}, + {"brp.dptk.imp", BRP (0x10, 1, 2)}, + {"brp.ret.sptk", BRP (0x11, 0, 0)}, + {"brp.ret.dptk", BRP (0x11, 0, 2)}, + {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, + {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, +#undef BRP + + {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}}, + +#define BR(a,b) \ + B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c} + {"br.cond.sptk.few", BR (0, 0, 0)}, + {"br.cond.sptk", BR (0, 0, 0), PSEUDO}, + {"br.cond.sptk.few.clr", BR (0, 0, 1)}, + {"br.cond.sptk.clr", BR (0, 0, 1), PSEUDO}, + {"br.cond.spnt.few", BR (0, 1, 0)}, + {"br.cond.spnt", BR (0, 1, 0), PSEUDO}, + {"br.cond.spnt.few.clr", BR (0, 1, 1)}, + {"br.cond.spnt.clr", BR (0, 1, 1), PSEUDO}, + {"br.cond.dptk.few", BR (0, 2, 0)}, + {"br.cond.dptk", BR (0, 2, 0), PSEUDO}, + {"br.cond.dptk.few.clr", BR (0, 2, 1)}, + {"br.cond.dptk.clr", BR (0, 2, 1), PSEUDO}, + {"br.cond.dpnt.few", BR (0, 3, 0)}, + {"br.cond.dpnt", BR (0, 3, 0), PSEUDO}, + {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, + {"br.cond.dpnt.clr", BR (0, 3, 1), PSEUDO}, + {"br.cond.sptk.many", BR (1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (1, 0, 1)}, + {"br.cond.spnt.many", BR (1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (1, 1, 1)}, + {"br.cond.dptk.many", BR (1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (1, 2, 1)}, + {"br.cond.dpnt.many", BR (1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, + {"br.sptk.few", BR (0, 0, 0)}, + {"br.sptk", BR (0, 0, 0), PSEUDO}, + {"br.sptk.few.clr", BR (0, 0, 1)}, + {"br.sptk.clr", BR (0, 0, 1), PSEUDO}, + {"br.spnt.few", BR (0, 1, 0)}, + {"br.spnt", BR (0, 1, 0), PSEUDO}, + {"br.spnt.few.clr", BR (0, 1, 1)}, + {"br.spnt.clr", BR (0, 1, 1), PSEUDO}, + {"br.dptk.few", BR (0, 2, 0)}, + {"br.dptk", BR (0, 2, 0), PSEUDO}, + {"br.dptk.few.clr", BR (0, 2, 1)}, + {"br.dptk.clr", BR (0, 2, 1), PSEUDO}, + {"br.dpnt.few", BR (0, 3, 0)}, + {"br.dpnt", BR (0, 3, 0), PSEUDO}, + {"br.dpnt.few.clr", BR (0, 3, 1)}, + {"br.dpnt.clr", BR (0, 3, 1), PSEUDO}, + {"br.sptk.many", BR (1, 0, 0)}, + {"br.sptk.many.clr", BR (1, 0, 1)}, + {"br.spnt.many", BR (1, 1, 0)}, + {"br.spnt.many.clr", BR (1, 1, 1)}, + {"br.dptk.many", BR (1, 2, 0)}, + {"br.dptk.many.clr", BR (1, 2, 1)}, + {"br.dpnt.many", BR (1, 3, 0)}, + {"br.dpnt.many.clr", BR (1, 3, 1)}, +#undef BR + +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 + {"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS}, + {"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS}, + {"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS}, + {"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS}, + {"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS}, + {"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS}, + {"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS}, + {"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS}, + {"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS}, + {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS}, + {"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS}, + {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS}, + {"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS}, + {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS}, + {"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS}, + {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS}, + {"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS}, + {"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS}, + {"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS}, + {"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS}, + {"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS}, + {"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS}, + {"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS}, + {"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS}, + {"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS}, + {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS}, + {"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS}, + {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS}, + {"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS}, + {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS}, + {"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS}, + {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED + {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, + {"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO}, + {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, + {"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO}, + {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, + {"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO}, + {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, + {"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO}, + {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, + {"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO}, + {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, + {"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO}, + {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, + {"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO}, + {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, + {"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO}, + {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, + {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, + {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, + {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, + {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, + {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, + {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, + {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, + {"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS}, + {"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS}, + {"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS}, + {"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS}, + {"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS}, + {"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS}, + {"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS}, + {"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS}, + {"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS}, + {"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS}, + {"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS}, + {"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS}, + {"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS}, + {"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS}, + {"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS}, + {"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS}, + {"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS}, + {"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS}, + {"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS}, + {"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS}, + {"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS}, + {"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS}, + {"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS}, + {"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS}, + {"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS}, + {"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS}, + {"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS}, + {"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS}, + {"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS}, + {"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS}, + {"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS}, + {"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 + {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}}, + {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}}, + {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}}, + {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}}, + {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}}, + {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}}, + {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}}, + {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}}, + {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}}, + {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}}, + {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}}, + {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}}, + {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}}, + {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}}, + {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}}, +#undef BR + + /* branch predict */ +#define BRP(a,b) \ + B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED + {"brp.sptk", BRP (0, 0)}, + {"brp.loop", BRP (0, 1)}, + {"brp.dptk", BRP (0, 2)}, + {"brp.exit", BRP (0, 3)}, + {"brp.sptk.imp", BRP (1, 0)}, + {"brp.loop.imp", BRP (1, 1)}, + {"brp.dptk.imp", BRP (1, 2)}, + {"brp.exit.imp", BRP (1, 3)}, +#undef BRP + + {0} + }; + +#undef B0 +#undef B +#undef bBtype +#undef bD +#undef bIh +#undef bPa +#undef bPr +#undef bWha +#undef bWhb +#undef bX6 +#undef mBtype +#undef mD +#undef mIh +#undef mPa +#undef mPr +#undef mWha +#undef mWhb +#undef mX6 +#undef OpX6 +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr +#undef OpX6BtypePaWhaD +#undef OpX6BtypePaWhaDPr +#undef OpIhWhb +#undef OpX6IhWhb diff --git a/opcodes/ia64-opc-d.c b/opcodes/ia64-opc-d.c new file mode 100644 index 0000000..27390f5 --- /dev/null +++ b/opcodes/ia64-opc-d.c @@ -0,0 +1,14 @@ +struct ia64_opcode ia64_opcodes_d[] = + { + {"add", IA64_TYPE_DYN, 1, 0, 0, + {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}}, + {"add", IA64_TYPE_DYN, 1, 0, 0, + {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}}, + {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, + {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}}, + {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, + {0} + }; diff --git a/opcodes/ia64-opc-f.c b/opcodes/ia64-opc-f.c new file mode 100644 index 0000000..2f898c6 --- /dev/null +++ b/opcodes/ia64-opc-f.c @@ -0,0 +1,646 @@ +/* ia64-opc-f.c -- IA-64 `F' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define f0 IA64_TYPE_F, 0 +#define f IA64_TYPE_F, 1 +#define f2 IA64_TYPE_F, 2 + +#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) +#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) +#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mF2 bF2 (-1) +#define mF4 bF4 (-1) +#define mQ bQ (-1) +#define mRa bRa (-1) +#define mRb bRb (-1) +#define mSf bSf (-1) +#define mTa bTa (-1) +#define mXa bXa (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX6 bX6 (-1) + +#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) +#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) +#define OpXaSfF2(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) +#define OpXaSfF4(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) +#define OpXaSfF2F4(a,b,c,d,e) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ + (mOp | mXa | mSf | mF2 | mF4) +#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) +#define OpXaX2F2(a,b,c,d) \ + (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) +#define OpRaRbTaSf(a,b,c,d,e) \ + (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ + (mOp | mRa | mRb | mTa | mSf) +#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) +#define OpXbQSf(a,b,c,d) \ + (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) +#define OpXbX6(a,b,c) \ + (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6F2(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) +#define OpXbX6Sf(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) + +struct ia64_opcode ia64_opcodes_f[] = + { + /* F-type instruction encodings (sorted according to major opcode) */ + + {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}}, + {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, + {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}}, + {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}}, + {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}}, + + {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}}, + {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO}, + {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}}, + {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}}, + {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}}, + + {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}}, + {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, + {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}}, + {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}}, + {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}}, + {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}}, + {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, + {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}}, + {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}}, + {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}}, + {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}}, + {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, + {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}}, + {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}}, + {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}}, + {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}}, + {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, + {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}}, + {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}}, + {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}}, + + {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO}, + {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO}, + {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}}, + {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}}, + + {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}}, + {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}}, + {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}}, + {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}}, + {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}}, + {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}}, + {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}}, + {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}}, + {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}}, + {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}}, + {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}}, + {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}}, + {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}}, + {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}}, + + {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}}, + {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO}, + {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}}, + {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}}, + {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}}, + {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}}, + {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO}, + {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}}, + {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}}, + {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}}, + {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}}, + {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO}, + {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}}, + {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}}, + {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}}, + {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}}, + {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO}, + {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}}, + {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}}, + {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}}, + + {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}}, + + {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}}, + {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO}, + {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}}, + {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}}, + {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}}, + {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0)}, + {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO}, + {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1)}, + {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2)}, + {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3)}, + {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}}, + {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO}, + {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}}, + {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}}, + {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}}, + + {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}}, + {"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}}, + + {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}}, + {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, + {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}}, + {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}}, + {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}}, + + {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}}, + {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO}, + {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}}, + {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}}, + {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}}, + + {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}}, + {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, + {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}}, + {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}}, + {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}}, + {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}}, + {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, + {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}}, + {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}}, + {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}}, + {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}}, + {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, + {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}}, + {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}}, + {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}}, + {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}}, + {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, + {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}}, + {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}}, + {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}}, + + {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}}, + {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}}, + {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}}, + {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}}, + {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}}, + {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}}, + {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}}, + {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}}, + {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}}, + {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}}, + {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}}, + {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}}, + {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}}, + {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}}, + {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}}, + {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}}, + {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}}, + {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}}, + {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}}, + {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}}, + {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}}, + {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}}, + {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}}, + {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}}, + {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}}, + {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}}, + {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}}, + {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}}, + {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO}, + {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO}, + {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}}, + {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}}, + {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}}, + {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}}, + + {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO}, + {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO}, + {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}}, + {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}}, + {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}}, + + {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}}, + {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}}, + {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}}, + {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}}, + {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}}, + {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}}, + {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}}, + {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}}, + {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}}, + {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}}, + {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}}, + {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}}, + {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}}, + {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}}, + {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}}, + {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}}, + + {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}}, + + /* pseudo-ops of the above */ + {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}}, + {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}}, + {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}}, + {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}}, + {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}}, + {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}}, + {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}}, + {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}}, + {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}}, + {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}}, + {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}}, + {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}}, + {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}}, + {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}}, + {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}}, + {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}}, + {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}}, + {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}}, + {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}}, + {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}}, + {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}}, + {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}}, + {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}}, + {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}}, + + {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}}, + {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO}, + {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}}, + {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO}, + + /* note: fnorm and fcvt.xuf have identical encodings! */ + {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}}, + {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}}, + {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}}, + {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}}, + {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}}, + {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}}, + {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}}, + {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}}, + + {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}}, + {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}}, + {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}}, + {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}}, + + {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}}, + {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}}, + {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}}, + {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}}, + + {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}}, + {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}}, + {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}}, + {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}}, + {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}}, + {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}}, + {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}}, + {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}}, + {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}}, + {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}}, + {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}}, + {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}}, + + {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}}, + {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}}, + {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}}, + {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}}, + + {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}}, + {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}}, + {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}}, + {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}}, + {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}}, + {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}}, + {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}}, + {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}}, + {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}}, + {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}}, + {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}}, + {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}}, + + {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}}, + {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}}, + {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}}, + {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}}, + + {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}}, + {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}}, + {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}}, + + {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}}, + + {0} + }; + +#undef f0 +#undef f +#undef f2 +#undef bF2 +#undef bF4 +#undef bQ +#undef bRa +#undef bRb +#undef bSf +#undef bTa +#undef bXa +#undef bXb +#undef bX2 +#undef bX6 +#undef mF2 +#undef mF4 +#undef mQ +#undef mRa +#undef mRb +#undef mSf +#undef mTa +#undef mXa +#undef mXb +#undef mX2 +#undef mX6 +#undef OpXa +#undef OpXaSf +#undef OpXaSfF2 +#undef OpXaSfF4 +#undef OpXaSfF2F4 +#undef OpXaX2 +#undef OpRaRbTaSf +#undef OpTa +#undef OpXbQSf +#undef OpXbX6 +#undef OpXbX6F2 +#undef OpXbX6Sf diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c new file mode 100644 index 0000000..899e651 --- /dev/null +++ b/opcodes/ia64-opc-i.c @@ -0,0 +1,296 @@ +/* ia64-opc-i.c -- IA-64 `I' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define I0 IA64_TYPE_I, 0 +#define I IA64_TYPE_I, 1 +#define I2 IA64_TYPE_I, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) +#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) +#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) +#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mIh bIh (-1) +#define mTa bTa (-1) +#define mTag13 bTag13 (-1) +#define mTb bTb (-1) +#define mVc bVc (-1) +#define mVe bVe (-1) +#define mWh bWh (-1) +#define mX bX (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX2c bX2c (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mYa bYa (-1) +#define mYb bYb (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b) +#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) +#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) +#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ + (mOp | mX2 | mX | mYa) +#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ + (mOp | mX2 | mX | mYb) +#define OpX2TaTbYaC(a,b,c,d,e,f) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ + (mOp | mX2 | mTa | mTb | mYa | mC) +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3XbIhWh(a,b,c,d,e) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ + (mOp | mX3 | mXb | mIh | mWh) +#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ + (mOp | mX3 | mXb | mIh | mWh | mTag13) + +struct ia64_opcode ia64_opcodes_i[] = + { + /* I-type instruction encodings (sorted according to major opcode) */ + + {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX}, + {"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX}, + {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}}, + + {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO}, +#define MOV(a,b,c,d) \ + I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b} + {"mov.sptk", MOV (7, 0, 0, 0)}, + {"mov.sptk.imp", MOV (7, 0, 1, 0)}, + {"mov", MOV (7, 0, 0, 1)}, + {"mov.imp", MOV (7, 0, 1, 1)}, + {"mov.dptk", MOV (7, 0, 0, 2)}, + {"mov.dptk.imp", MOV (7, 0, 1, 2)}, + {"mov.ret.sptk", MOV (7, 1, 0, 0)}, + {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, + {"mov.ret", MOV (7, 1, 0, 1)}, + {"mov.ret.imp", MOV (7, 1, 1, 1)}, + {"mov.ret.dptk", MOV (7, 1, 0, 2)}, + {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, +#undef MOV + {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}}, + {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}}, + {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}}, + {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}}, + {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}}, + {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}}, + {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}}, + {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}}, + {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}}, + {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}}, + {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}}, + {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}}, + {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}}, + {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}}, + {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}}, + {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}}, + {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}}, + {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}}, + + {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}}, + + {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}}, + + {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT}, + {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}}, + + {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT}, + {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}}, + + {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, + PSEUDO | LEN_EQ_64MCNT}, + {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}}, + {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}}, + {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}}, +#define TBIT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6} +#define TBITCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO + {"tbit.z", TBIT (0, 0, 0, 0)}, + {"tbit.nz", TBITCM (0, 0, 0, 0)}, + {"tbit.z.unc", TBIT (0, 0, 0, 1)}, + {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, + {"tbit.z.and", TBIT (0, 1, 0, 0)}, + {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, + {"tbit.nz.and", TBIT (0, 1, 0, 1)}, + {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, + {"tbit.z.or", TBIT (1, 0, 0, 0)}, + {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, + {"tbit.nz.or", TBIT (1, 0, 0, 1)}, + {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, + {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, + {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, + {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, + {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, +#undef TBIT +#define TNAT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3} +#define TNATCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO + {"tnat.z", TNAT (0, 0, 1, 0)}, + {"tnat.nz", TNATCM (0, 0, 1, 0)}, + {"tnat.z.unc", TNAT (0, 0, 1, 1)}, + {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, + {"tnat.z.and", TNAT (0, 1, 1, 0)}, + {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, + {"tnat.nz.and", TNAT (0, 1, 1, 1)}, + {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, + {"tnat.z.or", TNAT (1, 0, 1, 0)}, + {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, + {"tnat.nz.or", TNAT (1, 0, 1, 1)}, + {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, + {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, + {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, + {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, + {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, +#undef TNAT + + {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}}, + {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}}, + {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}}, + {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}}, + {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}}, + {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}}, + {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}}, + {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}}, + {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}}, + {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}}, + {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}}, + {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}}, + {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}}, + {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}}, + {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}}, + {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}}, + {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}}, + {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}}, + {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}}, + {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}}, + {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}}, + {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}}, + {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}}, + {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}}, + + {0} + }; + +#undef I0 +#undef I +#undef I2 +#undef L +#undef bC +#undef bIh +#undef bTa +#undef bTag13 +#undef bTb +#undef bVc +#undef bVe +#undef bWh +#undef bX +#undef bXb +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX2c +#undef bX3 +#undef bX6 +#undef bY +#undef bZa +#undef bZb +#undef mC +#undef mIh +#undef mTa +#undef mTag13 +#undef mTb +#undef mVc +#undef mVe +#undef mWh +#undef mX +#undef mXb +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX2c +#undef mX3 +#undef mX6 +#undef mY +#undef mZa +#undef mZb +#undef OpZaZbVeX2aX2b +#undef OpZaZbVeX2aX2bX2c +#undef OpX2X +#undef OpX2XYa +#undef OpX2XYb +#undef OpX2TaTbYaC +#undef OpX3 +#undef OpX3X6 +#undef OpX3XbIhWh +#undef OpX3XbIhWhTag13 diff --git a/opcodes/ia64-opc-m.c b/opcodes/ia64-opc-m.c new file mode 100644 index 0000000..bc09816 --- /dev/null +++ b/opcodes/ia64-opc-m.c @@ -0,0 +1,1060 @@ +/* ia64-opc-m.c -- IA-64 `M' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define M0 IA64_TYPE_M, 0 +#define M IA64_TYPE_M, 1 +#define M2 IA64_TYPE_M, 2 + +/* instruction bit fields: */ +#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) +#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) +#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) + +#define mM bM (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX3 bX3 (-1) +#define mX4 bX4 (-1) +#define mX6a bX6a (-1) +#define mX6b bX6b (-1) +#define mHint bHint (-1) + +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ + (mOp | mX3 | mX6b) +#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ + (mOp | mX3 | mX4) +#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ + (mOp | mX3 | mX4 | mX2) +#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ + (mOp | mX6a | mHint) +#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ + (mOp | mX | mX6a | mHint) +#define OpMXX6a(a,b,c,d) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) +#define OpMXX6aHint(a,b,c,d,e) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ + (mOp | mM | mX | mX6a | mHint) + +struct ia64_opcode ia64_opcodes_m[] = + { + /* M-type instruction encodings (sorted according to major opcode) */ + + {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}}, + {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}}, + {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}}, + {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}}, + + {"invala", M0, OpX3X4X2 (0, 0, 0, 1)}, + {"fwb", M0, OpX3X4X2 (0, 0, 0, 2)}, + {"mf", M0, OpX3X4X2 (0, 0, 2, 2)}, + {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2)}, + {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3)}, + {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3)}, + {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3)}, + {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {0, }, FIRST | NO_PRED}, + {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {0, }, FIRST | NO_PRED}, + {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}}, + {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}}, + {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}}, + + {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}}, + {"nop.m", M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}}, + + {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}}, + {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}}, + {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV}, + {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV}, + + {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}}, + {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}}, + {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV}, + + {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS}, + + {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}}, + {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}}, + {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}}, + {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}}, + {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}}, + {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}}, + {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}}, + {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}}, + {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}}, + {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV}, + {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV}, + + {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV}, + {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV}, + {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV}, + + {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}}, + {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}}, + + {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV}, + {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV}, + {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV}, + {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV}, + {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV}, + + {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}}, + {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}}, + {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV}, + {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV}, + + {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}}, + {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}}, + + {"fc", M0, OpX3X6b (1, 0, 0x30), {R3}}, + {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV}, + + /* integer load */ + {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}}, + {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}}, + {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}}, + {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}}, + {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}}, + {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}}, + {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}}, + {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}}, + {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}}, + {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}}, + {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}}, + {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}}, + {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}}, + {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}}, + {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}}, + {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}}, + {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}}, + {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}}, + {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}}, + {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}}, + {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}}, + {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}}, + {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}}, + {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}}, + {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}}, + {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}}, + {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}}, + {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}}, + {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}}, + {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}}, + {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}}, + {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}}, + {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}}, + {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}}, + {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}}, + {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}}, + {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}}, + {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}}, + {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}}, + {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}}, + {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}}, + {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}}, + {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}}, + {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}}, + {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}}, + {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}}, + {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}}, + {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}}, + {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}}, + + /* integer load w/increment by register */ +#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, + {"ld1", LDINCREG (0x00, 0)}, + {"ld1.nt1", LDINCREG (0x00, 1)}, + {"ld1.nta", LDINCREG (0x00, 3)}, + {"ld2", LDINCREG (0x01, 0)}, + {"ld2.nt1", LDINCREG (0x01, 1)}, + {"ld2.nta", LDINCREG (0x01, 3)}, + {"ld4", LDINCREG (0x02, 0)}, + {"ld4.nt1", LDINCREG (0x02, 1)}, + {"ld4.nta", LDINCREG (0x02, 3)}, + {"ld8", LDINCREG (0x03, 0)}, + {"ld8.nt1", LDINCREG (0x03, 1)}, + {"ld8.nta", LDINCREG (0x03, 3)}, + {"ld1.s", LDINCREG (0x04, 0)}, + {"ld1.s.nt1", LDINCREG (0x04, 1)}, + {"ld1.s.nta", LDINCREG (0x04, 3)}, + {"ld2.s", LDINCREG (0x05, 0)}, + {"ld2.s.nt1", LDINCREG (0x05, 1)}, + {"ld2.s.nta", LDINCREG (0x05, 3)}, + {"ld4.s", LDINCREG (0x06, 0)}, + {"ld4.s.nt1", LDINCREG (0x06, 1)}, + {"ld4.s.nta", LDINCREG (0x06, 3)}, + {"ld8.s", LDINCREG (0x07, 0)}, + {"ld8.s.nt1", LDINCREG (0x07, 1)}, + {"ld8.s.nta", LDINCREG (0x07, 3)}, + {"ld1.a", LDINCREG (0x08, 0)}, + {"ld1.a.nt1", LDINCREG (0x08, 1)}, + {"ld1.a.nta", LDINCREG (0x08, 3)}, + {"ld2.a", LDINCREG (0x09, 0)}, + {"ld2.a.nt1", LDINCREG (0x09, 1)}, + {"ld2.a.nta", LDINCREG (0x09, 3)}, + {"ld4.a", LDINCREG (0x0a, 0)}, + {"ld4.a.nt1", LDINCREG (0x0a, 1)}, + {"ld4.a.nta", LDINCREG (0x0a, 3)}, + {"ld8.a", LDINCREG (0x0b, 0)}, + {"ld8.a.nt1", LDINCREG (0x0b, 1)}, + {"ld8.a.nta", LDINCREG (0x0b, 3)}, + {"ld1.sa", LDINCREG (0x0c, 0)}, + {"ld1.sa.nt1", LDINCREG (0x0c, 1)}, + {"ld1.sa.nta", LDINCREG (0x0c, 3)}, + {"ld2.sa", LDINCREG (0x0d, 0)}, + {"ld2.sa.nt1", LDINCREG (0x0d, 1)}, + {"ld2.sa.nta", LDINCREG (0x0d, 3)}, + {"ld4.sa", LDINCREG (0x0e, 0)}, + {"ld4.sa.nt1", LDINCREG (0x0e, 1)}, + {"ld4.sa.nta", LDINCREG (0x0e, 3)}, + {"ld8.sa", LDINCREG (0x0f, 0)}, + {"ld8.sa.nt1", LDINCREG (0x0f, 1)}, + {"ld8.sa.nta", LDINCREG (0x0f, 3)}, + {"ld1.bias", LDINCREG (0x10, 0)}, + {"ld1.bias.nt1", LDINCREG (0x10, 1)}, + {"ld1.bias.nta", LDINCREG (0x10, 3)}, + {"ld2.bias", LDINCREG (0x11, 0)}, + {"ld2.bias.nt1", LDINCREG (0x11, 1)}, + {"ld2.bias.nta", LDINCREG (0x11, 3)}, + {"ld4.bias", LDINCREG (0x12, 0)}, + {"ld4.bias.nt1", LDINCREG (0x12, 1)}, + {"ld4.bias.nta", LDINCREG (0x12, 3)}, + {"ld8.bias", LDINCREG (0x13, 0)}, + {"ld8.bias.nt1", LDINCREG (0x13, 1)}, + {"ld8.bias.nta", LDINCREG (0x13, 3)}, + {"ld1.acq", LDINCREG (0x14, 0)}, + {"ld1.acq.nt1", LDINCREG (0x14, 1)}, + {"ld1.acq.nta", LDINCREG (0x14, 3)}, + {"ld2.acq", LDINCREG (0x15, 0)}, + {"ld2.acq.nt1", LDINCREG (0x15, 1)}, + {"ld2.acq.nta", LDINCREG (0x15, 3)}, + {"ld4.acq", LDINCREG (0x16, 0)}, + {"ld4.acq.nt1", LDINCREG (0x16, 1)}, + {"ld4.acq.nta", LDINCREG (0x16, 3)}, + {"ld8.acq", LDINCREG (0x17, 0)}, + {"ld8.acq.nt1", LDINCREG (0x17, 1)}, + {"ld8.acq.nta", LDINCREG (0x17, 3)}, + {"ld8.fill", LDINCREG (0x1b, 0)}, + {"ld8.fill.nt1", LDINCREG (0x1b, 1)}, + {"ld8.fill.nta", LDINCREG (0x1b, 3)}, + {"ld1.c.clr", LDINCREG (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCREG (0x20, 1)}, + {"ld1.c.clr.nta", LDINCREG (0x20, 3)}, + {"ld2.c.clr", LDINCREG (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCREG (0x21, 1)}, + {"ld2.c.clr.nta", LDINCREG (0x21, 3)}, + {"ld4.c.clr", LDINCREG (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCREG (0x22, 1)}, + {"ld4.c.clr.nta", LDINCREG (0x22, 3)}, + {"ld8.c.clr", LDINCREG (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCREG (0x23, 1)}, + {"ld8.c.clr.nta", LDINCREG (0x23, 3)}, + {"ld1.c.nc", LDINCREG (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCREG (0x24, 1)}, + {"ld1.c.nc.nta", LDINCREG (0x24, 3)}, + {"ld2.c.nc", LDINCREG (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCREG (0x25, 1)}, + {"ld2.c.nc.nta", LDINCREG (0x25, 3)}, + {"ld4.c.nc", LDINCREG (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCREG (0x26, 1)}, + {"ld4.c.nc.nta", LDINCREG (0x26, 3)}, + {"ld8.c.nc", LDINCREG (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCREG (0x27, 1)}, + {"ld8.c.nc.nta", LDINCREG (0x27, 3)}, + {"ld1.c.clr.acq", LDINCREG (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)}, + {"ld2.c.clr.acq", LDINCREG (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)}, + {"ld4.c.clr.acq", LDINCREG (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCREG (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, +#undef LDINCREG + + {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}}, + {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}}, + {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}}, + {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}}, + {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}}, + {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}}, + {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}}, + {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}}, + {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}}, + {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}}, + {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}}, + {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}}, + {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}}, + {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}}, + {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}}, + {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}}, + {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}}, + {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}}, + +#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV} + {"cmpxchg1.acq", CMPXCHG (0x00, 0)}, + {"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)}, + {"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)}, + {"cmpxchg2.acq", CMPXCHG (0x01, 0)}, + {"cmpxchg2.acq.nt1", CMPXCHG (0x01, 1)}, + {"cmpxchg2.acq.nta", CMPXCHG (0x01, 3)}, + {"cmpxchg4.acq", CMPXCHG (0x02, 0)}, + {"cmpxchg4.acq.nt1", CMPXCHG (0x02, 1)}, + {"cmpxchg4.acq.nta", CMPXCHG (0x02, 3)}, + {"cmpxchg8.acq", CMPXCHG (0x03, 0)}, + {"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)}, + {"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)}, + {"cmpxchg1.rel", CMPXCHG (0x04, 0)}, + {"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)}, + {"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)}, + {"cmpxchg2.rel", CMPXCHG (0x05, 0)}, + {"cmpxchg2.rel.nt1", CMPXCHG (0x05, 1)}, + {"cmpxchg2.rel.nta", CMPXCHG (0x05, 3)}, + {"cmpxchg4.rel", CMPXCHG (0x06, 0)}, + {"cmpxchg4.rel.nt1", CMPXCHG (0x06, 1)}, + {"cmpxchg4.rel.nta", CMPXCHG (0x06, 3)}, + {"cmpxchg8.rel", CMPXCHG (0x07, 0)}, + {"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)}, + {"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)}, +#undef CMPXCHG + {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}}, + {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}}, + {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}}, + {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}}, + {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}}, + {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}}, + {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}}, + {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}}, + {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}}, + {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}}, + {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}}, + {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}}, + + {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}}, + {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}}, + {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}}, + {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}}, + {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}}, + {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}}, + {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}}, + {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}}, + {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}}, + {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}}, + {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}}, + {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}}, + + {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}}, + {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}}, + {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}}, + {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}}, + + /* integer load w/increment by immediate */ +#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC + {"ld1", LDINCIMMED (0x00, 0)}, + {"ld1.nt1", LDINCIMMED (0x00, 1)}, + {"ld1.nta", LDINCIMMED (0x00, 3)}, + {"ld2", LDINCIMMED (0x01, 0)}, + {"ld2.nt1", LDINCIMMED (0x01, 1)}, + {"ld2.nta", LDINCIMMED (0x01, 3)}, + {"ld4", LDINCIMMED (0x02, 0)}, + {"ld4.nt1", LDINCIMMED (0x02, 1)}, + {"ld4.nta", LDINCIMMED (0x02, 3)}, + {"ld8", LDINCIMMED (0x03, 0)}, + {"ld8.nt1", LDINCIMMED (0x03, 1)}, + {"ld8.nta", LDINCIMMED (0x03, 3)}, + {"ld1.s", LDINCIMMED (0x04, 0)}, + {"ld1.s.nt1", LDINCIMMED (0x04, 1)}, + {"ld1.s.nta", LDINCIMMED (0x04, 3)}, + {"ld2.s", LDINCIMMED (0x05, 0)}, + {"ld2.s.nt1", LDINCIMMED (0x05, 1)}, + {"ld2.s.nta", LDINCIMMED (0x05, 3)}, + {"ld4.s", LDINCIMMED (0x06, 0)}, + {"ld4.s.nt1", LDINCIMMED (0x06, 1)}, + {"ld4.s.nta", LDINCIMMED (0x06, 3)}, + {"ld8.s", LDINCIMMED (0x07, 0)}, + {"ld8.s.nt1", LDINCIMMED (0x07, 1)}, + {"ld8.s.nta", LDINCIMMED (0x07, 3)}, + {"ld1.a", LDINCIMMED (0x08, 0)}, + {"ld1.a.nt1", LDINCIMMED (0x08, 1)}, + {"ld1.a.nta", LDINCIMMED (0x08, 3)}, + {"ld2.a", LDINCIMMED (0x09, 0)}, + {"ld2.a.nt1", LDINCIMMED (0x09, 1)}, + {"ld2.a.nta", LDINCIMMED (0x09, 3)}, + {"ld4.a", LDINCIMMED (0x0a, 0)}, + {"ld4.a.nt1", LDINCIMMED (0x0a, 1)}, + {"ld4.a.nta", LDINCIMMED (0x0a, 3)}, + {"ld8.a", LDINCIMMED (0x0b, 0)}, + {"ld8.a.nt1", LDINCIMMED (0x0b, 1)}, + {"ld8.a.nta", LDINCIMMED (0x0b, 3)}, + {"ld1.sa", LDINCIMMED (0x0c, 0)}, + {"ld1.sa.nt1", LDINCIMMED (0x0c, 1)}, + {"ld1.sa.nta", LDINCIMMED (0x0c, 3)}, + {"ld2.sa", LDINCIMMED (0x0d, 0)}, + {"ld2.sa.nt1", LDINCIMMED (0x0d, 1)}, + {"ld2.sa.nta", LDINCIMMED (0x0d, 3)}, + {"ld4.sa", LDINCIMMED (0x0e, 0)}, + {"ld4.sa.nt1", LDINCIMMED (0x0e, 1)}, + {"ld4.sa.nta", LDINCIMMED (0x0e, 3)}, + {"ld8.sa", LDINCIMMED (0x0f, 0)}, + {"ld8.sa.nt1", LDINCIMMED (0x0f, 1)}, + {"ld8.sa.nta", LDINCIMMED (0x0f, 3)}, + {"ld1.bias", LDINCIMMED (0x10, 0)}, + {"ld1.bias.nt1", LDINCIMMED (0x10, 1)}, + {"ld1.bias.nta", LDINCIMMED (0x10, 3)}, + {"ld2.bias", LDINCIMMED (0x11, 0)}, + {"ld2.bias.nt1", LDINCIMMED (0x11, 1)}, + {"ld2.bias.nta", LDINCIMMED (0x11, 3)}, + {"ld4.bias", LDINCIMMED (0x12, 0)}, + {"ld4.bias.nt1", LDINCIMMED (0x12, 1)}, + {"ld4.bias.nta", LDINCIMMED (0x12, 3)}, + {"ld8.bias", LDINCIMMED (0x13, 0)}, + {"ld8.bias.nt1", LDINCIMMED (0x13, 1)}, + {"ld8.bias.nta", LDINCIMMED (0x13, 3)}, + {"ld1.acq", LDINCIMMED (0x14, 0)}, + {"ld1.acq.nt1", LDINCIMMED (0x14, 1)}, + {"ld1.acq.nta", LDINCIMMED (0x14, 3)}, + {"ld2.acq", LDINCIMMED (0x15, 0)}, + {"ld2.acq.nt1", LDINCIMMED (0x15, 1)}, + {"ld2.acq.nta", LDINCIMMED (0x15, 3)}, + {"ld4.acq", LDINCIMMED (0x16, 0)}, + {"ld4.acq.nt1", LDINCIMMED (0x16, 1)}, + {"ld4.acq.nta", LDINCIMMED (0x16, 3)}, + {"ld8.acq", LDINCIMMED (0x17, 0)}, + {"ld8.acq.nt1", LDINCIMMED (0x17, 1)}, + {"ld8.acq.nta", LDINCIMMED (0x17, 3)}, + {"ld8.fill", LDINCIMMED (0x1b, 0)}, + {"ld8.fill.nt1", LDINCIMMED (0x1b, 1)}, + {"ld8.fill.nta", LDINCIMMED (0x1b, 3)}, + {"ld1.c.clr", LDINCIMMED (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)}, + {"ld1.c.clr.nta", LDINCIMMED (0x20, 3)}, + {"ld2.c.clr", LDINCIMMED (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)}, + {"ld2.c.clr.nta", LDINCIMMED (0x21, 3)}, + {"ld4.c.clr", LDINCIMMED (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)}, + {"ld4.c.clr.nta", LDINCIMMED (0x22, 3)}, + {"ld8.c.clr", LDINCIMMED (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)}, + {"ld8.c.clr.nta", LDINCIMMED (0x23, 3)}, + {"ld1.c.nc", LDINCIMMED (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)}, + {"ld1.c.nc.nta", LDINCIMMED (0x24, 3)}, + {"ld2.c.nc", LDINCIMMED (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)}, + {"ld2.c.nc.nta", LDINCIMMED (0x25, 3)}, + {"ld4.c.nc", LDINCIMMED (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)}, + {"ld4.c.nc.nta", LDINCIMMED (0x26, 3)}, + {"ld8.c.nc", LDINCIMMED (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)}, + {"ld8.c.nc.nta", LDINCIMMED (0x27, 3)}, + {"ld1.c.clr.acq", LDINCIMMED (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)}, + {"ld2.c.clr.acq", LDINCIMMED (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)}, + {"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, +#undef LDINCIMMED + + /* store w/increment by immediate */ +#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC + {"st1", STINCIMMED (0x30, 0)}, + {"st1.nta", STINCIMMED (0x30, 3)}, + {"st2", STINCIMMED (0x31, 0)}, + {"st2.nta", STINCIMMED (0x31, 3)}, + {"st4", STINCIMMED (0x32, 0)}, + {"st4.nta", STINCIMMED (0x32, 3)}, + {"st8", STINCIMMED (0x33, 0)}, + {"st8.nta", STINCIMMED (0x33, 3)}, + {"st1.rel", STINCIMMED (0x34, 0)}, + {"st1.rel.nta", STINCIMMED (0x34, 3)}, + {"st2.rel", STINCIMMED (0x35, 0)}, + {"st2.rel.nta", STINCIMMED (0x35, 3)}, + {"st4.rel", STINCIMMED (0x36, 0)}, + {"st4.rel.nta", STINCIMMED (0x36, 3)}, + {"st8.rel", STINCIMMED (0x37, 0)}, + {"st8.rel.nta", STINCIMMED (0x37, 3)}, + {"st8.spill", STINCIMMED (0x3b, 0)}, + {"st8.spill.nta", STINCIMMED (0x3b, 3)}, +#undef STINCIMMED + + /* floating-point load */ + {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}}, + {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}}, + {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}}, + {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}}, + {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}}, + {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}}, + {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}}, + {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}}, + {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}}, + {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}}, + {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}}, + {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}}, + {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}}, + {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}}, + {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}}, + {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}}, + {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}}, + {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}}, + {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}}, + {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}}, + {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}}, + {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}}, + {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}}, + {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}}, + {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}}, + + /* floating-point load w/increment by register */ +#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC + {"ldfs", FLDINCREG (0x02, 0)}, + {"ldfs.nt1", FLDINCREG (0x02, 1)}, + {"ldfs.nta", FLDINCREG (0x02, 3)}, + {"ldfd", FLDINCREG (0x03, 0)}, + {"ldfd.nt1", FLDINCREG (0x03, 1)}, + {"ldfd.nta", FLDINCREG (0x03, 3)}, + {"ldf8", FLDINCREG (0x01, 0)}, + {"ldf8.nt1", FLDINCREG (0x01, 1)}, + {"ldf8.nta", FLDINCREG (0x01, 3)}, + {"ldfe", FLDINCREG (0x00, 0)}, + {"ldfe.nt1", FLDINCREG (0x00, 1)}, + {"ldfe.nta", FLDINCREG (0x00, 3)}, + {"ldfs.s", FLDINCREG (0x06, 0)}, + {"ldfs.s.nt1", FLDINCREG (0x06, 1)}, + {"ldfs.s.nta", FLDINCREG (0x06, 3)}, + {"ldfd.s", FLDINCREG (0x07, 0)}, + {"ldfd.s.nt1", FLDINCREG (0x07, 1)}, + {"ldfd.s.nta", FLDINCREG (0x07, 3)}, + {"ldf8.s", FLDINCREG (0x05, 0)}, + {"ldf8.s.nt1", FLDINCREG (0x05, 1)}, + {"ldf8.s.nta", FLDINCREG (0x05, 3)}, + {"ldfe.s", FLDINCREG (0x04, 0)}, + {"ldfe.s.nt1", FLDINCREG (0x04, 1)}, + {"ldfe.s.nta", FLDINCREG (0x04, 3)}, + {"ldfs.a", FLDINCREG (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCREG (0x0a, 1)}, + {"ldfs.a.nta", FLDINCREG (0x0a, 3)}, + {"ldfd.a", FLDINCREG (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCREG (0x0b, 1)}, + {"ldfd.a.nta", FLDINCREG (0x0b, 3)}, + {"ldf8.a", FLDINCREG (0x09, 0)}, + {"ldf8.a.nt1", FLDINCREG (0x09, 1)}, + {"ldf8.a.nta", FLDINCREG (0x09, 3)}, + {"ldfe.a", FLDINCREG (0x08, 0)}, + {"ldfe.a.nt1", FLDINCREG (0x08, 1)}, + {"ldfe.a.nta", FLDINCREG (0x08, 3)}, + {"ldfs.sa", FLDINCREG (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCREG (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCREG (0x0e, 3)}, + {"ldfd.sa", FLDINCREG (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCREG (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCREG (0x0f, 3)}, + {"ldf8.sa", FLDINCREG (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCREG (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCREG (0x0d, 3)}, + {"ldfe.sa", FLDINCREG (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCREG (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCREG (0x0c, 3)}, + {"ldf.fill", FLDINCREG (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCREG (0x1b, 1)}, + {"ldf.fill.nta", FLDINCREG (0x1b, 3)}, + {"ldfs.c.clr", FLDINCREG (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCREG (0x22, 3)}, + {"ldfd.c.clr", FLDINCREG (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCREG (0x23, 3)}, + {"ldf8.c.clr", FLDINCREG (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCREG (0x21, 3)}, + {"ldfe.c.clr", FLDINCREG (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCREG (0x20, 3)}, + {"ldfs.c.nc", FLDINCREG (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCREG (0x26, 3)}, + {"ldfd.c.nc", FLDINCREG (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCREG (0x27, 3)}, + {"ldf8.c.nc", FLDINCREG (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCREG (0x25, 3)}, + {"ldfe.c.nc", FLDINCREG (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, +#undef FLDINCREG + + /* floating-point store */ + {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}}, + {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}}, + {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}}, + {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}}, + {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}}, + {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}}, + {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}}, + {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}}, + {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}}, + {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}}, + + /* floating-point load pair */ + {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}}, + {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}}, + {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}}, + {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}}, + {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}}, + {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}}, + {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}}, + {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}}, + {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}}, + {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}}, + {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}}, + {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}}, + {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}}, + {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}}, + {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}}, + {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}}, + {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}}, + {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}}, + {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}}, + {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}}, + {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}}, + {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}}, + {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}}, + {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}}, + {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}}, + {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}}, + {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}}, + {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}}, + {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}}, + {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}}, + {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}}, + {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}}, + {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}}, + {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}}, + {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}}, + {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}}, + {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}}, + {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}}, + {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}}, + {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}}, + {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}}, + {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}}, + {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}}, + {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}}, + {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}}, + {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}}, + {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}}, + {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}}, + {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}}, + {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}}, + {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}}, + {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}}, + {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}}, + {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}}, + + /* floating-point load pair w/increment by immediate */ +#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC + {"ldfps", LD (0x02, 0, C8)}, + {"ldfps.nt1", LD (0x02, 1, C8)}, + {"ldfps.nta", LD (0x02, 3, C8)}, + {"ldfpd", LD (0x03, 0, C16)}, + {"ldfpd.nt1", LD (0x03, 1, C16)}, + {"ldfpd.nta", LD (0x03, 3, C16)}, + {"ldfp8", LD (0x01, 0, C16)}, + {"ldfp8.nt1", LD (0x01, 1, C16)}, + {"ldfp8.nta", LD (0x01, 3, C16)}, + {"ldfps.s", LD (0x06, 0, C8)}, + {"ldfps.s.nt1", LD (0x06, 1, C8)}, + {"ldfps.s.nta", LD (0x06, 3, C8)}, + {"ldfpd.s", LD (0x07, 0, C16)}, + {"ldfpd.s.nt1", LD (0x07, 1, C16)}, + {"ldfpd.s.nta", LD (0x07, 3, C16)}, + {"ldfp8.s", LD (0x05, 0, C16)}, + {"ldfp8.s.nt1", LD (0x05, 1, C16)}, + {"ldfp8.s.nta", LD (0x05, 3, C16)}, + {"ldfps.a", LD (0x0a, 0, C8)}, + {"ldfps.a.nt1", LD (0x0a, 1, C8)}, + {"ldfps.a.nta", LD (0x0a, 3, C8)}, + {"ldfpd.a", LD (0x0b, 0, C16)}, + {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, + {"ldfpd.a.nta", LD (0x0b, 3, C16)}, + {"ldfp8.a", LD (0x09, 0, C16)}, + {"ldfp8.a.nt1", LD (0x09, 1, C16)}, + {"ldfp8.a.nta", LD (0x09, 3, C16)}, + {"ldfps.sa", LD (0x0e, 0, C8)}, + {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, + {"ldfps.sa.nta", LD (0x0e, 3, C8)}, + {"ldfpd.sa", LD (0x0f, 0, C16)}, + {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, + {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, + {"ldfp8.sa", LD (0x0d, 0, C16)}, + {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, + {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, + {"ldfps.c.clr", LD (0x22, 0, C8)}, + {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, + {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, + {"ldfpd.c.clr", LD (0x23, 0, C16)}, + {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, + {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, + {"ldfp8.c.clr", LD (0x21, 0, C16)}, + {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, + {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, + {"ldfps.c.nc", LD (0x26, 0, C8)}, + {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, + {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, + {"ldfpd.c.nc", LD (0x27, 0, C16)}, + {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, + {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, + {"ldfp8.c.nc", LD (0x25, 0, C16)}, + {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, + {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, +#undef LD + + /* line prefetch */ + {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}}, + {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}}, + {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}}, + {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}}, + + /* line prefetch w/increment by register */ +#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC + {"lfetch", LFETCHINCREG (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCREG (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCREG (0x2c, 2)}, + {"lfetch.nta", LFETCHINCREG (0x2c, 3)}, + {"lfetch.excl", LFETCHINCREG (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCREG (0x2d, 3)}, + {"lfetch.fault", LFETCHINCREG (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCREG (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCREG (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)}, +#undef LFETCHINCREG + + /* semaphore operations */ + {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}}, + {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}}, + {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}}, + {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}}, + + /* floating-point load w/increment by immediate */ +#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC + {"ldfs", FLDINCIMMED (0x02, 0)}, + {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, + {"ldfs.nta", FLDINCIMMED (0x02, 3)}, + {"ldfd", FLDINCIMMED (0x03, 0)}, + {"ldfd.nt1", FLDINCIMMED (0x03, 1)}, + {"ldfd.nta", FLDINCIMMED (0x03, 3)}, + {"ldf8", FLDINCIMMED (0x01, 0)}, + {"ldf8.nt1", FLDINCIMMED (0x01, 1)}, + {"ldf8.nta", FLDINCIMMED (0x01, 3)}, + {"ldfe", FLDINCIMMED (0x00, 0)}, + {"ldfe.nt1", FLDINCIMMED (0x00, 1)}, + {"ldfe.nta", FLDINCIMMED (0x00, 3)}, + {"ldfs.s", FLDINCIMMED (0x06, 0)}, + {"ldfs.s.nt1", FLDINCIMMED (0x06, 1)}, + {"ldfs.s.nta", FLDINCIMMED (0x06, 3)}, + {"ldfd.s", FLDINCIMMED (0x07, 0)}, + {"ldfd.s.nt1", FLDINCIMMED (0x07, 1)}, + {"ldfd.s.nta", FLDINCIMMED (0x07, 3)}, + {"ldf8.s", FLDINCIMMED (0x05, 0)}, + {"ldf8.s.nt1", FLDINCIMMED (0x05, 1)}, + {"ldf8.s.nta", FLDINCIMMED (0x05, 3)}, + {"ldfe.s", FLDINCIMMED (0x04, 0)}, + {"ldfe.s.nt1", FLDINCIMMED (0x04, 1)}, + {"ldfe.s.nta", FLDINCIMMED (0x04, 3)}, + {"ldfs.a", FLDINCIMMED (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)}, + {"ldfs.a.nta", FLDINCIMMED (0x0a, 3)}, + {"ldfd.a", FLDINCIMMED (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)}, + {"ldfd.a.nta", FLDINCIMMED (0x0b, 3)}, + {"ldf8.a", FLDINCIMMED (0x09, 0)}, + {"ldf8.a.nt1", FLDINCIMMED (0x09, 1)}, + {"ldf8.a.nta", FLDINCIMMED (0x09, 3)}, + {"ldfe.a", FLDINCIMMED (0x08, 0)}, + {"ldfe.a.nt1", FLDINCIMMED (0x08, 1)}, + {"ldfe.a.nta", FLDINCIMMED (0x08, 3)}, + {"ldfs.sa", FLDINCIMMED (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)}, + {"ldfd.sa", FLDINCIMMED (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)}, + {"ldf8.sa", FLDINCIMMED (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)}, + {"ldfe.sa", FLDINCIMMED (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)}, + {"ldf.fill", FLDINCIMMED (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)}, + {"ldf.fill.nta", FLDINCIMMED (0x1b, 3)}, + {"ldfs.c.clr", FLDINCIMMED (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)}, + {"ldfd.c.clr", FLDINCIMMED (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)}, + {"ldf8.c.clr", FLDINCIMMED (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)}, + {"ldfe.c.clr", FLDINCIMMED (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)}, + {"ldfs.c.nc", FLDINCIMMED (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)}, + {"ldfd.c.nc", FLDINCIMMED (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)}, + {"ldf8.c.nc", FLDINCIMMED (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)}, + {"ldfe.c.nc", FLDINCIMMED (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, +#undef FLDINCIMMED + + /* floating-point store w/increment by immediate */ +#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC + {"stfs", FSTINCIMMED (0x32, 0)}, + {"stfs.nta", FSTINCIMMED (0x32, 3)}, + {"stfd", FSTINCIMMED (0x33, 0)}, + {"stfd.nta", FSTINCIMMED (0x33, 3)}, + {"stf8", FSTINCIMMED (0x31, 0)}, + {"stf8.nta", FSTINCIMMED (0x31, 3)}, + {"stfe", FSTINCIMMED (0x30, 0)}, + {"stfe.nta", FSTINCIMMED (0x30, 3)}, + {"stf.spill", FSTINCIMMED (0x3b, 0)}, + {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, +#undef FSTINCIMMED + + /* line prefetch w/increment by immediate */ +#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC + {"lfetch", LFETCHINCIMMED (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)}, + {"lfetch.nta", LFETCHINCIMMED (0x2c, 3)}, + {"lfetch.excl", LFETCHINCIMMED (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3)}, + {"lfetch.fault", LFETCHINCIMMED (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)}, +#undef LFETCHINCIMMED + + {0} + }; + +#undef M0 +#undef M +#undef M2 +#undef bM +#undef bX +#undef bX2 +#undef bX3 +#undef bX4 +#undef bX6a +#undef bX6b +#undef bHint +#undef mM +#undef mX +#undef mX2 +#undef mX3 +#undef mX4 +#undef mX6a +#undef mX6b +#undef mHint +#undef OpX3 +#undef OpX3X6b +#undef OpX3X4 +#undef OpX3X4X2 +#undef OpX6aHint +#undef OpXX6aHint +#undef OpMXX6a +#undef OpMXX6aHint diff --git a/opcodes/ia64-opc-x.c b/opcodes/ia64-opc-x.c new file mode 100644 index 0000000..5f382fd --- /dev/null +++ b/opcodes/ia64-opc-x.c @@ -0,0 +1,178 @@ +/* ia64-opc-x.c -- IA-64 `X' opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by Timothy Wall + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +/* identify the specific X-unit type */ +#define X0 IA64_TYPE_X, 0 +#define X IA64_TYPE_X, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mVc bVc (-1) +#define mWha bWha (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) + +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) + +struct ia64_opcode ia64_opcodes_x[] = + { + {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}}, + {"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}}, + {"movl", X, OpVc (6, 0), {R1, IMMU64}}, +#define BRL(a,b) \ + X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0 + {"brl.few", BRL (0, 0) | PSEUDO}, + {"brl", BRL (0, 0) | PSEUDO}, + {"brl.few.clr", BRL (0, 1) | PSEUDO}, + {"brl.clr", BRL (0, 1) | PSEUDO}, + {"brl.many", BRL (1, 0) | PSEUDO}, + {"brl.many.clr", BRL (1, 1) | PSEUDO}, +#undef BRL +#define BRL(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0 + {"brl.cond.sptk.few", BRL (0, 0, 0)}, + {"brl.cond.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.cond.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.cond.spnt.few", BRL (0, 1, 0)}, + {"brl.cond.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.cond.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.cond.dptk.few", BRL (0, 2, 0)}, + {"brl.cond.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.cond.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.cond.dpnt.few", BRL (0, 3, 0)}, + {"brl.cond.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.cond.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.cond.sptk.many", BRL (1, 0, 0)}, + {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.cond.spnt.many", BRL (1, 1, 0)}, + {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.cond.dptk.many", BRL (1, 2, 0)}, + {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.cond.dpnt.many", BRL (1, 3, 0)}, + {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, + {"brl.sptk.few", BRL (0, 0, 0)}, + {"brl.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.spnt.few", BRL (0, 1, 0)}, + {"brl.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.dptk.few", BRL (0, 2, 0)}, + {"brl.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.dpnt.few", BRL (0, 3, 0)}, + {"brl.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.sptk.many", BRL (1, 0, 0)}, + {"brl.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.spnt.many", BRL (1, 1, 0)}, + {"brl.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.dptk.many", BRL (1, 2, 0)}, + {"brl.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.dpnt.many", BRL (1, 3, 0)}, + {"brl.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0 + {"brl.call.sptk.few", BRL (0, 0, 0)}, + {"brl.call.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.call.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.call.spnt.few", BRL (0, 1, 0)}, + {"brl.call.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.call.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.call.dptk.few", BRL (0, 2, 0)}, + {"brl.call.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.call.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.call.dpnt.few", BRL (0, 3, 0)}, + {"brl.call.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.call.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.call.sptk.many", BRL (1, 0, 0)}, + {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.call.spnt.many", BRL (1, 1, 0)}, + {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.call.dptk.many", BRL (1, 2, 0)}, + {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.call.dpnt.many", BRL (1, 3, 0)}, + {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL + {0} + }; + +#undef X0 +#undef X + +#undef bBtype +#undef bD +#undef bPa +#undef bPr +#undef bVc +#undef bWha +#undef bX3 +#undef bX6 + +#undef mBtype +#undef mD +#undef mPa +#undef mPr +#undef mVc +#undef mWha +#undef mX3 +#undef mX6 + +#undef OpX3X6 +#undef OpVc +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c new file mode 100644 index 0000000..9726381 --- /dev/null +++ b/opcodes/ia64-opc.c @@ -0,0 +1,762 @@ +/* ia64-opc.c -- Functions to access the compacted opcode table + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Bob Manson of Cygnus Solutions, + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ansidecl.h" +#include "libiberty.h" +#include "sysdep.h" +#include "ia64-asmtab.h" +#include "ia64-asmtab.c" + +static void get_opc_prefix PARAMS ((const char **, char *)); +static short int find_string_ent PARAMS ((const char *)); +static short int find_main_ent PARAMS ((short int)); +static short int find_completer PARAMS ((short int, short int, const char *)); +static ia64_insn apply_completer PARAMS ((ia64_insn, int)); +static int extract_op_bits PARAMS ((int, int, int)); +static int extract_op PARAMS ((int, int *, unsigned int *)); +static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type)); +static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type)); +static struct ia64_opcode *make_ia64_opcode + PARAMS ((ia64_insn, const char *, int, int)); +static struct ia64_opcode *ia64_find_matching_opcode + PARAMS ((const char *, short int)); + +const struct ia64_templ_desc ia64_templ_desc[16] = + { + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ + { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, + { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, + { 0, { 0, }, "-3-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ + { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ + { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, + { 0, { 0, }, "-a-" }, + { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ + { 0, { 0, }, "-d-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, + { 0, { 0, }, "-f-" }, + }; + + +/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. + PTR will be adjusted to point to the start of the next portion + of the opcode, or at the NUL character. */ + +static void +get_opc_prefix (ptr, dest) + const char **ptr; + char *dest; +{ + char *c = strchr (*ptr, '.'); + if (c != NULL) + { + memcpy (dest, *ptr, c - *ptr); + dest[c - *ptr] = '\0'; + *ptr = c + 1; + } + else + { + int l = strlen (*ptr); + memcpy (dest, *ptr, l); + dest[l] = '\0'; + *ptr += l; + } +} + +/* Find the index of the entry in the string table corresponding to + STR; return -1 if one does not exist. */ + +static short +find_string_ent (str) + const char *str; +{ + short start = 0; + short end = sizeof (ia64_strings) / sizeof (const char *); + short i = (start + end) / 2; + + if (strcmp (str, ia64_strings[end - 1]) > 0) + { + return -1; + } + while (start <= end) + { + int c = strcmp (str, ia64_strings[i]); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the opcode in the main opcode table whose name is STRINGINDEX, or + return -1 if one does not exist. */ + +static short +find_main_ent (nameindex) + short nameindex; +{ + short start = 0; + short end = sizeof (main_table) / sizeof (struct ia64_main_table); + short i = (start + end) / 2; + + if (nameindex < main_table[0].name_index + || nameindex > main_table[end - 1].name_index) + { + return -1; + } + while (start <= end) + { + if (nameindex < main_table[i].name_index) + { + end = i - 1; + } + else if (nameindex == main_table[i].name_index) + { + while (i > 0 && main_table[i - 1].name_index == nameindex) + { + i--; + } + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the index of the entry in the completer table that is part of + MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or + return -1 if one does not exist. */ + +static short +find_completer (main_ent, prev_completer, name) + short main_ent; + short prev_completer; + const char *name; +{ + short name_index = find_string_ent (name); + + if (name_index < 0) + { + return -1; + } + + if (prev_completer == -1) + { + prev_completer = main_table[main_ent].completers; + } + else + { + prev_completer = completer_table[prev_completer].subentries; + } + + while (prev_completer != -1) + { + if (completer_table[prev_completer].name_index == name_index) + { + return prev_completer; + } + prev_completer = completer_table[prev_completer].alternative; + } + return -1; +} + +/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and + return the result. */ + +static ia64_insn +apply_completer (opcode, completer_index) + ia64_insn opcode; + int completer_index; +{ + ia64_insn mask = completer_table[completer_index].mask; + ia64_insn bits = completer_table[completer_index].bits; + int shiftamt = (completer_table[completer_index].offset & 63); + + mask = mask << shiftamt; + bits = bits << shiftamt; + opcode = (opcode & ~mask) | bits; + return opcode; +} + +/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in + the dis_table array, and return its value. (BITOFFSET is numbered + starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the + first byte in OP_POINTER.) */ + +static int +extract_op_bits (op_pointer, bitoffset, bits) + int op_pointer; + int bitoffset; + int bits; +{ + int res = 0; + + op_pointer += (bitoffset / 8); + + if (bitoffset % 8) + { + unsigned int op = dis_table[op_pointer++]; + int numb = 8 - (bitoffset % 8); + int mask = (1 << numb) - 1; + int bata = (bits < numb) ? bits : numb; + int delta = numb - bata; + + res = (res << bata) | ((op & mask) >> delta); + bitoffset += bata; + bits -= bata; + } + while (bits >= 8) + { + res = (res << 8) | (dis_table[op_pointer++] & 255); + bits -= 8; + } + if (bits > 0) + { + unsigned int op = (dis_table[op_pointer++] & 255); + res = (res << bits) | (op >> (8 - bits)); + } + return res; +} + +/* Examine the state machine entry at OP_POINTER in the dis_table + array, and extract its values into OPVAL and OP. The length of the + state entry in bits is returned. */ + +static int +extract_op (op_pointer, opval, op) + int op_pointer; + int *opval; + unsigned int *op; +{ + int oplen = 5; + + *op = dis_table[op_pointer]; + + if ((*op) & 0x40) + { + opval[0] = extract_op_bits (op_pointer, oplen, 5); + oplen += 5; + } + switch ((*op) & 0x30) + { + case 0x10: + { + opval[1] = extract_op_bits (op_pointer, oplen, 8); + oplen += 8; + opval[1] += op_pointer; + break; + } + case 0x20: + { + opval[1] = extract_op_bits (op_pointer, oplen, 16); + if (! (opval[1] & 32768)) + { + opval[1] += op_pointer; + } + oplen += 16; + break; + } + case 0x30: + { + oplen--; + opval[2] = extract_op_bits (op_pointer, oplen, 12); + oplen += 12; + opval[2] |= 32768; + break; + } + } + if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) + { + opval[2] = extract_op_bits (op_pointer, oplen, 16); + oplen += 16; + if (! (opval[2] & 32768)) + { + opval[2] += op_pointer; + } + } + return oplen; +} + +/* Returns a non-zero value if the opcode in the main_table list at + PLACE matches OPCODE and is of type TYPE. */ + +static int +opcode_verify (opcode, place, type) + ia64_insn opcode; + int place; + enum ia64_insn_type type; +{ + if (main_table[place].opcode_type != type) + { + return 0; + } + if (main_table[place].flags + & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) + { + const struct ia64_operand *o1, *o2; + ia64_insn f2, f3; + + if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) + { + o1 = elf64_ia64_operands + IA64_OPND_F2; + o2 = elf64_ia64_operands + IA64_OPND_F3; + (*o1->extract) (o1, opcode, &f2); + (*o2->extract) (o2, opcode, &f3); + if (f2 != f3) + return 0; + } + else + { + ia64_insn len, count; + + /* length must equal 64-count: */ + o1 = elf64_ia64_operands + IA64_OPND_LEN6; + o2 = elf64_ia64_operands + main_table[place].operands[2]; + (*o1->extract) (o1, opcode, &len); + (*o2->extract) (o2, opcode, &count); + if (len != 64 - count) + return 0; + } + } + return 1; +} + +/* Find an instruction entry in the ia64_dis_names array that matches + opcode OPCODE and is of type TYPE. Returns either a positive index + into the array, or a negative value if an entry for OPCODE could + not be found. Checks all matches and returns the one with the highest + priority. */ + +static int +locate_opcode_ent (opcode, type) + ia64_insn opcode; + enum ia64_insn_type type; +{ + int currtest[41]; + int bitpos[41]; + int op_ptr[41]; + int currstatenum = 0; + short found_disent = -1; + short found_priority = -1; + + currtest[currstatenum] = 0; + op_ptr[currstatenum] = 0; + bitpos[currstatenum] = 40; + + while (1) + { + int op_pointer = op_ptr[currstatenum]; + unsigned int op; + int currbitnum = bitpos[currstatenum]; + int oplen; + int opval[3]; + int next_op; + int currbit; + + oplen = extract_op (op_pointer, opval, &op); + + bitpos[currstatenum] = currbitnum; + + /* Skip opval[0] bits in the instruction. */ + if (op & 0x40) + { + currbitnum -= opval[0]; + } + + /* The value of the current bit being tested. */ + currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; + next_op = -1; + + /* We always perform the tests specified in the current state in + a particular order, falling through to the next test if the + previous one failed. */ + switch (currtest[currstatenum]) + { + case 0: + currtest[currstatenum]++; + if (currbit == 0 && (op & 0x80)) + { + /* Check for a zero bit. If this test solely checks for + a zero bit, we can check for up to 8 consecutive zero + bits (the number to check is specified by the lower 3 + bits in the state code.) + + If the state instruction matches, we go to the very + next state instruction; otherwise, try the next test. */ + + if ((op & 0xf8) == 0x80) + { + int count = op & 0x7; + int x; + + for (x = 0; x <= count; x++) + { + int i = + opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; + if (i) + { + break; + } + } + if (x > count) + { + next_op = op_pointer + ((oplen + 7) / 8); + currbitnum -= count; + break; + } + } + else if (! currbit) + { + next_op = op_pointer + ((oplen + 7) / 8); + break; + } + } + /* FALLTHROUGH */ + case 1: + /* If the bit in the instruction is one, go to the state + instruction specified by opval[1]. */ + currtest[currstatenum]++; + if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) + { + next_op = opval[1]; + break; + } + /* FALLTHROUGH */ + case 2: + /* Don't care. Skip the current bit and go to the state + instruction specified by opval[2]. + + An encoding of 0x30 is special; this means that a 12-bit + offset into the ia64_dis_names[] array is specified. */ + currtest[currstatenum]++; + if ((op & 0x08) || ((op & 0x30) == 0x30)) + { + next_op = opval[2]; + break; + } + } + + /* If bit 15 is set in the address of the next state, an offset + in the ia64_dis_names array was specified instead. We then + check to see if an entry in the list of opcodes matches the + opcode we were given; if so, we have succeeded. */ + + if ((next_op >= 0) && (next_op & 32768)) + { + short disent = next_op & 32767; + short priority = -1; + + if (next_op > 65535) + { + abort (); + } + + /* Run through the list of opcodes to check, trying to find + one that matches. */ + while (disent >= 0) + { + int place = ia64_dis_names[disent].insn_index; + + priority = ia64_dis_names[disent].priority; + + if (opcode_verify (opcode, place, type) + && priority > found_priority) + { + break; + } + if (ia64_dis_names[disent].next_flag) + { + disent++; + } + else + { + disent = -1; + } + } + + if (disent >= 0) + { + found_disent = disent; + found_priority = priority; + } + /* Try the next test in this state, regardless of whether a match + was found. */ + next_op = -2; + } + + /* next_op == -1 is "back up to the previous state". + next_op == -2 is "stay in this state and try the next test". + Otherwise, transition to the state indicated by next_op. */ + + if (next_op == -1) + { + currstatenum--; + if (currstatenum < 0) + { + return found_disent; + } + } + else if (next_op >= 0) + { + currstatenum++; + bitpos[currstatenum] = currbitnum - 1; + op_ptr[currstatenum] = next_op; + currtest[currstatenum] = 0; + } + } +} + +/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ + +static struct ia64_opcode * +make_ia64_opcode (opcode, name, place, depind) + ia64_insn opcode; + const char *name; + int place; + int depind; +{ + struct ia64_opcode *res = + (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); + res->name = xstrdup (name); + res->type = main_table[place].opcode_type; + res->num_outputs = main_table[place].num_outputs; + res->opcode = opcode; + res->mask = main_table[place].mask; + res->operands[0] = main_table[place].operands[0]; + res->operands[1] = main_table[place].operands[1]; + res->operands[2] = main_table[place].operands[2]; + res->operands[3] = main_table[place].operands[3]; + res->operands[4] = main_table[place].operands[4]; + res->flags = main_table[place].flags; + res->ent_index = place; + res->dependencies = &op_dependencies[depind]; + return res; +} + +/* Determine the ia64_opcode entry for the opcode specified by INSN + and TYPE. If a valid entry is not found, return NULL. */ +struct ia64_opcode * +ia64_dis_opcode (insn, type) + ia64_insn insn; + enum ia64_insn_type type; +{ + int disent = locate_opcode_ent (insn, type); + + if (disent < 0) + { + return NULL; + } + else + { + unsigned int cb = ia64_dis_names[disent].completer_index; + static char name[128]; + int place = ia64_dis_names[disent].insn_index; + int ci = main_table[place].completers; + ia64_insn tinsn = main_table[place].opcode; + + strcpy (name, ia64_strings [main_table[place].name_index]); + + while (cb) + { + if (cb & 1) + { + int cname = completer_table[ci].name_index; + + tinsn = apply_completer (tinsn, ci); + + if (ia64_strings[cname][0] != '\0') + { + strcat (name, "."); + strcat (name, ia64_strings[cname]); + } + if (cb != 1) + { + ci = completer_table[ci].subentries; + } + } + else + { + ci = completer_table[ci].alternative; + } + if (ci < 0) + { + abort (); + } + cb = cb >> 1; + } + if (tinsn != (insn & main_table[place].mask)) + { + abort (); + } + return make_ia64_opcode (insn, name, place, + completer_table[ci].dependencies); + } +} + +/* Search the main_opcode table starting from PLACE for an opcode that + matches NAME. Return NULL if one is not found. */ + +static struct ia64_opcode * +ia64_find_matching_opcode (name, place) + const char *name; + short place; +{ + char op[129]; + const char *suffix; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + while (main_table[place].name_index == name_index) + { + const char *curr_suffix = suffix; + ia64_insn curr_insn = main_table[place].opcode; + short completer = -1; + + do { + if (suffix[0] == '\0') + { + completer = find_completer (place, completer, suffix); + } + else + { + get_opc_prefix (&curr_suffix, op); + completer = find_completer (place, completer, op); + } + if (completer != -1) + { + curr_insn = apply_completer (curr_insn, completer); + } + } while (completer != -1 && curr_suffix[0] != '\0'); + + if (completer != -1 && curr_suffix[0] == '\0' + && completer_table[completer].terminal_completer) + { + int depind = completer_table[completer].dependencies; + return make_ia64_opcode (curr_insn, name, place, depind); + } + else + { + place++; + } + } + return NULL; +} + +/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL + if one does not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_next_opcode (prev_ent) + struct ia64_opcode *prev_ent; +{ + return ia64_find_matching_opcode (prev_ent->name, + prev_ent->ent_index + 1); +} + +/* Find the first opcode that matches NAME, or return NULL if it does + not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_opcode (name) + const char *name; +{ + char op[129]; + const char *suffix; + short place; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + place = find_main_ent (name_index); + + if (place < 0) + { + return NULL; + } + return ia64_find_matching_opcode (name, place); +} + +/* Free any resources used by ENT. */ +void +ia64_free_opcode (ent) + struct ia64_opcode *ent; +{ + free ((void *)ent->name); + free (ent); +} + +const struct ia64_dependency * +ia64_find_dependency (index) + int index; +{ + index = DEP(index); + + if (index < 0 + || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0]))) + return NULL; + + return &dependencies[index]; +} diff --git a/opcodes/ia64-opc.h b/opcodes/ia64-opc.h new file mode 100644 index 0000000..b721cb8 --- /dev/null +++ b/opcodes/ia64-opc.h @@ -0,0 +1,130 @@ +/* ia64-opc.h -- IA-64 opcode table. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef IA64_OPC_H +#define IA64_OPC_H + +#include "opcode/ia64.h" + +/* define a couple of abbreviations: */ + +#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) +#define mOp bOp (-1) +#define Op(x) bOp (x), mOp + +#define FIRST IA64_OPCODE_FIRST +#define X_IN_MLX IA64_OPCODE_X_IN_MLX +#define LAST IA64_OPCODE_LAST +#define PRIV IA64_OPCODE_PRIV +#define NO_PRED IA64_OPCODE_NO_PRED +#define SLOT2 IA64_OPCODE_SLOT2 +#define PSEUDO IA64_OPCODE_PSEUDO +#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 +#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT +#define MOD_RRBS IA64_OPCODE_MOD_RRBS +#define POSTINC IA64_OPCODE_POSTINC + +#define AR_CCV IA64_OPND_AR_CCV +#define AR_PFS IA64_OPND_AR_PFS +#define C1 IA64_OPND_C1 +#define C8 IA64_OPND_C8 +#define C16 IA64_OPND_C16 +#define GR0 IA64_OPND_GR0 +#define IP IA64_OPND_IP +#define PR IA64_OPND_PR +#define PR_ROT IA64_OPND_PR_ROT +#define PSR IA64_OPND_PSR +#define PSR_L IA64_OPND_PSR_L +#define PSR_UM IA64_OPND_PSR_UM + +#define AR3 IA64_OPND_AR3 +#define B1 IA64_OPND_B1 +#define B2 IA64_OPND_B2 +#define CR3 IA64_OPND_CR3 +#define F1 IA64_OPND_F1 +#define F2 IA64_OPND_F2 +#define F3 IA64_OPND_F3 +#define F4 IA64_OPND_F4 +#define P1 IA64_OPND_P1 +#define P2 IA64_OPND_P2 +#define R1 IA64_OPND_R1 +#define R2 IA64_OPND_R2 +#define R3 IA64_OPND_R3 +#define R3_2 IA64_OPND_R3_2 + +#define CPUID_R3 IA64_OPND_CPUID_R3 +#define DBR_R3 IA64_OPND_DBR_R3 +#define DTR_R3 IA64_OPND_DTR_R3 +#define ITR_R3 IA64_OPND_ITR_R3 +#define IBR_R3 IA64_OPND_IBR_R3 +#define MR3 IA64_OPND_MR3 +#define MSR_R3 IA64_OPND_MSR_R3 +#define PKR_R3 IA64_OPND_PKR_R3 +#define PMC_R3 IA64_OPND_PMC_R3 +#define PMD_R3 IA64_OPND_PMD_R3 +#define RR_R3 IA64_OPND_RR_R3 + +#define CCNT5 IA64_OPND_CCNT5 +#define CNT2a IA64_OPND_CNT2a +#define CNT2b IA64_OPND_CNT2b +#define CNT2c IA64_OPND_CNT2c +#define CNT5 IA64_OPND_CNT5 +#define CNT6 IA64_OPND_CNT6 +#define CPOS6a IA64_OPND_CPOS6a +#define CPOS6b IA64_OPND_CPOS6b +#define CPOS6c IA64_OPND_CPOS6c +#define IMM1 IA64_OPND_IMM1 +#define IMM14 IA64_OPND_IMM14 +#define IMM17 IA64_OPND_IMM17 +#define IMM22 IA64_OPND_IMM22 +#define IMM44 IA64_OPND_IMM44 +#define SOF IA64_OPND_SOF +#define SOL IA64_OPND_SOL +#define SOR IA64_OPND_SOR +#define IMM8 IA64_OPND_IMM8 +#define IMM8U4 IA64_OPND_IMM8U4 +#define IMM8M1 IA64_OPND_IMM8M1 +#define IMM8M1U4 IA64_OPND_IMM8M1U4 +#define IMM8M1U8 IA64_OPND_IMM8M1U8 +#define IMM9a IA64_OPND_IMM9a +#define IMM9b IA64_OPND_IMM9b +#define IMMU2 IA64_OPND_IMMU2 +#define IMMU21 IA64_OPND_IMMU21 +#define IMMU24 IA64_OPND_IMMU24 +#define IMMU62 IA64_OPND_IMMU62 +#define IMMU64 IA64_OPND_IMMU64 +#define IMMU7a IA64_OPND_IMMU7a +#define IMMU7b IA64_OPND_IMMU7b +#define IMMU9 IA64_OPND_IMMU9 +#define INC3 IA64_OPND_INC3 +#define LEN4 IA64_OPND_LEN4 +#define LEN6 IA64_OPND_LEN6 +#define MBTYPE4 IA64_OPND_MBTYPE4 +#define MHTYPE8 IA64_OPND_MHTYPE8 +#define POS6 IA64_OPND_POS6 +#define TAG13 IA64_OPND_TAG13 +#define TAG13b IA64_OPND_TAG13b +#define TGT25 IA64_OPND_TGT25 +#define TGT25b IA64_OPND_TGT25b +#define TGT25c IA64_OPND_TGT25c +#define TGT64 IA64_OPND_TGT64 + +#endif diff --git a/opcodes/ia64-raw.tbl b/opcodes/ia64-raw.tbl new file mode 100644 index 0000000..ec35888 --- /dev/null +++ b/opcodes/ia64-raw.tbl @@ -0,0 +1,174 @@ +Resource Name; Writers; Readers; Semantics of Dependency +ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF +AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF +AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; br.ret; none +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF +AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none +AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF +CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF +CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF +CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF +CFM; alloc; IC:cfm-readers; none +CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data +CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 10.8.3.4 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data +CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data +CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data +CR[IFS]; IC:mov-to-CR-IFS; rfi; implied +CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data +CR[IIP]; IC:mov-to-CR-IIP; rfi; implied +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data +CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data +CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itr.d; implied +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr +CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 10.8.3.2 +CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 10.8.3.1 +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, thash; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l, rfi, rsm, ssm; SC Section 10.8.3.3 +CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF +DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF +DTR; ptr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none +DTR; ptr.d; itr.d, itc.d; impliedF +FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none +FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF +FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none +GR0; IC:none; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data +InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc; instr +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none +ITC; itc.i, itc.d, itr.i, itr.d; epc; instr +ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF +ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF +ITR; itr.i; epc; instr +ITR; ptr.i; itc.i, itr.i; impliedF +ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none +ITR; ptr.i; epc; instr +memory; IC:mem-writers; IC:mem-readers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific +PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC+3 Section 12.1.1 +PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR+12, IC:mov-to-PR+12; none +PR%, % in 1 - 15; IC:pr-writers+1, IC:mov-to-PR-allreg+7; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 1 - 15; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 1 - 15; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7; IC:pr-readers-br+1; none +PR%, % in 16 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 16 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 16 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF +PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF +PSR.cpl; epc, br.ret, rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied +PSR.da; rfi; IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.db; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; data +PSR.dd; rfi; IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-readers+8, IC:fr-writers+8; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-writers+8, IC:fr-readers+8; data +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; br.ia; data +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; data +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.i; rfi; IC:mov-from-PSR; data +PSR.ia; rfi; IC:none; none +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA; data +PSR.id; rfi; IC:none; none +PSR.is; br.ia, rfi; IC:none; none +PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf; data +PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.lp; IC:mov-to-PSR-l; br.ret; data +PSR.lp; rfi; IC:mov-from-PSR, br.ret; data +PSR.mc; rfi; IC:mov-from-PSR; none +PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers, IC:probe-all; data +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ri; rfi; IC:none; none +PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data +PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; data +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-AR-ITC; data +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data +PSR.ss; rfi; IC:all; data +PSR.tb; IC:mov-to-PSR-l, rfi; IC:branches, chk, fchkf; data +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag; data +RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF diff --git a/opcodes/ia64-war.tbl b/opcodes/ia64-war.tbl new file mode 100644 index 0000000..8cdfac5 --- /dev/null +++ b/opcodes/ia64-war.tbl @@ -0,0 +1,2 @@ +Resource Name; Readers; Writers; Semantics of Dependency +PR63; IC:pr-readers-br+1; IC:mod-sched-brs; stop diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl new file mode 100644 index 0000000..c8a3365 --- /dev/null +++ b/opcodes/ia64-waw.tbl @@ -0,0 +1,128 @@ +Resource Name; Writers; Writers; Semantics of Dependency +ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF +AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none +AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none +AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none +AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none +AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF +AR[PFS]; br.call, brl.call; br.call, brl.call; none +AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none +AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none +CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF +CPUID#; IC:none; IC:none; none +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF +CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF +CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF +CR[IVR]; IC:none; IC:none; SC +CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF +CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; itr.d; impliedF +DTR; itr.d; ptr.d; impliedF +DTR; ptr.d; ptr.d; none +FR%, % in 0 - 1; IC:none; IC:none; none +FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF +GR0; IC:none; IC:none; none +GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITR; itr.i; itr.i, ptr.i; impliedF +ITR; ptr.i; ptr.i; none +memory; IC:mem-writers; IC:mem-writers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF +PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-writers+1; none +PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7; impliedF +PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF +PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.bn; bsw, rfi; bsw, rfi; impliedF +PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF +PSR.da; rfi; rfi; impliedF +PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.dd; rfi; rfi; impliedF +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ed; rfi; rfi; impliedF +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ia; rfi; rfi; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.id; rfi; rfi; impliedF +PSR.is; br.ia, rfi; br.ia, rfi; impliedF +PSR.it; rfi; rfi; impliedF +PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.mc; rfi; rfi; impliedF +PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ri; rfi; rfi; impliedF +PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ss; rfi; rfi; impliedF +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF diff --git a/opcodes/m10200-dis.c b/opcodes/m10200-dis.c new file mode 100644 index 0000000..bd9a258 --- /dev/null +++ b/opcodes/m10200-dis.c @@ -0,0 +1,341 @@ +/* Disassemble MN10200 instructions. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include + +#include "sysdep.h" +#include "opcode/mn10200.h" +#include "dis-asm.h" +#include "opintl.h" + +static void disassemble PARAMS ((bfd_vma, struct disassemble_info *, + unsigned long insn, unsigned long, + unsigned int)); + +int +print_insn_mn10200 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + unsigned long extension = 0; + unsigned int consume; + + /* First figure out how big the opcode is. */ + status = (*info->read_memory_func) (memaddr, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = *(unsigned char *) buffer; + + /* These are one byte insns. */ + if ((insn & 0xf0) == 0x00 + || (insn & 0xf0) == 0x10 + || (insn & 0xf0) == 0x20 + || (insn & 0xf0) == 0x30 + || ((insn & 0xf0) == 0x80 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || (insn & 0xf0) == 0x90 + || (insn & 0xf0) == 0xa0 + || (insn & 0xf0) == 0xb0 + || (insn & 0xff) == 0xeb + || (insn & 0xff) == 0xf6 + || (insn & 0xff) == 0xfe + || (insn & 0xff) == 0xff) + { + extension = 0; + consume = 1; + } + + /* These are two byte insns. */ + else if ((insn & 0xf0) == 0x40 + || (insn & 0xf0) == 0x50 + || (insn & 0xf0) == 0x60 + || (insn & 0xf0) == 0x70 + || (insn & 0xf0) == 0x80 + || (insn & 0xfc) == 0xd0 + || (insn & 0xfc) == 0xd4 + || (insn & 0xfc) == 0xd8 + || (insn & 0xfc) == 0xe0 + || (insn & 0xfc) == 0xe4 + || (insn & 0xff) == 0xe8 + || (insn & 0xff) == 0xe9 + || (insn & 0xff) == 0xea + || (insn & 0xff) == 0xf0 + || (insn & 0xff) == 0xf1 + || (insn & 0xff) == 0xf2 + || (insn & 0xff) == 0xf3) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + consume = 2; + } + + /* These are three byte insns with a 16bit operand in little + endian form. */ + else if ((insn & 0xf0) == 0xc0 + || (insn & 0xfc) == 0xdc + || (insn & 0xfc) == 0xec + || (insn & 0xff) == 0xf8 + || (insn & 0xff) == 0xf9 + || (insn & 0xff) == 0xfa + || (insn & 0xff) == 0xfb + || (insn & 0xff) == 0xfc + || (insn & 0xff) == 0xfd) + { + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn <<= 16; + insn |= bfd_getl16 (buffer); + extension = 0; + consume = 3; + } + /* These are three byte insns too, but we don't have to mess with + endianness stuff. */ + else if ((insn & 0xff) == 0xf5) + { + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn <<= 16; + insn |= bfd_getb16 (buffer); + extension = 0; + consume = 3; + } + + /* These are four byte insns. */ + else if ((insn & 0xff) == 0xf7) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 16; + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= bfd_getl16 (buffer); + extension = 0; + consume = 4; + } + + /* These are five byte insns. */ + else if ((insn & 0xff) == 0xf4) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 16; + + status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= (*(unsigned char *)buffer << 8) & 0xff00; + + status = (*info->read_memory_func) (memaddr + 3, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= (*(unsigned char *)buffer) & 0xff; + + status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + extension = (*(unsigned char *)buffer) & 0xff; + consume = 5; + } + else + { + (*info->fprintf_func) (info->stream, _("unknown\t0x%02x"), insn); + return 1; + } + + disassemble (memaddr, info, insn, extension, consume); + + return consume; +} + +static void +disassemble (memaddr, info, insn, extension, size) + bfd_vma memaddr; + struct disassemble_info *info; + unsigned long insn; + unsigned long extension; + unsigned int size; +{ + struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes; + const struct mn10200_operand *operand; + int match = 0; + + /* Find the opcode. */ + while (op->name) + { + int mysize, extra_shift; + + if (op->format == FMT_1) + mysize = 1; + else if (op->format == FMT_2 + || op->format == FMT_4) + mysize = 2; + else if (op->format == FMT_3 + || op->format == FMT_5) + mysize = 3; + else if (op->format == FMT_6) + mysize = 4; + else if (op->format == FMT_7) + mysize = 5; + else + abort (); + + if (op->format == FMT_2 || op->format == FMT_5) + extra_shift = 8; + else if (op->format == FMT_3 + || op->format == FMT_6 + || op->format == FMT_7) + extra_shift = 16; + else + extra_shift = 0; + + if ((op->mask & insn) == op->opcode + && size == (unsigned int) mysize) + { + const unsigned char *opindex_ptr; + unsigned int nocomma; + int paren = 0; + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + + /* Now print the operands. */ + for (opindex_ptr = op->operands, nocomma = 1; + *opindex_ptr != 0; + opindex_ptr++) + { + unsigned long value; + + operand = &mn10200_operands[*opindex_ptr]; + + if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0) + { + value = (insn & 0xffff) << 8; + value |= extension; + } + else + { + value = ((insn >> (operand->shift)) + & ((1L << operand->bits) - 1L)); + } + + if ((operand->flags & MN10200_OPERAND_SIGNED) != 0) + value = ((long)(value << (32 - operand->bits)) + >> (32 - operand->bits)); + + if (!nocomma + && (!paren + || ((operand->flags & MN10200_OPERAND_PAREN) == 0))) + (*info->fprintf_func) (info->stream, ","); + + nocomma = 0; + + if ((operand->flags & MN10200_OPERAND_DREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "d%d", value); + } + + else if ((operand->flags & MN10200_OPERAND_AREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "a%d", value); + } + + else if ((operand->flags & MN10200_OPERAND_PSW) != 0) + (*info->fprintf_func) (info->stream, "psw"); + + else if ((operand->flags & MN10200_OPERAND_MDR) != 0) + (*info->fprintf_func) (info->stream, "mdr"); + + else if ((operand->flags & MN10200_OPERAND_PAREN) != 0) + { + if (paren) + (*info->fprintf_func) (info->stream, ")"); + else + { + (*info->fprintf_func) (info->stream, "("); + nocomma = 1; + } + paren = !paren; + } + + else if ((operand->flags & MN10200_OPERAND_PCREL) != 0) + (*info->print_address_func) ((value + memaddr + mysize) & 0xffffff, info); + + else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0) + (*info->print_address_func) (value, info); + + else + (*info->fprintf_func) (info->stream, "%ld", value); + } + /* All done. */ + break; + } + op++; + } + + if (!match) + { + (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); + } +} diff --git a/opcodes/m10200-opc.c b/opcodes/m10200-opc.c new file mode 100644 index 0000000..ca56503 --- /dev/null +++ b/opcodes/m10200-opc.c @@ -0,0 +1,360 @@ +/* Assemble Matsushita MN10200 instructions. + Copyright 1996, 1997, 2000 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "opcode/mn10200.h" + + +const struct mn10200_operand mn10200_operands[] = { +#define UNUSED 0 + {0, 0, 0}, + +/* dn register in the first register operand position. */ +#define DN0 (UNUSED+1) + {2, 0, MN10200_OPERAND_DREG}, + +/* dn register in the second register operand position. */ +#define DN1 (DN0+1) + {2, 2, MN10200_OPERAND_DREG}, + +/* dm register in the first register operand position. */ +#define DM0 (DN1+1) + {2, 0, MN10200_OPERAND_DREG}, + +/* dm register in the second register operand position. */ +#define DM1 (DM0+1) + {2, 2, MN10200_OPERAND_DREG}, + +/* an register in the first register operand position. */ +#define AN0 (DM1+1) + {2, 0, MN10200_OPERAND_AREG}, + +/* an register in the second register operand position. */ +#define AN1 (AN0+1) + {2, 2, MN10200_OPERAND_AREG}, + +/* am register in the first register operand position. */ +#define AM0 (AN1+1) + {2, 0, MN10200_OPERAND_AREG}, + +/* am register in the second register operand position. */ +#define AM1 (AM0+1) + {2, 2, MN10200_OPERAND_AREG}, + +/* 8 bit unsigned immediate which may promote to a 16bit + unsigned immediate. */ +#define IMM8 (AM1+1) + {8, 0, MN10200_OPERAND_PROMOTE}, + +/* 16 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM16 (IMM8+1) + {16, 0, MN10200_OPERAND_PROMOTE}, + +/* 16 bit pc-relative immediate which may promote to a 16bit + pc-relative immediate. */ +#define IMM16_PCREL (IMM16+1) + {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED}, + +/* 16bit unsigned dispacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM16_MEM (IMM16_PCREL+1) + {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR}, + +/* 24 immediate, low 16 bits in the main instruction + word, 8 in the extension word. */ + +#define IMM24 (IMM16_MEM+1) + {24, 0, MN10200_OPERAND_EXTENDED}, + +/* 32bit pc-relative offset. */ +#define IMM24_PCREL (IMM24+1) + {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED}, + +/* 32bit memory offset. */ +#define IMM24_MEM (IMM24_PCREL+1) + {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR}, + +/* Processor status word. */ +#define PSW (IMM24_MEM+1) + {0, 0, MN10200_OPERAND_PSW}, + +/* MDR register. */ +#define MDR (PSW+1) + {0, 0, MN10200_OPERAND_MDR}, + +/* Index register. */ +#define DI (MDR+1) + {2, 4, MN10200_OPERAND_DREG}, + +/* 8 bit signed displacement, may promote to 16bit signed dispacement. */ +#define SD8 (DI+1) + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 16 bit signed displacement, may promote to 32bit dispacement. */ +#define SD16 (SD8+1) + {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 8 bit pc-relative displacement. */ +#define SD8N_PCREL (SD16+1) + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, + +/* 8 bit signed immediate which may promote to 16bit signed immediate. */ +#define SIMM8 (SD8N_PCREL+1) + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 16 bit signed immediate which may promote to 32bit immediate. */ +#define SIMM16 (SIMM8+1) + {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 16 bit signed immediate which may not promote. */ +#define SIMM16N (SIMM16+1) + {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK}, + +/* Either an open paren or close paren. */ +#define PAREN (SIMM16N+1) + {0, 0, MN10200_OPERAND_PAREN}, + +/* dn register that appears in the first and second register positions. */ +#define DN01 (PAREN+1) + {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED}, + +/* an register that appears in the first and second register positions. */ +#define AN01 (DN01+1) + {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED}, +} ; + +#define MEM(ADDR) PAREN, ADDR, PAREN +#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct mn10200_opcode mn10200_opcodes[] = { +{ "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, +{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, +{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, +{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}}, +{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}}, +{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}}, +{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}}, +{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}}, +{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}}, +{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}}, +{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, +{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, +{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, +{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}}, +{ "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}}, +{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}}, +{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}}, +{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}}, +{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}}, +{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}}, +{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}}, +{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}}, +{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, +{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, +{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, +{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, +{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, +{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}}, +{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}}, +{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}}, +{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}}, +{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}}, +{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}}, +{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}}, +{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}}, +{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}}, +{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}}, + +{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, +{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, +{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, +{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, + +{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, +{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, +{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, +{ "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}}, +{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, +{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, +{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, +{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, +{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, +{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, + +{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}}, +{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, +{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, +{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, +{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, + +{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}}, +{ "extx", 0xb0, 0xfc, FMT_1, {DN0}}, +{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}}, +{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}}, +{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}}, + +{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}}, +{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}}, +{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}}, +{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, +{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, +{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, +{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}}, +{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}}, +{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}}, +{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, + +{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}}, +{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}}, +{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}}, +{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}}, +{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}}, +{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, +{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}}, + +{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}}, +{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}}, + +{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}}, + +{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}}, +{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}}, +{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}}, +{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, +{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, +{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}}, +{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, + +{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}}, +{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}}, +{ "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, +{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}}, +{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}}, +{ "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, +{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}}, +{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}}, + +{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}}, +{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}}, +{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}}, +{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}}, + +{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}}, +{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, +{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, + +{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}}, + +{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}}, + +{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}}, +{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}}, +{ "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, +{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}}, +{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}}, +{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, + +{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}}, + +{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}}, +{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}}, + +/* Extension. We need some instruction to trigger "emulated syscalls" + for our simulator. */ +{ "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}}, + +/* Extension. When talking to the simulator, gdb requires some instruction + that will trigger a "breakpoint" (really just an instruction that isn't + otherwise used by the tools. This instruction must be the same size + as the smallest instruction on the target machine. In the case of the + mn10x00 the "break" instruction must be one byte. 0xff is available on + both mn10x00 architectures. */ +{ "break", 0xff, 0xff, FMT_1, {UNUSED}}, + +{ 0, 0, 0, 0, {0}}, + +} ; + +const int mn10200_num_opcodes = + sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]); + + diff --git a/opcodes/m10300-dis.c b/opcodes/m10300-dis.c new file mode 100644 index 0000000..a8d4b51 --- /dev/null +++ b/opcodes/m10300-dis.c @@ -0,0 +1,687 @@ +/* Disassemble MN10300 instructions. + Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include + +#include "sysdep.h" +#include "opcode/mn10300.h" +#include "dis-asm.h" +#include "opintl.h" + +static void disassemble PARAMS ((bfd_vma, struct disassemble_info *, + unsigned long insn, unsigned int)); + +#define HAVE_AM33 (info->mach == AM33) +#define HAVE_AM30 (info->mach == AM30) + +int +print_insn_mn10300 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + unsigned int consume; + + /* First figure out how big the opcode is. */ + status = (*info->read_memory_func) (memaddr, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = *(unsigned char *) buffer; + + /* These are one byte insns. */ + if ((insn & 0xf3) == 0x00 + || (insn & 0xf0) == 0x10 + || (insn & 0xfc) == 0x3c + || (insn & 0xf3) == 0x41 + || (insn & 0xf3) == 0x40 + || (insn & 0xfc) == 0x50 + || (insn & 0xfc) == 0x54 + || (insn & 0xf0) == 0x60 + || (insn & 0xf0) == 0x70 + || ((insn & 0xf0) == 0x80 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0x90 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0xa0 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0xb0 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || (insn & 0xff) == 0xcb + || (insn & 0xfc) == 0xd0 + || (insn & 0xfc) == 0xd4 + || (insn & 0xfc) == 0xd8 + || (insn & 0xf0) == 0xe0 + || (insn & 0xff) == 0xff) + { + consume = 1; + } + + /* These are two byte insns. */ + else if ((insn & 0xf0) == 0x80 + || (insn & 0xf0) == 0x90 + || (insn & 0xf0) == 0xa0 + || (insn & 0xf0) == 0xb0 + || (insn & 0xfc) == 0x20 + || (insn & 0xfc) == 0x28 + || (insn & 0xf3) == 0x43 + || (insn & 0xf3) == 0x42 + || (insn & 0xfc) == 0x58 + || (insn & 0xfc) == 0x5c + || ((insn & 0xf0) == 0xc0 + && (insn & 0xff) != 0xcb + && (insn & 0xff) != 0xcc + && (insn & 0xff) != 0xcd) + || (insn & 0xff) == 0xf0 + || (insn & 0xff) == 0xf1 + || (insn & 0xff) == 0xf2 + || (insn & 0xff) == 0xf3 + || (insn & 0xff) == 0xf4 + || (insn & 0xff) == 0xf5 + || (insn & 0xff) == 0xf6) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + consume = 2; + } + + /* These are three byte insns. */ + else if ((insn & 0xff) == 0xf8 + || (insn & 0xff) == 0xcc + || (insn & 0xff) == 0xf9 + || (insn & 0xf3) == 0x01 + || (insn & 0xf3) == 0x02 + || (insn & 0xf3) == 0x03 + || (insn & 0xfc) == 0x24 + || (insn & 0xfc) == 0x2c + || (insn & 0xfc) == 0x30 + || (insn & 0xfc) == 0x34 + || (insn & 0xfc) == 0x38 + || (insn & 0xff) == 0xde + || (insn & 0xff) == 0xdf + || (insn & 0xff) == 0xf9 + || (insn & 0xff) == 0xcc) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 8; + status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= *(unsigned char *) buffer; + consume = 3; + } + + /* These are four byte insns. */ + else if ((insn & 0xff) == 0xfa + || (insn & 0xff) == 0xf7 + || (insn & 0xff) == 0xfb) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + consume = 4; + } + + /* These are five byte insns. */ + else if ((insn & 0xff) == 0xcd + || (insn & 0xff) == 0xdc) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + consume = 5; + } + + /* These are six byte insns. */ + else if ((insn & 0xff) == 0xfd + || (insn & 0xff) == 0xfc) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + consume = 6; + } + + /* Else its a seven byte insns (in theory). */ + else + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + consume = 7; + } + + disassemble (memaddr, info, insn, consume); + + return consume; +} + +static void +disassemble (memaddr, info, insn, size) + bfd_vma memaddr; + struct disassemble_info *info; + unsigned long insn; + unsigned int size; +{ + struct mn10300_opcode *op = (struct mn10300_opcode *)mn10300_opcodes; + const struct mn10300_operand *operand; + bfd_byte buffer[4]; + unsigned long extension = 0; + int status, match = 0; + + /* Find the opcode. */ + while (op->name) + { + int mysize, extra_shift; + + if (op->format == FMT_S0) + mysize = 1; + else if (op->format == FMT_S1 + || op->format == FMT_D0) + mysize = 2; + else if (op->format == FMT_S2 + || op->format == FMT_D1) + mysize = 3; + else if (op->format == FMT_S4) + mysize = 5; + else if (op->format == FMT_D2) + mysize = 4; + else if (op->format == FMT_D4) + mysize = 6; + else if (op->format == FMT_D6) + mysize = 3; + else if (op->format == FMT_D7 || op->format == FMT_D10) + mysize = 4; + else if (op->format == FMT_D8) + mysize = 6; + else if (op->format == FMT_D9) + mysize = 7; + else + mysize = 7; + + if ((op->mask & insn) == op->opcode + && size == (unsigned int) mysize + && (op->machine == 0 + || (op->machine == AM33 && HAVE_AM33) + || (op->machine == AM30 && HAVE_AM30))) + { + const unsigned char *opindex_ptr; + unsigned int nocomma; + int paren = 0; + + if (op->format == FMT_D1 || op->format == FMT_S1) + extra_shift = 8; + else if (op->format == FMT_D2 || op->format == FMT_D4 + || op->format == FMT_S2 || op->format == FMT_S4 + || op->format == FMT_S6 || op->format == FMT_D5) + extra_shift = 16; + else if (op->format == FMT_D7 + || op->format == FMT_D8 + || op->format == FMT_D9) + extra_shift = 8; + else + extra_shift = 0; + + if (size == 1 || size == 2) + { + extension = 0; + } + else if (size == 3 + && (op->format == FMT_D1 + || op->opcode == 0xdf0000 + || op->opcode == 0xde0000)) + { + extension = 0; + } + else if (size == 3 + && op->format == FMT_D6) + { + extension = 0; + } + else if (size == 3) + { + insn &= 0xff0000; + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + + insn |= bfd_getl16 (buffer); + extension = 0; + } + else if (size == 4 + && (op->opcode == 0xfaf80000 + || op->opcode == 0xfaf00000 + || op->opcode == 0xfaf40000)) + { + extension = 0; + } + else if (size == 4 + && (op->format == FMT_D7 + || op->format == FMT_D10)) + { + extension = 0; + } + else if (size == 4) + { + insn &= 0xffff0000; + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + + insn |= bfd_getl16 (buffer); + extension = 0; + } + else if (size == 5 && op->opcode == 0xdc000000) + { + unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xff000000; + insn |= (temp & 0xffffff00) >> 8; + extension = temp & 0xff; + } + else if (size == 5) + { + unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl16 (buffer); + + insn &= 0xff0000ff; + insn |= temp << 8; + + status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = *(unsigned char *) buffer; + } + else if (size == 6 && op->format == FMT_D8) + { + insn &= 0xffffff00; + status = (*info->read_memory_func) (memaddr + 5, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + insn |= *(unsigned char *) buffer; + + status = (*info->read_memory_func) (memaddr + 3, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = bfd_getl16 (buffer); + } + else if (size == 6) + { + unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xffff0000; + insn |= (temp >> 16) & 0xffff; + extension = temp & 0xffff; + } + else if (size == 7 && op->format == FMT_D9) + { + insn &= 0xffffff00; + status = (*info->read_memory_func) (memaddr + 3, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = bfd_getl32 (buffer); + insn |= (extension & 0xff000000) >> 24; + extension &= 0xffffff; + } + else if (size == 7 && op->opcode == 0xdd000000) + { + unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xff000000; + insn |= (temp >> 8) & 0xffffff; + extension = (temp & 0xff) << 16; + + status = (*info->read_memory_func) (memaddr + 5, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension |= bfd_getb16 (buffer); + } + else if (size == 7) + { + unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xffff0000; + insn |= (temp >> 16) & 0xffff; + extension = (temp & 0xffff) << 8; + + status = (*info->read_memory_func) (memaddr + 6, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension |= *(unsigned char *) buffer; + } + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + + /* Now print the operands. */ + for (opindex_ptr = op->operands, nocomma = 1; + *opindex_ptr != 0; + opindex_ptr++) + { + unsigned long value; + + operand = &mn10300_operands[*opindex_ptr]; + + /* If this operand is a PLUS (autoincrement), then do not emit + a comma before emitting the plus. */ + if ((operand->flags & MN10300_OPERAND_PLUS) != 0) + nocomma = 1; + + if ((operand->flags & MN10300_OPERAND_SPLIT) != 0) + { + unsigned long temp; + value = insn & ((1 << operand->bits) - 1); + value <<= (32 - operand->bits); + temp = extension >> operand->shift; + temp &= ((1 << (32 - operand->bits)) - 1); + value |= temp; + value = ((value ^ (((unsigned long) 1) << 31)) + - (((unsigned long) 1) << 31)); + } + else if ((operand->flags & MN10300_OPERAND_24BIT) != 0) + { + unsigned long temp; + value = insn & ((1 << operand->bits) - 1); + value <<= (24 - operand->bits); + temp = extension >> operand->shift; + temp &= ((1 << (24 - operand->bits)) - 1); + value |= temp; + if ((operand->flags & MN10300_OPERAND_SIGNED) != 0) + value = ((value & 0xffffff) ^ 0x800000) - 0x800000; + } + else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0) + { + value = ((extension >> (operand->shift)) + & ((1 << operand->bits) - 1)); + } + else + { + value = ((insn >> (operand->shift)) + & ((1 << operand->bits) - 1)); + } + + if ((operand->flags & MN10300_OPERAND_SIGNED) != 0 + /* These are properly extended by the code above. */ + && ((operand->flags & MN10300_OPERAND_24BIT) == 0)) + value = ((value ^ (((unsigned long) 1) << (operand->bits - 1))) + - (((unsigned long) 1) << (operand->bits - 1))); + + if (!nocomma + && (!paren + || ((operand->flags & MN10300_OPERAND_PAREN) == 0))) + (*info->fprintf_func) (info->stream, ","); + + nocomma = 0; + + if ((operand->flags & MN10300_OPERAND_DREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "d%d", (int) value); + } + + else if ((operand->flags & MN10300_OPERAND_AREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "a%d", (int) value); + } + + else if ((operand->flags & MN10300_OPERAND_SP) != 0) + (*info->fprintf_func) (info->stream, "sp"); + + else if ((operand->flags & MN10300_OPERAND_PSW) != 0) + (*info->fprintf_func) (info->stream, "psw"); + + else if ((operand->flags & MN10300_OPERAND_MDR) != 0) + (*info->fprintf_func) (info->stream, "mdr"); + + else if ((operand->flags & MN10300_OPERAND_RREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + if (value < 8) + (*info->fprintf_func) (info->stream, "r%d", (int) value); + else if (value < 12) + (*info->fprintf_func) (info->stream, "a%d", (int) value - 8); + else + (*info->fprintf_func) (info->stream, "d%d", (int) value - 12); + } + + else if ((operand->flags & MN10300_OPERAND_XRREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + if (value == 0) + (*info->fprintf_func) (info->stream, "sp", value); + else + (*info->fprintf_func) (info->stream, "xr%d", (int) value); + } + + else if ((operand->flags & MN10300_OPERAND_USP) != 0) + (*info->fprintf_func) (info->stream, "usp"); + + else if ((operand->flags & MN10300_OPERAND_SSP) != 0) + (*info->fprintf_func) (info->stream, "ssp"); + + else if ((operand->flags & MN10300_OPERAND_MSP) != 0) + (*info->fprintf_func) (info->stream, "msp"); + + else if ((operand->flags & MN10300_OPERAND_PC) != 0) + (*info->fprintf_func) (info->stream, "pc"); + + else if ((operand->flags & MN10300_OPERAND_EPSW) != 0) + (*info->fprintf_func) (info->stream, "epsw"); + + else if ((operand->flags & MN10300_OPERAND_PLUS) != 0) + (*info->fprintf_func) (info->stream, "+"); + + else if ((operand->flags & MN10300_OPERAND_PAREN) != 0) + { + if (paren) + (*info->fprintf_func) (info->stream, ")"); + else + { + (*info->fprintf_func) (info->stream, "("); + nocomma = 1; + } + paren = !paren; + } + + else if ((operand->flags & MN10300_OPERAND_PCREL) != 0) + (*info->print_address_func) ((long) value + memaddr, info); + + else if ((operand->flags & MN10300_OPERAND_MEMADDR) != 0) + (*info->print_address_func) (value, info); + + else if ((operand->flags & MN10300_OPERAND_REG_LIST) != 0) + { + int comma = 0; + + (*info->fprintf_func) (info->stream, "["); + if (value & 0x80) + { + (*info->fprintf_func) (info->stream, "d2"); + comma = 1; + } + + if (value & 0x40) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "d3"); + comma = 1; + } + + if (value & 0x20) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "a2"); + comma = 1; + } + + if (value & 0x10) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "a3"); + comma = 1; + } + + if (value & 0x08) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "other"); + comma = 1; + } + + if (value & 0x04) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "exreg0"); + comma = 1; + } + if (value & 0x02) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "exreg1"); + comma = 1; + } + if (value & 0x01) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "exother"); + comma = 1; + } + (*info->fprintf_func) (info->stream, "]"); + } + + else + (*info->fprintf_func) (info->stream, "%ld", (long) value); + } + /* All done. */ + break; + } + op++; + } + + if (!match) + { + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn); + } +} diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c new file mode 100644 index 0000000..84014e1 --- /dev/null +++ b/opcodes/m10300-opc.c @@ -0,0 +1,1427 @@ +/* Assemble Matsushita MN10300 instructions. + Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file is formatted at > 80 columns. Attempting to read it on a + screeen with less than 80 columns will be difficult. */ +#include "sysdep.h" +#include "opcode/mn10300.h" + + +const struct mn10300_operand mn10300_operands[] = { +#define UNUSED 0 + {0, 0, 0}, + +/* dn register in the first register operand position. */ +#define DN0 (UNUSED+1) + {2, 0, MN10300_OPERAND_DREG}, + +/* dn register in the second register operand position. */ +#define DN1 (DN0+1) + {2, 2, MN10300_OPERAND_DREG}, + +/* dn register in the third register operand position. */ +#define DN2 (DN1+1) + {2, 4, MN10300_OPERAND_DREG}, + +/* dm register in the first register operand position. */ +#define DM0 (DN2+1) + {2, 0, MN10300_OPERAND_DREG}, + +/* dm register in the second register operand position. */ +#define DM1 (DM0+1) + {2, 2, MN10300_OPERAND_DREG}, + +/* dm register in the third register operand position. */ +#define DM2 (DM1+1) + {2, 4, MN10300_OPERAND_DREG}, + +/* an register in the first register operand position. */ +#define AN0 (DM2+1) + {2, 0, MN10300_OPERAND_AREG}, + +/* an register in the second register operand position. */ +#define AN1 (AN0+1) + {2, 2, MN10300_OPERAND_AREG}, + +/* an register in the third register operand position. */ +#define AN2 (AN1+1) + {2, 4, MN10300_OPERAND_AREG}, + +/* am register in the first register operand position. */ +#define AM0 (AN2+1) + {2, 0, MN10300_OPERAND_AREG}, + +/* am register in the second register operand position. */ +#define AM1 (AM0+1) + {2, 2, MN10300_OPERAND_AREG}, + +/* am register in the third register operand position. */ +#define AM2 (AM1+1) + {2, 4, MN10300_OPERAND_AREG}, + +/* 8 bit unsigned immediate which may promote to a 16bit + unsigned immediate. */ +#define IMM8 (AM2+1) + {8, 0, MN10300_OPERAND_PROMOTE}, + +/* 16 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM16 (IMM8+1) + {16, 0, MN10300_OPERAND_PROMOTE}, + +/* 16 bit pc-relative immediate which may promote to a 16bit + pc-relative immediate. */ +#define IMM16_PCREL (IMM16+1) + {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, + +/* 16bit unsigned displacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM16_MEM (IMM16_PCREL+1) + {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, + +/* 32bit immediate, high 16 bits in the main instruction + word, 16bits in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32 (IMM16_MEM+1) + {16, 0, MN10300_OPERAND_SPLIT}, + +/* 32bit pc-relative offset. */ +#define IMM32_PCREL (IMM32+1) + {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, + +/* 32bit memory offset. */ +#define IMM32_MEM (IMM32_PCREL+1) + {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, + +/* 32bit immediate, high 16 bits in the main instruction + word, 16bits in the extension word, low 16bits are left + shifted 8 places. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_LOWSHIFT8 (IMM32_MEM+1) + {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, + +/* 32bit immediate, high 24 bits in the main instruction + word, 8 in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1) + {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, + +/* 32bit immediate, high 24 bits in the main instruction + word, 8 in the extension word, low 8 bits are left + shifted 16 places. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) + {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, + +/* Stack pointer. */ +#define SP (IMM32_HIGH24_LOWSHIFT16+1) + {8, 0, MN10300_OPERAND_SP}, + +/* Processor status word. */ +#define PSW (SP+1) + {0, 0, MN10300_OPERAND_PSW}, + +/* MDR register. */ +#define MDR (PSW+1) + {0, 0, MN10300_OPERAND_MDR}, + +/* Index register. */ +#define DI (MDR+1) + {2, 2, MN10300_OPERAND_DREG}, + +/* 8 bit signed displacement, may promote to 16bit signed displacement. */ +#define SD8 (DI+1) + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 16 bit signed displacement, may promote to 32bit displacement. */ +#define SD16 (SD8+1) + {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 8 bit signed displacement that can not promote. */ +#define SD8N (SD16+1) + {8, 0, MN10300_OPERAND_SIGNED}, + +/* 8 bit pc-relative displacement. */ +#define SD8N_PCREL (SD8N+1) + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, + +/* 8 bit signed displacement shifted left 8 bits in the instruction. */ +#define SD8N_SHIFT8 (SD8N_PCREL+1) + {8, 8, MN10300_OPERAND_SIGNED}, + +/* 8 bit signed immediate which may promote to 16bit signed immediate. */ +#define SIMM8 (SD8N_SHIFT8+1) + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 16 bit signed immediate which may promote to 32bit immediate. */ +#define SIMM16 (SIMM8+1) + {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* Either an open paren or close paren. */ +#define PAREN (SIMM16+1) + {0, 0, MN10300_OPERAND_PAREN}, + +/* dn register that appears in the first and second register positions. */ +#define DN01 (PAREN+1) + {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED}, + +/* an register that appears in the first and second register positions. */ +#define AN01 (DN01+1) + {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED}, + +/* 16bit pc-relative displacement which may promote to 32bit pc-relative + displacement. */ +#define D16_SHIFT (AN01+1) + {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, + +/* 8 bit immediate found in the extension word. */ +#define IMM8E (D16_SHIFT+1) + {8, 0, MN10300_OPERAND_EXTENDED}, + +/* Register list found in the extension word shifted 8 bits left. */ +#define REGSE_SHIFT8 (IMM8E+1) + {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST}, + +/* Register list shifted 8 bits left. */ +#define REGS_SHIFT8 (REGSE_SHIFT8 + 1) + {8, 8, MN10300_OPERAND_REG_LIST}, + +/* Reigster list. */ +#define REGS (REGS_SHIFT8+1) + {8, 0, MN10300_OPERAND_REG_LIST}, + +/* UStack pointer. */ +#define USP (REGS+1) + {0, 0, MN10300_OPERAND_USP}, + +/* SStack pointer. */ +#define SSP (USP+1) + {0, 0, MN10300_OPERAND_SSP}, + +/* MStack pointer. */ +#define MSP (SSP+1) + {0, 0, MN10300_OPERAND_MSP}, + +/* PC . */ +#define PC (MSP+1) + {0, 0, MN10300_OPERAND_PC}, + +/* 4 bit immediate for syscall. */ +#define IMM4 (PC+1) + {4, 0, 0}, + +/* Processor status word. */ +#define EPSW (IMM4+1) + {0, 0, MN10300_OPERAND_EPSW}, + +/* rn register in the first register operand position. */ +#define RN0 (EPSW+1) + {4, 0, MN10300_OPERAND_RREG}, + +/* rn register in the fourth register operand position. */ +#define RN2 (RN0+1) + {4, 4, MN10300_OPERAND_RREG}, + +/* rm register in the first register operand position. */ +#define RM0 (RN2+1) + {4, 0, MN10300_OPERAND_RREG}, + +/* rm register in the second register operand position. */ +#define RM1 (RM0+1) + {4, 2, MN10300_OPERAND_RREG}, + +/* rm register in the third register operand position. */ +#define RM2 (RM1+1) + {4, 4, MN10300_OPERAND_RREG}, + +#define RN02 (RM2+1) + {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED}, + +#define XRN0 (RN02+1) + {4, 0, MN10300_OPERAND_XRREG}, + +#define XRM2 (XRN0+1) + {4, 4, MN10300_OPERAND_XRREG}, + +/* + for autoincrement */ +#define PLUS (XRM2+1) + {0, 0, MN10300_OPERAND_PLUS}, + +#define XRN02 (PLUS+1) + {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED}, + +/* Ick */ +#define RD0 (XRN02+1) + {4, -8, MN10300_OPERAND_RREG}, + +#define RD2 (RD0+1) + {4, -4, MN10300_OPERAND_RREG}, + +/* 8 unsigned displacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM8_MEM (RD2+1) + {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, + +/* Index register. */ +#define RI (IMM8_MEM+1) + {4, 4, MN10300_OPERAND_RREG}, + +/* 24 bit signed displacement, may promote to 32bit displacement. */ +#define SD24 (RI+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 24 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM24 (SD24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, + +/* 24 bit signed immediate which may promote to a 32bit + signed immediate. */ +#define SIMM24 (IMM24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, + +/* 24bit unsigned displacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM24_MEM (SIMM24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, +/* 32bit immediate, high 8 bits in the main instruction + word, 24 in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH8 (IMM24_MEM+1) + {8, 0, MN10300_OPERAND_SPLIT}, + +/* Similarly, but a memory address. */ +#define IMM32_HIGH8_MEM (IMM32_HIGH8+1) + {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, + +/* rm register in the seventh register operand position. */ +#define RM6 (IMM32_HIGH8_MEM+1) + {4, 12, MN10300_OPERAND_RREG}, + +/* rm register in the fifth register operand position. */ +#define RN4 (RM6+1) + {4, 8, MN10300_OPERAND_RREG}, + +/* 4 bit immediate for dsp instructions. */ +#define IMM4_2 (RN4+1) + {4, 4, 0}, + +/* 4 bit immediate for dsp instructions. */ +#define SIMM4_2 (IMM4_2+1) + {4, 4, MN10300_OPERAND_SIGNED}, + +/* 4 bit immediate for dsp instructions. */ +#define SIMM4_6 (SIMM4_2+1) + {4, 12, MN10300_OPERAND_SIGNED}, + +} ; + +#define MEM(ADDR) PAREN, ADDR, PAREN +#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN +#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN +#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct mn10300_opcode mn10300_opcodes[] = { +{ "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, +{ "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, +{ "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, +{ "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, +{ "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}}, +{ "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}}, +{ "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}}, +{ "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}}, +{ "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}}, +{ "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}}, +{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, +{ "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}}, +{ "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, +{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, +{ "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}}, +{ "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}}, +{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, +{ "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}}, +{ "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, +{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, +{ "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}}, +{ "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}}, +{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, +{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, +{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, +{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, +{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, +{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, +{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, +{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, +{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, +{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, +{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, +{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, +{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, +{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, +{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, +{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, + +{ "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}}, +{ "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}}, +{ "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}}, +{ "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}}, +{ "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}}, +{ "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}}, +{ "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}}, +{ "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}}, +{ "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}}, +{ "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}}, +{ "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}}, +{ "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}}, +{ "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}}, +{ "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}}, +{ "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}}, +{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, +{ "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, +{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, +{ "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, +{ "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, +{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, +{ "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, +{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, +{ "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, +{ "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, +{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, +{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, +{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, +{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, +{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, +{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, +{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, +{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, +{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, +{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, +/* These must come after most of the other move instructions to avoid matching + a symbolic name with IMMxx operands. Ugh. */ +{ "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}}, +{ "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}}, +{ "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, +{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, +{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, +{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, +{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, +{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, +{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, +/* These non-promoting variants need to come after all the other memory + moves. */ +{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}}, +{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}}, +/* These are the same as the previous non-promoting versions. The am33 + does not have restrictions on the offsets used to load/store the stack + pointer. */ +{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, +{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, +/* These must come last so that we favor shorter move instructions for + loading immediates into d0-d3/a0-a3. */ +{ "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, XRN02}}, +{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, XRN02}}, +{ "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}}, +{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, + +{ "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, +{ "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, +{ "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, +{ "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, +{ "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, +{ "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, +{ "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, +{ "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, +{ "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, +{ "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, +{ "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, +{ "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, +{ "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, +{ "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, +{ "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, +{ "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, +{ "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, +{ "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, +{ "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, +{ "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, +{ "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, +{ "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, +{ "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, +{ "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, +{ "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, +{ "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, +{ "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, +{ "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}}, +{ "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, +{ "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, + +{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, +{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, +{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, +{ "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, +{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, +{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, +{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, +{ "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, +{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, +{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, +{ "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, +{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, +{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, +{ "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, +{ "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, +{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, +{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, +{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, +{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, +{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, +{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, +{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, +{ "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, +{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, +{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, +{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, +{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, +{ "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, +{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, +{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, +{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, +{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, +{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, +{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, + +{ "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, +{ "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, +{ "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, +{ "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, + +{ "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}}, +{ "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}}, +{ "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, +{ "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}}, +{ "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}}, +{ "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}}, +{ "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}}, +{ "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}}, +{ "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}}, +{ "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, +{ "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}}, +{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}}, +{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}}, +{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, +{ "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, +{ "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, +{ "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, +{ "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}}, +{ "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, +{ "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, +{ "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, +{ "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, +{ "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the + them to match last since they do not promote. */ +{ "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, +{ "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, + +{ "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, +{ "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, + +{ "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, +{ "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, + +{ "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}}, +{ "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, + +{ "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}}, +{ "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, + +{ "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}}, +{ "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, + +{ "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, + +{ "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}}, + +{ "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, +{ "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}}, +{ "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}}, +{ "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}}, +{ "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}}, +{ "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, +{ "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}}, +{ "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}}, + +{ "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, +{ "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, +{ "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}}, + +/* UDF instructions. */ +{ "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, + +{ "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}}, +{ "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}}, +{ "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, +{ "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, +{ "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, +{ "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, +{ "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, +{ "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, +{ "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}}, + +{ "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +/* Extension. We need some instruction to trigger "emulated syscalls" + for our simulator. */ +{ "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}}, +{ "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}}, + +/* Extension. When talking to the simulator, gdb requires some instruction + that will trigger a "breakpoint" (really just an instruction that isn't + otherwise used by the tools. This instruction must be the same size + as the smallest instruction on the target machine. In the case of the + mn10x00 the "break" instruction must be one byte. 0xff is available on + both mn10x00 architectures. */ +{ "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}}, + +{ "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +/* Ugh. Synthetic instructions. */ +{ "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, +{ "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, +{ "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, +{ "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, + +{ 0, 0, 0, 0, 0, 0, {0}}, + +} ; + +const int mn10300_num_opcodes = + sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]); + + diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c new file mode 100644 index 0000000..4abe187 --- /dev/null +++ b/opcodes/m32r-asm.c @@ -0,0 +1,753 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * parse_hash + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_slo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_ulo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); + +/* Handle '#' prefixes (i.e. skip over them). */ + +static const char * +parse_hash (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + const char **strp; + int opindex ATTRIBUTE_UNUSED; + unsigned long *valuep ATTRIBUTE_UNUSED; +{ + if (**strp == '#') + ++*strp; + return NULL; +} + +/* Handle shigh(), high(). */ + +static const char * +parse_hi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "high(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp, "shigh(", 6) == 0) + { + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (value >> 16) + (value & 0x8000 ? 1 : 0); + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in a signed context. Also handle sda(). + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_slo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "sda(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, + NULL, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in an unsigned context. + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_ulo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* -- */ + +const char * m32r_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +m32r_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case M32R_OPERAND_ACC : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_acc); + break; + case M32R_OPERAND_ACCD : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_accd); + break; + case M32R_OPERAND_ACCS : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_accs); + break; + case M32R_OPERAND_DCR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r1); + break; + case M32R_OPERAND_DISP16 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL, & value); + fields->f_disp16 = value; + } + break; + case M32R_OPERAND_DISP24 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL, & value); + fields->f_disp24 = value; + } + break; + case M32R_OPERAND_DISP8 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL, & value); + fields->f_disp8 = value; + } + break; + case M32R_OPERAND_DR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); + break; + case M32R_OPERAND_HASH : + errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, &junk); + break; + case M32R_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, &fields->f_hi16); + break; + case M32R_OPERAND_IMM1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_IMM1, &fields->f_imm1); + break; + case M32R_OPERAND_SCR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r2); + break; + case M32R_OPERAND_SIMM16 : + errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM16, &fields->f_simm16); + break; + case M32R_OPERAND_SIMM8 : + errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM8, &fields->f_simm8); + break; + case M32R_OPERAND_SLO16 : + errmsg = parse_slo16 (cd, strp, M32R_OPERAND_SLO16, &fields->f_simm16); + break; + case M32R_OPERAND_SR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); + break; + case M32R_OPERAND_SRC1 : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); + break; + case M32R_OPERAND_SRC2 : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); + break; + case M32R_OPERAND_UIMM16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM16, &fields->f_uimm16); + break; + case M32R_OPERAND_UIMM24 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL, & value); + fields->f_uimm24 = value; + } + break; + case M32R_OPERAND_UIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4); + break; + case M32R_OPERAND_UIMM5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5); + break; + case M32R_OPERAND_ULO16 : + errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const m32r_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +m32r_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + m32r_cgen_init_opcode_table (cd); + m32r_cgen_init_ibld_table (cd); + cd->parse_handlers = & m32r_cgen_parse_handlers[0]; + cd->parse_operand = m32r_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by m32r_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +m32r_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! m32r_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +m32r_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! m32r_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c new file mode 100644 index 0000000..de7bde4 --- /dev/null +++ b/opcodes/m32r-desc.c @@ -0,0 +1,1483 @@ +/* CPU data for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "m32r", MACH_M32R }, + { "m32rx", MACH_M32RX }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "m32r", ISA_M32R }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY PIPE_attr[] = +{ + { "NONE", PIPE_NONE }, + { "O", PIPE_O }, + { "S", PIPE_S }, + { "OS", PIPE_OS }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "FILL-SLOT", &bool_attr[0], &bool_attr[0] }, + { "SPECIAL", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA m32r_cgen_isa_table[] = { + { "m32r", 32, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH m32r_cgen_mach_table[] = { + { "m32r", "m32r", MACH_M32R, 0 }, + { "m32rx", "m32rx", MACH_M32RX, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] = +{ + { "fp", 13, {0, {0}}, 0, 0 }, + { "lr", 14, {0, {0}}, 0, 0 }, + { "sp", 15, {0, {0}}, 0, 0 }, + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32r_cgen_opval_gr_names = +{ + & m32r_cgen_opval_gr_names_entries[0], + 19, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] = +{ + { "psw", 0, {0, {0}}, 0, 0 }, + { "cbr", 1, {0, {0}}, 0, 0 }, + { "spi", 2, {0, {0}}, 0, 0 }, + { "spu", 3, {0, {0}}, 0, 0 }, + { "bpc", 6, {0, {0}}, 0, 0 }, + { "bbpsw", 8, {0, {0}}, 0, 0 }, + { "bbpc", 14, {0, {0}}, 0, 0 }, + { "cr0", 0, {0, {0}}, 0, 0 }, + { "cr1", 1, {0, {0}}, 0, 0 }, + { "cr2", 2, {0, {0}}, 0, 0 }, + { "cr3", 3, {0, {0}}, 0, 0 }, + { "cr4", 4, {0, {0}}, 0, 0 }, + { "cr5", 5, {0, {0}}, 0, 0 }, + { "cr6", 6, {0, {0}}, 0, 0 }, + { "cr7", 7, {0, {0}}, 0, 0 }, + { "cr8", 8, {0, {0}}, 0, 0 }, + { "cr9", 9, {0, {0}}, 0, 0 }, + { "cr10", 10, {0, {0}}, 0, 0 }, + { "cr11", 11, {0, {0}}, 0, 0 }, + { "cr12", 12, {0, {0}}, 0, 0 }, + { "cr13", 13, {0, {0}}, 0, 0 }, + { "cr14", 14, {0, {0}}, 0, 0 }, + { "cr15", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32r_cgen_opval_cr_names = +{ + & m32r_cgen_opval_cr_names_entries[0], + 23, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = +{ + { "a0", 0, {0, {0}}, 0, 0 }, + { "a1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32r_cgen_opval_h_accums = +{ + & m32r_cgen_opval_h_accums_entries[0], + 2, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY m32r_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & m32r_cgen_ifld_table[0]; +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & m32r_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & m32r_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */ + +static void +m32r_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & m32r_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & m32r_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (m32r_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = m32r_cgen_rebuild_tables; + m32r_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +m32r_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +m32r_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h new file mode 100644 index 0000000..b099730 --- /dev/null +++ b/opcodes/m32r-desc.h @@ -0,0 +1,234 @@ +/* CPU data header for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef M32R_CPU_H +#define M32R_CPU_H + +#define CGEN_ARCH m32r + +/* Given symbol S, return m32r_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) m32r##_cgen_##s +#else +#define CGEN_SYM(s) m32r/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_M32RBF +#define HAVE_CPU_M32RXF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 + +/* Enums. */ + +/* Enum declaration for insn format enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_10, OP1_11 + , OP1_12, OP1_13, OP1_14, OP1_15 +} INSN_OP1; + +/* Enum declaration for op2 enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_10, OP2_11 + , OP2_12, OP2_13, OP2_14, OP2_15 +} INSN_OP2; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 + , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 + , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 + , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 + , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum cr_names { + H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 + , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0 + , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4 + , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8 + , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12 + , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 +} CR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_M32R, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum pipe_attr { + PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS +} PIPE_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld m32r_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS + , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for m32r ifield types. */ +typedef enum ifield_type { + M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 + , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 + , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5 + , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8 + , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3 + , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67 + , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) M32R_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for m32r hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 + , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM + , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW + , HW_H_BBPSW, HW_H_LOCK, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31 + , CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for m32r operand types. */ +typedef enum cgen_operand_type { + M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 + , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 + , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16 + , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC + , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16 + , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24 + , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 26 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 11 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE + , CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD m32r_cgen_opval_gr_names; +extern CGEN_KEYWORD m32r_cgen_opval_cr_names; +extern CGEN_KEYWORD m32r_cgen_opval_h_accums; + + + + +#endif /* M32R_CPU_H */ diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c new file mode 100644 index 0000000..07560e1 --- /dev/null +++ b/opcodes/m32r-dis.c @@ -0,0 +1,678 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + +/* -- dis.c */ +static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + +/* Immediate values are prefixed with '#'. */ + +#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ + do \ + { \ + if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \ + (*info->fprintf_func) (info->stream, "#"); \ + } \ + while (0) + +/* Handle '#' prefixes as operands. */ + +static void +print_hash (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value ATTRIBUTE_UNUSED; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "#"); +} + +#undef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN my_print_insn + +static int +my_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buffer[CGEN_MAX_INSN_SIZE]; + char *buf = buffer; + int status; + int buflen = (pc & 3) == 0 ? 4 : 2; + + /* Read the base part of the insn. */ + + status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* 32 bit insn? */ + if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) + return print_insn (cd, pc, info, buf, buflen); + + /* Print the first insn. */ + if ((pc & 3) == 0) + { + if (print_insn (cd, pc, info, buf, 2) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + buf += 2; + } + + if (buf[0] & 0x80) + { + /* Parallel. */ + (*info->fprintf_func) (info->stream, " || "); + buf[0] &= 0x7f; + } + else + (*info->fprintf_func) (info->stream, " -> "); + + /* The "& 3" is to pass a consistent address. + Parallel insns arguably both begin on the word boundary. + Also, branch insns are calculated relative to the word boundary. */ + if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + + return (pc & 3) ? 2 : 4; +} + +/* -- */ + +void m32r_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case M32R_OPERAND_ACC : + print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0); + break; + case M32R_OPERAND_ACCD : + print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0); + break; + case M32R_OPERAND_ACCS : + print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0); + break; + case M32R_OPERAND_DCR : + print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0); + break; + case M32R_OPERAND_DISP16 : + print_address (cd, info, fields->f_disp16, 0|(1<f_disp24, 0|(1<f_disp8, 0|(1<f_r1, 0); + break; + case M32R_OPERAND_HASH : + print_hash (cd, info, 0, 0|(1<f_hi16, 0|(1<f_imm1, 0|(1<f_r2, 0); + break; + case M32R_OPERAND_SIMM16 : + print_normal (cd, info, fields->f_simm16, 0|(1<f_simm8, 0|(1<f_simm16, 0|(1<f_r2, 0); + break; + case M32R_OPERAND_SRC1 : + print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); + break; + case M32R_OPERAND_SRC2 : + print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); + break; + case M32R_OPERAND_UIMM16 : + print_normal (cd, info, fields->f_uimm16, 0|(1<f_uimm24, 0|(1<f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm16, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const m32r_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +m32r_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + m32r_cgen_init_opcode_table (cd); + m32r_cgen_init_ibld_table (cd); + cd->print_handlers = & m32r_cgen_print_handlers[0]; + cd->print_operand = m32r_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! m32r_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_m32r (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_m32r +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + m32r_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c new file mode 100644 index 0000000..ef1ee0e --- /dev/null +++ b/opcodes/m32r-ibld.c @@ -0,0 +1,1198 @@ +/* Instruction building/extraction support for m32r. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * m32r_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32R_OPERAND_ACC : + errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer); + break; + case M32R_OPERAND_ACCD : + errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer); + break; + case M32R_OPERAND_ACCS : + errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer); + break; + case M32R_OPERAND_DCR : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_DISP16 : + { + long value = fields->f_disp16; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp24; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp8; + value = ((int) (((value) - (((pc) & (-4))))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_r1, 0, 0, 4, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + errmsg = insert_normal (cd, fields->f_hi16, 0|(1<f_imm1; + value = ((value) - (1)); + errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer); + } + break; + case M32R_OPERAND_SCR : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_SIMM16 : + errmsg = insert_normal (cd, fields->f_simm16, 0|(1<f_simm8, 0|(1<f_simm16, 0|(1<f_r2, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_SRC1 : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_SRC2 : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM24 : + errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<f_uimm4, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM5 : + errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer); + break; + case M32R_OPERAND_ULO16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int m32r_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32R_OPERAND_ACC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc); + break; + case M32R_OPERAND_ACCD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd); + break; + case M32R_OPERAND_ACCS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs); + break; + case M32R_OPERAND_DCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); + break; + case M32R_OPERAND_DISP16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp16 = value; + } + break; + case M32R_OPERAND_DISP24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp24 = value; + } + break; + case M32R_OPERAND_DISP8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp8 = value; + } + break; + case M32R_OPERAND_DR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_hi16); + break; + case M32R_OPERAND_IMM1 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value); + value = ((value) + (1)); + fields->f_imm1 = value; + } + break; + case M32R_OPERAND_SCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); + break; + case M32R_OPERAND_SIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case M32R_OPERAND_SIMM8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm8); + break; + case M32R_OPERAND_SLO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case M32R_OPERAND_SR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); + break; + case M32R_OPERAND_SRC1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); + break; + case M32R_OPERAND_SRC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); + break; + case M32R_OPERAND_UIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); + break; + case M32R_OPERAND_UIMM24 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_uimm24); + break; + case M32R_OPERAND_UIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4); + break; + case M32R_OPERAND_UIMM5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5); + break; + case M32R_OPERAND_ULO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const m32r_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const m32r_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int m32r_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma m32r_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +m32r_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case M32R_OPERAND_ACC : + value = fields->f_acc; + break; + case M32R_OPERAND_ACCD : + value = fields->f_accd; + break; + case M32R_OPERAND_ACCS : + value = fields->f_accs; + break; + case M32R_OPERAND_DCR : + value = fields->f_r1; + break; + case M32R_OPERAND_DISP16 : + value = fields->f_disp16; + break; + case M32R_OPERAND_DISP24 : + value = fields->f_disp24; + break; + case M32R_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case M32R_OPERAND_DR : + value = fields->f_r1; + break; + case M32R_OPERAND_HASH : + value = 0; + break; + case M32R_OPERAND_HI16 : + value = fields->f_hi16; + break; + case M32R_OPERAND_IMM1 : + value = fields->f_imm1; + break; + case M32R_OPERAND_SCR : + value = fields->f_r2; + break; + case M32R_OPERAND_SIMM16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SIMM8 : + value = fields->f_simm8; + break; + case M32R_OPERAND_SLO16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SR : + value = fields->f_r2; + break; + case M32R_OPERAND_SRC1 : + value = fields->f_r1; + break; + case M32R_OPERAND_SRC2 : + value = fields->f_r2; + break; + case M32R_OPERAND_UIMM16 : + value = fields->f_uimm16; + break; + case M32R_OPERAND_UIMM24 : + value = fields->f_uimm24; + break; + case M32R_OPERAND_UIMM4 : + value = fields->f_uimm4; + break; + case M32R_OPERAND_UIMM5 : + value = fields->f_uimm5; + break; + case M32R_OPERAND_ULO16 : + value = fields->f_uimm16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +m32r_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case M32R_OPERAND_ACC : + value = fields->f_acc; + break; + case M32R_OPERAND_ACCD : + value = fields->f_accd; + break; + case M32R_OPERAND_ACCS : + value = fields->f_accs; + break; + case M32R_OPERAND_DCR : + value = fields->f_r1; + break; + case M32R_OPERAND_DISP16 : + value = fields->f_disp16; + break; + case M32R_OPERAND_DISP24 : + value = fields->f_disp24; + break; + case M32R_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case M32R_OPERAND_DR : + value = fields->f_r1; + break; + case M32R_OPERAND_HASH : + value = 0; + break; + case M32R_OPERAND_HI16 : + value = fields->f_hi16; + break; + case M32R_OPERAND_IMM1 : + value = fields->f_imm1; + break; + case M32R_OPERAND_SCR : + value = fields->f_r2; + break; + case M32R_OPERAND_SIMM16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SIMM8 : + value = fields->f_simm8; + break; + case M32R_OPERAND_SLO16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SR : + value = fields->f_r2; + break; + case M32R_OPERAND_SRC1 : + value = fields->f_r1; + break; + case M32R_OPERAND_SRC2 : + value = fields->f_r2; + break; + case M32R_OPERAND_UIMM16 : + value = fields->f_uimm16; + break; + case M32R_OPERAND_UIMM24 : + value = fields->f_uimm24; + break; + case M32R_OPERAND_UIMM4 : + value = fields->f_uimm4; + break; + case M32R_OPERAND_UIMM5 : + value = fields->f_uimm5; + break; + case M32R_OPERAND_ULO16 : + value = fields->f_uimm16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void m32r_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void m32r_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +m32r_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case M32R_OPERAND_ACC : + fields->f_acc = value; + break; + case M32R_OPERAND_ACCD : + fields->f_accd = value; + break; + case M32R_OPERAND_ACCS : + fields->f_accs = value; + break; + case M32R_OPERAND_DCR : + fields->f_r1 = value; + break; + case M32R_OPERAND_DISP16 : + fields->f_disp16 = value; + break; + case M32R_OPERAND_DISP24 : + fields->f_disp24 = value; + break; + case M32R_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case M32R_OPERAND_DR : + fields->f_r1 = value; + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + fields->f_hi16 = value; + break; + case M32R_OPERAND_IMM1 : + fields->f_imm1 = value; + break; + case M32R_OPERAND_SCR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SIMM16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case M32R_OPERAND_SLO16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case M32R_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; + case M32R_OPERAND_UIMM24 : + fields->f_uimm24 = value; + break; + case M32R_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case M32R_OPERAND_UIMM5 : + fields->f_uimm5 = value; + break; + case M32R_OPERAND_ULO16 : + fields->f_uimm16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +m32r_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case M32R_OPERAND_ACC : + fields->f_acc = value; + break; + case M32R_OPERAND_ACCD : + fields->f_accd = value; + break; + case M32R_OPERAND_ACCS : + fields->f_accs = value; + break; + case M32R_OPERAND_DCR : + fields->f_r1 = value; + break; + case M32R_OPERAND_DISP16 : + fields->f_disp16 = value; + break; + case M32R_OPERAND_DISP24 : + fields->f_disp24 = value; + break; + case M32R_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case M32R_OPERAND_DR : + fields->f_r1 = value; + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + fields->f_hi16 = value; + break; + case M32R_OPERAND_IMM1 : + fields->f_imm1 = value; + break; + case M32R_OPERAND_SCR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SIMM16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case M32R_OPERAND_SLO16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case M32R_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; + case M32R_OPERAND_UIMM24 : + fields->f_uimm24 = value; + break; + case M32R_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case M32R_OPERAND_UIMM5 : + fields->f_uimm5 = value; + break; + case M32R_OPERAND_ULO16 : + fields->f_uimm16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +m32r_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & m32r_cgen_insert_handlers[0]; + cd->extract_handlers = & m32r_cgen_extract_handlers[0]; + + cd->insert_operand = m32r_cgen_insert_operand; + cd->extract_operand = m32r_cgen_extract_operand; + + cd->get_int_operand = m32r_cgen_get_int_operand; + cd->set_int_operand = m32r_cgen_set_int_operand; + cd->get_vma_operand = m32r_cgen_get_vma_operand; + cd->set_vma_operand = m32r_cgen_set_vma_operand; +} diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c new file mode 100644 index 0000000..5b20f4d --- /dev/null +++ b/opcodes/m32r-opc.c @@ -0,0 +1,1714 @@ +/* Instruction opcode table for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & m32r_cgen_ifld_table[M32R_##f] +#else +#define F(f) & m32r_cgen_ifld_table[M32R_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_and3 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_or3 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addv3 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc8 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc24 = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqz = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpi = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpz = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div = { + 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jc = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ld24 = { + 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi16 = { + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_machi_a = { + 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvfachi = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvfachi_a = { + 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvfc = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvtachi = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvtachi_a = { + 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvtc = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_nop = { + 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rac_dsi = { + 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_seth = { + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slli = { + 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_st_d = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_trap = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_satb = { + 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) M32R_OPERAND_##op +#else +#define OPERAND(op) M32R_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xa0 } + }, +/* add3 $dr,$sr,$hash$slo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, + & ifmt_add3, { 0x80a00000 } + }, +/* and $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xc0 } + }, +/* and3 $dr,$sr,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, + & ifmt_and3, { 0x80c00000 } + }, +/* or $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xe0 } + }, +/* or3 $dr,$sr,$hash$ulo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, + & ifmt_or3, { 0x80e00000 } + }, +/* xor $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xd0 } + }, +/* xor3 $dr,$sr,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, + & ifmt_and3, { 0x80d00000 } + }, +/* addi $dr,$simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, + & ifmt_addi, { 0x4000 } + }, +/* addv $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x80 } + }, +/* addv3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x80800000 } + }, +/* addx $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x90 } + }, +/* bc.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7c00 } + }, +/* bc.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xfc000000 } + }, +/* beq $src1,$src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beq, { 0xb0000000 } + }, +/* beqz $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0800000 } + }, +/* bgez $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0b00000 } + }, +/* bgtz $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0d00000 } + }, +/* blez $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0c00000 } + }, +/* bltz $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0a00000 } + }, +/* bnez $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0900000 } + }, +/* bl.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7e00 } + }, +/* bl.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xfe000000 } + }, +/* bcl.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7800 } + }, +/* bcl.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xf8000000 } + }, +/* bnc.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7d00 } + }, +/* bnc.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xfd000000 } + }, +/* bne $src1,$src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beq, { 0xb0100000 } + }, +/* bra.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7f00 } + }, +/* bra.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xff000000 } + }, +/* bncl.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7900 } + }, +/* bncl.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xf9000000 } + }, +/* cmp $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x40 } + }, +/* cmpi $src2,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, + & ifmt_cmpi, { 0x80400000 } + }, +/* cmpu $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50 } + }, +/* cmpui $src2,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, + & ifmt_cmpi, { 0x80500000 } + }, +/* cmpeq $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x60 } + }, +/* cmpz $src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), 0 } }, + & ifmt_cmpz, { 0x70 } + }, +/* div $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90000000 } + }, +/* divu $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90100000 } + }, +/* rem $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90200000 } + }, +/* remu $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90300000 } + }, +/* divh $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90000010 } + }, +/* jc $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1cc0 } + }, +/* jnc $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1dc0 } + }, +/* jl $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1ec0 } + }, +/* jmp $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1fc0 } + }, +/* ld $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20c0 } + }, +/* ld $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0c00000 } + }, +/* ldb $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x2080 } + }, +/* ldb $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0800000 } + }, +/* ldh $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20a0 } + }, +/* ldh $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0a00000 } + }, +/* ldub $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x2090 } + }, +/* ldub $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0900000 } + }, +/* lduh $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20b0 } + }, +/* lduh $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0b00000 } + }, +/* ld $dr,@$sr+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, + & ifmt_add, { 0x20e0 } + }, +/* ld24 $dr,$uimm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, + & ifmt_ld24, { 0xe0000000 } + }, +/* ldi8 $dr,$simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, + & ifmt_addi, { 0x6000 } + }, +/* ldi16 $dr,$hash$slo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, + & ifmt_ldi16, { 0x90f00000 } + }, +/* lock $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20d0 } + }, +/* machi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3040 } + }, +/* machi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3040 } + }, +/* maclo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3050 } + }, +/* maclo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3050 } + }, +/* macwhi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3060 } + }, +/* macwhi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3060 } + }, +/* macwlo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3070 } + }, +/* macwlo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3070 } + }, +/* mul $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1060 } + }, +/* mulhi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3000 } + }, +/* mulhi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3000 } + }, +/* mullo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3010 } + }, +/* mullo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3010 } + }, +/* mulwhi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3020 } + }, +/* mulwhi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3020 } + }, +/* mulwlo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3030 } + }, +/* mulwlo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3030 } + }, +/* mv $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1080 } + }, +/* mvfachi $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_mvfachi, { 0x50f0 } + }, +/* mvfachi $dr,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, + & ifmt_mvfachi_a, { 0x50f0 } + }, +/* mvfaclo $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_mvfachi, { 0x50f1 } + }, +/* mvfaclo $dr,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, + & ifmt_mvfachi_a, { 0x50f1 } + }, +/* mvfacmi $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_mvfachi, { 0x50f2 } + }, +/* mvfacmi $dr,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, + & ifmt_mvfachi_a, { 0x50f2 } + }, +/* mvfc $dr,$scr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, + & ifmt_mvfc, { 0x1090 } + }, +/* mvtachi $src1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), 0 } }, + & ifmt_mvtachi, { 0x5070 } + }, +/* mvtachi $src1,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, + & ifmt_mvtachi_a, { 0x5070 } + }, +/* mvtaclo $src1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), 0 } }, + & ifmt_mvtachi, { 0x5071 } + }, +/* mvtaclo $src1,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, + & ifmt_mvtachi_a, { 0x5071 } + }, +/* mvtc $sr,$dcr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, + & ifmt_mvtc, { 0x10a0 } + }, +/* neg $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x30 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x7000 } + }, +/* not $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xb0 } + }, +/* rac */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x5090 } + }, +/* rac $accd,$accs,$imm1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, + & ifmt_rac_dsi, { 0x5090 } + }, +/* rach */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x5080 } + }, +/* rach $accd,$accs,$imm1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, + & ifmt_rac_dsi, { 0x5080 } + }, +/* rte */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x10d6 } + }, +/* seth $dr,$hash$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, + & ifmt_seth, { 0xd0c00000 } + }, +/* sll $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1040 } + }, +/* sll3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x90c00000 } + }, +/* slli $dr,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, + & ifmt_slli, { 0x5040 } + }, +/* sra $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1020 } + }, +/* sra3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x90a00000 } + }, +/* srai $dr,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, + & ifmt_slli, { 0x5020 } + }, +/* srl $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1000 } + }, +/* srl3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x90800000 } + }, +/* srli $dr,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, + & ifmt_slli, { 0x5000 } + }, +/* st $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2040 } + }, +/* st $src1,@($slo16,$src2) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, + & ifmt_st_d, { 0xa0400000 } + }, +/* stb $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2000 } + }, +/* stb $src1,@($slo16,$src2) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, + & ifmt_st_d, { 0xa0000000 } + }, +/* sth $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2020 } + }, +/* sth $src1,@($slo16,$src2) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, + & ifmt_st_d, { 0xa0200000 } + }, +/* st $src1,@+$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2060 } + }, +/* st $src1,@-$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2070 } + }, +/* sub $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x20 } + }, +/* subv $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x0 } + }, +/* subx $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x10 } + }, +/* trap $uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM4), 0 } }, + & ifmt_trap, { 0x10f0 } + }, +/* unlock $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2050 } + }, +/* satb $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_satb, { 0x80600300 } + }, +/* sath $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_satb, { 0x80600200 } + }, +/* sat $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_satb, { 0x80600000 } + }, +/* pcmpbz $src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), 0 } }, + & ifmt_cmpz, { 0x370 } + }, +/* sadd */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x50e4 } + }, +/* macwu1 $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50b0 } + }, +/* msblo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50d0 } + }, +/* mulwu1 $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50a0 } + }, +/* maclh1 $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50c0 } + }, +/* sc */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x7401 } + }, +/* snc */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x7501 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & m32r_cgen_ifld_table[M32R_##f] +#else +#define F(f) & m32r_cgen_ifld_table[M32R_/**/f] +#endif +static const CGEN_IFMT ifmt_bc8r = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc24r = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bl8r = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bl24r = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcl8r = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcl24r = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnc8r = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnc24r = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra8r = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra24r = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bncl8r = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bncl24r = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ld_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ld_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldb_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldb_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldh_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldh_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldub_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldub_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lduh_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lduh_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pop = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi8a = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi16a = { + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rac_d = { + 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rac_ds = { + 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rach_d = { + 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rach_ds = { + 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_st_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_st_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stb_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stb_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sth_2 = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sth_d2 = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) M32R_OPERAND_##op +#else +#define OPERAND(op) M32R_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE m32r_cgen_macro_insn_table[] = +{ +/* bc $disp8 */ + { + -1, "bc8r", "bc", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & m32r_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + m32r_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h new file mode 100644 index 0000000..0a69dc4 --- /dev/null +++ b/opcodes/m32r-opc.h @@ -0,0 +1,132 @@ +/* Instruction opcode header for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef M32R_OPC_H +#define M32R_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 256 +#undef CGEN_DIS_HASH +#define X(b) (((unsigned char *) (b))[0] & 0xf0) +#define CGEN_DIS_HASH(buffer, value) \ +(X (buffer) | \ + (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ + : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ + : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ + : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) + +/* -- */ +/* Enum declaration for m32r instruction types. */ +typedef enum cgen_insn_type { + M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND + , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR + , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3 + , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ + , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ + , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24 + , M32R_INSN_BCL8, M32R_INSN_BCL24, M32R_INSN_BNC8, M32R_INSN_BNC24 + , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8 + , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU + , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV + , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH + , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP + , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D + , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D + , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24 + , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI + , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI + , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL + , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A + , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A + , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO + , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC + , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A + , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT + , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI + , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3 + , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI + , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST + , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH + , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB + , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK + , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ + , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1 + , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID M32R_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) M32R_INSN_SNC + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_op1; + long f_op2; + long f_cond; + long f_r1; + long f_r2; + long f_simm8; + long f_simm16; + long f_shift_op2; + long f_uimm4; + long f_uimm5; + long f_uimm16; + long f_uimm24; + long f_hi16; + long f_disp8; + long f_disp16; + long f_disp24; + long f_op23; + long f_op3; + long f_acc; + long f_accs; + long f_accd; + long f_bits67; + long f_bit14; + long f_imm1; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* M32R_OPC_H */ diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c new file mode 100644 index 0000000..f89c230 --- /dev/null +++ b/opcodes/m32r-opinst.c @@ -0,0 +1,707 @@ +/* Semantic operand instances for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" + +/* Operand references. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OP_ENT(op) M32R_OPERAND_##op +#else +#define OP_ENT(op) M32R_OPERAND_/**/op +#endif +#define INPUT CGEN_OPINST_INPUT +#define OUTPUT CGEN_OPINST_OUTPUT +#define END CGEN_OPINST_END +#define COND_REF CGEN_OPINST_COND_REF + +static const CGEN_OPINST sfmt_empty_ops[] = { + { END } +}; + +static const CGEN_OPINST sfmt_add_ops[] = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_add3_ops[] = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_and3_ops[] = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_or3_ops[] = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_addi_ops[] = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_addv_ops[] = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_addv3_ops[] = { + { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_addx_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_bc8_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_bc24_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_beq_ops[] = { + { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_beqz_ops[] = { + { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_bl8_ops[] = { + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_bl24_ops[] = { + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_bcl8_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_bcl24_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_bra8_ops[] = { + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_bra24_ops[] = { + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_cmp_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_cmpi_ops[] = { + { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_cmpz_ops[] = { + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_div_ops[] = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_jc_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_jl_ops[] = { + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_jmp_ops[] = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ld_ops[] = { + { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ld_d_ops[] = { + { INPUT, "h_memory_SI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ldb_ops[] = { + { INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ldb_d_ops[] = { + { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ldh_ops[] = { + { INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ldh_d_ops[] = { + { INPUT, "h_memory_HI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ld_plus_ops[] = { + { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ld24_ops[] = { + { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ldi8_ops[] = { + { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_ldi16_ops[] = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_lock_ops[] = { + { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_machi_ops[] = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_machi_a_ops[] = { + { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mulhi_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mulhi_a_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mv_ops[] = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mvfachi_ops[] = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mvfachi_a_ops[] = { + { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mvfc_ops[] = { + { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mvtachi_ops[] = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mvtachi_a_ops[] = { + { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mvtc_ops[] = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_nop_ops[] = { + { END } +}; + +static const CGEN_OPINST sfmt_rac_ops[] = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_rac_dsi_ops[] = { + { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 }, + { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_rte_ops[] = { + { INPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 }, + { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_seth_ops[] = { + { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_sll3_ops[] = { + { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_slli_ops[] = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_st_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_st_d_ops[] = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_stb_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_stb_d_ops[] = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_sth_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_sth_d_ops[] = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_st_plus_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_trap_ops[] = { + { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { INPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 }, + { OUTPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 }, + { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_unlock_ops[] = { + { INPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF }, + { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF }, + { END } +}; + +static const CGEN_OPINST sfmt_satb_ops[] = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_sat_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_sadd_ops[] = { + { INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_macwu1_ops[] = { + { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_mulwu1_ops[] = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { END } +}; + +static const CGEN_OPINST sfmt_sc_ops[] = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END } +}; + +#undef OP_ENT +#undef INPUT +#undef OUTPUT +#undef END +#undef COND_REF + +/* Operand instance lookup table. */ + +static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = { + 0, + & sfmt_add_ops[0], + & sfmt_add3_ops[0], + & sfmt_add_ops[0], + & sfmt_and3_ops[0], + & sfmt_add_ops[0], + & sfmt_or3_ops[0], + & sfmt_add_ops[0], + & sfmt_and3_ops[0], + & sfmt_addi_ops[0], + & sfmt_addv_ops[0], + & sfmt_addv3_ops[0], + & sfmt_addx_ops[0], + & sfmt_bc8_ops[0], + & sfmt_bc24_ops[0], + & sfmt_beq_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_bl8_ops[0], + & sfmt_bl24_ops[0], + & sfmt_bcl8_ops[0], + & sfmt_bcl24_ops[0], + & sfmt_bc8_ops[0], + & sfmt_bc24_ops[0], + & sfmt_beq_ops[0], + & sfmt_bra8_ops[0], + & sfmt_bra24_ops[0], + & sfmt_bcl8_ops[0], + & sfmt_bcl24_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpi_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpi_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpz_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_jc_ops[0], + & sfmt_jc_ops[0], + & sfmt_jl_ops[0], + & sfmt_jmp_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ldb_ops[0], + & sfmt_ldb_d_ops[0], + & sfmt_ldh_ops[0], + & sfmt_ldh_d_ops[0], + & sfmt_ldb_ops[0], + & sfmt_ldb_d_ops[0], + & sfmt_ldh_ops[0], + & sfmt_ldh_d_ops[0], + & sfmt_ld_plus_ops[0], + & sfmt_ld24_ops[0], + & sfmt_ldi8_ops[0], + & sfmt_ldi16_ops[0], + & sfmt_lock_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_add_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mv_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_a_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_a_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_a_ops[0], + & sfmt_mvfc_ops[0], + & sfmt_mvtachi_ops[0], + & sfmt_mvtachi_a_ops[0], + & sfmt_mvtachi_ops[0], + & sfmt_mvtachi_a_ops[0], + & sfmt_mvtc_ops[0], + & sfmt_mv_ops[0], + & sfmt_nop_ops[0], + & sfmt_mv_ops[0], + & sfmt_rac_ops[0], + & sfmt_rac_dsi_ops[0], + & sfmt_rac_ops[0], + & sfmt_rac_dsi_ops[0], + & sfmt_rte_ops[0], + & sfmt_seth_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_st_ops[0], + & sfmt_st_d_ops[0], + & sfmt_stb_ops[0], + & sfmt_stb_d_ops[0], + & sfmt_sth_ops[0], + & sfmt_sth_d_ops[0], + & sfmt_st_plus_ops[0], + & sfmt_st_plus_ops[0], + & sfmt_add_ops[0], + & sfmt_addv_ops[0], + & sfmt_addx_ops[0], + & sfmt_trap_ops[0], + & sfmt_unlock_ops[0], + & sfmt_satb_ops[0], + & sfmt_satb_ops[0], + & sfmt_sat_ops[0], + & sfmt_cmpz_ops[0], + & sfmt_sadd_ops[0], + & sfmt_macwu1_ops[0], + & sfmt_machi_ops[0], + & sfmt_mulwu1_ops[0], + & sfmt_macwu1_ops[0], + & sfmt_sc_ops[0], + & sfmt_sc_ops[0], +}; + +/* Function to call before using the operand instance table. */ + +void +m32r_cgen_init_opinst_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + insns[i].opinst = oi[i]; +} diff --git a/opcodes/m68hc11-dis.c b/opcodes/m68hc11-dis.c new file mode 100644 index 0000000..bb0cc20 --- /dev/null +++ b/opcodes/m68hc11-dis.c @@ -0,0 +1,640 @@ +/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#include "ansidecl.h" +#include "opcode/m68hc11.h" +#include "dis-asm.h" + +static const char *const reg_name[] = { + "X", "Y", "SP", "PC" +}; + +static const char *const reg_src_table[] = { + "A", "B", "CCR", "TMP3", "D", "X", "Y", "SP" +}; + +static const char *const reg_dst_table[] = { + "A", "B", "CCR", "TMP2", "D", "X", "Y", "SP" +}; + +#define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4) + +/* Prototypes for local functions. */ +static int read_memory + PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *)); +static int print_indexed_operand + PARAMS ((bfd_vma, struct disassemble_info *, int)); +static int print_insn + PARAMS ((bfd_vma, struct disassemble_info *, int)); + +static int +read_memory (memaddr, buffer, size, info) + bfd_vma memaddr; + bfd_byte *buffer; + int size; + struct disassemble_info *info; +{ + int status; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = (*info->read_memory_func) (memaddr, buffer, size, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + return 0; +} + + +/* Read the 68HC12 indexed operand byte and print the corresponding mode. + Returns the number of bytes read or -1 if failure. */ +static int +print_indexed_operand (memaddr, info, mov_insn) + bfd_vma memaddr; + struct disassemble_info *info; + int mov_insn; +{ + bfd_byte buffer[4]; + int reg; + int status; + short sval; + int pos = 1; + + status = read_memory (memaddr, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + /* n,r with 5-bits signed constant. */ + if ((buffer[0] & 0x20) == 0) + { + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x1f); + if (sval & 0x10) + sval |= 0xfff0; + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + } + + /* Auto pre/post increment/decrement. */ + else if ((buffer[0] & 0xc0) != 0xc0) + { + const char *mode; + + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x0f); + if (sval & 0x8) + { + sval |= 0xfff0; + sval = -sval; + mode = "-"; + } + else + { + sval = sval + 1; + mode = "+"; + } + (*info->fprintf_func) (info->stream, "%d,%s%s%s", + (int) sval, + (buffer[0] & 0x10 ? "" : mode), + reg_name[reg], (buffer[0] & 0x10 ? mode : "")); + } + + /* [n,r] 16-bits offset indexed indirect. */ + else if ((buffer[0] & 0x07) == 3) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + (*info->fprintf_func) (info->stream, "[%u,%s]", + sval & 0x0ffff, reg_name[reg]); + } + else if ((buffer[0] & 0x4) == 0) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, + &buffer[1], (buffer[0] & 0x2 ? 2 : 1), info); + if (status != 0) + { + return status; + } + if (buffer[0] & 2) + { + sval = ((buffer[1] << 8) | (buffer[2] & 0x0FF)); + sval &= 0x0FFFF; + pos += 2; + } + else + { + sval = buffer[1] & 0x00ff; + if (buffer[0] & 0x01) + sval |= 0xff00; + pos++; + } + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + } + else + { + reg = (buffer[0] >> 3) & 0x03; + switch (buffer[0] & 3) + { + case 0: + (*info->fprintf_func) (info->stream, "A,%s", reg_name[reg]); + break; + case 1: + (*info->fprintf_func) (info->stream, "B,%s", reg_name[reg]); + break; + case 2: + (*info->fprintf_func) (info->stream, "D,%s", reg_name[reg]); + break; + case 3: + default: + (*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]); + break; + } + } + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +static int +print_insn (memaddr, info, arch) + bfd_vma memaddr; + struct disassemble_info *info; + int arch; +{ + int status; + bfd_byte buffer[4]; + unsigned char code; + long format, pos, i; + short sval; + const struct m68hc11_opcode *opcode; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = read_memory (memaddr, buffer, 1, info); + if (status != 0) + { + return status; + } + + format = 0; + code = buffer[0]; + pos = 0; + + /* Look for page2,3,4 opcodes. */ + if (code == M6811_OPCODE_PAGE2) + { + pos++; + format = M6811_OP_PAGE2; + } + else if (code == M6811_OPCODE_PAGE3 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE3; + } + else if (code == M6811_OPCODE_PAGE4 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE4; + } + + /* We are in page2,3,4; get the real opcode. */ + if (pos == 1) + { + status = read_memory (memaddr + pos, &buffer[1], 1, info); + if (status != 0) + { + return status; + } + code = buffer[1]; + } + + + /* Look first for a 68HC12 alias. All of them are 2-bytes long and + in page 1. There is no operand to print. We read the second byte + only when we have a possible match. */ + if ((arch & cpu6812) && format == 0) + { + int must_read = 1; + + /* Walk the alias table to find a code1+code2 match. */ + for (i = 0; i < m68hc12_num_alias; i++) + { + if (m68hc12_alias[i].code1 == code) + { + if (must_read) + { + status = read_memory (memaddr + pos + 1, + &buffer[1], 1, info); + if (status != 0) + break; + + must_read = 1; + } + if (m68hc12_alias[i].code2 == (unsigned char) buffer[1]) + { + (*info->fprintf_func) (info->stream, "%s", + m68hc12_alias[i].name); + return 2; + } + } + } + } + + pos++; + + /* Scan the opcode table until we find the opcode + with the corresponding page. */ + opcode = m68hc11_opcodes; + for (i = 0; i < m68hc11_num_opcodes; i++, opcode++) + { + int offset; + + if ((opcode->arch & arch) == 0) + continue; + if (opcode->opcode != code) + continue; + if ((opcode->format & OP_PAGE_MASK) != format) + continue; + + if (opcode->format & M6812_OP_REG) + { + int j; + int is_jump; + + if (opcode->format & M6811_OP_JUMP_REL) + is_jump = 1; + else + is_jump = 0; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + for (j = 0; i + j < m68hc11_num_opcodes; j++) + { + if ((opcode[j].arch & arch) == 0) + continue; + if (opcode[j].opcode != code) + continue; + if (is_jump) + { + if (!(opcode[j].format & M6811_OP_JUMP_REL)) + continue; + + if ((opcode[j].format & M6812_OP_IBCC_MARKER) + && (buffer[0] & 0xc0) != 0x80) + continue; + if ((opcode[j].format & M6812_OP_TBCC_MARKER) + && (buffer[0] & 0xc0) != 0x40) + continue; + if ((opcode[j].format & M6812_OP_DBCC_MARKER) + && (buffer[0] & 0xc0) != 0) + continue; + if ((opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) == 0) + break; + if (!(opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) != 0) + break; + continue; + } + if (opcode[j].format & M6812_OP_EXG_MARKER && buffer[0] & 0x80) + break; + if ((opcode[j].format & M6812_OP_SEX_MARKER) + && (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7)) + && ((buffer[0] & 0x0f0) <= 0x20)) + break; + if (opcode[j].format & M6812_OP_TFR_MARKER + && !(buffer[0] & 0x80)) + break; + } + if (i + j < m68hc11_num_opcodes) + opcode = &opcode[j]; + } + + /* We have found the opcode. Extract the operand and print it. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + format = opcode->format; + if (format & (M6811_OP_MASK | M6811_OP_BITMASK + | M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) + { + (*info->fprintf_func) (info->stream, "\t"); + } + + /* The movb and movw must be handled in a special way... + The source constant 'ii' is not always at the same place. + This is the same for the destination for the post-indexed byte. + The 'offset' is used to do the appropriate correction. + + offset offset + for constant for destination + movb 18 OB ii hh ll 0 0 + 18 08 xb ii 1 -1 + 18 0C hh ll hh ll 0 0 + 18 09 xb hh ll 1 -1 + 18 0D xb hh ll 0 0 + 18 0A xb xb 0 0 + + movw 18 03 jj kk hh ll 0 0 + 18 00 xb jj kk 1 -1 + 18 04 hh ll hh ll 0 0 + 18 01 xb hh ll 1 -1 + 18 05 xb hh ll 0 0 + 18 02 xb xb 0 0 + + After the source operand is read, the position 'pos' is incremented + this explains the negative offset for destination. + + movb/movw above are the only instructions with this matching + format. */ + offset = ((format & M6812_OP_IDX_P2) + && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | + M6811_OP_IND16))); + + /* Operand with one more byte: - immediate, offset, + direct-low address. */ + if (format & + (M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT)) + { + status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + + /* This movb/movw is special (see above). */ + offset = -offset; + + if (format & M6811_OP_IMM8) + { + (*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]); + format &= ~M6811_OP_IMM8; + } + else if (format & M6811_OP_IX) + { + /* Offsets are in range 0..255, print them unsigned. */ + (*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF); + format &= ~M6811_OP_IX; + } + else if (format & M6811_OP_IY) + { + (*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF); + format &= ~M6811_OP_IY; + } + else if (format & M6811_OP_DIRECT) + { + (*info->fprintf_func) (info->stream, "*"); + (*info->print_address_func) (buffer[0] & 0x0FF, info); + format &= ~M6811_OP_DIRECT; + } + } + +#define M6812_INDEXED_FLAGS (M6812_OP_IDX|M6812_OP_IDX_1|M6812_OP_IDX_2) + /* Analyze the 68HC12 indexed byte. */ + if (format & M6812_INDEXED_FLAGS) + { + status = print_indexed_operand (memaddr + pos, info, 0); + if (status < 0) + { + return status; + } + pos += status; + } + + /* 68HC12 dbcc/ibcc/tbcc operands. */ + if ((format & M6812_OP_REG) && (format & M6811_OP_JUMP_REL)) + { + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + (*info->fprintf_func) (info->stream, "%s,", + reg_src_table[buffer[0] & 0x07]); + sval = buffer[1] & 0x0ff; + if (buffer[0] & 0x10) + sval |= 0xff00; + + pos += 2; + (*info->print_address_func) (memaddr + pos + sval, info); + format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL); + } + else if (format & (M6812_OP_REG | M6812_OP_REG_2)) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + (*info->fprintf_func) (info->stream, "%s,%s", + reg_src_table[(buffer[0] >> 4) & 7], + reg_dst_table[(buffer[0] & 7)]); + } + + /* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately + and in that order. The brset/brclr insn have a bitmask and then + a relative branch offset. */ + if (format & M6811_OP_BITMASK) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + pos++; + (*info->fprintf_func) (info->stream, " #$%02x%s", + buffer[0] & 0x0FF, + (format & M6811_OP_JUMP_REL ? " " : "")); + format &= ~M6811_OP_BITMASK; + } + if (format & M6811_OP_JUMP_REL) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0]; + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6811_OP_JUMP_REL; + } + else if (format & M6812_OP_JUMP_REL16) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + if (val & 0x8000) + val |= 0xffff0000; + + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6812_OP_JUMP_REL16; + } + if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) + { + int val; + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + if (format & M6812_OP_IDX_P2) + offset = -2; + else + offset = 0; + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + if (format & M6811_OP_IMM16) + { + format &= ~M6811_OP_IMM16; + (*info->fprintf_func) (info->stream, "#"); + } + else + format &= ~M6811_OP_IND16; + + (*info->print_address_func) (val, info); + } + + if (format & M6812_OP_IDX_P2) + { + (*info->fprintf_func) (info->stream, ", "); + status = print_indexed_operand (memaddr + pos + offset, info, 1); + if (status < 0) + return status; + pos += status; + } + + if (format & M6812_OP_IND16_P2) + { + int val; + + (*info->fprintf_func) (info->stream, ", "); + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + (*info->print_address_func) (val, info); + } + +#ifdef DEBUG + /* Consistency check. 'format' must be 0, so that we have handled + all formats; and the computed size of the insn must match the + opcode table content. */ + if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2)) + { + (*info->fprintf_func) (info->stream, "; Error, format: %x", format); + } + if (pos != opcode->size) + { + (*info->fprintf_func) (info->stream, "; Error, size: %d expect %d", + pos, opcode->size); + } +#endif + return pos; + } + + /* Opcode not recognized. */ + if (format == M6811_OP_PAGE2 && arch & cpu6812 + && ((code >= 0x30 && code <= 0x39) || (code >= 0x40 && code <= 0xff))) + (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff); + + else if (format == M6811_OP_PAGE2) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE2, code); + else if (format == M6811_OP_PAGE3) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE3, code); + else if (format == M6811_OP_PAGE4) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE4, code); + else + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", code); + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +int +print_insn_m68hc11 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn (memaddr, info, cpu6811); +} + +int +print_insn_m68hc12 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn (memaddr, info, cpu6812); +} diff --git a/opcodes/m68hc11-opc.c b/opcodes/m68hc11-opc.c new file mode 100644 index 0000000..1e37971 --- /dev/null +++ b/opcodes/m68hc11-opc.c @@ -0,0 +1,1074 @@ +/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +*/ + +#include +#include "ansidecl.h" +#include "opcode/m68hc11.h" + +#define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0])) + +/* Combination of CCR flags. */ +#define M6811_ZC_BIT M6811_Z_BIT|M6811_C_BIT +#define M6811_NZ_BIT M6811_N_BIT|M6811_Z_BIT +#define M6811_NZV_BIT M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT +#define M6811_NZC_BIT M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT +#define M6811_NVC_BIT M6811_N_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_ZVC_BIT M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_NZVC_BIT M6811_ZVC_BIT|M6811_N_BIT +#define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT +#define M6811_HNVC_BIT M6811_NVC_BIT|M6811_H_BIT +#define M6811_VC_BIT M6811_V_BIT|M6811_C_BIT + +/* Flags when the insn only changes some CCR flags. */ +#define CHG_NONE 0,0,0 +#define CHG_Z 0,0,M6811_Z_BIT +#define CHG_C 0,0,M6811_C_BIT +#define CHG_ZVC 0,0,M6811_ZVC_BIT +#define CHG_NZC 0,0,M6811_NZC_BIT +#define CHG_NZV 0,0,M6811_NZV_BIT +#define CHG_NZVC 0,0,M6811_NZVC_BIT +#define CHG_HNZVC 0,0,M6811_HNZVC_BIT +#define CHG_ALL 0,0,0xff + +/* The insn clears and changes some flags. */ +#define CLR_I 0,M6811_I_BIT,0 +#define CLR_C 0,M6811_C_BIT,0 +#define CLR_V 0,M6811_V_BIT,0 +#define CLR_V_CHG_ZC 0,M6811_V_BIT,M6811_ZC_BIT +#define CLR_V_CHG_NZ 0,M6811_V_BIT,M6811_NZ_BIT +#define CLR_V_CHG_ZVC 0,M6811_V_BIT,M6811_ZVC_BIT +#define CLR_N_CHG_ZVC 0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */ +#define CLR_VC_CHG_NZ 0,M6811_VC_BIT,M6811_NZ_BIT + +/* The insn sets some flags. */ +#define SET_I M6811_I_BIT,0,0 +#define SET_C M6811_C_BIT,0,0 +#define SET_V M6811_V_BIT,0,0 +#define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0 +#define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT +#define SET_Z_CHG_HNVC M6811_Z_BIT,0,M6811_HNVC_BIT + +#define _M 0xff +#define OP_NONE M6811_OP_NONE +#define OP_PAGE2 M6811_OP_PAGE2 +#define OP_PAGE3 M6811_OP_PAGE3 +#define OP_PAGE4 M6811_OP_PAGE4 +#define OP_IMM8 M6811_OP_IMM8 +#define OP_IMM16 M6811_OP_IMM16 +#define OP_IX M6811_OP_IX +#define OP_IY M6811_OP_IY +#define OP_IND16 M6811_OP_IND16 +#define OP_IDX M6812_OP_IDX +#define OP_IDX_1 M6812_OP_IDX_1 +#define OP_IDX_2 M6812_OP_IDX_2 +#define OP_D_IDX M6812_OP_D_IDX +#define OP_D_IDX_2 M6812_OP_D_IDX_2 +#define OP_DIRECT M6811_OP_DIRECT +#define OP_BITMASK M6811_OP_BITMASK +#define OP_JUMP_REL M6811_OP_JUMP_REL +#define OP_JUMP_REL16 M6812_OP_JUMP_REL16 +#define OP_REG M6812_OP_REG +#define OP_REG_1 M6812_OP_REG +#define OP_REG_2 M6812_OP_REG_2 +#define OP_IDX_p2 M6812_OP_IDX_P2 +#define OP_IND16_p2 M6812_OP_IND16_P2 +#define OP_TRAP_ID M6812_OP_TRAP_ID +#define OP_EXG_MARKER M6812_OP_EXG_MARKER +#define OP_TFR_MARKER M6812_OP_TFR_MARKER +#define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER) +#define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER) +#define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER) + +/* + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + +-- cpu + Name -+ +------- Insn CCR changes + Format ------+ +----------- Max # cycles + Size --------------------+ +--------------- Min # cycles + +--------------------- Opcode +*/ +const struct m68hc11_opcode m68hc11_opcodes[] = { + { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 }, + { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 }, + { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 }, + { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 }, + + { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 }, + { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 }, + { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 }, + { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 }, + { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 }, + { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 }, + { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + + { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 }, + + { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 }, + { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 }, + { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + + { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811}, + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK + | OP_JUMP_REL + | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 }, + + { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK + | OP_JUMP_REL + | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 }, + + + { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 }, + { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 }, + + { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "call", OP_IND16, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_1, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_2, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX_2, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + + { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 }, + { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 }, + + { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 }, + { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 }, + + { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + + { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + + { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 }, + + { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + + { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + + { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 }, + { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 }, + { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 }, + { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + + { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 }, + { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 }, + { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 }, + { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 }, + { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 }, + { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + + /* After 'daa', the Z flag is undefined. Mark it as changed. */ + { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 }, + { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 }, + + { "dbeq", OP_DBEQ_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "dbne", OP_DBNE_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 }, + + { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 }, + + { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 }, + { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 }, + { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 }, + { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 }, + + { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 }, + { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 }, + { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 }, + + { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 }, + { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 }, + { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 }, + + { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + + { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + + { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + + { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + + { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 }, + { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 }, + + { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 }, + + { "exg", OP_EXG_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811}, + { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 }, + + { "ibeq", OP_IBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "ibne", OP_IBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811}, + { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 }, + { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 }, + + { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 }, + + { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 }, + { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 }, + { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 }, + { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 }, + + { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 }, + + { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 }, + { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 }, + { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 }, + + { "jmp", OP_IND16, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 }, + { "jmp", OP_IND16, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 }, + + { "jsr", OP_DIRECT, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, + { "jsr", OP_IND16, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_DIRECT, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IND16, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 }, + + { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 }, + { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 }, + { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 }, + { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 }, + { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 }, + { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 }, + { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 }, + { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 }, + { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 }, + { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 }, + { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 }, + { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 }, + { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 }, + { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 }, + + { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + + { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + + { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 }, + + { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 }, + { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 }, + { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + + { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 }, + { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 }, + + { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + + { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + + { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 }, + + { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + + { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + + { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 }, + { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 }, + + { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 }, + + { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 }, + { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 }, + + { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 }, + { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 }, + { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + + { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 }, + { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 }, + + { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 }, + + { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 }, + { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 }, + { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 }, + { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 }, + { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 }, + { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 }, + + { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 }, + { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 }, + { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 }, + { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 }, + { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 }, + { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 }, + + { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 }, + { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 }, + + { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 }, + { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + + { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 }, + { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 }, + { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 }, + { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 }, + + { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 }, + { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 }, + { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + + { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 }, + { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811}, + { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812}, + { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 }, + { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 }, + + { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 }, + { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 }, + + { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 }, + { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 }, + { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 }, + + { "sex", M6812_OP_SEX_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 }, + { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 }, + + { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 }, + { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 }, + { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 }, + { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 }, + { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 }, + { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + + { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 }, + + { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 }, + + { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + + { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 }, + + { "tbeq", OP_TBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 }, + + { "tbne", OP_TBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tfr", OP_TFR_MARKER + | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 }, + + { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 }, + { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 }, + { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 }, + { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 }, + + { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 }, + + { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 }, + + { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 }, + { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 } +}; + +const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes); + +/* The following alias table provides source compatibility to + move from 68HC11 assembly to 68HC12. */ +const struct m68hc12_opcode_alias m68hc12_alias[] = { + { "abx", "leax b,x", 2, 0x1a, 0xe5 }, + { "aby", "leay b,y", 2, 0x19, 0xed }, + { "clc", "andcc #$fe", 2, 0x10, 0xfe }, + { "cli", "andcc #$ef", 2, 0x10, 0xef }, + { "clv", "andcc #$fd", 2, 0x10, 0xfd }, + { "des", "leas -1,sp", 2, 0x1b, 0x9f }, + { "ins", "leas 1,sp", 2, 0x1b, 0x81 }, + { "sec", "orcc #$01", 2, 0x14, 0x01 }, + { "sei", "orcc #$10", 2, 0x14, 0x10 }, + { "sev", "orcc #$02", 2, 0x14, 0x02 }, + { "tap", "tfr a,ccr", 2, 0xb7, 0x02 }, + { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 }, + { "tsx", "tfr sp,x", 2, 0xb7, 0x75 }, + { "tsy", "tfr sp,y", 2, 0xb7, 0x76 }, + { "txs", "tfr x,sp", 2, 0xb7, 0x57 }, + { "tys", "tfr y,sp", 2, 0xb7, 0x67 }, + { "xgdx","exg d,x", 2, 0xb7, 0xc5 }, + { "xgdy","exg d,y", 2, 0xb7, 0xc6 } +}; +const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias); diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c new file mode 100644 index 0000000..d575088 --- /dev/null +++ b/opcodes/m68k-dis.c @@ -0,0 +1,1327 @@ +/* Print Motorola 68k instructions. + Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, + 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "floatformat.h" +#include "libiberty.h" +#include "opintl.h" + +#include "opcode/m68k.h" + +/* Local function prototypes */ + +static int +fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); + +static void +dummy_print_address PARAMS ((bfd_vma, struct disassemble_info *)); + +static int +fetch_arg PARAMS ((unsigned char *, int, int, disassemble_info *)); + +static void +print_base PARAMS ((int, bfd_vma, disassemble_info *)); + +static unsigned char * +print_indexed PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *)); + +static int +print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *, + bfd_vma, disassemble_info *)); + +CONST char * CONST fpcr_names[] = { + "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", + "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" +}; + +static char *const reg_names[] = { + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", + "%ps", "%pc" +}; + +/* Sign-extend an (unsigned char). */ +#if __STDC__ == 1 +#define COERCE_SIGNED_CHAR(ch) ((signed char) (ch)) +#else +#define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128) +#endif + +/* Get a 1 byte signed integer. */ +#define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1])) + +/* Get a 2 byte signed integer. */ +#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) +#define NEXTWORD(p) \ + (p += 2, FETCH_DATA (info, p), \ + COERCE16 ((p[-2] << 8) + p[-1])) + +/* Get a 4 byte signed integer. */ +#define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000) +#define NEXTLONG(p) \ + (p += 4, FETCH_DATA (info, p), \ + (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))) + +/* Get a 4 byte unsigned integer. */ +#define NEXTULONG(p) \ + (p += 4, FETCH_DATA (info, p), \ + (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])) + +/* Get a single precision float. */ +#define NEXTSINGLE(val, p) \ + (p += 4, FETCH_DATA (info, p), \ + floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val)) + +/* Get a double precision float. */ +#define NEXTDOUBLE(val, p) \ + (p += 8, FETCH_DATA (info, p), \ + floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val)) + +/* Get an extended precision float. */ +#define NEXTEXTEND(val, p) \ + (p += 12, FETCH_DATA (info, p), \ + floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val)) + +/* Need a function to convert from packed to double + precision. Actually, it's easier to print a + packed number than a double anyway, so maybe + there should be a special case to handle this... */ +#define NEXTPACKED(p) \ + (p += 12, FETCH_DATA (info, p), 0.0) + +/* Maximum length of an instruction. */ +#define MAXLEN 22 + +#include + +struct private { + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (info, addr) + struct disassemble_info *info; + bfd_byte *addr; +{ + int status; + struct private *priv = (struct private *)info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} + +/* This function is used to print to the bit-bucket. */ +static int +#ifdef __STDC__ +dummy_printer (FILE *file ATTRIBUTE_UNUSED, + const char *format ATTRIBUTE_UNUSED, ...) +#else +dummy_printer (file) + FILE *file ATTRIBUTE_UNUSED; +#endif +{ + return 0; +} + +static void +dummy_print_address (vma, info) + bfd_vma vma ATTRIBUTE_UNUSED; + struct disassemble_info *info ATTRIBUTE_UNUSED; +{ +} + +/* Print the m68k instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_m68k (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + register int i; + register unsigned char *p; + unsigned char *save_p; + register const char *d; + register unsigned long bestmask; + const struct m68k_opcode *best; + unsigned int arch_mask; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + fprintf_ftype save_printer = info->fprintf_func; + void (*save_print_address) PARAMS ((bfd_vma, struct disassemble_info *)) + = info->print_address_func; + int major_opcode; + static int numopcodes[16]; + static const struct m68k_opcode **opcodes[16]; + + if (!opcodes[0]) + { + /* Speed up the matching by sorting the opcode table on the upper + four bits of the opcode. */ + const struct m68k_opcode **opc_pointer[16]; + + /* First count how many opcodes are in each of the sixteen buckets. */ + for (i = 0; i < m68k_numopcodes; i++) + numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; + + /* Then create a sorted table of pointers that point into the + unsorted table. */ + opc_pointer[0] = ((const struct m68k_opcode **) + xmalloc (sizeof (struct m68k_opcode *) + * m68k_numopcodes)); + opcodes[0] = opc_pointer[0]; + for (i = 1; i < 16; i++) + { + opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; + opcodes[i] = opc_pointer[i]; + } + + for (i = 0; i < m68k_numopcodes; i++) + *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; + + } + + info->private_data = (PTR) &priv; + /* Tell objdump to use two bytes per chunk and six bytes per line for + displaying raw data. */ + info->bytes_per_chunk = 2; + info->bytes_per_line = 6; + info->display_endian = BFD_ENDIAN_BIG; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + best = NULL; + switch (info->mach) + { + default: + case 0: + arch_mask = (unsigned int) -1; + break; + case bfd_mach_m68000: + arch_mask = m68000; + break; + case bfd_mach_m68008: + arch_mask = m68008; + break; + case bfd_mach_m68010: + arch_mask = m68010; + break; + case bfd_mach_m68020: + arch_mask = m68020; + break; + case bfd_mach_m68030: + arch_mask = m68030; + break; + case bfd_mach_m68040: + arch_mask = m68040; + break; + case bfd_mach_m68060: + arch_mask = m68060; + break; + case bfd_mach_mcf5200: + arch_mask = mcf5200; + break; + case bfd_mach_mcf5206e: + arch_mask = mcf5206e; + break; + case bfd_mach_mcf5307: + arch_mask = mcf5307; + break; + case bfd_mach_mcf5407: + arch_mask = mcf5407; + break; + } + + arch_mask |= m68881 | m68851; + + bestmask = 0; + FETCH_DATA (info, buffer + 2); + major_opcode = (buffer[0] >> 4) & 15; + for (i = 0; i < numopcodes[major_opcode]; i++) + { + const struct m68k_opcode *opc = opcodes[major_opcode][i]; + unsigned long opcode = opc->opcode; + unsigned long match = opc->match; + + if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) + && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) + /* Only fetch the next two bytes if we need to. */ + && (((0xffff & match) == 0) + || + (FETCH_DATA (info, buffer + 4) + && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) + && ((0xff & buffer[3] & match) == (0xff & opcode))) + ) + && (opc->arch & arch_mask) != 0) + { + /* Don't use for printout the variants of divul and divsl + that have the same register number in two places. + The more general variants will match instead. */ + for (d = opc->args; *d; d += 2) + if (d[1] == 'D') + break; + + /* Don't use for printout the variants of most floating + point coprocessor instructions which use the same + register number in two places, as above. */ + if (*d == '\0') + for (d = opc->args; *d; d += 2) + if (d[1] == 't') + break; + + /* Don't match fmovel with more than one register; wait for + fmoveml. */ + if (*d == '\0') + { + for (d = opc->args; *d; d += 2) + { + if (d[0] == 's' && d[1] == '8') + { + int val; + + val = fetch_arg (buffer, d[1], 3, info); + if ((val & (val - 1)) != 0) + break; + } + } + } + + if (*d == '\0' && match > bestmask) + { + best = opc; + bestmask = match; + } + } + } + + if (best == NULL) + goto invalid; + + /* Point at first word of argument data, + and at descriptor for first argument. */ + p = buffer + 2; + + /* Figure out how long the fixed-size portion of the instruction is. + The only place this is stored in the opcode table is + in the arguments--look for arguments which specify fields in the 2nd + or 3rd words of the instruction. */ + for (d = best->args; *d; d += 2) + { + /* I don't think it is necessary to be checking d[0] here; I suspect + all this could be moved to the case statement below. */ + if (d[0] == '#') + { + if (d[1] == 'l' && p - buffer < 6) + p = buffer + 6; + else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') + p = buffer + 4; + } + if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) + p = buffer + 4; + switch (d[1]) + { + case '1': + case '2': + case '3': + case '7': + case '8': + case '9': + case 'i': + if (p - buffer < 4) + p = buffer + 4; + break; + case '4': + case '5': + case '6': + if (p - buffer < 6) + p = buffer + 6; + break; + default: + break; + } + } + + /* pflusha is an exceptions. It takes no arguments but is two words + long. Recognize it by looking at the lower 16 bits of the mask. */ + if (p - buffer < 4 && (best->match & 0xFFFF) != 0) + p = buffer + 4; + + /* lpstop is another exception. It takes a one word argument but is + three words long. */ + if (p - buffer < 6 + && (best->match & 0xffff) == 0xffff + && best->args[0] == '#' + && best->args[1] == 'w') + { + /* Copy the one word argument into the usual location for a one + word argument, to simplify printing it. We can get away with + this because we know exactly what the second word is, and we + aren't going to print anything based on it. */ + p = buffer + 6; + FETCH_DATA (info, p); + buffer[2] = buffer[4]; + buffer[3] = buffer[5]; + } + + FETCH_DATA (info, p); + + d = best->args; + + /* We can the operands twice. The first time we don't print anything, + but look for errors. */ + + save_p = p; + info->print_address_func = dummy_print_address; + info->fprintf_func = (fprintf_ftype) dummy_printer; + for (; *d; d += 2) + { + int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + if (eaten >= 0) + p += eaten; + else if (eaten == -1) + goto invalid; + else + { + (*info->fprintf_func) (info->stream, + /* xgettext:c-format */ + _("\n"), + best->name, + best->args); + goto invalid; + } + + } + p = save_p; + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + + d = best->args; + + (*info->fprintf_func) (info->stream, "%s", best->name); + + if (*d) + (*info->fprintf_func) (info->stream, " "); + + while (*d) + { + p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + d += 2; + if (*d && *(d - 2) != 'I' && *d != 'k') + (*info->fprintf_func) (info->stream, ","); + } + return p - buffer; + + invalid: + /* Handle undefined instructions. */ + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + (*info->fprintf_func) (info->stream, "0%o", + (buffer[0] << 8) + buffer[1]); + return 2; +} + +/* Returns number of bytes "eaten" by the operand, or + return -1 if an invalid operand was found, or -2 if + an opcode tabe error was found. */ + +static int +print_insn_arg (d, buffer, p0, addr, info) + const char *d; + unsigned char *buffer; + unsigned char *p0; + bfd_vma addr; /* PC for this arg to be relative to */ + disassemble_info *info; +{ + register int val = 0; + register int place = d[1]; + register unsigned char *p = p0; + int regno; + register CONST char *regname; + register unsigned char *p1; + double flval; + int flt_p; + bfd_signed_vma disp; + unsigned int uval; + + switch (*d) + { + case 'c': /* cache identifier */ + { + static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; + val = fetch_arg (buffer, place, 2, info); + (*info->fprintf_func) (info->stream, cacheFieldName[val]); + break; + } + + case 'a': /* address register indirect only. Cf. case '+'. */ + { + (*info->fprintf_func) + (info->stream, + "%s@", + reg_names[fetch_arg (buffer, place, 3, info) + 8]); + break; + } + + case '_': /* 32-bit absolute address for move16. */ + { + uval = NEXTULONG (p); + (*info->print_address_func) (uval, info); + break; + } + + case 'C': + (*info->fprintf_func) (info->stream, "%%ccr"); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "%%sr"); + break; + + case 'U': + (*info->fprintf_func) (info->stream, "%%usp"); + break; + + case 'E': + (*info->fprintf_func) (info->stream, "%%acc"); + break; + + case 'G': + (*info->fprintf_func) (info->stream, "%%macsr"); + break; + + case 'H': + (*info->fprintf_func) (info->stream, "%%mask"); + break; + + case 'J': + { + static const struct { char *name; int value; } names[] + = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, + {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, + {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, + {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, + {"%msp", 0x803}, {"%isp", 0x804}, + + /* Should we be calling this psr like we do in case 'Y'? */ + {"%mmusr",0x805}, + + {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}}; + + val = fetch_arg (buffer, place, 12, info); + for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--) + if (names[regno].value == val) + { + (*info->fprintf_func) (info->stream, "%s", names[regno].name); + break; + } + if (regno < 0) + (*info->fprintf_func) (info->stream, "%d", val); + } + break; + + case 'Q': + val = fetch_arg (buffer, place, 3, info); + /* 0 means 8, except for the bkpt instruction... */ + if (val == 0 && d[1] != 's') + val = 8; + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'M': + if (place == 'h') + { + static char *const scalefactor_name[] = { "<<", ">>" }; + val = fetch_arg (buffer, place, 1, info); + (*info->fprintf_func) (info->stream, scalefactor_name[val]); + } + else + { + val = fetch_arg (buffer, place, 8, info); + if (val & 0x80) + val = val - 0x100; + (*info->fprintf_func) (info->stream, "#%d", val); + } + break; + + case 'T': + val = fetch_arg (buffer, place, 4, info); + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'D': + (*info->fprintf_func) (info->stream, "%s", + reg_names[fetch_arg (buffer, place, 3, info)]); + break; + + case 'A': + (*info->fprintf_func) + (info->stream, "%s", + reg_names[fetch_arg (buffer, place, 3, info) + 010]); + break; + + case 'R': + (*info->fprintf_func) + (info->stream, "%s", + reg_names[fetch_arg (buffer, place, 4, info)]); + break; + + case 'r': + regno = fetch_arg (buffer, place, 4, info); + if (regno > 7) + (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); + else + (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); + break; + + case 'F': + (*info->fprintf_func) + (info->stream, "%%fp%d", + fetch_arg (buffer, place, 3, info)); + break; + + case 'O': + val = fetch_arg (buffer, place, 6, info); + if (val & 0x20) + (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); + else + (*info->fprintf_func) (info->stream, "%d", val); + break; + + case '+': + (*info->fprintf_func) + (info->stream, "%s@+", + reg_names[fetch_arg (buffer, place, 3, info) + 8]); + break; + + case '-': + (*info->fprintf_func) + (info->stream, "%s@-", + reg_names[fetch_arg (buffer, place, 3, info) + 8]); + break; + + case 'k': + if (place == 'k') + (*info->fprintf_func) + (info->stream, "{%s}", + reg_names[fetch_arg (buffer, place, 3, info)]); + else if (place == 'C') + { + val = fetch_arg (buffer, place, 7, info); + if (val > 63) /* This is a signed constant. */ + val -= 128; + (*info->fprintf_func) (info->stream, "{#%d}", val); + } + else + return -2; + break; + + case '#': + case '^': + p1 = buffer + (*d == '#' ? 2 : 4); + if (place == 's') + val = fetch_arg (buffer, place, 4, info); + else if (place == 'C') + val = fetch_arg (buffer, place, 7, info); + else if (place == '8') + val = fetch_arg (buffer, place, 3, info); + else if (place == '3') + val = fetch_arg (buffer, place, 8, info); + else if (place == 'b') + val = NEXTBYTE (p1); + else if (place == 'w' || place == 'W') + val = NEXTWORD (p1); + else if (place == 'l') + val = NEXTLONG (p1); + else + return -2; + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'B': + if (place == 'b') + disp = NEXTBYTE (p); + else if (place == 'B') + disp = COERCE_SIGNED_CHAR (buffer[1]); + else if (place == 'w' || place == 'W') + disp = NEXTWORD (p); + else if (place == 'l' || place == 'L' || place == 'C') + disp = NEXTLONG (p); + else if (place == 'g') + { + disp = NEXTBYTE (buffer); + if (disp == 0) + disp = NEXTWORD (p); + else if (disp == -1) + disp = NEXTLONG (p); + } + else if (place == 'c') + { + if (buffer[1] & 0x40) /* If bit six is one, long offset */ + disp = NEXTLONG (p); + else + disp = NEXTWORD (p); + } + else + return -2; + + (*info->print_address_func) (addr + disp, info); + break; + + case 'd': + val = NEXTWORD (p); + (*info->fprintf_func) + (info->stream, "%s@(%d)", + reg_names[fetch_arg (buffer, place, 3, info) + 8], val); + break; + + case 's': + (*info->fprintf_func) (info->stream, "%s", + fpcr_names[fetch_arg (buffer, place, 3, info)]); + break; + + case 'I': + /* Get coprocessor ID... */ + val = fetch_arg (buffer, 'd', 3, info); + + if (val != 1) /* Unusual coprocessor ID? */ + (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); + break; + + case '*': + case '~': + case '%': + case ';': + case '@': + case '!': + case '$': + case '?': + case '/': + case '&': + case '|': + case '<': + case '>': + case 'm': + case 'n': + case 'o': + case 'p': + case 'q': + case 'v': + + if (place == 'd') + { + val = fetch_arg (buffer, 'x', 6, info); + val = ((val & 7) << 3) + ((val >> 3) & 7); + } + else + val = fetch_arg (buffer, 's', 6, info); + + /* Get register number assuming address register. */ + regno = (val & 7) + 8; + regname = reg_names[regno]; + switch (val >> 3) + { + case 0: + (*info->fprintf_func) (info->stream, "%s", reg_names[val]); + break; + + case 1: + (*info->fprintf_func) (info->stream, "%s", regname); + break; + + case 2: + (*info->fprintf_func) (info->stream, "%s@", regname); + break; + + case 3: + (*info->fprintf_func) (info->stream, "%s@+", regname); + break; + + case 4: + (*info->fprintf_func) (info->stream, "%s@-", regname); + break; + + case 5: + val = NEXTWORD (p); + (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); + break; + + case 6: + p = print_indexed (regno, p, addr, info); + break; + + case 7: + switch (val & 7) + { + case 0: + val = NEXTWORD (p); + (*info->print_address_func) (val, info); + break; + + case 1: + uval = NEXTULONG (p); + (*info->print_address_func) (uval, info); + break; + + case 2: + val = NEXTWORD (p); + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (addr + val, info); + (*info->fprintf_func) (info->stream, ")"); + break; + + case 3: + p = print_indexed (-1, p, addr, info); + break; + + case 4: + flt_p = 1; /* Assume it's a float... */ + switch (place) + { + case 'b': + val = NEXTBYTE (p); + flt_p = 0; + break; + + case 'w': + val = NEXTWORD (p); + flt_p = 0; + break; + + case 'l': + val = NEXTLONG (p); + flt_p = 0; + break; + + case 'f': + NEXTSINGLE (flval, p); + break; + + case 'F': + NEXTDOUBLE (flval, p); + break; + + case 'x': + NEXTEXTEND (flval, p); + break; + + case 'p': + flval = NEXTPACKED (p); + break; + + default: + return -1; + } + if (flt_p) /* Print a float? */ + (*info->fprintf_func) (info->stream, "#%g", flval); + else + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + default: + return -1; + } + } + break; + + case 'L': + case 'l': + if (place == 'w') + { + char doneany; + p1 = buffer + 2; + val = NEXTWORD (p1); + /* Move the pointer ahead if this point is farther ahead + than the last. */ + p = p1 > p ? p1 : p; + if (val == 0) + { + (*info->fprintf_func) (info->stream, "#0"); + break; + } + if (*d == 'l') + { + register int newval = 0; + for (regno = 0; regno < 16; ++regno) + if (val & (0x8000 >> regno)) + newval |= 1 << regno; + val = newval; + } + val &= 0xffff; + doneany = 0; + for (regno = 0; regno < 16; ++regno) + if (val & (1 << regno)) + { + int first_regno; + if (doneany) + (*info->fprintf_func) (info->stream, "/"); + doneany = 1; + (*info->fprintf_func) (info->stream, "%s", reg_names[regno]); + first_regno = regno; + while (val & (1 << (regno + 1))) + ++regno; + if (regno > first_regno) + (*info->fprintf_func) (info->stream, "-%s", + reg_names[regno]); + } + } + else if (place == '3') + { + /* `fmovem' insn. */ + char doneany; + val = fetch_arg (buffer, place, 8, info); + if (val == 0) + { + (*info->fprintf_func) (info->stream, "#0"); + break; + } + if (*d == 'l') + { + register int newval = 0; + for (regno = 0; regno < 8; ++regno) + if (val & (0x80 >> regno)) + newval |= 1 << regno; + val = newval; + } + val &= 0xff; + doneany = 0; + for (regno = 0; regno < 8; ++regno) + if (val & (1 << regno)) + { + int first_regno; + if (doneany) + (*info->fprintf_func) (info->stream, "/"); + doneany = 1; + (*info->fprintf_func) (info->stream, "%%fp%d", regno); + first_regno = regno; + while (val & (1 << (regno + 1))) + ++regno; + if (regno > first_regno) + (*info->fprintf_func) (info->stream, "-%%fp%d", regno); + } + } + else if (place == '8') + { + /* fmoveml for FP status registers */ + (*info->fprintf_func) (info->stream, "%s", + fpcr_names[fetch_arg (buffer, place, 3, + info)]); + } + else + return -2; + break; + + case 'X': + place = '8'; + case 'Y': + case 'Z': + case 'W': + case '0': + case '1': + case '2': + case '3': + { + int val = fetch_arg (buffer, place, 5, info); + char *name = 0; + switch (val) + { + case 2: name = "%tt0"; break; + case 3: name = "%tt1"; break; + case 0x10: name = "%tc"; break; + case 0x11: name = "%drp"; break; + case 0x12: name = "%srp"; break; + case 0x13: name = "%crp"; break; + case 0x14: name = "%cal"; break; + case 0x15: name = "%val"; break; + case 0x16: name = "%scc"; break; + case 0x17: name = "%ac"; break; + case 0x18: name = "%psr"; break; + case 0x19: name = "%pcsr"; break; + case 0x1c: + case 0x1d: + { + int break_reg = ((buffer[3] >> 2) & 7); + (*info->fprintf_func) + (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", + break_reg); + } + break; + default: + (*info->fprintf_func) (info->stream, "", val); + } + if (name) + (*info->fprintf_func) (info->stream, "%s", name); + } + break; + + case 'f': + { + int fc = fetch_arg (buffer, place, 5, info); + if (fc == 1) + (*info->fprintf_func) (info->stream, "%%dfc"); + else if (fc == 0) + (*info->fprintf_func) (info->stream, "%%sfc"); + else + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _(""), fc); + } + break; + + case 'V': + (*info->fprintf_func) (info->stream, "%%val"); + break; + + case 't': + { + int level = fetch_arg (buffer, place, 3, info); + (*info->fprintf_func) (info->stream, "%d", level); + } + break; + + case 'u': + { + short is_upper = 0; + int reg = fetch_arg (buffer, place, 5, info); + + if (reg & 0x10) + { + is_upper = 1; + reg &= 0xf; + } + (*info->fprintf_func) (info->stream, "%s%s", + reg_names[reg], + is_upper ? "u" : "l"); + } + break; + + default: + return -2; + } + + return p - p0; +} + +/* Fetch BITS bits from a position in the instruction specified by CODE. + CODE is a "place to put an argument", or 'x' for a destination + that is a general address (mode and register). + BUFFER contains the instruction. */ + +static int +fetch_arg (buffer, code, bits, info) + unsigned char *buffer; + int code; + int bits; + disassemble_info *info; +{ + register int val = 0; + switch (code) + { + case 's': + val = buffer[1]; + break; + + case 'd': /* Destination, for register or quick. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 9; + break; + + case 'x': /* Destination, for general arg */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 6; + break; + + case 'k': + FETCH_DATA (info, buffer + 3); + val = (buffer[3] >> 4); + break; + + case 'C': + FETCH_DATA (info, buffer + 3); + val = buffer[3]; + break; + + case '1': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 12; + break; + + case '2': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 6; + break; + + case '3': + case 'j': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + break; + + case '4': + FETCH_DATA (info, buffer + 5); + val = (buffer[4] << 8) + buffer[5]; + val >>= 12; + break; + + case '5': + FETCH_DATA (info, buffer + 5); + val = (buffer[4] << 8) + buffer[5]; + val >>= 6; + break; + + case '6': + FETCH_DATA (info, buffer + 5); + val = (buffer[4] << 8) + buffer[5]; + break; + + case '7': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 7; + break; + + case '8': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 10; + break; + + case '9': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 5; + break; + + case 'e': + val = (buffer[1] >> 6); + break; + + case 'm': + val = (buffer[1] & 0x40 ? 0x8 : 0) + | ((buffer[0] >> 1) & 0x7) + | (buffer[3] & 0x80 ? 0x10 : 0); + break; + + case 'n': + val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); + break; + + case 'o': + val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); + break; + + case 'M': + val = buffer[1] | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'N': + val = buffer[3] | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'h': + val = buffer[2] >> 2; + break; + + default: + abort (); + } + + switch (bits) + { + case 1: + return val & 1; + case 2: + return val & 3; + case 3: + return val & 7; + case 4: + return val & 017; + case 5: + return val & 037; + case 6: + return val & 077; + case 7: + return val & 0177; + case 8: + return val & 0377; + case 12: + return val & 07777; + default: + abort (); + } +} + +/* Print an indexed argument. The base register is BASEREG (-1 for pc). + P points to extension word, in buffer. + ADDR is the nominal core address of that extension word. */ + +static unsigned char * +print_indexed (basereg, p, addr, info) + int basereg; + unsigned char *p; + bfd_vma addr; + disassemble_info *info; +{ + register int word; + static char *const scales[] = { "", ":2", ":4", ":8" }; + bfd_vma base_disp; + bfd_vma outer_disp; + char buf[40]; + char vmabuf[50]; + + word = NEXTWORD (p); + + /* Generate the text for the index register. + Where this will be output is not yet determined. */ + sprintf (buf, "%s:%c%s", + reg_names[(word >> 12) & 0xf], + (word & 0x800) ? 'l' : 'w', + scales[(word >> 9) & 3]); + + /* Handle the 68000 style of indexing. */ + + if ((word & 0x100) == 0) + { + base_disp = word & 0xff; + if ((base_disp & 0x80) != 0) + base_disp -= 0x100; + if (basereg == -1) + base_disp += addr; + print_base (basereg, base_disp, info); + (*info->fprintf_func) (info->stream, ",%s)", buf); + return p; + } + + /* Handle the generalized kind. */ + /* First, compute the displacement to add to the base register. */ + + if (word & 0200) + { + if (basereg == -1) + basereg = -3; + else + basereg = -2; + } + if (word & 0100) + buf[0] = '\0'; + base_disp = 0; + switch ((word >> 4) & 3) + { + case 2: + base_disp = NEXTWORD (p); + break; + case 3: + base_disp = NEXTLONG (p); + } + if (basereg == -1) + base_disp += addr; + + /* Handle single-level case (not indirect) */ + + if ((word & 7) == 0) + { + print_base (basereg, base_disp, info); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + return p; + } + + /* Two level. Compute displacement to add after indirection. */ + + outer_disp = 0; + switch (word & 3) + { + case 2: + outer_disp = NEXTWORD (p); + break; + case 3: + outer_disp = NEXTLONG (p); + } + + print_base (basereg, base_disp, info); + if ((word & 4) == 0 && buf[0] != '\0') + { + (*info->fprintf_func) (info->stream, ",%s", buf); + buf[0] = '\0'; + } + sprintf_vma (vmabuf, outer_disp); + (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + + return p; +} + +/* Print a base register REGNO and displacement DISP, on INFO->STREAM. + REGNO = -1 for pc, -2 for none (suppressed). */ + +static void +print_base (regno, disp, info) + int regno; + bfd_vma disp; + disassemble_info *info; +{ + if (regno == -1) + { + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (disp, info); + } + else + { + char buf[50]; + + if (regno == -2) + (*info->fprintf_func) (info->stream, "@("); + else if (regno == -3) + (*info->fprintf_func) (info->stream, "%%zpc@("); + else + (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); + + sprintf_vma (buf, disp); + (*info->fprintf_func) (info->stream, "%s", buf); + } +} diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c new file mode 100644 index 0000000..79d7db0 --- /dev/null +++ b/opcodes/m68k-opc.c @@ -0,0 +1,2211 @@ +/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001 + Free Software Foundation, Inc. + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include "sysdep.h" +#include "opcode/m68k.h" + +#define one(x) ((unsigned int) (x) << 16) +#define two(x, y) (((unsigned int) (x) << 16) + (y)) + +/* The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler will bomb at + runtime. */ + +const struct m68k_opcode m68k_opcodes[] = +{ +{"abcd", one(0140400), one(0170770), "DsDd", m68000up }, +{"abcd", one(0140410), one(0170770), "-s-d", m68000up }, + +{"addaw", one(0150300), one(0170700), "*wAd", m68000up }, +{"addal", one(0150700), one(0170700), "*lAd", m68000up | mcf }, + +{"addib", one(0003000), one(0177700), "#b$s", m68000up }, +{"addiw", one(0003100), one(0177700), "#w$s", m68000up }, +{"addil", one(0003200), one(0177700), "#l$s", m68000up }, +{"addil", one(0003200), one(0177700), "#lDs", mcf }, + +{"addqb", one(0050000), one(0170700), "Qd$b", m68000up }, +{"addqw", one(0050100), one(0170700), "Qd%w", m68000up }, +{"addql", one(0050200), one(0170700), "Qd%l", m68000up | mcf }, + +/* The add opcode can generate the adda, addi, and addq instructions. */ +{"addb", one(0050000), one(0170700), "Qd$b", m68000up }, +{"addb", one(0003000), one(0177700), "#b$s", m68000up }, +{"addb", one(0150000), one(0170700), ";bDd", m68000up }, +{"addb", one(0150400), one(0170700), "Dd~b", m68000up }, +{"addw", one(0050100), one(0170700), "Qd%w", m68000up }, +{"addw", one(0150300), one(0170700), "*wAd", m68000up }, +{"addw", one(0003100), one(0177700), "#w$s", m68000up }, +{"addw", one(0150100), one(0170700), "*wDd", m68000up }, +{"addw", one(0150500), one(0170700), "Dd~w", m68000up }, +{"addl", one(0050200), one(0170700), "Qd%l", m68000up | mcf }, +{"addl", one(0003200), one(0177700), "#l$s", m68000up }, +{"addl", one(0003200), one(0177700), "#lDs", mcf }, +{"addl", one(0150700), one(0170700), "*lAd", m68000up | mcf }, +{"addl", one(0150200), one(0170700), "*lDd", m68000up | mcf }, +{"addl", one(0150600), one(0170700), "Dd~l", m68000up | mcf }, + +{"addxb", one(0150400), one(0170770), "DsDd", m68000up }, +{"addxb", one(0150410), one(0170770), "-s-d", m68000up }, +{"addxw", one(0150500), one(0170770), "DsDd", m68000up }, +{"addxw", one(0150510), one(0170770), "-s-d", m68000up }, +{"addxl", one(0150600), one(0170770), "DsDd", m68000up | mcf }, +{"addxl", one(0150610), one(0170770), "-s-d", m68000up }, + +{"andib", one(0001000), one(0177700), "#b$s", m68000up }, +{"andib", one(0001074), one(0177777), "#bCs", m68000up }, +{"andiw", one(0001100), one(0177700), "#w$s", m68000up }, +{"andiw", one(0001174), one(0177777), "#wSs", m68000up }, +{"andil", one(0001200), one(0177700), "#l$s", m68000up }, +{"andil", one(0001200), one(0177700), "#lDs", mcf }, +{"andi", one(0001100), one(0177700), "#w$s", m68000up }, +{"andi", one(0001074), one(0177777), "#bCs", m68000up }, +{"andi", one(0001174), one(0177777), "#wSs", m68000up }, + +/* The and opcode can generate the andi instruction. */ +{"andb", one(0001000), one(0177700), "#b$s", m68000up }, +{"andb", one(0001074), one(0177777), "#bCs", m68000up }, +{"andb", one(0140000), one(0170700), ";bDd", m68000up }, +{"andb", one(0140400), one(0170700), "Dd~b", m68000up }, +{"andw", one(0001100), one(0177700), "#w$s", m68000up }, +{"andw", one(0001174), one(0177777), "#wSs", m68000up }, +{"andw", one(0140100), one(0170700), ";wDd", m68000up }, +{"andw", one(0140500), one(0170700), "Dd~w", m68000up }, +{"andl", one(0001200), one(0177700), "#l$s", m68000up }, +{"andl", one(0001200), one(0177700), "#lDs", mcf }, +{"andl", one(0140200), one(0170700), ";lDd", m68000up | mcf }, +{"andl", one(0140600), one(0170700), "Dd~l", m68000up | mcf }, +{"and", one(0001100), one(0177700), "#w$w", m68000up }, +{"and", one(0001074), one(0177777), "#bCs", m68000up }, +{"and", one(0001174), one(0177777), "#wSs", m68000up }, +{"and", one(0140100), one(0170700), ";wDd", m68000up }, +{"and", one(0140500), one(0170700), "Dd~w", m68000up }, + +{"aslb", one(0160400), one(0170770), "QdDs", m68000up }, +{"aslb", one(0160440), one(0170770), "DdDs", m68000up }, +{"aslw", one(0160500), one(0170770), "QdDs", m68000up }, +{"aslw", one(0160540), one(0170770), "DdDs", m68000up }, +{"aslw", one(0160700), one(0177700), "~s", m68000up }, +{"asll", one(0160600), one(0170770), "QdDs", m68000up | mcf }, +{"asll", one(0160640), one(0170770), "DdDs", m68000up | mcf }, + +{"asrb", one(0160000), one(0170770), "QdDs", m68000up }, +{"asrb", one(0160040), one(0170770), "DdDs", m68000up }, +{"asrw", one(0160100), one(0170770), "QdDs", m68000up }, +{"asrw", one(0160140), one(0170770), "DdDs", m68000up }, +{"asrw", one(0160300), one(0177700), "~s", m68000up }, +{"asrl", one(0160200), one(0170770), "QdDs", m68000up | mcf }, +{"asrl", one(0160240), one(0170770), "DdDs", m68000up | mcf }, + +{"bhiw", one(0061000), one(0177777), "BW", m68000up | mcf }, +{"blsw", one(0061400), one(0177777), "BW", m68000up | mcf }, +{"bccw", one(0062000), one(0177777), "BW", m68000up | mcf }, +{"bcsw", one(0062400), one(0177777), "BW", m68000up | mcf }, +{"bnew", one(0063000), one(0177777), "BW", m68000up | mcf }, +{"beqw", one(0063400), one(0177777), "BW", m68000up | mcf }, +{"bvcw", one(0064000), one(0177777), "BW", m68000up | mcf }, +{"bvsw", one(0064400), one(0177777), "BW", m68000up | mcf }, +{"bplw", one(0065000), one(0177777), "BW", m68000up | mcf }, +{"bmiw", one(0065400), one(0177777), "BW", m68000up | mcf }, +{"bgew", one(0066000), one(0177777), "BW", m68000up | mcf }, +{"bltw", one(0066400), one(0177777), "BW", m68000up | mcf }, +{"bgtw", one(0067000), one(0177777), "BW", m68000up | mcf }, +{"blew", one(0067400), one(0177777), "BW", m68000up | mcf }, + +{"bhil", one(0061377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"blsl", one(0061777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bccl", one(0062377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bcsl", one(0062777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bnel", one(0063377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"beql", one(0063777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bvcl", one(0064377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bvsl", one(0064777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bpll", one(0065377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bmil", one(0065777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bgel", one(0066377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bltl", one(0066777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bgtl", one(0067377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"blel", one(0067777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, + +{"bhis", one(0061000), one(0177400), "BB", m68000up | mcf }, +{"blss", one(0061400), one(0177400), "BB", m68000up | mcf }, +{"bccs", one(0062000), one(0177400), "BB", m68000up | mcf }, +{"bcss", one(0062400), one(0177400), "BB", m68000up | mcf }, +{"bnes", one(0063000), one(0177400), "BB", m68000up | mcf }, +{"beqs", one(0063400), one(0177400), "BB", m68000up | mcf }, +{"bvcs", one(0064000), one(0177400), "BB", m68000up | mcf }, +{"bvss", one(0064400), one(0177400), "BB", m68000up | mcf }, +{"bpls", one(0065000), one(0177400), "BB", m68000up | mcf }, +{"bmis", one(0065400), one(0177400), "BB", m68000up | mcf }, +{"bges", one(0066000), one(0177400), "BB", m68000up | mcf }, +{"blts", one(0066400), one(0177400), "BB", m68000up | mcf }, +{"bgts", one(0067000), one(0177400), "BB", m68000up | mcf }, +{"bles", one(0067400), one(0177400), "BB", m68000up | mcf }, + +{"jhi", one(0061000), one(0177400), "Bg", m68000up | mcf }, +{"jls", one(0061400), one(0177400), "Bg", m68000up | mcf }, +{"jcc", one(0062000), one(0177400), "Bg", m68000up | mcf }, +{"jcs", one(0062400), one(0177400), "Bg", m68000up | mcf }, +{"jne", one(0063000), one(0177400), "Bg", m68000up | mcf }, +{"jeq", one(0063400), one(0177400), "Bg", m68000up | mcf }, +{"jvc", one(0064000), one(0177400), "Bg", m68000up | mcf }, +{"jvs", one(0064400), one(0177400), "Bg", m68000up | mcf }, +{"jpl", one(0065000), one(0177400), "Bg", m68000up | mcf }, +{"jmi", one(0065400), one(0177400), "Bg", m68000up | mcf }, +{"jge", one(0066000), one(0177400), "Bg", m68000up | mcf }, +{"jlt", one(0066400), one(0177400), "Bg", m68000up | mcf }, +{"jgt", one(0067000), one(0177400), "Bg", m68000up | mcf }, +{"jle", one(0067400), one(0177400), "Bg", m68000up | mcf }, + +{"bchg", one(0000500), one(0170700), "Dd$s", m68000up | mcf }, +{"bchg", one(0004100), one(0177700), "#b$s", m68000up }, +{"bchg", one(0004100), one(0177700), "#bqs", mcf }, + +{"bclr", one(0000600), one(0170700), "Dd$s", m68000up }, +{"bclr", one(0000600), one(0170700), "Ddvs", mcf }, +{"bclr", one(0004200), one(0177700), "#b$s", m68000up }, +{"bclr", one(0004200), one(0177700), "#bqs", mcf }, + +{"bfchg", two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{"bfclr", two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{"bfexts", two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{"bfextu", two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{"bfffo", two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{"bfins", two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, +{"bfset", two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{"bftst", two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, + +{"bgnd", one(0045372), one(0177777), "", cpu32 }, + +{"bkpt", one(0044110), one(0177770), "ts", m68010up }, + +{"braw", one(0060000), one(0177777), "BW", m68000up | mcf }, +{"bral", one(0060377), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bras", one(0060000), one(0177400), "BB", m68000up | mcf }, + +{"bset", one(0000700), one(0170700), "Dd$s", m68000up }, +{"bset", one(0000700), one(0170700), "Ddvs", mcf }, +{"bset", one(0004300), one(0177700), "#b$s", m68000up }, +{"bset", one(0004300), one(0177700), "#bqs", mcf }, + +{"bsrw", one(0060400), one(0177777), "BW", m68000up | mcf }, +{"bsrl", one(0060777), one(0177777), "BL", m68020up | cpu32 | mcf5407}, +{"bsrs", one(0060400), one(0177400), "BB", m68000up | mcf }, + +{"btst", one(0000400), one(0170700), "Dd;b", m68000up | mcf }, +{"btst", one(0004000), one(0177700), "#b@s", m68000up }, +{"btst", one(0004000), one(0177700), "#bqs", mcf }, + +{"callm", one(0003300), one(0177700), "#b!s", m68020 }, + +{"cas2w", two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, +{"cas2w", two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, +{"cas2l", two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, +{"cas2l", two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, + +{"casb", two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{"casw", two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{"casl", two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, + +{"chk2b", two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, +{"chk2w", two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, +{"chk2l", two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, + +{"chkl", one(0040400), one(0170700), ";lDd", m68000up }, +{"chkw", one(0040600), one(0170700), ";wDd", m68000up }, + +#define SCOPE_LINE (0x1 << 3) +#define SCOPE_PAGE (0x2 << 3) +#define SCOPE_ALL (0x3 << 3) + +{"cinva", one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, +{"cinvl", one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, +{"cinvp", one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, + +{"cpusha", one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, +{"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcf }, +{"cpushp", one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, + +#undef SCOPE_LINE +#undef SCOPE_PAGE +#undef SCOPE_ALL + +{"clrb", one(0041000), one(0177700), "$s", m68000up | mcf }, +{"clrw", one(0041100), one(0177700), "$s", m68000up | mcf }, +{"clrl", one(0041200), one(0177700), "$s", m68000up | mcf }, + +{"cmp2b", two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, +{"cmp2w", two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, +{"cmp2l", two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, + +{"cmpaw", one(0130300), one(0170700), "*wAd", m68000up }, +{"cmpal", one(0130700), one(0170700), "*lAd", m68000up | mcf }, + +{"cmpib", one(0006000), one(0177700), "#b@s", m68000up }, +{"cmpib", one(0006000), one(0177700), "#bDs", mcf5407 }, +{"cmpiw", one(0006100), one(0177700), "#w@s", m68000up }, +{"cmpiw", one(0006100), one(0177700), "#wDs", mcf5407 }, +{"cmpil", one(0006200), one(0177700), "#l@s", m68000up }, +{"cmpil", one(0006200), one(0177700), "#lDs", mcf }, + +{"cmpmb", one(0130410), one(0170770), "+s+d", m68000up }, +{"cmpmw", one(0130510), one(0170770), "+s+d", m68000up }, +{"cmpml", one(0130610), one(0170770), "+s+d", m68000up }, + +/* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ +{"cmpb", one(0006000), one(0177700), "#b@s", m68000up }, +{"cmpb", one(0006000), one(0177700), "#bDs", mcf5407 }, +{"cmpb", one(0130410), one(0170770), "+s+d", m68000up }, +{"cmpb", one(0130000), one(0170700), ";bDd", m68000up }, +{"cmpb", one(0130000), one(0170700), "*bDd", mcf5407 }, +{"cmpw", one(0130300), one(0170700), "*wAd", m68000up }, +{"cmpw", one(0006100), one(0177700), "#w@s", m68000up }, +{"cmpw", one(0006100), one(0177700), "#wDs", mcf5407 }, +{"cmpw", one(0130510), one(0170770), "+s+d", m68000up }, +{"cmpw", one(0130100), one(0170700), "*wDd", m68000up | mcf5407 }, +{"cmpl", one(0130700), one(0170700), "*lAd", m68000up | mcf }, +{"cmpl", one(0006200), one(0177700), "#l@s", m68000up }, +{"cmpl", one(0006200), one(0177700), "#lDs", mcf }, +{"cmpl", one(0130610), one(0170770), "+s+d", m68000up }, +{"cmpl", one(0130200), one(0170700), "*lDd", m68000up | mcf }, + +{"dbcc", one(0052310), one(0177770), "DsBw", m68000up }, +{"dbcs", one(0052710), one(0177770), "DsBw", m68000up }, +{"dbeq", one(0053710), one(0177770), "DsBw", m68000up }, +{"dbf", one(0050710), one(0177770), "DsBw", m68000up }, +{"dbge", one(0056310), one(0177770), "DsBw", m68000up }, +{"dbgt", one(0057310), one(0177770), "DsBw", m68000up }, +{"dbhi", one(0051310), one(0177770), "DsBw", m68000up }, +{"dble", one(0057710), one(0177770), "DsBw", m68000up }, +{"dbls", one(0051710), one(0177770), "DsBw", m68000up }, +{"dblt", one(0056710), one(0177770), "DsBw", m68000up }, +{"dbmi", one(0055710), one(0177770), "DsBw", m68000up }, +{"dbne", one(0053310), one(0177770), "DsBw", m68000up }, +{"dbpl", one(0055310), one(0177770), "DsBw", m68000up }, +{"dbt", one(0050310), one(0177770), "DsBw", m68000up }, +{"dbvc", one(0054310), one(0177770), "DsBw", m68000up }, +{"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, + +{"divsw", one(0100700), one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e }, + +{"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, +{"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD", mcf5307up | mcf5206e }, + +{"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, +{"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, + +{"divuw", one(0100300), one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e }, + +{"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, +{"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, +{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD", mcf5307up | mcf5206e }, + +{"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, +{"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, + +{"eorib", one(0005000), one(0177700), "#b$s", m68000up }, +{"eorib", one(0005074), one(0177777), "#bCs", m68000up }, +{"eoriw", one(0005100), one(0177700), "#w$s", m68000up }, +{"eoriw", one(0005174), one(0177777), "#wSs", m68000up }, +{"eoril", one(0005200), one(0177700), "#l$s", m68000up }, +{"eoril", one(0005200), one(0177700), "#lDs", mcf }, +{"eori", one(0005074), one(0177777), "#bCs", m68000up }, +{"eori", one(0005174), one(0177777), "#wSs", m68000up }, +{"eori", one(0005100), one(0177700), "#w$s", m68000up }, + +/* The eor opcode can generate the eori instruction. */ +{"eorb", one(0005000), one(0177700), "#b$s", m68000up }, +{"eorb", one(0005074), one(0177777), "#bCs", m68000up }, +{"eorb", one(0130400), one(0170700), "Dd$s", m68000up }, +{"eorw", one(0005100), one(0177700), "#w$s", m68000up }, +{"eorw", one(0005174), one(0177777), "#wSs", m68000up }, +{"eorw", one(0130500), one(0170700), "Dd$s", m68000up }, +{"eorl", one(0005200), one(0177700), "#l$s", m68000up }, +{"eorl", one(0005200), one(0177700), "#lDs", mcf }, +{"eorl", one(0130600), one(0170700), "Dd$s", m68000up | mcf }, +{"eor", one(0005074), one(0177777), "#bCs", m68000up }, +{"eor", one(0005174), one(0177777), "#wSs", m68000up }, +{"eor", one(0005100), one(0177700), "#w$s", m68000up }, +{"eor", one(0130500), one(0170700), "Dd$s", m68000up }, + +{"exg", one(0140500), one(0170770), "DdDs", m68000up }, +{"exg", one(0140510), one(0170770), "AdAs", m68000up }, +{"exg", one(0140610), one(0170770), "DdAs", m68000up }, +{"exg", one(0140610), one(0170770), "AsDd", m68000up }, + +{"extw", one(0044200), one(0177770), "Ds", m68000up|mcf }, +{"extl", one(0044300), one(0177770), "Ds", m68000up|mcf }, +{"extbl", one(0044700), one(0177770), "Ds", m68020up|cpu32|mcf }, + +/* float stuff starts here */ + +{"fabsb", two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fabsd", two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fabsl", two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fabsp", two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fabss", two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fabsw", two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fabsx", two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fabsx", two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fabsx", two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsabsb", two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsabsd", two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsabsl", two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsabsp", two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsabss", two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsabsw", two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsabsx", two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsabsx", two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fsabsx", two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdabsb", two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, +{"fdabsd", two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, +{"fdabsl", two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, +{"fdabsp", two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, +{"fdabss", two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, +{"fdabsw", two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, +{"fdabsx", two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, +{"fdabsx", two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, +{"fdabsx", two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, + +{"facosb", two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"facosd", two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"facosl", two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"facosp", two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"facoss", two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"facosw", two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"facosx", two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"facosx", two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"facosx", two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"faddb", two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"faddd", two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"faddl", two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"faddp", two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fadds", two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"faddw", two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"faddx", two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"faddx", two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fsaddb", two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsaddd", two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsaddl", two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsaddp", two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsadds", two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsaddw", two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsaddx", two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsaddx", two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fdaddb", two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdaddd", two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdaddl", two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdaddp", two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdadds", two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdaddw", two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdaddx", two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdaddx", two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fasinb", two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fasind", two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fasinl", two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fasinp", two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fasins", two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fasinw", two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fasinx", two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fasinx", two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fasinx", two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fatanb", two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fatand", two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fatanl", two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fatanp", two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fatans", two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fatanw", two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fatanx", two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fatanx", two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fatanx", two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fatanhb", two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fatanhd", two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fatanhl", two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fatanhp", two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fatanhs", two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fatanhw", two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fatanhx", two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fatanhx", two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fatanhx", two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fbeq", one(0xF081), one(0xF1FF), "IdBW", mfloat }, +{"fbf", one(0xF080), one(0xF1FF), "IdBW", mfloat }, +{"fbge", one(0xF093), one(0xF1FF), "IdBW", mfloat }, +{"fbgl", one(0xF096), one(0xF1FF), "IdBW", mfloat }, +{"fbgle", one(0xF097), one(0xF1FF), "IdBW", mfloat }, +{"fbgt", one(0xF092), one(0xF1FF), "IdBW", mfloat }, +{"fble", one(0xF095), one(0xF1FF), "IdBW", mfloat }, +{"fblt", one(0xF094), one(0xF1FF), "IdBW", mfloat }, +{"fbne", one(0xF08E), one(0xF1FF), "IdBW", mfloat }, +{"fbnge", one(0xF09C), one(0xF1FF), "IdBW", mfloat }, +{"fbngl", one(0xF099), one(0xF1FF), "IdBW", mfloat }, +{"fbngle", one(0xF098), one(0xF1FF), "IdBW", mfloat }, +{"fbngt", one(0xF09D), one(0xF1FF), "IdBW", mfloat }, +{"fbnle", one(0xF09A), one(0xF1FF), "IdBW", mfloat }, +{"fbnlt", one(0xF09B), one(0xF1FF), "IdBW", mfloat }, +{"fboge", one(0xF083), one(0xF1FF), "IdBW", mfloat }, +{"fbogl", one(0xF086), one(0xF1FF), "IdBW", mfloat }, +{"fbogt", one(0xF082), one(0xF1FF), "IdBW", mfloat }, +{"fbole", one(0xF085), one(0xF1FF), "IdBW", mfloat }, +{"fbolt", one(0xF084), one(0xF1FF), "IdBW", mfloat }, +{"fbor", one(0xF087), one(0xF1FF), "IdBW", mfloat }, +{"fbseq", one(0xF091), one(0xF1FF), "IdBW", mfloat }, +{"fbsf", one(0xF090), one(0xF1FF), "IdBW", mfloat }, +{"fbsne", one(0xF09E), one(0xF1FF), "IdBW", mfloat }, +{"fbst", one(0xF09F), one(0xF1FF), "IdBW", mfloat }, +{"fbt", one(0xF08F), one(0xF1FF), "IdBW", mfloat }, +{"fbueq", one(0xF089), one(0xF1FF), "IdBW", mfloat }, +{"fbuge", one(0xF08B), one(0xF1FF), "IdBW", mfloat }, +{"fbugt", one(0xF08A), one(0xF1FF), "IdBW", mfloat }, +{"fbule", one(0xF08D), one(0xF1FF), "IdBW", mfloat }, +{"fbult", one(0xF08C), one(0xF1FF), "IdBW", mfloat }, +{"fbun", one(0xF088), one(0xF1FF), "IdBW", mfloat }, + +{"fbeql", one(0xF0C1), one(0xF1FF), "IdBC", mfloat }, +{"fbfl", one(0xF0C0), one(0xF1FF), "IdBC", mfloat }, +{"fbgel", one(0xF0D3), one(0xF1FF), "IdBC", mfloat }, +{"fbgll", one(0xF0D6), one(0xF1FF), "IdBC", mfloat }, +{"fbglel", one(0xF0D7), one(0xF1FF), "IdBC", mfloat }, +{"fbgtl", one(0xF0D2), one(0xF1FF), "IdBC", mfloat }, +{"fblel", one(0xF0D5), one(0xF1FF), "IdBC", mfloat }, +{"fbltl", one(0xF0D4), one(0xF1FF), "IdBC", mfloat }, +{"fbnel", one(0xF0CE), one(0xF1FF), "IdBC", mfloat }, +{"fbngel", one(0xF0DC), one(0xF1FF), "IdBC", mfloat }, +{"fbngll", one(0xF0D9), one(0xF1FF), "IdBC", mfloat }, +{"fbnglel", one(0xF0D8), one(0xF1FF), "IdBC", mfloat }, +{"fbngtl", one(0xF0DD), one(0xF1FF), "IdBC", mfloat }, +{"fbnlel", one(0xF0DA), one(0xF1FF), "IdBC", mfloat }, +{"fbnltl", one(0xF0DB), one(0xF1FF), "IdBC", mfloat }, +{"fbogel", one(0xF0C3), one(0xF1FF), "IdBC", mfloat }, +{"fbogll", one(0xF0C6), one(0xF1FF), "IdBC", mfloat }, +{"fbogtl", one(0xF0C2), one(0xF1FF), "IdBC", mfloat }, +{"fbolel", one(0xF0C5), one(0xF1FF), "IdBC", mfloat }, +{"fboltl", one(0xF0C4), one(0xF1FF), "IdBC", mfloat }, +{"fborl", one(0xF0C7), one(0xF1FF), "IdBC", mfloat }, +{"fbseql", one(0xF0D1), one(0xF1FF), "IdBC", mfloat }, +{"fbsfl", one(0xF0D0), one(0xF1FF), "IdBC", mfloat }, +{"fbsnel", one(0xF0DE), one(0xF1FF), "IdBC", mfloat }, +{"fbstl", one(0xF0DF), one(0xF1FF), "IdBC", mfloat }, +{"fbtl", one(0xF0CF), one(0xF1FF), "IdBC", mfloat }, +{"fbueql", one(0xF0C9), one(0xF1FF), "IdBC", mfloat }, +{"fbugel", one(0xF0CB), one(0xF1FF), "IdBC", mfloat }, +{"fbugtl", one(0xF0CA), one(0xF1FF), "IdBC", mfloat }, +{"fbulel", one(0xF0CD), one(0xF1FF), "IdBC", mfloat }, +{"fbultl", one(0xF0CC), one(0xF1FF), "IdBC", mfloat }, +{"fbunl", one(0xF0C8), one(0xF1FF), "IdBC", mfloat }, + +{"fjeq", one(0xF081), one(0xF1BF), "IdBc", mfloat }, +{"fjf", one(0xF080), one(0xF1BF), "IdBc", mfloat }, +{"fjge", one(0xF093), one(0xF1BF), "IdBc", mfloat }, +{"fjgl", one(0xF096), one(0xF1BF), "IdBc", mfloat }, +{"fjgle", one(0xF097), one(0xF1BF), "IdBc", mfloat }, +{"fjgt", one(0xF092), one(0xF1BF), "IdBc", mfloat }, +{"fjle", one(0xF095), one(0xF1BF), "IdBc", mfloat }, +{"fjlt", one(0xF094), one(0xF1BF), "IdBc", mfloat }, +{"fjne", one(0xF08E), one(0xF1BF), "IdBc", mfloat }, +{"fjnge", one(0xF09C), one(0xF1BF), "IdBc", mfloat }, +{"fjngl", one(0xF099), one(0xF1BF), "IdBc", mfloat }, +{"fjngle", one(0xF098), one(0xF1BF), "IdBc", mfloat }, +{"fjngt", one(0xF09D), one(0xF1BF), "IdBc", mfloat }, +{"fjnle", one(0xF09A), one(0xF1BF), "IdBc", mfloat }, +{"fjnlt", one(0xF09B), one(0xF1BF), "IdBc", mfloat }, +{"fjoge", one(0xF083), one(0xF1BF), "IdBc", mfloat }, +{"fjogl", one(0xF086), one(0xF1BF), "IdBc", mfloat }, +{"fjogt", one(0xF082), one(0xF1BF), "IdBc", mfloat }, +{"fjole", one(0xF085), one(0xF1BF), "IdBc", mfloat }, +{"fjolt", one(0xF084), one(0xF1BF), "IdBc", mfloat }, +{"fjor", one(0xF087), one(0xF1BF), "IdBc", mfloat }, +{"fjseq", one(0xF091), one(0xF1BF), "IdBc", mfloat }, +{"fjsf", one(0xF090), one(0xF1BF), "IdBc", mfloat }, +{"fjsne", one(0xF09E), one(0xF1BF), "IdBc", mfloat }, +{"fjst", one(0xF09F), one(0xF1BF), "IdBc", mfloat }, +{"fjt", one(0xF08F), one(0xF1BF), "IdBc", mfloat }, +{"fjueq", one(0xF089), one(0xF1BF), "IdBc", mfloat }, +{"fjuge", one(0xF08B), one(0xF1BF), "IdBc", mfloat }, +{"fjugt", one(0xF08A), one(0xF1BF), "IdBc", mfloat }, +{"fjule", one(0xF08D), one(0xF1BF), "IdBc", mfloat }, +{"fjult", one(0xF08C), one(0xF1BF), "IdBc", mfloat }, +{"fjun", one(0xF088), one(0xF1BF), "IdBc", mfloat }, + +{"fcmpb", two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fcmpd", two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fcmpl", two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fcmpp", two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fcmps", two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fcmpw", two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fcmpx", two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fcmpx", two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fcosb", two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fcosd", two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fcosl", two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fcosp", two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fcoss", two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fcosw", two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fcosx", two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fcosx", two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fcosx", two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fcoshb", two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fcoshd", two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fcoshl", two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fcoshp", two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fcoshs", two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fcoshw", two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fcoshx", two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fcoshx", two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fcoshx", two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fdbeq", two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbf", two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbge", two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbgl", two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbgle", two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbgt", two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdble", two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdblt", two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbne", two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbnge", two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbngl", two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbngle", two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbngt", two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbnle", two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbnlt", two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdboge", two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbogl", two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbogt", two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbole", two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbolt", two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbor", two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbseq", two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbsf", two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbsne", two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbst", two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbt", two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbueq", two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbuge", two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbugt", two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbule", two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbult", two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbun", two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, + +{"fdivb", two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fdivd", two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fdivl", two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fdivp", two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fdivs", two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fdivw", two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fdivx", two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fdivx", two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fsdivb", two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsdivd", two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsdivl", two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsdivp", two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsdivs", two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsdivw", two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsdivx", two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsdivx", two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fddivb", two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fddivd", two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fddivl", two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fddivp", two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fddivs", two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fddivw", two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fddivx", two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fddivx", two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fetoxb", two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fetoxd", two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fetoxl", two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fetoxp", two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fetoxs", two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fetoxw", two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fetoxx", two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fetoxx", two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fetoxx", two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fetoxm1b", two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fetoxm1d", two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fetoxm1l", two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fetoxm1p", two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fetoxm1s", two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fetoxm1w", two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fetoxm1x", two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fetoxm1x", two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fetoxm1x", two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fgetexpb", two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fgetexpd", two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fgetexpl", two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fgetexpp", two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fgetexps", two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fgetexpw", two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fgetexpx", two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fgetexpx", two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fgetexpx", two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fgetmanb", two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fgetmand", two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fgetmanl", two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fgetmanp", two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fgetmans", two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fgetmanw", two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fgetmanx", two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fgetmanx", two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fgetmanx", two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fintb", two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fintd", two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fintl", two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fintp", two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fints", two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fintw", two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fintx", two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fintx", two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fintx", two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fintrzb", two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fintrzd", two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fintrzl", two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fintrzp", two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fintrzs", two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fintrzw", two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fintrzx", two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fintrzx", two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fintrzx", two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flog10b", two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flog10d", two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flog10l", two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flog10p", two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flog10s", two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flog10w", two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flog10x", two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flog10x", two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flog10x", two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flog2b", two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flog2d", two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flog2l", two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flog2p", two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flog2s", two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flog2w", two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flog2x", two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flog2x", two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flog2x", two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flognb", two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flognd", two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flognl", two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flognp", two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flogns", two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flognw", two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flognx", two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flognx", two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flognx", two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flognp1b", two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flognp1d", two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flognp1l", two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flognp1p", two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flognp1s", two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flognp1w", two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flognp1x", two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flognp1x", two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flognp1x", two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fmodb", two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fmodd", two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fmodl", two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fmodp", two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fmods", two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fmodw", two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fmodx", two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fmodx", two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fmoveb", two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fmoveb", two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, +{"fmoved", two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fmoved", two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, +{"fmovel", two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fmovel", two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, +/* FIXME: the next two variants should not permit moving an address + register to anything but the floating point instruction register. */ +{"fmovel", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{"fmovel", two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, +{"fmovep", two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fmovep", two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, +{"fmovep", two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, +{"fmoves", two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fmoves", two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, +{"fmovew", two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fmovew", two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, +{"fmovex", two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, +{"fmovex", two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fmovex", two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, + +{"fsmoveb", two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsmoved", two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsmovel", two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsmoves", two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsmovew", two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsmovex", two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsmovex", two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fsmovep", two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, + +{"fdmoveb", two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdmoved", two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdmovel", two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdmoves", two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdmovew", two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdmovex", two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdmovex", two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdmovep", two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, + +{"fmovecrx", two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, + +{"fmovemx", two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, +{"fmovemx", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, +{"fmovemx", two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, +{"fmovemx", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, +{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, +{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, +{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, +{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, +{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, +{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, +{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, +{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, + +{"fmoveml", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{"fmoveml", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, +/* FIXME: In the next instruction, we should only permit %dn if the + target is a single register. We should only permit %an if the + target is a single %fpiar. */ +{"fmoveml", two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, + +{"fmovem", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, +{"fmovem", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, +{"fmovem", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, +{"fmovem", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, +{"fmovem", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, +{"fmovem", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, +{"fmovem", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, +{"fmovem", two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, +{"fmovem", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, +{"fmovem", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, +{"fmovem", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, +{"fmovem", two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, +{"fmovem", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{"fmovem", two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, +{"fmovem", two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, +{"fmovem", two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, + +{"fmulb", two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fmuld", two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fmull", two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fmulp", two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fmuls", two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fmulw", two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fmulx", two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fmulx", two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fsmulb", two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsmuld", two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsmull", two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsmulp", two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsmuls", two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsmulw", two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsmulx", two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsmulx", two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fdmulb", two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdmuld", two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdmull", two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdmulp", two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdmuls", two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdmulw", two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdmulx", two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdmulx", two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fnegb", two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fnegd", two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fnegl", two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fnegp", two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fnegs", two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fnegw", two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fnegx", two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fnegx", two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fnegx", two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsnegb", two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsnegd", two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsnegl", two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsnegp", two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsnegs", two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsnegw", two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsnegx", two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsnegx", two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fsnegx", two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdnegb", two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdnegd", two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdnegl", two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdnegp", two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdnegs", two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdnegw", two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdnegx", two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdnegx", two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdnegx", two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fnop", two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat }, + +{"fremb", two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fremd", two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"freml", two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fremp", two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"frems", two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fremw", two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fremx", two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fremx", two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"frestore", one(0xF140), one(0xF1C0), "Ids", mfloat }, + +{"fscaleb", two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fscaled", two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fscalel", two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fscalep", two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fscales", two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fscalew", two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fscalex", two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fscalex", two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +/* $ is necessary to prevent the assembler from using PC-relative. + If @ were used, "label: fseq label" could produce "ftrapeq", + because "label" became "pc@label". */ +{"fseq", two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsf", two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsge", two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsgl", two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsgle", two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsgt", two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsle", two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fslt", two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsne", two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsnge", two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsngl", two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsngle", two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsngt", two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsnle", two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsnlt", two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsoge", two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsogl", two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsogt", two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsole", two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsolt", two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsor", two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsseq", two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fssf", two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fssne", two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsst", two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fst", two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsueq", two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsuge", two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsugt", two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsule", two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsult", two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsun", two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, + +{"fsgldivb", two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsgldivd", two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsgldivl", two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsgldivp", two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsgldivs", two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsgldivw", two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsgldivx", two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsgldivx", two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsgldivx", two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsglmulb", two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsglmuld", two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsglmull", two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsglmulp", two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsglmuls", two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsglmulw", two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsglmulx", two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsglmulx", two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsglmulx", two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsinb", two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsind", two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsinl", two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsinp", two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsins", two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsinw", two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsinx", two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsinx", two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsinx", two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsincosb", two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, +{"fsincosd", two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, +{"fsincosl", two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, +{"fsincosp", two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, +{"fsincoss", two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, +{"fsincosw", two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, +{"fsincosx", two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, +{"fsincosx", two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, + +{"fsinhb", two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsinhd", two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsinhl", two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsinhp", two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsinhs", two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsinhw", two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsinhx", two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsinhx", two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsinhx", two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsqrtb", two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsqrtd", two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsqrtl", two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsqrtp", two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsqrts", two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsqrtw", two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsqrtx", two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsqrtx", two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsqrtx", two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fssqrtb", two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fssqrtd", two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fssqrtl", two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fssqrtp", two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fssqrts", two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fssqrtw", two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fssqrtx", two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fssqrtx", two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fssqrtx", two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdsqrtb", two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdsqrtd", two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdsqrtl", two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdsqrtp", two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdsqrts", two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdsqrtw", two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdsqrtx", two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdsqrtx", two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdsqrtx", two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fsubb", two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsubd", two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsubl", two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsubp", two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsubs", two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsubw", two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsubx", two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsubx", two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsubx", two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fssubb", two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fssubd", two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fssubl", two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fssubp", two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fssubs", two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fssubw", two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fssubx", two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fssubx", two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fssubx", two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdsubb", two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdsubd", two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdsubl", two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdsubp", two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdsubs", two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdsubw", two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdsubx", two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdsubx", two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdsubx", two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"ftanb", two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftand", two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftanl", two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftanp", two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftans", two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftanw", two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftanx", two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftanx", two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftanx", two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"ftanhb", two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftanhd", two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftanhl", two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftanhp", two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftanhs", two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftanhw", two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftanhx", two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftanhx", two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftanhx", two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"ftentoxb", two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftentoxd", two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftentoxl", two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftentoxp", two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftentoxs", two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftentoxw", two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftentoxx", two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftentoxx", two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftentoxx", two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"ftrapeq", two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapf", two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapge", two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapgl", two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapgle", two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapgt", two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftraple", two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftraplt", two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapne", two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapnge", two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapngl", two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapngle", two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapngt", two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapnle", two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapnlt", two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapoge", two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapogl", two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapogt", two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapole", two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapolt", two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapor", two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapseq", two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapsf", two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapsne", two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapst", two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapt", two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapueq", two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapuge", two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapugt", two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapule", two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapult", two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapun", two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, + +{"ftrapeqw", two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapfw", two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapgew", two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapglw", two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapglew", two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapgtw", two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftraplew", two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapltw", two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnew", two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapngew", two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnglw", two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnglew", two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapngtw", two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnlew", two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnltw", two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapogew", two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapoglw", two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapogtw", two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapolew", two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapoltw", two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftraporw", two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapseqw", two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapsfw", two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapsnew", two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapstw", two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftraptw", two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapueqw", two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapugew", two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapugtw", two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapulew", two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapultw", two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapunw", two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, + +{"ftrapeql", two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapfl", two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapgel", two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapgll", two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapglel", two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapgtl", two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftraplel", two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapltl", two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnel", two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapngel", two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapngll", two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnglel", two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapngtl", two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnlel", two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnltl", two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapogel", two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapogll", two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapogtl", two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapolel", two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapoltl", two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftraporl", two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapseql", two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapsfl", two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapsnel", two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapstl", two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftraptl", two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapueql", two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapugel", two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapugtl", two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapulel", two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapultl", two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapunl", two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, + +{"ftstb", two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, +{"ftstd", two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, +{"ftstl", two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, +{"ftstp", two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, +{"ftsts", two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, +{"ftstw", two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, +{"ftstx", two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, +{"ftstx", two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, + +{"ftwotoxb", two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftwotoxd", two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftwotoxl", two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftwotoxp", two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftwotoxs", two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftwotoxw", two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftwotoxx", two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftwotoxx", two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftwotoxx", two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"halt", one(0045310), one(0177777), "", m68060 | mcf }, + +{"illegal", one(0045374), one(0177777), "", m68000up }, + +{"jmp", one(0047300), one(0177700), "!s", m68000up | mcf }, + +{"jra", one(0060000), one(0177400), "Bg", m68000up | mcf }, +{"jra", one(0047300), one(0177700), "!s", m68000up | mcf }, + +{"jsr", one(0047200), one(0177700), "!s", m68000up | mcf }, + +{"jbsr", one(0060400), one(0177400), "Bg", m68000up | mcf }, +{"jbsr", one(0047200), one(0177700), "!s", m68000up | mcf }, + +{"lea", one(0040700), one(0170700), "!sAd", m68000up | mcf }, + +{"lpstop", two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 }, + +{"linkw", one(0047120), one(0177770), "As#w", m68000up | mcf }, +{"linkl", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, +{"link", one(0047120), one(0177770), "As#W", m68000up | mcf }, +{"link", one(0044010), one(0177770), "As#l", m68020up | cpu32 }, + +{"lslb", one(0160410), one(0170770), "QdDs", m68000up }, +{"lslb", one(0160450), one(0170770), "DdDs", m68000up }, +{"lslw", one(0160510), one(0170770), "QdDs", m68000up }, +{"lslw", one(0160550), one(0170770), "DdDs", m68000up }, +{"lslw", one(0161700), one(0177700), "~s", m68000up }, +{"lsll", one(0160610), one(0170770), "QdDs", m68000up | mcf }, +{"lsll", one(0160650), one(0170770), "DdDs", m68000up | mcf }, + +{"lsrb", one(0160010), one(0170770), "QdDs", m68000up }, +{"lsrb", one(0160050), one(0170770), "DdDs", m68000up }, +{"lsrw", one(0160110), one(0170770), "QdDs", m68000up }, +{"lsrw", one(0160150), one(0170770), "DdDs", m68000up }, +{"lsrw", one(0161300), one(0177700), "~s", m68000up }, +{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf }, +{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf }, + + /* FIXME: add MAM mode (`&' after operand) / remove MACM */ +{"macw", two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5307up | mcf5206e }, +{"macw", two(0120000, 0001000), two(0170660, 0005400), "uMumMh",mcf5307up | mcf5206e }, +{"macw", two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e }, +{"macw", two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e }, +{"macw", two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e }, +{"macw", two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e }, +{"macw", two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e }, +{"macw", two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e }, +{"macw", two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e }, +{"macw", two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e }, +{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e }, +{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e }, +{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e }, +{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e }, +{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e }, +{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e }, +{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e }, +{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e }, + +{"macl", two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5307up | mcf5206e }, +{"macl", two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5307up | mcf5206e }, +{"macl", two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e }, +{"macl", two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e }, +{"macl", two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e }, +{"macl", two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e }, +{"macl", two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e }, +{"macl", two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e }, +{"macl", two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e }, +{"macl", two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e }, +{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e }, +{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e }, +{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e }, +{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e }, +{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e }, +{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e }, +{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e }, +{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e }, + +/* NOTE: The mcf5200 family programmer's reference manual does not + indicate the byte form of the movea instruction is invalid (as it + is on 68000 family cpus). However, experiments on the 5202 yeild + unexpected results. The value is copied, but it is not sign extended + (as is done with movea.w) and the top three bytes in the address + register are not disturbed. I don't know if this is the intended + behavior --- it could be a hole in instruction decoding (Motorola + decided not to trap all invalid instructions for performance reasons) + --- but I suspect that it is not. + + I reported this to Motorola ISD Technical Communications Support, + which replied that other coldfire assemblers reject movea.b. For + this reason I've decided to not allow moveab. + + jtc@cygnus.com - 97/01/24 + */ + +{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf }, +{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf }, + +{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcf }, +{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcf }, +{"movec", one(0047172), one(0177777), "JjR1", m68010up }, +{"movec", one(0047172), one(0177777), "#jR1", m68010up }, + +{"movemw", one(0044200), one(0177700), "Lw&s", m68000up }, +{"movemw", one(0044240), one(0177770), "lw-s", m68000up }, +{"movemw", one(0044200), one(0177700), "#w>s", m68000up }, +{"movemw", one(0046200), one(0177700), "s", m68000up }, +{"moveml", one(0046300), one(0177700), " operand) / remove MSACM */ +{"msacw", two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5307up | mcf5206e }, +{"msacw", two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5307up | mcf5206e }, +{"msacw", two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e }, +{"msacw", two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e }, +{"msacw", two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e }, +{"msacw", two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e }, +{"msacw", two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e }, +{"msacw", two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e }, +{"msacw", two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e }, +{"msacw", two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5307up | mcf5206e }, +{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5307up | mcf5206e }, + +{"msacl", two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5307up | mcf5206e }, +{"msacl", two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5307up | mcf5206e }, +{"msacl", two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e }, +{"msacl", two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e }, +{"msacl", two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e }, +{"msacl", two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e }, +{"msacl", two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e }, +{"msacl", two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e }, +{"msacl", two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e }, +{"msacl", two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e }, +{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5307up | mcf5206e }, +{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5307up | mcf5206e }, +{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5307up | mcf5206e }, +{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5307up | mcf5206e }, +{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5307up | mcf5206e }, +{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5307up | mcf5206e }, +{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5307up | mcf5206e }, +{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5307up | mcf5206e }, + +{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf }, +{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, +{"mulsl", two(0046000,004000), two(0177700,0107770), "qsD1", mcf }, +{"mulsl", two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, + +{"muluw", one(0140300), one(0170700), ";wDd", m68000up|mcf }, +{"mulul", two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, +{"mulul", two(0046000,000000), two(0177700,0107770), "qsD1", mcf }, +{"mulul", two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, + +{"nbcd", one(0044000), one(0177700), "$s", m68000up }, + +{"negb", one(0042000), one(0177700), "$s", m68000up }, +{"negw", one(0042100), one(0177700), "$s", m68000up }, +{"negl", one(0042200), one(0177700), "$s", m68000up }, +{"negl", one(0042200), one(0177700), "Ds", mcf}, + +{"negxb", one(0040000), one(0177700), "$s", m68000up }, +{"negxw", one(0040100), one(0177700), "$s", m68000up }, +{"negxl", one(0040200), one(0177700), "$s", m68000up }, +{"negxl", one(0040200), one(0177700), "Ds", mcf}, + +{"nop", one(0047161), one(0177777), "", m68000up | mcf}, + +{"notb", one(0043000), one(0177700), "$s", m68000up }, +{"notw", one(0043100), one(0177700), "$s", m68000up }, +{"notl", one(0043200), one(0177700), "$s", m68000up }, +{"notl", one(0043200), one(0177700), "Ds", mcf}, + +{"orib", one(0000000), one(0177700), "#b$s", m68000up }, +{"orib", one(0000074), one(0177777), "#bCs", m68000up }, +{"oriw", one(0000100), one(0177700), "#w$s", m68000up }, +{"oriw", one(0000174), one(0177777), "#wSs", m68000up }, +{"oril", one(0000200), one(0177700), "#l$s", m68000up }, +{"oril", one(0000200), one(0177700), "#lDs", mcf }, +{"ori", one(0000074), one(0177777), "#bCs", m68000up }, +{"ori", one(0000100), one(0177700), "#w$s", m68000up }, +{"ori", one(0000174), one(0177777), "#wSs", m68000up }, + +/* The or opcode can generate the ori instruction. */ +{"orb", one(0000000), one(0177700), "#b$s", m68000up }, +{"orb", one(0000074), one(0177777), "#bCs", m68000up }, +{"orb", one(0100000), one(0170700), ";bDd", m68000up }, +{"orb", one(0100400), one(0170700), "Dd~s", m68000up }, +{"orw", one(0000100), one(0177700), "#w$s", m68000up }, +{"orw", one(0000174), one(0177777), "#wSs", m68000up }, +{"orw", one(0100100), one(0170700), ";wDd", m68000up }, +{"orw", one(0100500), one(0170700), "Dd~s", m68000up }, +{"orl", one(0000200), one(0177700), "#l$s", m68000up }, +{"orl", one(0000200), one(0177700), "#lDs", mcf }, +{"orl", one(0100200), one(0170700), ";lDd", m68000up | mcf }, +{"orl", one(0100600), one(0170700), "Dd~s", m68000up | mcf }, +{"or", one(0000074), one(0177777), "#bCs", m68000up }, +{"or", one(0000100), one(0177700), "#w$s", m68000up }, +{"or", one(0000174), one(0177777), "#wSs", m68000up }, +{"or", one(0100100), one(0170700), ";wDd", m68000up }, +{"or", one(0100500), one(0170700), "Dd~s", m68000up }, + +{"pack", one(0100500), one(0170770), "DsDd#w", m68020up }, +{"pack", one(0100510), one(0170770), "-s-d#w", m68020up }, + +{"pbac", one(0xf087), one(0xffbf), "Bc", m68851 }, +{"pbacw", one(0xf087), one(0xffff), "BW", m68851 }, +{"pbas", one(0xf086), one(0xffbf), "Bc", m68851 }, +{"pbasw", one(0xf086), one(0xffff), "BW", m68851 }, +{"pbbc", one(0xf081), one(0xffbf), "Bc", m68851 }, +{"pbbcw", one(0xf081), one(0xffff), "BW", m68851 }, +{"pbbs", one(0xf080), one(0xffbf), "Bc", m68851 }, +{"pbbsw", one(0xf080), one(0xffff), "BW", m68851 }, +{"pbcc", one(0xf08f), one(0xffbf), "Bc", m68851 }, +{"pbccw", one(0xf08f), one(0xffff), "BW", m68851 }, +{"pbcs", one(0xf08e), one(0xffbf), "Bc", m68851 }, +{"pbcsw", one(0xf08e), one(0xffff), "BW", m68851 }, +{"pbgc", one(0xf08d), one(0xffbf), "Bc", m68851 }, +{"pbgcw", one(0xf08d), one(0xffff), "BW", m68851 }, +{"pbgs", one(0xf08c), one(0xffbf), "Bc", m68851 }, +{"pbgsw", one(0xf08c), one(0xffff), "BW", m68851 }, +{"pbic", one(0xf08b), one(0xffbf), "Bc", m68851 }, +{"pbicw", one(0xf08b), one(0xffff), "BW", m68851 }, +{"pbis", one(0xf08a), one(0xffbf), "Bc", m68851 }, +{"pbisw", one(0xf08a), one(0xffff), "BW", m68851 }, +{"pblc", one(0xf083), one(0xffbf), "Bc", m68851 }, +{"pblcw", one(0xf083), one(0xffff), "BW", m68851 }, +{"pbls", one(0xf082), one(0xffbf), "Bc", m68851 }, +{"pblsw", one(0xf082), one(0xffff), "BW", m68851 }, +{"pbsc", one(0xf085), one(0xffbf), "Bc", m68851 }, +{"pbscw", one(0xf085), one(0xffff), "BW", m68851 }, +{"pbss", one(0xf084), one(0xffbf), "Bc", m68851 }, +{"pbssw", one(0xf084), one(0xffff), "BW", m68851 }, +{"pbwc", one(0xf089), one(0xffbf), "Bc", m68851 }, +{"pbwcw", one(0xf089), one(0xffff), "BW", m68851 }, +{"pbws", one(0xf088), one(0xffbf), "Bc", m68851 }, +{"pbwsw", one(0xf088), one(0xffff), "BW", m68851 }, + +{"pdbac", two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbas", two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbbc", two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbbs", two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbcc", two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbcs", two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbgc", two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbgs", two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbic", two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbis", two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdblc", two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbls", two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbsc", two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbss", two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbwc", two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbws", two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, + +{"pea", one(0044100), one(0177700), "!s", m68000up|mcf }, + +{"pflusha", one(0xf518), one(0xfff8), "", m68040up }, +{"pflusha", two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, + +{"pflush", two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, +{"pflush", two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, +{"pflush", two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, +{"pflush", two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, +{"pflush", two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, +{"pflush", two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, +{"pflush", one(0xf508), one(0xfff8), "as", m68040up }, +{"pflush", one(0xf508), one(0xfff8), "As", m68040up }, + +{"pflushan", one(0xf510), one(0xfff8), "", m68040up }, +{"pflushn", one(0xf500), one(0xfff8), "as", m68040up }, +{"pflushn", one(0xf500), one(0xfff8), "As", m68040up }, + +{"pflushr", two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, + +{"pflushs", two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, +{"pflushs", two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, +{"pflushs", two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, +{"pflushs", two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, +{"pflushs", two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, +{"pflushs", two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, + +{"ploadr", two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, +{"ploadr", two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, +{"ploadr", two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, +{"ploadw", two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, +{"ploadw", two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, +{"ploadw", two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, + +{"plpar", one(0xf5c8), one(0xfff8), "as", m68060 }, +{"plpaw", one(0xf588), one(0xfff8), "as", m68060 }, + +{"pmove", two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, +{"pmove", two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, +{"pmove", two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, +{"pmove", two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, +{"pmove", two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, +{"pmove", two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, +{"pmove", two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, +{"pmove", two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, +{"pmove", two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 }, +{"pmove", two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 }, +{"pmove", two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, +{"pmove", two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, +{"pmove", two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, +{"pmove", two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, +{"pmove", two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, + +{"pmovefd", two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, +{"pmovefd", two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, +{"pmovefd", two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, + +{"prestore", one(0xf140), one(0xffc0), "s", m68851 }, + +{"psac", two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, +{"psas", two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, +{"psbc", two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, +{"psbs", two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, +{"pscc", two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, +{"pscs", two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, +{"psgc", two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, +{"psgs", two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, +{"psic", two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, +{"psis", two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, +{"pslc", two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, +{"psls", two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, +{"pssc", two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, +{"psss", two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, +{"pswc", two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, +{"psws", two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, + +{"ptestr", two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, +{"ptestr", two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, +{"ptestr", two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, +{"ptestr", two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, +{"ptestr", two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, +{"ptestr", two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, +{"ptestr", one(0xf568), one(0xfff8), "as", m68040 }, + +{"ptestw", two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, +{"ptestw", two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, +{"ptestw", two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, +{"ptestw", two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, +{"ptestw", two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, +{"ptestw", two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, +{"ptestw", one(0xf548), one(0xfff8), "as", m68040 }, + +{"ptrapacw", two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapacl", two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapac", two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapasw", two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapasl", two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapas", two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapbcw", two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapbcl", two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapbc", two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapbsw", two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapbsl", two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapbs", two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapccw", two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapccl", two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapcc", two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapcsw", two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapcsl", two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapcs", two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapgcw", two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapgcl", two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapgc", two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapgsw", two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapgsl", two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapgs", two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapicw", two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapicl", two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapic", two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapisw", two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapisl", two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapis", two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, + +{"ptraplcw", two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, +{"ptraplcl", two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, +{"ptraplc", two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, + +{"ptraplsw", two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, +{"ptraplsl", two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapls", two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapscw", two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapscl", two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapsc", two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapssw", two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapssl", two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapss", two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapwcw", two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapwcl", two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapwc", two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapwsw", two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapwsl", two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapws", two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, + +{"pulse", one(0045314), one(0177777), "", m68060 | mcf }, + +{"pvalid", two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, +{"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, + + /* FIXME: don't allow Dw==Dx. */ +{"remsl", two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e }, +{"remul", two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e }, + +{"reset", one(0047160), one(0177777), "", m68000up }, + +{"rolb", one(0160430), one(0170770), "QdDs", m68000up }, +{"rolb", one(0160470), one(0170770), "DdDs", m68000up }, +{"rolw", one(0160530), one(0170770), "QdDs", m68000up }, +{"rolw", one(0160570), one(0170770), "DdDs", m68000up }, +{"rolw", one(0163700), one(0177700), "~s", m68000up }, +{"roll", one(0160630), one(0170770), "QdDs", m68000up }, +{"roll", one(0160670), one(0170770), "DdDs", m68000up }, + +{"rorb", one(0160030), one(0170770), "QdDs", m68000up }, +{"rorb", one(0160070), one(0170770), "DdDs", m68000up }, +{"rorw", one(0160130), one(0170770), "QdDs", m68000up }, +{"rorw", one(0160170), one(0170770), "DdDs", m68000up }, +{"rorw", one(0163300), one(0177700), "~s", m68000up }, +{"rorl", one(0160230), one(0170770), "QdDs", m68000up }, +{"rorl", one(0160270), one(0170770), "DdDs", m68000up }, + +{"roxlb", one(0160420), one(0170770), "QdDs", m68000up }, +{"roxlb", one(0160460), one(0170770), "DdDs", m68000up }, +{"roxlw", one(0160520), one(0170770), "QdDs", m68000up }, +{"roxlw", one(0160560), one(0170770), "DdDs", m68000up }, +{"roxlw", one(0162700), one(0177700), "~s", m68000up }, +{"roxll", one(0160620), one(0170770), "QdDs", m68000up }, +{"roxll", one(0160660), one(0170770), "DdDs", m68000up }, + +{"roxrb", one(0160020), one(0170770), "QdDs", m68000up }, +{"roxrb", one(0160060), one(0170770), "DdDs", m68000up }, +{"roxrw", one(0160120), one(0170770), "QdDs", m68000up }, +{"roxrw", one(0160160), one(0170770), "DdDs", m68000up }, +{"roxrw", one(0162300), one(0177700), "~s", m68000up }, +{"roxrl", one(0160220), one(0170770), "QdDs", m68000up }, +{"roxrl", one(0160260), one(0170770), "DdDs", m68000up }, + +{"rtd", one(0047164), one(0177777), "#w", m68010up }, + +{"rte", one(0047163), one(0177777), "", m68000up | mcf }, + +{"rtm", one(0003300), one(0177760), "Rs", m68020 }, + +{"rtr", one(0047167), one(0177777), "", m68000up }, + +{"rts", one(0047165), one(0177777), "", m68000up | mcf }, + +{"satsl", one(0046200), one(0177770), "Ds", mcf5407 }, + +{"sbcd", one(0100400), one(0170770), "DsDd", m68000up }, +{"sbcd", one(0100410), one(0170770), "-s-d", m68000up }, + +{"scc", one(0052300), one(0177700), "$s", m68000up }, +{"scc", one(0052300), one(0177700), "Ds", mcf }, +{"scs", one(0052700), one(0177700), "$s", m68000up }, +{"scs", one(0052700), one(0177700), "Ds", mcf }, +{"seq", one(0053700), one(0177700), "$s", m68000up }, +{"seq", one(0053700), one(0177700), "Ds", mcf }, +{"sf", one(0050700), one(0177700), "$s", m68000up }, +{"sf", one(0050700), one(0177700), "Ds", mcf }, +{"sge", one(0056300), one(0177700), "$s", m68000up }, +{"sge", one(0056300), one(0177700), "Ds", mcf }, +{"sgt", one(0057300), one(0177700), "$s", m68000up }, +{"sgt", one(0057300), one(0177700), "Ds", mcf }, +{"shi", one(0051300), one(0177700), "$s", m68000up }, +{"shi", one(0051300), one(0177700), "Ds", mcf }, +{"sle", one(0057700), one(0177700), "$s", m68000up }, +{"sle", one(0057700), one(0177700), "Ds", mcf }, +{"sls", one(0051700), one(0177700), "$s", m68000up }, +{"sls", one(0051700), one(0177700), "Ds", mcf }, +{"slt", one(0056700), one(0177700), "$s", m68000up }, +{"slt", one(0056700), one(0177700), "Ds", mcf }, +{"smi", one(0055700), one(0177700), "$s", m68000up }, +{"smi", one(0055700), one(0177700), "Ds", mcf }, +{"sne", one(0053300), one(0177700), "$s", m68000up }, +{"sne", one(0053300), one(0177700), "Ds", mcf }, +{"spl", one(0055300), one(0177700), "$s", m68000up }, +{"spl", one(0055300), one(0177700), "Ds", mcf }, +{"st", one(0050300), one(0177700), "$s", m68000up }, +{"st", one(0050300), one(0177700), "Ds", mcf }, +{"svc", one(0054300), one(0177700), "$s", m68000up }, +{"svc", one(0054300), one(0177700), "Ds", mcf }, +{"svs", one(0054700), one(0177700), "$s", m68000up }, +{"svs", one(0054700), one(0177700), "Ds", mcf }, + +{"stop", one(0047162), one(0177777), "#w", m68000up | mcf }, + +{"subal", one(0110700), one(0170700), "*lAd", m68000up | mcf }, +{"subaw", one(0110300), one(0170700), "*wAd", m68000up }, + +{"subib", one(0002000), one(0177700), "#b$s", m68000up }, +{"subiw", one(0002100), one(0177700), "#w$s", m68000up }, +{"subil", one(0002200), one(0177700), "#l$s", m68000up }, +{"subil", one(0002200), one(0177700), "#lDs", mcf }, + +{"subqb", one(0050400), one(0170700), "Qd%s", m68000up }, +{"subqw", one(0050500), one(0170700), "Qd%s", m68000up }, +{"subql", one(0050600), one(0170700), "Qd%s", m68000up | mcf }, + +/* The sub opcode can generate the suba, subi, and subq instructions. */ +{"subb", one(0050400), one(0170700), "Qd%s", m68000up }, +{"subb", one(0002000), one(0177700), "#b$s", m68000up }, +{"subb", one(0110000), one(0170700), ";bDd", m68000up }, +{"subb", one(0110400), one(0170700), "Dd~s", m68000up }, +{"subw", one(0050500), one(0170700), "Qd%s", m68000up }, +{"subw", one(0002100), one(0177700), "#w$s", m68000up }, +{"subw", one(0110300), one(0170700), "*wAd", m68000up }, +{"subw", one(0110100), one(0170700), "*wDd", m68000up }, +{"subw", one(0110500), one(0170700), "Dd~s", m68000up }, +{"subl", one(0050600), one(0170700), "Qd%s", m68000up | mcf }, +{"subl", one(0002200), one(0177700), "#l$s", m68000up }, +{"subl", one(0002200), one(0177700), "#lDs", mcf }, +{"subl", one(0110700), one(0170700), "*lAd", m68000up | mcf }, +{"subl", one(0110200), one(0170700), "*lDd", m68000up | mcf }, +{"subl", one(0110600), one(0170700), "Dd~s", m68000up | mcf }, + +{"subxb", one(0110400), one(0170770), "DsDd", m68000up }, +{"subxb", one(0110410), one(0170770), "-s-d", m68000up }, +{"subxw", one(0110500), one(0170770), "DsDd", m68000up }, +{"subxw", one(0110510), one(0170770), "-s-d", m68000up }, +{"subxl", one(0110600), one(0170770), "DsDd", m68000up | mcf }, +{"subxl", one(0110610), one(0170770), "-s-d", m68000up }, + +{"swap", one(0044100), one(0177770), "Ds", m68000up | mcf }, + +/* swbeg and swbegl are magic constants used on sysV68. The compiler + generates them before a switch table. They tell the debugger and + disassembler that a switch table follows. The parameter is the + number of elements in the table. swbeg means that the entries in + the table are word (2 byte) sized, and swbegl means that the + entries in the table are longword (4 byte) sized. */ +{"swbeg", one(0045374), one(0177777), "#w", m68000up | mcf }, +{"swbegl", one(0045375), one(0177777), "#l", m68000up | mcf }, + +{"tas", one(0045300), one(0177700), "$s", m68000up | mcf5407}, + +#define TBL1(name,signed,round,size) \ + {name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \ + two(0177700,0107777), "!sD1", cpu32 }, \ + {name, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \ + two(0177770,0107770), "DsD3D1", cpu32 } +#define TBL(name1, name2, name3, s, r) \ + TBL1(name1, s, r, 0), TBL1(name2, s, r, 1), TBL1(name3, s, r, 2) +TBL("tblsb", "tblsw", "tblsl", 1, 1), +TBL("tblsnb", "tblsnw", "tblsnl", 1, 0), +TBL("tblub", "tbluw", "tblul", 0, 1), +TBL("tblunb", "tblunw", "tblunl", 0, 0), + +{"trap", one(0047100), one(0177760), "Ts", m68000up | mcf }, + +{"trapcc", one(0052374), one(0177777), "", m68020up | cpu32 }, +{"trapcs", one(0052774), one(0177777), "", m68020up | cpu32 }, +{"trapeq", one(0053774), one(0177777), "", m68020up | cpu32 }, +{"trapf", one(0050774), one(0177777), "", m68020up | cpu32 | mcf }, +{"trapge", one(0056374), one(0177777), "", m68020up | cpu32 }, +{"trapgt", one(0057374), one(0177777), "", m68020up | cpu32 }, +{"traphi", one(0051374), one(0177777), "", m68020up | cpu32 }, +{"traple", one(0057774), one(0177777), "", m68020up | cpu32 }, +{"trapls", one(0051774), one(0177777), "", m68020up | cpu32 }, +{"traplt", one(0056774), one(0177777), "", m68020up | cpu32 }, +{"trapmi", one(0055774), one(0177777), "", m68020up | cpu32 }, +{"trapne", one(0053374), one(0177777), "", m68020up | cpu32 }, +{"trappl", one(0055374), one(0177777), "", m68020up | cpu32 }, +{"trapt", one(0050374), one(0177777), "", m68020up | cpu32 }, +{"trapvc", one(0054374), one(0177777), "", m68020up | cpu32 }, +{"trapvs", one(0054774), one(0177777), "", m68020up | cpu32 }, + +{"trapccw", one(0052372), one(0177777), "#w", m68020up|cpu32 }, +{"trapcsw", one(0052772), one(0177777), "#w", m68020up|cpu32 }, +{"trapeqw", one(0053772), one(0177777), "#w", m68020up|cpu32 }, +{"trapfw", one(0050772), one(0177777), "#w", m68020up|cpu32|mcf}, +{"trapgew", one(0056372), one(0177777), "#w", m68020up|cpu32 }, +{"trapgtw", one(0057372), one(0177777), "#w", m68020up|cpu32 }, +{"traphiw", one(0051372), one(0177777), "#w", m68020up|cpu32 }, +{"traplew", one(0057772), one(0177777), "#w", m68020up|cpu32 }, +{"traplsw", one(0051772), one(0177777), "#w", m68020up|cpu32 }, +{"trapltw", one(0056772), one(0177777), "#w", m68020up|cpu32 }, +{"trapmiw", one(0055772), one(0177777), "#w", m68020up|cpu32 }, +{"trapnew", one(0053372), one(0177777), "#w", m68020up|cpu32 }, +{"trapplw", one(0055372), one(0177777), "#w", m68020up|cpu32 }, +{"traptw", one(0050372), one(0177777), "#w", m68020up|cpu32 }, +{"trapvcw", one(0054372), one(0177777), "#w", m68020up|cpu32 }, +{"trapvsw", one(0054772), one(0177777), "#w", m68020up|cpu32 }, + +{"trapccl", one(0052373), one(0177777), "#l", m68020up|cpu32 }, +{"trapcsl", one(0052773), one(0177777), "#l", m68020up|cpu32 }, +{"trapeql", one(0053773), one(0177777), "#l", m68020up|cpu32 }, +{"trapfl", one(0050773), one(0177777), "#l", m68020up|cpu32|mcf}, +{"trapgel", one(0056373), one(0177777), "#l", m68020up|cpu32 }, +{"trapgtl", one(0057373), one(0177777), "#l", m68020up|cpu32 }, +{"traphil", one(0051373), one(0177777), "#l", m68020up|cpu32 }, +{"traplel", one(0057773), one(0177777), "#l", m68020up|cpu32 }, +{"traplsl", one(0051773), one(0177777), "#l", m68020up|cpu32 }, +{"trapltl", one(0056773), one(0177777), "#l", m68020up|cpu32 }, +{"trapmil", one(0055773), one(0177777), "#l", m68020up|cpu32 }, +{"trapnel", one(0053373), one(0177777), "#l", m68020up|cpu32 }, +{"trappll", one(0055373), one(0177777), "#l", m68020up|cpu32 }, +{"traptl", one(0050373), one(0177777), "#l", m68020up|cpu32 }, +{"trapvcl", one(0054373), one(0177777), "#l", m68020up|cpu32 }, +{"trapvsl", one(0054773), one(0177777), "#l", m68020up|cpu32 }, + +{"trapv", one(0047166), one(0177777), "", m68000up }, + +{"tstb", one(0045000), one(0177700), ";b", m68020up|cpu32|mcf }, +{"tstb", one(0045000), one(0177700), "$b", m68000up }, +{"tstw", one(0045100), one(0177700), "*w", m68020up|cpu32|mcf }, +{"tstw", one(0045100), one(0177700), "$w", m68000up }, +{"tstl", one(0045200), one(0177700), "*l", m68020up|cpu32|mcf }, +{"tstl", one(0045200), one(0177700), "$l", m68000up }, + +{"unlk", one(0047130), one(0177770), "As", m68000up | mcf }, + +{"unpk", one(0100600), one(0170770), "DsDd#w", m68020up }, +{"unpk", one(0100610), one(0170770), "-s-d#w", m68020up }, + +{"wddatab", one(0175400), one(0177700), "~s", mcf }, +{"wddataw", one(0175500), one(0177700), "~s", mcf }, +{"wddatal", one(0175600), one(0177700), "~s", mcf }, + +{"wdebug", two(0175720, 03), two(0177770, 0xffff), "as", mcf }, +{"wdebug", two(0175750, 03), two(0177770, 0xffff), "ds", mcf }, +}; + +const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; + +/* These aliases used to be in the above table, each one duplicating + all of the entries for its primary exactly. This table was + constructed by mechanical processing of the opcode table, with a + small number of tweaks done by hand. There are probably a lot more + aliases above that could be moved down here, except for very minor + differences. */ + +const struct m68k_opcode_alias m68k_opcode_aliases[] = +{ + { "add", "addw", }, + { "adda", "addaw", }, + { "addi", "addiw", }, + { "addq", "addqw", }, + { "addx", "addxw", }, + { "asl", "aslw", }, + { "asr", "asrw", }, + { "bhi", "bhiw", }, + { "bls", "blsw", }, + { "bcc", "bccw", }, + { "bcs", "bcsw", }, + { "bne", "bnew", }, + { "beq", "beqw", }, + { "bvc", "bvcw", }, + { "bvs", "bvsw", }, + { "bpl", "bplw", }, + { "bmi", "bmiw", }, + { "bge", "bgew", }, + { "blt", "bltw", }, + { "bgt", "bgtw", }, + { "ble", "blew", }, + { "bra", "braw", }, + { "bsr", "bsrw", }, + { "bhib", "bhis", }, + { "blsb", "blss", }, + { "bccb", "bccs", }, + { "bcsb", "bcss", }, + { "bneb", "bnes", }, + { "beqb", "beqs", }, + { "bvcb", "bvcs", }, + { "bvsb", "bvss", }, + { "bplb", "bpls", }, + { "bmib", "bmis", }, + { "bgeb", "bges", }, + { "bltb", "blts", }, + { "bgtb", "bgts", }, + { "bleb", "bles", }, + { "brab", "bras", }, + { "bsrb", "bsrs", }, + { "bhs", "bccw" }, + { "bhss", "bccs" }, + { "bhsb", "bccs" }, + { "bhsw", "bccw" }, + { "bhsl", "bccl" }, + { "blo", "bcsw" }, + { "blos", "bcss" }, + { "blob", "bcss" }, + { "blow", "bcsw" }, + { "blol", "bcsl" }, + { "br", "braw", }, + { "brs", "bras", }, + { "brb", "bras", }, + { "brw", "braw", }, + { "brl", "bral", }, + { "jfnlt", "bcc", }, /* apparently a sun alias */ + { "jfngt", "ble", }, /* apparently a sun alias */ + { "jfeq", "beqs", }, /* apparently a sun alias */ + { "bchgb", "bchg", }, + { "bchgl", "bchg", }, + { "bclrb", "bclr", }, + { "bclrl", "bclr", }, + { "bsetb", "bset", }, + { "bsetl", "bset", }, + { "btstb", "btst", }, + { "btstl", "btst", }, + { "cas2", "cas2w", }, + { "cas", "casw", }, + { "chk2", "chk2w", }, + { "chk", "chkw", }, + { "clr", "clrw", }, + { "cmp2", "cmp2w", }, + { "cmpa", "cmpaw", }, + { "cmpi", "cmpiw", }, + { "cmpm", "cmpmw", }, + { "cmp", "cmpw", }, + { "dbccw", "dbcc", }, + { "dbcsw", "dbcs", }, + { "dbeqw", "dbeq", }, + { "dbfw", "dbf", }, + { "dbgew", "dbge", }, + { "dbgtw", "dbgt", }, + { "dbhiw", "dbhi", }, + { "dblew", "dble", }, + { "dblsw", "dbls", }, + { "dbltw", "dblt", }, + { "dbmiw", "dbmi", }, + { "dbnew", "dbne", }, + { "dbplw", "dbpl", }, + { "dbtw", "dbt", }, + { "dbvcw", "dbvc", }, + { "dbvsw", "dbvs", }, + { "dbhs", "dbcc", }, + { "dbhsw", "dbcc", }, + { "dbra", "dbf", }, + { "dbraw", "dbf", }, + { "tdivsl", "divsl", }, + { "divs", "divsw", }, + { "divu", "divuw", }, + { "ext", "extw", }, + { "extbw", "extw", }, + { "extwl", "extl", }, + { "fbneq", "fbne", }, + { "fbsneq", "fbsne", }, + { "fdbneq", "fdbne", }, + { "fdbsneq", "fdbsne", }, + { "fmovecr", "fmovecrx", }, + { "fmovm", "fmovem", }, + { "fsneq", "fsne", }, + { "fssneq", "fssne", }, + { "ftrapneq", "ftrapne", }, + { "ftrapsneq", "ftrapsne", }, + { "fjneq", "fjne", }, + { "fjsneq", "fjsne", }, + { "jmpl", "jmp", }, + { "jmps", "jmp", }, + { "jsrl", "jsr", }, + { "jsrs", "jsr", }, + { "leal", "lea", }, + { "lsl", "lslw", }, + { "lsr", "lsrw", }, + { "mac", "macw" }, + { "movea", "moveaw", }, + { "movem", "movemw", }, + { "movml", "moveml", }, + { "movmw", "movemw", }, + { "movm", "movemw", }, + { "movep", "movepw", }, + { "movpw", "movepw", }, + { "moves", "movesw" }, + { "muls", "mulsw", }, + { "mulu", "muluw", }, + { "msac", "msacw" }, + { "nbcdb", "nbcd" }, + { "neg", "negw", }, + { "negx", "negxw", }, + { "not", "notw", }, + { "peal", "pea", }, + { "rol", "rolw", }, + { "ror", "rorw", }, + { "roxl", "roxlw", }, + { "roxr", "roxrw", }, + { "sats", "satsl", }, + { "sbcdb", "sbcd", }, + { "sccb", "scc", }, + { "scsb", "scs", }, + { "seqb", "seq", }, + { "sfb", "sf", }, + { "sgeb", "sge", }, + { "sgtb", "sgt", }, + { "shib", "shi", }, + { "sleb", "sle", }, + { "slsb", "sls", }, + { "sltb", "slt", }, + { "smib", "smi", }, + { "sneb", "sne", }, + { "splb", "spl", }, + { "stb", "st", }, + { "svcb", "svc", }, + { "svsb", "svs", }, + { "sfge", "sge", }, + { "sfgt", "sgt", }, + { "sfle", "sle", }, + { "sflt", "slt", }, + { "sfneq", "sne", }, + { "suba", "subaw", }, + { "subi", "subiw", }, + { "subq", "subqw", }, + { "sub", "subw", }, + { "subx", "subxw", }, + { "swapw", "swap", }, + { "tasb", "tas", }, + { "tpcc", "trapcc", }, + { "tcc", "trapcc", }, + { "tst", "tstw", }, + { "jbra", "jra", }, + { "jbhi", "jhi", }, + { "jbls", "jls", }, + { "jbcc", "jcc", }, + { "jbcs", "jcs", }, + { "jbne", "jne", }, + { "jbeq", "jeq", }, + { "jbvc", "jvc", }, + { "jbvs", "jvs", }, + { "jbpl", "jpl", }, + { "jbmi", "jmi", }, + { "jbge", "jge", }, + { "jblt", "jlt", }, + { "jbgt", "jgt", }, + { "jble", "jle", }, + { "movql", "moveq", }, + { "moveql", "moveq", }, + { "movl", "movel", }, + { "movq", "moveq", }, + { "moval", "moveal", }, + { "movaw", "moveaw", }, + { "movb", "moveb", }, + { "movc", "movec", }, + { "movecl", "movec", }, + { "movpl", "movepl", }, + { "movw", "movew", }, + { "movsb", "movesb", }, + { "movsl", "movesl", }, + { "movsw", "movesw", }, + { "mov3q", "mov3ql", }, + + { "tdivul", "divul", }, /* for m68k-svr4 */ + { "fmovb", "fmoveb", }, + { "fsmovb", "fsmoveb", }, + { "fdmovb", "fdmoveb", }, + { "fmovd", "fmoved", }, + { "fsmovd", "fsmoved", }, + { "fmovl", "fmovel", }, + { "fsmovl", "fsmovel", }, + { "fdmovl", "fdmovel", }, + { "fmovp", "fmovep", }, + { "fsmovp", "fsmovep", }, + { "fdmovp", "fdmovep", }, + { "fmovs", "fmoves", }, + { "fsmovs", "fsmoves", }, + { "fdmovs", "fdmoves", }, + { "fmovw", "fmovew", }, + { "fsmovw", "fsmovew", }, + { "fdmovw", "fdmovew", }, + { "fmovx", "fmovex", }, + { "fsmovx", "fsmovex", }, + { "fdmovx", "fdmovex", }, + { "fmovcr", "fmovecr", }, + { "fmovcrx", "fmovecrx", }, + { "ftestb", "ftstb", }, + { "ftestd", "ftstd", }, + { "ftestl", "ftstl", }, + { "ftestp", "ftstp", }, + { "ftests", "ftsts", }, + { "ftestw", "ftstw", }, + { "ftestx", "ftstx", }, +}; + +const int m68k_numaliases = + sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0]; diff --git a/opcodes/m88k-dis.c b/opcodes/m88k-dis.c new file mode 100644 index 0000000..cd549d6 --- /dev/null +++ b/opcodes/m88k-dis.c @@ -0,0 +1,294 @@ +/* Print instructions for the Motorola 88000, for GDB and GNU Binutils. + Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001 + Free Software Foundation, Inc. + Contributed by Data General Corporation, November 1989. + Partially derived from an earlier printcmd.c. + +This file is part of GDB and the GNU Binutils. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/m88k.h" +#include "opintl.h" + +INSTAB *hashtable[HASHVAL] = {0}; + +static int +m88kdis PARAMS ((bfd_vma, unsigned long, struct disassemble_info *)); + +static void +printop PARAMS ((struct disassemble_info *, OPSPEC *, unsigned long, bfd_vma, int)); + +static void +init_disasm PARAMS ((void)); + +static void +install PARAMS ((INSTAB *instptr)); + + +/* Disassemble an M88000 instruction at `memaddr'. */ + +int +print_insn_m88k (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + bfd_byte buffer[4]; + int status; + + /* Instruction addresses may have low two bits set. Clear them. */ + memaddr &=~ (bfd_vma) 3; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + return m88kdis (memaddr, bfd_getb32 (buffer), info); +} + +/* + * Disassemble the instruction in `instruction'. + * `pc' should be the address of this instruction, it will be used to + * print the target address if this is a relative jump or call the + * disassembled instruction is written to `info'. + * + * The function returns the length of this instruction in bytes. + */ + +static int +m88kdis (pc, instruction, info) + bfd_vma pc; + unsigned long instruction; + struct disassemble_info *info; +{ + static int ihashtab_initialized = 0; + unsigned int opcode; + INSTAB *entry_ptr; + int opmask; + unsigned int class; + + if (! ihashtab_initialized) + init_disasm (); + + /* Create the appropriate mask to isolate the opcode. */ + opmask = DEFMASK; + class = instruction & DEFMASK; + if ((class >= SFU0) && (class <= SFU7)) + { + if (instruction < SFU1) + opmask = CTRLMASK; + else + opmask = SFUMASK; + } + else if (class == RRR) + opmask = RRRMASK; + else if (class == RRI10) + opmask = RRI10MASK; + + /* Isolate the opcode. */ + opcode = instruction & opmask; + + /* Search the hash table with the isolated opcode. */ + for (entry_ptr = hashtable[opcode % HASHVAL]; + (entry_ptr != NULL) && (entry_ptr->opcode != opcode); + entry_ptr = entry_ptr->next) + ; + + if (entry_ptr == NULL) + (*info->fprintf_func) (info->stream, "word\t%08x", instruction); + else + { + (*info->fprintf_func) (info->stream, "%s", entry_ptr->mnemonic); + printop (info, &(entry_ptr->op1), instruction, pc, 1); + printop (info, &(entry_ptr->op2), instruction, pc, 0); + printop (info, &(entry_ptr->op3), instruction, pc, 0); + } + + return 4; +} + +/* + * Decode an Operand of an instruction. + * + * This function formats and writes an operand of an instruction to + * info based on the operand specification. When the `first' flag is + * set this is the first operand of an instruction. Undefined operand + * types cause a message. + * + * Parameters: + * disassemble_info where the operand may be printed + * OPSPEC *opptr pointer to an operand specification + * UINT inst instruction from which operand is extracted + * UINT pc pc of instruction; used for pc-relative disp. + * int first flag which if nonzero indicates the first + * operand of an instruction + * + * The operand specified is extracted from the instruction and is + * written to buf in the format specified. The operand is preceded by + * a comma if it is not the first operand of an instruction and it is + * not a register indirect form. Registers are preceded by 'r' and + * hex values by '0x'. + */ + +static void +printop (info, opptr, inst, pc, first) + struct disassemble_info *info; + OPSPEC *opptr; + unsigned long inst; + bfd_vma pc; + int first; +{ + int extracted_field; + char *cond_mask_sym; + + if (opptr->width == 0) + return; + + if (! first) + { + switch (opptr->type) + { + case REGSC: + case CONT: + break; + default: + (*info->fprintf_func) (info->stream, ","); + break; + } + } + + switch (opptr->type) + { + case CRREG: + (*info->fprintf_func) (info->stream, "cr%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case FCRREG: + (*info->fprintf_func) (info->stream, "fcr%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case REGSC: + (*info->fprintf_func) (info->stream, "[r%d]", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case REG: + (*info->fprintf_func) (info->stream, "r%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case XREG: + (*info->fprintf_func) (info->stream, "x%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case HEX: + extracted_field = UEXT (inst, opptr->offset, opptr->width); + if (extracted_field == 0) + (*info->fprintf_func) (info->stream, "0"); + else + (*info->fprintf_func) (info->stream, "0x%02x", extracted_field); + break; + + case DEC: + extracted_field = UEXT (inst, opptr->offset, opptr->width); + (*info->fprintf_func) (info->stream, "%d", extracted_field); + break; + + case CONDMASK: + extracted_field = UEXT (inst, opptr->offset, opptr->width); + switch (extracted_field & 0x0f) + { + case 0x1: cond_mask_sym = "gt0"; break; + case 0x2: cond_mask_sym = "eq0"; break; + case 0x3: cond_mask_sym = "ge0"; break; + case 0xc: cond_mask_sym = "lt0"; break; + case 0xd: cond_mask_sym = "ne0"; break; + case 0xe: cond_mask_sym = "le0"; break; + default: cond_mask_sym = NULL; break; + } + if (cond_mask_sym != NULL) + (*info->fprintf_func) (info->stream, "%s", cond_mask_sym); + else + (*info->fprintf_func) (info->stream, "%x", extracted_field); + break; + + case PCREL: + (*info->print_address_func) + (pc + (4 * (SEXT (inst, opptr->offset, opptr->width))), + info); + break; + + case CONT: + (*info->fprintf_func) (info->stream, "%d,r%d", + UEXT (inst, opptr->offset, 5), + UEXT (inst, (opptr->offset) + 5, 5)); + break; + + case BF: + (*info->fprintf_func) (info->stream, "%d<%d>", + UEXT (inst, (opptr->offset) + 5, 5), + UEXT (inst, opptr->offset, 5)); + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _("# "), inst); + } +} + +/* + * Initialize the disassembler instruction table. + * + * Initialize the hash table and instruction table for the + * disassembler. This should be called once before the first call to + * disasm(). + */ + +static void +init_disasm () +{ + int i, size; + + for (i = 0; i < HASHVAL; i++) + hashtable[i] = NULL; + + size = sizeof (instructions) / sizeof (INSTAB); + for (i = 0; i < size; i++) + install (&instructions[i]); +} + +/* + * Insert an instruction into the disassembler table by hashing the + * opcode and inserting it into the linked list for that hash value. + */ + +static void +install (instptr) + INSTAB *instptr; +{ + unsigned int i; + + i = (instptr->opcode) % HASHVAL; + instptr->next = hashtable[i]; + hashtable[i] = instptr; +} diff --git a/opcodes/makefile.vms b/opcodes/makefile.vms new file mode 100644 index 0000000..fc87048 --- /dev/null +++ b/opcodes/makefile.vms @@ -0,0 +1,42 @@ +# +# Makefile for libopcodes under openVMS VAX and Alpha +# +# For use with gnu-make for vms +# +# Created by Klaus K"ampf, kkaempf@progis.de +# +# +ifeq ($(ARCH),alpha) +OBJS=alpha-dis.obj,alpha-opc.obj,dis-buf.obj,disassemble.obj +FORMAT=OBJ_EVAX +ARCHDEF="ARCH_alpha" +else +OBJS=vax-dis.obj,dis-buf.obj,disassemble.obj +FORMAT=OBJ_VAX +ARCHDEF="ARCH_vax" +endif + +ifeq ($(CC),gcc) +DEFS=/define=($(FORMAT)) +CFLAGS=/include=([],[-.include],[-.bfd])$(DEFS) +else +DEFS=/define=($(FORMAT),"const=") +CFLAGS=/noopt/debug/include=([],[-.include],[-.bfd])$(DEFS)\ +/warnings=disable=(missingreturn,implicitfunc,longextern) +endif + +libopcodes.olb: sysdep.h $(OBJS) + purge + lib/create libopcodes *.obj + +disassemble.obj: disassemble.c + $(CC)$(CFLAGS)/define=($(ARCHDEF)) $< + +sysdep.h: [-.bfd.hosts]$(ARCH)vms.h + $(CP) $< $@ + +clean: + $$ purge + $(RM) *.obj; + $(RM) sysdep.h; + $(RM) libopcodes.olb; diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c new file mode 100644 index 0000000..ad45318 --- /dev/null +++ b/opcodes/mcore-dis.c @@ -0,0 +1,275 @@ +/* Disassemble Motorola M*Core instructions. + Copyright 1993, 1999, 2000 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "mcore-opc.h" +#include "dis-asm.h" + +/* Mask for each mcore_opclass: */ +static const unsigned short imsk[] = { + /* O0 */ 0xFFFF, + /* OT */ 0xFFFC, + /* O1 */ 0xFFF0, + /* OC */ 0xFE00, + /* O2 */ 0xFF00, + /* X1 */ 0xFFF0, + /* OI */ 0xFE00, + /* OB */ 0xFE00, + + /* OMa */ 0xFFF0, + /* SI */ 0xFE00, + /* I7 */ 0xF800, + /* LS */ 0xF000, + /* BR */ 0xF800, + /* BL */ 0xFF00, + /* LR */ 0xF000, + /* LJ */ 0xFF00, + + /* RM */ 0xFFF0, + /* RQ */ 0xFFF0, + /* JSR */ 0xFFF0, + /* JMP */ 0xFFF0, + /* OBRa*/ 0xFFF0, + /* OBRb*/ 0xFF80, + /* OBRc*/ 0xFF00, + /* OBR2*/ 0xFE00, + + /* O1R1*/ 0xFFF0, + /* OMb */ 0xFF80, + /* OMc */ 0xFF00, + /* SIa */ 0xFE00, + + /* MULSH */ 0xFF00, + /* OPSR */ 0xFFF8, /* psrset/psrclr */ + + /* JC */ 0, /* JC,JU,JL don't appear in object */ + /* JU */ 0, + /* JL */ 0, + /* RSI */ 0, + /* DO21*/ 0, + /* OB2 */ 0 /* OB2 won't appear in object. */ +}; + +static const char *grname[] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" +}; + +static const char X[] = "??"; + +static const char *crname[] = { + "psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1", + "ss2", "ss3", "ss4", "gcr", "gsr", X, X, X, + X, X, X, X, X, X, X, X, + X, X, X, X, X, X, X, X +}; + +static const unsigned isiz[] = { 2, 0, 1, 0 }; + +int +print_insn_mcore (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + unsigned char ibytes[4]; + fprintf_ftype fprintf = info->fprintf_func; + void * stream = info->stream; + unsigned short inst; + mcore_opcode_info * op; + int status; + + info->bytes_per_chunk = 2; + + status = info->read_memory_func (memaddr, ibytes, 2, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + inst = (ibytes[0] << 8) | ibytes[1]; + else if (info->endian == BFD_ENDIAN_LITTLE) + inst = (ibytes[1] << 8) | ibytes[0]; + else + abort (); + + /* Just a linear search of the table. */ + for (op = mcore_table; op->name != 0; op++) + if (op->inst == (inst & imsk[op->opclass])) + break; + + if (op->name == 0) + fprintf (stream, ".short 0x%04x", inst); + else + { + const char *name = grname[inst & 0x0F]; + + fprintf (stream, "%s", op->name); + + switch (op->opclass) + { + case O0: break; + case OT: fprintf (stream, "\t%d", inst & 0x3); break; + case O1: + case JMP: + case JSR: fprintf (stream, "\t%s", name); break; + case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break; + case O1R1: fprintf (stream, "\t%s, r1", name); break; + case MULSH: + case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break; + case X1: fprintf (stream, "\tr1, %s", name); break; + case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break; + case RM: fprintf (stream, "\t%s-r15, (r0)", name); break; + case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break; + case OB: + case OBRa: + case OBRb: + case OBRc: + case SI: + case SIa: + case OMa: + case OMb: + case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break; + case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break; + case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF], + name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]); + break; + + case BR: + { + long val = inst & 0x3FF; + + if (inst & 0x400) + val |= 0xFFFFFC00; + + fprintf (stream, "\t0x%x", memaddr + 2 + (val << 1)); + + if (strcmp (op->name, "bsr") == 0) + { + /* For bsr, we'll try to get a symbol for the target. */ + val = memaddr + 2 + (val << 1); + + if (info->print_address_func && val != 0) + { + fprintf (stream, "\t// "); + info->print_address_func (val, info); + } + } + } + break; + + case BL: + { + long val; + val = (inst & 0x000F); + fprintf (stream, "\t%s, 0x%x", + grname[(inst >> 4) & 0xF], memaddr - (val << 1)); + } + break; + + case LR: + { + unsigned long val; + + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; + + status = info->read_memory_func (val, ibytes, 4, info); + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + break; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + val = (ibytes[3] << 24) | (ibytes[2] << 16) + | (ibytes[1] << 8) | (ibytes[0]); + else + val = (ibytes[0] << 24) | (ibytes[1] << 16) + | (ibytes[2] << 8) | (ibytes[3]); + + /* Removed [] around literal value to match ABI syntax 12/95. */ + fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val); + + if (val == 0) + fprintf (stream, "\t// from address pool at 0x%x", + (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + } + break; + + case LJ: + { + unsigned long val; + + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; + + status = info->read_memory_func (val, ibytes, 4, info); + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + break; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + val = (ibytes[3] << 24) | (ibytes[2] << 16) + | (ibytes[1] << 8) | (ibytes[0]); + else + val = (ibytes[0] << 24) | (ibytes[1] << 16) + | (ibytes[2] << 8) | (ibytes[3]); + + /* Removed [] around literal value to match ABI syntax 12/95. */ + fprintf (stream, "\t0x%X", val); + /* For jmpi/jsri, we'll try to get a symbol for the target. */ + if (info->print_address_func && val != 0) + { + fprintf (stream, "\t// "); + info->print_address_func (val, info); + } + else + { + fprintf (stream, "\t// from address pool at 0x%x", + (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + } + } + break; + + case OPSR: + { + static char *fields[] = { + "af", "ie", "fe", "fe,ie", + "ee", "ee,ie", "ee,fe", "ee,fe,ie" + }; + + fprintf (stream, "\t%s", fields[inst & 0x7]); + } + break; + + default: + /* If the disassembler lags the instruction set. */ + fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst); + break; + } + } + + /* Say how many bytes we consumed. */ + return 2; +} diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h new file mode 100644 index 0000000..7e4f539 --- /dev/null +++ b/opcodes/mcore-opc.h @@ -0,0 +1,209 @@ +/* Assembler instructions for Motorola's Mcore processor + Copyright 1999, 2000 Free Software Foundation, Inc. + + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "ansidecl.h" + +typedef enum +{ + O0, OT, O1, OC, O2, X1, OI, OB, + OMa, SI, I7, LS, BR, BL, LR, LJ, + RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2, + O1R1, OMb, OMc, SIa, + MULSH, OPSR, + JC, JU, JL, RSI, DO21, OB2 +} +mcore_opclass; + +typedef struct inst +{ + char * name; + mcore_opclass opclass; + unsigned char transfer; + unsigned short inst; +} +mcore_opcode_info; + +#ifdef DEFINE_TABLE +mcore_opcode_info mcore_table[] = +{ + { "bkpt", O0, 0, 0x0000 }, + { "sync", O0, 0, 0x0001 }, + { "rte", O0, 1, 0x0002 }, + { "rfe", O0, 1, 0x0002 }, + { "rfi", O0, 1, 0x0003 }, + { "stop", O0, 0, 0x0004 }, + { "wait", O0, 0, 0x0005 }, + { "doze", O0, 0, 0x0006 }, + { "idly4", O0, 0, 0x0007 }, + { "trap", OT, 0, 0x0008 }, +/* SPACE: 0x000C - 0x000F */ +/* SPACE: 0x0010 - 0x001F */ + { "mvc", O1, 0, 0x0020 }, + { "mvcv", O1, 0, 0x0030 }, + { "ldq", RQ, 0, 0x0040 }, + { "stq", RQ, 0, 0x0050 }, + { "ldm", RM, 0, 0x0060 }, + { "stm", RM, 0, 0x0070 }, + { "dect", O1, 0, 0x0080 }, + { "decf", O1, 0, 0x0090 }, + { "inct", O1, 0, 0x00A0 }, + { "incf", O1, 0, 0x00B0 }, + { "jmp", JMP, 2, 0x00C0 }, +#define MCORE_INST_JMP 0x00C0 + { "jsr", JSR, 0, 0x00D0 }, +#define MCORE_INST_JSR 0x00E0 + { "ff1", O1, 0, 0x00E0 }, + { "brev", O1, 0, 0x00F0 }, + { "xtrb3", X1, 0, 0x0100 }, + { "xtrb2", X1, 0, 0x0110 }, + { "xtrb1", X1, 0, 0x0120 }, + { "xtrb0", X1, 0, 0x0130 }, + { "zextb", O1, 0, 0x0140 }, + { "sextb", O1, 0, 0x0150 }, + { "zexth", O1, 0, 0x0160 }, + { "sexth", O1, 0, 0x0170 }, + { "declt", O1, 0, 0x0180 }, + { "tstnbz", O1, 0, 0x0190 }, + { "decgt", O1, 0, 0x01A0 }, + { "decne", O1, 0, 0x01B0 }, + { "clrt", O1, 0, 0x01C0 }, + { "clrf", O1, 0, 0x01D0 }, + { "abs", O1, 0, 0x01E0 }, + { "not", O1, 0, 0x01F0 }, + { "movt", O2, 0, 0x0200 }, + { "mult", O2, 0, 0x0300 }, + { "loopt", BL, 0, 0x0400 }, + { "subu", O2, 0, 0x0500 }, + { "sub", O2, 0, 0x0500 }, /* Official alias. */ + { "addc", O2, 0, 0x0600 }, + { "subc", O2, 0, 0x0700 }, +/* SPACE: 0x0800-0x08ff for a diadic operation */ +/* SPACE: 0x0900-0x09ff for a diadic operation */ + { "movf", O2, 0, 0x0A00 }, + { "lsr", O2, 0, 0x0B00 }, + { "cmphs", O2, 0, 0x0C00 }, + { "cmplt", O2, 0, 0x0D00 }, + { "tst", O2, 0, 0x0E00 }, + { "cmpne", O2, 0, 0x0F00 }, + { "mfcr", OC, 0, 0x1000 }, + { "psrclr", OPSR, 0, 0x11F0 }, + { "psrset", OPSR, 0, 0x11F8 }, + { "mov", O2, 0, 0x1200 }, + { "bgenr", O2, 0, 0x1300 }, + { "rsub", O2, 0, 0x1400 }, + { "ixw", O2, 0, 0x1500 }, + { "and", O2, 0, 0x1600 }, + { "xor", O2, 0, 0x1700 }, + { "mtcr", OC, 0, 0x1800 }, + { "asr", O2, 0, 0x1A00 }, + { "lsl", O2, 0, 0x1B00 }, + { "addu", O2, 0, 0x1C00 }, + { "add", O2, 0, 0x1C00 }, /* Official alias. */ + { "ixh", O2, 0, 0x1D00 }, + { "or", O2, 0, 0x1E00 }, + { "andn", O2, 0, 0x1F00 }, + { "addi", OI, 0, 0x2000 }, +#define MCORE_INST_ADDI 0x2000 + { "cmplti", OI, 0, 0x2200 }, + { "subi", OI, 0, 0x2400 }, +/* SPACE: 0x2600-0x27ff open for a register+immediate operation */ + { "rsubi", OB, 0, 0x2800 }, + { "cmpnei", OB, 0, 0x2A00 }, + { "bmaski", OMa, 0, 0x2C00 }, + { "divu", O1R1, 0, 0x2C10 }, +/* SPACE: 0x2c20 - 0x2c7f */ + { "bmaski", OMb, 0, 0x2C80 }, + { "bmaski", OMc, 0, 0x2D00 }, + { "andi", OB, 0, 0x2E00 }, + { "bclri", OB, 0, 0x3000 }, +/* SPACE: 0x3200 - 0x320f */ + { "divs", O1R1, 0, 0x3210 }, +/* SPACE: 0x3220 - 0x326f */ + { "bgeni", OBRa, 0, 0x3270 }, + { "bgeni", OBRb, 0, 0x3280 }, + { "bgeni", OBRc, 0, 0x3300 }, + { "bseti", OB, 0, 0x3400 }, + { "btsti", OB, 0, 0x3600 }, + { "xsr", O1, 0, 0x3800 }, + { "rotli", SIa, 0, 0x3800 }, + { "asrc", O1, 0, 0x3A00 }, + { "asri", SIa, 0, 0x3A00 }, + { "lslc", O1, 0, 0x3C00 }, + { "lsli", SIa, 0, 0x3C00 }, + { "lsrc", O1, 0, 0x3E00 }, + { "lsri", SIa, 0, 0x3E00 }, +/* SPACE: 0x4000 - 0x5fff */ + { "movi", I7, 0, 0x6000 }, +#define MCORE_INST_BMASKI_ALT 0x6000 +#define MCORE_INST_BGENI_ALT 0x6000 + { "mulsh", MULSH, 0, 0x6800 }, + { "muls.h", MULSH, 0, 0x6800 }, +/* SPACE: 0x6900 - 0x6FFF */ + { "jmpi", LJ, 1, 0x7000 }, + { "jsri", LJ, 0, 0x7F00 }, +#define MCORE_INST_JMPI 0x7000 + { "lrw", LR, 0, 0x7000 }, +#define MCORE_INST_JSRI 0x7F00 + { "ld", LS, 0, 0x8000 }, + { "ldw", LS, 0, 0x8000 }, + { "ld.w", LS, 0, 0x8000 }, + { "st", LS, 0, 0x9000 }, + { "stw", LS, 0, 0x9000 }, + { "st.w", LS, 0, 0x9000 }, + { "ldb", LS, 0, 0xA000 }, + { "ld.b", LS, 0, 0xA000 }, + { "stb", LS, 0, 0xB000 }, + { "st.b", LS, 0, 0xB000 }, + { "ldh", LS, 0, 0xC000 }, + { "ld.h", LS, 0, 0xC000 }, + { "sth", LS, 0, 0xD000 }, + { "st.h", LS, 0, 0xD000 }, + { "bt", BR, 0, 0xE000 }, + { "bf", BR, 0, 0xE800 }, + { "br", BR, 1, 0xF000 }, +#define MCORE_INST_BR 0xF000 + { "bsr", BR, 0, 0xF800 }, +#define MCORE_INST_BSR 0xF800 + +/* The following are relaxable branches */ + { "jbt", JC, 0, 0xE000 }, + { "jbf", JC, 0, 0xE800 }, + { "jbr", JU, 1, 0xF000 }, + { "jbsr", JL, 0, 0xF800 }, + +/* The following are aliases for other instructions */ + { "rts", O0, 2, 0x00CF }, /* jmp r15 */ + { "rolc", DO21, 0, 0x0600 }, /* addc rd,rd */ + { "rotlc", DO21, 0, 0x0600 }, /* addc rd,rd */ + { "setc", O0, 0, 0x0C00 }, /* cmphs r0,r0 */ + { "clrc", O0, 0, 0x0F00 }, /* cmpne r0,r0 */ + { "tstle", O1, 0, 0x2200 }, /* cmplti rd,1 */ + { "cmplei", OB, 0, 0x2200 }, /* cmplei rd,X -> cmplti rd,X+1 */ + { "neg", O1, 0, 0x2800 }, /* rsubi rd,0 */ + { "tstne", O1, 0, 0x2A00 }, /* cmpnei rd,0 */ + { "tstlt", O1, 0, 0x37F0 }, /* btsti rx,31 */ + { "mclri", OB2, 0, 0x3000 }, /* bclri rx,log2(imm) */ + { "mgeni", OBR2, 0, 0x3200 }, /* bgeni rx,log2(imm) */ + { "mseti", OB2, 0, 0x3400 }, /* bseti rx,log2(imm) */ + { "mtsti", OB2, 0, 0x3600 }, /* btsti rx,log2(imm) */ + { "rori", RSI, 0, 0x3800 }, + { "rotri", RSI, 0, 0x3800 }, + { "nop", O0, 0, 0x1200 }, /* mov r0, r0 */ + { 0, 0, 0, 0 } +}; +#endif diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c new file mode 100644 index 0000000..661c179 --- /dev/null +++ b/opcodes/mips-dis.c @@ -0,0 +1,1166 @@ +/* Print mips instructions for GDB, the GNU debugger, or for objdump. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002 + Free Software Foundation, Inc. + Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). + +This file is part of GDB, GAS, and the GNU binutils. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/mips.h" +#include "opintl.h" + +/* FIXME: These are needed to figure out if the code is mips16 or + not. The low bit of the address is often a good indicator. No + symbol table is available when this code runs out in an embedded + system as when it is used for disassembler support in a monitor. */ + +#if !defined(EMBEDDED_ENV) +#define SYMTAB_AVAILABLE 1 +#include "elf-bfd.h" +#include "elf/mips.h" +#endif + +/* Mips instructions are at maximum this many bytes long. */ +#define INSNLEN 4 + +static int _print_insn_mips + PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian)); +static int print_insn_mips + PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *)); +static void print_insn_arg + PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *)); +static void mips_isa_type + PARAMS ((int, int *, int *)); +static int print_insn_mips16 + PARAMS ((bfd_vma, struct disassemble_info *)); +static int is_newabi + PARAMS ((Elf_Internal_Ehdr *)); +static void print_mips16_insn_arg + PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma, + struct disassemble_info *)); + +/* FIXME: These should be shared with gdb somehow. */ + +/* The mips16 register names. */ +static const char * const mips16_reg_names[] = { + "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" +}; + +static const char * const mips32_reg_names[] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", + "sr", "lo", "hi", "bad", "cause", "pc", + "fv0", "$f1", "fv1", "$f3", "ft0", "$f5", "ft1", "$f7", + "ft2", "$f9", "ft3", "$f11", "fa0", "$f13", "fa1", "$f15", + "ft4", "f17", "ft5", "f19", "fs0", "f21", "fs1", "f23", + "fs2", "$f25", "fs3", "$f27", "fs4", "$f29", "fs5", "$f31", + "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi", + "epc", "prid" +}; + +static const char * const mips64_reg_names[] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", + "sr", "lo", "hi", "bad", "cause", "pc", + "fv0", "$f1", "fv1", "$f3", "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", + "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", + "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fsr", "fir", "fp", "inx", "rand", "tlblo", "ctxt", "tlbhi", + "epc", "prid" +}; + +/* Scalar register names. _print_insn_mips() decides which register name + table to use. */ +static const char * const *reg_names = NULL; + +/* Print insn arguments for 32/64-bit code. */ + +static void +print_insn_arg (d, l, pc, info) + const char *d; + register unsigned long int l; + bfd_vma pc; + struct disassemble_info *info; +{ + int delta; + + switch (*d) + { + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", *d); + break; + + case 's': + case 'b': + case 'r': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + reg_names[(l >> OP_SH_RS) & OP_MASK_RS]); + break; + + case 't': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + break; + + case 'i': + case 'u': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); + break; + + case 'j': /* Same as i, but sign-extended. */ + case 'o': + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + (*info->fprintf_func) (info->stream, "%d", + delta); + break; + + case 'h': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_PREFX) + & OP_MASK_PREFX)); + break; + + case 'k': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_CACHE) + & OP_MASK_CACHE)); + break; + + case 'a': + info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) + | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); + (*info->print_address_func) (info->target, info); + break; + + case 'p': + /* Sign extend the displacement. */ + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + info->target = (delta << 2) + pc + INSNLEN; + (*info->print_address_func) (info->target, info); + break; + + case 'd': + (*info->fprintf_func) (info->stream, "%s", + reg_names[(l >> OP_SH_RD) & OP_MASK_RD]); + break; + + case 'U': + { + /* First check for both rd and rt being equal. */ + unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; + if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) + (*info->fprintf_func) (info->stream, "%s", + reg_names[reg]); + else + { + /* If one is zero use the other. */ + if (reg == 0) + (*info->fprintf_func) (info->stream, "%s", + reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) + (*info->fprintf_func) (info->stream, "%s", + reg_names[reg]); + else /* Bogus, result depends on processor. */ + (*info->fprintf_func) (info->stream, "%s or %s", + reg_names[reg], + reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + } + } + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", reg_names[0]); + break; + + case '<': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); + break; + + case 'c': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_CODE) & OP_MASK_CODE); + break; + + case 'q': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_CODE2) & OP_MASK_CODE2); + break; + + case 'C': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_COPZ) & OP_MASK_COPZ); + break; + + case 'B': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_CODE20) & OP_MASK_CODE20); + break; + + case 'J': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_CODE19) & OP_MASK_CODE19); + break; + + case 'S': + case 'V': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FS) & OP_MASK_FS); + break; + + case 'T': + case 'W': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FT) & OP_MASK_FT); + break; + + case 'D': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FD) & OP_MASK_FD); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FR) & OP_MASK_FR); + break; + + case 'E': + (*info->fprintf_func) (info->stream, "$%d", + (l >> OP_SH_RT) & OP_MASK_RT); + break; + + case 'G': + (*info->fprintf_func) (info->stream, "$%d", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + + case 'N': + (*info->fprintf_func) (info->stream, "$fcc%d", + (l >> OP_SH_BCC) & OP_MASK_BCC); + break; + + case 'M': + (*info->fprintf_func) (info->stream, "$fcc%d", + (l >> OP_SH_CCC) & OP_MASK_CCC); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "%d", + (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); + break; + + case 'H': + (*info->fprintf_func) (info->stream, "%d", + (l >> OP_SH_SEL) & OP_MASK_SEL); + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, undefined modifier(%c)"), + *d); + break; + } +} + +/* Figure out the MIPS ISA and CPU based on the machine number. */ + +static void +mips_isa_type (mach, isa, cputype) + int mach; + int *isa; + int *cputype; +{ + switch (mach) + { + case bfd_mach_mips3000: + *cputype = CPU_R3000; + *isa = ISA_MIPS1; + break; + case bfd_mach_mips3900: + *cputype = CPU_R3900; + *isa = ISA_MIPS1; + break; + case bfd_mach_mips4000: + *cputype = CPU_R4000; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips4010: + *cputype = CPU_R4010; + *isa = ISA_MIPS2; + break; + case bfd_mach_mips4100: + *cputype = CPU_VR4100; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips4111: + *cputype = CPU_R4111; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips4300: + *cputype = CPU_R4300; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips4400: + *cputype = CPU_R4400; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips4600: + *cputype = CPU_R4600; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips4650: + *cputype = CPU_R4650; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips5000: + *cputype = CPU_R5000; + *isa = ISA_MIPS4; + break; + case bfd_mach_mips6000: + *cputype = CPU_R6000; + *isa = ISA_MIPS2; + break; + case bfd_mach_mips8000: + *cputype = CPU_R8000; + *isa = ISA_MIPS4; + break; + case bfd_mach_mips10000: + *cputype = CPU_R10000; + *isa = ISA_MIPS4; + break; + case bfd_mach_mips12000: + *cputype = CPU_R12000; + *isa = ISA_MIPS4; + break; + case bfd_mach_mips16: + *cputype = CPU_MIPS16; + *isa = ISA_MIPS3; + break; + case bfd_mach_mips5: + *cputype = CPU_MIPS5; + *isa = ISA_MIPS5; + break; + case bfd_mach_mips_sb1: + *cputype = CPU_SB1; + *isa = ISA_MIPS64 | INSN_MIPS3D | INSN_SB1; + break; + case bfd_mach_mipsisa32: + *cputype = CPU_MIPS32; + /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. + Note that MIPS-3D is not applicable to MIPS32. (See _MIPS32 + Architecture For Programmers Volume I: Introduction to the + MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), + page 1. */ + *isa = ISA_MIPS32; + break; + case bfd_mach_mipsisa64: + *cputype = CPU_MIPS64; + /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ + *isa = ISA_MIPS64 | INSN_MIPS3D; + break; + + default: + *cputype = CPU_R3000; + *isa = ISA_MIPS3; + break; + } +} + +/* Check if the object uses NewABI conventions. */ + +static int +is_newabi (header) + Elf_Internal_Ehdr *header; +{ + /* There are no old-style ABIs which use 64-bit ELF. */ + if (header->e_ident[EI_CLASS] == ELFCLASS64) + return 1; + + /* If a 32-bit ELF file, n32 is a new-style ABI. */ + if ((header->e_flags & EF_MIPS_ABI2) != 0) + return 1; + + return 0; +} + +/* Print the mips instruction at address MEMADDR in debugged memory, + on using INFO. Returns length of the instruction, in bytes, which is + always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if + this is little-endian code. */ + +static int +print_insn_mips (memaddr, word, info) + bfd_vma memaddr; + unsigned long int word; + struct disassemble_info *info; +{ + register const struct mips_opcode *op; + int target_processor, mips_isa; + static boolean init = 0; + static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; + + /* Build a hash table to shorten the search time. */ + if (! init) + { + unsigned int i; + + for (i = 0; i <= OP_MASK_OP; i++) + { + for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo == INSN_MACRO) + continue; + if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) + { + mips_hash[i] = op; + break; + } + } + } + + init = 1; + } + +#if ! SYMTAB_AVAILABLE + /* This is running out on a target machine, not in a host tool. + FIXME: Where does mips_target_info come from? */ + target_processor = mips_target_info.processor; + mips_isa = mips_target_info.isa; +#else + mips_isa_type (info->mach, &mips_isa, &target_processor); +#endif + + info->bytes_per_chunk = INSNLEN; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; + if (op != NULL) + { + for (; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) + { + register const char *d; + + if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor)) + continue; + + /* Figure out instruction type and branch delay information. */ + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + if ((info->insn_type & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_jsr; + else + info->insn_type = dis_branch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_COND_BRANCH_DELAY + | INSN_COND_BRANCH_LIKELY)) != 0) + { + if ((info->insn_type & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_condjsr; + else + info->insn_type = dis_condbranch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_STORE_MEMORY + | INSN_LOAD_MEMORY_DELAY)) != 0) + info->insn_type = dis_dref; + + (*info->fprintf_func) (info->stream, "%s", op->name); + + d = op->args; + if (d != NULL && *d != '\0') + { + (*info->fprintf_func) (info->stream, "\t"); + for (; *d != '\0'; d++) + print_insn_arg (d, word, memaddr, info); + } + + return INSNLEN; + } + } + } + + /* Handle undefined instructions. */ + info->insn_type = dis_noninsn; + (*info->fprintf_func) (info->stream, "0x%x", word); + return INSNLEN; +} + +/* In an environment where we do not know the symbol type of the + instruction we are forced to assume that the low order bit of the + instructions' address may mark it as a mips16 instruction. If we + are single stepping, or the pc is within the disassembled function, + this works. Otherwise, we need a clue. Sometimes. */ + +static int +_print_insn_mips (memaddr, info, endianness) + bfd_vma memaddr; + struct disassemble_info *info; + enum bfd_endian endianness; +{ + bfd_byte buffer[INSNLEN]; + int status; + +#if 1 + /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ + /* Only a few tools will work this way. */ + if (memaddr & 0x01) + return print_insn_mips16 (memaddr, info); +#endif + +#if SYMTAB_AVAILABLE + if (info->mach == 16 + || (info->flavour == bfd_target_elf_flavour + && info->symbols != NULL + && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other + == STO_MIPS16))) + return print_insn_mips16 (memaddr, info); +#endif + + /* Use mips64_reg_names for new ABI. */ + reg_names = mips32_reg_names; + + if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL) + { + Elf_Internal_Ehdr *header; + + header = elf_elfheader (bfd_asymbol_bfd (*(info->symbols))); + if (is_newabi (header)) + reg_names = mips64_reg_names; + } + + status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); + if (status == 0) + { + unsigned long insn; + + if (endianness == BFD_ENDIAN_BIG) + insn = (unsigned long) bfd_getb32 (buffer); + else + insn = (unsigned long) bfd_getl32 (buffer); + + return print_insn_mips (memaddr, insn, info); + } + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } +} + +int +print_insn_big_mips (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); +} + +int +print_insn_little_mips (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); +} + +/* Disassemble mips16 instructions. */ + +static int +print_insn_mips16 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + bfd_byte buffer[2]; + int length; + int insn; + boolean use_extend; + int extend = 0; + const struct mips_opcode *op, *opend; + + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Handle the extend opcode specially. */ + use_extend = false; + if ((insn & 0xf800) == 0xf000) + { + use_extend = true; + extend = insn & 0x7ff; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Check for an extend opcode followed by an extend opcode. */ + if ((insn & 0xf800) == 0xf000) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length; + } + + length += 2; + } + + /* FIXME: Should probably use a hash table on the major opcode here. */ + + opend = mips16_opcodes + bfd_mips16_num_opcodes; + for (op = mips16_opcodes; op < opend; op++) + { + if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) + { + const char *s; + + if (strchr (op->args, 'a') != NULL) + { + if (use_extend) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length - 2; + } + + use_extend = false; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, + info); + if (status == 0) + { + use_extend = true; + if (info->endian == BFD_ENDIAN_BIG) + extend = bfd_getb16 (buffer); + else + extend = bfd_getl16 (buffer); + length += 2; + } + } + + (*info->fprintf_func) (info->stream, "%s", op->name); + if (op->args[0] != '\0') + (*info->fprintf_func) (info->stream, "\t"); + + for (s = op->args; *s != '\0'; s++) + { + if (*s == ',' + && s[1] == 'w' + && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) + == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + if (*s == ',' + && s[1] == 'v' + && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) + == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, + info); + } + + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + info->branch_delay_insns = 1; + if (info->insn_type != dis_jsr) + info->insn_type = dis_branch; + } + + return length; + } + } + + if (use_extend) + (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); + (*info->fprintf_func) (info->stream, "0x%x", insn); + info->insn_type = dis_noninsn; + + return length; +} + +/* Disassemble an operand for a mips16 instruction. */ + +static void +print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) + char type; + const struct mips_opcode *op; + int l; + boolean use_extend; + int extend; + bfd_vma memaddr; + struct disassemble_info *info; +{ + switch (type) + { + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", type); + break; + + case 'y': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY)]); + break; + + case 'x': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX)]); + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ)]); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z)]); + break; + + case '0': + (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[0]); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[29]); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "$pc"); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[31]); + break; + + case 'X': + (*info->fprintf_func) (info->stream, "%s", + mips32_reg_names[((l >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32)]); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "%s", + mips32_reg_names[MIPS16OP_EXTRACT_REG32R (l)]); + break; + + case '<': + case '>': + case '[': + case ']': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '6': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + case 'p': + case 'q': + case 'A': + case 'B': + case 'E': + { + int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; + + shift = 0; + signedp = 0; + extbits = 16; + pcrel = 0; + extu = 0; + branch = 0; + switch (type) + { + case '<': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 5; + extu = 1; + break; + case '>': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 5; + extu = 1; + break; + case '[': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 6; + extu = 1; + break; + case ']': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 6; + extu = 1; + break; + case '4': + nbits = 4; + immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; + signedp = 1; + extbits = 15; + break; + case '5': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 1; + break; + case 'H': + nbits = 5; + shift = 1; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 2; + break; + case 'W': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 + && (op->pinfo & MIPS16_INSN_READ_SP) == 0) + { + info->insn_type = dis_dref; + info->data_size = 4; + } + break; + case 'D': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'j': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + signedp = 1; + break; + case '6': + nbits = 6; + immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + break; + case '8': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + break; + case 'V': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + /* FIXME: This might be lw, or it might be addiu to $sp or + $pc. We assume it's load. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'C': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'U': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + extu = 1; + break; + case 'k': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'K': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'p': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + pcrel = 1; + branch = 1; + info->insn_type = dis_condbranch; + break; + case 'q': + nbits = 11; + immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; + signedp = 1; + pcrel = 1; + branch = 1; + info->insn_type = dis_branch; + break; + case 'A': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + pcrel = 1; + /* FIXME: This can be lw or la. We assume it is lw. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'B': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'E': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + break; + default: + abort (); + } + + if (! use_extend) + { + if (signedp && immed >= (1 << (nbits - 1))) + immed -= 1 << nbits; + immed <<= shift; + if ((type == '<' || type == '>' || type == '[' || type == ']') + && immed == 0) + immed = 8; + } + else + { + if (extbits == 16) + immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); + else if (extbits == 15) + immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); + else + immed = ((extend >> 6) & 0x1f) | (extend & 0x20); + immed &= (1 << extbits) - 1; + if (! extu && immed >= (1 << (extbits - 1))) + immed -= 1 << extbits; + } + + if (! pcrel) + (*info->fprintf_func) (info->stream, "%d", immed); + else + { + bfd_vma baseaddr; + + if (branch) + { + immed *= 2; + baseaddr = memaddr + 2; + } + else if (use_extend) + baseaddr = memaddr - 2; + else + { + int status; + bfd_byte buffer[2]; + + baseaddr = memaddr; + + /* If this instruction is in the delay slot of a jr + instruction, the base address is the address of the + jr instruction. If it is in the delay slot of jalr + instruction, the base address is the address of the + jalr instruction. This test is unreliable: we have + no way of knowing whether the previous word is + instruction or data. */ + status = (*info->read_memory_func) (memaddr - 4, buffer, 2, + info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf800) == 0x1800)) + baseaddr = memaddr - 4; + else + { + status = (*info->read_memory_func) (memaddr - 2, buffer, + 2, info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf81f) == 0xe800)) + baseaddr = memaddr - 2; + } + } + info->target = (baseaddr & ~((1 << shift) - 1)) + immed; + (*info->print_address_func) (info->target, info); + } + } + break; + + case 'a': + if (! use_extend) + extend = 0; + l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; + (*info->print_address_func) (info->target, info); + info->insn_type = dis_jsr; + info->branch_delay_insns = 1; + break; + + case 'l': + case 'L': + { + int need_comma, amask, smask; + + need_comma = 0; + + l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + + amask = (l >> 3) & 7; + + if (amask > 0 && amask < 5) + { + (*info->fprintf_func) (info->stream, "%s", mips32_reg_names[4]); + if (amask > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips32_reg_names[amask + 3]); + need_comma = 1; + } + + smask = (l >> 1) & 3; + if (smask == 3) + { + (*info->fprintf_func) (info->stream, "%s??", + need_comma ? "," : ""); + need_comma = 1; + } + else if (smask > 0) + { + (*info->fprintf_func) (info->stream, "%s%s", + need_comma ? "," : "", + mips32_reg_names[16]); + if (smask > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips32_reg_names[smask + 15]); + need_comma = 1; + } + + if (l & 1) + { + (*info->fprintf_func) (info->stream, "%s%s", + need_comma ? "," : "", + mips32_reg_names[31]); + need_comma = 1; + } + + if (amask == 5 || amask == 6) + { + (*info->fprintf_func) (info->stream, "%s$f0", + need_comma ? "," : ""); + if (amask == 6) + (*info->fprintf_func) (info->stream, "-$f1"); + } + } + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) + (info->stream, + _("# internal disassembler error, unrecognised modifier (%c)"), + type); + abort (); + } +} diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c new file mode 100644 index 0000000..4b8cbc7 --- /dev/null +++ b/opcodes/mips-opc.c @@ -0,0 +1,955 @@ +/* mips-opc.c -- MIPS opcode list. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + Contributed by Ralph Campbell and OSF + Commented and modified by Ian Lance Taylor, Cygnus Support + Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. + MIPS-3D support added by Broadcom Corporation (SiByte). + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/mips.h" + +/* Short hand so the lines aren't too long. */ + +#define LDD INSN_LOAD_MEMORY_DELAY +#define LCD INSN_LOAD_COPROC_DELAY +#define UBD INSN_UNCOND_BRANCH_DELAY +#define CBD INSN_COND_BRANCH_DELAY +#define COD INSN_COPROC_MOVE_DELAY +#define CLD INSN_COPROC_MEMORY_DELAY +#define CBL INSN_COND_BRANCH_LIKELY +#define TRAP INSN_TRAP +#define SM INSN_STORE_MEMORY + +#define WR_d INSN_WRITE_GPR_D +#define WR_t INSN_WRITE_GPR_T +#define WR_31 INSN_WRITE_GPR_31 +#define WR_D INSN_WRITE_FPR_D +#define WR_T INSN_WRITE_FPR_T +#define WR_S INSN_WRITE_FPR_S +#define RD_s INSN_READ_GPR_S +#define RD_b INSN_READ_GPR_S +#define RD_t INSN_READ_GPR_T +#define RD_S INSN_READ_FPR_S +#define RD_T INSN_READ_FPR_T +#define RD_R INSN_READ_FPR_R +#define WR_CC INSN_WRITE_COND_CODE +#define RD_CC INSN_READ_COND_CODE +#define RD_C0 INSN_COP +#define RD_C1 INSN_COP +#define RD_C2 INSN_COP +#define RD_C3 INSN_COP +#define WR_C0 INSN_COP +#define WR_C1 INSN_COP +#define WR_C2 INSN_COP +#define WR_C3 INSN_COP + +#define WR_HI INSN_WRITE_HI +#define RD_HI INSN_READ_HI +#define MOD_HI WR_HI|RD_HI + +#define WR_LO INSN_WRITE_LO +#define RD_LO INSN_READ_LO +#define MOD_LO WR_LO|RD_LO + +#define WR_HILO WR_HI|WR_LO +#define RD_HILO RD_HI|RD_LO +#define MOD_HILO WR_HILO|RD_HILO + +#define IS_M INSN_MULT + +#define I1 INSN_ISA1 +#define I2 INSN_ISA2 +#define I3 INSN_ISA3 +#define I4 INSN_ISA4 +#define I5 INSN_ISA5 +#define I32 INSN_ISA32 +#define I64 INSN_ISA64 + +/* MIPS64 MIPS-3D ASE support. */ +#define M3D INSN_MIPS3D + +#define P3 INSN_4650 +#define L1 INSN_4010 +#define V1 INSN_4100 +#define T3 INSN_3900 +#define M1 INSN_10000 +#define SB1 INSN_SB1 + +#define G1 (T3 \ + ) + +#define G2 (T3 \ + ) + +#define G3 (I4 \ + ) + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. + + Many instructions are short hand for other instructions (i.e., The + jal instruction is short for jalr ). */ + +const struct mips_opcode mips_builtin_opcodes[] = +{ +/* These instructions appear first so that the disassembler will find + them first. The assemblers uses a hash table based on the + instruction name anyhow. */ +/* name, args, match, mask, pinfo, membership */ +{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 }, +{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, +{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, +{"ssnop", "", 0x00000040, 0xffffffff, 0, I32 }, +{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ +{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ +{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, +{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 }, +{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ +{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ +{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ +{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ +{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ +{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ + +{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, +{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 }, +{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, +{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, +{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, +{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, +{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, +{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, +{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, +/* b is at the top of the table. */ +/* bal is at the top of the table. */ +{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, +{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, +{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, +{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, +{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, +{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 }, +{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, +{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 }, +{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, +{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 }, +{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, +{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 }, +{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, +{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, +{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, +{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 }, +{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, +{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, +{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 }, +{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 }, +{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, +{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, +{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 }, +{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 }, +{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, +{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, +{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, +{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 }, +{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 }, +{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, +{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, +{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 }, +{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 }, +{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, +{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, +{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 }, +{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 }, +{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, +{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, +{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 }, +{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 }, +{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, +{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, +{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 }, +{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 }, +{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, +{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, +{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 }, +{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 }, +{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, +{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, +{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, +{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, +{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 }, +{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, +{"break", "B", 0x0000000d, 0xfc00003f, TRAP, I32 }, +{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, +{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, +{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, +{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3}, +{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, +{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, +{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, +{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, +{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32 }, +{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32 }, +{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, +{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, +{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, +{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, +{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, +{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, +{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D }, +{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D }, +{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, +{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, +{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, +{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, +{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, +{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64 }, +{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64 }, +/* dctr and dctw are used on the r5000. */ +{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, +{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, +{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 }, +/* For ddiv, see the comments about div. */ +{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, +{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, +{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, +/* For ddivu, see the comments about div. */ +{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, +{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, +{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, +/* The MIPS assembler treats the div opcode with two operands as + though the first operand appeared twice (the first operand is both + a source and a destination). To get the div machine instruction, + you must use an explicit destination of $0. */ +{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, +{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, +{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, +{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, +{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 }, +/* For divu, see the comments about div. */ +{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, +{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, +{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, +{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, +{"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */ +{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, +{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ +{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ +{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, + +{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, V1 }, +{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, +{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, +{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, +{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, +{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, +{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, +{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, +{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, +{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 }, +{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 }, +{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 }, +{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 }, +{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 }, +{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 }, +{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 }, +{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 }, +{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, +{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, +{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, +{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, +{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, +{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, +{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, +{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, +{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ +{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ +{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, +{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, +{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, +{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, +{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, +{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, +{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 }, +{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 }, +{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 }, +{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 }, +{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, +{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ +{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */ +{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, +{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */ +{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */ +{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, +{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */ +{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */ +{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 }, +{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, +{"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 }, +{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 }, +{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, +{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, +{"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, +{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, +{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */ +/* SVR4 PIC code requires special handling for j, so it must be a + macro. */ +{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 }, +/* This form of j is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"j", "a", 0x08000000, 0xfc000000, UBD, I1 }, +{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 }, +{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 }, +/* SVR4 PIC code requires special handling for jal, so it must be a + macro. */ +{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 }, +{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 }, +{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 }, +/* This form of jal is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, + /* jalx really should only be avaliable if mips16 is available, + but for now make it I1. */ +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, +{"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */ +{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, +{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, +{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 }, +{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 }, +{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 }, +{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, +{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, +{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, +{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, +{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */ +{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 }, +{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 }, +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 }, +{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, +{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 }, +{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, +{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 }, +{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, +{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 }, +{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 }, +/* li is at the start of the table. */ +{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 }, +{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 }, +{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 }, +{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 }, +{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, +{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 }, +{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, +{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 }, +{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, +{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5 }, +{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 }, +{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, +{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 }, +{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, +{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, +{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, +{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, +{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ +{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 }, +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 }, +{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ +{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */ +{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 }, +{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ +{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */ +{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, +{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 }, +{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, +{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 }, +{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 }, +{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32}, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 }, +{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32}, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 }, +{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, +{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 }, +{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 }, +{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 }, +{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, +{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, +{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, +{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, +{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 }, +{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, +{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, +{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 }, +{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32}, +{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 }, +{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 }, +{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 }, +{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 }, +{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 }, +{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 }, +{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 }, +{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 }, +{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 }, +{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 }, +{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 }, +{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 }, +{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 }, +{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 }, +{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 }, +/* move is at the top of the table. */ +{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, +{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, +{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 }, +{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, +{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 }, +{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1 }, +{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1 }, +{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, +{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, +{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, +{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, +{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, +{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 }, +{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, +{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, +{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 }, +{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, +{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, +{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, +{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, +{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, +{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, +{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, +{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 }, +{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, +{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 }, +{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, +{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */ +{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */ +{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 }, +{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, +{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, +/* nop is at the start of the table. */ +{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, +{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ +{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, +{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, + +{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, + + /* pref and prefx are at the start of the table. */ + +{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, + +{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, +{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, +{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D }, +{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, +{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, +{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, +{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, +{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, +{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, +{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, +{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, +{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, +{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, +{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, +{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 }, +{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, +{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, +{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D }, +{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, +{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, +{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, +{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, +{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, +{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, +{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 }, +{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 }, +{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 }, +{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 }, +{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 }, +{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 }, +{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 }, +{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 }, +{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 }, +{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, +{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, +{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, +{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 }, +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 }, +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 }, +{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, +{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 }, +{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 }, +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 }, +{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 }, +{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 }, +{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 }, +{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, +{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, L1 }, +{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, L1 }, +{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 }, +{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 }, +{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 }, +{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 }, +{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 }, +{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 }, +{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 }, +{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 }, +{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 }, +{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, +{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, +{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, +{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, +{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, +{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 }, +{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, +{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ +{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, +{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, +{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, +{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 }, +{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 }, +{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 }, +{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, +{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, +{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, +{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ +{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, +{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, +{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ +{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, +/* ssnop is at the start of the table. */ +{"standby", "", 0x42000021, 0xffffffff, 0, V1 }, +{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, +{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, +{"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, +{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5 }, +{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 }, +{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 }, +{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 }, +{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, +{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, +{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, +{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, +{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ +{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 }, +{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 }, +{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ +{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */ +{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 }, +{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ +{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */ +{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, +{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 }, +{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 }, +{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 }, +{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 }, +{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 }, +{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 }, +{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 }, +{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 }, +{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 }, +{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 }, +{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 }, +{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 }, +{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 }, +{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 }, +{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 }, +{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 }, +{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 }, +{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 }, +{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 }, +{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 }, +{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 }, +{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 }, +{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, +{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, +{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, +{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, +{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, +{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 }, +{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 }, +{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, +{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, +/* No hazard protection on coprocessor instructions--they shouldn't + change the state of the processor and if they do it's up to the + user to put in nops as necessary. These are at the end so that the + disassembler recognizes more specific versions first. */ +{"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, +{"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, +{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, +{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 }, +{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 }, +{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 }, +{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 }, +{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 }, + + /* Conflicts with the 4650's "mul" instruction. Nobody's using the + 4010 any more, so move this insn out of the way. If the object + format gave us more info, we could do this right. */ +{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 }, +}; + +#define MIPS_NUM_OPCODES \ + ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) +const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; + +/* const removed from the following to allow for dynamic extensions to the + * built-in instruction set. */ +struct mips_opcode *mips_opcodes = + (struct mips_opcode *) mips_builtin_opcodes; +int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; +#undef MIPS_NUM_OPCODES diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c new file mode 100644 index 0000000..d7fcfc2 --- /dev/null +++ b/opcodes/mips16-opc.c @@ -0,0 +1,227 @@ +/* mips16-opc.c. Mips16 opcode table. + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. + Contributed by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/mips.h" + +/* This is the opcodes table for the mips16 processor. The format of + this table is intentionally identical to the one in mips-opc.c. + However, the special letters that appear in the argument string are + different, and the table uses some different flags. */ + +/* Use some short hand macros to keep down the length of the lines in + the opcodes table. */ + +#define UBD INSN_UNCOND_BRANCH_DELAY +#define BR MIPS16_INSN_BRANCH + +#define WR_x MIPS16_INSN_WRITE_X +#define WR_y MIPS16_INSN_WRITE_Y +#define WR_z MIPS16_INSN_WRITE_Z +#define WR_T MIPS16_INSN_WRITE_T +#define WR_SP MIPS16_INSN_WRITE_SP +#define WR_31 MIPS16_INSN_WRITE_31 +#define WR_Y MIPS16_INSN_WRITE_GPR_Y + +#define RD_x MIPS16_INSN_READ_X +#define RD_y MIPS16_INSN_READ_Y +#define RD_Z MIPS16_INSN_READ_Z +#define RD_T MIPS16_INSN_READ_T +#define RD_SP MIPS16_INSN_READ_SP +#define RD_31 MIPS16_INSN_READ_31 +#define RD_PC MIPS16_INSN_READ_PC +#define RD_X MIPS16_INSN_READ_GPR_X + +#define WR_HI INSN_WRITE_HI +#define WR_LO INSN_WRITE_LO +#define RD_HI INSN_READ_HI +#define RD_LO INSN_READ_LO + +#define TRAP INSN_TRAP + +#define I3 INSN_ISA3 + +#define T3 INSN_3900 + +const struct mips_opcode mips16_opcodes[] = +{ +{"nop", "", 0x6500, 0xffff, RD_Z, 0 }, /* move $0,$Z */ +{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0 }, +{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0 }, +{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 }, +{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 }, +{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 }, +{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 }, +{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0 }, +{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 }, +{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 }, +{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, +{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 }, +{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 }, +{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0 }, +{"b", "q", 0x1000, 0xf800, BR, 0 }, +{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0 }, +{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0 }, +{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0 }, +{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0 }, +{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0 }, +{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0 }, +{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0 }, +{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0 }, +{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0 }, +{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0 }, +{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0 }, +{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0 }, +{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0 }, +{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0 }, +{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0 }, +{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0 }, +{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0 }, +{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0 }, +{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0 }, +{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0 }, +{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0 }, +{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0 }, +{"break", "6", 0xe805, 0xf81f, TRAP, 0 }, +{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0 }, +{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0 }, +{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 }, +{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0 }, +{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 }, +{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, +{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, +{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, +{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, I3 }, +{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, +{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, +{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, +{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0 }, +{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0 }, +{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0 }, +{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0 }, +{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 }, +{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0 }, +{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0 }, +{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 }, +{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 }, +{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 }, +{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, I3 }, +{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0 }, +{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0 }, +{"exit", "L", 0xed09, 0xff1f, TRAP, 0 }, +{"exit", "L", 0xee09, 0xff1f, TRAP, 0 }, +{"exit", "L", 0xef09, 0xff1f, TRAP, 0 }, +{"entry", "l", 0xe809, 0xf81f, TRAP, 0 }, +{"extend", "e", 0xf000, 0xf800, 0, 0 }, +{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, +{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0 }, +{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0 }, +{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 }, +{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0 }, +{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 }, +{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0 }, +{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0 }, +{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0 }, +{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 }, +{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, +{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, +{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 }, +{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0 }, +{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0 }, +{"li", "x,U", 0x6800, 0xf800, WR_x, 0 }, +{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0 }, +{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0 }, +{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0 }, +{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0 }, +{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 }, +{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0 }, +{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0 }, +{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0 }, +{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0 }, +{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0 }, +{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0 }, +{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0 }, +{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0 }, +{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0 }, +{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, +{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0 }, +{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0 }, +{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 }, +{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0 }, +{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0 }, +{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0 }, +{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 }, +{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0 }, +{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 }, +{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 }, +{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0 }, +{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 }, +{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0 }, +{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0 }, +{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 }, +{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0 }, +{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0 }, +{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0 }, +{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0 }, +{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0 }, +{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0 }, +{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0 }, +}; + +const int bfd_mips16_num_opcodes = + ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0]))); diff --git a/opcodes/mmix-dis.c b/opcodes/mmix-dis.c new file mode 100644 index 0000000..c81e679 --- /dev/null +++ b/opcodes/mmix-dis.c @@ -0,0 +1,523 @@ +/* mmix-dis.c -- Disassemble MMIX instructions. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + +This file is part of GDB and the GNU binutils. + +GDB and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version 2, +or (at your option) any later version. + +GDB and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include +#include +#include "opcode/mmix.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "bfd.h" +#include "opintl.h" + +#define BAD_CASE(x) \ + do \ + { \ + fprintf (stderr, \ + _("Bad case %d (%s) in %s:%d\n"), \ + x, #x, __FILE__, __LINE__); \ + abort (); \ + } \ + while (0) + +#define FATAL_DEBUG \ + do \ + { \ + fprintf (stderr, \ + _("Internal: Non-debugged code (test-case missing): %s:%d"), \ + __FILE__, __LINE__); \ + abort (); \ + } \ + while (0) + +#define ROUND_MODE(n) \ + ((n) == 1 ? "ROUND_OFF" : (n) == 2 ? "ROUND_UP" : \ + (n) == 3 ? "ROUND_DOWN" : (n) == 4 ? "ROUND_NEAR" : \ + _("(unknown)")) + +#define INSN_IMMEDIATE_BIT (IMM_OFFSET_BIT << 24) +#define INSN_BACKWARD_OFFSET_BIT (1 << 24) + +struct mmix_dis_info + { + const char *reg_name[256]; + const char *spec_reg_name[32]; + + /* Waste a little memory so we don't have to allocate each separately. + We could have an array with static contents for these, but on the + other hand, we don't have to. */ + char basic_reg_name[256][sizeof ("$255")]; + }; + +static boolean initialize_mmix_dis_info PARAMS ((struct disassemble_info *)); +static const struct mmix_opcode *get_opcode PARAMS ((unsigned long)); + + +/* Initialize a target-specific array in INFO. */ + +static boolean +initialize_mmix_dis_info (info) + struct disassemble_info *info; +{ + struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info)); + int i; + + if (minfop == NULL) + return false; + + memset (minfop, 0, sizeof (*minfop)); + + /* Initialize register names from register symbols. If there's no + register section, then there are no register symbols. */ + if ((info->section != NULL && info->section->owner != NULL) + || (info->symbols != NULL + && info->symbols[0] != NULL + && bfd_asymbol_bfd (info->symbols[0]) != NULL)) + { + bfd *abfd = info->section && info->section->owner != NULL + ? info->section->owner + : bfd_asymbol_bfd (info->symbols[0]); + asection *reg_section = bfd_get_section_by_name (abfd, "*REG*"); + + if (reg_section != NULL) + { + /* The returned symcount *does* include the ending NULL. */ + long symsize = bfd_get_symtab_upper_bound (abfd); + asymbol **syms = malloc (symsize); + long nsyms; + long i; + + if (syms == NULL) + { FATAL_DEBUG; + free (minfop); + return false; + } + nsyms = bfd_canonicalize_symtab (abfd, syms); + + /* We use the first name for a register. If this is MMO, then + it's the name with the first sequence number, presumably the + first in the source. */ + for (i = 0; i < nsyms && syms[i] != NULL; i++) + { + if (syms[i]->section == reg_section + && syms[i]->value < 256 + && minfop->reg_name[syms[i]->value] == NULL) + minfop->reg_name[syms[i]->value] = syms[i]->name; + } + } + } + + /* Fill in the rest with the canonical names. */ + for (i = 0; i < 256; i++) + if (minfop->reg_name[i] == NULL) + { + sprintf (minfop->basic_reg_name[i], "$%d", i); + minfop->reg_name[i] = minfop->basic_reg_name[i]; + } + + /* We assume it's actually a one-to-one mapping of number-to-name. */ + for (i = 0; mmix_spec_regs[i].name != NULL; i++) + minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name; + + info->private_data = (PTR) minfop; + return true; +} + +/* A table indexed by the first byte is constructed as we disassemble each + tetrabyte. The contents is a pointer into mmix_insns reflecting the + first found entry with matching match-bits and lose-bits. Further + entries are considered one after one until the operand constraints + match or the match-bits and lose-bits do not match. Normally a + "further entry" will just show that there was no other match. */ + +static const struct mmix_opcode * +get_opcode (insn) + unsigned long insn; +{ + static const struct mmix_opcode **opcodes = NULL; + const struct mmix_opcode *opcodep = mmix_opcodes; + unsigned int opcode_part = (insn >> 24) & 255; + if (opcodes == NULL) + opcodes = xcalloc (256, sizeof (struct mmix_opcode *)); + + opcodep = opcodes[opcode_part]; + if (opcodep == NULL + || (opcodep->match & insn) != opcodep->match + || (opcodep->lose & insn) != 0) + { + /* Search through the table. */ + for (opcodep = mmix_opcodes; opcodep->name != NULL; opcodep++) + { + /* FIXME: Break out this into an initialization function. */ + if ((opcodep->match & (opcode_part << 24)) == opcode_part + && (opcodep->lose & (opcode_part << 24)) == 0) + opcodes[opcode_part] = opcodep; + + if ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0) + break; + } + } + + if (opcodep->name == NULL) + return NULL; + + /* Check constraints. If they don't match, loop through the next opcode + entries. */ + do + { + switch (opcodep->operands) + { + /* These have no restraint on what can be in the lower three + bytes. */ + case mmix_operands_regs: + case mmix_operands_reg_yz: + case mmix_operands_regs_z_opt: + case mmix_operands_regs_z: + case mmix_operands_jmp: + case mmix_operands_pushgo: + case mmix_operands_pop: + case mmix_operands_sync: + case mmix_operands_x_regs_z: + case mmix_operands_neg: + case mmix_operands_pushj: + case mmix_operands_regaddr: + case mmix_operands_get: + case mmix_operands_set: + case mmix_operands_save: + case mmix_operands_unsave: + case mmix_operands_xyz_opt: + return opcodep; + + /* For a ROUND_MODE, the middle byte must be 0..4. */ + case mmix_operands_roundregs_z: + case mmix_operands_roundregs: + { + int midbyte = (insn >> 8) & 255; + if (midbyte <= 4) + return opcodep; + } + break; + + case mmix_operands_put: + /* A "PUT". If it is "immediate", then no restrictions, + otherwise we have to make sure the register number is < 32. */ + if ((insn & INSN_IMMEDIATE_BIT) + || ((insn >> 16) & 255) < 32) + return opcodep; + break; + + case mmix_operands_resume: + /* Middle bytes must be zero. */ + if ((insn & 0x00ffff00) == 0) + return opcodep; + break; + + default: + BAD_CASE (opcodep->operands); + } + + opcodep++; + } + while ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0); + + /* If we got here, we had no match. */ + return NULL; +} + +/* The main disassembly function. */ + +int +print_insn_mmix (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + unsigned char buffer[4]; + unsigned long insn; + unsigned int x, y, z; + const struct mmix_opcode *opcodep; + int status = (*info->read_memory_func) (memaddr, buffer, 4, info); + struct mmix_dis_info *minfop; + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* FIXME: Is -1 suitable? */ + if (info->private_data == NULL + && ! initialize_mmix_dis_info (info)) + return -1; + + minfop = (struct mmix_dis_info *) info->private_data; + x = buffer[1]; + y = buffer[2]; + z = buffer[3]; + + insn = bfd_getb32 (buffer); + + opcodep = get_opcode (insn); + + if (opcodep == NULL) + { + (*info->fprintf_func) (info->stream, _("*unknown*")); + return 4; + } + + (*info->fprintf_func) (info->stream, "%s ", opcodep->name); + + /* Present bytes in the order they are laid out in memory. */ + info->display_endian = BFD_ENDIAN_BIG; + + info->insn_info_valid = 1; + info->bytes_per_chunk = 4; + info->branch_delay_insns = 0; + info->target = 0; + switch (opcodep->type) + { + case mmix_type_normal: + case mmix_type_memaccess_block: + info->insn_type = dis_nonbranch; + break; + + case mmix_type_branch: + info->insn_type = dis_branch; + break; + + case mmix_type_condbranch: + info->insn_type = dis_condbranch; + break; + + case mmix_type_memaccess_octa: + info->insn_type = dis_dref; + info->data_size = 8; + break; + + case mmix_type_memaccess_tetra: + info->insn_type = dis_dref; + info->data_size = 4; + break; + + case mmix_type_memaccess_wyde: + info->insn_type = dis_dref; + info->data_size = 2; + break; + + case mmix_type_memaccess_byte: + info->insn_type = dis_dref; + info->data_size = 1; + break; + + case mmix_type_jsr: + info->insn_type = dis_jsr; + break; + + default: + BAD_CASE(opcodep->type); + } + + switch (opcodep->operands) + { + case mmix_operands_regs: + /* All registers: "$X,$Y,$Z". */ + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + minfop->reg_name[y], + minfop->reg_name[z]); + break; + + case mmix_operands_reg_yz: + /* Like SETH - "$X,YZ". */ + (*info->fprintf_func) (info->stream, "%s,0x%x", + minfop->reg_name[x], y * 256 + z); + break; + + case mmix_operands_regs_z_opt: + case mmix_operands_regs_z: + case mmix_operands_pushgo: + /* The regular "$X,$Y,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%s,%d", + minfop->reg_name[x], minfop->reg_name[y], z); + else + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + minfop->reg_name[y], + minfop->reg_name[z]); + break; + + case mmix_operands_jmp: + /* Address; only JMP. */ + { + bfd_signed_vma offset = (x * 65536 + y * 256 + z) * 4; + + if (insn & INSN_BACKWARD_OFFSET_BIT) + offset -= (256 * 65536) * 4; + + info->target = memaddr + offset; + (*info->print_address_func) (memaddr + offset, info); + } + break; + + case mmix_operands_roundregs_z: + /* Two registers, like FLOT, possibly with rounding: "$X,$Z|Z" + "$X,ROUND_MODE,$Z|Z". */ + if (y != 0) + { + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%s,%d", + minfop->reg_name[x], + ROUND_MODE (y), z); + else + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + ROUND_MODE (y), + minfop->reg_name[z]); + } + else + { + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%d", + minfop->reg_name[x], z); + else + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->reg_name[z]); + } + break; + + case mmix_operands_pop: + /* Like POP - "X,YZ". */ + (*info->fprintf_func) (info->stream, "%d,%d", x, y*256 + z); + break; + + case mmix_operands_roundregs: + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + if (y != 0) + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + ROUND_MODE (y), + minfop->reg_name[z]); + else + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->reg_name[z]); + break; + + case mmix_operands_sync: + /* Like SYNC - "XYZ". */ + (*info->fprintf_func) (info->stream, "%u", + x * 65536 + y * 256 + z); + break; + + case mmix_operands_x_regs_z: + /* Like SYNCD - "X,$Y,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%d,%s,%d", + x, minfop->reg_name[y], z); + else + (*info->fprintf_func) (info->stream, "%d,%s,%s", + x, minfop->reg_name[y], + minfop->reg_name[z]); + break; + + case mmix_operands_neg: + /* Like NEG and NEGU - "$X,Y,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%d,%d", + minfop->reg_name[x], y, z); + else + (*info->fprintf_func) (info->stream, "%s,%d,%s", + minfop->reg_name[x], y, + minfop->reg_name[z]); + break; + + case mmix_operands_pushj: + case mmix_operands_regaddr: + /* Like GETA or branches - "$X,Address". */ + { + bfd_signed_vma offset = (y * 256 + z) * 4; + + if (insn & INSN_BACKWARD_OFFSET_BIT) + offset -= 65536 * 4; + + info->target = memaddr + offset; + + (*info->fprintf_func) (info->stream, "%s,", minfop->reg_name[x]); + (*info->print_address_func) (memaddr + offset, info); + } + break; + + case mmix_operands_get: + /* GET - "X,spec_reg". */ + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->spec_reg_name[z]); + break; + + case mmix_operands_put: + /* PUT - "spec_reg,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%d", + minfop->spec_reg_name[x], z); + else + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->spec_reg_name[x], + minfop->reg_name[z]); + break; + + case mmix_operands_set: + /* Two registers, "$X,$Y". */ + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->reg_name[y]); + break; + + case mmix_operands_save: + /* SAVE - "$X,0". */ + (*info->fprintf_func) (info->stream, "%s,0", minfop->reg_name[x]); + break; + + case mmix_operands_unsave: + /* UNSAVE - "0,$Z". */ + (*info->fprintf_func) (info->stream, "0,%s", minfop->reg_name[z]); + break; + + case mmix_operands_xyz_opt: + /* Like SWYM or TRAP - "X,Y,Z". */ + (*info->fprintf_func) (info->stream, "%d,%d,%d", x, y, z); + break; + + case mmix_operands_resume: + /* Just "Z", like RESUME. */ + (*info->fprintf_func) (info->stream, "%d", z); + break; + + default: + (*info->fprintf_func) (info->stream, _("*unknown operands type: %d*"), + opcodep->operands); + break; + } + + return 4; +} diff --git a/opcodes/mmix-opc.c b/opcodes/mmix-opc.c new file mode 100644 index 0000000..76dc5d8 --- /dev/null +++ b/opcodes/mmix-opc.c @@ -0,0 +1,340 @@ +/* mmix-opc.c -- MMIX opcode table + Copyright (C) 2001 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version 2, +or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "opcode/mmix.h" +#include "symcat.h" + +/* Register-name-table for special registers. */ +const struct mmix_spec_reg mmix_spec_regs[] = + { + /* Keep rJ at top; it's the most frequently used one. */ + {"rJ", 4}, + {"rA", 21}, + {"rB", 0}, + {"rC", 8}, + {"rD", 1}, + {"rE", 2}, + {"rF", 22}, + {"rG", 19}, + {"rH", 3}, + {"rI", 12}, + {"rK", 15}, + {"rL", 20}, + {"rM", 5}, + {"rN", 9}, + {"rO", 10}, + {"rP", 23}, + {"rQ", 16}, + {"rR", 6}, + {"rS", 11}, + {"rT", 13}, + {"rU", 17}, + {"rV", 18}, + {"rW", 24}, + {"rX", 25}, + {"rY", 26}, + {"rZ", 27}, + {"rBB", 7}, + {"rTT", 14}, + {"rWW", 28}, + {"rXX", 29}, + {"rYY", 30}, + {"rZZ", 31}, + {NULL, 0} + }; + +/* Opcode-table. In order to cut down on redundant contents, we use helper + macros. */ + +/* All bits in the opcode-byte are significant. Add "| ..." expressions + to add zero-bits. */ +#undef O +#define O(m) ((m) << 24), ((~(m) & 255) << 24) + +/* Bits 7..1 of the opcode are significant. */ +#undef Z +#define Z(m) ((m) << 24), ((~(m) & 254) << 24) + +/* For easier overview of the table. */ +#define N mmix_type_normal +#define B mmix_type_branch +#define C mmix_type_condbranch +#define MB mmix_type_memaccess_byte +#define MW mmix_type_memaccess_wyde +#define MT mmix_type_memaccess_tetra +#define MO mmix_type_memaccess_octa +#define M mmix_type_memaccess_block +#define J mmix_type_jsr +#define P mmix_type_pseudo + +#define OP(y) XCONCAT2 (mmix_operands_,y) + +/* Groups of instructions specified here must, if all are matching the + same instruction, be consecutive, in order more-specific to + less-specific match. */ + +const struct mmix_opcode mmix_opcodes[] = + { + {"trap", O (0), OP (xyz_opt), J}, + {"fcmp", O (1), OP (regs), N}, + {"flot", Z (8), OP (roundregs_z), N}, + + {"fun", O (2), OP (regs), N}, + {"feql", O (3), OP (regs), N}, + {"flotu", Z (10), OP (roundregs_z), N}, + + {"fadd", O (4), OP (regs), N}, + {"fix", O (5), OP (roundregs), N}, + {"sflot", Z (12), OP (roundregs_z), N}, + + {"fsub", O (6), OP (regs), N}, + {"fixu", O (7), OP (roundregs), N}, + {"sflotu", Z (14), OP (roundregs_z), N}, + + {"fmul", O (16), OP (regs), N}, + {"fcmpe", O (17), OP (regs), N}, + {"mul", Z (24), OP (regs_z), N}, + + {"fune", O (18), OP (regs), N}, + {"feqle", O (19), OP (regs), N}, + {"mulu", Z (26), OP (regs_z), N}, + + {"fdiv", O (20), OP (regs), N}, + {"fsqrt", O (21), OP (roundregs), N}, + {"div", Z (28), OP (regs_z), N}, + + {"frem", O (22), OP (regs), N}, + {"fint", O (23), OP (roundregs), N}, + {"divu", Z (30), OP (regs_z), N}, + + {"add", Z (0x20), OP (regs_z), N}, + {"2addu", Z (0x28), OP (regs_z), N}, + + {"addu", Z (0x22), OP (regs_z), N}, + /* Synonym for ADDU. Put after ADDU, since we don't prefer it for + disassembly. It's supposed to be used for addresses, so we make it + a memory block reference for purposes of assembly. */ + {"lda", Z (0x22), OP (regs_z_opt), M}, + {"4addu", Z (0x2a), OP (regs_z), N}, + + {"sub", Z (0x24), OP (regs_z), N}, + {"8addu", Z (0x2c), OP (regs_z), N}, + + {"subu", Z (0x26), OP (regs_z), N}, + {"16addu", Z (0x2e), OP (regs_z), N}, + + {"cmp", Z (0x30), OP (regs_z), N}, + {"sl", Z (0x38), OP (regs_z), N}, + + {"cmpu", Z (0x32), OP (regs_z), N}, + {"slu", Z (0x3a), OP (regs_z), N}, + + {"neg", Z (0x34), OP (neg), N}, + {"sr", Z (0x3c), OP (regs_z), N}, + + {"negu", Z (0x36), OP (neg), N}, + {"sru", Z (0x3e), OP (regs_z), N}, + + {"bn", Z (0x40), OP (regaddr), C}, + {"bnn", Z (0x48), OP (regaddr), C}, + + {"bz", Z (0x42), OP (regaddr), C}, + {"bnz", Z (0x4a), OP (regaddr), C}, + + {"bp", Z (0x44), OP (regaddr), C}, + {"bnp", Z (0x4c), OP (regaddr), C}, + + {"bod", Z (0x46), OP (regaddr), C}, + {"bev", Z (0x4e), OP (regaddr), C}, + + {"pbn", Z (0x50), OP (regaddr), C}, + {"pbnn", Z (0x58), OP (regaddr), C}, + + {"pbz", Z (0x52), OP (regaddr), C}, + {"pbnz", Z (0x5a), OP (regaddr), C}, + + {"pbp", Z (0x54), OP (regaddr), C}, + {"pbnp", Z (0x5c), OP (regaddr), C}, + + {"pbod", Z (0x56), OP (regaddr), C}, + {"pbev", Z (0x5e), OP (regaddr), C}, + + {"csn", Z (0x60), OP (regs_z), N}, + {"csnn", Z (0x68), OP (regs_z), N}, + + {"csz", Z (0x62), OP (regs_z), N}, + {"csnz", Z (0x6a), OP (regs_z), N}, + + {"csp", Z (0x64), OP (regs_z), N}, + {"csnp", Z (0x6c), OP (regs_z), N}, + + {"csod", Z (0x66), OP (regs_z), N}, + {"csev", Z (0x6e), OP (regs_z), N}, + + {"zsn", Z (0x70), OP (regs_z), N}, + {"zsnn", Z (0x78), OP (regs_z), N}, + + {"zsz", Z (0x72), OP (regs_z), N}, + {"zsnz", Z (0x7a), OP (regs_z), N}, + + {"zsp", Z (0x74), OP (regs_z), N}, + {"zsnp", Z (0x7c), OP (regs_z), N}, + + {"zsod", Z (0x76), OP (regs_z), N}, + {"zsev", Z (0x7e), OP (regs_z), N}, + + {"ldb", Z (0x80), OP (regs_z_opt), MB}, + {"ldt", Z (0x88), OP (regs_z_opt), MT}, + + {"ldbu", Z (0x82), OP (regs_z_opt), MB}, + {"ldtu", Z (0x8a), OP (regs_z_opt), MT}, + + {"ldw", Z (0x84), OP (regs_z_opt), MW}, + {"ldo", Z (0x8c), OP (regs_z_opt), MO}, + + {"ldwu", Z (0x86), OP (regs_z_opt), MW}, + {"ldou", Z (0x8e), OP (regs_z_opt), MO}, + + {"ldsf", Z (0x90), OP (regs_z_opt), MT}, + + /* This doesn't seem to access memory, just the TLB. */ + {"ldvts", Z (0x98), OP (regs_z_opt), M}, + + {"ldht", Z (0x92), OP (regs_z_opt), MT}, + + /* Neither does this per-se. */ + {"preld", Z (0x9a), OP (x_regs_z), N}, + + {"cswap", Z (0x94), OP (regs_z_opt), MO}, + {"prego", Z (0x9c), OP (x_regs_z), N}, + + {"ldunc", Z (0x96), OP (regs_z_opt), MO}, + {"go", Z (0x9e), OP (regs_z_opt), B}, + + {"stb", Z (0xa0), OP (regs_z_opt), MB}, + {"stt", Z (0xa8), OP (regs_z_opt), MT}, + + {"stbu", Z (0xa2), OP (regs_z_opt), MB}, + {"sttu", Z (0xaa), OP (regs_z_opt), MT}, + + {"stw", Z (0xa4), OP (regs_z_opt), MW}, + {"sto", Z (0xac), OP (regs_z_opt), MO}, + + {"stwu", Z (0xa6), OP (regs_z_opt), MW}, + {"stou", Z (0xae), OP (regs_z_opt), MO}, + + {"stsf", Z (0xb0), OP (regs_z_opt), MT}, + {"syncd", Z (0xb8), OP (x_regs_z), M}, + + {"stht", Z (0xb2), OP (regs_z_opt), MT}, + {"prest", Z (0xba), OP (x_regs_z), M}, + + {"stco", Z (0xb4), OP (x_regs_z), MO}, + {"syncid", Z (0xbc), OP (x_regs_z), M}, + + {"stunc", Z (0xb6), OP (regs_z_opt), MO}, + {"pushgo", Z (0xbe), OP (pushgo), J}, + + /* Synonym for OR with a zero Z. */ + {"set", O (0xc1) + | 0xff, OP (set), N}, + + {"or", Z (0xc0), OP (regs_z), N}, + {"and", Z (0xc8), OP (regs_z), N}, + + {"orn", Z (0xc2), OP (regs_z), N}, + {"andn", Z (0xca), OP (regs_z), N}, + + {"nor", Z (0xc4), OP (regs_z), N}, + {"nand", Z (0xcc), OP (regs_z), N}, + + {"xor", Z (0xc6), OP (regs_z), N}, + {"nxor", Z (0xce), OP (regs_z), N}, + + {"bdif", Z (0xd0), OP (regs_z), N}, + {"mux", Z (0xd8), OP (regs_z), N}, + + {"wdif", Z (0xd2), OP (regs_z), N}, + {"sadd", Z (0xda), OP (regs_z), N}, + + {"tdif", Z (0xd4), OP (regs_z), N}, + {"mor", Z (0xdc), OP (regs_z), N}, + + {"odif", Z (0xd6), OP (regs_z), N}, + {"mxor", Z (0xde), OP (regs_z), N}, + + {"seth", O (0xe0), OP (reg_yz), N}, + {"setmh", O (0xe1), OP (reg_yz), N}, + {"orh", O (0xe8), OP (reg_yz), N}, + {"ormh", O (0xe9), OP (reg_yz), N}, + + {"setml", O (0xe2), OP (reg_yz), N}, + {"setl", O (0xe3), OP (reg_yz), N}, + {"orml", O (0xea), OP (reg_yz), N}, + {"orl", O (0xeb), OP (reg_yz), N}, + + {"inch", O (0xe4), OP (reg_yz), N}, + {"incmh", O (0xe5), OP (reg_yz), N}, + {"andnh", O (0xec), OP (reg_yz), N}, + {"andnmh", O (0xed), OP (reg_yz), N}, + + {"incml", O (0xe6), OP (reg_yz), N}, + {"incl", O (0xe7), OP (reg_yz), N}, + {"andnml", O (0xee), OP (reg_yz), N}, + {"andnl", O (0xef), OP (reg_yz), N}, + + {"jmp", Z (0xf0), OP (jmp), B}, + {"pop", O (0xf8), OP (pop), B}, + {"resume", O (0xf9) + | 0xffff00, OP (resume), B}, + + {"pushj", Z (0xf2), OP (pushj), J}, + {"save", O (0xfa) + | 0xffff, OP (save), M}, + {"unsave", O (0xfb) + | 0xffff00, OP (unsave), M}, + + {"geta", Z (0xf4), OP (regaddr), N}, + {"sync", O (0xfc), OP (sync), N}, + {"swym", O (0xfd), OP (xyz_opt), N}, + + {"put", Z (0xf6) | 0xff00, OP (put), N}, + {"get", O (0xfe) | 0xffe0, OP (get), N}, + {"trip", O (0xff), OP (xyz_opt), J}, + + /* We have mmixal pseudos in the ordinary instruction table so we can + avoid the "set" vs. ".set" ambiguity that would be the effect if we + had pseudos handled "normally" and defined NO_PSEUDO_DOT. + + Note that IS and GREG are handled fully by md_start_line_hook, so + they're not here. */ + {"loc", ~0, ~0, OP (loc), P}, + {"prefix", ~0, ~0, OP (prefix), P}, + {"byte", ~0, ~0, OP (byte), P}, + {"wyde", ~0, ~0, OP (wyde), P}, + {"tetra", ~0, ~0, OP (tetra), P}, + {"octa", ~0, ~0, OP (octa), P}, + {"local", ~0, ~0, OP (local), P}, + {"bspec", ~0, ~0, OP (bspec), P}, + {"espec", ~0, ~0, OP (espec), P}, + + {NULL, ~0, ~0, OP (none), N} + }; diff --git a/opcodes/mpw-config.in b/opcodes/mpw-config.in new file mode 100644 index 0000000..ff9be9d --- /dev/null +++ b/opcodes/mpw-config.in @@ -0,0 +1,27 @@ +# Configuration fragment for opcodes. + +Set target_arch `echo {target_canonical} | sed -e 's/-.*-.*//'` + +Set archname ARCH_{target_arch} + +If "{target_arch}" =~ /m68k/ + Set BFD_MACHINES '"{o}"m68k-dis.c.o "{o}"m68k-opc.c.o' +Else If "{target_arch}" =~ /powerpc/ + Set BFD_MACHINES '"{o}"ppc-dis.c.o "{o}"ppc-opc.c.o' +Else If "{target_arch}" =~ /i386/ + Set BFD_MACHINES '"{o}"i386-dis.c.o' +Else If "{target_arch}" =~ /mips/ + Set BFD_MACHINES '"{o}"mips-dis.c.o "{o}"mips-opc.c.o' +Else If "{target_arch}" =~ /sh/ + Set BFD_MACHINES '"{o}"sh-dis.c.o' +End If + +Echo '# Start from mpw-config.in' > "{o}"mk.tmp +Echo "BFD_MACHINES = " {BFD_MACHINES} >> "{o}"mk.tmp +Echo "ARCHDEFS = -d" {archname} >> "{o}"mk.tmp +Echo '# End from mpw-config.in' >> "{o}"mk.tmp + +Echo '/* config.h. Generated by mpw-configure. */' > "{o}"config.new +Echo '#include "mpw.h"' >> "{o}"config.new + +MoveIfChange "{o}"config.new "{o}"config.h diff --git a/opcodes/mpw-make.sed b/opcodes/mpw-make.sed new file mode 100644 index 0000000..ee60486 --- /dev/null +++ b/opcodes/mpw-make.sed @@ -0,0 +1,25 @@ +# Sed commands to finish translating the opcodes Makefile.in into MPW syntax. + +# Empty HDEFINES. +/HDEFINES/s/@HDEFINES@// + +# Fix pathnames to include directories. +/^INCDIR = /s/^INCDIR = .*$/INCDIR = "{topsrcdir}"include/ +/^CSEARCH = /s/$/ -i "{INCDIR}":mpw: -i ::extra-include:/ + +/BFD_MACHINES/s/@BFD_MACHINES@/{BFD_MACHINES}/ +/archdefs/s/@archdefs@/{ARCHDEFS}/ + +# No PIC foolery in this environment. +/@ALLLIBS@/s/@ALLLIBS@/{TARGETLIB}/ +/@PICLIST@/s/@PICLIST@// +/@PICFLAG@/s/@PICFLAG@// +/^{OFILES} \\Option-f stamp-picdir/,/^$/d + +# Remove the pic trickery from the default build rule. +/^\.c\.o \\Option-f /,/End If/c\ +.c.o \\Option-f .c + +# Remove pic trickery from other rules - aimed at the rule +# for disassemble.o in particular. +/-n "{PICFLAG}"/,/End If/d diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c new file mode 100644 index 0000000..49facb3 --- /dev/null +++ b/opcodes/ns32k-dis.c @@ -0,0 +1,904 @@ +/* Print National Semiconductor 32000 instructions. + Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001 + Free Software Foundation, Inc. + +This file is part of opcodes library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include "bfd.h" +#include "sysdep.h" +#include "dis-asm.h" +#if !defined(const) && !defined(__STDC__) +#define const +#endif +#include "opcode/ns32k.h" +#include "opintl.h" + +static disassemble_info *dis_info; + +/* + * Hacks to get it to compile <= READ THESE AS FIXES NEEDED + */ +#define INVALID_FLOAT(val, size) invalid_float((char *)val, size) + +static int print_insn_arg + PARAMS ((int, int, int *, char *, bfd_vma, char *, int)); +static int get_displacement PARAMS ((char *, int *)); +static int invalid_float PARAMS ((char *, int)); +static long int read_memory_integer PARAMS ((unsigned char *, int)); +static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); +struct ns32k_option; +static void optlist PARAMS ((int, const struct ns32k_option *, char *)); +static void list_search PARAMS ((int, const struct ns32k_option *, char *)); +static int bit_extract PARAMS ((bfd_byte *, int, int)); +static int bit_extract_simple PARAMS ((bfd_byte *, int, int)); +static void bit_copy PARAMS ((char *, int, int, char *)); +static int sign_extend PARAMS ((int, int)); +static void flip_bytes PARAMS ((char *, int)); + +static long read_memory_integer(addr, nr) + unsigned char *addr; + int nr; +{ + long val; + int i; + for (val = 0, i = nr - 1; i >= 0; i--) { + val = (val << 8); + val |= (0xff & *(addr + i)); + } + return val; +} + +/* 32000 instructions are never longer than this. */ +#define MAXLEN 62 + + +#include + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (info, addr) + struct disassemble_info *info; + bfd_byte *addr; +{ + int status; + struct private *priv = (struct private *)info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} +/* Number of elements in the opcode table. */ +#define NOPCODES (sizeof ns32k_opcodes / sizeof ns32k_opcodes[0]) + +#define NEXT_IS_ADDR '|' + + +struct ns32k_option { + char *pattern; /* the option itself */ + unsigned long value; /* binary value of the option */ + unsigned long match; /* these bits must match */ +}; + + +static const struct ns32k_option opt_u[]= /* restore, exit */ +{ + { "r0", 0x80, 0x80 }, + { "r1", 0x40, 0x40 }, + { "r2", 0x20, 0x20 }, + { "r3", 0x10, 0x10 }, + { "r4", 0x08, 0x08 }, + { "r5", 0x04, 0x04 }, + { "r6", 0x02, 0x02 }, + { "r7", 0x01, 0x01 }, + { 0 , 0x00, 0x00 } +}; + +static const struct ns32k_option opt_U[]= /* save, enter */ +{ + { "r0", 0x01, 0x01 }, + { "r1", 0x02, 0x02 }, + { "r2", 0x04, 0x04 }, + { "r3", 0x08, 0x08 }, + { "r4", 0x10, 0x10 }, + { "r5", 0x20, 0x20 }, + { "r6", 0x40, 0x40 }, + { "r7", 0x80, 0x80 }, + { 0 , 0x00, 0x00 } +}; + +static const struct ns32k_option opt_O[]= /* setcfg */ +{ + { "c", 0x8, 0x8 }, + { "m", 0x4, 0x4 }, + { "f", 0x2, 0x2 }, + { "i", 0x1, 0x1 }, + { 0 , 0x0, 0x0 } +}; + +static const struct ns32k_option opt_C[]= /* cinv */ +{ + { "a", 0x4, 0x4 }, + { "i", 0x2, 0x2 }, + { "d", 0x1, 0x1 }, + { 0 , 0x0, 0x0 } +}; + +static const struct ns32k_option opt_S[]= /* string inst */ +{ + { "b", 0x1, 0x1 }, + { "u", 0x6, 0x6 }, + { "w", 0x2, 0x2 }, + { 0 , 0x0, 0x0 } +}; + +static const struct ns32k_option list_P532[]= /* lpr spr */ +{ + { "us", 0x0, 0xf }, + { "dcr", 0x1, 0xf }, + { "bpc", 0x2, 0xf }, + { "dsr", 0x3, 0xf }, + { "car", 0x4, 0xf }, + { "fp", 0x8, 0xf }, + { "sp", 0x9, 0xf }, + { "sb", 0xa, 0xf }, + { "usp", 0xb, 0xf }, + { "cfg", 0xc, 0xf }, + { "psr", 0xd, 0xf }, + { "intbase", 0xe, 0xf }, + { "mod", 0xf, 0xf }, + { 0 , 0x00, 0xf } +}; + +static const struct ns32k_option list_M532[]= /* lmr smr */ +{ + { "mcr", 0x9, 0xf }, + { "msr", 0xa, 0xf }, + { "tear", 0xb, 0xf }, + { "ptb0", 0xc, 0xf }, + { "ptb1", 0xd, 0xf }, + { "ivar0", 0xe, 0xf }, + { "ivar1", 0xf, 0xf }, + { 0 , 0x0, 0xf } +}; + +static const struct ns32k_option list_P032[]= /* lpr spr */ +{ + { "upsr", 0x0, 0xf }, + { "fp", 0x8, 0xf }, + { "sp", 0x9, 0xf }, + { "sb", 0xa, 0xf }, + { "psr", 0xb, 0xf }, + { "intbase", 0xe, 0xf }, + { "mod", 0xf, 0xf }, + { 0 , 0x0, 0xf } +}; + +static const struct ns32k_option list_M032[]= /* lmr smr */ +{ + { "bpr0", 0x0, 0xf }, + { "bpr1", 0x1, 0xf }, + { "pf0", 0x4, 0xf }, + { "pf1", 0x5, 0xf }, + { "sc", 0x8, 0xf }, + { "msr", 0xa, 0xf }, + { "bcnt", 0xb, 0xf }, + { "ptb0", 0xc, 0xf }, + { "ptb1", 0xd, 0xf }, + { "eia", 0xf, 0xf }, + { 0 , 0x0, 0xf } +}; + + +/* + * figure out which options are present + */ +static void +optlist(options, optionP, result) + int options; + const struct ns32k_option *optionP; + char *result; +{ + if (options == 0) { + sprintf(result, "[]"); + return; + } + sprintf(result, "["); + + for (; (options != 0) && optionP->pattern; optionP++) { + if ((options & optionP->match) == optionP->value) { + /* we found a match, update result and options */ + strcat(result, optionP->pattern); + options &= ~optionP->value; + if (options != 0) /* more options to come */ + strcat(result, ","); + } + } + if (options != 0) + strcat(result, "undefined"); + + strcat(result, "]"); +} + +static void +list_search (reg_value, optionP, result) + int reg_value; + const struct ns32k_option *optionP; + char *result; +{ + for (; optionP->pattern; optionP++) { + if ((reg_value & optionP->match) == optionP->value) { + sprintf(result, "%s", optionP->pattern); + return; + } + } + sprintf(result, "undefined"); +} + +/* + * extract "count" bits starting "offset" bits + * into buffer + */ + +static int +bit_extract (buffer, offset, count) + bfd_byte *buffer; + int offset; + int count; +{ + int result; + int bit; + + buffer += offset >> 3; + offset &= 7; + bit = 1; + result = 0; + while (count--) + { + FETCH_DATA(dis_info, buffer + 1); + if ((*buffer & (1 << offset))) + result |= bit; + if (++offset == 8) + { + offset = 0; + buffer++; + } + bit <<= 1; + } + return result; +} + +/* Like bit extract but the buffer is valid and doen't need to be + * fetched + */ +static int +bit_extract_simple (buffer, offset, count) + bfd_byte *buffer; + int offset; + int count; +{ + int result; + int bit; + + buffer += offset >> 3; + offset &= 7; + bit = 1; + result = 0; + while (count--) + { + if ((*buffer & (1 << offset))) + result |= bit; + if (++offset == 8) + { + offset = 0; + buffer++; + } + bit <<= 1; + } + return result; +} + +static void +bit_copy (buffer, offset, count, to) + char *buffer; + int offset; + int count; + char *to; +{ + for(; count > 8; count -= 8, to++, offset += 8) + *to = bit_extract (buffer, offset, 8); + *to = bit_extract (buffer, offset, count); +} + + +static int +sign_extend (value, bits) + int value, bits; +{ + value = value & ((1 << bits) - 1); + return (value & (1 << (bits-1)) + ? value | (~((1 << bits) - 1)) + : value); +} + +static void +flip_bytes (ptr, count) + char *ptr; + int count; +{ + char tmp; + + while (count > 0) + { + tmp = ptr[0]; + ptr[0] = ptr[count-1]; + ptr[count-1] = tmp; + ptr++; + count -= 2; + } +} + +/* Given a character C, does it represent a general addressing mode? */ +#define Is_gen(c) \ + ((c) == 'F' || (c) == 'L' || (c) == 'B' \ + || (c) == 'W' || (c) == 'D' || (c) == 'A' || (c) == 'I' || (c) == 'Z') + +/* Adressing modes. */ +#define Adrmod_index_byte 0x1c +#define Adrmod_index_word 0x1d +#define Adrmod_index_doubleword 0x1e +#define Adrmod_index_quadword 0x1f + +/* Is MODE an indexed addressing mode? */ +#define Adrmod_is_index(mode) \ + (mode == Adrmod_index_byte \ + || mode == Adrmod_index_word \ + || mode == Adrmod_index_doubleword \ + || mode == Adrmod_index_quadword) + + +/* Print the 32000 instruction at address MEMADDR in debugged memory, + on STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_ns32k (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + register unsigned int i; + register char *d; + unsigned short first_word; + int ioffset; /* bits into instruction */ + int aoffset; /* bits into arguments */ + char arg_bufs[MAX_ARGS+1][ARG_LEN]; + int argnum; + int maxarg; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + dis_info = info; + + info->private_data = (PTR) &priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + /* Look for 8bit opcodes first. Other wise, fetching two bytes could take + * us over the end of accessible data unnecessarilly + */ + FETCH_DATA(info, buffer + 1); + for (i = 0; i < NOPCODES; i++) + if (ns32k_opcodes[i].opcode_id_size <= 8 + && ((buffer[0] + & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) + == ns32k_opcodes[i].opcode_seed)) + break; + if (i == NOPCODES) { + /* Maybe it is 9 to 16 bits big */ + FETCH_DATA(info, buffer + 2); + first_word = read_memory_integer(buffer, 2); + + for (i = 0; i < NOPCODES; i++) + if ((first_word + & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) + == ns32k_opcodes[i].opcode_seed) + break; + + /* Handle undefined instructions. */ + if (i == NOPCODES) + { + (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]); + return 1; + } + } + + (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name); + + ioffset = ns32k_opcodes[i].opcode_size; + aoffset = ns32k_opcodes[i].opcode_size; + d = ns32k_opcodes[i].operands; + + if (*d) + { + /* Offset in bits of the first thing beyond each index byte. + Element 0 is for operand A and element 1 is for operand B. + The rest are irrelevant, but we put them here so we don't + index outside the array. */ + int index_offset[MAX_ARGS]; + + /* 0 for operand A, 1 for operand B, greater for other args. */ + int whicharg = 0; + + (*dis_info->fprintf_func)(dis_info->stream, "\t"); + + maxarg = 0; + + /* First we have to find and keep track of the index bytes, + if we are using scaled indexed addressing mode, since the index + bytes occur right after the basic instruction, not as part + of the addressing extension. */ + if (Is_gen(d[1])) + { + int addr_mode = bit_extract (buffer, ioffset - 5, 5); + + if (Adrmod_is_index (addr_mode)) + { + aoffset += 8; + index_offset[0] = aoffset; + } + } + if (d[2] && Is_gen(d[3])) + { + int addr_mode = bit_extract (buffer, ioffset - 10, 5); + + if (Adrmod_is_index (addr_mode)) + { + aoffset += 8; + index_offset[1] = aoffset; + } + } + + while (*d) + { + argnum = *d - '1'; + d++; + if (argnum > maxarg && argnum < MAX_ARGS) + maxarg = argnum; + ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer, + memaddr, arg_bufs[argnum], + index_offset[whicharg]); + d++; + whicharg++; + } + for (argnum = 0; argnum <= maxarg; argnum++) + { + bfd_vma addr; + char *ch; + for (ch = arg_bufs[argnum]; *ch;) + { + if (*ch == NEXT_IS_ADDR) + { + ++ch; + addr = bfd_scan_vma (ch, NULL, 16); + (*dis_info->print_address_func) (addr, dis_info); + while (*ch && *ch != NEXT_IS_ADDR) + ++ch; + if (*ch) + ++ch; + } + else + (*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++); + } + if (argnum < maxarg) + (*dis_info->fprintf_func)(dis_info->stream, ", "); + } + } + return aoffset / 8; +} + +/* Print an instruction operand of category given by d. IOFFSET is + the bit position below which small (<1 byte) parts of the operand can + be found (usually in the basic instruction, but for indexed + addressing it can be in the index byte). AOFFSETP is a pointer to the + bit position of the addressing extension. BUFFER contains the + instruction. ADDR is where BUFFER was read from. Put the disassembled + version of the operand in RESULT. INDEX_OFFSET is the bit position + of the index byte (it contains garbage if this operand is not a + general operand using scaled indexed addressing mode). */ + +static int +print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset) + int d; + int ioffset, *aoffsetp; + char *buffer; + bfd_vma addr; + char *result; + int index_offset; +{ + int addr_mode; + float Fvalue; + double Lvalue; + int Ivalue; + int disp1, disp2; + int index; + int size; + + switch (d) + { + case 'f': + /* a "gen" operand but 5 bits from the end of instruction */ + ioffset -= 5; + case 'Z': + case 'F': + case 'L': + case 'I': + case 'B': + case 'W': + case 'D': + case 'A': + addr_mode = bit_extract (buffer, ioffset-5, 5); + ioffset -= 5; + switch (addr_mode) + { + case 0x0: case 0x1: case 0x2: case 0x3: + case 0x4: case 0x5: case 0x6: case 0x7: + /* register mode R0 -- R7 */ + switch (d) + { + case 'F': + case 'L': + case 'Z': + sprintf (result, "f%d", addr_mode); + break; + default: + sprintf (result, "r%d", addr_mode); + } + break; + case 0x8: case 0x9: case 0xa: case 0xb: + case 0xc: case 0xd: case 0xe: case 0xf: + /* Register relative disp(R0 -- R7) */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(r%d)", disp1, addr_mode & 7); + break; + case 0x10: + case 0x11: + case 0x12: + /* Memory relative disp2(disp1(FP, SP, SB)) */ + disp1 = get_displacement (buffer, aoffsetp); + disp2 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(%d(%s))", disp2, disp1, + addr_mode==0x10?"fp":addr_mode==0x11?"sp":"sb"); + break; + case 0x13: + /* reserved */ + sprintf (result, "reserved"); + break; + case 0x14: + /* Immediate */ + switch (d) + { + case 'I': case 'Z': case 'A': + /* I and Z are output operands and can`t be immediate + * A is an address and we can`t have the address of + * an immediate either. We don't know how much to increase + * aoffsetp by since whatever generated this is broken + * anyway! + */ + sprintf (result, _("$")); + break; + case 'B': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + Ivalue = sign_extend (Ivalue, 8); + *aoffsetp += 8; + sprintf (result, "$%d", Ivalue); + break; + case 'W': + Ivalue = bit_extract (buffer, *aoffsetp, 16); + flip_bytes ((char *) & Ivalue, 2); + *aoffsetp += 16; + Ivalue = sign_extend (Ivalue, 16); + sprintf (result, "$%d", Ivalue); + break; + case 'D': + Ivalue = bit_extract (buffer, *aoffsetp, 32); + flip_bytes ((char *) & Ivalue, 4); + *aoffsetp += 32; + sprintf (result, "$%d", Ivalue); + break; + case 'F': + bit_copy (buffer, *aoffsetp, 32, (char *) &Fvalue); + flip_bytes ((char *) & Fvalue, 4); + *aoffsetp += 32; + if (INVALID_FLOAT (&Fvalue, 4)) + sprintf (result, "<>", *(int *) &Fvalue); + else /* assume host has ieee float */ + sprintf (result, "$%g", Fvalue); + break; + case 'L': + bit_copy (buffer, *aoffsetp, 64, (char *) &Lvalue); + flip_bytes ((char *) & Lvalue, 8); + *aoffsetp += 64; + if (INVALID_FLOAT (&Lvalue, 8)) + sprintf (result, "<>", + *(((int *) &Lvalue) + 1), *(int *) &Lvalue); + else /* assume host has ieee float */ + sprintf (result, "$%g", Lvalue); + break; + } + break; + case 0x15: + /* Absolute @disp */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "@|%d|", disp1); + break; + case 0x16: + /* External EXT(disp1) + disp2 (Mod table stuff) */ + disp1 = get_displacement (buffer, aoffsetp); + disp2 = get_displacement (buffer, aoffsetp); + sprintf (result, "EXT(%d) + %d", disp1, disp2); + break; + case 0x17: + /* Top of stack tos */ + sprintf (result, "tos"); + break; + case 0x18: + /* Memory space disp(FP) */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(fp)", disp1); + break; + case 0x19: + /* Memory space disp(SP) */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(sp)", disp1); + break; + case 0x1a: + /* Memory space disp(SB) */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(sb)", disp1); + break; + case 0x1b: + /* Memory space disp(PC) */ + disp1 = get_displacement (buffer, aoffsetp); + *result++ = NEXT_IS_ADDR; + sprintf_vma (result, addr + disp1); + result += strlen (result); + *result++ = NEXT_IS_ADDR; + *result = '\0'; + break; + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + /* Scaled index basemode[R0 -- R7:B,W,D,Q] */ + index = bit_extract (buffer, index_offset - 8, 3); + print_insn_arg (d, index_offset, aoffsetp, buffer, addr, + result, 0); + { + static const char *ind = "bwdq"; + char *off; + + off = result + strlen (result); + sprintf (off, "[r%d:%c]", index, + ind[addr_mode & 3]); + } + break; + } + break; + case 'H': + case 'q': + Ivalue = bit_extract (buffer, ioffset-4, 4); + Ivalue = sign_extend (Ivalue, 4); + sprintf (result, "%d", Ivalue); + ioffset -= 4; + break; + case 'r': + Ivalue = bit_extract (buffer, ioffset-3, 3); + sprintf (result, "r%d", Ivalue&7); + ioffset -= 3; + break; + case 'd': + sprintf (result, "%d", get_displacement (buffer, aoffsetp)); + break; + case 'b': + Ivalue = get_displacement (buffer, aoffsetp); + /* + * Warning!! HACK ALERT! + * Operand type 'b' is only used by the cmp{b,w,d} and + * movm{b,w,d} instructions; we need to know whether + * it's a `b' or `w' or `d' instruction; and for both + * cmpm and movm it's stored at the same place so we + * just grab two bits of the opcode and look at it... + * + */ + size = bit_extract(buffer, ioffset-6, 2); + if (size == 0) /* 00 => b */ + size = 1; + else if (size == 1) /* 01 => w */ + size = 2; + else + size = 4; /* 11 => d */ + + sprintf (result, "%d", (Ivalue / size) + 1); + break; + case 'p': + *result++ = NEXT_IS_ADDR; + sprintf_vma (result, addr + get_displacement (buffer, aoffsetp)); + result += strlen (result); + *result++ = NEXT_IS_ADDR; + *result = '\0'; + break; + case 'i': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + *aoffsetp += 8; + sprintf (result, "0x%x", Ivalue); + break; + case 'u': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + optlist(Ivalue, opt_u, result); + *aoffsetp += 8; + break; + case 'U': + Ivalue = bit_extract(buffer, *aoffsetp, 8); + optlist(Ivalue, opt_U, result); + *aoffsetp += 8; + break; + case 'O': + Ivalue = bit_extract(buffer, ioffset-9, 9); + optlist(Ivalue, opt_O, result); + ioffset -= 9; + break; + case 'C': + Ivalue = bit_extract(buffer, ioffset-4, 4); + optlist(Ivalue, opt_C, result); + ioffset -= 4; + break; + case 'S': + Ivalue = bit_extract(buffer, ioffset - 8, 8); + optlist(Ivalue, opt_S, result); + ioffset -= 8; + break; + case 'M': + Ivalue = bit_extract(buffer, ioffset-4, 4); + list_search(Ivalue, 0 ? list_M032 : list_M532, result); + ioffset -= 4; + break; + case 'P': + Ivalue = bit_extract(buffer, ioffset-4, 4); + list_search(Ivalue, 0 ? list_P032 : list_P532, result); + ioffset -= 4; + break; + case 'g': + Ivalue = bit_extract(buffer, *aoffsetp, 3); + sprintf(result, "%d", Ivalue); + *aoffsetp += 3; + break; + case 'G': + Ivalue = bit_extract(buffer, *aoffsetp, 5); + sprintf(result, "%d", Ivalue + 1); + *aoffsetp += 5; + break; + } + return ioffset; +} + +static int +get_displacement (buffer, aoffsetp) + char *buffer; + int *aoffsetp; +{ + int Ivalue; + short Ivalue2; + + Ivalue = bit_extract (buffer, *aoffsetp, 8); + switch (Ivalue & 0xc0) + { + case 0x00: + case 0x40: + Ivalue = sign_extend (Ivalue, 7); + *aoffsetp += 8; + break; + case 0x80: + Ivalue2 = bit_extract (buffer, *aoffsetp, 16); + flip_bytes ((char *) & Ivalue2, 2); + Ivalue = sign_extend (Ivalue2, 14); + *aoffsetp += 16; + break; + case 0xc0: + Ivalue = bit_extract (buffer, *aoffsetp, 32); + flip_bytes ((char *) & Ivalue, 4); + Ivalue = sign_extend (Ivalue, 30); + *aoffsetp += 32; + break; + } + return Ivalue; +} + + +#if 1 /* a version that should work on ns32k f's&d's on any machine */ +static int +invalid_float (p, len) + register char *p; + register int len; +{ + register int val; + + if ( len == 4 ) + val = (bit_extract_simple(p, 23, 8)/*exponent*/ == 0xff + || (bit_extract_simple(p, 23, 8)/*exponent*/ == 0 && + bit_extract_simple(p, 0, 23)/*mantisa*/ != 0)); + else if ( len == 8 ) + val = (bit_extract_simple(p, 52, 11)/*exponent*/ == 0x7ff + || (bit_extract_simple(p, 52, 11)/*exponent*/ == 0 + && (bit_extract_simple(p, 0, 32)/*low mantisa*/ != 0 + || bit_extract_simple(p, 32, 20)/*high mantisa*/ != 0))); + else + val = 1; + return (val); +} +#else + +/* assumes the bytes have been swapped to local order */ +typedef union { double d; + float f; + struct { unsigned m:23, e:8, :1;} sf; + struct { unsigned lm; unsigned m:20, e:11, :1;} sd; + } float_type_u; + +static int +invalid_float (p, len) + register float_type_u *p; + register int len; +{ + register int val; + if ( len == sizeof (float) ) + val = (p->sf.e == 0xff + || (p->sf.e == 0 && p->sf.m != 0)); + else if ( len == sizeof (double) ) + val = (p->sd.e == 0x7ff + || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0))); + else + val = 1; + return (val); +} +#endif diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c new file mode 100644 index 0000000..d47659b --- /dev/null +++ b/opcodes/openrisc-asm.c @@ -0,0 +1,672 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +static const char * parse_hi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_lo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); + +long +openrisc_sign_extend_16bit (value) + long value; +{ + return (long) (short) value; +} + +/* Handle hi(). */ + +static const char * +parse_hi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "hi(", 3) == 0) + { + *strp += 3; + +#if 0 + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + if (errmsg != NULL) + fprintf (stderr, "parse_hi: %s\n", errmsg); + if (errmsg != NULL) +#endif + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = (long) (short) value; + + return errmsg; + } + else + { + if (**strp == '-') + errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value); + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) &value); + } + *valuep = (long) (short) (value & 0xffff); + return errmsg; +} + +/* Handle lo(). */ + +static const char * +parse_lo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "lo(", 3) == 0) + { + *strp += 3; + +#if 0 + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + if (errmsg != NULL) + fprintf (stderr, "parse_lo: %s\n", errmsg); + + if (errmsg != NULL) +#endif + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = (long) (short) value; + + return errmsg; + } + + if (**strp == '-') + errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value); + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) &value); + *valuep = (long) (short) (value & 0xffff); + return errmsg; +} + +/* -- */ + +const char * openrisc_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +openrisc_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_ABS_26, 0, NULL, & value); + fields->f_abs26 = value; + } + break; + case OPENRISC_OPERAND_DISP_26 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_DISP_26, 0, NULL, & value); + fields->f_disp26 = value; + } + break; + case OPENRISC_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, OPENRISC_OPERAND_HI16, &fields->f_simm16); + break; + case OPENRISC_OPERAND_LO16 : + errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_LO16, &fields->f_lo16); + break; + case OPENRISC_OPERAND_OP_F_23 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_23, &fields->f_op4); + break; + case OPENRISC_OPERAND_OP_F_3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_3, &fields->f_op5); + break; + case OPENRISC_OPERAND_RA : + errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r2); + break; + case OPENRISC_OPERAND_RB : + errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r3); + break; + case OPENRISC_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r1); + break; + case OPENRISC_OPERAND_SIMM_16 : + errmsg = cgen_parse_signed_integer (cd, strp, OPENRISC_OPERAND_SIMM_16, &fields->f_simm16); + break; + case OPENRISC_OPERAND_UI16NC : + errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_UI16NC, &fields->f_i16nc); + break; + case OPENRISC_OPERAND_UIMM_16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_16, &fields->f_uimm16); + break; + case OPENRISC_OPERAND_UIMM_5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_5, &fields->f_uimm5); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const openrisc_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +openrisc_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + openrisc_cgen_init_opcode_table (cd); + openrisc_cgen_init_ibld_table (cd); + cd->parse_handlers = & openrisc_cgen_parse_handlers[0]; + cd->parse_operand = openrisc_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by openrisc_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +openrisc_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! openrisc_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +openrisc_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! openrisc_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c new file mode 100644 index 0000000..f66514c --- /dev/null +++ b/opcodes/openrisc-desc.c @@ -0,0 +1,1059 @@ +/* CPU data for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "openrisc", MACH_OPENRISC }, + { "or1300", MACH_OR1300 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "or32", ISA_OR32 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] = +{ + { "DATA_CACHE", HAS_CACHE_DATA_CACHE }, + { "INSN_CACHE", HAS_CACHE_INSN_CACHE }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA openrisc_cgen_isa_table[] = { + { "or32", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH openrisc_cgen_mach_table[] = { + { "openrisc", "openrisc", MACH_OPENRISC, 0 }, + { "or1300", "openrisc:1300", MACH_OR1300, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 }, + { "r16", 16, {0, {0}}, 0, 0 }, + { "r17", 17, {0, {0}}, 0, 0 }, + { "r18", 18, {0, {0}}, 0, 0 }, + { "r19", 19, {0, {0}}, 0, 0 }, + { "r20", 20, {0, {0}}, 0, 0 }, + { "r21", 21, {0, {0}}, 0, 0 }, + { "r22", 22, {0, {0}}, 0, 0 }, + { "r23", 23, {0, {0}}, 0, 0 }, + { "r24", 24, {0, {0}}, 0, 0 }, + { "r25", 25, {0, {0}}, 0, 0 }, + { "r26", 26, {0, {0}}, 0, 0 }, + { "r27", 27, {0, {0}}, 0, 0 }, + { "r28", 28, {0, {0}}, 0, 0 }, + { "r29", 29, {0, {0}}, 0, 0 }, + { "r30", 30, {0, {0}}, 0, 0 }, + { "r31", 31, {0, {0}}, 0, 0 }, + { "lr", 11, {0, {0}}, 0, 0 }, + { "sp", 1, {0, {0}}, 0, 0 }, + { "fp", 2, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD openrisc_cgen_opval_h_gr = +{ + & openrisc_cgen_opval_h_gr_entries[0], + 35, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY openrisc_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & openrisc_cgen_ifld_table[0]; +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of openrisc_cgen_cpu_open to rebuild the tables. */ + +static void +openrisc_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & openrisc_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & openrisc_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = openrisc_cgen_rebuild_tables; + openrisc_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +openrisc_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +openrisc_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h new file mode 100644 index 0000000..a85930e --- /dev/null +++ b/opcodes/openrisc-desc.h @@ -0,0 +1,250 @@ +/* CPU data header for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef OPENRISC_CPU_H +#define OPENRISC_CPU_H + +#define CGEN_ARCH openrisc + +/* Given symbol S, return openrisc_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) openrisc##_cgen_##s +#else +#define CGEN_SYM(s) openrisc/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_OPENRISCBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 + +/* Enums. */ + +/* Enum declaration for exception vectors. */ +typedef enum e_exception { + E_RESET, E_BUSERR, E_DPF, E_IPF + , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT + , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL + , E_BREAK, E_RESERVED +} E_EXCEPTION; + +/* Enum declaration for FIXME. */ +typedef enum insn_class { + OP1_0, OP1_1, OP1_2, OP1_3 +} INSN_CLASS; + +/* Enum declaration for FIXME. */ +typedef enum insn_sub { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_10, OP2_11 + , OP2_12, OP2_13, OP2_14, OP2_15 +} INSN_SUB; + +/* Enum declaration for FIXME. */ +typedef enum insn_op3 { + OP3_0, OP3_1, OP3_2, OP3_3 +} INSN_OP3; + +/* Enum declaration for FIXME. */ +typedef enum insn_op4 { + OP4_0, OP4_1, OP4_2, OP4_3 + , OP4_4, OP4_5, OP4_6, OP4_7 +} INSN_OP4; + +/* Enum declaration for FIXME. */ +typedef enum insn_op5 { + OP5_0, OP5_1, OP5_2, OP5_3 + , OP5_4, OP5_5, OP5_6, OP5_7 + , OP5_8, OP5_9, OP5_10, OP5_11 + , OP5_12, OP5_13, OP5_14, OP5_15 + , OP5_16, OP5_17, OP5_18, OP5_19 + , OP5_20, OP5_21, OP5_22, OP5_23 + , OP5_24, OP5_25, OP5_26, OP5_27 + , OP5_28, OP5_29, OP5_30, OP5_31 +} INSN_OP5; + +/* Enum declaration for FIXME. */ +typedef enum insn_op6 { + OP6_0, OP6_1, OP6_2, OP6_3 + , OP6_4, OP6_5, OP6_6, OP6_7 +} INSN_OP6; + +/* Enum declaration for FIXME. */ +typedef enum insn_op7 { + OP7_0, OP7_1, OP7_2, OP7_3 + , OP7_4, OP7_5, OP7_6, OP7_7 + , OP7_8, OP7_9, OP7_10, OP7_11 + , OP7_12, OP7_13, OP7_14, OP7_15 +} INSN_OP7; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_OR32, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for if this model has caches. */ +typedef enum has_cache_attr { + HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE +} HAS_CACHE_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld openrisc_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for openrisc ifield types. */ +typedef enum ifield_type { + OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB + , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16 + , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16 + , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4 + , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1 + , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC + , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3 + , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) OPENRISC_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for openrisc hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR + , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN + , HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for openrisc operand types. */ +typedef enum cgen_operand_type { + OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 + , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5 + , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23 + , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC + , OPENRISC_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 16 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD openrisc_cgen_opval_h_gr; + + + + +#endif /* OPENRISC_CPU_H */ diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c new file mode 100644 index 0000000..e6a7d6a --- /dev/null +++ b/opcodes/openrisc-dis.c @@ -0,0 +1,565 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + + +void openrisc_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + print_address (cd, info, fields->f_abs26, 0|(1<f_disp26, 0|(1<f_simm16, 0|(1<f_lo16, 0|(1<f_op4, 0, pc, length); + break; + case OPENRISC_OPERAND_OP_F_3 : + print_normal (cd, info, fields->f_op5, 0, pc, length); + break; + case OPENRISC_OPERAND_RA : + print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0); + break; + case OPENRISC_OPERAND_RB : + print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0); + break; + case OPENRISC_OPERAND_RD : + print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0); + break; + case OPENRISC_OPERAND_SIMM_16 : + print_normal (cd, info, fields->f_simm16, 0|(1<f_i16nc, 0|(1<f_uimm16, 0, pc, length); + break; + case OPENRISC_OPERAND_UIMM_5 : + print_normal (cd, info, fields->f_uimm5, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const openrisc_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +openrisc_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + openrisc_cgen_init_opcode_table (cd); + openrisc_cgen_init_ibld_table (cd); + cd->print_handlers = & openrisc_cgen_print_handlers[0]; + cd->print_operand = openrisc_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! openrisc_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_openrisc (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_openrisc +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + openrisc_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/openrisc-ibld.c b/opcodes/openrisc-ibld.c new file mode 100644 index 0000000..c2e5156 --- /dev/null +++ b/opcodes/openrisc-ibld.c @@ -0,0 +1,1023 @@ +/* Instruction building/extraction support for openrisc. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * openrisc_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + { + long value = fields->f_abs26; + value = ((unsigned int) (pc) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp26; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_simm16, 0|(1<f_lo16, 0|(1<f_op4, 0, 0, 23, 3, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_OP_F_3 : + errmsg = insert_normal (cd, fields->f_op5, 0, 0, 25, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_RA : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_RB : + errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_RD : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_SIMM_16 : + errmsg = insert_normal (cd, fields->f_simm16, 0|(1<> (11))) & (31)); + FLD (f_i16_1) = ((FLD (f_i16nc)) & (2047)); +} + errmsg = insert_normal (cd, fields->f_i16_1, 0, 0, 10, 11, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_i16_2, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case OPENRISC_OPERAND_UIMM_16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_UIMM_5 : + errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 4, 5, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int openrisc_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_abs26 = value; + } + break; + case OPENRISC_OPERAND_DISP_26 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp26 = value; + } + break; + case OPENRISC_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case OPENRISC_OPERAND_LO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lo16); + break; + case OPENRISC_OPERAND_OP_F_23 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_op4); + break; + case OPENRISC_OPERAND_OP_F_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_op5); + break; + case OPENRISC_OPERAND_RA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); + break; + case OPENRISC_OPERAND_RB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); + break; + case OPENRISC_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); + break; + case OPENRISC_OPERAND_SIMM_16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case OPENRISC_OPERAND_UI16NC : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_i16_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); + if (length <= 0) break; +{ + FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); +} + } + break; + case OPENRISC_OPERAND_UIMM_16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); + break; + case OPENRISC_OPERAND_UIMM_5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_uimm5); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const openrisc_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const openrisc_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int openrisc_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma openrisc_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +openrisc_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + value = fields->f_abs26; + break; + case OPENRISC_OPERAND_DISP_26 : + value = fields->f_disp26; + break; + case OPENRISC_OPERAND_HI16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_LO16 : + value = fields->f_lo16; + break; + case OPENRISC_OPERAND_OP_F_23 : + value = fields->f_op4; + break; + case OPENRISC_OPERAND_OP_F_3 : + value = fields->f_op5; + break; + case OPENRISC_OPERAND_RA : + value = fields->f_r2; + break; + case OPENRISC_OPERAND_RB : + value = fields->f_r3; + break; + case OPENRISC_OPERAND_RD : + value = fields->f_r1; + break; + case OPENRISC_OPERAND_SIMM_16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_UI16NC : + value = fields->f_i16nc; + break; + case OPENRISC_OPERAND_UIMM_16 : + value = fields->f_uimm16; + break; + case OPENRISC_OPERAND_UIMM_5 : + value = fields->f_uimm5; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +openrisc_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + value = fields->f_abs26; + break; + case OPENRISC_OPERAND_DISP_26 : + value = fields->f_disp26; + break; + case OPENRISC_OPERAND_HI16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_LO16 : + value = fields->f_lo16; + break; + case OPENRISC_OPERAND_OP_F_23 : + value = fields->f_op4; + break; + case OPENRISC_OPERAND_OP_F_3 : + value = fields->f_op5; + break; + case OPENRISC_OPERAND_RA : + value = fields->f_r2; + break; + case OPENRISC_OPERAND_RB : + value = fields->f_r3; + break; + case OPENRISC_OPERAND_RD : + value = fields->f_r1; + break; + case OPENRISC_OPERAND_SIMM_16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_UI16NC : + value = fields->f_i16nc; + break; + case OPENRISC_OPERAND_UIMM_16 : + value = fields->f_uimm16; + break; + case OPENRISC_OPERAND_UIMM_5 : + value = fields->f_uimm5; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void openrisc_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void openrisc_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +openrisc_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + fields->f_abs26 = value; + break; + case OPENRISC_OPERAND_DISP_26 : + fields->f_disp26 = value; + break; + case OPENRISC_OPERAND_HI16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_LO16 : + fields->f_lo16 = value; + break; + case OPENRISC_OPERAND_OP_F_23 : + fields->f_op4 = value; + break; + case OPENRISC_OPERAND_OP_F_3 : + fields->f_op5 = value; + break; + case OPENRISC_OPERAND_RA : + fields->f_r2 = value; + break; + case OPENRISC_OPERAND_RB : + fields->f_r3 = value; + break; + case OPENRISC_OPERAND_RD : + fields->f_r1 = value; + break; + case OPENRISC_OPERAND_SIMM_16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_UI16NC : + fields->f_i16nc = value; + break; + case OPENRISC_OPERAND_UIMM_16 : + fields->f_uimm16 = value; + break; + case OPENRISC_OPERAND_UIMM_5 : + fields->f_uimm5 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +openrisc_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + fields->f_abs26 = value; + break; + case OPENRISC_OPERAND_DISP_26 : + fields->f_disp26 = value; + break; + case OPENRISC_OPERAND_HI16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_LO16 : + fields->f_lo16 = value; + break; + case OPENRISC_OPERAND_OP_F_23 : + fields->f_op4 = value; + break; + case OPENRISC_OPERAND_OP_F_3 : + fields->f_op5 = value; + break; + case OPENRISC_OPERAND_RA : + fields->f_r2 = value; + break; + case OPENRISC_OPERAND_RB : + fields->f_r3 = value; + break; + case OPENRISC_OPERAND_RD : + fields->f_r1 = value; + break; + case OPENRISC_OPERAND_SIMM_16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_UI16NC : + fields->f_i16nc = value; + break; + case OPENRISC_OPERAND_UIMM_16 : + fields->f_uimm16 = value; + break; + case OPENRISC_OPERAND_UIMM_5 : + fields->f_uimm5 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +openrisc_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & openrisc_cgen_insert_handlers[0]; + cd->extract_handlers = & openrisc_cgen_extract_handlers[0]; + + cd->insert_operand = openrisc_cgen_insert_operand; + cd->extract_operand = openrisc_cgen_extract_operand; + + cd->get_int_operand = openrisc_cgen_get_int_operand; + cd->set_int_operand = openrisc_cgen_set_int_operand; + cd->get_vma_operand = openrisc_cgen_get_vma_operand; + cd->set_vma_operand = openrisc_cgen_set_vma_operand; +} diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c new file mode 100644 index 0000000..687996c --- /dev/null +++ b/opcodes/openrisc-opc.c @@ -0,0 +1,707 @@ +/* Instruction opcode table for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f] +#else +#define F(f) & openrisc_cgen_ifld_table[OPENRISC_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_l_j = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_ABS26) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_jr = { + 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_bal = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_DISP26) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_movhi = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_mfsr = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_mtsr = { + 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_I16_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_lw = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sw = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R3) }, { F (F_I16NC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sll = { + 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_3) }, { F (F_OP6) }, { F (F_F_4_1) }, { F (F_OP7) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_slli = { + 32, 32, 0xfc00ffe0, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_F_15_8) }, { F (F_OP6) }, { F (F_UIMM5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_add = { + 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_7) }, { F (F_OP7) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_addi = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_LO16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sfgts = { + 32, 32, 0xffe007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sfgtsi = { + 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sfgtui = { + 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) OPENRISC_OPERAND_##op +#else +#define OPERAND(op) OPENRISC_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE openrisc_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* l.j ${abs-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS_26), 0 } }, + & ifmt_l_j, { 0x0 } + }, +/* l.jal ${abs-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS_26), 0 } }, + & ifmt_l_j, { 0x4000000 } + }, +/* l.jr $rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), 0 } }, + & ifmt_l_jr, { 0x14000000 } + }, +/* l.jalr $rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), 0 } }, + & ifmt_l_jr, { 0x14200000 } + }, +/* l.bal ${disp-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP_26), 0 } }, + & ifmt_l_bal, { 0x8000000 } + }, +/* l.bnf ${disp-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP_26), 0 } }, + & ifmt_l_bal, { 0xc000000 } + }, +/* l.bf ${disp-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP_26), 0 } }, + & ifmt_l_bal, { 0x10000000 } + }, +/* l.brk ${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM_16), 0 } }, + & ifmt_l_jr, { 0x17000000 } + }, +/* l.rfe $rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), 0 } }, + & ifmt_l_jr, { 0x14400000 } + }, +/* l.sys ${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM_16), 0 } }, + & ifmt_l_jr, { 0x16000000 } + }, +/* l.nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_l_jr, { 0x15000000 } + }, +/* l.movhi $rD,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (HI16), 0 } }, + & ifmt_l_movhi, { 0x18000000 } + }, +/* l.mfsr $rD,$rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, + & ifmt_l_mfsr, { 0x1c000000 } + }, +/* l.mtsr $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_mtsr, { 0x40000000 } + }, +/* l.lw $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x80000000 } + }, +/* l.lbz $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x84000000 } + }, +/* l.lbs $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x88000000 } + }, +/* l.lhz $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x8c000000 } + }, +/* l.lhs $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x90000000 } + }, +/* l.sw ${ui16nc}($rA),$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, + & ifmt_l_sw, { 0xd4000000 } + }, +/* l.sb ${ui16nc}($rA),$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, + & ifmt_l_sw, { 0xd8000000 } + }, +/* l.sh ${ui16nc}($rA),$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, + & ifmt_l_sw, { 0xdc000000 } + }, +/* l.sll $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000008 } + }, +/* l.slli $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000000 } + }, +/* l.srl $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000028 } + }, +/* l.srli $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000020 } + }, +/* l.sra $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000048 } + }, +/* l.srai $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000040 } + }, +/* l.ror $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000088 } + }, +/* l.rori $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000080 } + }, +/* l.add $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000000 } + }, +/* l.addi $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0x94000000 } + }, +/* l.sub $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000002 } + }, +/* l.subi $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0x9c000000 } + }, +/* l.and $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000003 } + }, +/* l.andi $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xa0000000 } + }, +/* l.or $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000004 } + }, +/* l.ori $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xa4000000 } + }, +/* l.xor $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000005 } + }, +/* l.xori $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xa8000000 } + }, +/* l.mul $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000006 } + }, +/* l.muli $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xac000000 } + }, +/* l.div $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000009 } + }, +/* l.divu $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe000000a } + }, +/* l.sfgts $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4c00000 } + }, +/* l.sfgtu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4400000 } + }, +/* l.sfges $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4e00000 } + }, +/* l.sfgeu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4600000 } + }, +/* l.sflts $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe5000000 } + }, +/* l.sfltu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4800000 } + }, +/* l.sfles $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe5200000 } + }, +/* l.sfleu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4a00000 } + }, +/* l.sfgtsi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8c00000 } + }, +/* l.sfgtui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8400000 } + }, +/* l.sfgesi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8e00000 } + }, +/* l.sfgeui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8600000 } + }, +/* l.sfltsi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb9000000 } + }, +/* l.sfltui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8800000 } + }, +/* l.sflesi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb9200000 } + }, +/* l.sfleui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8a00000 } + }, +/* l.sfeq $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4000000 } + }, +/* l.sfeqi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8000000 } + }, +/* l.sfne $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4200000 } + }, +/* l.sfnei $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8200000 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f] +#else +#define F(f) & openrisc_cgen_ifld_table[OPENRISC_/**/f] +#endif +static const CGEN_IFMT ifmt_l_ret = { + 32, 32, 0xffffffff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) OPENRISC_OPERAND_##op +#else +#define OPERAND(op) OPENRISC_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE openrisc_cgen_macro_insn_table[] = +{ +/* l.ret */ + { + -1, "l-ret", "l.ret", 32, + { 0|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & openrisc_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + openrisc_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/openrisc-opc.h b/opcodes/openrisc-opc.h new file mode 100644 index 0000000..494ba5c --- /dev/null +++ b/opcodes/openrisc-opc.h @@ -0,0 +1,113 @@ +/* Instruction opcode header for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef OPENRISC_OPC_H +#define OPENRISC_OPC_H + +/* -- opc.h */ +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 64 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) + +extern long openrisc_sign_extend_16bit PARAMS ((long)); +/* -- */ +/* Enum declaration for openrisc instruction types. */ +typedef enum cgen_insn_type { + OPENRISC_INSN_INVALID, OPENRISC_INSN_L_J, OPENRISC_INSN_L_JAL, OPENRISC_INSN_L_JR + , OPENRISC_INSN_L_JALR, OPENRISC_INSN_L_BAL, OPENRISC_INSN_L_BNF, OPENRISC_INSN_L_BF + , OPENRISC_INSN_L_BRK, OPENRISC_INSN_L_RFE, OPENRISC_INSN_L_SYS, OPENRISC_INSN_L_NOP + , OPENRISC_INSN_L_MOVHI, OPENRISC_INSN_L_MFSR, OPENRISC_INSN_L_MTSR, OPENRISC_INSN_L_LW + , OPENRISC_INSN_L_LBZ, OPENRISC_INSN_L_LBS, OPENRISC_INSN_L_LHZ, OPENRISC_INSN_L_LHS + , OPENRISC_INSN_L_SW, OPENRISC_INSN_L_SB, OPENRISC_INSN_L_SH, OPENRISC_INSN_L_SLL + , OPENRISC_INSN_L_SLLI, OPENRISC_INSN_L_SRL, OPENRISC_INSN_L_SRLI, OPENRISC_INSN_L_SRA + , OPENRISC_INSN_L_SRAI, OPENRISC_INSN_L_ROR, OPENRISC_INSN_L_RORI, OPENRISC_INSN_L_ADD + , OPENRISC_INSN_L_ADDI, OPENRISC_INSN_L_SUB, OPENRISC_INSN_L_SUBI, OPENRISC_INSN_L_AND + , OPENRISC_INSN_L_ANDI, OPENRISC_INSN_L_OR, OPENRISC_INSN_L_ORI, OPENRISC_INSN_L_XOR + , OPENRISC_INSN_L_XORI, OPENRISC_INSN_L_MUL, OPENRISC_INSN_L_MULI, OPENRISC_INSN_L_DIV + , OPENRISC_INSN_L_DIVU, OPENRISC_INSN_L_SFGTS, OPENRISC_INSN_L_SFGTU, OPENRISC_INSN_L_SFGES + , OPENRISC_INSN_L_SFGEU, OPENRISC_INSN_L_SFLTS, OPENRISC_INSN_L_SFLTU, OPENRISC_INSN_L_SFLES + , OPENRISC_INSN_L_SFLEU, OPENRISC_INSN_L_SFGTSI, OPENRISC_INSN_L_SFGTUI, OPENRISC_INSN_L_SFGESI + , OPENRISC_INSN_L_SFGEUI, OPENRISC_INSN_L_SFLTSI, OPENRISC_INSN_L_SFLTUI, OPENRISC_INSN_L_SFLESI + , OPENRISC_INSN_L_SFLEUI, OPENRISC_INSN_L_SFEQ, OPENRISC_INSN_L_SFEQI, OPENRISC_INSN_L_SFNE + , OPENRISC_INSN_L_SFNEI +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID OPENRISC_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) OPENRISC_INSN_L_SFNEI + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_class; + long f_sub; + long f_r1; + long f_r2; + long f_r3; + long f_simm16; + long f_uimm16; + long f_uimm5; + long f_hi16; + long f_lo16; + long f_op1; + long f_op2; + long f_op3; + long f_op4; + long f_op5; + long f_op6; + long f_op7; + long f_i16_1; + long f_i16_2; + long f_disp26; + long f_abs26; + long f_i16nc; + long f_f_15_8; + long f_f_10_3; + long f_f_4_1; + long f_f_7_3; + long f_f_10_7; + long f_f_10_11; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* OPENRISC_OPC_H */ diff --git a/opcodes/opintl.h b/opcodes/opintl.h new file mode 100644 index 0000000..d19b664 --- /dev/null +++ b/opcodes/opintl.h @@ -0,0 +1,42 @@ +/* opintl.h - opcodes specific header for gettext code. + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + + Written by Tom Tromey + + This file is part of the opcodes library used by GAS and the GNU binutils. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifdef ENABLE_NLS +# include +/* Note the use of dgetext() and PACKAGE here, rather than gettext(). + + This is because the code in this directory is used to build a library which + will be linked with code in other directories to form programs. We want to + maintain a seperate translation file for this directory however, rather + than being forced to merge it with that of any program linked to + libopcodes. This is a library, so it cannot depend on the catalog + currently loaded. + + In order to do this, we have to make sure that when we extract messages we + use the OPCODES domain rather than the domain of the program that included + the opcodes library, (eg OBJDUMP). Hence we use dgettext (PACKAGE, String) + and define PACKAGE to be 'opcodes'. (See the code in configure). */ +# define _(String) dgettext (PACKAGE, String) +# ifdef gettext_noop +# define N_(String) gettext_noop (String) +# else +# define N_(String) (String) +# endif +#else +# define gettext(Msgid) (Msgid) +# define dgettext(Domainname, Msgid) (Msgid) +# define dcgettext(Domainname, Msgid, Category) (Msgid) +# define textdomain(Domainname) while (0) /* nothing */ +# define bindtextdomain(Domainname, Dirname) while (0) /* nothing */ +# define _(String) (String) +# define N_(String) (String) +#endif diff --git a/opcodes/or32-dis.c b/opcodes/or32-dis.c new file mode 100644 index 0000000..8876a30 --- /dev/null +++ b/opcodes/or32-dis.c @@ -0,0 +1,348 @@ +/* Instruction printing code for the OpenRISC 1000 + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Damjan Lampret . + Modified from a29k port. + + This file is part of Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DEBUG 0 + +#include "dis-asm.h" +#include "opcode/or32.h" +#include "safe-ctype.h" +#include +#include + +#define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x))) + +static void find_bytes_big PARAMS ((unsigned char *, unsigned long *)); +static void find_bytes_little PARAMS ((unsigned char *, unsigned long *)); +static unsigned long or32_extract PARAMS ((char, char *, unsigned long)); +static int or32_opcode_match PARAMS ((unsigned long, char *)); +static void or32_print_register PARAMS ((char, char *, unsigned long, struct disassemble_info *)); +static void or32_print_immediate PARAMS ((char, char *, unsigned long, struct disassemble_info *)); +static int print_insn PARAMS ((bfd_vma, struct disassemble_info *)); + +/* Now find the four bytes of INSN_CH and put them in *INSN. */ + +static void +find_bytes_big (insn_ch, insn) + unsigned char *insn_ch; + unsigned long *insn; +{ + *insn = + ((unsigned long) insn_ch[0] << 24) + + ((unsigned long) insn_ch[1] << 16) + + ((unsigned long) insn_ch[2] << 8) + + ((unsigned long) insn_ch[3]); +#if DEBUG + printf ("find_bytes_big3: %x\n", *insn); +#endif +} + +static void +find_bytes_little (insn_ch, insn) + unsigned char *insn_ch; + unsigned long *insn; +{ + *insn = + ((unsigned long) insn_ch[3] << 24) + + ((unsigned long) insn_ch[2] << 16) + + ((unsigned long) insn_ch[1] << 8) + + ((unsigned long) insn_ch[0]); +} + +typedef void (*find_byte_func_type) + PARAMS ((unsigned char *, unsigned long *)); + +static unsigned long +or32_extract (param_ch, enc_initial, insn) + char param_ch; + char *enc_initial; + unsigned long insn; +{ + char *enc; + unsigned long ret = 0; + int opc_pos = 0; + int param_pos = 0; + + for (enc = enc_initial; *enc != '\0'; enc++) + if (*enc == param_ch) + { + if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) + continue; + else + param_pos++; + } + +#if DEBUG + printf ("or32_extract: %c %x ", param_ch, param_pos); +#endif + opc_pos = 32; + + for (enc = enc_initial; *enc != '\0'; ) + if ((*enc == '0') && (*(enc + 1) == 'x')) + { + opc_pos -= 4; + + if ((param_ch == '0') || (param_ch == '1')) + { + unsigned long tmp = strtoul (enc, NULL, 16); +#if DEBUG + printf (" enc=%s, tmp=%x ", enc, tmp); +#endif + if (param_ch == '0') + tmp = 15 - tmp; + ret |= tmp << opc_pos; + } + enc += 3; + } + else if ((*enc == '0') || (*enc == '1')) + { + opc_pos--; + if (param_ch == *enc) + ret |= 1 << opc_pos; + enc++; + } + else if (*enc == param_ch) + { + opc_pos--; + param_pos--; +#if DEBUG + printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); +#endif + ret += ((insn >> opc_pos) & 0x1) << param_pos; + + if (!param_pos + && letter_signed (param_ch) + && ret >> (letter_range (param_ch) - 1)) + { +#if DEBUG + printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", + ret, opc_pos, param_pos); +#endif + ret |= 0xffffffff << letter_range(param_ch); +#if DEBUG + printf ("\n after conversion to signed: ret=%x\n", ret); +#endif + } + enc++; + } + else if (ISALPHA (*enc)) + { + opc_pos--; + enc++; + } + else if (*enc == '-') + { + opc_pos--; + enc++; + } + else + enc++; + +#if DEBUG + printf ("ret=%x\n", ret); +#endif + return ret; +} + +static int +or32_opcode_match (insn, encoding) + unsigned long insn; + char *encoding; +{ + unsigned long ones, zeros; + +#if DEBUG + printf ("or32_opcode_match: %.8lx\n", insn); +#endif + ones = or32_extract ('1', encoding, insn); + zeros = or32_extract ('0', encoding, insn); + +#if DEBUG + printf ("ones: %x \n", ones); + printf ("zeros: %x \n", zeros); +#endif + if ((insn & ones) != ones) + { +#if DEBUG + printf ("ret1\n"); +#endif + return 0; + } + + if ((~insn & zeros) != zeros) + { +#if DEBUG + printf ("ret2\n"); +#endif + return 0; + } + +#if DEBUG + printf ("ret3\n"); +#endif + return 1; +} + +/* Print register to INFO->STREAM. Used only by print_insn. */ + +static void +or32_print_register (param_ch, encoding, insn, info) + char param_ch; + char *encoding; + unsigned long insn; + struct disassemble_info *info; +{ + int regnum = or32_extract (param_ch, encoding, insn); + +#if DEBUG + printf ("or32_print_register: %c, %s, %x\n", param_ch, encoding, insn); +#endif + if (param_ch == 'A') + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (param_ch == 'B') + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (param_ch == 'D') + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (regnum < 16) + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (regnum < 32) + (*info->fprintf_func) (info->stream, "r%d", regnum-16); + else + (*info->fprintf_func) (info->stream, "X%d", regnum); +} + +/* Print immediate to INFO->STREAM. Used only by print_insn. */ + +static void +or32_print_immediate (param_ch, encoding, insn, info) + char param_ch; + char *encoding; + unsigned long insn; + struct disassemble_info *info; +{ + int imm = or32_extract(param_ch, encoding, insn); + + if (letter_signed(param_ch)) + (*info->fprintf_func) (info->stream, "0x%x", imm); +/* (*info->fprintf_func) (info->stream, "%d", imm); */ + else + (*info->fprintf_func) (info->stream, "0x%x", imm); +} + +/* Print one instruction from MEMADDR on INFO->STREAM. + Return the size of the instruction (always 4 on or32). */ + +static int +print_insn (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + /* The raw instruction. */ + unsigned char insn_ch[4]; + /* Address. Will be sign extened 27-bit. */ + unsigned long addr; + /* The four bytes of the instruction. */ + unsigned long insn; + find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data; + struct or32_opcode CONST * opcode; + + { + int status = + (*info->read_memory_func) (memaddr, (bfd_byte *) &insn_ch[0], 4, info); + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + (*find_byte_func) (&insn_ch[0], &insn); + + for (opcode = &or32_opcodes[0]; + opcode < &or32_opcodes[or32_num_opcodes]; + ++opcode) + { + if (or32_opcode_match (insn, opcode->encoding)) + { + char *s; + + (*info->fprintf_func) (info->stream, "%s ", opcode->name); + + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case '\0': + return 4; + + case 'r': + or32_print_register (*++s, opcode->encoding, insn, info); + break; + + case 'X': + addr = or32_extract ('X', opcode->encoding, insn) << 2; + + /* Calulate the correct address. XXX is this really correct ?? */ + addr = memaddr + EXTEND29 (addr); + + (*info->print_address_func) + (addr, info); + break; + + default: + if (strchr (opcode->encoding, *s)) + or32_print_immediate (*s, opcode->encoding, insn, info); + else + (*info->fprintf_func) (info->stream, "%c", *s); + } + } + + return 4; + } + } + + /* This used to be %8x for binutils. */ + (*info->fprintf_func) + (info->stream, ".word 0x%08x", insn); + return 4; +} + +/* Disassemble a big-endian or32 instruction. */ + +int +print_insn_big_or32 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + info->private_data = (PTR) find_bytes_big; + return print_insn (memaddr, info); +} + +/* Disassemble a little-endian or32 instruction. */ + +int +print_insn_little_or32 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + info->private_data = (PTR) find_bytes_little; + return print_insn (memaddr, info); +} diff --git a/opcodes/or32-opc.c b/opcodes/or32-opc.c new file mode 100644 index 0000000..8ccdfb1 --- /dev/null +++ b/opcodes/or32-opc.c @@ -0,0 +1,1052 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of gen_or1k_isa, or1k, GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ +#include +#include +#include +#include "safe-ctype.h" +#include "ansidecl.h" +#ifdef HAVE_CONFIG_H +# include "config.h" +#endif +#include "opcode/or32.h" + +static unsigned long insn_extract PARAMS ((char, char *)); +static unsigned long * cover_insn PARAMS ((unsigned long *, int, unsigned int)); +static int num_ones PARAMS ((unsigned long)); +static struct insn_op_struct * parse_params PARAMS ((const struct or32_opcode *, struct insn_op_struct *)); +static unsigned long or32_extract PARAMS ((char, char *, unsigned long)); +static void or32_print_register PARAMS ((char, char *, unsigned long)); +static void or32_print_immediate PARAMS ((char, char *, unsigned long)); +static unsigned long extend_imm PARAMS ((unsigned long, char)); + +const struct or32_letter or32_letters[] = + { + { 'A', NUM_UNSIGNED }, + { 'B', NUM_UNSIGNED }, + { 'D', NUM_UNSIGNED }, + { 'I', NUM_SIGNED }, + { 'K', NUM_UNSIGNED }, + { 'L', NUM_UNSIGNED }, + { 'N', NUM_SIGNED }, + { '0', NUM_UNSIGNED }, + { '\0', 0 } /* Dummy entry. */ + }; + +/* Opcode encoding: + machine[31:30]: first two bits of opcode + 00 - neither of source operands is GPR + 01 - second source operand is GPR (rB) + 10 - first source operand is GPR (rA) + 11 - both source operands are GPRs (rA and rB) + machine[29:26]: next four bits of opcode + machine[25:00]: instruction operands (specific to individual instruction) + + Recommendation: irrelevant instruction bits should be set with a value of + bits in same positions of instruction preceding current instruction in the + code (when assembling). */ + +#define EFN &l_none + +#ifdef HAS_EXECUTION +#define EF(func) &(func) +#define EFI &l_invalid +#else /* HAS_EXECUTION */ +#define EF(func) EFN +#define EFI EFN +#endif /* HAS_EXECUTION */ + +const struct or32_opcode or32_opcodes[] = + { + { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY }, + { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY }, + { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG}, + { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG }, + { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 }, + { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/ + { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/ + + { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 }, + { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */ + { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY }, + + { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 }, + { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 }, + { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 }, + { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 }, + { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 }, + { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 }, + { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 }, + { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 }, + { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 }, + { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 }, + { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 }, + { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 }, + { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 }, + { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 }, + { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 }, + { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 }, + { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 }, + { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 }, + { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 }, + { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 }, + { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 }, + { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 }, + { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 }, + { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 }, + { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 }, + { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 }, + { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 }, + { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 }, + { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 }, + { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 }, + { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 }, + { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 }, + { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 }, + { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 }, + { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 }, + { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 }, + { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 }, + { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 }, + { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 }, + { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 }, + { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 }, + { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 }, + { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 }, + { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 }, + { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 }, + { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 }, + { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 }, + { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 }, + { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 }, + { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 }, + { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 }, + { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 }, + { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 }, + { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 }, + { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 }, + { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 }, + { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 }, + { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 }, + { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 }, + { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 }, + { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 }, + { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 }, + { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 }, + { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 }, + { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 }, + { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 }, + { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 }, + { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 }, + { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 }, + { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 }, + { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 }, + { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 }, + { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 }, + { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 }, + { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 }, + { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 }, + { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 }, + { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 }, + { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 }, + + { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, + { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, + { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 }, + + { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, + { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, + { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 }, + + { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 }, + { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 }, + { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + + { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY }, + { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY }, + { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 }, + { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 }, + { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 }, + { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 }, + { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 }, + + { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 }, + { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 }, + { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 }, + { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 }, + { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 }, + + { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 }, + { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 }, + { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 }, + { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 }, + { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 }, + { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 }, + { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 }, + { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 }, + { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 }, + + { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG }, + { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG }, + { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG }, + { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG }, + { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG }, + { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG }, + { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG }, + { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG }, + { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG }, + { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG }, + + { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 }, + { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/ + { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/ + + { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 }, + { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 }, + { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 }, + { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 }, + + { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 }, + { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 }, + { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 }, + { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 }, + { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 }, + { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 }, + { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 }, + + { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 }, + { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 }, + { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 }, + { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 }, + { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 }, + { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 }, + { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 }, + { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 }, + { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 }, + { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 }, + { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 }, + { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 }, + { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 }, + { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 }, + { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 }, + + { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG }, + { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG }, + { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG }, + { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG }, + { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG }, + { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG }, + { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG }, + { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG }, + { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG }, + { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG }, + + { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 }, + + /* This section should not be defined in or1ksim, since it contains duplicates, + which would cause machine builder to complain. */ +#ifdef HAS_CUST + { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, +#endif + + /* Dummy entry, not included in num_opcodes. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", "", "", EFI, 0 } +}; + +#undef EFI +#undef EFN +#undef EF + +/* Define dummy, if debug is not defined. */ + +#if !defined HAS_DEBUG +static void debug PARAMS ((int, const char *, ...)); + +static void +debug (int level, const char *format, ...) +{ + /* Just to get rid of warnings. */ + format = (char *) level = 0; +} +#endif + +const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ + +int +insn_len (insn_index) + int insn_index ATTRIBUTE_UNUSED; +{ + return 4; +} + +/* Is individual insn's operand signed or unsigned? */ + +int +letter_signed (l) + char l; +{ + const struct or32_letter *pletter; + + for (pletter = or32_letters; pletter->letter != '\0'; pletter++) + if (pletter->letter == l) + return pletter->sign; + + printf ("letter_signed(%c): Unknown letter.\n", l); + return 0; +} + +/* Number of letters in the individual lettered operand. */ + +int +letter_range (l) + char l; +{ + const struct or32_opcode *pinsn; + char *enc; + int range = 0; + + for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++) + { + if (strchr (pinsn->encoding,l)) + { + for (enc = pinsn->encoding; *enc != '\0'; enc++) + if ((*enc == '0') && (*(enc+1) == 'x')) + enc += 2; + else if (*enc == l) + range++; + return range; + } + } + + printf ("\nABORT: letter_range(%c): Never used letter.\n", l); + exit (1); +} + +/* MM: Returns index of given instruction name. */ + +int +insn_index (char *insn) +{ + unsigned int i; + int found = -1; + + for (i = 0; i < or32_num_opcodes; i++) + if (!strcmp (or32_opcodes[i].name, insn)) + { + found = i; + break; + } + return found; +} + +const char * +insn_name (index) + int index; +{ + if (index >= 0 && index < (int) or32_num_opcodes) + return or32_opcodes[index].name; + else + return "???"; +} + +void +l_none () +{ +} + +/* Finite automata for instruction decoding building code. */ + +/* Find simbols in encoding. */ +static unsigned long +insn_extract (param_ch, enc_initial) + char param_ch; + char *enc_initial; +{ + char *enc; + unsigned long ret = 0; + unsigned opc_pos = 32; + + for (enc = enc_initial; *enc != '\0'; ) + if ((*enc == '0') && (*(enc + 1) == 'x')) + { + unsigned long tmp = strtol (enc+2, NULL, 16); + + opc_pos -= 4; + if (param_ch == '0' || param_ch == '1') + { + if (param_ch == '0') + tmp = 15 - tmp; + ret |= tmp << opc_pos; + } + enc += 3; + } + else + { + if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc)) + { + opc_pos--; + if (param_ch == *enc) + ret |= 1 << opc_pos; + } + enc++; + } + return ret; +} + +#define MAX_AUTOMATA_SIZE (1200) +#define MAX_OP_TABLE_SIZE (1200) +#define LEAF_FLAG (0x80000000) +#define MAX_LEN (8) + +#ifndef MIN +# define MIN(x,y) ((x) < (y) ? (x) : (y)) +#endif + +unsigned long *automata; +int nuncovered; +int curpass = 0; + +/* MM: Struct that hold runtime build information about instructions. */ +struct temp_insn_struct +{ + unsigned long insn; + unsigned long insn_mask; + int in_pass; +} *ti; + +struct insn_op_struct *op_data, **op_start; + +/* Recursive utility function used to find best match and to build automata. */ + +static unsigned long * +cover_insn (cur, pass, mask) + unsigned long * cur; + int pass; + unsigned int mask; +{ + int best_first = 0, last_match = -1, ninstr = 0; + unsigned int best_len = 0; + unsigned int i; + unsigned long cur_mask = mask; + unsigned long *next; + + for (i = 0; i < or32_num_opcodes; i++) + if (ti[i].in_pass == pass) + { + cur_mask &= ti[i].insn_mask; + ninstr++; + last_match = i; + } + + debug (8, "%08X %08X\n", mask, cur_mask); + + if (ninstr == 0) + return 0; + + if (ninstr == 1) + { + /* Leaf holds instruction index. */ + debug (8, "%i>I%i %s\n", + cur - automata, last_match, or32_opcodes[last_match].name); + + *cur = LEAF_FLAG | last_match; + cur++; + nuncovered--; + } + else + { + /* Find longest match. */ + for (i = 0; i < 32; i++) + { + unsigned int len; + + for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++) + { + unsigned long m = (1UL << ((unsigned long)len)) - 1; + + debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)", + len,m, cur_mask, i, (cur_mask >> (unsigned)i), + (cur_mask >> (unsigned)i) & m); + + if ((m & (cur_mask >> (unsigned)i)) == m) + { + best_len = len; + best_first = i; + debug (9, "!"); + } + else + break; + } + } + + debug (9, "\n"); + + if (!best_len) + { + fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask); + + for (i = 0; i < or32_num_opcodes; i++) + if (ti[i].in_pass == pass) + fprintf (stderr, "%s ", or32_opcodes[i].name); + + fprintf (stderr, "\n"); + exit (1); + } + + debug (8, "%i> #### %i << %i (%i) ####\n", + cur - automata, best_len, best_first, ninstr); + + *cur = best_first; + cur++; + *cur = (1 << best_len) - 1; + cur++; + next = cur; + + /* Allocate space for pointers. */ + cur += 1 << best_len; + cur_mask = (1 << (unsigned long)best_len) - 1; + + for (i = 0; i < ((unsigned) 1 << best_len); i++) + { + unsigned int j; + unsigned long *c; + + curpass++; + for (j = 0; j < or32_num_opcodes; j++) + if (ti[j].in_pass == pass + && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i + && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask) + ti[j].in_pass = curpass; + + debug (9, "%08X %08X %i\n", mask, cur_mask, best_first); + c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first))); + if (c) + { + debug (8, "%i> #%X -> %u\n", next - automata, i, cur - automata); + *next = cur - automata; + cur = c; + } + else + { + debug (8, "%i> N/A\n", next - automata); + *next = 0; + } + next++; + } + } + return cur; +} + +/* Returns number of nonzero bits. */ + +static int +num_ones (value) + unsigned long value; +{ + int c = 0; + + while (value) + { + if (value & 1) + c++; + value >>= 1; + } + return c; +} + +/* Utility function, which converts parameters from or32_opcode format to more binary form. + Parameters are stored in ti struct. */ + +static struct insn_op_struct * +parse_params (opcode, cur) + const struct or32_opcode * opcode; + struct insn_op_struct * cur; +{ + char *args = opcode->args; + int i, type; + + i = 0; + type = 0; + /* In case we don't have any parameters, we add dummy read from r0. */ + + if (!(*args)) + { + cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST; + cur->data = 0; + debug (9, "#%08X %08X\n", cur->type, cur->data); + cur++; + return cur; + } + + while (*args != '\0') + { + if (*args == 'r') + { + args++; + type |= OPTYPE_REG; + } + else if (ISALPHA (*args)) + { + unsigned long arg; + + arg = insn_extract (*args, opcode->encoding); + debug (9, "%s : %08X ------\n", opcode->name, arg); + if (letter_signed (*args)) + { + type |= OPTYPE_SIG; + type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT; + } + + /* Split argument to sequences of consecutive ones. */ + while (arg) + { + int shr = 0; + unsigned long tmp = arg, mask = 0; + + while ((tmp & 1) == 0) + { + shr++; + tmp >>= 1; + } + while (tmp & 1) + { + mask++; + tmp >>= 1; + } + cur->type = type | shr; + cur->data = mask; + arg &= ~(((1 << mask) - 1) << shr); + debug (6, "|%08X %08X\n", cur->type, cur->data); + cur++; + } + args++; + } + else if (*args == '(') + { + /* Next param is displacement. Later we will treat them as one operand. */ + cur--; + cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP; + debug (9, ">%08X %08X\n", cur->type, cur->data); + cur++; + type = 0; + i++; + args++; + } + else if (*args == OPERAND_DELIM) + { + cur--; + cur->type = type | cur->type | OPTYPE_OP; + debug (9, ">%08X %08X\n", cur->type, cur->data); + cur++; + type = 0; + i++; + args++; + } + else if (*args == '0') + { + cur->type = type; + cur->data = 0; + debug (9, ">%08X %08X\n", cur->type, cur->data); + cur++; + type = 0; + i++; + args++; + } + else if (*args == ')') + args++; + else + { + fprintf (stderr, "%s : parse error in args.\n", opcode->name); + exit (1); + } + } + + cur--; + cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST; + debug (9, "#%08X %08X\n", cur->type, cur->data); + cur++; + + return cur; +} + +/* Constructs new automata based on or32_opcodes array. */ + +void +build_automata () +{ + unsigned int i; + unsigned long *end; + struct insn_op_struct *cur; + + automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long)); + ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes); + + nuncovered = or32_num_opcodes; + printf ("Building automata... "); + /* Build temporary information about instructions. */ + for (i = 0; i < or32_num_opcodes; i++) + { + unsigned long ones, zeros; + char *encoding = or32_opcodes[i].encoding; + + ones = insn_extract('1', encoding); + zeros = insn_extract('0', encoding); + + ti[i].insn_mask = ones | zeros; + ti[i].insn = ones; + ti[i].in_pass = curpass = 0; + + /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name, + or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/ + } + + /* Until all are covered search for best criteria to separate them. */ + end = cover_insn (automata, curpass, 0xFFFFFFFF); + + if (end - automata > MAX_AUTOMATA_SIZE) + { + fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE."); + exit (1); + } + + printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes); + printf ("Parsing operands data... "); + + op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct)); + op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *)); + cur = op_data; + + for (i = 0; i < or32_num_opcodes; i++) + { + op_start[i] = cur; + cur = parse_params (&or32_opcodes[i], cur); + + if (cur - op_data > MAX_OP_TABLE_SIZE) + { + fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n"); + exit (1); + } + } + printf ("done.\n"); +} + +void +destruct_automata () +{ + free (ti); + free (automata); + free (op_data); + free (op_start); +} + +/* Decodes instruction and returns instruction index. */ + +int +insn_decode (insn) + unsigned int insn; +{ + unsigned long *a = automata; + int i; + + while (!(*a & LEAF_FLAG)) + { + unsigned int first = *a; + + debug (9, "%i ", a - automata); + + a++; + i = (insn >> first) & *a; + a++; + if (!*(a + i)) + { + /* Invalid instruction found? */ + debug (9, "XXX\n", i); + return -1; + } + a = automata + *(a + i); + } + + i = *a & ~LEAF_FLAG; + + debug (9, "%i\n", i); + + /* Final check - do we have direct match? + (based on or32_opcodes this should be the only possibility, + but in case of invalid/missing instruction we must perform a check) */ + if ((ti[i].insn_mask & insn) == ti[i].insn) + return i; + else + return -1; +} + +static char disassembled_str[50]; +char *disassembled = &disassembled_str[0]; + +/* Automagically does zero- or sign- extension and also finds correct + sign bit position if sign extension is correct extension. Which extension + is proper is figured out from letter description. */ + +static unsigned long +extend_imm (imm, l) + unsigned long imm; + char l; +{ + unsigned long mask; + int letter_bits; + + /* First truncate all bits above valid range for this letter + in case it is zero extend. */ + letter_bits = letter_range (l); + mask = (1 << letter_bits) - 1; + imm &= mask; + + /* Do sign extend if this is the right one. */ + if (letter_signed(l) && (imm >> (letter_bits - 1))) + imm |= (~mask); + + return imm; +} + +static unsigned long +or32_extract (param_ch, enc_initial, insn) + char param_ch; + char *enc_initial; + unsigned long insn; +{ + char *enc; + unsigned long ret = 0; + int opc_pos = 0; + int param_pos = 0; + + for (enc = enc_initial; *enc != '\0'; enc++) + if (*enc == param_ch) + { + if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) + continue; + else + param_pos++; + } + +#if DEBUG + printf ("or32_extract: %x ", param_pos); +#endif + opc_pos = 32; + + for (enc = enc_initial; *enc != '\0'; ) + if ((*enc == '0') && (*(enc + 1) == 'x')) + { + opc_pos -= 4; + if ((param_ch == '0') || (param_ch == '1')) + { + unsigned long tmp = strtol (enc, NULL, 16); +#if DEBUG + printf (" enc=%s, tmp=%x ", enc, tmp); +#endif + if (param_ch == '0') + tmp = 15 - tmp; + ret |= tmp << opc_pos; + } + enc += 3; + } + else if ((*enc == '0') || (*enc == '1')) + { + opc_pos--; + if (param_ch == *enc) + ret |= 1 << opc_pos; + enc++; + } + else if (*enc == param_ch) + { + opc_pos--; + param_pos--; +#if DEBUG + printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); +#endif + if (ISLOWER (param_ch)) + ret -= ((insn >> opc_pos) & 0x1) << param_pos; + else + ret += ((insn >> opc_pos) & 0x1) << param_pos; + enc++; + } + else if (ISALPHA (*enc)) + { + opc_pos--; + enc++; + } + else if (*enc == '-') + { + opc_pos--; + enc++; + } + else + enc++; + +#if DEBUG + printf ("ret=%x\n", ret); +#endif + return ret; +} + +/* Print register. Used only by print_insn. */ + +static void +or32_print_register (param_ch, encoding, insn) + char param_ch; + char *encoding; + unsigned long insn; +{ + int regnum = or32_extract(param_ch, encoding, insn); + + sprintf (disassembled, "%sr%d", disassembled, regnum); +} + +/* Print immediate. Used only by print_insn. */ + +static void +or32_print_immediate (param_ch, encoding, insn) + char param_ch; + char *encoding; + unsigned long insn; +{ + int imm = or32_extract (param_ch, encoding, insn); + + imm = extend_imm (imm, param_ch); + + if (letter_signed (param_ch)) + { + if (imm < 0) + sprintf (disassembled, "%s%d", disassembled, imm); + else + sprintf (disassembled, "%s0x%x", disassembled, imm); + } + else + sprintf (disassembled, "%s%#x", disassembled, imm); +} + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ + +int +disassemble_insn (insn) + unsigned long insn; +{ + int index; + index = insn_decode (insn); + + if (index >= 0) + { + struct or32_opcode const *opcode = &or32_opcodes[index]; + char *s; + + sprintf (disassembled, "%s ", opcode->name); + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case '\0': + return 4; + + case 'r': + or32_print_register (*++s, opcode->encoding, insn); + break; + + default: + if (strchr (opcode->encoding, *s)) + or32_print_immediate (*s, opcode->encoding, insn); + else + sprintf (disassembled, "%s%c", disassembled, *s); + } + } + } + else + { + /* This used to be %8x for binutils. */ + sprintf (disassembled, "%s.word 0x%08lx", disassembled, insn); + } + + return insn_len (insn); +} diff --git a/opcodes/pdp11-dis.c b/opcodes/pdp11-dis.c new file mode 100644 index 0000000..507db93 --- /dev/null +++ b/opcodes/pdp11-dis.c @@ -0,0 +1,394 @@ +/* Print DEC PDP-11 instructions. + Copyright 2001, 2002 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/pdp11.h" + +#define AFTER_INSTRUCTION "\t" +#define OPERAND_SEPARATOR ", " + +#define JUMP 0x1000 /* flag that this operand is used in a jump */ + +#define FPRINTF (*info->fprintf_func) +#define F info->stream + +/* sign-extend a 16-bit number in an int */ +#define SIGN_BITS (8 * sizeof (int) - 16) +#define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS) + +static int read_word PARAMS ((bfd_vma memaddr, int *word, + disassemble_info *info)); +static void print_signed_octal PARAMS ((int n, disassemble_info *info)); +static void print_reg PARAMS ((int reg, disassemble_info *info)); +static void print_freg PARAMS ((int freg, disassemble_info *info)); +static int print_operand PARAMS ((bfd_vma *memaddr, int code, + disassemble_info *info)); +static int print_foperand PARAMS ((bfd_vma *memaddr, int code, + disassemble_info *info)); +int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info)); + +static int +read_word (memaddr, word, info) + bfd_vma memaddr; + int *word; + disassemble_info *info; +{ + int status; + bfd_byte x[2]; + + status = (*info->read_memory_func) (memaddr, x, 2, info); + if (status != 0) + return -1; + + *word = x[1] << 8 | x[0]; + return 0; +} + +static void +print_signed_octal (n, info) + int n; + disassemble_info *info; +{ + if (n < 0) + FPRINTF (F, "-%o", -n); + else + FPRINTF (F, "%o", n); +} + +static void +print_reg (reg, info) + int reg; + disassemble_info *info; +{ + /* mask off the addressing mode, if any */ + reg &= 7; + + switch (reg) + { + case 0: case 1: case 2: case 3: case 4: case 5: + FPRINTF (F, "r%d", reg); break; + case 6: FPRINTF (F, "sp"); break; + case 7: FPRINTF (F, "pc"); break; + default: /* error */ + } +} + +static void +print_freg (freg, info) + int freg; + disassemble_info *info; +{ + FPRINTF (F, "fr%d", freg); +} + +static int +print_operand (memaddr, code, info) + bfd_vma *memaddr; + int code; + disassemble_info *info; +{ + int mode = (code >> 3) & 7; + int reg = code & 7; + int disp; + + switch (mode) + { + case 0: + print_reg (reg, info); + break; + case 1: + FPRINTF (F, "("); + print_reg (reg, info); + FPRINTF (F, ")"); + break; + case 2: + if (reg == 7) + { + int data; + if (read_word (*memaddr, &data, info) < 0) + return -1; + FPRINTF (F, "$"); + print_signed_octal (sign_extend (data), info); + *memaddr += 2; + } + else + { + FPRINTF (F, "("); + print_reg (reg, info); + FPRINTF (F, ")+"); + } + break; + case 3: + if (reg == 7) + { + int address; + if (read_word (*memaddr, &address, info) < 0) + return -1; + FPRINTF (F, "*$%o", address); + *memaddr += 2; + } + else + { + FPRINTF (F, "*("); + print_reg (reg, info); + FPRINTF (F, ")+"); + } + break; + case 4: + FPRINTF (F, "-("); + print_reg (reg, info); + FPRINTF (F, ")"); + break; + case 5: + FPRINTF (F, "*-("); + print_reg (reg, info); + FPRINTF (F, ")"); + break; + case 6: + case 7: + if (read_word (*memaddr, &disp, info) < 0) + return -1; + *memaddr += 2; + if (reg == 7) + { + bfd_vma address = *memaddr + sign_extend (disp); + if (mode == 7) + FPRINTF (F, "*"); + if (!(code & JUMP)) + FPRINTF (F, "$"); + (*info->print_address_func) (address, info); + } + else + { + if (mode == 7) + FPRINTF (F, "*"); + print_signed_octal (sign_extend (disp), info); + FPRINTF (F, "("); + print_reg (reg, info); + FPRINTF (F, ")"); + } + break; + } + + return 0; +} + +static int +print_foperand (memaddr, code, info) + bfd_vma *memaddr; + int code; + disassemble_info *info; +{ + int mode = (code >> 3) & 7; + int reg = code & 7; + + if (mode == 0) + print_freg (reg, info); + else + return print_operand (memaddr, code, info); + + return 0; +} + +/* Print the PDP-11 instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_pdp11 (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + bfd_vma start_memaddr = memaddr; + int opcode; + int src, dst; + int i; + + info->bytes_per_line = 6; + info->bytes_per_chunk = 2; + info->display_endian = BFD_ENDIAN_LITTLE; + + if (read_word (memaddr, &opcode, info) != 0) + return -1; + memaddr += 2; + + src = (opcode >> 6) & 0x3f; + dst = opcode & 0x3f; + + for (i = 0; i < pdp11_num_opcodes; i++) + { +#define OP pdp11_opcodes[i] + if ((opcode & OP.mask) == OP.opcode) + switch (OP.type) + { + case PDP11_OPCODE_NO_OPS: + FPRINTF (F, OP.name); + goto done; + case PDP11_OPCODE_REG: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_reg (dst, info); + goto done; + case PDP11_OPCODE_OP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (strcmp (OP.name, "jmp") == 0) + dst |= JUMP; + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_FOP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (strcmp (OP.name, "jmp") == 0) + dst |= JUMP; + if (print_foperand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_REG_OP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_reg (src, info); + FPRINTF (F, OPERAND_SEPARATOR); + if (strcmp (OP.name, "jsr") == 0) + dst |= JUMP; + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_REG_OP_REV: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + print_reg (src, info); + goto done; + case PDP11_OPCODE_AC_FOP: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_freg (ac, info); + FPRINTF (F, OPERAND_SEPARATOR); + if (print_foperand (&memaddr, dst, info) < 0) + return -1; + goto done; + } + case PDP11_OPCODE_FOP_AC: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_foperand (&memaddr, dst, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + print_freg (ac, info); + goto done; + } + case PDP11_OPCODE_AC_OP: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_freg (ac, info); + FPRINTF (F, OPERAND_SEPARATOR); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + } + case PDP11_OPCODE_OP_AC: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + print_freg (ac, info); + goto done; + } + case PDP11_OPCODE_OP_OP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_operand (&memaddr, src, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_DISPL: + { + int displ = (opcode & 0xff) << 8; + bfd_vma address = memaddr + (sign_extend (displ) >> 7); + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + (*info->print_address_func) (address, info); + goto done; + } + case PDP11_OPCODE_REG_DISPL: + { + int displ = (opcode & 0x3f) << 10; + bfd_vma address = memaddr + (sign_extend (displ) >> 9); + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_reg (src, info); + FPRINTF (F, OPERAND_SEPARATOR); + (*info->print_address_func) (address, info); + goto done; + } + case PDP11_OPCODE_IMM8: + { + int code = opcode & 0xff; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", code); + goto done; + } + case PDP11_OPCODE_IMM6: + { + int code = opcode & 0x3f; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", code); + goto done; + } + case PDP11_OPCODE_IMM3: + { + int code = opcode & 7; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", code); + goto done; + } + case PDP11_OPCODE_ILLEGAL: + { + FPRINTF (F, ".word"); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", opcode); + goto done; + } + default: + /* TODO: is this a proper way of signalling an error? */ + FPRINTF (F, ""); + return -1; + } +#undef OP + } + done: + + return memaddr - start_memaddr; +} diff --git a/opcodes/pdp11-opc.c b/opcodes/pdp11-opc.c new file mode 100644 index 0000000..7445cde --- /dev/null +++ b/opcodes/pdp11-opc.c @@ -0,0 +1,272 @@ +/* Opcode table for PDP-11. + Copyright 2001, 2002 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "opcode/pdp11.h" + +const struct pdp11_opcode pdp11_opcodes[] = +{ + /* name, pattern, mask, opcode type, insn type, alias */ + { "halt", 0x0000, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "wait", 0x0001, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "rti", 0x0002, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "bpt", 0x0003, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "iot", 0x0004, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "reset", 0x0005, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "rtt", 0x0006, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_LEIS }, + { "mfpt", 0x0007, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_MFPT }, + { "jmp", 0x0040, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rts", 0x0080, 0xfff8, PDP11_OPCODE_REG, PDP11_BASIC }, + { "", 0x0088, 0xfff8, PDP11_OPCODE_ILLEGAL, PDP11_NONE }, + { "", 0x0090, 0xfff8, PDP11_OPCODE_ILLEGAL, PDP11_NONE }, + { "spl", 0x0098, 0xfff8, PDP11_OPCODE_IMM3, PDP11_SPL }, + { "nop", 0x00a0, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "clc", 0x00a1, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "clv", 0x00a2, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_3", 0x00a3, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "clz", 0x00a4, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_5", 0x00a5, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_6", 0x00a6, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_7", 0x00a7, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cln", 0x00a8, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_9", 0x00a9, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_a", 0x00aa, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_b", 0x00ab, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_c", 0x00ac, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_d", 0x00ad, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_e", 0x00ae, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "ccc", 0x00af, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_0", 0x00b0, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sec", 0x00a1, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sev", 0x00b2, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_3", 0x00b3, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sez", 0x00b4, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_5", 0x00b5, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_6", 0x00b6, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_7", 0x00b7, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sen", 0x00b8, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_9", 0x00b9, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_a", 0x00ba, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_b", 0x00bb, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_c", 0x00bc, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_d", 0x00bd, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_e", 0x00be, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "scc", 0x00bf, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "swab", 0x00c0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "br", 0x0100, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bne", 0x0200, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "beq", 0x0300, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bge", 0x0400, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "blt", 0x0500, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bgt", 0x0600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "ble", 0x0700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "jsr", 0x0800, 0xfe00, PDP11_OPCODE_REG_OP, PDP11_BASIC }, + { "clr", 0x0a00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "com", 0x0a40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "inc", 0x0a80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "dec", 0x0ac0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "neg", 0x0b00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "adc", 0x0b40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "sbc", 0x0b80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "tst", 0x0bc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "ror", 0x0c00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rol", 0x0c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "asr", 0x0c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "asl", 0x0cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mark", 0x0d00, 0xffc0, PDP11_OPCODE_IMM6, PDP11_LEIS }, + { "mfpi", 0x0d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mtpi", 0x0d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "sxt", 0x0dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_LEIS }, + { "csm", 0x0e00, 0xffc0, PDP11_OPCODE_OP, PDP11_CSM }, + { "tstset", 0x0e40, 0xffc0, PDP11_OPCODE_OP, PDP11_MPROC }, + { "wrtlck", 0x0e80, 0xffc0, PDP11_OPCODE_OP, PDP11_MPROC }, +/*{ "", 0x0ec0, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ + { "mov", 0x1000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "cmp", 0x2000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bit", 0x3000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bic", 0x4000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bis", 0x5000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "add", 0x6000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "mul", 0x7000, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "div", 0x7200, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "ash", 0x7400, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "ashc", 0x7600, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "xor", 0x7800, 0xfe00, PDP11_OPCODE_REG_OP, PDP11_LEIS }, + { "fadd", 0x7a00, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, + { "fsub", 0x7a08, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, + { "fmul", 0x7a10, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, + { "fdiv", 0x7a18, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, +/*{ "", 0x7a20, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ +/*{ "", 0x7a40, 0xffc0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ +/*{ "", 0x7a80, 0xff80, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ +/*{ "", 0x7b00, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ + { "l2dr", 0x7c10, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },/*l2d*/ + { "movc", 0x7c18, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movrc", 0x7c19, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movtc", 0x7c1a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "locc", 0x7c20, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "skpc", 0x7c21, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "scanc", 0x7c22, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "spanc", 0x7c23, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpc", 0x7c24, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "matc", 0x7c25, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "addn", 0x7c28, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subn", 0x7c29, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpn", 0x7c2a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnl", 0x7c2b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpn", 0x7c2c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnp", 0x7c2d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashn", 0x7c2e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtln", 0x7c2f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "l3dr", 0x7c30, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },/*l3d*/ + { "addp", 0x7c38, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subp", 0x7c39, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpp", 0x7c3a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpl", 0x7c3b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "mulp", 0x7c3c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "divp", 0x7c3d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashp", 0x7c3e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtlp", 0x7c3f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movci", 0x7c58, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movrci", 0x7c59, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movtci", 0x7c5a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "locci", 0x7c60, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "skpci", 0x7c61, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "scanci", 0x7c62, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "spanci", 0x7c63, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpci", 0x7c64, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "matci", 0x7c65, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "addni", 0x7c68, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subni", 0x7c69, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpni", 0x7c6a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnli", 0x7c6b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpni", 0x7c6c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnpi", 0x7c6d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashni", 0x7c6e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtlni", 0x7c6f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "addpi", 0x7c78, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subpi", 0x7c79, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmppi", 0x7c7a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpli", 0x7c7b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "mulpi", 0x7c7c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "divpi", 0x7c7d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashpi", 0x7c7e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtlpi", 0x7c7f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "med", 0x7d80, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_UCODE }, + { "xfc", 0x7dc0, 0xffc0, PDP11_OPCODE_IMM6, PDP11_UCODE }, + { "sob", 0x7e00, 0xfe00, PDP11_OPCODE_REG_DISPL, PDP11_LEIS }, + { "bpl", 0x8000, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bmi", 0x8100, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bhi", 0x8200, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "blos", 0x8300, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bvc", 0x8400, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bvs", 0x8500, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bcc", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },/*bhis*/ + { "bcs", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },/*blo*/ + { "emt", 0x8800, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC }, + { "sys", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC },/*trap*/ + { "clrb", 0x8a00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "comb", 0x8a40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "incb", 0x8a80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "decb", 0x8ac0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "negb", 0x8b00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "adcb", 0x8b40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "sbcb", 0x8b80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "tstb", 0x8bc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rorb", 0x8c00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rolb", 0x8c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "asrb", 0x8c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "aslb", 0x8cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mtps", 0x8d00, 0xffc0, PDP11_OPCODE_OP, PDP11_MXPS }, + { "mfpd", 0x8d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mtpd", 0x8d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mfps", 0x8dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_MXPS }, + { "movb", 0x9000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "cmpb", 0xa000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bitb", 0xb000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bicb", 0xc000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bisb", 0xd000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "sub", 0xe000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "cfcc", 0xf000, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "setf", 0xf001, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "seti", 0xf002, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "ldub", 0xf003, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_UCODE }, + /* fpp trap 0xf004..0xf008 */ + { "setd", 0xf009, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "setl", 0xf00a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + /* fpp trap 0xf00b..0xf03f */ + { "ldfps", 0xf040, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP }, + { "stfps", 0xf080, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP }, + { "stst", 0xf0c0, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP }, + { "clrf", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "tstf", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "absf", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "negf", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "mulf", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "modf", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "addf", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "ldf", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/ + { "subf", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "cmpf", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "stf", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/ + { "divf", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "stexp", 0xfa00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcfi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcff", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */ + { "ldexp", 0xfd00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcif", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcff", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */ +/* This entry MUST be last; it is a "catch-all" entry that will match when no + * other opcode entry matches during disassembly. + */ + { "", 0x0000, 0x0000, PDP11_OPCODE_ILLEGAL, PDP11_NONE }, +}; + +const struct pdp11_opcode pdp11_aliases[] = +{ + /* name, pattern, mask, opcode type, insn type */ + { "l2d", 0x7c10, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS }, + { "l3d", 0x7c30, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS }, + { "bhis", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "blo", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "trap", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC }, + /* fpp xxxd alternate names to xxxf opcodes */ + { "clrd", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "tstd", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "absd", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "negd", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "muld", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "modd", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "addd", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "ldd", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/ + { "subd", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "cmpd", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "std", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/ + { "divd", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "stcfl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcdi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcdl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcfd", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */ + { "stcdf", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */ + { "ldcid", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldclf", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcld", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcfd", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */ + { "ldcdf", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */ +}; + +const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0]; +const int pdp11_num_aliases = sizeof pdp11_aliases / sizeof pdp11_aliases[0]; diff --git a/opcodes/pj-dis.c b/opcodes/pj-dis.c new file mode 100644 index 0000000..b8b81a9 --- /dev/null +++ b/opcodes/pj-dis.c @@ -0,0 +1,181 @@ +/* pj-dis.c -- Disassemble picoJava instructions. + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/pj.h" +#include "dis-asm.h" + +extern const pj_opc_info_t pj_opc_info[512]; + +static int get_int PARAMS ((bfd_vma, int *, struct disassemble_info *)); + + +static int +get_int (memaddr, iptr, info) + bfd_vma memaddr; + int *iptr; + struct disassemble_info *info; +{ + unsigned char ival[4]; + + int status = info->read_memory_func (memaddr, ival, 4, info); + + *iptr = (ival[0] << 24) + | (ival[1] << 16) + | (ival[2] << 8) + | (ival[3] << 0); + + return status; +} + +int +print_insn_pj (addr, info) + bfd_vma addr; + struct disassemble_info *info; +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned char opcode; + int status; + + if ((status = info->read_memory_func (addr, &opcode, 1, info))) + goto fail; + + if (opcode == 0xff) + { + unsigned char byte_2; + if ((status = info->read_memory_func (addr + 1, &byte_2, 1, info))) + goto fail; + fprintf_fn (stream, "%s\t", pj_opc_info[opcode + byte_2].name); + return 2; + } + else + { + char *sep = "\t"; + int insn_start = addr; + const pj_opc_info_t *op = &pj_opc_info[opcode]; + int a; + addr++; + fprintf_fn (stream, "%s", op->name); + + /* The tableswitch instruction is followed by the default + address, low value, high value and the destinations. */ + + if (strcmp (op->name, "tableswitch") == 0) + { + int lowval; + int highval; + int val; + + addr = (addr + 3) & ~3; + if ((status = get_int (addr, &val, info))) + goto fail; + + fprintf_fn (stream, " default: "); + (*info->print_address_func) (val + insn_start, info); + addr += 4; + + if ((status = get_int (addr, &lowval, info))) + goto fail; + addr += 4; + + if ((status = get_int (addr, &highval, info))) + goto fail; + addr += 4; + + while (lowval <= highval) + { + if ((status = get_int (addr, &val, info))) + goto fail; + fprintf_fn (stream, " %d:[", lowval); + (*info->print_address_func) (val + insn_start, info); + fprintf_fn (stream, " ]"); + addr += 4; + lowval++; + } + return addr - insn_start; + } + + /* The lookupswitch instruction is followed by the default + address, element count and pairs of values and + addresses. */ + + if (strcmp (op->name, "lookupswitch") == 0) + { + int count; + int val; + + addr = (addr + 3) & ~3; + if ((status = get_int (addr, &val, info))) + goto fail; + addr += 4; + + fprintf_fn (stream, " default: "); + (*info->print_address_func) (val + insn_start, info); + + if ((status = get_int (addr, &count, info))) + goto fail; + addr += 4; + + while (count--) + { + if ((status = get_int (addr, &val, info))) + goto fail; + addr += 4; + fprintf_fn (stream, " %d:[", val); + + if ((status = get_int (addr, &val, info))) + goto fail; + addr += 4; + + (*info->print_address_func) (val + insn_start, info); + fprintf_fn (stream, " ]"); + } + return addr - insn_start; + } + for (a = 0; op->arg[a]; a++) + { + unsigned char data[4]; + int val = 0; + int i; + int size = ASIZE (op->arg[a]); + + if ((status = info->read_memory_func (addr, data, size, info))) + goto fail; + + val = (UNS (op->arg[0]) || ((data[0] & 0x80) == 0)) ? 0 : -1; + + for (i = 0; i < size; i++) + val = (val << 8) | (data[i] & 0xff); + + if (PCREL (op->arg[a])) + (*info->print_address_func) (val + insn_start, info); + else + fprintf_fn (stream, "%s%d", sep, val); + + sep = ","; + addr += size; + } + return op->len; + } + + fail: + info->memory_error_func (status, addr, info); + return -1; +} diff --git a/opcodes/pj-opc.c b/opcodes/pj-opc.c new file mode 100644 index 0000000..ca2a867 --- /dev/null +++ b/opcodes/pj-opc.c @@ -0,0 +1,536 @@ +/* pj-opc.c -- Definitions for picoJava opcodes. + Copyright 1999, 2000 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include "sysdep.h" +#include "opcode/pj.h" + +const pj_opc_info_t pj_opc_info[512] = +{ +{ 0x00, -1, 1, {O_N, O_N}, "nop"}, +{ 0x01, -1, 1, {O_N, O_N}, "aconst_null"}, +{ 0x02, -1, 1, {O_N, O_N}, "iconst_m1"}, +{ 0x03, -1, 1, {O_N, O_N}, "iconst_0"}, +{ 0x04, -1, 1, {O_N, O_N}, "iconst_1"}, +{ 0x05, -1, 1, {O_N, O_N}, "iconst_2"}, +{ 0x06, -1, 1, {O_N, O_N}, "iconst_3"}, +{ 0x07, -1, 1, {O_N, O_N}, "iconst_4"}, +{ 0x08, -1, 1, {O_N, O_N}, "iconst_5"}, +{ 0x09, -1, 1, {O_N, O_N}, "lconst_0"}, +{ 0x0a, -1, 1, {O_N, O_N}, "lconst_1"}, +{ 0x0b, -1, 1, {O_N, O_N}, "fconst_0"}, +{ 0x0c, -1, 1, {O_N, O_N}, "fconst_1"}, +{ 0x0d, -1, 1, {O_N, O_N}, "fconst_2"}, +{ 0x0e, -1, 1, {O_N, O_N}, "dconst_0"}, +{ 0x0f, -1, 1, {O_N, O_N}, "dconst_1"}, +{ 0x10, -1, 2, {O_8, O_N}, "bipush"}, +{ 0x11, -1, 3, {O_16, O_N}, "sipush"}, +{ 0x12, -1, 2, {O_N, O_N}, "ldc"}, +{ 0x13, -1, 3, {O_N, O_N}, "ldc_w"}, +{ 0x14, -1, 3, {O_N, O_N}, "ldc2_w"}, +{ 0x15, -1, 2, {O_U8, O_N}, "iload"}, +{ 0x16, -1, 2, {O_U8, O_N}, "lload"}, +{ 0x17, -1, 2, {O_U8, O_N}, "fload"}, +{ 0x18, -1, 2, {O_U8, O_N}, "dload"}, +{ 0x19, -1, 2, {O_U8, O_N}, "aload"}, +{ 0x1a, -1, 1, {O_N, O_N}, "iload_0"}, +{ 0x1b, -1, 1, {O_N, O_N}, "iload_1"}, +{ 0x1c, -1, 1, {O_N, O_N}, "iload_2"}, +{ 0x1d, -1, 1, {O_N, O_N}, "iload_3"}, +{ 0x1e, -1, 1, {O_N, O_N}, "lload_0"}, +{ 0x1f, -1, 1, {O_N, O_N}, "lload_1"}, +{ 0x20, -1, 1, {O_N, O_N}, "lload_2"}, +{ 0x21, -1, 1, {O_N, O_N}, "lload_3"}, +{ 0x22, -1, 1, {O_N, O_N}, "fload_0"}, +{ 0x23, -1, 1, {O_N, O_N}, "fload_1"}, +{ 0x24, -1, 1, {O_N, O_N}, "fload_2"}, +{ 0x25, -1, 1, {O_N, O_N}, "fload_3"}, +{ 0x26, -1, 1, {O_N, O_N}, "dload_0"}, +{ 0x27, -1, 1, {O_N, O_N}, "dload_1"}, +{ 0x28, -1, 1, {O_N, O_N}, "dload_2"}, +{ 0x29, -1, 1, {O_N, O_N}, "dload_3"}, +{ 0x2a, -1, 1, {O_N, O_N}, "aload_0"}, +{ 0x2b, -1, 1, {O_N, O_N}, "aload_1"}, +{ 0x2c, -1, 1, {O_N, O_N}, "aload_2"}, +{ 0x2d, -1, 1, {O_N, O_N}, "aload_3"}, +{ 0x2e, -1, 1, {O_N, O_N}, "iaload"}, +{ 0x2f, -1, 1, {O_N, O_N}, "laload"}, +{ 0x30, -1, 1, {O_N, O_N}, "faload"}, +{ 0x31, -1, 1, {O_N, O_N}, "daload"}, +{ 0x32, -1, 1, {O_N, O_N}, "aaload"}, +{ 0x33, -1, 1, {O_N, O_N}, "baload"}, +{ 0x34, -1, 1, {O_N, O_N}, "caload"}, +{ 0x35, -1, 1, {O_N, O_N}, "saload"}, +{ 0x36, -1, 2, {O_U8, O_N}, "istore"}, +{ 0x37, -1, 2, {O_U8, O_N}, "lstore"}, +{ 0x38, -1, 2, {O_U8, O_N}, "fstore"}, +{ 0x39, -1, 2, {O_U8, O_N}, "dstore"}, +{ 0x3a, -1, 2, {O_U8, O_N}, "astore"}, +{ 0x3b, -1, 1, {O_N, O_N}, "istore_0"}, +{ 0x3c, -1, 1, {O_N, O_N}, "istore_1"}, +{ 0x3d, -1, 1, {O_N, O_N}, "istore_2"}, +{ 0x3e, -1, 1, {O_N, O_N}, "istore_3"}, +{ 0x3f, -1, 1, {O_N, O_N}, "lstore_0"}, +{ 0x40, -1, 1, {O_N, O_N}, "lstore_1"}, +{ 0x41, -1, 1, {O_N, O_N}, "lstore_2"}, +{ 0x42, -1, 1, {O_N, O_N}, "lstore_3"}, +{ 0x43, -1, 1, {O_N, O_N}, "fstore_0"}, +{ 0x44, -1, 1, {O_N, O_N}, "fstore_1"}, +{ 0x45, -1, 1, {O_N, O_N}, "fstore_2"}, +{ 0x46, -1, 1, {O_N, O_N}, "fstore_3"}, +{ 0x47, -1, 1, {O_N, O_N}, "dstore_0"}, +{ 0x48, -1, 1, {O_N, O_N}, "dstore_1"}, +{ 0x49, -1, 1, {O_N, O_N}, "dstore_2"}, +{ 0x4a, -1, 1, {O_N, O_N}, "dstore_3"}, +{ 0x4b, -1, 1, {O_N, O_N}, "astore_0"}, +{ 0x4c, -1, 1, {O_N, O_N}, "astore_1"}, +{ 0x4d, -1, 1, {O_N, O_N}, "astore_2"}, +{ 0x4e, -1, 1, {O_N, O_N}, "astore_3"}, +{ 0x4f, -1, 1, {O_N, O_N}, "iastore"}, +{ 0x50, -1, 1, {O_N, O_N}, "lastore"}, +{ 0x51, -1, 1, {O_N, O_N}, "fastore"}, +{ 0x52, -1, 1, {O_N, O_N}, "dastore"}, +{ 0x53, -1, 1, {O_N, O_N}, "aastore"}, +{ 0x54, -1, 1, {O_N, O_N}, "bastore"}, +{ 0x55, -1, 1, {O_N, O_N}, "castore"}, +{ 0x56, -1, 1, {O_N, O_N}, "sastore"}, +{ 0x57, -1, 1, {O_N, O_N}, "pop"}, +{ 0x58, -1, 1, {O_N, O_N}, "pop2"}, +{ 0x59, -1, 1, {O_N, O_N}, "dup"}, +{ 0x5a, -1, 1, {O_N, O_N}, "dup_x1"}, +{ 0x5b, -1, 1, {O_N, O_N}, "dup_x2"}, +{ 0x5c, -1, 1, {O_N, O_N}, "dup2"}, +{ 0x5d, -1, 1, {O_N, O_N}, "dup2_x1"}, +{ 0x5e, -1, 1, {O_N, O_N}, "dup2_x2"}, +{ 0x5f, -1, 1, {O_N, O_N}, "swap"}, +{ 0x60, -1, 1, {O_N, O_N}, "iadd"}, +{ 0x61, -1, 1, {O_N, O_N}, "ladd"}, +{ 0x62, -1, 1, {O_N, O_N}, "fadd"}, +{ 0x63, -1, 1, {O_N, O_N}, "dadd"}, +{ 0x64, -1, 1, {O_N, O_N}, "isub"}, +{ 0x65, -1, 1, {O_N, O_N}, "lsub"}, +{ 0x66, -1, 1, {O_N, O_N}, "fsub"}, +{ 0x67, -1, 1, {O_N, O_N}, "dsub"}, +{ 0x68, -1, 1, {O_N, O_N}, "imul"}, +{ 0x69, -1, 1, {O_N, O_N}, "lmul"}, +{ 0x6a, -1, 1, {O_N, O_N}, "fmul"}, +{ 0x6b, -1, 1, {O_N, O_N}, "dmul"}, +{ 0x6c, -1, 1, {O_N, O_N}, "idiv"}, +{ 0x6d, -1, 1, {O_N, O_N}, "ldiv"}, +{ 0x6e, -1, 1, {O_N, O_N}, "fdiv"}, +{ 0x6f, -1, 1, {O_N, O_N}, "ddiv"}, +{ 0x70, -1, 1, {O_N, O_N}, "irem"}, +{ 0x71, -1, 1, {O_N, O_N}, "lrem"}, +{ 0x72, -1, 1, {O_N, O_N}, "frem"}, +{ 0x73, -1, 1, {O_N, O_N}, "drem"}, +{ 0x74, -1, 1, {O_N, O_N}, "ineg"}, +{ 0x75, -1, 1, {O_N, O_N}, "lneg"}, +{ 0x76, -1, 1, {O_N, O_N}, "fneg"}, +{ 0x77, -1, 1, {O_N, O_N}, "dneg"}, +{ 0x78, -1, 1, {O_N, O_N}, "ishl"}, +{ 0x79, -1, 1, {O_N, O_N}, "lshl"}, +{ 0x7a, -1, 1, {O_N, O_N}, "ishr"}, +{ 0x7b, -1, 1, {O_N, O_N}, "lshr"}, +{ 0x7c, -1, 1, {O_N, O_N}, "iushr"}, +{ 0x7d, -1, 1, {O_N, O_N}, "lushr"}, +{ 0x7e, -1, 1, {O_N, O_N}, "iand"}, +{ 0x7f, -1, 1, {O_N, O_N}, "land"}, +{ 0x80, -1, 1, {O_N, O_N}, "ior"}, +{ 0x81, -1, 1, {O_N, O_N}, "lor"}, +{ 0x82, -1, 1, {O_N, O_N}, "ixor"}, +{ 0x83, -1, 1, {O_N, O_N}, "lxor"}, +{ 0x84, -1, 3, {O_U8, O_8}, "iinc"}, +{ 0x85, -1, 1, {O_N, O_N}, "i2l"}, +{ 0x86, -1, 1, {O_N, O_N}, "i2f"}, +{ 0x87, -1, 1, {O_N, O_N}, "i2d"}, +{ 0x88, -1, 1, {O_N, O_N}, "l2i"}, +{ 0x89, -1, 1, {O_N, O_N}, "l2f"}, +{ 0x8a, -1, 1, {O_N, O_N}, "l2d"}, +{ 0x8b, -1, 1, {O_N, O_N}, "f2i"}, +{ 0x8c, -1, 1, {O_N, O_N}, "f2l"}, +{ 0x8d, -1, 1, {O_N, O_N}, "f2d"}, +{ 0x8e, -1, 1, {O_N, O_N}, "d2i"}, +{ 0x8f, -1, 1, {O_N, O_N}, "d2l"}, +{ 0x90, -1, 1, {O_N, O_N}, "d2f"}, +{ 0x91, -1, 1, {O_N, O_N}, "i2b"}, +{ 0x92, -1, 1, {O_N, O_N}, "i2c"}, +{ 0x93, -1, 1, {O_N, O_N}, "i2s"}, +{ 0x94, -1, 1, {O_N, O_N}, "lcmp"}, +{ 0x95, -1, 1, {O_N, O_N}, "fcmpl"}, +{ 0x96, -1, 1, {O_N, O_N}, "fcmpg"}, +{ 0x97, -1, 1, {O_N, O_N}, "dcmpl"}, +{ 0x98, -1, 1, {O_N, O_N}, "dcmpg"}, +{ 0x99, -1, 3, {O_R16, O_N}, "ifeq"}, +{ 0x9a, -1, 3, {O_R16, O_N}, "ifne"}, +{ 0x9b, -1, 3, {O_R16, O_N}, "iflt"}, +{ 0x9c, -1, 3, {O_R16, O_N}, "ifge"}, +{ 0x9d, -1, 3, {O_R16, O_N}, "ifgt"}, +{ 0x9e, -1, 3, {O_R16, O_N}, "ifle"}, +{ 0x9f, -1, 3, {O_R16, O_N}, "if_icmpeq"}, +{ 0xa0, -1, 3, {O_R16, O_N}, "if_icmpne"}, +{ 0xa1, -1, 3, {O_R16, O_N}, "if_icmplt"}, +{ 0xa2, -1, 3, {O_R16, O_N}, "if_icmpge"}, +{ 0xa3, -1, 3, {O_R16, O_N}, "if_icmpgt"}, +{ 0xa4, -1, 3, {O_R16, O_N}, "if_icmple"}, +{ 0xa5, -1, 3, {O_R16, O_N}, "if_acmpeq"}, +{ 0xa6, -1, 3, {O_R16, O_N}, "if_acmpne"}, +{ 0xa7, -1, 3, {O_R16, O_N}, "goto"}, +{ 0xa8, -1, 3, {O_N, O_N}, "jsr"}, +{ 0xa9, -1, 2, {O_N, O_N}, "ret"}, +{ 0xaa, -1, 1, {O_N, O_N}, "tableswitch"}, +{ 0xab, -1, 1, {O_N, O_N}, "lookupswitch"}, +{ 0xac, -1, 1, {O_N, O_N}, "ireturn"}, +{ 0xad, -1, 1, {O_N, O_N}, "lreturn"}, +{ 0xae, -1, 1, {O_N, O_N}, "freturn"}, +{ 0xaf, -1, 1, {O_N, O_N}, "dreturn"}, +{ 0xb0, -1, 1, {O_N, O_N}, "areturn"}, +{ 0xb1, -1, 1, {O_N, O_N}, "return"}, +{ 0xb2, -1, 3, {O_N, O_N}, "getstatic"}, +{ 0xb3, -1, 3, {O_N, O_N}, "putstatic"}, +{ 0xb4, -1, 3, {O_N, O_N}, "getfield"}, +{ 0xb5, -1, 3, {O_N, O_N}, "putfield"}, +{ 0xb6, -1, 3, {O_N, O_N}, "invokevirtual"}, +{ 0xb7, -1, 3, {O_N, O_N}, "invokespecial"}, +{ 0xb8, -1, 3, {O_N, O_N}, "invokestatic"}, +{ 0xb9, -1, 5, {O_N, O_N}, "invokeinterface"}, +{ 0xba, -1, 1, {O_N, O_N}, "bad_ba"}, +{ 0xbb, -1, 3, {O_N, O_N}, "new"}, +{ 0xbc, -1, 2, {O_N, O_N}, "newarray"}, +{ 0xbd, -1, 3, {O_N, O_N}, "anewarray"}, +{ 0xbe, -1, 1, {O_N, O_N}, "arraylength"}, +{ 0xbf, -1, 1, {O_N, O_N}, "athrow"}, +{ 0xc0, -1, 3, {O_N, O_N}, "checkcast"}, +{ 0xc1, -1, 3, {O_N, O_N}, "instanceof"}, +{ 0xc2, -1, 1, {O_N, O_N}, "monitorenter"}, +{ 0xc3, -1, 1, {O_N, O_N}, "monitorexit"}, +{ 0xc4, -1, 1, {O_N, O_N}, "wide"}, +{ 0xc5, -1, 4, {O_N, O_N}, "multianewarray"}, +{ 0xc6, -1, 3, {O_N, O_N}, "ifnull"}, +{ 0xc7, -1, 3, {O_N, O_N}, "ifnonnull"}, +{ 0xc8, -1, 5, {O_N, O_N}, "goto_w"}, +{ 0xc9, -1, 5, {O_N, O_N}, "jsr_w"}, +{ 0xca, -1, 1, {O_N, O_N}, "breakpoint"}, +{ 0xcb, -1, 1, {O_N, O_N}, "bytecode"}, +{ 0xcc, -1, 1, {O_N, O_N}, "try"}, +{ 0xcd, -1, 1, {O_N, O_N}, "endtry"}, +{ 0xce, -1, 1, {O_N, O_N}, "catch"}, +{ 0xcf, -1, 1, {O_N, O_N}, "var"}, +{ 0xd0, -1, 1, {O_N, O_N}, "endvar"}, +{ 0xd1, -1, 1, {O_N, O_N}, "bad_d1"}, +{ 0xd2, -1, 1, {O_N, O_N}, "bad_d2"}, +{ 0xd3, -1, 1, {O_N, O_N}, "bad_d3"}, +{ 0xd4, -1, 1, {O_N, O_N}, "bad_d4"}, +{ 0xd5, -1, 1, {O_N, O_N}, "bad_d5"}, +{ 0xd6, -1, 1, {O_N, O_N}, "bad_d6"}, +{ 0xd7, -1, 1, {O_N, O_N}, "bad_d7"}, +{ 0xd8, -1, 1, {O_N, O_N}, "bad_d8"}, +{ 0xd9, -1, 1, {O_N, O_N}, "bad_d9"}, +{ 0xda, -1, 1, {O_N, O_N}, "bad_da"}, +{ 0xdb, -1, 1, {O_N, O_N}, "bad_db"}, +{ 0xdc, -1, 1, {O_N, O_N}, "bad_dc"}, +{ 0xdd, -1, 1, {O_N, O_N}, "bad_dd"}, +{ 0xde, -1, 1, {O_N, O_N}, "bad_de"}, +{ 0xdf, -1, 1, {O_N, O_N}, "bad_df"}, +{ 0xe0, -1, 1, {O_N, O_N}, "bad_e0"}, +{ 0xe1, -1, 1, {O_N, O_N}, "bad_e1"}, +{ 0xe2, -1, 1, {O_N, O_N}, "bad_e2"}, +{ 0xe3, -1, 1, {O_N, O_N}, "bad_e3"}, +{ 0xe4, -1, 1, {O_N, O_N}, "bad_e4"}, +{ 0xe5, -1, 1, {O_N, O_N}, "bad_e5"}, +{ 0xe6, -1, 1, {O_N, O_N}, "bad_e6"}, +{ 0xe7, -1, 1, {O_N, O_N}, "bad_e7"}, +{ 0xe8, -1, 1, {O_N, O_N}, "bad_e8"}, +{ 0xe9, -1, 1, {O_N, O_N}, "bad_e9"}, +{ 0xea, -1, 1, {O_N, O_N}, "bad_ea"}, +{ 0xeb, -1, 1, {O_N, O_N}, "bad_eb"}, +{ 0xec, -1, 1, {O_N, O_N}, "bad_ec"}, +{ 0xed, -1, 3, {O_16, O_N}, "sethi"}, +{ 0xee, -1, 3, {O_U8, O_8}, "load_word_index"}, +{ 0xef, -1, 3, {O_U8, O_8}, "load_short_index"}, +{ 0xf0, -1, 3, {O_U8, O_8}, "load_char_index"}, +{ 0xf1, -1, 3, {O_U8, O_8}, "load_byte_index"}, +{ 0xf2, -1, 3, {O_U8, O_8}, "load_ubyte_index"}, +{ 0xf3, -1, 3, {O_U8, O_8}, "store_word_index"}, +{ 0xf4, -1, 3, {O_U8, O_8}, "na_store_word_index"}, +{ 0xf5, -1, 3, {O_U8, O_8}, "store_short_index"}, +{ 0xf6, -1, 3, {O_U8, O_8}, "store_byte_index"}, +{ 0xf7, -1, 1, {O_N, O_N}, "bad_f7"}, +{ 0xf8, -1, 1, {O_N, O_N}, "bad_f8"}, +{ 0xf9, -1, 1, {O_N, O_N}, "bad_f9"}, +{ 0xfa, -1, 1, {O_N, O_N}, "bad_fa"}, +{ 0xfb, -1, 1, {O_N, O_N}, "bad_fb"}, +{ 0xfc, -1, 1, {O_N, O_N}, "bad_fc"}, +{ 0xfd, -1, 1, {O_N, O_N}, "bad_fd"}, +{ 0xfe, -1, 1, {O_N, O_N}, "bad_fe"}, +{ 0xff, 0x00, 2, {O_N, O_N}, "load_ubyte"}, +{ 0xff, 0x01, 2, {O_N, O_N}, "load_byte"}, +{ 0xff, 0x02, 2, {O_N, O_N}, "load_char"}, +{ 0xff, 0x03, 2, {O_N, O_N}, "load_short"}, +{ 0xff, 0x04, 2, {O_N, O_N}, "load_word"}, +{ 0xff, 0x05, 2, {O_N, O_N}, "priv_ret_from_trap"}, +{ 0xff, 0x06, 2, {O_N, O_N}, "priv_read_dcache_tag"}, +{ 0xff, 0x07, 2, {O_N, O_N}, "priv_read_dcache_data"}, +{ 0xff, 0x08, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x09, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x0a, 2, {O_N, O_N}, "load_char_oe"}, +{ 0xff, 0x0b, 2, {O_N, O_N}, "load_short_oe"}, +{ 0xff, 0x0c, 2, {O_N, O_N}, "load_word_oe"}, +{ 0xff, 0x0d, 2, {O_N, O_N}, "return0"}, +{ 0xff, 0x0e, 2, {O_N, O_N}, "priv_read_icache_tag"}, +{ 0xff, 0x0f, 2, {O_N, O_N}, "priv_read_icache_data"}, +{ 0xff, 0x10, 2, {O_N, O_N}, "ncload_ubyte"}, +{ 0xff, 0x11, 2, {O_N, O_N}, "ncload_byte"}, +{ 0xff, 0x12, 2, {O_N, O_N}, "ncload_char"}, +{ 0xff, 0x13, 2, {O_N, O_N}, "ncload_short"}, +{ 0xff, 0x14, 2, {O_N, O_N}, "ncload_word"}, +{ 0xff, 0x15, 2, {O_N, O_N}, "iucmp"}, +{ 0xff, 0x16, 2, {O_N, O_N}, "priv_powerdown"}, +{ 0xff, 0x17, 2, {O_N, O_N}, "cache_invalidate"}, +{ 0xff, 0x18, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x19, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x1a, 2, {O_N, O_N}, "ncload_char_oe"}, +{ 0xff, 0x1b, 2, {O_N, O_N}, "ncload_short_oe"}, +{ 0xff, 0x1c, 2, {O_N, O_N}, "ncload_word_oe"}, +{ 0xff, 0x1d, 2, {O_N, O_N}, "return1"}, +{ 0xff, 0x1e, 2, {O_N, O_N}, "cache_flush"}, +{ 0xff, 0x1f, 2, {O_N, O_N}, "cache_index_flush"}, +{ 0xff, 0x20, 2, {O_N, O_N}, "store_byte"}, +{ 0xff, 0x21, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x22, 2, {O_N, O_N}, "store_short"}, +{ 0xff, 0x23, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x24, 2, {O_N, O_N}, "store_word"}, +{ 0xff, 0x25, 2, {O_N, O_N}, "soft_trap"}, +{ 0xff, 0x26, 2, {O_N, O_N}, "priv_write_dcache_tag"}, +{ 0xff, 0x27, 2, {O_N, O_N}, "priv_write_dcache_data"}, +{ 0xff, 0x28, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x29, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x2a, 2, {O_N, O_N}, "store_short_oe"}, +{ 0xff, 0x2b, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x2c, 2, {O_N, O_N}, "store_word_oe"}, +{ 0xff, 0x2d, 2, {O_N, O_N}, "return2"}, +{ 0xff, 0x2e, 2, {O_N, O_N}, "priv_write_icache_tag"}, +{ 0xff, 0x2f, 2, {O_N, O_N}, "priv_write_icache_data"}, +{ 0xff, 0x30, 2, {O_N, O_N}, "ncstore_byte"}, +{ 0xff, 0x31, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x32, 2, {O_N, O_N}, "ncstore_short"}, +{ 0xff, 0x33, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x34, 2, {O_N, O_N}, "ncstore_word"}, +{ 0xff, 0x35, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x36, 2, {O_N, O_N}, "priv_reset"}, +{ 0xff, 0x37, 2, {O_N, O_N}, "get_current_class"}, +{ 0xff, 0x38, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x39, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x3a, 2, {O_N, O_N}, "ncstore_short_oe"}, +{ 0xff, 0x3b, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x3c, 2, {O_N, O_N}, "ncstore_word_oe"}, +{ 0xff, 0x3d, 2, {O_N, O_N}, "call"}, +{ 0xff, 0x3e, 2, {O_N, O_N}, "zero_line"}, +{ 0xff, 0x3f, 2, {O_N, O_N}, "priv_update_optop"}, +{ 0xff, 0x40, 2, {O_N, O_N}, "read_pc"}, +{ 0xff, 0x41, 2, {O_N, O_N}, "read_vars"}, +{ 0xff, 0x42, 2, {O_N, O_N}, "read_frame"}, +{ 0xff, 0x43, 2, {O_N, O_N}, "read_optop"}, +{ 0xff, 0x44, 2, {O_N, O_N}, "priv_read_oplim"}, +{ 0xff, 0x45, 2, {O_N, O_N}, "read_const_pool"}, +{ 0xff, 0x46, 2, {O_N, O_N}, "priv_read_psr"}, +{ 0xff, 0x47, 2, {O_N, O_N}, "priv_read_trapbase"}, +{ 0xff, 0x48, 2, {O_N, O_N}, "priv_read_lockcount0"}, +{ 0xff, 0x49, 2, {O_N, O_N}, "priv_read_lockcount1"}, +{ 0xff, 0x4a, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x4b, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x4c, 2, {O_N, O_N}, "priv_read_lockaddr0"}, +{ 0xff, 0x4d, 2, {O_N, O_N}, "priv_read_lockaddr1"}, +{ 0xff, 0x4e, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x4f, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x50, 2, {O_N, O_N}, "priv_read_userrange1"}, +{ 0xff, 0x51, 2, {O_N, O_N}, "priv_read_gc_config"}, +{ 0xff, 0x52, 2, {O_N, O_N}, "priv_read_brk1a"}, +{ 0xff, 0x53, 2, {O_N, O_N}, "priv_read_brk2a"}, +{ 0xff, 0x54, 2, {O_N, O_N}, "priv_read_brk12c"}, +{ 0xff, 0x55, 2, {O_N, O_N}, "priv_read_userrange2"}, +{ 0xff, 0x56, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x57, 2, {O_N, O_N}, "priv_read_versionid"}, +{ 0xff, 0x58, 2, {O_N, O_N}, "priv_read_hcr"}, +{ 0xff, 0x59, 2, {O_N, O_N}, "priv_read_sc_bottom"}, +{ 0xff, 0x5a, 2, {O_N, O_N}, "read_global0"}, +{ 0xff, 0x5b, 2, {O_N, O_N}, "read_global1"}, +{ 0xff, 0x5c, 2, {O_N, O_N}, "read_global2"}, +{ 0xff, 0x5d, 2, {O_N, O_N}, "read_global3"}, +{ 0xff, 0x5e, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x5f, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x60, 2, {O_N, O_N}, "write_pc"}, +{ 0xff, 0x61, 2, {O_N, O_N}, "write_vars"}, +{ 0xff, 0x62, 2, {O_N, O_N}, "write_frame"}, +{ 0xff, 0x63, 2, {O_N, O_N}, "write_optop"}, +{ 0xff, 0x64, 2, {O_N, O_N}, "priv_write_oplim"}, +{ 0xff, 0x65, 2, {O_N, O_N}, "write_const_pool"}, +{ 0xff, 0x66, 2, {O_N, O_N}, "priv_write_psr"}, +{ 0xff, 0x67, 2, {O_N, O_N}, "priv_write_trapbase"}, +{ 0xff, 0x68, 2, {O_N, O_N}, "priv_write_lockcount0"}, +{ 0xff, 0x69, 2, {O_N, O_N}, "priv_write_lockcount1"}, +{ 0xff, 0x6a, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x6b, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x6c, 2, {O_N, O_N}, "priv_write_lockaddr0"}, +{ 0xff, 0x6d, 2, {O_N, O_N}, "priv_write_lockaddr1"}, +{ 0xff, 0x6e, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x6f, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x70, 2, {O_N, O_N}, "priv_write_userrange1"}, +{ 0xff, 0x71, 2, {O_N, O_N}, "priv_write_gc_config"}, +{ 0xff, 0x72, 2, {O_N, O_N}, "priv_write_brk1a"}, +{ 0xff, 0x73, 2, {O_N, O_N}, "priv_write_brk2a"}, +{ 0xff, 0x74, 2, {O_N, O_N}, "priv_write_brk12c"}, +{ 0xff, 0x75, 2, {O_N, O_N}, "priv_write_userrange2"}, +{ 0xff, 0x76, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x77, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x78, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x79, 2, {O_N, O_N}, "priv_write_sc_bottom"}, +{ 0xff, 0x7a, 2, {O_N, O_N}, "write_global0"}, +{ 0xff, 0x7b, 2, {O_N, O_N}, "write_global1"}, +{ 0xff, 0x7c, 2, {O_N, O_N}, "write_global2"}, +{ 0xff, 0x7d, 2, {O_N, O_N}, "write_global3"}, +{ 0xff, 0x7e, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x7f, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x80, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x81, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x82, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x83, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x84, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x85, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x86, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x87, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x88, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x89, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x8a, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x8b, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x8c, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x8d, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x8e, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x8f, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x90, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x91, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x92, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x93, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x94, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x95, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x96, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x97, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x98, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x99, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x9a, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x9b, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x9c, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x9d, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x9e, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0x9f, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa0, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa1, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa2, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa3, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa4, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa5, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa6, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa7, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa8, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xa9, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xaa, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xab, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xac, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xad, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xae, 2, {O_N, O_N}, "tm_putchar"}, +{ 0xff, 0xaf, 2, {O_N, O_N}, "tm_exit"}, +{ 0xff, 0xb0, 2, {O_N, O_N}, "tm_trap"}, +{ 0xff, 0xb1, 2, {O_N, O_N}, "tm_minfo"}, +{ 0xff, 0xb2, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb3, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb4, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb5, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb6, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb7, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb8, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xb9, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xba, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xbb, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xbc, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xbd, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xbe, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xbf, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc0, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc1, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc2, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc3, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc4, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc5, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc6, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc7, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc8, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xc9, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xca, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xcb, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xcc, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xcd, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xce, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xcf, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd0, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd1, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd2, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd3, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd4, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd5, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd6, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd7, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd8, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xd9, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xda, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xdb, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xdc, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xdd, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xde, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xdf, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe0, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe1, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe2, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe3, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe4, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe5, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe6, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe7, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe8, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xe9, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xea, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xeb, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xec, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xed, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xee, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xef, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf0, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf1, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf2, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf3, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf4, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf5, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf6, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf7, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf8, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xf9, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xfa, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xfb, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xfc, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xfd, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xfe, 2, {O_N, O_N}, "bad"}, +{ 0xff, 0xff, 2, {O_N, O_N}, "bad"}, +}; diff --git a/opcodes/po/.cvsignore b/opcodes/po/.cvsignore new file mode 100644 index 0000000..becd153 --- /dev/null +++ b/opcodes/po/.cvsignore @@ -0,0 +1 @@ +*.gmo diff --git a/opcodes/po/Make-in b/opcodes/po/Make-in new file mode 100644 index 0000000..0552db1 --- /dev/null +++ b/opcodes/po/Make-in @@ -0,0 +1,251 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +PACKAGE = @PACKAGE@ +VERSION = @VERSION@ + +SHELL = /bin/sh +@SET_MAKE@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +datadir = $(prefix)/@DATADIRNAME@ +localedir = $(datadir)/locale +gnulocaledir = $(prefix)/share/locale +gettextsrcdir = $(prefix)/share/gettext/po +subdir = po + +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +MKINSTALLDIRS = @MKINSTALLDIRS@ + +CC = @CC@ +GENCAT = @GENCAT@ +GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ +MSGFMT = @MSGFMT@ +XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ +MSGMERGE = PATH=../src:$$PATH msgmerge + +DEFS = @DEFS@ +CFLAGS = @CFLAGS@ +CPPFLAGS = @CPPFLAGS@ + +INCLUDES = -I.. -I$(top_srcdir)/intl + +COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) + +SOURCES = cat-id-tbl.c +POFILES = @POFILES@ +GMOFILES = @GMOFILES@ +DISTFILES = ChangeLog Makefile.in.in POTFILES.in $(PACKAGE).pot \ +stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) + +POTFILES = \ + +CATALOGS = @CATALOGS@ +CATOBJEXT = @CATOBJEXT@ +INSTOBJEXT = @INSTOBJEXT@ + +.SUFFIXES: +.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat + +.c.o: + $(COMPILE) $< + +.po.pox: + $(MAKE) $(PACKAGE).pot + $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox + +.po.mo: + $(MSGFMT) -o $@ $< + +.po.gmo: + file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \ + && rm -f $$file && $(GMSGFMT) -o $$file $< + +.po.cat: + sed -f ../intl/po2msg.sed < $< > $*.msg \ + && rm -f $@ && $(GENCAT) $@ $*.msg + + +all: all-@USE_NLS@ + +all-yes: $(CATALOGS) @MAINT@ $(PACKAGE).pot +all-no: + +$(srcdir)/$(PACKAGE).pot: $(POTFILES) + $(XGETTEXT) --default-domain=$(PACKAGE) --directory=$(top_srcdir) \ + --add-comments --keyword=_ --keyword=N_ \ + --files-from=$(srcdir)/POTFILES.in + rm -f $(srcdir)/$(PACKAGE).pot + mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot + +$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: +$(srcdir)/stamp-cat-id: $(PACKAGE).pot + rm -f cat-id-tbl.tmp + sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ + | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp + if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ + rm cat-id-tbl.tmp; \ + else \ + echo cat-id-tbl.c changed; \ + rm -f $(srcdir)/cat-id-tbl.c; \ + mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ + fi + cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id + + +install: install-exec install-data +install-exec: +install-info: +install-data: install-data-@USE_NLS@ +install-data-no: all +install-data-yes: all + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $(datadir); \ + else \ + $(top_srcdir)/mkinstalldirs $(datadir); \ + fi + @catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + case "$$cat" in \ + *.gmo) destdir=$(gnulocaledir);; \ + *) destdir=$(localedir);; \ + esac; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + dir=$$destdir/$$lang/LC_MESSAGES; \ + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $$dir; \ + else \ + $(top_srcdir)/mkinstalldirs $$dir; \ + fi; \ + if test -r $$cat; then \ + $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ + echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ + else \ + $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ + echo "installing $(srcdir)/$$cat as" \ + "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ + fi; \ + if test -r $$cat.m; then \ + $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ + echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ + else \ + if test -r $(srcdir)/$$cat.m ; then \ + $(INSTALL_DATA) $(srcdir)/$$cat.m \ + $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ + echo "installing $(srcdir)/$$cat as" \ + "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ + else \ + true; \ + fi; \ + fi; \ + done + if test "$(PACKAGE)" = "gettext"; then \ + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $(gettextsrcdir); \ + else \ + $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \ + fi; \ + $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ + $(gettextsrcdir)/Makefile.in.in; \ + else \ + : ; \ + fi + +# Define this as empty until I found a useful application. +installcheck: + +uninstall: + catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + done + rm -f $(gettextsrcdir)/po-Makefile.in.in + +check: all + +cat-id-tbl.o: ../intl/libgettext.h + +dvi info tags TAGS ID: + +mostlyclean: + rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp + rm -fr *.o + +clean: mostlyclean + +distclean: clean + rm -f Makefile Makefile.in POTFILES *.mo *.msg *.cat *.cat.m + +maintainer-clean: distclean + @echo "This command is intended for maintainers to use;" + @echo "it deletes files that may require special tools to rebuild." + rm -f $(GMOFILES) + +distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) +dist distdir: update-po $(DISTFILES) + dists="$(DISTFILES)"; \ + for file in $$dists; do \ + ln $(srcdir)/$$file $(distdir) 2> /dev/null \ + || cp -p $(srcdir)/$$file $(distdir); \ + done + +update-po: Makefile + $(MAKE) $(PACKAGE).pot + PATH=`pwd`/../src:$$PATH; \ + cd $(srcdir); \ + catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + mv $$lang.po $$lang.old.po; \ + echo "$$lang:"; \ + if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ + rm -f $$lang.old.po; \ + else \ + echo "msgmerge for $$cat failed!"; \ + rm -f $$lang.po; \ + mv $$lang.old.po $$lang.po; \ + fi; \ + done + +POTFILES: POTFILES.in + ( if test 'x$(srcdir)' != 'x.'; then \ + posrcprefix='$(top_srcdir)/'; \ + else \ + posrcprefix="../"; \ + fi; \ + rm -f $@-t $@ \ + && (sed -e '/^#/d' -e '/^[ ]*$$/d' \ + -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ + | sed -e '$$s/\\$$//') > $@-t \ + && chmod a-w $@-t \ + && mv $@-t $@ ) + +POTFILES.in: @MAINT@ ../Makefile + cd .. && $(MAKE) po/POTFILES.in + +Makefile: Make-in ../config.status POTFILES + cd .. \ + && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ + CONFIG_HEADERS= $(SHELL) ./config.status + +# Tell versions [3.59,3.63) of GNU make not to export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in new file mode 100644 index 0000000..0cb531b --- /dev/null +++ b/opcodes/po/POTFILES.in @@ -0,0 +1,119 @@ +a29k-dis.c +alpha-dis.c +alpha-opc.c +arc-dis.c +arc-ext.c +arc-opc.c +arm-dis.c +arm-opc.h +avr-dis.c +cgen-asm.c +cgen-dis.c +cgen-opc.c +cris-dis.c +cris-opc.c +d10v-dis.c +d10v-opc.c +d30v-dis.c +d30v-opc.c +dis-buf.c +disassemble.c +fr30-asm.c +fr30-desc.c +fr30-desc.h +fr30-dis.c +fr30-ibld.c +fr30-opc.c +fr30-opc.h +h8300-dis.c +h8500-dis.c +h8500-opc.h +hppa-dis.c +i370-dis.c +i370-opc.c +i386-dis.c +i860-dis.c +i960-dis.c +ia64-asmtab.c +ia64-asmtab.h +ia64-dis.c +ia64-gen.c +ia64-opc-a.c +ia64-opc-b.c +ia64-opc-d.c +ia64-opc-f.c +ia64-opc-i.c +ia64-opc-m.c +ia64-opc.c +ia64-opc.h +m10200-dis.c +m10200-opc.c +m10300-dis.c +m10300-opc.c +m32r-asm.c +m32r-desc.c +m32r-desc.h +m32r-dis.c +m32r-ibld.c +m32r-opc.c +m32r-opc.h +m32r-opinst.c +m68hc11-dis.c +m68hc11-opc.c +m68k-dis.c +m68k-opc.c +m88k-dis.c +mcore-dis.c +mcore-opc.h +mips-dis.c +mips-opc.c +mips16-opc.c +mmix-dis.c +mmix-opc.c +ns32k-dis.c +openrisc-asm.c +openrisc-desc.c +openrisc-desc.h +openrisc-dis.c +openrisc-ibld.c +openrisc-opc.c +openrisc-opc.h +or32-dis.c +or32-opc.c +pdp11-dis.c +pdp11-opc.c +pj-dis.c +pj-opc.c +ppc-dis.c +ppc-opc.c +s390-dis.c +s390-mkopc.c +s390-opc.c +sh-dis.c +sh-opc.h +sh64-dis.c +sh64-opc.c +sh64-opc.h +sparc-dis.c +sparc-opc.c +sysdep.h +tic30-dis.c +tic54x-dis.c +tic54x-opc.c +tic80-dis.c +tic80-opc.c +v850-dis.c +v850-opc.c +vax-dis.c +w65-dis.c +w65-opc.h +xstormy16-asm.c +xstormy16-desc.c +xstormy16-desc.h +xstormy16-dis.c +xstormy16-ibld.c +xstormy16-opc.c +xstormy16-opc.h +z8k-dis.c +z8k-opc.h +z8kgen.c diff --git a/opcodes/po/da.po b/opcodes/po/da.po new file mode 100644 index 0000000..674b505 --- /dev/null +++ b/opcodes/po/da.po @@ -0,0 +1,400 @@ +# Danish messages for opcodes. +# Copyright (C) 2001 Free Software Foundation, Inc. +# Keld Simonsen , 2002. +# Christian Rose , 2001. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12-pre020121\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" +"PO-Revision-Date: 2002-02-12 19:35+0200\n" +"Last-Translator: Keld Simonsen \n" +"Language-Team: Danish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=iso-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "operanden for betinget hop ligger på skæv adresse" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "hopperådet ligger på skæv adresse" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Ugyldig limm-reference i sidste instruktion!\n" + +#: arm-dis.c:509 +msgid "" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Ukendt registernavn er angivet: %s\n" + +#: arm-dis.c:1026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Ukendt disassembleralternativ: %s\n" + +#: arm-dis.c:1198 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n" +"sammen med flaget -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "udefineret" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Intern fejl i disassembleren" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "ukendt begrænsning \"%c\"" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operanden er uden for intervallet (%ld er ikke mellem %ld og %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operanden er uden for intervallet (%lu er ikke mellem %lu og %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Ukendt fejl %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adressen 0x%x ligger uden for tilladte grænser.\n" + +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Ukendt felt %d ved tolkning.\n" + +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "Mangler mnemonic i syntaksstreng" + +#. We couldn't parse it. +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 +#: m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 +#: openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +msgid "unrecognized instruction" +msgstr "ukendt instruktion" + +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaksfejl (tegnet \"%c\" forventedes, fandt \"%c\")" + +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaksfejl (tegnet \"%c\" forventedes, fandt slut på instruktion)" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +msgid "junk at end of line" +msgstr "snavs ved slutning på linjen" + +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "ukendt form af instruktion" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "fejlagtig instruktion \"%.50s...\"" + +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "fejlagtig instruktion \"%.50s\"" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +msgid "*unknown*" +msgstr "*ukendt*" + +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Ukendt felt %d ved udskrift af instruktion.\n" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operanden er uden for intervallet (%ld er ikke mellem %ld og %lu)" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operanden uden for intervallet (%lu ikke mellem 0 og %lu)" + +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Ukendt felt %d ved konstruktion af instruktion.\n" + +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Ukendt felt %d ved afkodning af instruktion.\n" + +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Ukendt felt %d ved hentning af heltalsoperand.\n" + +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Ukendt felt %d ved hentning af vma-operand.\n" + +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Ukendt felt %d ved indstilling af heltalsoperand.\n" + +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Ukendt felt %d ved indstilling af vma-operand.\n" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "Forstår ikke %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kan ikke indsætte %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*ukendt*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "ukendt\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "ukendt\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "ukendt\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# intern fejl, ukendt modifikator(%c)" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# intern disassembler-fejl, ukendt modifikator (%c)" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Fejlagtig 'case' %d (%s) i %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Internt: ikke-fejltestet kode (test-tilfælde mangler): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(ukendt)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*ukendt operandstype: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "ugyldigt betinget flag" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "forsøg på at sætte y-bitten når modifikatoren + eller - blev brugt" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "afsæt ikke et produkt af 4" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "afsæt ikke mellem -2048 og 2047" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "afsæt ikke mellem -8192 og 8191" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "ignorerer mindste betydende bit i afsæt for betinget hop" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "ugyldig bitmaske" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "værdien er uden for intervallet" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "indeksregistret er i indlæsningsintervallet" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "ugyldig registeroperand ved opdatering" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "ukendt" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "ukendt operandskiftning: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "ukendt pop-register: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "forskydningsværdien er ikke indenfor intervallet og ligger ikke på lige adresse" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "forskydningsværdien er uden for intervallet" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "forskydningsværdien ligger ikke på lige adresse" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "værdien for betinget hop er ikke inden for intervallet og til et ulige afsæt" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "værdien for betinget hop er uden for intervallet" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "betinget hop til ulige afsæt" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "værdien for betinget hop er ikke indenfor intervallet og til et ulige afsæt" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "ugyldigt register for stakjustering" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "umiddelbar værdi er ikke indenfor intervallet og ikke lige" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "umiddelbar værdi skal være lige" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "ukendt navn på nøgleord/register" diff --git a/opcodes/po/de.po b/opcodes/po/de.po new file mode 100644 index 0000000..6039e3e --- /dev/null +++ b/opcodes/po/de.po @@ -0,0 +1,391 @@ +# Katalog für opcodes. +# Copyright (C) 2002 Free Software Foundation, Inc. +# Martin v. Löwis , 2002. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12-pre020121\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" +"PO-Revision-Date: 2002-02-24 13:59+0100\n" +"Last-Translator: Martin v. Löwis \n" +"Language-Team: German \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "Sprung-Operand ist nicht ausgerichtet (unaligned)." + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "Sprunghinweis ist nicht ausgerichtet (unaligned)." + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Ungültige limm-Referenz in der letzten Anweisung!\n" + +#: arm-dis.c:509 +msgid "" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Unbekannte Registernamensmenge: %s\n" + +#: arm-dis.c:1026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Unbekannte Disassembler-Option: %s\n" + +#: arm-dis.c:1198 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "undefiniert" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Interner Disassemblerfehler." + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Unbekannter Fehler %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "" + +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "" + +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "" + +#. We couldn't parse it. +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +msgid "unrecognized instruction" +msgstr "" + +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "Syntaxfehler (erwartetes Zeichen »%c«, gefunden »%c«)" + +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +msgid "junk at end of line" +msgstr "" + +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "" + +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +msgid "*unknown*" +msgstr "" + +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "" + +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "" + +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "" + +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "" + +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "" + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "Der Direktoperand muss gerade sein." diff --git a/opcodes/po/es.po b/opcodes/po/es.po new file mode 100644 index 0000000..a423506 --- /dev/null +++ b/opcodes/po/es.po @@ -0,0 +1,399 @@ +# Mensajes en español para opcodes-2.12-pre020121 +# Copyright (C) 2002 Free Software Foundation, Inc. +# Cristian Othón Martínez Vera , 2002. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12-pre020121\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" +"PO-Revision-Date: 2002-01-24 08:55-0600\n" +"Last-Translator: Cristian Othón Martínez Vera \n" +"Language-Team: Spanish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "operando de ramificación sin alinear" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "pista de salto sin alinear" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "¡Referencia limm ilegal en la última instrucción!\n" + +#: arm-dis.c:509 +msgid "" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Conjunto de nombres de registro no reconocido: %s\n" + +#: arm-dis.c:1026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Opción de desensamblador no reconocida: %s\n" + +#: arm-dis.c:1198 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Las siguientes opciones de desensamblador específicas de ARM tienen soporte\n" +"para su uso con el interruptor -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "sin definir" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Error interno del desensamblador" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "restricción `%c' desconocida" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operando fuera de rango (%ld no está entre %ld y %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operando fuera de rango (%lu no está entre %lu y %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Error desconocido %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "La dirección 0x%x está fuera de los límites.\n" + +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "No se reconoció el campo %d durante la decodificación.\n" + +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "falta el mnemónico en la cadena sintáctica" + +#. We couldn't parse it. +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 +#: m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 +#: openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +msgid "unrecognized instruction" +msgstr "instrucción no reconocida" + +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "error sintáctico (se esperaba el carácter `%c', se encontró `%c')" + +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "error sintáctico (se esperaba el carácter `%c', se encontró el final de la instrucción)" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +msgid "junk at end of line" +msgstr "basura al final de la línea" + +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "forma de instrucción no reconocida" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instrucción errónea `%.50s...'" + +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instrucción errónea `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +msgid "*unknown*" +msgstr "*desconocida*" + +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "No se reconoció el campo %d al mostrar insn.\n" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operando fuera de rango (%ld no está entre %ld y %lu)" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operando fuera de rango (%lu no está entre 0 y %lu)" + +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "No se reconoció el campo %d al construir insn.\n" + +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "No se reconoció el campo %d al decodificar insn.\n" + +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "No se reconoció el campo %d al obtener el operando int.\n" + +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "No se reconoció el campo %d al obtener el operando vma.\n" + +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "No se reconoció el campo %d al establecer el operando int.\n" + +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "No se reconoció el campo %d al establecer el operando vma.\n" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "No se entiende %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "no se puede lidiar con insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*desconocido*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "desconocido\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "desconocido\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "desconocido\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# error interno, modificador(%c) sin definir" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# error interno del desensamblador, modificador (%c) no reconocido" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case %d erróneo (%s) en %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Interno: Código no depurado (falta el caso de prueba): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(desconocido)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tipo de operandos operandos desconocido: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "opción condicional inválida" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "intento de establecer el bit y cuando se usaba el modificador + ó -" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "el desplazamiento no es un múltiplo de 4" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "el desplazamiento no está entre -2048 y 2047" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "el desplazamiento no está entre -8192 y 8191" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "ignorando los bits menos significativos en el desplazamiento de la rama" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "máscara de bits ilegal" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "valor fuera de rango" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "registro índice en el rango de carga" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "operando de registro inválido mientras se actualizaba" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "desconocida" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Error interno: sparc-opcode.h erróneo: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "operando de desplazamiento desconocido: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "registro pop desconocido: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "el valor de desubicación no está en el rango y no está alineado" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "el valor de desubicación está fuera de rango" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "el valor de desubicación no está alineado" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "el valor inmediato está fuera de rango" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "el valor de ramificación no está en rango e indica un desplazamiento impar" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "el valor de ramificación está fuera de rango" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "ramificación a un desplazamiento impar" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "el valor de ramificación no está en rango e indica un desplazamiento impar" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "registro inválido para el ajuste de la pila" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "el valor inmediato no está en rango y no es par" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "el valor inmediato debe ser par" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "nombre clave/de registro no reconocido" diff --git a/opcodes/po/fr.po b/opcodes/po/fr.po new file mode 100644 index 0000000..e1806b0 --- /dev/null +++ b/opcodes/po/fr.po @@ -0,0 +1,398 @@ +# Messages français pour opcodes. +# Copyright (C) 1996 Free Software Foundation, Inc. +# Michel Robitaille , 1996. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12-pre020121\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" +"PO-Revision-Date: 2002-03-17 20:00-0500\n" +"Last-Translator: Michel Robitaille \n" +"Language-Team: French \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "opérande de branchement non alignée" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "saut indicé non aligné" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Référence limite illégale dans la dernière instruction!\n" + +#: arm-dis.c:509 +msgid "" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Nom de jeu de registres inconnu: %s\n" + +#: arm-dis.c:1026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Option du désassembleur non reconnue: %s\n" + +#: arm-dis.c:1198 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Les options spécifiques ARM suivantes sont supportées avec l'utilisation de\n" +"l'option -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "non défini" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Erreur interne du désassembleur" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "contrainte inconnue « %c »" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "opérande hors gamme (%ld n'est pas entre %ld et %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "opérande hors gamme (%lu n'est pas entre %lu et %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Erreur inconnue %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adresse 0x%x est hors gamme.\n" + +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Champ non reconnu %d lors de l'analyse.\n" + +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "mnémonique manquante dans la syntaxe de la chaîne" + +#. We couldn't parse it. +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +msgid "unrecognized instruction" +msgstr "instruction non reconnue" + +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "erreur de syntaxe (caractère « %c » attendu, « %c » obtenu)" + +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "erreur de syntaxe (caractère « %c » attendu, fin de l'instruction obtenue)" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +msgid "junk at end of line" +msgstr "rebut à la fin de la ligne" + +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "forme d'instruction non reconnue" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instruction erronée « %.50s... »" + +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instruction erronée « %.50s »" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +msgid "*unknown*" +msgstr "*inconnu*" + +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Champ non reconnu %d lors de l'impression insn.\n" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "opérande hors gamme (%ld n'est pas entre %ld et %lu)" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "opérande hors gamme (%lu n'est pas entre 0 et %lu)" + +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Champ non reconnu %d lors de la construction de insn.\n" + +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Champ non reconnu %d lors du décodage de insn.\n" + +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Champ non reconnu %d lors de la prise d'une opérande int.\n" + +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Champ non reconnu %d lors de la prise d'une opérande vma.\n" + +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande int.\n" + +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande vma.\n" + +# h8300-dis.c:380Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "Hummm %x" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "Ne comprend pas %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "Ne peut gérer l'insertion %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*inconnu*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "inconnu\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "inconnu\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "inconnu\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# erreur interne, modificateur non défini(%c)" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# erreur interne du déssassembleur, modificateur non reconnu(%c)" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case erroné %d (%s) dans %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Interne: code qui n'est pas au point (case de test manquant): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(inconnu)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*type d'opérande inconnue: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "option conditionnelle invalide" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "tentative d'initialisation du bit y lorsque le modificateur + ou - a été utilisé" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "décalage n'est pas un multiple de 4" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "décalage n'est pas entre -2048 et 2047" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "décalage n'est pas entre -8192 et 8191" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "Les derniers bits les moins significatifs sont ignorés dans le décalage de branchement" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "masque de bits illégal" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "valeur hors gamme" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "registre index n'est pas dans la plage de chargement" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "opérande registre invalide lors de la mise à jour" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "inconnu" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erreur interne: sparc-opcode.h erroné: « %s », %#.8lx, %#.8lx\n" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erreur interne: sparc-opcode.h erroné: « %s », %#.8lx, %#.8lx\n" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Erreur interne: sparc-opcode.h erroné: « %s » == « %s »\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "décalage d'opérande inconnu: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "registre de pile inconnu: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "La valeur de déplacement est hors gamme et n'est pas alignée." + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "La valeur de déplacement est hors gamme." + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "La valeur de déplacement n'est pas alignée." + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "La valeur immédiate est hors gamme." + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "Valeur de branchement est hors gamme et a un décalage impair." + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "Valeur de branchement hors gamme." + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "Branchement avec un décalage impair." + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "Valeur de branchement est hors gamme et a un décalage impair" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "registre invalide pour un ajustement de la pile" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "La valeur immédiate est hors gamme et est impaire." + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "La valeur immédiate doit être paire." + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "nom de mot clé ou de registre non reconnu" diff --git a/opcodes/po/id.po b/opcodes/po/id.po new file mode 100644 index 0000000..3c69b4b --- /dev/null +++ b/opcodes/po/id.po @@ -0,0 +1,395 @@ +# opcodes 2.12-pre020121 (Indonesian) +# Copyright (C) 2002 Free Software Foundation, Inc. +# Tedi Heriyanto , 2002. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12-pre020121\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" +"PO-Revision-Date: 2002-04-02 08:20GMT+0700\n" +"Last-Translator: Tedi Heriyanto \n" +"Language-Team: Indonesian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Generator: KBabel 0.9.5\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "operand cabang tidak rata" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "petunjuk lompat tidak rata" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "referensi limm ilegal dalam instruksi terakhir!\n" + +#: arm-dis.c:509 +msgid "" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Set nama register tidak dikenal: %s\n" + +#: arm-dis.c:1026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Option disasembler tidak dikenal: %s\n" + +#: arm-dis.c:1198 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Option disablembler khusus ARM berikut ini didukung untuk digunakan dengan\n" +"switch -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "tidak didefinisikan" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Kesalahan disasembler internal" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "konstrain tidak dikenal `%c'" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operand keluar batas (%ld tidak antara %ld dan %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operand keluar batas (%lu tidak antara %lu dan %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Kesalahan tidak dikenal %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Alamat 0x%x di luar batas.\n" + +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Field tidak dikenal %d saat parsing.\n" + +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "mnemonik hilang dalam string sintaks" + +#. We couldn't parse it. +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +msgid "unrecognized instruction" +msgstr "instruksti tidak dikenal" + +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan `%c')" + +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan akhir instruksi)" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +msgid "junk at end of line" +msgstr "sampah di akhir baris" + +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "bentuk instruksi tidak dikenal" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instruksi buruk `%.50s...'" + +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instruksi buruk `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +msgid "*unknown*" +msgstr "*tidak dikenal*" + +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Field tidak dikenal %d saat mencetak insn.\n" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operand di luar batas (%ld tidak antara %ld dan %lu)" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operand di luar batas (%lu tidak antara 0 dan %lu)" + +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Field tidak dikenal %d saat membuild insn.\n" + +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Field tidak dikenal %d saat mendekode insn.\n" + +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Field tidak dikenal %d saat memperoleh operand int.\n" + +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Field tidak dikenal %d saat memperoleh operand vma.\n" + +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Field tidak dikenal %d saat menset operand int.\n" + +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Field tidak dikenal %d saat menset operand vma.\n" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "Tidak mengerti %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "tidak dapat menangani insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*tidak dikenal*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "tidak dikenal\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "tidak dikenal\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "tidak dikenal\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# kesalahan internal, modifier tidak didefinisikan(%c)" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# kesalahan internal disasembler, modifier tidak dikenal (%c)" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case buruk %d (%s) dalam %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Internal: Kode belum didebug (tidak ada test-case): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(tidak dikenal)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tipe operand tidak dikenal: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "option kondisional tidak valid" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "berusaha menset bit y saat menggunakan modifier + atau -" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "offset bukan kelipatan 4" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "offset tidak berada antara -2048 dan 2047" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "offset tidak berada antara -8192 dan 8191" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "mengabaikan least significant bit dalam offset cabang" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "bitmask ilegal" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "nilai di luar batas" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "register indeks dalam daerah pemuatan" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "operand register tidak valid saat mengupdate" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "tidak dikenal" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "shift operand tidak dikenal: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "reg pop tidak dikenal: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "nilai displacement tidak dalam jangkauan dan tidak rata" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "nilai displacement di luar batas" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "nilai displacement tidak rata" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "nilai langsung di luar batas" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "nilai cabang tidak dalam jangkauan" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "nilai cabang di luar jangkauan" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "cabang offset ganjil" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "nilai cabang di luar jangkauan dan offset ganjil" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "register tidak valid untuk penyesuaian stack" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "nilai langsung tidak dalam jangkauan dan tidak genap" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "nilai langsung harus genap" diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot new file mode 100644 index 0000000..fbc549d --- /dev/null +++ b/opcodes/po/opcodes.pot @@ -0,0 +1,427 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR Free Software Foundation, Inc. +# FIRST AUTHOR , YEAR. +# +#, fuzzy +msgid "" +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"POT-Creation-Date: 2002-02-08 03:24-0200\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=CHARSET\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "" + +#: arm-dis.c:502 +msgid "" +msgstr "" + +#: arm-dis.c:1012 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "" + +#: arm-dis.c:1191 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#: xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "" + +#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "" + +#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281 +msgid "missing mnemonic in syntax string" +msgstr "" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511 +#: m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 +#: openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623 +#: xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508 +#: xstormy16-asm.c:610 +msgid "unrecognized instruction" +msgstr "" + +#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "" + +#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "" + +#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502 +msgid "junk at end of line" +msgstr "" + +#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609 +msgid "unrecognized form of instruction" +msgstr "" + +#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "" + +#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 +msgid "*unknown*" +msgstr "" + +#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "" + +#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "" + +#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "" + +#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "" + +#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "" + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "" + +#. Mark as non-valid instruction +#: sparc-dis.c:750 +msgid "unknown" +msgstr "" + +#: sparc-dis.c:825 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "" + +#: sparc-dis.c:836 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "" + +#: sparc-dis.c:885 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "" + +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "" + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "" diff --git a/opcodes/po/sv.po b/opcodes/po/sv.po new file mode 100644 index 0000000..a6eda07 --- /dev/null +++ b/opcodes/po/sv.po @@ -0,0 +1,438 @@ +# Swedish messages for opcodes. +# Copyright (C) 2001 Free Software Foundation, Inc. +# Christian Rose , 2001. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.11\n" +"POT-Creation-Date: 2002-01-31 17:10+0000\n" +"PO-Revision-Date: 2001-10-23 15:35+0200\n" +"Last-Translator: Christian Rose \n" +"Language-Team: Swedish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=iso-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "grenoperanden ligger inte på jämn gräns" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "hopptipset ligger inte på jämn gräns" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Otillåten limm-referens i sista instruktionen!\n" + +#: arm-dis.c:502 +msgid "" +msgstr "" + +#: arm-dis.c:1012 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Okänt registernamn är angivet: %s\n" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Okänt disassembleralternativ: %s\n" + +#: arm-dis.c:1191 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Följande ARM-specifika disassembleralternativ stöds för användning\n" +"tillsammans med flaggan -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "odefinierad" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Internt fel i disassembleraren" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "okänd begränsning \"%c\"" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#: xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operanden är utanför intervallet (%lu är inte mellan %lu och %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Okänt fel %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adressen 0x%x ligger utanför tillåtna gränser.\n" + +#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Okänt fält %d vid tolkning.\n" + +#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281 +msgid "missing mnemonic in syntax string" +msgstr "" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511 +#: m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 +#: openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623 +#: xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508 +#: xstormy16-asm.c:610 +msgid "unrecognized instruction" +msgstr "okänd instruktion" + +#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade \"%c\")" + +#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474 +#, fuzzy, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade \"%c\")" + +#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502 +msgid "junk at end of line" +msgstr "skräp vid slutet på raden" + +#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609 +#, fuzzy +msgid "unrecognized form of instruction" +msgstr "okänd instruktion" + +#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "felaktig instruktion \"%.50s...\"" + +#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "felaktig instruktion \"%.50s\"" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 +msgid "*unknown*" +msgstr "*okänd*" + +#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Okänt fält %d vid utskrift av instruktion.\n" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, fuzzy, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %ld)" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operanden utanför intervallet (%lu inte mellan 0 och %lu)" + +#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Okänt fält %d vid konstruktion av instruktion.\n" + +#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Okänt fält %d vid avkodning av instruktion.\n" + +#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Okänt fält %d vid hämtning av heltalsoperand.\n" + +#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Okänt fält %d vid hämtning av vma-operand.\n" + +#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Okänt fält %d vid inställning av heltalsoperand.\n" + +#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Okänt fält %d vid inställning av vma-operand.\n" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "Förstår inte %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kan inte sätta in %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*okänd*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "okänd\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "okänd\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "okänd\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# internt fel, okänd modifierare(%c)" + +#: mips-dis.c:1154 +#, fuzzy, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# internt fel, okänd modifierare(%c)" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "" + +#: mmix-dis.c:53 +#, fuzzy +msgid "(unknown)" +msgstr "okänd" + +#: mmix-dis.c:517 +#, fuzzy, c-format +msgid "*unknown operands type: %d*" +msgstr "okänt operandskifte: %x\n" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "ogiltig villkorlig flagga" + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "försök att ställa in y-biten då modifieraren + eller - användes" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "ignorerar minst signifikanta bitarna i grenavstånd" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "otillåten bitmask" + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "värdet är utanför intervallet" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "indexregistret är i inläsningsintervallet" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "ogiltig registeroperand vid uppdatering" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "okänd" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "okänt operandskifte: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "okänt pop-register: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "" +"förskjutningsvärdet är inte inom intervallet och ligger inte på jämn gräns" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "förskjutningsvärdet är utanför intervallet" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "förskjutningsvärdet ligger inte på jämn gräns" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "omedelbara värdet är utanför intervallet" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "grenvärdet är inte inom intervallet och till ett udda avstånd" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "grenvärdet är utanför intervallet" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "grening till udda avstånd" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "grenvärdet är inte inom intervallet och till ett udda avstånd" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "ogiltigt register för stackjustering" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "omedelbara värdet är inte inom intervallet och inte jämnt" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "omedelbara värdet måste vara jämnt" + +#: xstormy16-asm.c:74 +#, fuzzy +msgid "Bad register in preincrement" +msgstr "indexregistret är i inläsningsintervallet" + +#: xstormy16-asm.c:79 +#, fuzzy +msgid "Bad register in postincrement" +msgstr "ogiltigt register för stackjustering" + +#: xstormy16-asm.c:81 +#, fuzzy +msgid "Bad register name" +msgstr "indexregistret är i inläsningsintervallet" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "okänt namn på nyckelord/register" diff --git a/opcodes/po/tr.po b/opcodes/po/tr.po new file mode 100644 index 0000000..e776662 --- /dev/null +++ b/opcodes/po/tr.po @@ -0,0 +1,397 @@ +# Binutils Opcode Turkish Translation +# Copyright (C) 2001 Free Software Foundation, Inc. +# Deniz Akkus Kanca , 2001. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12-pre020121\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" +"PO-Revision-Date: 2002-02-17 11:26EET\n" +"Last-Translator: Deniz Akkus Kanca \n" +"Language-Team: Turkish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Generator: KBabel 0.9.5\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "dal iÅŸleneni hizalı deÄŸil" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "atlama iÅŸareti hizalı deÄŸil" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Son iÅŸlemde geçersiz limm referansı!\n" + +#: arm-dis.c:509 +msgid "" +msgstr "" + +#: arm-dis.c:1019 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Bilinmeyen yazmaç ad kümesi: %s\n" + +#: arm-dis.c:1026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Bilinmeyen karşıt-çevirici seçeneÄŸi: %s\n" + +#: arm-dis.c:1198 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"AÅŸağıdaki ARM'a özgü karşıt-çevirici seçenekleri \n" +"-M seçeneÄŸi ile kullanılabilir:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "tanımlanmamış" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "İç karşıt-çevirici hatası " + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "`%c' bilinmeyen kısıtı" + +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "Kapsam dışı terim (%ld, %ld ve %ld arasında deÄŸil) " + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "Kapsam dışı terim (%lu, %lu ve %lu arasında deÄŸil)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Bilinmeyen hata %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "0x%x adresi sınırların dışında.\n" + +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Ayrıştırma esnasında bilinmeyen alan %d bulundu.\n" + +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "biçem dizgesinde ipucu eksik" + +#. We couldn't parse it. +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 +#: m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 +#: openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +msgid "unrecognized instruction" +msgstr "bilinmeyen iÅŸlem" + +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "biçem hatası (char `%c' beklenirken `%c' bulundu)" + +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "biçem hatası (char `%c' beklenirken iÅŸlem sonu bulundu)" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +msgid "junk at end of line" +msgstr "Satır sonu bozuk " + +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "bilinmeyen iÅŸlem türü" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "geçersiz iÅŸlem `%.50s...'" + +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "geçersiz iÅŸlem `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +msgid "*unknown*" +msgstr "*bilinmeyen*" + +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "yönerge yazdırılırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "Kapsam dışı iÅŸlenen (%ld, %ld ve %lu arasında deÄŸil) " + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "kapsam dışı terim (%lu 0 ve %lu arasında deÄŸil) " + +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Yönerge oluÅŸturulurken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Yönerge çözümlenirken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "`int' terimi alınırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "`vma' terimi alınırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "`int' terimi atanırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "`vma' terimi atanırken bilinmeyen alan %d bulundu.\n" + +#: h8300-dis.c:384 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:395 +#, c-format +msgid "Don't understand %x \n" +msgstr "%x anlaşılamadı\n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "insert %d yaptırılamıyor\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*bilinmeyen*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "bilinmeyen\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "bilinmeyen\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "bilinmeyen\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# <`dis' hatası: %08x>" + +#: mips-dis.c:290 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "#iç hata, tanımlanmamış deÄŸiÅŸtirici (%c)" + +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "#iç karşıt-çevirici hatası, tanımlanmamış deÄŸiÅŸtirici (%c)" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Hatalı durum %d (%s), %s içerisinde:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "İç Hata: Hata ayıklanmamış kod (test eksik): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(bilinmeyen)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "bilinmeyen iÅŸlenen türü: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:765 ppc-opc.c:798 +msgid "invalid conditional option" +msgstr "koÅŸullu seçenek geçersiz " + +#: ppc-opc.c:800 +msgid "attempt to set y bit when using + or - modifier" +msgstr "+ veya - deÄŸiÅŸtiricisini kullanırken y bitini atama denemesi" + +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "görece 4'ün katı deÄŸil" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "görece -2048 ve 2047 arasında deÄŸil" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "görece -8192 ve 8191 arasında deÄŸil" + +#: ppc-opc.c:910 +msgid "ignoring least significant bits in branch offset" +msgstr "Dal göreli konumunda en önemsiz bitler atlanıyor" + +#: ppc-opc.c:944 ppc-opc.c:981 +msgid "illegal bitmask" +msgstr "geçersiz bitmask " + +#: ppc-opc.c:1054 +msgid "value out of range" +msgstr "deÄŸer aralık dışı" + +#: ppc-opc.c:1130 +msgid "index register in load range" +msgstr "yükleme aralığında endeks yazmacı" + +#: ppc-opc.c:1146 +msgid "invalid register operand when updating" +msgstr "güncelleme esnasında geçersiz yazmaç terimi bulundu" + +#. Mark as non-valid instruction +#: sparc-dis.c:749 +msgid "unknown" +msgstr "bilinmeyen" + +#: sparc-dis.c:824 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:884 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "bilinmeyen terim kaydırması: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "bilinmeyen çek yazmacı: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "yer deÄŸiÅŸtirme deÄŸeri kapsam dışında ve hizalanmamış" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "yer deÄŸiÅŸtirme deÄŸeri kapsam dışında" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "yer deÄŸiÅŸtirme deÄŸeri hizalanmamış" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "ÅŸimdiki deÄŸer kapsam dışı" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "dal deÄŸeri kapsam dışında ve tek sayılı göreli konuma iÅŸaret ediyor" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "dal deÄŸeri kapsam dışında " + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "dallanma tek sayılı göreli konuma iÅŸaret ediyor" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "dal deÄŸeri kapsam dışında ve tek sayılı göreli konuma iÅŸaret ediyor" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "yığıt düzeltmesi için geçersiz yazmaç " + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "ÅŸimdiki deÄŸer kapsam dışı ve çift sayı deÄŸil" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "ÅŸimdiki deÄŸer çift sayı olmalı" diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c new file mode 100644 index 0000000..0ac8275 --- /dev/null +++ b/opcodes/ppc-dis.c @@ -0,0 +1,273 @@ +/* ppc-dis.c -- Disassemble PowerPC instructions + Copyright 1994, 1995, 2000, 2001, 2002 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/ppc.h" + +/* This file provides several disassembler functions, all of which use + the disassembler interface defined in dis-asm.h. Several functions + are provided because this file handles disassembly for the PowerPC + in both big and little endian mode and also for the POWER (RS/6000) + chip. */ + +static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *, + int bigendian, int dialect)); + +static int powerpc_dialect PARAMS ((struct disassemble_info *)); + +/* Determine which set of machines to disassemble for. PPC403/601 or + BookE. For convenience, also disassemble instructions supported + by the AltiVec vector unit. */ + +int +powerpc_dialect(info) + struct disassemble_info *info; +{ + int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC; + + if (BFD_DEFAULT_TARGET_SIZE == 64) + dialect |= PPC_OPCODE_64; + + if (info->disassembler_options + && (strcmp (info->disassembler_options, "booke") == 0 + || strcmp (info->disassembler_options, "booke32") == 0 + || strcmp (info->disassembler_options, "booke64") == 0)) + dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; + else + dialect |= PPC_OPCODE_403 | PPC_OPCODE_601; + + if (info->disassembler_options + && strcmp (info->disassembler_options, "power4") == 0) + dialect |= PPC_OPCODE_POWER4; + + if (info->disassembler_options) + { + if (strstr (info->disassembler_options, "32") != NULL) + dialect &= ~PPC_OPCODE_64; + else if (strstr (info->disassembler_options, "64") != NULL) + dialect |= PPC_OPCODE_64; + } + + return dialect; +} + +/* Print a big endian PowerPC instruction. */ + +int +print_insn_big_powerpc (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info)); +} + +/* Print a little endian PowerPC instruction. */ + +int +print_insn_little_powerpc (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info)); +} + +/* Print a POWER (RS/6000) instruction. */ + +int +print_insn_rs6000 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); +} + +/* Print a PowerPC or POWER instruction. */ + +static int +print_insn_powerpc (memaddr, info, bigendian, dialect) + bfd_vma memaddr; + struct disassemble_info *info; + int bigendian; + int dialect; +{ + bfd_byte buffer[4]; + int status; + unsigned long insn; + const struct powerpc_opcode *opcode; + const struct powerpc_opcode *opcode_end; + unsigned long op; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (bigendian) + insn = bfd_getb32 (buffer); + else + insn = bfd_getl32 (buffer); + + /* Get the major opcode of the instruction. */ + op = PPC_OP (insn); + + /* Find the first match in the opcode table. We could speed this up + a bit by doing a binary search on the major opcode. */ + opcode_end = powerpc_opcodes + powerpc_num_opcodes; + for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) + { + unsigned long table_op; + const unsigned char *opindex; + const struct powerpc_operand *operand; + int invalid; + int need_comma; + int need_paren; + + table_op = PPC_OP (opcode->opcode); + if (op < table_op) + break; + if (op > table_op) + continue; + + if ((insn & opcode->mask) != opcode->opcode + || (opcode->flags & dialect) == 0) + continue; + + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = powerpc_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, dialect, &invalid); + } + if (invalid) + continue; + + /* The instruction is valid. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + + /* Now extract and print the operands. */ + need_comma = 0; + need_paren = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + long value; + + operand = powerpc_operands + *opindex; + + /* Operands that are marked FAKE are simply ignored. We + already made sure that the extract function considered + the instruction to be valid. */ + if ((operand->flags & PPC_OPERAND_FAKE) != 0) + continue; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, dialect, (int *) NULL); + else + { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & PPC_OPERAND_SIGNED) != 0 + && (value & (1 << (operand->bits - 1))) != 0) + value -= 1 << operand->bits; + } + + /* If the operand is optional, and the value is zero, don't + print anything. */ + if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 + && (operand->flags & PPC_OPERAND_NEXT) == 0 + && value == 0) + continue; + + if (need_comma) + { + (*info->fprintf_func) (info->stream, ","); + need_comma = 0; + } + + /* Print the operand as directed by the flags. */ + if ((operand->flags & PPC_OPERAND_GPR) != 0) + (*info->fprintf_func) (info->stream, "r%ld", value); + else if ((operand->flags & PPC_OPERAND_FPR) != 0) + (*info->fprintf_func) (info->stream, "f%ld", value); + else if ((operand->flags & PPC_OPERAND_VR) != 0) + (*info->fprintf_func) (info->stream, "v%ld", value); + else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) + (*info->print_address_func) (memaddr + value, info); + else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) + (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); + else if ((operand->flags & PPC_OPERAND_CR) == 0 + || (dialect & PPC_OPCODE_PPC) == 0) + (*info->fprintf_func) (info->stream, "%ld", value); + else + { + if (operand->bits == 3) + (*info->fprintf_func) (info->stream, "cr%d", value); + else + { + static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; + int cr; + int cc; + + cr = value >> 2; + if (cr != 0) + (*info->fprintf_func) (info->stream, "4*cr%d", cr); + cc = value & 3; + if (cc != 0) + { + if (cr != 0) + (*info->fprintf_func) (info->stream, "+"); + (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); + } + } + } + + if (need_paren) + { + (*info->fprintf_func) (info->stream, ")"); + need_paren = 0; + } + + if ((operand->flags & PPC_OPERAND_PARENS) == 0) + need_comma = 1; + else + { + (*info->fprintf_func) (info->stream, "("); + need_paren = 1; + } + } + + /* We have found and printed an instruction; return. */ + return 4; + } + + /* We could not find a match. */ + (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); + + return 4; +} diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c new file mode 100644 index 0000000..70167f7 --- /dev/null +++ b/opcodes/ppc-opc.c @@ -0,0 +1,4066 @@ +/* ppc-opc.c -- PowerPC opcode list + Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002 + Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/ppc.h" +#include "opintl.h" + +/* This file holds the PowerPC opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* Local insertion and extraction functions. */ + +static unsigned long insert_bat + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bat + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bba + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bba + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bd + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bd + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bdm + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bdm + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bdp + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bdp + PARAMS ((unsigned long, int, int *)); +static int valid_bo + PARAMS ((long, int)); +static unsigned long insert_bo + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bo + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_boe + PARAMS ((unsigned long, long, int, const char **)); +static long extract_boe + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ds + PARAMS ((unsigned long, long, int, const char **)); +static long extract_ds + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_de + PARAMS ((unsigned long, long, int, const char **)); +static long extract_de + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_des + PARAMS ((unsigned long, long, int, const char **)); +static long extract_des + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_li + PARAMS ((unsigned long, long, int, const char **)); +static long extract_li + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_mbe + PARAMS ((unsigned long, long, int, const char **)); +static long extract_mbe + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_mb6 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_mb6 + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_nb + PARAMS ((unsigned long, long, int, const char **)); +static long extract_nb + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_nsi + PARAMS ((unsigned long, long, int, const char **)); +static long extract_nsi + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ral + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_ram + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_ras + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_rbs + PARAMS ((unsigned long, long, int, const char **)); +static long extract_rbs + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_sh6 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_sh6 + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_spr + PARAMS ((unsigned long, long, int, const char **)); +static long extract_spr + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_tbr + PARAMS ((unsigned long, long, int, const char **)); +static long extract_tbr + PARAMS ((unsigned long, int, int *)); + +/* The operands table. + + The fields are bits, shift, insert, extract, flags. + + We used to put parens around the various additions, like the one + for BA just below. However, that caused trouble with feeble + compilers with a limit on depth of a parenthesized expression, like + (reportedly) the compiler in Microsoft Developer Studio 5. So we + omit the parens, since the macros are never used in a context where + the addition will be ambiguous. */ + +const struct powerpc_operand powerpc_operands[] = +{ + /* The zero index is used to indicate the end of the list of + operands. */ +#define UNUSED 0 + { 0, 0, 0, 0, 0 }, + + /* The BA field in an XL form instruction. */ +#define BA UNUSED + 1 +#define BA_MASK (0x1f << 16) + { 5, 16, 0, 0, PPC_OPERAND_CR }, + + /* The BA field in an XL form instruction when it must be the same + as the BT field in the same instruction. */ +#define BAT BA + 1 + { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, + + /* The BB field in an XL form instruction. */ +#define BB BAT + 1 +#define BB_MASK (0x1f << 11) + { 5, 11, 0, 0, PPC_OPERAND_CR }, + + /* The BB field in an XL form instruction when it must be the same + as the BA field in the same instruction. */ +#define BBA BB + 1 + { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, + + /* The BD field in a B form instruction. The lower two bits are + forced to zero. */ +#define BD BBA + 1 + { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when absolute addressing is + used. */ +#define BDA BD + 1 + { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the - modifier is used. + This sets the y bit of the BO field appropriately. */ +#define BDM BDA + 1 + { 16, 0, insert_bdm, extract_bdm, + PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the - modifier is used + and absolute address is used. */ +#define BDMA BDM + 1 + { 16, 0, insert_bdm, extract_bdm, + PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the + modifier is used. + This sets the y bit of the BO field appropriately. */ +#define BDP BDMA + 1 + { 16, 0, insert_bdp, extract_bdp, + PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the + modifier is used + and absolute addressing is used. */ +#define BDPA BDP + 1 + { 16, 0, insert_bdp, extract_bdp, + PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BF field in an X or XL form instruction. */ +#define BF BDPA + 1 + { 3, 23, 0, 0, PPC_OPERAND_CR }, + + /* An optional BF field. This is used for comparison instructions, + in which an omitted BF field is taken as zero. */ +#define OBF BF + 1 + { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + + /* The BFA field in an X or XL form instruction. */ +#define BFA OBF + 1 + { 3, 18, 0, 0, PPC_OPERAND_CR }, + + /* The BI field in a B form or XL form instruction. */ +#define BI BFA + 1 +#define BI_MASK (0x1f << 16) + { 5, 16, 0, 0, PPC_OPERAND_CR }, + + /* The BO field in a B form instruction. Certain values are + illegal. */ +#define BO BI + 1 +#define BO_MASK (0x1f << 21) + { 5, 21, insert_bo, extract_bo, 0 }, + + /* The BO field in a B form instruction when the + or - modifier is + used. This is like the BO field, but it must be even. */ +#define BOE BO + 1 + { 5, 21, insert_boe, extract_boe, 0 }, + + /* The BT field in an X or XL form instruction. */ +#define BT BOE + 1 + { 5, 21, 0, 0, PPC_OPERAND_CR }, + + /* The condition register number portion of the BI field in a B form + or XL form instruction. This is used for the extended + conditional branch mnemonics, which set the lower two bits of the + BI field. This field is optional. */ +#define CR BT + 1 + { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + + /* The CT field in an X form instruction. */ +#define CT CR + 1 + { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, + + /* The D field in a D form instruction. This is a displacement off + a register, and implies that the next operand is a register in + parentheses. */ +#define D CT + 1 + { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The DE field in a DE form instruction. This is like D, but is 12 + bits only. */ +#define DE D + 1 + { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, + + /* The DES field in a DES form instruction. This is like DS, but is 14 + bits only (12 stored.) */ +#define DES DE + 1 + { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The DS field in a DS form instruction. This is like D, but the + lower two bits are forced to zero. */ +#define DS DES + 1 + { 16, 0, insert_ds, extract_ds, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, + + /* The E field in a wrteei instruction. */ +#define E DS + 1 + { 1, 15, 0, 0, 0 }, + + /* The FL1 field in a POWER SC form instruction. */ +#define FL1 E + 1 + { 4, 12, 0, 0, 0 }, + + /* The FL2 field in a POWER SC form instruction. */ +#define FL2 FL1 + 1 + { 3, 2, 0, 0, 0 }, + + /* The FLM field in an XFL form instruction. */ +#define FLM FL2 + 1 + { 8, 17, 0, 0, 0 }, + + /* The FRA field in an X or A form instruction. */ +#define FRA FLM + 1 +#define FRA_MASK (0x1f << 16) + { 5, 16, 0, 0, PPC_OPERAND_FPR }, + + /* The FRB field in an X or A form instruction. */ +#define FRB FRA + 1 +#define FRB_MASK (0x1f << 11) + { 5, 11, 0, 0, PPC_OPERAND_FPR }, + + /* The FRC field in an A form instruction. */ +#define FRC FRB + 1 +#define FRC_MASK (0x1f << 6) + { 5, 6, 0, 0, PPC_OPERAND_FPR }, + + /* The FRS field in an X form instruction or the FRT field in a D, X + or A form instruction. */ +#define FRS FRC + 1 +#define FRT FRS + { 5, 21, 0, 0, PPC_OPERAND_FPR }, + + /* The FXM field in an XFX instruction. */ +#define FXM FRS + 1 +#define FXM_MASK (0xff << 12) + { 8, 12, 0, 0, 0 }, + + /* The L field in a D or X form instruction. */ +#define L FXM + 1 + { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, + + /* The LEV field in a POWER SC form instruction. */ +#define LEV L + 1 + { 7, 5, 0, 0, 0 }, + + /* The LI field in an I form instruction. The lower two bits are + forced to zero. */ +#define LI LEV + 1 + { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The LI field in an I form instruction when used as an absolute + address. */ +#define LIA LI + 1 + { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The LS field in an X (sync) form instruction. */ +#define LS LIA + 1 + { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL }, + + /* The MB field in an M form instruction. */ +#define MB LS + 1 +#define MB_MASK (0x1f << 6) + { 5, 6, 0, 0, 0 }, + + /* The ME field in an M form instruction. */ +#define ME MB + 1 +#define ME_MASK (0x1f << 1) + { 5, 1, 0, 0, 0 }, + + /* The MB and ME fields in an M form instruction expressed a single + operand which is a bitmask indicating which bits to select. This + is a two operand form using PPC_OPERAND_NEXT. See the + description in opcode/ppc.h for what this means. */ +#define MBE ME + 1 + { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, + { 32, 0, insert_mbe, extract_mbe, 0 }, + + /* The MB or ME field in an MD or MDS form instruction. The high + bit is wrapped to the low end. */ +#define MB6 MBE + 2 +#define ME6 MB6 +#define MB6_MASK (0x3f << 5) + { 6, 5, insert_mb6, extract_mb6, 0 }, + + /* The MO field in an mbar instruction. */ +#define MO MB6 + 1 + { 5, 21, 0, 0, 0 }, + + /* The NB field in an X form instruction. The value 32 is stored as + 0. */ +#define NB MO + 1 + { 6, 11, insert_nb, extract_nb, 0 }, + + /* The NSI field in a D form instruction. This is the same as the + SI field, only negated. */ +#define NSI NB + 1 + { 16, 0, insert_nsi, extract_nsi, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + + /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ +#define RA NSI + 1 +#define RA_MASK (0x1f << 16) + { 5, 16, 0, 0, PPC_OPERAND_GPR }, + + /* The RA field in a D or X form instruction which is an updating + load, which means that the RA field may not be zero and may not + equal the RT field. */ +#define RAL RA + 1 + { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, + + /* The RA field in an lmw instruction, which has special value + restrictions. */ +#define RAM RAL + 1 + { 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, + + /* The RA field in a D or X form instruction which is an updating + store or an updating floating point load, which means that the RA + field may not be zero. */ +#define RAS RAM + 1 + { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, + + /* The RB field in an X, XO, M, or MDS form instruction. */ +#define RB RAS + 1 +#define RB_MASK (0x1f << 11) + { 5, 11, 0, 0, PPC_OPERAND_GPR }, + + /* The RB field in an X form instruction when it must be the same as + the RS field in the instruction. This is used for extended + mnemonics like mr. */ +#define RBS RB + 1 + { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, + + /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form + instruction or the RT field in a D, DS, X, XFX or XO form + instruction. */ +#define RS RBS + 1 +#define RT RS +#define RT_MASK (0x1f << 21) + { 5, 21, 0, 0, PPC_OPERAND_GPR }, + + /* The SH field in an X or M form instruction. */ +#define SH RS + 1 +#define SH_MASK (0x1f << 11) + { 5, 11, 0, 0, 0 }, + + /* The SH field in an MD form instruction. This is split. */ +#define SH6 SH + 1 +#define SH6_MASK ((0x1f << 11) | (1 << 1)) + { 6, 1, insert_sh6, extract_sh6, 0 }, + + /* The SI field in a D form instruction. */ +#define SI SH6 + 1 + { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, + + /* The SI field in a D form instruction when we accept a wide range + of positive values. */ +#define SISIGNOPT SI + 1 + { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + + /* The SPR field in an XFX form instruction. This is flipped--the + lower 5 bits are stored in the upper 5 and vice- versa. */ +#define SPR SISIGNOPT + 1 +#define SPR_MASK (0x3ff << 11) + { 10, 11, insert_spr, extract_spr, 0 }, + + /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ +#define SPRBAT SPR + 1 +#define SPRBAT_MASK (0x3 << 17) + { 2, 17, 0, 0, 0 }, + + /* The SPRG register number in an XFX form m[ft]sprg instruction. */ +#define SPRG SPRBAT + 1 +#define SPRG_MASK (0x3 << 16) + { 2, 16, 0, 0, 0 }, + + /* The SR field in an X form instruction. */ +#define SR SPRG + 1 + { 4, 16, 0, 0, 0 }, + + /* The STRM field in an X AltiVec form instruction. */ +#define STRM SR + 1 +#define STRM_MASK (0x3 << 21) + { 2, 21, 0, 0, 0 }, + + /* The SV field in a POWER SC form instruction. */ +#define SV STRM + 1 + { 14, 2, 0, 0, 0 }, + + /* The TBR field in an XFX form instruction. This is like the SPR + field, but it is optional. */ +#define TBR SV + 1 + { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, + + /* The TO field in a D or X form instruction. */ +#define TO TBR + 1 +#define TO_MASK (0x1f << 21) + { 5, 21, 0, 0, 0 }, + + /* The U field in an X form instruction. */ +#define U TO + 1 + { 4, 12, 0, 0, 0 }, + + /* The UI field in a D form instruction. */ +#define UI U + 1 + { 16, 0, 0, 0, 0 }, + + /* The VA field in a VA, VX or VXR form instruction. */ +#define VA UI + 1 +#define VA_MASK (0x1f << 16) + { 5, 16, 0, 0, PPC_OPERAND_VR }, + + /* The VB field in a VA, VX or VXR form instruction. */ +#define VB VA + 1 +#define VB_MASK (0x1f << 11) + { 5, 11, 0, 0, PPC_OPERAND_VR }, + + /* The VC field in a VA form instruction. */ +#define VC VB + 1 +#define VC_MASK (0x1f << 6) + { 5, 6, 0, 0, PPC_OPERAND_VR }, + + /* The VD or VS field in a VA, VX, VXR or X form instruction. */ +#define VD VC + 1 +#define VS VD +#define VD_MASK (0x1f << 21) + { 5, 21, 0, 0, PPC_OPERAND_VR }, + + /* The SIMM field in a VX form instruction. */ +#define SIMM VD + 1 + { 5, 16, 0, 0, PPC_OPERAND_SIGNED}, + + /* The UIMM field in a VX form instruction. */ +#define UIMM SIMM + 1 + { 5, 16, 0, 0, 0 }, + + /* The SHB field in a VA form instruction. */ +#define SHB UIMM + 1 + { 4, 6, 0, 0, 0 }, + + /* The WS field. */ +#define WS SHB + 1 +#define WS_MASK (0x7 << 11) + { 3, 11, 0, 0, 0 }, + + /* The L field in an mtmsrd instruction */ +#define MTMSRD_L WS + 1 + { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL }, + +}; + +/* The functions used to insert and extract complicated operands. */ + +/* The BA field in an XL form instruction when it must be the same as + the BT field in the same instruction. This operand is marked FAKE. + The insertion function just copies the BT field into the BA field, + and the extraction function just checks that the fields are the + same. */ + +/*ARGSUSED*/ +static unsigned long +insert_bat (insn, value, dialect, errmsg) + unsigned long insn; + long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (((insn >> 21) & 0x1f) << 16); +} + +static long +extract_bat (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid; +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The BB field in an XL form instruction when it must be the same as + the BA field in the same instruction. This operand is marked FAKE. + The insertion function just copies the BA field into the BB field, + and the extraction function just checks that the fields are the + same. */ + +/*ARGSUSED*/ +static unsigned long +insert_bba (insn, value, dialect, errmsg) + unsigned long insn; + long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (((insn >> 16) & 0x1f) << 11); +} + +static long +extract_bba (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid; +{ + if (invalid != (int *) NULL + && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The BD field in a B form instruction. The lower two bits are + forced to zero. */ + +/*ARGSUSED*/ +static unsigned long +insert_bd (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (value & 0xfffc); +} + +/*ARGSUSED*/ +static long +extract_bd (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* The BD field in a B form instruction when the - modifier is used. + This modifier means that the branch is not expected to be taken. + For chips built to versions of the architecture prior to version 2 + (ie. not Power4 compatible), we set the y bit of the BO field to 1 + if the offset is negative. When extracting, we require that the y + bit be 1 and that the offset be positive, since if the y bit is 0 + we just want to print the normal form of the instruction. + Power4 compatible targets use two bits, "a", and "t", instead of + the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, + "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 + in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 + for branch on CTR. We only handle the taken/not-taken hint here. */ + +/*ARGSUSED*/ +static unsigned long +insert_bdm (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect; + const char **errmsg ATTRIBUTE_UNUSED; +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if ((value & 0x8000) != 0) + insn |= 1 << 21; + } + else + { + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x02 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x08 << 21; + } + return insn | (value & 0xfffc); +} + +static long +extract_bdm (insn, dialect, invalid) + unsigned long insn; + int dialect; + int *invalid; +{ + if (invalid != (int *) NULL) + { + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x06 << 21) + && (insn & (0x1d << 21)) != (0x18 << 21)) + *invalid = 1; + } + } + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* The BD field in a B form instruction when the + modifier is used. + This is like BDM, above, except that the branch is expected to be + taken. */ + +/*ARGSUSED*/ +static unsigned long +insert_bdp (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect; + const char **errmsg ATTRIBUTE_UNUSED; +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if ((value & 0x8000) == 0) + insn |= 1 << 21; + } + else + { + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x03 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x09 << 21; + } + return insn | (value & 0xfffc); +} + +static long +extract_bdp (insn, dialect, invalid) + unsigned long insn; + int dialect; + int *invalid; +{ + if (invalid != (int *) NULL) + { + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x07 << 21) + && (insn & (0x1d << 21)) != (0x19 << 21)) + *invalid = 1; + } + } + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* Check for legal values of a BO field. */ + +static int +valid_bo (value, dialect) + long value; + int dialect; +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, y may be anything): + 001zy + 011zy + 1z00y + 1z01y + 1z1zz + */ + switch (value & 0x14) + { + default: + case 0: + return 1; + case 0x4: + return (value & 0x2) == 0; + case 0x10: + return (value & 0x8) == 0; + case 0x14: + return value == 0x14; + } + } + else + { + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, a & t may be anything): + 0000z + 0001z + 0100z + 0101z + 001at + 011at + 1a00t + 1a01t + 1z1zz + */ + if ((value & 0x14) == 0) + return (value & 0x1) == 0; + else if ((value & 0x14) == 0x14) + return value == 0x14; + else + return 1; + } +} + +/* The BO field in a B form instruction. Warn about attempts to set + the field to an illegal value. */ + +static unsigned long +insert_bo (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect; + const char **errmsg; +{ + if (errmsg != (const char **) NULL + && ! valid_bo (value, dialect)) + *errmsg = _("invalid conditional option"); + return insn | ((value & 0x1f) << 21); +} + +static long +extract_bo (insn, dialect, invalid) + unsigned long insn; + int dialect; + int *invalid; +{ + long value; + + value = (insn >> 21) & 0x1f; + if (invalid != (int *) NULL + && ! valid_bo (value, dialect)) + *invalid = 1; + return value; +} + +/* The BO field in a B form instruction when the + or - modifier is + used. This is like the BO field, but it must be even. When + extracting it, we force it to be even. */ + +static unsigned long +insert_boe (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect; + const char **errmsg; +{ + if (errmsg != (const char **) NULL) + { + if (! valid_bo (value, dialect)) + *errmsg = _("invalid conditional option"); + else if ((value & 1) != 0) + *errmsg = _("attempt to set y bit when using + or - modifier"); + } + return insn | ((value & 0x1f) << 21); +} + +static long +extract_boe (insn, dialect, invalid) + unsigned long insn; + int dialect; + int *invalid; +{ + long value; + + value = (insn >> 21) & 0x1f; + if (invalid != (int *) NULL + && ! valid_bo (value, dialect)) + *invalid = 1; + return value & 0x1e; +} + +/* The DS field in a DS form instruction. This is like D, but the + lower two bits are forced to zero. */ + +/*ARGSUSED*/ +static unsigned long +insert_ds (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value & 3) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 4"); + return insn | (value & 0xfffc); +} + +/*ARGSUSED*/ +static long +extract_ds (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* The DE field in a DE form instruction. */ + +/*ARGSUSED*/ +static unsigned long +insert_de (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value > 2047 || value < -2048) && errmsg != NULL) + *errmsg = _("offset not between -2048 and 2047"); + return insn | ((value << 4) & 0xfff0); +} + +/*ARGSUSED*/ +static long +extract_de (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return (insn & 0xfff0) >> 4; +} + +/* The DES field in a DES form instruction. */ + +/*ARGSUSED*/ +static unsigned long +insert_des (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value > 8191 || value < -8192) && errmsg != NULL) + *errmsg = _("offset not between -8192 and 8191"); + else if ((value & 3) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 4"); + return insn | ((value << 2) & 0xfff0); +} + +/*ARGSUSED*/ +static long +extract_des (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; +} + +/* The LI field in an I form instruction. The lower two bits are + forced to zero. */ + +/*ARGSUSED*/ +static unsigned long +insert_li (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value & 3) != 0 && errmsg != (const char **) NULL) + *errmsg = _("ignoring least significant bits in branch offset"); + return insn | (value & 0x3fffffc); +} + +/*ARGSUSED*/ +static long +extract_li (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; +} + +/* The MB and ME fields in an M form instruction expressed as a single + operand which is itself a bitmask. The extraction function always + marks it as invalid, since we never want to recognize an + instruction which uses a field of this type. */ + +static unsigned long +insert_mbe (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + unsigned long uval, mask; + int mb, me, mx, count, last; + + uval = value; + + if (uval == 0) + { + if (errmsg != (const char **) NULL) + *errmsg = _("illegal bitmask"); + return insn; + } + + mb = 0; + me = 32; + if ((uval & 1) != 0) + last = 1; + else + last = 0; + count = 0; + + /* mb: location of last 0->1 transition */ + /* me: location of last 1->0 transition */ + /* count: # transitions */ + + for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1) + { + if ((uval & mask) && !last) + { + ++count; + mb = mx; + last = 1; + } + else if (!(uval & mask) && last) + { + ++count; + me = mx; + last = 0; + } + } + if (me == 0) + me = 32; + + if (count != 2 && (count != 0 || ! last)) + { + if (errmsg != (const char **) NULL) + *errmsg = _("illegal bitmask"); + } + + return insn | (mb << 6) | ((me - 1) << 1); +} + +static long +extract_mbe (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid; +{ + long ret; + int mb, me; + int i; + + if (invalid != (int *) NULL) + *invalid = 1; + + mb = (insn >> 6) & 0x1f; + me = (insn >> 1) & 0x1f; + if (mb < me + 1) + { + ret = 0; + for (i = mb; i <= me; i++) + ret |= (long) 1 << (31 - i); + } + else if (mb == me + 1) + ret = ~0; + else /* (mb > me + 1) */ + { + ret = ~ (long) 0; + for (i = me + 1; i < mb; i++) + ret &= ~ ((long) 1 << (31 - i)); + } + return ret; +} + +/* The MB or ME field in an MD or MDS form instruction. The high bit + is wrapped to the low end. */ + +/*ARGSUSED*/ +static unsigned long +insert_mb6 (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | ((value & 0x1f) << 6) | (value & 0x20); +} + +/*ARGSUSED*/ +static long +extract_mb6 (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn >> 6) & 0x1f) | (insn & 0x20); +} + +/* The NB field in an X form instruction. The value 32 is stored as + 0. */ + +static unsigned long +insert_nb (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if (value < 0 || value > 32) + *errmsg = _("value out of range"); + if (value == 32) + value = 0; + return insn | ((value & 0x1f) << 11); +} + +/*ARGSUSED*/ +static long +extract_nb (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + long ret; + + ret = (insn >> 11) & 0x1f; + if (ret == 0) + ret = 32; + return ret; +} + +/* The NSI field in a D form instruction. This is the same as the SI + field, only negated. The extraction function always marks it as + invalid, since we never want to recognize an instruction which uses + a field of this type. */ + +/*ARGSUSED*/ +static unsigned long +insert_nsi (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | ((- value) & 0xffff); +} + +static long +extract_nsi (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid; +{ + if (invalid != (int *) NULL) + *invalid = 1; + return - (((insn & 0xffff) ^ 0x8000) - 0x8000); +} + +/* The RA field in a D or X form instruction which is an updating + load, which means that the RA field may not be zero and may not + equal the RT field. */ + +static unsigned long +insert_ral (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if (value == 0 + || (unsigned long) value == ((insn >> 21) & 0x1f)) + *errmsg = "invalid register operand when updating"; + return insn | ((value & 0x1f) << 16); +} + +/* The RA field in an lmw instruction, which has special value + restrictions. */ + +static unsigned long +insert_ram (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((unsigned long) value >= ((insn >> 21) & 0x1f)) + *errmsg = _("index register in load range"); + return insn | ((value & 0x1f) << 16); +} + +/* The RA field in a D or X form instruction which is an updating + store or an updating floating point load, which means that the RA + field may not be zero. */ + +static unsigned long +insert_ras (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if (value == 0) + *errmsg = _("invalid register operand when updating"); + return insn | ((value & 0x1f) << 16); +} + +/* The RB field in an X form instruction when it must be the same as + the RS field in the instruction. This is used for extended + mnemonics like mr. This operand is marked FAKE. The insertion + function just copies the BT field into the BA field, and the + extraction function just checks that the fields are the same. */ + +/*ARGSUSED*/ +static unsigned long +insert_rbs (insn, value, dialect, errmsg) + unsigned long insn; + long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | (((insn >> 21) & 0x1f) << 11); +} + +static long +extract_rbs (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid; +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The SH field in an MD form instruction. This is split. */ + +/*ARGSUSED*/ +static unsigned long +insert_sh6 (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); +} + +/*ARGSUSED*/ +static long +extract_sh6 (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); +} + +/* The SPR field in an XFX form instruction. This is flipped--the + lower 5 bits are stored in the upper 5 and vice- versa. */ + +static unsigned long +insert_spr (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); +} + +static long +extract_spr (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); +} + +/* The TBR field in an XFX instruction. This is just like SPR, but it + is optional. When TBR is omitted, it must be inserted as 268 (the + magic number of the TB register). These functions treat 0 + (indicating an omitted optional operand) as 268. This means that + ``mftb 4,0'' is not handled correctly. This does not matter very + much, since the architecture manual does not define mftb as + accepting any values other than 268 or 269. */ + +#define TB (268) + +static unsigned long +insert_tbr (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + if (value == 0) + value = TB; + return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); +} + +static long +extract_tbr (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + long ret; + + ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); + if (ret == TB) + ret = 0; + return ret; +} + +/* Macros used to form opcodes. */ + +/* The main opcode. */ +#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) +#define OP_MASK OP (0x3f) + +/* The main opcode combined with a trap code in the TO field of a D + form instruction. Used for extended mnemonics for the trap + instructions. */ +#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) +#define OPTO_MASK (OP_MASK | TO_MASK) + +/* The main opcode combined with a comparison size bit in the L field + of a D form or X form instruction. Used for extended mnemonics for + the comparison instructions. */ +#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) +#define OPL_MASK OPL (0x3f,1) + +/* An A form instruction. */ +#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) +#define A_MASK A (0x3f, 0x1f, 1) + +/* An A_MASK with the FRB field fixed. */ +#define AFRB_MASK (A_MASK | FRB_MASK) + +/* An A_MASK with the FRC field fixed. */ +#define AFRC_MASK (A_MASK | FRC_MASK) + +/* An A_MASK with the FRA and FRC fields fixed. */ +#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) + +/* A B form instruction. */ +#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) +#define B_MASK B (0x3f, 1, 1) + +/* A B form instruction setting the BO field. */ +#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) +#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) + +/* A BBO_MASK with the y bit of the BO field removed. This permits + matching a conditional branch regardless of the setting of the y + bit. Similarly for the 'at' bits used for power4 branch hints. */ +#define Y_MASK (((unsigned long) 1) << 21) +#define AT1_MASK (((unsigned long) 3) << 21) +#define AT2_MASK (((unsigned long) 9) << 21) +#define BBOY_MASK (BBO_MASK &~ Y_MASK) +#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) + +/* A B form instruction setting the BO field and the condition bits of + the BI field. */ +#define BBOCB(op, bo, cb, aa, lk) \ + (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) +#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) + +/* A BBOCB_MASK with the y bit of the BO field removed. */ +#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) +#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) +#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) + +/* A BBOYCB_MASK in which the BI field is fixed. */ +#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) +#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) + +/* The main opcode mask with the RA field clear. */ +#define DRA_MASK (OP_MASK | RA_MASK) + +/* A DS form instruction. */ +#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) +#define DS_MASK DSO (0x3f, 3) + +/* A DE form instruction. */ +#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) +#define DE_MASK DEO (0x3e, 0xf) + +/* An M form instruction. */ +#define M(op, rc) (OP (op) | ((rc) & 1)) +#define M_MASK M (0x3f, 1) + +/* An M form instruction with the ME field specified. */ +#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) + +/* An M_MASK with the MB and ME fields fixed. */ +#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) + +/* An M_MASK with the SH and ME fields fixed. */ +#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) + +/* An MD form instruction. */ +#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) +#define MD_MASK MD (0x3f, 0x7, 1) + +/* An MD_MASK with the MB field fixed. */ +#define MDMB_MASK (MD_MASK | MB6_MASK) + +/* An MD_MASK with the SH field fixed. */ +#define MDSH_MASK (MD_MASK | SH6_MASK) + +/* An MDS form instruction. */ +#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) +#define MDS_MASK MDS (0x3f, 0xf, 1) + +/* An MDS_MASK with the MB field fixed. */ +#define MDSMB_MASK (MDS_MASK | MB6_MASK) + +/* An SC form instruction. */ +#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) +#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) + +/* An VX form instruction. */ +#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) + +/* The mask for an VX form instruction. */ +#define VX_MASK VX(0x3f, 0x7ff) + +/* An VA form instruction. */ +#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) + +/* The mask for an VA form instruction. */ +#define VXA_MASK VXA(0x3f, 0x3f) + +/* An VXR form instruction. */ +#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) + +/* The mask for a VXR form instruction. */ +#define VXR_MASK VXR(0x3f, 0x3ff, 1) + +/* An X form instruction. */ +#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) + +/* An X form instruction with the RC bit specified. */ +#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) + +/* The mask for an X form instruction. */ +#define X_MASK XRC (0x3f, 0x3ff, 1) + +/* An X_MASK with the RA field fixed. */ +#define XRA_MASK (X_MASK | RA_MASK) + +/* An X_MASK with the RB field fixed. */ +#define XRB_MASK (X_MASK | RB_MASK) + +/* An X_MASK with the RT field fixed. */ +#define XRT_MASK (X_MASK | RT_MASK) + +/* An X_MASK with the RA and RB fields fixed. */ +#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) + +/* An XRARB_MASK, but with the L bit clear. */ +#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) + +/* An X_MASK with the RT and RA fields fixed. */ +#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) + +/* An XRTRA_MASK, but with L bit clear. */ +#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) + +/* An X form comparison instruction. */ +#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) + +/* The mask for an X form comparison instruction. */ +#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) + +/* The mask for an X form comparison instruction with the L field + fixed. */ +#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) + +/* An X form trap instruction with the TO field specified. */ +#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) +#define XTO_MASK (X_MASK | TO_MASK) + +/* An X form tlb instruction with the SH field specified. */ +#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) +#define XTLB_MASK (X_MASK | SH_MASK) + +/* An X form sync instruction. */ +#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) + +/* An X form sync instruction with everything filled in except the LS field. */ +#define XSYNC_MASK (0xff9fffff) + +/* An X form AltiVec dss instruction. */ +#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) +#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) + +/* An XFL form instruction. */ +#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) +#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) + +/* An XL form instruction with the LK field set to 0. */ +#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) + +/* An XL form instruction which uses the LK field. */ +#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) + +/* The mask for an XL form instruction. */ +#define XL_MASK XLLK (0x3f, 0x3ff, 1) + +/* An XL form instruction which explicitly sets the BO field. */ +#define XLO(op, bo, xop, lk) \ + (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) +#define XLO_MASK (XL_MASK | BO_MASK) + +/* An XL form instruction which explicitly sets the y bit of the BO + field. */ +#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) +#define XLYLK_MASK (XL_MASK | Y_MASK) + +/* An XL form instruction which sets the BO field and the condition + bits of the BI field. */ +#define XLOCB(op, bo, cb, xop, lk) \ + (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) +#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) + +/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ +#define XLBB_MASK (XL_MASK | BB_MASK) +#define XLYBB_MASK (XLYLK_MASK | BB_MASK) +#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) + +/* An XL_MASK with the BO and BB fields fixed. */ +#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) + +/* An XL_MASK with the BO, BI and BB fields fixed. */ +#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) + +/* An XO form instruction. */ +#define XO(op, xop, oe, rc) \ + (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) +#define XO_MASK XO (0x3f, 0x1ff, 1, 1) + +/* An XO_MASK with the RB field fixed. */ +#define XORB_MASK (XO_MASK | RB_MASK) + +/* An XS form instruction. */ +#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) +#define XS_MASK XS (0x3f, 0x1ff, 1) + +/* A mask for the FXM version of an XFX form instruction. */ +#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11)) + +/* An XFX form instruction with the FXM field filled in. */ +#define XFXM(op, xop, fxm) \ + (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) + +/* An XFX form instruction with the SPR field filled in. */ +#define XSPR(op, xop, spr) \ + (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) +#define XSPR_MASK (X_MASK | SPR_MASK) + +/* An XFX form instruction with the SPR field filled in except for the + SPRBAT field. */ +#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) + +/* An XFX form instruction with the SPR field filled in except for the + SPRG field. */ +#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) + +/* An X form instruction with everything filled in except the E field. */ +#define XE_MASK (0xffff7fff) + +/* The BO encodings used in extended conditional branch mnemonics. */ +#define BODNZF (0x0) +#define BODNZFP (0x1) +#define BODZF (0x2) +#define BODZFP (0x3) +#define BODNZT (0x8) +#define BODNZTP (0x9) +#define BODZT (0xa) +#define BODZTP (0xb) + +#define BOF (0x4) +#define BOFP (0x5) +#define BOFM4 (0x6) +#define BOFP4 (0x7) +#define BOT (0xc) +#define BOTP (0xd) +#define BOTM4 (0xe) +#define BOTP4 (0xf) + +#define BODNZ (0x10) +#define BODNZP (0x11) +#define BODZ (0x12) +#define BODZP (0x13) +#define BODNZM4 (0x18) +#define BODNZP4 (0x19) +#define BODZM4 (0x1a) +#define BODZP4 (0x1b) + +#define BOU (0x14) + +/* The BI condition bit encodings used in extended conditional branch + mnemonics. */ +#define CBLT (0) +#define CBGT (1) +#define CBEQ (2) +#define CBSO (3) + +/* The TO encodings used in extended trap mnemonics. */ +#define TOLGT (0x1) +#define TOLLT (0x2) +#define TOEQ (0x4) +#define TOLGE (0x5) +#define TOLNL (0x5) +#define TOLLE (0x6) +#define TOLNG (0x6) +#define TOGT (0x8) +#define TOGE (0xc) +#define TONL (0xc) +#define TOLT (0x10) +#define TOLE (0x14) +#define TONG (0x14) +#define TONE (0x18) +#define TOU (0x1f) + +/* Smaller names for the flags so each entry in the opcodes table will + fit on a single line. */ +#undef PPC +#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY +#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM +#define POWER4 PPC_OPCODE_POWER4 | PPCCOM +#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY +#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY +#define PPCONLY PPC_OPCODE_PPC +#define PPC403 PPC_OPCODE_403 +#define PPC405 PPC403 +#define PPC750 PPC +#define PPC860 PPC +#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC +#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY +#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY +#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY +#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32 +#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 +#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY +#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define MFDEC1 PPC_OPCODE_POWER +#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 +#define BOOKE PPC_OPCODE_BOOKE +#define BOOKE64 PPC_OPCODE_BOOKE64 + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK FLAGS { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + FLAGS are flags indicated what processors support the instruction. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct powerpc_opcode powerpc_opcodes[] = { +{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, +{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, + +{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, +{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, +{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, +{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, + +{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } }, +{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } }, +{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } }, +{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } }, +{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } }, +{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } }, +{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, +{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, +{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, +{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, +{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, +{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, +{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, +{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, +{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, +{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, +{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, +{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, +{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, +{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, +{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, +{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, +{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, +{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, +{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, +{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, +{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, +{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, +{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, +{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, +{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, + +{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, +{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, + +{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, +{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, + +{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, + +{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, +{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, +{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, +{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, + +{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, +{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, +{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, +{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, + +{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, +{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, +{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } }, +{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, + +{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, +{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, +{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, + +{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, +{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, +{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, + +{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, +{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, +{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, +{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } }, +{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } }, +{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, + +{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, +{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, +{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } }, +{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } }, +{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, + +{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, +{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, +{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, +{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, +{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, +{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, +{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, +{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, +{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, +{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, +{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, +{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, +{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, +{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, +{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, +{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, +{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, +{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, +{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, +{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, +{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, +{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, +{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, +{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, +{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, +{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, +{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, +{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, +{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, +{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, + +{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, +{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, +{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, +{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, +{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, + +{ "b", B(18,0,0), B_MASK, COM, { LI } }, +{ "bl", B(18,0,1), B_MASK, COM, { LI } }, +{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, +{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, + +{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, + +{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, +{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, +{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, +{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, +{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, +{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, +{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, +{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, +{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, +{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, +{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, +{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, +{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, +{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, + +{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, + +{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, +{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, + +{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, +{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } }, +{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } }, + +{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, + +{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, + +{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, +{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, + +{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, +{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, + +{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, + +{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, + +{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, +{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, + +{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, + +{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, +{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, + +{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, +{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, +{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, +{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, +{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, +{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } }, +{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, +{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, +{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, +{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, +{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, + +{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, +{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, + +{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, +{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, + +{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, +{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, +{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, +{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, +{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, +{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, +{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, +{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, + +{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, +{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, + +{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, +{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, +{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, +{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, + +{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, +{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, +{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, +{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, +{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, +{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, + +{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, +{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, +{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, + +{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, +{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, + +{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, +{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, + +{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, +{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, + +{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, +{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, + +{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, +{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, + +{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, +{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, +{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, +{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, +{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, +{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, + +{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, +{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, + +{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, +{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, + +{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, +{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, + +{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, +{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, +{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, +{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, + +{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, +{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, + +{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, +{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, +{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, +{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, + +{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, +{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, +{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, +{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, +{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, +{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, +{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, +{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, + +{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, +{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, +{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, +{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, + +{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, + +{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, + +{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, + +{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } }, + +{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, + +{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, + +{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, + +{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, +{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, + +{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, +{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, +{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, +{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, + +{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, +{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, +{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, +{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, + +{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, +{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, + +{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, +{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, + +{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, +{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, + +{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, + +{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, +{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, +{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, +{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, + +{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, +{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, +{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, +{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, + +{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, + +{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, + +{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, +{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, + +{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, + +{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, +{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, + +{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, +{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, + +{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, +{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, +{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, +{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, +{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, +{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, +{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, +{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, +{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, +{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, +{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, +{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, +{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, +{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, +{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, + +{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, + +{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, + +{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, + +{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, + +{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } }, + +{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, + +{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, + +{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, +{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, +{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, +{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, + +{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, +{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, +{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, +{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, + +{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, + +{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, + +{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, + +{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, +{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, +{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, +{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, + +{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, + +{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, +{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } }, + +{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, + +{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, + +{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }}, +{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, + +{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, + +{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } }, + +{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, + +{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, +{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, + +{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, +{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, + +{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, +{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, + +{ "wrteei", X(31,163), XE_MASK, PPC403, { E } }, +{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } }, + +{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, + +{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, + +{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, +{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } }, + +{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, +{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, + +{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, + +{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, + +{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, + +{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, + +{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, + +{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, + +{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, +{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, + +{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, +{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, + +{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, + +{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, + +{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, +{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, +{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, +{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, + +{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, + +{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, +{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, + +{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } }, + +{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, + +{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, +{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, + +{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, + +{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, + +{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, + +{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, + +{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, +{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, +{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, +{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, + +{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, +{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, + +{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } }, + +{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, + +{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, +{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, + +{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } }, + +{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, + +{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, +{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, + +{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, + +{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, +{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } }, + +{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, + +{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, + +{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, +{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, + +{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, + +{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, +{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, +{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, +{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, +{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, +{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, +{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, +{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, +{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, +{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, +{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, +{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, +{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, +{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, +{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, +{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, +{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, +{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, +{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, +{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, +{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, +{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, +{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, +{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, +{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, +{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, +{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, +{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } }, +{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } }, + +{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, +{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, +{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, +{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, + +{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, +{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, +{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, +{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, +{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, +{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, +{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, +{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, +{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, +{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, +{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, +{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, +{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, +{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, +{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, +{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, +{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, +{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, +{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, +{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, +{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, +{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, +{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, +{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, +{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, +{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, +{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, +{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, +{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, +{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, +{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, +{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, +{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, +{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, +{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, +{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, +{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, +{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, +{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, +{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, +{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, +{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, +{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, +{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, +{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, +{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, +{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, +{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, +{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, +{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, +{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, +{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, +{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, +{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, +{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, +{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, +{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, +{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, +{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, +{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, +{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, +{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, +{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, +{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, +{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, +{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, +{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, +{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, +{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, +{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, +{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, +{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, +{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, +{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, +{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, +{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, +{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, +{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, +{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, +{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, +{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, +{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, +{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, +{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, +{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, +{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, +{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, +{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, +{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, +{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, +{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, +{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, +{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, +{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, +{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, +{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, +{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, + +{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, + +{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, +{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, + +{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, + +{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, +{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, + +{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } }, + +{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, +{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, +{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, +{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, + +{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, +{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, +{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, +{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, + +{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, + +{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } }, +{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, +{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, + +{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, + +{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, + +{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, + +{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, + +{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, +{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, + +{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, +{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, + +{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, + +{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, + +{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, + +{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, + +{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, + +{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, + +{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, +{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, + +{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, +{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, + +{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, + +{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, + +{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, + +{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, + +{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, +{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, +{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, +{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, + +{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } }, +{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } }, +{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } }, +{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } }, +{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } }, +{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } }, +{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } }, +{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } }, +{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } }, +{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } }, +{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } }, +{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } }, +{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } }, +{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } }, +{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } }, +{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } }, +{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } }, +{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } }, +{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } }, +{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } }, +{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } }, +{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } }, +{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } }, +{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } }, +{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } }, +{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } }, +{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } }, +{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } }, +{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } }, + +{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, + +{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, + +{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, + +{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, + +{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, +{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, +{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, +{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, +{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, +{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, +{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, +{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, +{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, +{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, +{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, +{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, +{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, +{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, +{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } }, +{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } }, +{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } }, +{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } }, +{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } }, +{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } }, +{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } }, +{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } }, +{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } }, +{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } }, +{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } }, +{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } }, +{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } }, +{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } }, +{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } }, +{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } }, +{ "mtvrsave",XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } }, +{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, +{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, +{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, +{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } }, +{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } }, +{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } }, +{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } }, +{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } }, +{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } }, +{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, +{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, +{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, +{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, +{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } }, +{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } }, +{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } }, +{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } }, +{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } }, +{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } }, +{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } }, +{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } }, +{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } }, +{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } }, +{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } }, +{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } }, +{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } }, +{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } }, +{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } }, +{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } }, +{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } }, +{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } }, +{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } }, +{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } }, +{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } }, +{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } }, +{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } }, +{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } }, +{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } }, +{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } }, +{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } }, +{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } }, +{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } }, +{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } }, +{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } }, +{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } }, +{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } }, +{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } }, +{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } }, +{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } }, +{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } }, +{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } }, +{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } }, +{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } }, +{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } }, +{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } }, +{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } }, +{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } }, +{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } }, +{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } }, +{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } }, +{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } }, +{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } }, +{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } }, +{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } }, +{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } }, +{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } }, +{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } }, +{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } }, +{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, + +{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, + +{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, +{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, + +{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, + +{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, +{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, +{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, +{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, + +{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, +{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, + +{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, + +{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, +{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, + +{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, + +{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, + +{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, + +{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } }, + +{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, + +{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, +{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, + +{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } }, +{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, + +{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, + +{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, +{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, +{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, +{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, + +{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, +{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, + +{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, +{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, + +{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, +{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, + +{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } }, + +{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, + +{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, + +{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, + +{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, + +{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, +{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, + +{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } }, +{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, +{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, +{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, +{ "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } }, + +{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, + +{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } }, + +{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, + +{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, + +{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, + +{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, + +{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, + +{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, +{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } }, + +{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } }, +{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } }, + +{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } }, + +{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, +{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, + +{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, +{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, + +{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } }, + +{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, + +{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, +{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, + +{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, + +{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, +{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } }, + +{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } }, + +{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, +{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, + +{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, +{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, + +{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } }, + +{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } }, +{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } }, + +{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, + +{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, +{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, + +{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, + +{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, +{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } }, + +{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, + +{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, +{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, +{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, +{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, + +{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, +{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, + +{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, + +{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, +{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, + +{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, +{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, +{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, +{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, + +{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, + +{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, +{ "mbar", X(31,854), 0xffffffff, BOOKE, { MO } }, + +{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, +{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, + +{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE, { RA, RB } }, + +{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, + +{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, + +{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, +{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, + +{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, +{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, + +{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, +{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, +{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, +{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, + +{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, WS } }, + +{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, +{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, + +{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, +{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, + +{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, +{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, + +{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, + +{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } }, + +{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, + +{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, +{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, +{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, + +{ "tlbwe", X(31,978), X_MASK, BOOKE, { RT, RA, WS } }, + +{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, + +{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, + +{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, +{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, + +{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } }, + +{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, +{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } }, + +{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, + +{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, +{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, + +{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, +{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, +{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, +{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, +{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, +{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, + +{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } }, +{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } }, + +{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, +{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } }, + +{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } }, + +{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, + +{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } }, +{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } }, + +{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, +{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } }, + +{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } }, + +{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, + +{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } }, + +{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, + +{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } }, + +{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, + +{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } }, + +{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, + +{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, +{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } }, + +{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } }, +{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } }, + +{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, + +{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, + +{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, + +{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, + +{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } }, + +{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, + +{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } }, + +{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, + +{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, + +{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, + +{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, +{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, +{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, + +{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } }, + +{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, + +{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } }, + +{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, +{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, + +{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, +{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, + +{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, +{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, + +{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, +{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, + +{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, +{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, + +{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, +{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, + +{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, + +{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, + +{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, + +{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, + +{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, + +{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, + +{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } }, +{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } }, +{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } }, +{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, +{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } }, +{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, +{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } }, +{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, +{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } }, +{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, +{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } }, +{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, + +{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } }, + +{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, + +{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, + +{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, +{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, + +{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, +{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, +{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, +{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, + +{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, +{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, +{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, +{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, + +{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, +{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, +{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, +{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, + +{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, +{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, +{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, +{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, + +{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, +{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, +{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, +{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, + +{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, +{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, + +{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, + +{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, +{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, +{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, +{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, + +{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, +{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, + +{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, + +{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, + +{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, + +{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, +{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, +{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, + +{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, + +{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, +{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, + +{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, +{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, + +{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, + +{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, +{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, + +{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, +{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, + +{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, +{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, + +{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, +{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, + +{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, +{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, + +{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, +{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, + +{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, +{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, + +{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, +{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, + +{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, +{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, + +{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, +{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, + +}; + +const int powerpc_num_opcodes = + sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); + +/* The macro table. This is only used by the assembler. */ + +/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 + when x=0; 32-x when x is between 1 and 31; are negative if x is + negative; and are 32 or more otherwise. This is what you want + when, for instance, you are emulating a right shift by a + rotate-left-and-mask, because the underlying instructions support + shifts of size 0 but not shifts of size 32. By comparison, when + extracting x bits from some word you want to use just 32-x, because + the underlying instructions don't support extracting 0 bits but do + support extracting the whole word (32 bits in this case). */ + +const struct powerpc_macro powerpc_macros[] = { +{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, +{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, +{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, +{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, +{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, +{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, +{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, +{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, +{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, +{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, +{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, +{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, +{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, +{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, +{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, +{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, + +{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, +{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, +{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, +{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, +{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, +{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, +{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, +{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, +{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, +{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, +{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, +{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, +{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, +{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, +{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, +{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, +{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, +{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, +{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, + +}; + +const int powerpc_num_macros = + sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c new file mode 100644 index 0000000..8745a89 --- /dev/null +++ b/opcodes/s390-dis.c @@ -0,0 +1,257 @@ +/* s390-dis.c -- Disassemble S390 instructions + Copyright 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GDB, GAS and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include "ansidecl.h" +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/s390.h" + +static int init_flag = 0; +static int opc_index[256]; +static int current_arch_mask = 0; + +static void init_disasm PARAMS ((struct disassemble_info *)); +static unsigned int s390_extract_operand + PARAMS ((unsigned char *, const struct s390_operand *)); + +/* Set up index table for first opcode byte. */ + +static void +init_disasm (info) + struct disassemble_info *info; +{ + const struct s390_opcode *opcode; + const struct s390_opcode *opcode_end; + + memset (opc_index, 0, sizeof (opc_index)); + opcode_end = s390_opcodes + s390_num_opcodes; + for (opcode = s390_opcodes; opcode < opcode_end; opcode++) + { + opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; + while ((opcode < opcode_end) && + (opcode[1].opcode[0] == opcode->opcode[0])) + opcode++; + } + switch (info->mach) + { + case bfd_mach_s390_31: + current_arch_mask = 1 << S390_OPCODE_ESA; + break; + case bfd_mach_s390_64: + current_arch_mask = 1 << S390_OPCODE_ESAME; + break; + default: + abort (); + } + init_flag = 1; +} + +/* Extracts an operand value from an instruction. */ + +static inline unsigned int +s390_extract_operand (insn, operand) + unsigned char *insn; + const struct s390_operand *operand; +{ + unsigned int val; + int bits; + + /* Extract fragments of the operand byte for byte. */ + insn += operand->shift / 8; + bits = (operand->shift & 7) + operand->bits; + val = 0; + do + { + val <<= 8; + val |= (unsigned int) *insn++; + bits -= 8; + } + while (bits > 0); + val >>= -bits; + val &= ((1U << (operand->bits - 1)) << 1) - 1; + + /* Sign extend value if the operand is signed or pc relative. */ + if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) + && (val & (1U << (operand->bits - 1)))) + val |= (-1U << (operand->bits - 1)) << 1; + + /* Double value if the operand is pc relative. */ + if (operand->flags & S390_OPERAND_PCREL) + val <<= 1; + + /* Length x in an instructions has real length x+1. */ + if (operand->flags & S390_OPERAND_LENGTH) + val++; + return val; +} + +/* Print a S390 instruction. */ + +int +print_insn_s390 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + bfd_byte buffer[6]; + const struct s390_opcode *opcode; + const struct s390_opcode *opcode_end; + unsigned int value; + int status, opsize, bufsize; + char separator; + + if (init_flag == 0) + init_disasm (info); + + /* The output looks better if we put 6 bytes on a line. */ + info->bytes_per_line = 6; + + /* Every S390 instruction is max 6 bytes long. */ + memset (buffer, 0, 6); + status = (*info->read_memory_func) (memaddr, buffer, 6, info); + if (status != 0) + { + for (bufsize = 0; bufsize < 6; bufsize++) + if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) + break; + if (bufsize <= 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* Opsize calculation looks strange but it works + 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes, + 11xxxxxx -> 6 bytes. */ + opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; + status = opsize > bufsize; + } + else + { + bufsize = 6; + opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; + } + + if (status == 0) + { + /* Find the first match in the opcode table. */ + opcode_end = s390_opcodes + s390_num_opcodes; + for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; + (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); + opcode++) + { + const struct s390_operand *operand; + const unsigned char *opindex; + + /* Check architecture. */ + if (!(opcode->architecture & current_arch_mask)) + continue; + /* Check signature of the opcode. */ + if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] + || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] + || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] + || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] + || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) + continue; + + /* The instruction is valid. */ + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + /* Extract the operands. */ + separator = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + unsigned int value; + + operand = s390_operands + *opindex; + value = s390_extract_operand (buffer, operand); + + if ((operand->flags & S390_OPERAND_INDEX) && value == 0) + continue; + if ((operand->flags & S390_OPERAND_BASE) && + value == 0 && separator == '(') + { + separator = ','; + continue; + } + + if (separator) + (*info->fprintf_func) (info->stream, "%c", separator); + + if (operand->flags & S390_OPERAND_GPR) + (*info->fprintf_func) (info->stream, "%%r%i", value); + else if (operand->flags & S390_OPERAND_FPR) + (*info->fprintf_func) (info->stream, "%%f%i", value); + else if (operand->flags & S390_OPERAND_AR) + (*info->fprintf_func) (info->stream, "%%a%i", value); + else if (operand->flags & S390_OPERAND_CR) + (*info->fprintf_func) (info->stream, "%%c%i", value); + else if (operand->flags & S390_OPERAND_PCREL) + (*info->print_address_func) (memaddr + (int) value, info); + else if (operand->flags & S390_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%i", (int) value); + else + (*info->fprintf_func) (info->stream, "%i", value); + + if (operand->flags & S390_OPERAND_DISP) + { + separator = '('; + } + else if (operand->flags & S390_OPERAND_BASE) + { + (*info->fprintf_func) (info->stream, ")"); + separator = ','; + } + else + separator = ','; + } + + /* Found instruction, printed it, return its size. */ + return opsize; + } + /* No matching instruction found, fall through to hex print. */ + } + + if (bufsize >= 4) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + value = (value << 8) + (unsigned int) buffer[2]; + value = (value << 8) + (unsigned int) buffer[3]; + (*info->fprintf_func) (info->stream, ".long\t0x%08x", value); + return 4; + } + else if (bufsize >= 2) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + (*info->fprintf_func) (info->stream, ".short\t0x%04x", value); + return 2; + } + else + { + value = (unsigned int) buffer[0]; + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value); + return 1; + } +} diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c new file mode 100644 index 0000000..d79ff81 --- /dev/null +++ b/opcodes/s390-mkopc.c @@ -0,0 +1,190 @@ +/* s390-mkopc.c -- Generates opcode table out of s390-opc.txt + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include +#include + +/* ARCHBITS_ESA and ARCH_ESAME correspond to the bit numbers defined + by s390_opcode_arch_val in include/opcode/s390.h: + ARCHBITS_ESAONLY = (1<= max_ops) + { + max_ops = max_ops * 2; + op_array = realloc (op_array, max_ops * sizeof (struct op_struct)); + } + + sort_value = 0; + str = opcode; + for (ix = 0; ix < 16; ix++) + { + if (*str >= '0' && *str <= '9') + sort_value = (sort_value << 4) + (*str - '0'); + else if (*str >= 'a' && *str <= 'f') + sort_value = (sort_value << 4) + (*str - 'a' + 10); + else if (*str >= 'A' && *str <= 'F') + sort_value = (sort_value << 4) + (*str - 'A' + 10); + else if (*str == '?') + sort_value <<= 4; + else + break; + str ++; + } + sort_value <<= 4*(16 - ix); + no_nibbles = ix; + for (ix = 0; ix < no_ops; ix++) + if (sort_value > op_array[ix].sort_value) + break; + for (k = no_ops; k > ix; k--) + op_array[k] = op_array[k-1]; + strcpy(op_array[ix].opcode, opcode); + strcpy(op_array[ix].mnemonic, mnemonic); + strcpy(op_array[ix].format, format); + op_array[ix].sort_value = sort_value; + op_array[ix].no_nibbles = no_nibbles; + op_array[ix].archbits = archbits; + no_ops++; +} + +static char file_header[] = + "/* The opcode table. This file was generated by s390-mkopc.\n\n" + " The format of the opcode table is:\n\n" + " NAME OPCODE MASK OPERANDS\n\n" + " Name is the name of the instruction.\n" + " OPCODE is the instruction opcode.\n" + " MASK is the opcode mask; this is used to tell the disassembler\n" + " which bits in the actual opcode must match OPCODE.\n" + " OPERANDS is the list of operands.\n\n" + " The disassembler reads the table in order and prints the first\n" + " instruction which matches. */\n\n" + "const struct s390_opcode s390_opcodes[] =\n {\n"; + +/* `dumpTable': write opcode table. */ + +static void +dumpTable (void) +{ + char *str; + int ix; + + /* Write hash table entries (slots). */ + printf (file_header); + + for (ix = 0; ix < no_ops; ix++) + { + printf (" { \"%s\", ", op_array[ix].mnemonic); + for (str = op_array[ix].opcode; *str != 0; str++) + if (*str == '?') + *str = '0'; + printf ("OP%i(0x%sLL), ", + op_array[ix].no_nibbles*4, op_array[ix].opcode); + printf ("MASK_%s, INSTR_%s, ", + op_array[ix].format, op_array[ix].format); + printf ("%i}", op_array[ix].archbits); + if (ix < no_ops-1) + printf (",\n"); + else + printf ("\n"); + } + printf ("};\n\n"); + printf ("const int s390_num_opcodes =\n"); + printf (" sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);\n\n"); +} + +int +main (void) +{ + char currentLine[256]; + + createTable (); + + /* Read opcode descriptions from `stdin'. For each mnemonic, + make an entry into the opcode table. */ + while (fgets (currentLine, sizeof (currentLine), stdin) != NULL) + { + char opcode[16]; + char mnemonic[16]; + char format[16]; + char description[64]; + char archtag[16]; + int archbits; + + if (currentLine[0] == '#') + continue; + memset (opcode, 0, 8); + if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s", + opcode, mnemonic, format, description, archtag) == 5) + { + if (strcmp (archtag, "esaonly") == 0) + archbits = ARCHBITS_ESAONLY; + else if (strcmp (archtag, "esa") == 0) + archbits = ARCHBITS_ESA; + else if (strcmp (archtag, "esame") == 0) + archbits = ARCHBITS_ESAME; + else + archbits = 0; + insertOpcode (opcode, mnemonic, format, archbits); + } + else + fprintf (stderr, "Couldn't scan line %s\n", currentLine); + } + + dumpTable (); + return 0; +} diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c new file mode 100644 index 0000000..7cd8231 --- /dev/null +++ b/opcodes/s390-opc.c @@ -0,0 +1,318 @@ +/* s390-opc.c -- S390 opcode list + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/s390.h" + +/* This file holds the S390 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* The operands table. + The fields are bits, shift, insert, extract, flags. */ + +const struct s390_operand s390_operands[] = +{ +#define UNUSED 0 + { 0, 0, 0 }, /* Indicates the end of the operand list */ + +#define R_8 1 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +#define R_12 2 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +#define R_16 3 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +#define R_20 4 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +#define R_24 5 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +#define R_28 6 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +#define R_32 7 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + +#define F_8 8 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +#define F_12 9 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +#define F_16 10 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_20 11 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_24 12 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +#define F_28 13 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +#define F_32 14 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + +#define A_8 15 /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +#define A_12 16 /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +#define A_24 17 /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +#define A_28 18 /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + +#define C_8 19 /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +#define C_12 20 /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + +#define B_16 21 /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, +#define B_32 22 /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, + +#define X_12 23 /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, + +#define D_20 24 /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +#define D_36 25 /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, + +#define L4_8 26 /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +#define L4_12 27 /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +#define L8_8 28 /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + +#define U4_8 29 /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +#define U4_12 30 /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +#define U4_16 31 /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +#define U4_20 32 /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +#define U8_8 33 /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +#define U8_16 34 /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +#define I16_16 35 /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +#define U16_16 36 /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +#define J16_16 37 /* PC relative jump offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +#define J32_16 38 /* PC relative long offset at 16 */ + { 32, 16, S390_OPERAND_PCREL } +}; + + +/* Macros used to form opcodes. */ + +/* 8/16/48 bit opcodes. */ +#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } +#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ + (x >> 16) & 255, (x >> 8) & 255, x & 255} + +/* The new format of the INSTR_x_y and MASK_x_y defines is based + on the following rules: + 1) the middle part of the definition (x in INSTR_x_y) is the official + names of the instruction format that you can find in the principals + of operation. + 2) the last part of the definition (y in INSTR_x_y) gives you an idea + which operands the binary represenation of the instruction has. + The meanings of the letters in y are: + a - access register + c - control register + d - displacement, 12 bit + f - floating pointer register + i - signed integer, 4 or 8 bit + l - length, 4 or 8 bit + p - pc relative + r - general purpose register + u - unsigned integer, 4 or 8 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in + storage and not the order of the paramaters of the instructions. + The use of the letters is not a 100% match with the PoP but it is + quite close. + + For example the instruction "mvo" is defined in the PoP as follows: + + MVO D1(L1,B1),D2(L2,B2) [SS] + + -------------------------------------- + | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | + -------------------------------------- + 0 8 12 16 20 32 36 + + The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ + +#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ +#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ +#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ +#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ +#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ +#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ +#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ +#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ +#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ +#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ +#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ +#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ +#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ +#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ +#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ +#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ +#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ +#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ +#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ +#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ +#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ +#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ +#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ +#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ +#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ +#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ +#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ +#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ +#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ +#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ +#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ +#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ +#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ +#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ +#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ +#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ +#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ +#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ + +#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } +#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + +/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + +const struct s390_opcode s390_opformats[] = + { + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 }, +}; + +const int s390_num_opformats = + sizeof (s390_opformats) / sizeof (s390_opformats[0]); + +#include "s390-opc.tab" diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt new file mode 100644 index 0000000..ddcf089 --- /dev/null +++ b/opcodes/s390-opc.txt @@ -0,0 +1,626 @@ +# S/390 opcodes list. Use s390-mkopc to convert it into the opcode table. +# Copyright 2000, 2001 Free Software Foundation, Inc. +# Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). +5a a RX_RRRD "add" esa +6a ad RX_FRRD "add normalized (long)" esa +2a adr RR_FF "add normalized (long)" esa +7a ae RX_FRRD "add normalized (short)" esa +3a aer RR_FF "add normalized (short)" esa +4a ah RX_RRRD "add halfword" esa +5e al RX_RRRD "add logical" esa +1e alr RR_RR "add logical" esa +fa ap SS_LLRDRD "add decimal" esa +1a ar RR_RR "add" esa +7e au RX_FRRD "add unnormalized (short)" esa +3e aur RR_FF "add unnormalized (short)" esa +6e aw RX_FRRD "add unnormalized (long)" esa +2e awr RR_FF "add unnormalized (long)" esa +36 axr RR_FF "add normalized" esa +b240 bakr RRE_RR "branch and stack" esa +45 bal RX_RRRD "branch and link" esa +05 balr RR_RR "branch and link" esa +4d bas RX_RRRD "branch and save" esa +0d basr RR_RR "branch and save" esa +0c bassm RR_RR "branch and save and set mode" esa +47 bc RX_URRD "branch on condition" esa +07 bcr RR_UR "branch on condition" esa +46 bct RX_RRRD "branch on count" esa +06 bctr RR_RR "branch on count" esa +b258 bsg RRE_RR "branch in subspace group" esa +0b bsm RR_RR "branch and set mode" esa +86 bxh RS_RRRD "branch on index high" esa +87 bxle RS_RRRD "branch on index low or equal" esa +59 c RX_RRRD "compare" esa +69 cd RX_FRRD "compare (long)" esa +29 cdr RR_FF "compare (long)" esa +bb cds RS_RRRD "compare double and swap" esa +79 ce RX_FRRD "compare (short)" esa +39 cer RR_FF "compare (short)" esa +b21a cfc S_RD "compare and form codeword" esa +49 ch RX_RRRD "compare halfword" esa +55 cl RX_RRRD "compare logical" esa +d5 clc SS_L0RDRD "compare logical" esa +0f clcl RR_RR "compare logical long" esa +95 cli SI_URD "compare logical" esa +bd clm RS_RURD "compare logical characters under mask" esa +15 clr RR_RR "compare logical" esa +b25d clst RRE_RR "compare logical string" esa +b263 cmpsc RRE_RR "compression call" esa +f9 cp SS_LLRDRD "compare decimal" esa +b24d cpya RRE_AA "copy access" esa +19 cr RR_RR "compare" esa +ba cs RS_RRRD "compare and swap" esa +b230 csch S_00 "clear subchannel" esa +b257 cuse RRE_RR "compare until substring equal" esa +b250 csp RRE_RR "compare and swap and purge" esa +4f cvb RX_RRRD "convert to binary" esa +4e cvd RX_RRRD "convert to decimal" esa +5d d RX_RRRD "divide" esa +6d dd RX_FRRD "divide (long)" esa +2d ddr RR_FF "divide (long)" esa +7d de RX_FRRD "divide (short)" esa +3d der RR_FF "divide (short)" esa +83 diag RS_RRRD "diagnose" esa +fd dp SS_LLRDRD "divide decimal" esa +1d dr RR_RR "divide" esa +b22d dxr RRE_F0 "divide (ext.)" esa +b24f ear RRE_RA "extract access" esa +de ed SS_L0RDRD "edit" esa +df edmk SS_L0RDRD "edit and mark" esa +b226 epar RRE_R0 "extract primary ASN" esa +b249 ereg RRE_RR "extract stacked registers" esa +b227 esar RRE_R0 "extract secondary ASN" esa +b24a esta RRE_RR "extract stacked state" esa +44 ex RX_RRRD "execute" esa +24 hdr RR_FF "halve (long)" esa +34 her RR_FF "halve (short)" esa +b231 hsch S_00 "halt subchannel" esa +b224 iac RRE_R0 "insert address space control" esa +43 ic RX_RRRD "insert character" esa +bf icm RS_RURD "insert characters under mask" esa +b20b ipk S_00 "insert PSW key" esa +b222 ipm RRE_R0 "insert program mask" esa +b221 ipte RRE_RR "invalidate page table entry" esa +b229 iske RRE_RR "insert storage key extended" esa +b223 ivsk RRE_RR "insert virtual storage key" esa +58 l RX_RRRD "load" esa +41 la RX_RRRD "load address" esa +51 lae RX_RRRD "load address extended" esa +9a lam RS_AARD "load access multiple" esa +e500 lasp SSE_RDRD "load address space parameters" esa +23 lcdr RR_FF "load complement (long)" esa +33 lcer RR_FF "load complement (short)" esa +13 lcr RR_RR "load complement" esa +b7 lctl RS_CCRD "load control" esa +68 ld RX_FRRD "load (long)" esa +28 ldr RR_FF "load (long)" esa +78 le RX_FRRD "load (short)" esa +38 ler RR_FF "load (short)" esa +48 lh RX_RRRD "load halfword" esa +98 lm RS_RRRD "load multiple" esa +21 lndr RR_FF "load negative (long)" esa +31 lner RR_FF "load negative (short)" esa +11 lnr RR_RR "load negative" esa +20 lpdr RR_FF "load positive (long)" esa +30 lper RR_FF "load positive (short)" esa +10 lpr RR_RR "load positive" esa +82 lpsw S_RD "load PSW" esa +18 lr RR_RR "load" esa +b1 lra RX_RRRD "load real address" esa +25 lrdr RR_FF "load rounded (ext. to long)" esa +35 lrer RR_FF "load rounded (long to short)" esa +22 ltdr RR_FF "load and test (long)" esa +32 lter RR_FF "load and test (short)" esa +12 ltr RR_RR "load and test" esa +b24b lura RRE_RR "load using real address" esa +5c m RX_RRRD "multiply" esa +af mc SI_URD "monitor call" esa +6c md RX_FRRD "multiply (long)" esa +2c mdr RR_FF "multiply (long)" esa +7c me RX_FRRD "multiply (short to long)" esa +3c mer RR_FF "multiply (short to long)" esa +4c mh RX_RRRD "multiply halfword" esa +fc mp SS_LLRDRD "multiply decimal" esa +1c mr RR_RR "multiply" esa +b232 msch S_RD "modify subchannel" esa +b247 msta RRE_R0 "modify stacked state" esa +d2 mvc SS_L0RDRD "move" esa +e50f mvcdk SSE_RDRD "move with destination key" esa +e8 mvcin SS_L0RDRD "move inverse" esa +d9 mvck SS_RRRDRD "move with key" esa +0e mvcl RR_RR "move long" esa +da mvcp SS_RRRDRD "move to primary" esa +db mvcs SS_RRRDRD "move to secondary" esa +e50e mvcsk SSE_RDRD "move with source key" esa +92 mvi SI_URD "move" esa +d1 mvn SS_L0RDRD "move numerics" esa +f1 mvo SS_LLRDRD "move with offset" esa +b254 mvpg RRE_RR "move page" esa +b255 mvst RRE_RR "move string" esa +d3 mvz SS_L0RDRD "move zones" esa +67 mxd RX_FRRD "multiply (long to ext.)" esa +27 mxdr RR_FF "multiply (long to ext.)" esa +26 mxr RR_FF "multiply (ext.)" esa +54 n RX_RRRD "AND" esa +d4 nc SS_L0RDRD "AND" esa +94 ni SI_URD "AND" esa +14 nr RR_RR "AND" esa +56 o RX_RRRD "OR" esa +d6 oc SS_L0RDRD "OR" esa +96 oi SI_URD "OR" esa +16 or RR_RR "OR" esa +f2 pack SS_LLRDRD "pack" esa +b248 palb RRE_00 "purge ALB" esa +b218 pc S_RD "program call" esa +0101 pr E "program return" esa +b228 pt RRE_RR "program transfer" esa +b20d ptlb S_00 "purge TLB" esa +b23b rchp S_00 "reset channel path" esa +b22a rrbe RRE_RR "reset reference bit extended" esa +b238 rsch S_00 "resume subchannel" esa +5b s RX_RRRD "subtract" esa +b219 sac S_RD "set address space control" esa +b279 sacf S_RD "set address space control fast" esa +b237 sal S_00 "set address limit" esa +b24e sar RRE_AR "set access" esa +b23c schm S_00 "set channel monitor" esa +b204 sck S_RD "set clock" esa +b206 sckc S_RD "set clock comparator" esa +6b sd RX_FRRD "subtract normalized (long)" esa +2b sdr RR_FF "subtract normalized (long)" esa +7b se RX_FRRD "subtract normalized (short)" esa +3b ser RR_FF "subtract normalized (short)" esa +4b sh RX_RRRD "subtract halfword" esa +b214 sie S_RD "start interpretive execution" esa +ae sigp RS_RRRD "signal processor" esa +5f sl RX_RRRD "subtract logical" esa +8b sla RS_R0RD "shift left single" esa +8f slda RS_R0RD "shift left double (long)" esa +8d sldl RS_R0RD "shift left double logical (long)" esa +89 sll RS_R0RD "shift left single logical" esa +1f slr RR_RR "subtract logical" esa +fb sp SS_LLRDRD "subtract decimal" esa +b20a spka S_RD "set PSW key from address" esa +04 spm RR_R0 "set program mask" esa +b208 spt S_RD "set CPU timer" esa +b210 spx S_RD "set prefix" esa +b244 sqdr RRE_F0 "square root (long)" esa +b245 sqer RRE_F0 "square root (short)" esa +1b sr RR_RR "subtract" esa +8a sra RS_R0RD "shift right single" esa +8e srda RS_R0RD "shift right double (long)" esa +8c srdl RS_R0RD "shift right double logical (long)" esa +88 srl RS_R0RD "shift right single logical" esa +f0 srp SS_LIRDRD "shift and round decimal" esa +b25e srst RRE_RR "search string" esa +b225 ssar RRE_R0 "set secondary ASN" esa +b233 ssch S_RD "start subchannel" esa +b22b sske RRE_RR "set storage key extended" esa +80 ssm S_RD "set system mask" esa +50 st RX_RRRD "store" esa +9b stam RS_AARD "store access multiple" esa +b212 stap S_RD "store CPU address" esa +42 stc RX_RRRD "store character" esa +b205 stck S_RD "store clock" esa +b207 stckc S_RD "store clock comparator" esa +be stcm RS_RURD "store characters under mask" esa +b23a stcps S_RD "store channel path status" esa +b239 stcrw S_RD "store channel report word" esa +b6 stctl RS_CCRD "store control" esa +60 std RX_FRRD "store (long)" esa +70 ste RX_FRRD "store (short)" esa +40 sth RX_RRRD "store halfword" esa +b202 stidp S_RD "store CPU id" esa +90 stm RS_RRRD "store multiple" esa +ac stnsm SI_URD "store then AND system mask" esa +ad stosm SI_URD "store then OR system mask" esa +b209 stpt S_RD "store CPU timer" esa +b211 stpx S_RD "store prefix" esa +b234 stsch S_RD "store subchannel" esa +b246 stura RRE_RR "store using real address" esa +7f su RX_FRRD "subtract unnormalized (short)" esa +3f sur RR_FF "subtract unnormalized (short)" esa +0a svc RR_U0 "supervisor call" esa +6f sw RX_FRRD "subtract unnormalized (long)" esa +2f swr RR_FF "subtract unnormalized (long)" esa +37 sxr RR_FF "subtract normalized (ext.)" esa +b24c tar RRE_AR "test access" esa +b22c tb RRE_0R "test block" esa +91 tm SI_URD "test under mask" esa +b236 tpi S_RD "test pending interruption" esa +e501 tprot SSE_RDRD "test protection" esa +dc tr SS_L0RDRD "translate" esa +99 trace RS_RRRD "trace" esa +dd trt SS_L0RDRD "translate and test" esa +93 ts S_RD "test and set" esa +b235 tsch S_RD "test subchannel" esa +f3 unpk SS_LLRDRD "unpack" esa +0102 upt E "update tree" esa +57 x RX_RRRD "exclusive OR" esa +d7 xc SS_L0RDRD "exclusive OR" esa +97 xi SI_URD "exclusive OR" esa +17 xr RR_RR "exclusive OR" esa +f8 zap SS_LLRDRD "zero and add" esa +a70a ahi RI_RI "add halfword immediate" esa +84 brxh RSI_RRP "branch relative on index high" esa +85 brxle RSI_RRP "branch relative on index low or equal" esa +a705 bras RI_RP "branch relative and save" esa +a704 brc RI_UP "branch relative on condition" esa +a706 brct RI_RP "branch relative on count" esa +b241 cksm RRE_RR "checksum" esa +a70e chi RI_RI "compare halfword immediate" esa +a9 clcle RS_RRRD "compare logical long extended" esa +a708 lhi RI_RI "load halfword immediate" esa +a8 mvcle RS_RRRD "move long extended" esa +a70c mhi RI_RI "multiply halfword immediate" esa +b252 msr RRE_RR "multiply single" esa +71 ms RX_RRRD "multiply single" esa +a700 tmh RI_RU "test under mask high" esa +a701 tml RI_RU "test under mask low" esa +0700 nopr RR_0R "no operation" esa +0710 bor RR_0R "branch on overflow / if ones" esa +0720 bhr RR_0R "branch on high" esa +0720 bpr RR_0R "branch on plus" esa +0730 bnler RR_0R "branch on not low or equal" esa +0740 blr RR_0R "branch on low" esa +0740 bmr RR_0R "branch on minus / if mixed" esa +0750 bnher RR_0R "branch on not high or equal" esa +0760 blhr RR_0R "branch on low or high" esa +0770 bner RR_0R "branch on not equal" esa +0770 bnzr RR_0R "branch on not zero / if not zeros" esa +0780 ber RR_0R "branch on equal" esa +0780 bzr RR_0R "branch on zero / if zeros" esa +0790 bnlhr RR_0R "branch on not low or high" esa +07a0 bher RR_0R "branch on high or equal" esa +07b0 bnlr RR_0R "branch on not low" esa +07b0 bnmr RR_0R "branch on not minus / if not mixed" esa +07c0 bler RR_0R "brach on low or equal" esa +07d0 bnhr RR_0R "branch on not high" esa +07d0 bnpr RR_0R "branch on not plus" esa +07e0 bnor RR_0R "branch on not overflow / if not ones" esa +07f0 br RR_0R "unconditional branch" esa +4700 nop RX_0RRD "no operation" esa +4710 bo RX_0RRD "branch on overflow / if ones" esa +4720 bh RX_0RRD "branch on high" esa +4720 bp RX_0RRD "branch on plus" esa +4730 bnle RX_0RRD "branch on not low or equal" esa +4740 bl RX_0RRD "branch on low" esa +4740 bm RX_0RRD "branch on minus / if mixed" esa +4750 bnhe RX_0RRD "branch on not high or equal" esa +4760 blh RX_0RRD "branch on low or high" esa +4770 bne RX_0RRD "branch on not equal" esa +4770 bnz RX_0RRD "branch on not zero / if not zeros" esa +4780 be RX_0RRD "branch on equal" esa +4780 bz RX_0RRD "branch on zero / if zeros" esa +4790 bnlh RX_0RRD "branch on not low or high" esa +47a0 bhe RX_0RRD "branch on high or equal" esa +47b0 bnl RX_0RRD "branch on not low" esa +47b0 bnm RX_0RRD "branch on not minus / if not mixed" esa +47c0 ble RX_0RRD "branch on low or equal" esa +47d0 bnh RX_0RRD "branch on not high" esa +47d0 bnp RX_0RRD "branch on not plus" esa +47e0 bno RX_0RRD "branch on not overflow / if not ones" esa +47f0 b RX_0RRD "unconditional branch" esa +a714 jo RI_0P "jump on overflow / if ones" esa +a724 jh RI_0P "jump on A high" esa +a724 jp RI_0P "jump on plus" esa +a734 jnle RI_0P "jump on not low or equal" esa +a744 jl RI_0P "jump on A low" esa +a744 jm RI_0P "jump on minus / if mixed" esa +a754 jnhe RI_0P "jump on not high or equal" esa +a764 jlh RI_0P "jump on low or high" esa +a774 jne RI_0P "jump on A not equal B" esa +a774 jnz RI_0P "jump on not zero / if not zeros" esa +a784 je RI_0P "jump on A equal B" esa +a784 jz RI_0P "jump on zero / if zeros" esa +a794 jnlh RI_0P "jump on not low or high" esa +a7a4 jhe RI_0P "jump on high or equal" esa +a7b4 jnl RI_0P "jump on A not low" esa +a7b4 jnm RI_0P "jump on not minus / if not mixed" esa +a7c4 jle RI_0P "jump on low or equal" esa +a7d4 jnh RI_0P "jump on A not high" esa +a7d4 jnp RI_0P "jump on not plus" esa +a7e4 jno RI_0P "jump on not overflow / if not ones" esa +a7f4 j RI_0P "jump" esa +b34a axbr RRE_FF "add extended bfp" esa +b31a adbr RRE_FF "add long bfp" esa +ed000000001a adb RXE_FRRD "add long bfp" esa +b30a aebr RRE_FF "add short bfp" esa +ed000000000a aeb RXE_FRRD "add short bfp" esa +b349 cxbr RRE_FF "compare extended bfp" esa +b319 cdbr RRE_FF "compare long bfp" esa +ed0000000019 cdb RXE_FRRD "compare long bfp" esa +b309 cebr RRE_FF "compare short bfp" esa +ed0000000009 ceb RXE_FRRD "compare short bfp" esa +b348 kxbr RRE_FF "compare and signal extended bfp" esa +b318 kdbr RRE_FF "compare and signal long bfp" esa +ed0000000018 kdb RXE_FRRD "compare and signal long bfp" esa +b308 kebr RRE_FF "compare and signal short bfp" esa +ed0000000008 keb RXE_FRRD "compare and signal short bfp" esa +b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" esa +b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" esa +b394 cefbr RRE_RF "convert from fixed 32 to short bfp" esa +b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" esa +b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" esa +b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" esa +b34d dxbr RRE_FF "divide extended bfp" esa +b31d ddbr RRE_FF "divide long bfp" esa +ed000000001d ddb RXE_FRRD "divide long bfp" esa +b30d debr RRE_FF "divide short bfp" esa +ed000000000d deb RXE_FRRD "divide short bfp" esa +b35b didbr RRF_FUFF "divide to integer long bfp" esa +b353 diebr RRF_FUFF "divide to integer short bfp" esa +b38c efpc RRE_RR "extract fpc" esa +b342 ltxbr RRE_FF "load and test extended bfp" esa +b312 ltdbr RRE_FF "load and test long bfp" esa +b302 ltebr RRE_FF "load and test short bfp" esa +b343 lcxbr RRE_FF "load complement extended bfp" esa +b313 lcdbr RRE_FF "load complement long bfp" esa +b303 lcebr RRE_FF "load complement short bfp" esa +b347 fixbr RRF_U0FF "load fp integer extended bfp" esa +b35f fidbr RRF_U0FF "load fp integer long bfp" esa +b357 fiebr RRF_U0FF "load fp integer short bfp" esa +b29d lfpc S_RD "load fpc" esa +b305 lxdbr RRE_FF "load lengthened long to extended bfp" esa +ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" esa +b306 lxebr RRE_FF "load lengthened short to extended bfp" esa +ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" esa +b304 ldebr RRE_FF "load lengthened short to long bfp" esa +ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" esa +b341 lnxbr RRE_FF "load negative extended bfp" esa +b311 lndbr RRE_FF "load negative long bfp" esa +b301 lnebr RRE_FF "load negative short bfp" esa +b340 lpxbr RRE_FF "load positive extended bfp" esa +b310 lpdbr RRE_FF "load positive long bfp" esa +b300 lpebr RRE_FF "load positive short bfp" esa +b345 ldxbr RRE_FF "load rounded extended to long bfp" esa +b346 lexbr RRE_FF "load rounded extended to short bfp" esa +b344 ledbr RRE_FF "load rounded long to short bfp" esa +b34c mxbr RRE_FF "multiply extended bfp" esa +b31c mdbr RRE_FF "multiply long bfp" esa +ed000000001c mdb RXE_FRRD "multiply long bfp" esa +b307 mxdbr RRE_FF "multiply long to extended bfp" esa +ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" esa +b317 meebr RRE_FF "multiply short bfp" esa +ed0000000017 meeb RXE_FRRD "multiply short bfp" esa +b30c mdebr RRE_FF "multiply short to long bfp" esa +ed000000000c mdeb RXE_FRRD "multiply short to long bfp" esa +b31e madbr RRF_F0FF "multiply and add long bfp" esa +ed000000001e madb RXF_FRRDF "multiply and add long bfp" esa +b30e maebr RRF_F0FF "multiply and add short bfp" esa +ed000000000e maeb RXF_FRRDF "multiply and add short bfp" esa +b31f msdbr RRF_F0FF "multiply and subtract long bfp" esa +ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" esa +b30f msebr RRF_F0FF "multiply and subtract short bfp" esa +ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" esa +b384 sfpc RRE_RR "set fpc" esa +b299 srnm S_RD "set rounding mode" esa +b316 sqxbr RRE_FF "square root extended bfp" esa +b315 sqdbr RRE_FF "square root long bfp" esa +ed0000000015 sqdb RXE_FRRD "square root long bfp" esa +b314 sqebr RRE_FF "square root short bfp" esa +ed0000000014 sqeb RXE_FRRD "square root short bfp" esa +b29c stfpc S_RD "store fpc" esa +b34b sxbr RRE_FF "subtract extended bfp" esa +b31b sdbr RRE_FF "subtract long bfp" esa +ed000000001b sdb RXE_FRRD "subtract long bfp" esa +b30b sebr RRE_FF "subtract short bfp" esa +ed000000000b seb RXE_FRRD "subtract short bfp" esa +ed0000000012 tcxb RXE_FRRD "test data class extended bfp" esa +ed0000000011 tcdb RXE_FRRD "test data class long bfp" esa +ed0000000010 tceb RXE_FRRD "test data class short bfp" esa +b274 siga S_RD "signal adapter" esa +# are the following instructions confidential ?? +b2a6 cuutf RRE_RR "convert unicode to utf-8" esa +b2a7 cutfu RRE_RR "convert utf-8 to unicode" esa +ee plo SS_RRRDRD2 "perform locked operation" esa +b25a bsa RRE_RR "branch and set authority" esa +b277 rp S_RD "resume program" esa +0107 sckpf E "set clock programmable field" esa +b27d stsi S_RD "store system information" esa +01ff trap2 E "trap" esa +b2ff trap4 S_RD "trap4" esa +# Here are the new esame instructions: +b946 bctgr RRE_RR "branch on count 64" esame +b900 lpgr RRE_RR "load positive 64" esame +b910 lpgfr RRE_RR "load positive 64<32" esame +b901 lngr RRE_RR "load negative 64" esame +b911 lngfr RRE_RR "load negative 64<32" esame +b902 ltgr RRE_RR "load and test 64" esame +b912 ltgfr RRE_RR "load and test 64<32" esame +b903 lcgr RRE_RR "load complement 64" esame +b913 lcgfr RRE_RR "load complement 64<32" esame +b980 ngr RRE_RR "and 64" esame +b921 clgr RRE_RR "compare logical 64" esame +b931 clgfr RRE_RR "compare logical 64<32" esame +b981 ogr RRE_RR "or 64" esame +b982 xgr RRE_RR "exclusive or 64" esame +b904 lgr RRE_RR "load 64" esame +b914 lgfr RRE_RR "load 64<32" esame +b920 cgr RRE_RR "compare 64" esame +b930 cgfr RRE_RR "compare 64<32" esame +b908 agr RRE_RR "add 64" esame +b918 agfr RRE_RR "add 64<32" esame +b909 sgr RRE_RR "subtract 64" esame +b919 sgfr RRE_RR "subtract 64<32" esame +b90a algr RRE_RR "add logical 64" esame +b91a algfr RRE_RR "add logical 64<32" esame +b90b slgr RRE_RR "subtract logical 64" esame +b91b slgfr RRE_RR "subtract logical 64<32" esame +e30000000046 bctg RXE_RRRD "branch on count 64" esame +e3000000002e cvdg RXE_RRRD "convert to decimal 64" esame +e3000000000e cvbg RXE_RRRD "convert to binary 64" esame +e30000000024 stg RXE_RRRD "store 64" esame +e30000000080 ng RXE_RRRD "and 64" esame +e30000000021 clg RXE_RRRD "compare logical 64" esame +e30000000031 clgf RXE_RRRD "comparee logical 64<32" esame +e30000000081 og RXE_RRRD "or 64" esame +e30000000082 xg RXE_RRRD "exclusive or 64" esame +e30000000004 lg RXE_RRRD "load 64" esame +e30000000014 lgf RXE_RRRD "load 64<32" esame +e30000000015 lgh RXE_RRRD "load halfword 64" esame +e30000000020 cg RXE_RRRD "compare 64" esame +e30000000030 cgf RXE_RRRD "compare 64<32" esame +e30000000008 ag RXE_RRRD "add 64" esame +e30000000018 agf RXE_RRRD "add 64<32" esame +e30000000009 sg RXE_RRRD "subtract 64" esame +e30000000019 sgf RXE_RRRD "subtract 64<32" esame +e3000000000a alg RXE_RRRD "add logical 64" esame +e3000000001a algf RXE_RRRD "add logical 64<32" esame +e3000000000b slg RXE_RRRD "subtract logical 64" esame +e3000000001b slgf RXE_RRRD "subtract logical 64<32" esame +e3000000000c msg RXE_RRRD "multiply single 64" esame +e3000000001c msgf RXE_RRRD "multiply single 64<32" esame +ec0000000044 brxhg RIE_RRP "branch relative on index high 64" esame +ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" esame +eb0000000044 bxhg RSE_RRRD "branch on index high 64" esame +eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" esame +eb000000000c srlg RSE_RRRD "shift right single logical 64" esame +eb000000000d sllg RSE_RRRD "shift left single logical 64" esame +eb000000000a srag RSE_RRRD "shift right single 64" esame +eb000000000b slag RSE_RRRD "shift left single 64" esame +eb0000000024 stmg RSE_RRRD "store multiple 64" esame +eb0000000026 stmh RSE_RRRD "store multiple high" esame +eb0000000004 lmg RSE_RRRD "load multiple 64" esame +eb0000000096 lmh RSE_RRRD "load multiple high" esame +ef lmd SS_RRRDRD3 "load multiple disjoint" esame +eb000000000f tracg RSE_RRRD "trace 64" esame +e30000000003 lrag RXE_RRRD "load real address 64" esame +e50000000002 strag SSE_RDRD "store read address" esame +eb0000000025 stctg RSE_RRRD "store control 64" esame +eb000000002f lctlg RSE_RRRD "load control 64" esame +eb0000000030 csg RSE_RRRD "compare and swap 64" esame +eb000000003e cdsg RSE_RRRD "compare double and swap 64" esame +eb0000000020 clmh RSE_RURD "compare logical characters under mask high" esame +eb000000002c stcmh RSE_RURD "store characters under mask high" esame +eb0000000080 icmh RSE_RURD "insert characters under mask high" esame +a700 tmlh RI_RU "test under mask low high" esame +a702 tmhh RI_RU "test under mask high high" esame +a701 tmll RI_RU "test under mask low low" esame +a703 tmhl RI_RU "test under mask high low" esame +c004 brcl RIL_UP "branch relative on condition long" esame +c014 jgo RIL_0P "jump long on overflow / if ones" esame +c024 jgh RIL_0P "jump long on high" esame +c024 jgp RIL_0P "jump long on plus" esame +c034 jgnle RIL_0P "jump long on not low or equal" esame +c044 jgl RIL_0P "jump long on low" esame +c044 jgm RIL_0P "jump long on minus / if mixed" esame +c054 jgnhe RIL_0P "jump long on not high or equal" esame +c064 jglh RIL_0P "jump long on low or high" esame +c074 jgne RIL_0P "jump long on not equal" esame +c074 jgnz RIL_0P "jump long on not zero / if not zeros" esame +c084 jge RIL_0P "jump long on equal" esame +c084 jgz RIL_0P "jump long on zero / if zeros" esame +c094 jgnlh RIL_0P "jump long on not low or high" esame +c0a4 jghe RIL_0P "jump long on high or equal" esame +c0b4 jgnl RIL_0P "jump long on not low" esame +c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" esame +c0c4 jgle RIL_0P "jump long on low or equal" esame +c0d4 jgnh RIL_0P "jump long on not high" esame +c0d4 jgnp RIL_0P "jump long on not plus" esame +c0e4 jgno RIL_0P "jump long on not overflow / if not ones" esame +c0f4 jg RIL_0P "jump long" esame +c005 brasl RIL_RP "branch relative and save long" esame +a707 brctg RI_RP "branch relative on count 64" esame +a709 lghi RI_RI "load halfword immediate 64" esame +a70b aghi RI_RI "add halfword immediate 64" esame +a70d mghi RI_RI "multiply halfword immediate 64" esame +a70f cghi RI_RI "compare halfword immediate 64" esame +b925 sturg RRE_RR "store using real address 64" esame +b90e eregg RRE_RR "extract stacked registers 64" esame +b905 lurag RRE_RR "load using real address 64" esame +b90c msgr RRE_RR "multiply single 64" esame +b91c msgfr RRE_RR "multiply single 64<32" esame +b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" esame +b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" esame +b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" esame +b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" esame +b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" esame +b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" esame +b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" esame +b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" esame +b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" esame +b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" esame +b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" esame +b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" esame +010b tam E "test addressing mode" esame +010c sam24 E "set addressing mode 24" esame +010d sam31 E "set addressing mode 31" esame +010e sam64 E "set addressing mode 64" esame +a500 iihh RI_RU "insert immediate high high" esame +a501 iihl RI_RU "insert immediate high low" esame +a502 iilh RI_RU "insert immediate low high" esame +a503 iill RI_RU "insert immediate low low" esame +a504 nihh RI_RU "and immediate high high" esame +a505 nihl RI_RU "and immediate high low" esame +a506 nilh RI_RU "and immediate low high" esame +a507 nill RI_RU "and immediate low low" esame +a508 oihh RI_RU "or immediate high high" esame +a509 oihl RI_RU "or immediate high low" esame +a50a oilh RI_RU "or immediate low high" esame +a50b oill RI_RU "or immediate low low" esame +a50c llihh RI_RU "load logical immediate high high" esame +a50d llihl RI_RU "load logical immediate high low" esame +a50e llilh RI_RU "load logical immediate low high" esame +a50f llill RI_RU "load logical immediate low low" esame +b2b1 stfl S_RD "store facility list" esame +b2b2 lpswe S_RD "load psw extended" esame +b90d dsgr RRE_RR "divide single 64" esame +b90f lrvgr RRE_RR "load reversed 64" esame +b916 llgfr RRE_RR "load logical 64<32" esame +b917 llgtr RRE_RR "load logical thirty one bits" esame +b91d dsgfr RRE_RR "divide single 64<32" esame +b91f lrvr RRE_RR "load reversed 32" esame +b986 mlgr RRE_RR "multiply logical 64" esame +b987 dlgr RRE_RR "divide logical 64" esame +b988 alcgr RRE_RR "add logical with carry 64" esame +b989 slbgr RRE_RR "subtract logical with borrow 64" esame +b98d epsw RRE_RR "extract psw" esame +b996 mlr RRE_RR "multiply logical 32" esame +b997 dlr RRE_RR "divide logical 32" esame +b998 alcr RRE_RR "add logical with carry 32" esame +b999 slbr RRE_RR "subtract logical with borrow 32" esame +b99d esea RRE_R0 "extract and set extended authority" esame +c000 larl RIL_RP "load address relative long" esame +e3000000000d dsg RXE_RRRD "divide single 64" esame +e3000000000f lrvg RXE_RRRD "load reversed 64" esame +e30000000016 llgf RXE_RRRD "load logical 64<32" esame +e30000000017 llgt RXE_RRRD "load logical thirty one bits" esame +e3000000001d dsgf RXE_RRRD "divide single 64<32" esame +e3000000001e lrv RXE_RRRD "load reversed 32" esame +e3000000001f lrvh RXE_RRRD "load reversed 16" esame +e3000000002f strvg RXE_RRRD "store reversed 64" esame +e3000000003e strv RXE_RRRD "store reversed 32" esame +e3000000003f strvh RXE_RRRD "store reversed 64" esame +e30000000086 mlg RXE_RRRD "multiply logical 64" esame +e30000000087 dlg RXE_RRRD "divide logical 64" esame +e30000000088 alcg RXE_RRRD "add logical with carry 64" esame +e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" esame +e3000000008e stpq RXE_RRRD "store pair to quadword" esame +e3000000008f lpq RXE_RRRD "load pair from quadword" esame +e30000000096 ml RXE_RRRD "multiply logical 32" esame +e30000000097 dl RXE_RRRD "divide logical 32" esame +e30000000098 alc RXE_RRRD "add logical with carry 32" esame +e30000000099 slb RXE_RRRD "subtract logical with borrow 32" esame +e30000000090 llgc RXE_RRRD "load logical character" esame +e30000000091 llgh RXE_RRRD "load logical halfword" esame +eb000000001c rllg RSE_RRRD "rotate left single logical 64" esame +eb000000001d rll RSE_RRRD "rotate left single logical 32" esame +b278 stcke S_RD "store clock extended" esame +b2a5 tre RRE_RR "translate extended" esame +eb000000008e mvclu RSE_RRRD "move long unicode" esame +e9 pka SS_L0RDRD "pack ascii" esame +e1 pku SS_L0RDRD "pack unicode" esame +b993 troo RRE_RR "translate one to one" esame +b992 trot RRE_RR "translate one to two" esame +b991 trto RRE_RR "translate two to one" esame +b990 trtt RRE_RR "translate two to two" esame +ea unpka SS_L0RDRD "unpack ascii" esame +e2 unpku SS_L0RDRD "unpack unicode" esame +b358 thder RRE_RR "convert short bfp to long hfp" esame +b359 thdr RRE_RR "convert long bfp to long hfp" esame +b350 tbedr RRF_U0FF "convert long hfp to short bfp" esame +b351 tbdr RRF_U0FF "convert long hfp to long bfp" esame +b374 lzer RRE_R0 "load short zero" esame +b375 lzdr RRE_R0 "load long zero" esame +b376 lzxr RRE_R0 "load extended zero" esame diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c new file mode 100644 index 0000000..24d4b41 --- /dev/null +++ b/opcodes/sh-dis.c @@ -0,0 +1,734 @@ +/* Disassemble SH instructions. + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001 + Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "sh-opc.h" +#include "dis-asm.h" + +static void print_movxy + PARAMS ((sh_opcode_info *, int, int, fprintf_ftype, void *)); +static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); +static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); +static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); + +static void +print_movxy (op, rn, rm, fprintf_fn, stream) + sh_opcode_info *op; + int rn, rm; + fprintf_ftype fprintf_fn; + void *stream; +{ + int n; + + fprintf_fn (stream, "%s\t", op->name); + for (n = 0; n < 2; n++) + { + switch (op->arg[n]) + { + case A_IND_N: + fprintf_fn (stream, "@r%d", rn); + break; + case A_INC_N: + fprintf_fn (stream, "@r%d+", rn); + break; + case A_PMOD_N: + fprintf_fn (stream, "@r%d+r8", rn); + break; + case A_PMODY_N: + fprintf_fn (stream, "@r%d+r9", rn); + break; + case DSP_REG_M: + fprintf_fn (stream, "a%c", '0' + rm); + break; + case DSP_REG_X: + fprintf_fn (stream, "x%c", '0' + rm); + break; + case DSP_REG_Y: + fprintf_fn (stream, "y%c", '0' + rm); + break; + default: + abort (); + } + if (n == 0) + fprintf_fn (stream, ","); + } +} + +/* Print a double data transfer insn. INSN is just the lower three + nibbles of the insn, i.e. field a and the bit that indicates if + a parallel processing insn follows. + Return nonzero if a field b of a parallel processing insns follows. */ + +static void +print_insn_ddt (insn, info) + int insn; + struct disassemble_info *info; +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + + /* If this is just a nop, make sure to emit something. */ + if (insn == 0x000) + fprintf_fn (stream, "nopx\tnopy"); + + /* If a parallel processing insn was printed before, + and we got a non-nop, emit a tab. */ + if ((insn & 0x800) && (insn & 0x3ff)) + fprintf_fn (stream, "\t"); + + /* Check if either the x or y part is invalid. */ + if (((insn & 0xc) == 0 && (insn & 0x2a0)) + || ((insn & 3) == 0 && (insn & 0x150))) + fprintf_fn (stream, ".word 0x%x", insn); + else + { + static sh_opcode_info *first_movx, *first_movy; + sh_opcode_info *opx, *opy; + unsigned int insn_x, insn_y; + + if (! first_movx) + { + for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;) + first_movx++; + for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;) + first_movy++; + } + insn_x = (insn >> 2) & 0xb; + if (insn_x) + { + for (opx = first_movx; opx->nibbles[2] != insn_x;) + opx++; + print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, + fprintf_fn, stream); + } + insn_y = (insn & 3) | ((insn >> 1) & 8); + if (insn_y) + { + if (insn_x) + fprintf_fn (stream, "\t"); + for (opy = first_movy; opy->nibbles[2] != insn_y;) + opy++; + print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, + fprintf_fn, stream); + } + } +} + +static void +print_dsp_reg (rm, fprintf_fn, stream) + int rm; + fprintf_ftype fprintf_fn; + void *stream; +{ + switch (rm) + { + case A_A1_NUM: + fprintf_fn (stream, "a1"); + break; + case A_A0_NUM: + fprintf_fn (stream, "a0"); + break; + case A_X0_NUM: + fprintf_fn (stream, "x0"); + break; + case A_X1_NUM: + fprintf_fn (stream, "x1"); + break; + case A_Y0_NUM: + fprintf_fn (stream, "y0"); + break; + case A_Y1_NUM: + fprintf_fn (stream, "y1"); + break; + case A_M0_NUM: + fprintf_fn (stream, "m0"); + break; + case A_A1G_NUM: + fprintf_fn (stream, "a1g"); + break; + case A_M1_NUM: + fprintf_fn (stream, "m1"); + break; + case A_A0G_NUM: + fprintf_fn (stream, "a0g"); + break; + default: + fprintf_fn (stream, "0x%x", rm); + break; + } +} + +static void +print_insn_ppi (field_b, info) + int field_b; + struct disassemble_info *info; +{ + static char *sx_tab[] = { "x0", "x1", "a0", "a1" }; + static char *sy_tab[] = { "y0", "y1", "m0", "m1" }; + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned int nib1, nib2, nib3; + char *dc = NULL; + sh_opcode_info *op; + + if ((field_b & 0xe800) == 0) + { + fprintf_fn (stream, "psh%c\t#%d,", + field_b & 0x1000 ? 'a' : 'l', + (field_b >> 4) & 127); + print_dsp_reg (field_b & 0xf, fprintf_fn, stream); + return; + } + if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) + { + static char *du_tab[] = { "x0", "y0", "a0", "a1" }; + static char *se_tab[] = { "x0", "x1", "y0", "a1" }; + static char *sf_tab[] = { "y0", "y1", "x0", "a1" }; + static char *sg_tab[] = { "m0", "m1", "a0", "a1" }; + + if (field_b & 0x2000) + { + fprintf_fn (stream, "p%s %s,%s,%s\t", + (field_b & 0x1000) ? "add" : "sub", + sx_tab[(field_b >> 6) & 3], + sy_tab[(field_b >> 4) & 3], + du_tab[(field_b >> 0) & 3]); + } + fprintf_fn (stream, "pmuls%c%s,%s,%s", + field_b & 0x2000 ? ' ' : '\t', + se_tab[(field_b >> 10) & 3], + sf_tab[(field_b >> 8) & 3], + sg_tab[(field_b >> 2) & 3]); + return; + } + + nib1 = PPIC; + nib2 = field_b >> 12 & 0xf; + nib3 = field_b >> 8 & 0xf; + switch (nib3 & 0x3) + { + case 0: + dc = ""; + nib1 = PPI3; + break; + case 1: + dc = ""; + break; + case 2: + dc = "dct "; + nib3 -= 1; + break; + case 3: + dc = "dcf "; + nib3 -= 2; + break; + } + for (op = sh_table; op->name; op++) + { + if (op->nibbles[1] == nib1 + && op->nibbles[2] == nib2 + && op->nibbles[3] == nib3) + { + int n; + + fprintf_fn (stream, "%s%s\t", dc, op->name); + for (n = 0; n < 3 && op->arg[n] != A_END; n++) + { + if (n && op->arg[1] != A_END) + fprintf_fn (stream, ","); + switch (op->arg[n]) + { + case DSP_REG_N: + print_dsp_reg (field_b & 0xf, fprintf_fn, stream); + break; + case DSP_REG_X: + fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); + break; + case DSP_REG_Y: + fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); + break; + case A_MACH: + fprintf_fn (stream, "mach"); + break; + case A_MACL: + fprintf_fn (stream, "macl"); + break; + default: + abort (); + } + } + return; + } + } + /* Not found. */ + fprintf_fn (stream, ".word 0x%x", field_b); +} + +int +print_insn_sh (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned char insn[2]; + unsigned char nibs[4]; + int status; + bfd_vma relmask = ~(bfd_vma) 0; + sh_opcode_info *op; + int target_arch; + + switch (info->mach) + { + case bfd_mach_sh: + target_arch = arch_sh1; + /* SH coff object files lack information about the machine type, so + we end up with bfd_mach_sh unless it was set explicitly (which + could have happended if this is a call from gdb or the simulator.) */ + if (info->symbols + && bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour) + target_arch = arch_sh4; + break; + case bfd_mach_sh2: + target_arch = arch_sh2; + break; + case bfd_mach_sh_dsp: + target_arch = arch_sh_dsp; + break; + case bfd_mach_sh3: + target_arch = arch_sh3; + break; + case bfd_mach_sh3_dsp: + target_arch = arch_sh3_dsp; + break; + case bfd_mach_sh3e: + target_arch = arch_sh3e; + break; + case bfd_mach_sh4: + target_arch = arch_sh4; + break; + case bfd_mach_sh5: +#ifdef INCLUDE_SHMEDIA + status = print_insn_sh64 (memaddr, info); + if (status != -2) + return status; +#endif + /* When we get here for sh64, it's because we want to disassemble + SHcompact, i.e. arch_sh4. */ + target_arch = arch_sh4; + break; + default: + abort (); + } + + status = info->read_memory_func (memaddr, insn, 2, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + { + nibs[0] = (insn[1] >> 4) & 0xf; + nibs[1] = insn[1] & 0xf; + + nibs[2] = (insn[0] >> 4) & 0xf; + nibs[3] = insn[0] & 0xf; + } + else + { + nibs[0] = (insn[0] >> 4) & 0xf; + nibs[1] = insn[0] & 0xf; + + nibs[2] = (insn[1] >> 4) & 0xf; + nibs[3] = insn[1] & 0xf; + } + + if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up) + { + if (nibs[1] & 8) + { + int field_b; + + status = info->read_memory_func (memaddr + 2, insn, 2, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr + 2, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + field_b = insn[1] << 8 | insn[0]; + else + field_b = insn[0] << 8 | insn[1]; + + print_insn_ppi (field_b, info); + print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); + return 4; + } + print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); + return 2; + } + for (op = sh_table; op->name; op++) + { + int n; + int imm = 0; + int rn = 0; + int rm = 0; + int rb = 0; + int disp_pc; + bfd_vma disp_pc_addr = 0; + + if ((op->arch & target_arch) == 0) + goto fail; + for (n = 0; n < 4; n++) + { + int i = op->nibbles[n]; + + if (i < 16) + { + if (nibs[n] == i) + continue; + goto fail; + } + switch (i) + { + case BRANCH_8: + imm = (nibs[2] << 4) | (nibs[3]); + if (imm & 0x80) + imm |= ~0xff; + imm = ((char) imm) * 2 + 4; + goto ok; + case BRANCH_12: + imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); + if (imm & 0x800) + imm |= ~0xfff; + imm = imm * 2 + 4; + goto ok; + case IMM0_4: + case IMM1_4: + imm = nibs[3]; + goto ok; + case IMM0_4BY2: + case IMM1_4BY2: + imm = nibs[3] << 1; + goto ok; + case IMM0_4BY4: + case IMM1_4BY4: + imm = nibs[3] << 2; + goto ok; + case IMM0_8: + case IMM1_8: + imm = (nibs[2] << 4) | nibs[3]; + goto ok; + case PCRELIMM_8BY2: + imm = ((nibs[2] << 4) | nibs[3]) << 1; + relmask = ~(bfd_vma) 1; + goto ok; + case PCRELIMM_8BY4: + imm = ((nibs[2] << 4) | nibs[3]) << 2; + relmask = ~(bfd_vma) 3; + goto ok; + case IMM0_8BY2: + case IMM1_8BY2: + imm = ((nibs[2] << 4) | nibs[3]) << 1; + goto ok; + case IMM0_8BY4: + case IMM1_8BY4: + imm = ((nibs[2] << 4) | nibs[3]) << 2; + goto ok; + case REG_N: + rn = nibs[n]; + break; + case REG_M: + rm = nibs[n]; + break; + case REG_NM: + rn = (nibs[n] & 0xc) >> 2; + rm = (nibs[n] & 0x3); + break; + case REG_B: + rb = nibs[n] & 0x07; + break; + case SDT_REG_N: + /* sh-dsp: single data transfer. */ + rn = nibs[n]; + if ((rn & 0xc) != 4) + goto fail; + rn = rn & 0x3; + rn |= (!(rn & 2)) << 2; + break; + case PPI: + case REPEAT: + goto fail; + default: + abort (); + } + } + + ok: + fprintf_fn (stream, "%s\t", op->name); + disp_pc = 0; + for (n = 0; n < 3 && op->arg[n] != A_END; n++) + { + if (n && op->arg[1] != A_END) + fprintf_fn (stream, ","); + switch (op->arg[n]) + { + case A_IMM: + fprintf_fn (stream, "#%d", (char) (imm)); + break; + case A_R0: + fprintf_fn (stream, "r0"); + break; + case A_REG_N: + fprintf_fn (stream, "r%d", rn); + break; + case A_INC_N: + fprintf_fn (stream, "@r%d+", rn); + break; + case A_DEC_N: + fprintf_fn (stream, "@-r%d", rn); + break; + case A_IND_N: + fprintf_fn (stream, "@r%d", rn); + break; + case A_DISP_REG_N: + fprintf_fn (stream, "@(%d,r%d)", imm, rn); + break; + case A_PMOD_N: + fprintf_fn (stream, "@r%d+r8", rn); + break; + case A_REG_M: + fprintf_fn (stream, "r%d", rm); + break; + case A_INC_M: + fprintf_fn (stream, "@r%d+", rm); + break; + case A_DEC_M: + fprintf_fn (stream, "@-r%d", rm); + break; + case A_IND_M: + fprintf_fn (stream, "@r%d", rm); + break; + case A_DISP_REG_M: + fprintf_fn (stream, "@(%d,r%d)", imm, rm); + break; + case A_REG_B: + fprintf_fn (stream, "r%d_bank", rb); + break; + case A_DISP_PC: + disp_pc = 1; + disp_pc_addr = imm + 4 + (memaddr & relmask); + (*info->print_address_func) (disp_pc_addr, info); + break; + case A_IND_R0_REG_N: + fprintf_fn (stream, "@(r0,r%d)", rn); + break; + case A_IND_R0_REG_M: + fprintf_fn (stream, "@(r0,r%d)", rm); + break; + case A_DISP_GBR: + fprintf_fn (stream, "@(%d,gbr)", imm); + break; + case A_R0_GBR: + fprintf_fn (stream, "@(r0,gbr)"); + break; + case A_BDISP12: + case A_BDISP8: + (*info->print_address_func) (imm + memaddr, info); + break; + case A_SR: + fprintf_fn (stream, "sr"); + break; + case A_GBR: + fprintf_fn (stream, "gbr"); + break; + case A_VBR: + fprintf_fn (stream, "vbr"); + break; + case A_DSR: + fprintf_fn (stream, "dsr"); + break; + case A_MOD: + fprintf_fn (stream, "mod"); + break; + case A_RE: + fprintf_fn (stream, "re"); + break; + case A_RS: + fprintf_fn (stream, "rs"); + break; + case A_A0: + fprintf_fn (stream, "a0"); + break; + case A_X0: + fprintf_fn (stream, "x0"); + break; + case A_X1: + fprintf_fn (stream, "x1"); + break; + case A_Y0: + fprintf_fn (stream, "y0"); + break; + case A_Y1: + fprintf_fn (stream, "y1"); + break; + case DSP_REG_M: + print_dsp_reg (rm, fprintf_fn, stream); + break; + case A_SSR: + fprintf_fn (stream, "ssr"); + break; + case A_SPC: + fprintf_fn (stream, "spc"); + break; + case A_MACH: + fprintf_fn (stream, "mach"); + break; + case A_MACL: + fprintf_fn (stream, "macl"); + break; + case A_PR: + fprintf_fn (stream, "pr"); + break; + case A_SGR: + fprintf_fn (stream, "sgr"); + break; + case A_DBR: + fprintf_fn (stream, "dbr"); + break; + case F_REG_N: + fprintf_fn (stream, "fr%d", rn); + break; + case F_REG_M: + fprintf_fn (stream, "fr%d", rm); + break; + case DX_REG_N: + if (rn & 1) + { + fprintf_fn (stream, "xd%d", rn & ~1); + break; + } + case D_REG_N: + fprintf_fn (stream, "dr%d", rn); + break; + case DX_REG_M: + if (rm & 1) + { + fprintf_fn (stream, "xd%d", rm & ~1); + break; + } + case D_REG_M: + fprintf_fn (stream, "dr%d", rm); + break; + case FPSCR_M: + case FPSCR_N: + fprintf_fn (stream, "fpscr"); + break; + case FPUL_M: + case FPUL_N: + fprintf_fn (stream, "fpul"); + break; + case F_FR0: + fprintf_fn (stream, "fr0"); + break; + case V_REG_N: + fprintf_fn (stream, "fv%d", rn * 4); + break; + case V_REG_M: + fprintf_fn (stream, "fv%d", rm * 4); + break; + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; + default: + abort (); + } + } + +#if 0 + /* This code prints instructions in delay slots on the same line + as the instruction which needs the delay slots. This can be + confusing, since other disassembler don't work this way, and + it means that the instructions are not all in a line. So I + disabled it. Ian. */ + if (!(info->flags & 1) + && (op->name[0] == 'j' + || (op->name[0] == 'b' + && (op->name[1] == 'r' + || op->name[1] == 's')) + || (op->name[0] == 'r' && op->name[1] == 't') + || (op->name[0] == 'b' && op->name[2] == '.'))) + { + info->flags |= 1; + fprintf_fn (stream, "\t(slot "); + print_insn_sh (memaddr + 2, info); + info->flags &= ~1; + fprintf_fn (stream, ")"); + return 4; + } +#endif + + if (disp_pc && strcmp (op->name, "mova") != 0) + { + int size; + bfd_byte bytes[4]; + + if (relmask == ~(bfd_vma) 1) + size = 2; + else + size = 4; + status = info->read_memory_func (disp_pc_addr, bytes, size, info); + if (status == 0) + { + unsigned int val; + + if (size == 2) + { + if (info->endian == BFD_ENDIAN_LITTLE) + val = bfd_getl16 (bytes); + else + val = bfd_getb16 (bytes); + } + else + { + if (info->endian == BFD_ENDIAN_LITTLE) + val = bfd_getl32 (bytes); + else + val = bfd_getb32 (bytes); + } + fprintf_fn (stream, "\t! 0x%x", val); + } + } + + return 2; + fail: + ; + + } + fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); + return 2; +} diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h new file mode 100644 index 0000000..abdc464 --- /dev/null +++ b/opcodes/sh-opc.h @@ -0,0 +1,842 @@ +/* Definitions for SH opcodes. + Copyright 1993, 1994, 1995, 1997, 1999, 2000 + Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +typedef enum { + HEX_0, + HEX_1, + HEX_2, + HEX_3, + HEX_4, + HEX_5, + HEX_6, + HEX_7, + HEX_8, + HEX_9, + HEX_A, + HEX_B, + HEX_C, + HEX_D, + HEX_E, + HEX_F, + REG_N, + REG_M, + SDT_REG_N, + REG_NM, + REG_B, + BRANCH_12, + BRANCH_8, + IMM0_4, + IMM0_4BY2, + IMM0_4BY4, + IMM1_4, + IMM1_4BY2, + IMM1_4BY4, + PCRELIMM_8BY2, + PCRELIMM_8BY4, + IMM0_8, + IMM0_8BY2, + IMM0_8BY4, + IMM1_8, + IMM1_8BY2, + IMM1_8BY4, + PPI, + NOPX, + NOPY, + MOVX, + MOVY, + PSH, + PMUL, + PPI3, + PDC, + PPIC, + REPEAT +} sh_nibble_type; + +typedef enum { + A_END, + A_BDISP12, + A_BDISP8, + A_DEC_M, + A_DEC_N, + A_DISP_GBR, + A_PC, + A_DISP_PC, + A_DISP_PC_ABS, + A_DISP_REG_M, + A_DISP_REG_N, + A_GBR, + A_IMM, + A_INC_M, + A_INC_N, + A_IND_M, + A_IND_N, + A_PMOD_N, + A_PMODY_N, + A_IND_R0_REG_M, + A_IND_R0_REG_N, + A_MACH, + A_MACL, + A_PR, + A_R0, + A_R0_GBR, + A_REG_M, + A_REG_N, + A_REG_B, + A_SR, + A_VBR, + A_MOD, + A_RE, + A_RS, + A_DSR, + DSP_REG_M, + DSP_REG_N, + DSP_REG_X, + DSP_REG_Y, + DSP_REG_E, + DSP_REG_F, + DSP_REG_G, + A_A0, + A_X0, + A_X1, + A_Y0, + A_Y1, + A_SSR, + A_SPC, + A_SGR, + A_DBR, + F_REG_N, + F_REG_M, + D_REG_N, + D_REG_M, + X_REG_N, /* Only used for argument parsing */ + X_REG_M, /* Only used for argument parsing */ + DX_REG_N, + DX_REG_M, + V_REG_N, + V_REG_M, + XMTRX_M4, + F_FR0, + FPUL_N, + FPUL_M, + FPSCR_N, + FPSCR_M +} sh_arg_type; + +typedef enum { + A_A1_NUM = 5, + A_A0_NUM = 7, + A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, + A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM +} sh_dsp_reg_nums; + +#define arch_sh1 0x0001 +#define arch_sh2 0x0002 +#define arch_sh3 0x0004 +#define arch_sh3e 0x0008 +#define arch_sh4 0x0010 +#define arch_sh_dsp 0x0100 +#define arch_sh3_dsp 0x0200 + +#define arch_sh1_up (arch_sh1 | arch_sh2_up) +#define arch_sh2_up (arch_sh2 | arch_sh3_up | arch_sh_dsp) +#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp) +#define arch_sh3e_up (arch_sh3e | arch_sh4_up) +#define arch_sh4_up arch_sh4 + +#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) +#define arch_sh3_dsp_up arch_sh3_dsp + +typedef struct { + char *name; + sh_arg_type arg[4]; + sh_nibble_type nibbles[4]; + int arch; +} sh_opcode_info; + +#ifdef DEFINE_TABLE + +sh_opcode_info sh_table[] = { + +/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up}, + +/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, + +/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up}, + +/* 0011nnnnmmmm1111 addv ,*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up}, + +/* 11001001i8*1.... and #,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up}, + +/* 0010nnnnmmmm1001 and , */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up}, + +/* 11001101i8*1.... and.b #,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up}, + +/* 1010i12......... bra */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up}, + +/* 1011i12......... bsr */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up}, + +/* 10001001i8p1.... bt */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up}, + +/* 10001011i8p1.... bf */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up}, + +/* 10001101i8p1.... bt.s */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, + +/* 10001101i8p1.... bt/s */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, + +/* 10001111i8p1.... bf.s */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, + +/* 10001111i8p1.... bf/s */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, + +/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, + +/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, + +/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up}, + +/* 10001000i8*1.... cmp/eq #,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up}, + +/* 0011nnnnmmmm0000 cmp/eq ,*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up}, + +/* 0011nnnnmmmm0011 cmp/ge ,*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up}, + +/* 0011nnnnmmmm0111 cmp/gt ,*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up}, + +/* 0011nnnnmmmm0110 cmp/hi ,*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up}, + +/* 0011nnnnmmmm0010 cmp/hs ,*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up}, + +/* 0100nnnn00010101 cmp/pl */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up}, + +/* 0100nnnn00010001 cmp/pz */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up}, + +/* 0010nnnnmmmm1100 cmp/str ,*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up}, + +/* 0010nnnnmmmm0111 div0s ,*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up}, + +/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up}, + +/* 0011nnnnmmmm0100 div1 ,*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up}, + +/* 0110nnnnmmmm1110 exts.b ,*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up}, + +/* 0110nnnnmmmm1111 exts.w ,*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up}, + +/* 0110nnnnmmmm1100 extu.b ,*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up}, + +/* 0110nnnnmmmm1101 extu.w ,*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, + +/* 0100nnnn00101011 jmp @ */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, + +/* 0100nnnn00001011 jsr @ */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, + +/* 0100nnnn00001110 ldc ,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up}, + +/* 0100nnnn00011110 ldc ,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, + +/* 0100nnnn00101110 ldc ,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, + +/* 0100nnnn01011110 ldc ,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, + +/* 0100nnnn01111110 ldc ,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, + +/* 0100nnnn01101110 ldc ,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, + +/* 0100nnnn00111110 ldc ,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_up}, + +/* 0100nnnn01001110 ldc ,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, + +/* 0100nnnn11111010 ldc ,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_up}, + +/* 0100nnnn1xxx1110 ldc ,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, + +/* 0100nnnn00000111 ldc.l @+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up}, + +/* 0100nnnn00010111 ldc.l @+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up}, + +/* 0100nnnn00100111 ldc.l @+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, + +/* 0100nnnn01010111 ldc.l @+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, + +/* 0100nnnn01110111 ldc.l @+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, + +/* 0100nnnn01100111 ldc.l @+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, + +/* 0100nnnn00110111 ldc.l @+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_up}, + +/* 0100nnnn01000111 ldc.l @+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, + +/* 0100nnnn11110110 ldc.l @+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_up}, + +/* 0100nnnn1xxx0111 ldc.l ,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, + +/* 10001110i8p2.... ldre @(,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, + +/* 10001100i8p2.... ldrs @(,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}, + +/* 0100nnnn00001010 lds ,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up}, + +/* 0100nnnn00011010 lds ,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up}, + +/* 0100nnnn00101010 lds ,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up}, + +/* 0100nnnn01101010 lds ,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn01111010 lds ,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10001010 lds ,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10011010 lds ,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10101010 lds ,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10111010 lds ,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn01011010 lds ,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh3e_up}, + +/* 0100nnnn01101010 lds ,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh3e_up}, + +/* 0100nnnn00000110 lds.l @+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, + +/* 0100nnnn00010110 lds.l @+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up}, + +/* 0100nnnn00100110 lds.l @+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up}, + +/* 0100nnnn01100110 lds.l @+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn01110110 lds.l @+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10000110 lds.l @+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10010110 lds.l @+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10100110 lds.l @+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10110110 lds.l @+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn01010110 lds.l @+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh3e_up}, + +/* 0100nnnn01100110 lds.l @+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh3e_up}, + +/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, + +/* 0100nnnnmmmm1111 mac.w @+,@+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, + +/* 1110nnnni8*1.... mov #, */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up}, + +/* 0110nnnnmmmm0011 mov , */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up}, + +/* 0000nnnnmmmm0100 mov.b ,@(R0,)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up}, + +/* 0010nnnnmmmm0100 mov.b ,@-*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up}, + +/* 0010nnnnmmmm0000 mov.b ,@*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up}, + +/* 10000100mmmmi4*1 mov.b @(,),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up}, + +/* 11000100i8*1.... mov.b @(,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up}, + +/* 0000nnnnmmmm1100 mov.b @(R0,),*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up}, + +/* 0110nnnnmmmm0100 mov.b @+,*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up}, + +/* 0110nnnnmmmm0000 mov.b @,*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up}, + +/* 10000000mmmmi4*1 mov.b R0,@(,)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up}, + +/* 11000000i8*1.... mov.b R0,@(,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up}, + +/* 0001nnnnmmmmi4*4 mov.l ,@(,)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up}, + +/* 0000nnnnmmmm0110 mov.l ,@(R0,)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up}, + +/* 0010nnnnmmmm0110 mov.l ,@-*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up}, + +/* 0010nnnnmmmm0010 mov.l ,@*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up}, + +/* 0101nnnnmmmmi4*4 mov.l @(,),*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up}, + +/* 11000110i8*4.... mov.l @(,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up}, + +/* 1101nnnni8p4.... mov.l @(,PC),*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up}, + +/* 0000nnnnmmmm1110 mov.l @(R0,),*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up}, + +/* 0110nnnnmmmm0110 mov.l @+,*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up}, + +/* 0110nnnnmmmm0010 mov.l @,*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up}, + +/* 11000010i8*4.... mov.l R0,@(,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up}, + +/* 0000nnnnmmmm0101 mov.w ,@(R0,)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up}, + +/* 0010nnnnmmmm0101 mov.w ,@-*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up}, + +/* 0010nnnnmmmm0001 mov.w ,@*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up}, + +/* 10000101mmmmi4*2 mov.w @(,),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up}, + +/* 11000101i8*2.... mov.w @(,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up}, + +/* 1001nnnni8p2.... mov.w @(,PC),*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up}, + +/* 0000nnnnmmmm1101 mov.w @(R0,),*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up}, + +/* 0110nnnnmmmm0101 mov.w @+,*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up}, + +/* 0110nnnnmmmm0001 mov.w @,*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up}, + +/* 10000001mmmmi4*2 mov.w R0,@(,)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up}, + +/* 11000001i8*2.... mov.w R0,@(,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, + +/* 11000111i8p4.... mova @(,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, +/* 0000nnnn11000011 movca.l R0,@ */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up}, + + +/* 0000nnnn00101001 movt */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, + +/* 0010nnnnmmmm1111 muls.w ,*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, +/* 0010nnnnmmmm1111 muls ,*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, + +/* 0000nnnnmmmm0111 mul.l ,*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, + +/* 0010nnnnmmmm1110 mulu.w ,*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, +/* 0010nnnnmmmm1110 mulu ,*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, + +/* 0110nnnnmmmm1011 neg , */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up}, + +/* 0110nnnnmmmm1010 negc ,*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up}, + +/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, + +/* 0110nnnnmmmm0111 not , */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, +/* 0000nnnn10010011 ocbi @ */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_up}, + +/* 0000nnnn10100011 ocbp @ */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_up}, + +/* 0000nnnn10110011 ocbwb @ */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up}, + + +/* 11001011i8*1.... or #,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, + +/* 0010nnnnmmmm1011 or , */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up}, + +/* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, + +/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up}, + +/* 0100nnnn00100100 rotcl */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, + +/* 0100nnnn00100101 rotcr */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up}, + +/* 0100nnnn00000100 rotl */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up}, + +/* 0100nnnn00000101 rotr */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up}, + +/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up}, + +/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, + +/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, +/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, + +/* 0100nnnn00010100 setrc */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, + +/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}, + +/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, + +/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_up}, + +/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_up}, + +/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, + +/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up}, + +/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up}, + +/* 0100nnnn00101000 shll16 */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up}, + +/* 0100nnnn00001000 shll2 */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up}, + +/* 0100nnnn00011000 shll8 */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up}, + +/* 0100nnnn00000001 shlr */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up}, + +/* 0100nnnn00101001 shlr16 */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up}, + +/* 0100nnnn00001001 shlr2 */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up}, + +/* 0100nnnn00011001 shlr8 */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up}, + +/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up}, + +/* 0000nnnn00000010 stc SR, */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up}, + +/* 0000nnnn00010010 stc GBR, */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up}, + +/* 0000nnnn00100010 stc VBR, */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up}, + +/* 0000nnnn01010010 stc MOD, */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, + +/* 0000nnnn01110010 stc RE, */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, + +/* 0000nnnn01100010 stc RS, */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, + +/* 0000nnnn00110010 stc SSR, */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_up}, + +/* 0000nnnn01000010 stc SPC, */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, + +/* 0000nnnn00111010 stc SGR, */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_up}, + +/* 0000nnnn11111010 stc DBR, */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_up}, + +/* 0000nnnn1xxx0010 stc Rn_BANK, */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, + +/* 0100nnnn00000011 stc.l SR,@- */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up}, + +/* 0100nnnn00100011 stc.l VBR,@- */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up}, + +/* 0100nnnn01010011 stc.l MOD,@- */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, + +/* 0100nnnn01110011 stc.l RE,@- */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, + +/* 0100nnnn01100011 stc.l RS,@- */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, + +/* 0100nnnn00110011 stc.l SSR,@- */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_up}, + +/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_up}, + +/* 0100nnnn00010011 stc.l GBR,@- */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, + +/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up}, + +/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_up}, + +/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, + +/* 0000nnnn00001010 sts MACH, */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up}, + +/* 0000nnnn00011010 sts MACL, */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up}, + +/* 0000nnnn00101010 sts PR, */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up}, + +/* 0000nnnn01101010 sts DSR, */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn01111010 sts A0, */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10001010 sts X0, */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10011010 sts X1, */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10101010 sts Y0, */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10111010 sts Y1, */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn01011010 sts FPUL, */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh3e_up}, + +/* 0000nnnn01101010 sts FPSCR, */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh3e_up}, + +/* 0100nnnn00000010 sts.l MACH,@-*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, + +/* 0100nnnn00010010 sts.l MACL,@-*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up}, + +/* 0100nnnn00100010 sts.l PR,@- */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up}, + +/* 0100nnnn01100110 sts.l DSR,@- */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn01110110 sts.l A0,@- */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10000110 sts.l X0,@- */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10010110 sts.l X1,@- */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10100110 sts.l Y0,@- */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10110110 sts.l Y1,@- */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn01010010 sts.l FPUL,@-*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh3e_up}, + +/* 0100nnnn01100010 sts.l FPSCR,@-*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh3e_up}, + +/* 0011nnnnmmmm1000 sub , */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, + +/* 0011nnnnmmmm1010 subc ,*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up}, + +/* 0011nnnnmmmm1011 subv ,*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up}, + +/* 0110nnnnmmmm1000 swap.b ,*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up}, + +/* 0110nnnnmmmm1001 swap.w ,*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, + +/* 0100nnnn00011011 tas.b @ */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, + +/* 11000011i8*1.... trapa # */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up}, + +/* 11001000i8*1.... tst #,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up}, + +/* 0010nnnnmmmm1000 tst , */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up}, + +/* 11001100i8*1.... tst.b #,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up}, + +/* 11001010i8*1.... xor #,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up}, + +/* 0010nnnnmmmm1010 xor , */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up}, + +/* 11001110i8*1.... xor.b #,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up}, + +/* 0010nnnnmmmm1101 xtrct ,*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up}, + +/* 0000nnnnmmmm0111 mul.l ,*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up}, + +/* 0100nnnn00010000 dt */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, + +/* 0011nnnnmmmm1101 dmuls.l ,*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, + +/* 0011nnnnmmmm0101 dmulu.l ,*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, + +/* 0000nnnnmmmm1111 mac.l @+,@+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, + +/* 0000nnnn00100011 braf */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, + +/* 0000nnnn00000011 bsrf */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, + +/* 111101nnmmmm0000 movs.w @-, */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, + +/* 111101nnmmmm0001 movs.w @, */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, + +/* 111101nnmmmm0010 movs.w @+, */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, + +/* 111101nnmmmm0011 movs.w @+r8, */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, + +/* 111101nnmmmm0100 movs.w ,@- */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, + +/* 111101nnmmmm0101 movs.w ,@ */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, + +/* 111101nnmmmm0110 movs.w ,@+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, + +/* 111101nnmmmm0111 movs.w ,@+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, + +/* 111101nnmmmm1000 movs.l @-, */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, + +/* 111101nnmmmm1001 movs.l @, */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, + +/* 111101nnmmmm1010 movs.l @+, */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, + +/* 111101nnmmmm1011 movs.l @+r8, */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, + +/* 111101nnmmmm1100 movs.l ,@- */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, + +/* 111101nnmmmm1101 movs.l ,@ */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, + +/* 111101nnmmmm1110 movs.l ,@+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, + +/* 111101nnmmmm1111 movs.l ,@+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, + +/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, +/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, +/* n*m*0*01** movx.w @, */ {"movx.w",{A_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, +/* n*m*0*10** movx.w @+, */ {"movx.w",{A_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, +/* n*m*0*11** movx.w @+r8, */ {"movx.w",{A_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, +/* n*m*1*01** movx.w ,@ */ {"movx.w",{DSP_REG_M,A_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, +/* n*m*1*10** movx.w ,@+ */ {"movx.w",{DSP_REG_M,A_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, +/* n*m*1*11** movx.w ,@+r8 */ {"movx.w",{DSP_REG_M,A_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, +/* *n*m*0**01 movy.w @, */ {"movy.w",{A_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, +/* *n*m*0**10 movy.w @+, */ {"movy.w",{A_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, +/* *n*m*0**11 movy.w @+r9, */ {"movy.w",{A_PMODY_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, +/* *n*m*1**01 movy.w ,@ */ {"movy.w",{DSP_REG_M,A_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, +/* *n*m*1**10 movy.w ,@+ */ {"movy.w",{DSP_REG_M,A_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, +/* *n*m*1**11 movy.w ,@+r9 */ {"movy.w",{DSP_REG_M,A_PMODY_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, + +/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, +/* 10100000xxyynnnn psubc ,, */ +{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}, +/* 10110000xxyynnnn paddc ,, */ +{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}, +/* 10000100xxyynnnn pcmp , */ +{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}, +/* 10100100xxyynnnn pwsb ,, */ +{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}, +/* 10110100xxyynnnn pwad ,, */ +{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, +/* 10001000xxyynnnn pabs , */ +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up}, +/* 10101000xxyynnnn pabs , */ +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up}, +/* 10011000xxyynnnn prnd , */ +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up}, +/* 10111000xxyynnnn prnd , */ +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up}, + +{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, +{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, + +/* 10000001xxyynnnn pshl ,, */ +{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}, +/* 00000iiiiiiinnnn pshl #, */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, +/* 10010001xxyynnnn psha ,, */ +{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}, +/* 00010iiiiiiinnnn psha #, */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, +/* 10100001xxyynnnn psub ,, */ +{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, +/* 10110001xxyynnnn padd ,, */ +{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, +/* 10010101xxyynnnn pand ,, */ +{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}, +/* 10100101xxyynnnn pxor ,, */ +{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}, +/* 10110101xxyynnnn por ,, */ +{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}, +/* 10001001xxyynnnn pdec , */ +{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, +/* 10101001xxyynnnn pdec , */ +{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, +/* 10011001xxyynnnn pinc , */ +{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up}, +/* 10111001xxyynnnn pinc , */ +{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up}, +/* 10001101xxyynnnn pclr */ +{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, +/* 10011101xxyynnnn pdmsb , */ +{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D}, arch_sh_dsp_up}, +/* 10111101xxyynnnn pdmsb , */ +{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up}, +/* 11001001xxyynnnn pneg , */ +{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, +/* 11101001xxyynnnn pneg , */ +{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}, +/* 11011001xxyynnnn pcopy , */ +{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}, +/* 11111001xxyynnnn pcopy , */ +{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}, +/* 11001101xxyynnnn psts MACH, */ +{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}, +/* 11011101xxyynnnn psts MACL, */ +{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}, +/* 11101101xxyynnnn plds ,MACH */ +{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, +/* 11111101xxyynnnn plds ,MACL */ +{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, + +/* 1111nnnn01011101 fabs */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh3e_up}, +/* 1111nnnn01011101 fabs */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up}, + +/* 1111nnnnmmmm0000 fadd ,*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh3e_up}, +/* 1111nnn0mmm00000 fadd ,*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up}, + +/* 1111nnnnmmmm0100 fcmp/eq ,*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh3e_up}, +/* 1111nnn0mmm00100 fcmp/eq ,*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up}, + +/* 1111nnnnmmmm0101 fcmp/gt ,*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh3e_up}, +/* 1111nnn0mmm00101 fcmp/gt ,*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up}, + +/* 1111nnn010111101 fcnvds ,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up}, + +/* 1111nnn010101101 fcnvsd FPUL,*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up}, + +/* 1111nnnnmmmm0011 fdiv ,*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh3e_up}, +/* 1111nnn0mmm00011 fdiv ,*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up}, + +/* 1111nnmm11101101 fipr ,*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, + +/* 1111nnnn10001101 fldi0 */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh3e_up}, + +/* 1111nnnn10011101 fldi1 */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh3e_up}, + +/* 1111nnnn00011101 flds ,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh3e_up}, + +/* 1111nnnn00101101 float FPUL,*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh3e_up}, +/* 1111nnnn00101101 float FPUL,*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up}, + +/* 1111nnnnmmmm1110 fmac FR0,,*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh3e_up}, + +/* 1111nnnnmmmm1100 fmov ,*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh3e_up}, +/* 1111nnnnmmmm1100 fmov ,*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up}, + +/* 1111nnnnmmmm1000 fmov @,*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, +/* 1111nnnnmmmm1000 fmov @,*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, + +/* 1111nnnnmmmm1010 fmov ,@*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, +/* 1111nnnnmmmm1010 fmov ,@*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, + +/* 1111nnnnmmmm1001 fmov @+,*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, +/* 1111nnnnmmmm1001 fmov @+,*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, + +/* 1111nnnnmmmm1011 fmov ,@-*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, +/* 1111nnnnmmmm1011 fmov ,@-*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, + +/* 1111nnnnmmmm0110 fmov @(R0,),*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, +/* 1111nnnnmmmm0110 fmov @(R0,),*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, + +/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, +/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, + +/* 1111nnnnmmmm1000 fmov.d @,*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, + +/* 1111nnnnmmmm1010 fmov.d ,@*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, + +/* 1111nnnnmmmm1001 fmov.d @+,*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, + +/* 1111nnnnmmmm1011 fmov.d ,@-*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, + +/* 1111nnnnmmmm0110 fmov.d @(R0,),*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, + +/* 1111nnnnmmmm0111 fmov.d ,@(R0,)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, + +/* 1111nnnnmmmm1000 fmov.s @,*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, + +/* 1111nnnnmmmm1010 fmov.s ,@*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, + +/* 1111nnnnmmmm1001 fmov.s @+,*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, + +/* 1111nnnnmmmm1011 fmov.s ,@-*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, + +/* 1111nnnnmmmm0110 fmov.s @(R0,),*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, + +/* 1111nnnnmmmm0111 fmov.s ,@(R0,)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, + +/* 1111nnnnmmmm0010 fmul ,*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh3e_up}, +/* 1111nnn0mmm00010 fmul ,*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up}, + +/* 1111nnnn01001101 fneg */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh3e_up}, +/* 1111nnnn01001101 fneg */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up}, + +/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, + +/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up}, + +/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up}, +/* 1111nnnn01101101 fsqrt */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up}, + +/* 1111nnnn00001101 fsts FPUL,*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh3e_up}, + +/* 1111nnnnmmmm0001 fsub ,*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh3e_up}, +/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up}, + +/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh3e_up}, +/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up}, + +/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up}, + +{ 0, {0}, {0}, 0 } +}; + +#endif diff --git a/opcodes/sh64-dis.c b/opcodes/sh64-dis.c new file mode 100644 index 0000000..10c0f31 --- /dev/null +++ b/opcodes/sh64-dis.c @@ -0,0 +1,638 @@ +/* Disassemble SH64 instructions. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#include "dis-asm.h" +#include "sysdep.h" +#include "sh64-opc.h" +#include "libiberty.h" + +/* We need to refer to the ELF header structure. */ +#include "elf-bfd.h" +#include "elf/sh.h" + +#define ELF_MODE32_CODE_LABEL_P(SYM) \ + (((elf_symbol_type *) (SYM))->internal_elf_sym.st_other & STO_SH5_ISA32) + +#define SAVED_MOVI_R(INFO) \ + (((struct sh64_disassemble_info *) ((INFO)->private_data))->address_reg) + +#define SAVED_MOVI_IMM(INFO) \ + (((struct sh64_disassemble_info *) ((INFO)->private_data))->built_address) + +struct sh64_disassemble_info + { + /* When we see a MOVI, we save the register and the value, and merge a + subsequent SHORI and display the address, if there is one. */ + unsigned int address_reg; + bfd_signed_vma built_address; + + /* This is the range decriptor for the current address. It is kept + around for the next call. */ + sh64_elf_crange crange; + }; + +/* Each item in the table is a mask to indicate which bits to be set + to determine an instruction's operator. + The index is as same as the instruction in the opcode table. + Note that some archs have this as a field in the opcode table. */ +static unsigned long *shmedia_opcode_mask_table; + +static void initialize_shmedia_opcode_mask_table PARAMS ((void)); +static int print_insn_shmedia PARAMS ((bfd_vma, disassemble_info *)); +static const char *creg_name PARAMS ((int)); +static boolean init_sh64_disasm_info PARAMS ((struct disassemble_info *)); +static enum sh64_elf_cr_type sh64_get_contents_type_disasm + PARAMS ((bfd_vma, struct disassemble_info *)); + +/* Initialize the SH64 opcode mask table for each instruction in SHmedia + mode. */ + +static void +initialize_shmedia_opcode_mask_table () +{ + int n_opc; + int n; + + /* Calculate number of opcodes. */ + for (n_opc = 0; shmedia_table[n_opc].name != NULL; n_opc++) + ; + + shmedia_opcode_mask_table + = xmalloc (sizeof (shmedia_opcode_mask_table[0]) * n_opc); + + for (n = 0; n < n_opc; n++) + { + int i; + + unsigned long mask = 0; + + for (i = 0; shmedia_table[n].arg[i] != A_NONE; i++) + { + int offset = shmedia_table[n].nibbles[i]; + int length; + + switch (shmedia_table[n].arg[i]) + { + case A_GREG_M: + case A_GREG_N: + case A_GREG_D: + case A_CREG_K: + case A_CREG_J: + case A_FREG_G: + case A_FREG_H: + case A_FREG_F: + case A_DREG_G: + case A_DREG_H: + case A_DREG_F: + case A_FMREG_G: + case A_FMREG_H: + case A_FMREG_F: + case A_FPREG_G: + case A_FPREG_H: + case A_FPREG_F: + case A_FVREG_G: + case A_FVREG_H: + case A_FVREG_F: + case A_REUSE_PREV: + length = 6; + break; + + case A_TREG_A: + case A_TREG_B: + length = 3; + break; + + case A_IMMM: + abort (); + break; + + case A_IMMU5: + length = 5; + break; + + case A_IMMS6: + case A_IMMU6: + case A_IMMS6BY32: + length = 6; + break; + + case A_IMMS10: + case A_IMMS10BY1: + case A_IMMS10BY2: + case A_IMMS10BY4: + case A_IMMS10BY8: + length = 10; + break; + + case A_IMMU16: + case A_IMMS16: + case A_PCIMMS16BY4: + case A_PCIMMS16BY4_PT: + length = 16; + break; + + default: + abort (); + length = 0; + break; + } + + if (length != 0) + mask |= (0xffffffff >> (32 - length)) << offset; + } + shmedia_opcode_mask_table[n] = 0xffffffff & ~mask; + } +} + +/* Get a predefined control-register-name, or return NULL. */ + +const char * +creg_name (cregno) + int cregno; +{ + const shmedia_creg_info *cregp; + + /* If control register usage is common enough, change this to search a + hash-table. */ + for (cregp = shmedia_creg_table; cregp->name != NULL; cregp++) + { + if (cregp->cregno == cregno) + return cregp->name; + } + + return NULL; +} + +/* Main function to disassemble SHmedia instructions. */ + +static int +print_insn_shmedia (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + + unsigned char insn[4]; + unsigned long instruction; + int status; + int n; + const shmedia_opcode_info *op; + int i; + unsigned int r = 0; + long imm = 0; + bfd_vma disp_pc_addr; + + status = info->read_memory_func (memaddr, insn, 4, info); + + /* If we can't read four bytes, something is wrong. Display any data we + can get as .byte:s. */ + if (status != 0) + { + int i; + + for (i = 0; i < 3; i++) + { + status = info->read_memory_func (memaddr + i, insn, 1, info); + if (status != 0) + break; + (*fprintf_fn) (stream, "%s0x%02x", + i == 0 ? ".byte " : ", ", + insn[0]); + } + + return i ? i : -1; + } + + /* Rearrange the bytes to make up an instruction. */ + if (info->endian == BFD_ENDIAN_LITTLE) + instruction = bfd_getl32 (insn); + else + instruction = bfd_getb32 (insn); + + /* FIXME: Searching could be implemented using a hash on relevant + fields. */ + for (n = 0, op = shmedia_table; + op->name != NULL + && ((instruction & shmedia_opcode_mask_table[n]) != op->opcode_base); + n++, op++) + ; + + /* FIXME: We should also check register number constraints. */ + if (op->name == NULL) + { + fprintf_fn (stream, ".long 0x%08x", instruction); + return 4; + } + + fprintf_fn (stream, "%s\t", op->name); + + for (i = 0; i < 3 && op->arg[i] != A_NONE; i++) + { + unsigned long temp = instruction >> op->nibbles[i]; + int by_number = 0; + + if (i > 0 && op->arg[i] != A_REUSE_PREV) + fprintf_fn (stream, ","); + + switch (op->arg[i]) + { + case A_REUSE_PREV: + continue; + + case A_GREG_M: + case A_GREG_N: + case A_GREG_D: + r = temp & 0x3f; + fprintf_fn (stream, "r%d", r); + break; + + case A_FVREG_F: + case A_FVREG_G: + case A_FVREG_H: + r = temp & 0x3f; + fprintf_fn (stream, "fv%d", r); + break; + + case A_FPREG_F: + case A_FPREG_G: + case A_FPREG_H: + r = temp & 0x3f; + fprintf_fn (stream, "fp%d", r); + break; + + case A_FMREG_F: + case A_FMREG_G: + case A_FMREG_H: + r = temp & 0x3f; + fprintf_fn (stream, "mtrx%d", r); + break; + + case A_CREG_K: + case A_CREG_J: + { + const char *name; + r = temp & 0x3f; + + name = creg_name (r); + + if (name != NULL) + fprintf_fn (stream, "%s", name); + else + fprintf_fn (stream, "cr%d", r); + } + break; + + case A_FREG_G: + case A_FREG_H: + case A_FREG_F: + r = temp & 0x3f; + fprintf_fn (stream, "fr%d", r); + break; + + case A_DREG_G: + case A_DREG_H: + case A_DREG_F: + r = temp & 0x3f; + fprintf_fn (stream, "dr%d", r); + break; + + case A_TREG_A: + case A_TREG_B: + r = temp & 0x7; + fprintf_fn (stream, "tr%d", r); + break; + + /* A signed 6-bit number. */ + case A_IMMS6: + imm = temp & 0x3f; + if (imm & (unsigned long) 0x20) + imm |= ~(unsigned long) 0x3f; + fprintf_fn (stream, "%d", imm); + break; + + /* A signed 6-bit number, multiplied by 32 when used. */ + case A_IMMS6BY32: + imm = temp & 0x3f; + if (imm & (unsigned long) 0x20) + imm |= ~(unsigned long) 0x3f; + fprintf_fn (stream, "%d", imm * 32); + break; + + /* A signed 10-bit number, multiplied by 8 when used. */ + case A_IMMS10BY8: + by_number++; + /* Fall through. */ + + /* A signed 10-bit number, multiplied by 4 when used. */ + case A_IMMS10BY4: + by_number++; + /* Fall through. */ + + /* A signed 10-bit number, multiplied by 2 when used. */ + case A_IMMS10BY2: + by_number++; + /* Fall through. */ + + /* A signed 10-bit number. */ + case A_IMMS10: + case A_IMMS10BY1: + imm = temp & 0x3ff; + if (imm & (unsigned long) 0x200) + imm |= ~(unsigned long) 0x3ff; + imm <<= by_number; + fprintf_fn (stream, "%d", imm); + break; + + /* A signed 16-bit number. */ + case A_IMMS16: + imm = temp & 0xffff; + if (imm & (unsigned long) 0x8000) + imm |= ~((unsigned long) 0xffff); + fprintf_fn (stream, "%d", imm); + break; + + /* A PC-relative signed 16-bit number, multiplied by 4 when + used. */ + case A_PCIMMS16BY4: + imm = temp & 0xffff; /* 16 bits */ + if (imm & (unsigned long) 0x8000) + imm |= ~(unsigned long) 0xffff; + imm <<= 2; + disp_pc_addr = (bfd_vma) imm + memaddr; + (*info->print_address_func) (disp_pc_addr, info); + break; + + /* An unsigned 5-bit number. */ + case A_IMMU5: + imm = temp & 0x1f; + fprintf_fn (stream, "%d", imm); + break; + + /* An unsigned 6-bit number. */ + case A_IMMU6: + imm = temp & 0x3f; + fprintf_fn (stream, "%d", imm); + break; + + /* An unsigned 16-bit number. */ + case A_IMMU16: + imm = temp & 0xffff; + fprintf_fn (stream, "%d", imm); + break; + + default: + abort (); + break; + } + } + + /* FIXME: Looks like 32-bit values only are handled. + FIXME: PC-relative numbers aren't handled correctly. */ + if (op->opcode_base == (unsigned long) SHMEDIA_SHORI_OPC + && SAVED_MOVI_R (info) == r) + { + asection *section = info->section; + + /* Most callers do not set the section field correctly yet. Revert + to getting the section from symbols, if any. */ + if (section == NULL + && info->symbols != NULL + && bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour + && ! bfd_is_und_section (bfd_get_section (info->symbols[0])) + && ! bfd_is_abs_section (bfd_get_section (info->symbols[0]))) + section = bfd_get_section (info->symbols[0]); + + /* Only guess addresses when the contents of this section is fully + relocated. Otherwise, the value will be zero or perhaps even + bogus. */ + if (section == NULL + || section->owner == NULL + || elf_elfheader (section->owner)->e_type == ET_EXEC) + { + bfd_signed_vma shori_addr; + + shori_addr = SAVED_MOVI_IMM (info) << 16; + shori_addr |= imm; + + fprintf_fn (stream, "\t! 0x"); + (*info->print_address_func) (shori_addr, info); + } + } + + if (op->opcode_base == SHMEDIA_MOVI_OPC) + { + SAVED_MOVI_IMM (info) = imm; + SAVED_MOVI_R (info) = r; + } + else + { + SAVED_MOVI_IMM (info) = 0; + SAVED_MOVI_R (info) = 255; + } + + return 4; +} + +/* Check the type of contents about to be disassembled. This is like + sh64_get_contents_type (which may be called from here), except that it + takes the same arguments as print_insn_* and does what can be done if + no section is available. */ + +static enum sh64_elf_cr_type +sh64_get_contents_type_disasm (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + struct sh64_disassemble_info *sh64_infop = info->private_data; + + /* Perhaps we have a region from a previous probe and it still counts + for this address? */ + if (sh64_infop->crange.cr_type != CRT_NONE + && memaddr >= sh64_infop->crange.cr_addr + && memaddr < sh64_infop->crange.cr_addr + sh64_infop->crange.cr_size) + return sh64_infop->crange.cr_type; + + /* If we have a section, try and use it. */ + if (info->section + && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour) + { + enum sh64_elf_cr_type cr_type + = sh64_get_contents_type (info->section, memaddr, + &sh64_infop->crange); + + if (cr_type != CRT_NONE) + return cr_type; + } + + /* If we have symbols, we can try and get at a section from *that*. */ + if (info->symbols != NULL + && bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour + && ! bfd_is_und_section (bfd_get_section (info->symbols[0])) + && ! bfd_is_abs_section (bfd_get_section (info->symbols[0]))) + { + enum sh64_elf_cr_type cr_type + = sh64_get_contents_type (bfd_get_section (info->symbols[0]), + memaddr, &sh64_infop->crange); + + if (cr_type != CRT_NONE) + return cr_type; + } + + /* We can make a reasonable guess based on the st_other field of a + symbol; for a BranchTarget this is marked as STO_SH5_ISA32 and then + it's most probably code there. */ + if (info->symbols + && bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour + && elf_symbol_from (bfd_asymbol_bfd (info->symbols[0]), + info->symbols[0])->internal_elf_sym.st_other + == STO_SH5_ISA32) + return CRT_SH5_ISA32; + + /* If all else fails, guess this is code and guess on the low bit set. */ + return (memaddr & 1) == 1 ? CRT_SH5_ISA32 : CRT_SH5_ISA16; +} + +/* Initialize static and dynamic disassembly state. */ + +static boolean +init_sh64_disasm_info (info) + struct disassemble_info *info; +{ + struct sh64_disassemble_info *sh64_infop + = calloc (sizeof (*sh64_infop), 1); + + if (sh64_infop == NULL) + return false; + + info->private_data = sh64_infop; + + SAVED_MOVI_IMM (info) = 0; + SAVED_MOVI_R (info) = 255; + + if (shmedia_opcode_mask_table == NULL) + initialize_shmedia_opcode_mask_table (); + + return true; +} + +/* Main entry to disassemble SHmedia instructions, given an endian set in + INFO. Note that the simulator uses this as the main entry and does not + use any of the functions further below. */ + +int +print_insn_sh64x_media (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + if (info->private_data == NULL && ! init_sh64_disasm_info (info)) + return -1; + + /* Make reasonable output. */ + info->bytes_per_line = 4; + info->bytes_per_chunk = 4; + + return print_insn_shmedia (memaddr, info); +} + +/* Main entry to disassemble SHmedia insns. + If we see an SHcompact instruction, return -2. */ + +int +print_insn_sh64 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + enum bfd_endian endian = info->endian; + enum sh64_elf_cr_type cr_type; + + if (info->private_data == NULL && ! init_sh64_disasm_info (info)) + return -1; + + cr_type = sh64_get_contents_type_disasm (memaddr, info); + if (cr_type != CRT_SH5_ISA16) + { + int length = 4 - (memaddr % 4); + info->display_endian = endian; + + /* If we got an uneven address to indicate SHmedia, adjust it. */ + if (cr_type == CRT_SH5_ISA32 && length == 3) + memaddr--, length = 4; + + /* Only disassemble on four-byte boundaries. Addresses that are not + a multiple of four can happen after a data region. */ + if (cr_type == CRT_SH5_ISA32 && length == 4) + return print_insn_sh64x_media (memaddr, info); + + /* We get CRT_DATA *only* for data regions in a mixed-contents + section. For sections with data only, we get indication of one + of the ISA:s. You may think that we shouldn't disassemble + section with only data if we can figure that out. However, the + disassembly function is by default not called for data-only + sections, so if the user explicitly specified disassembly of a + data section, that's what we should do. */ + if (cr_type == CRT_DATA || length != 4) + { + int status; + unsigned char data[4]; + struct sh64_disassemble_info *sh64_infop = info->private_data; + + if (length == 4 + && sh64_infop->crange.cr_type != CRT_NONE + && memaddr >= sh64_infop->crange.cr_addr + && memaddr < (sh64_infop->crange.cr_addr + + sh64_infop->crange.cr_size)) + length + = (sh64_infop->crange.cr_addr + + sh64_infop->crange.cr_size - memaddr); + + status + = (*info->read_memory_func) (memaddr, data, + length >= 4 ? 4 : length, info); + + if (status == 0 && length >= 4) + { + (*info->fprintf_func) (info->stream, ".long 0x%08lx", + endian == BFD_ENDIAN_BIG + ? (long) (bfd_getb32 (data)) + : (long) (bfd_getl32 (data))); + return 4; + } + else + { + int i; + + for (i = 0; i < length; i++) + { + status = info->read_memory_func (memaddr + i, data, 1, info); + if (status != 0) + break; + (*info->fprintf_func) (info->stream, "%s0x%02x", + i == 0 ? ".byte " : ", ", + data[0]); + } + + return i ? i : -1; + } + } + } + + /* SH1 .. SH4 instruction, let caller handle it. */ + return -2; +} diff --git a/opcodes/sh64-opc.c b/opcodes/sh64-opc.c new file mode 100644 index 0000000..ad61038 --- /dev/null +++ b/opcodes/sh64-opc.c @@ -0,0 +1,774 @@ +/* Definitions for SH64 opcodes. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sh64-opc.h" +#include + +/* Users currently assume that no mnemonic appears twice. For + disassembly, the first complete match is displayed. */ +const shmedia_opcode_info shmedia_table[] = { + +/* 000000mmmmmm1001nnnnnndddddd0000 add ,, */ + { "add", {A_GREG_M,A_GREG_N,A_GREG_D}, + {OFFSET_20,OFFSET_10,OFFSET_4}, SHMEDIA_ADD_OPC + }, +/* 000000mmmmmm1000nnnnnndddddd0000 add.l ,, */ + { "add.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00080000 + }, +/* 110100mmmmmmssssssssssdddddd0000 addi ,, */ + { "addi", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, + SHMEDIA_ADDI_OPC + }, +/* 110101mmmmmmssssssssssdddddd0000 addi.l ,, */ + { "addi.l", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd4000000 + }, +/* 000000mmmmmm1100nnnnnndddddd0000 addz.l ,, */ + { "addz.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000c0000 + }, +/* 111000mmmmmm0100ssssss1111110000 alloco , */ + { "alloco", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00403f0 + }, +/* 000001mmmmmm1011nnnnnndddddd0000 and ,, */ + { "and", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040b0000 + }, +/* 000001mmmmmm1111nnnnnndddddd0000 andc ,, */ + { "andc", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040f0000 + }, +/* 110110mmmmmmssssssssssdddddd0000 andi ,, */ + { "andi", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd8000000 + }, +/* 011001mmmmmm0001nnnnnnl00ccc0000 beq ,, */ + { "beq/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200 + }, +/* 011001mmmmmm0001nnnnnnl00ccc0000 beq ,, */ + { "beq", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200 + }, +/* 011001mmmmmm0001nnnnnn000ccc0000 beq/u ,, */ + { "beq/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010000 + }, +/* 111001mmmmmm0001ssssssl00ccc0000 beqi ,, */ + { "beqi/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200 + }, +/* 111001mmmmmm0001ssssssl00ccc0000 beqi ,, */ + { "beqi", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200 + }, +/* 111001mmmmmm0001ssssss000ccc0000 beqi/u ,, */ + { "beqi/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010000 + }, +/* 011001mmmmmm0011nnnnnnl00ccc0000 bge ,, */ + { "bge/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200 + }, +/* 011001mmmmmm0011nnnnnnl00ccc0000 bge ,, */ + { "bge", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200 + }, +/* 011001mmmmmm0011nnnnnn000ccc0000 bge/u ,, */ + { "bge/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030000 + }, +/* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu ,, */ + { "bgeu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200 + }, +/* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu ,, */ + { "bgeu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200 + }, +/* 011001mmmmmm1011nnnnnn000ccc0000 bgeu/u ,, */ + { "bgeu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0000 + }, +/* 011001mmmmmm0111nnnnnnl00ccc0000 bgt ,, */ + { "bgt/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200 + }, +/* 011001mmmmmm0111nnnnnnl00ccc0000 bgt ,, */ + { "bgt", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200 + }, +/* 011001mmmmmm0111nnnnnn000ccc0000 bgt/u ,, */ + { "bgt/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070000 + }, +/* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu ,, */ + { "bgtu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200 + }, +/* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu ,, */ + { "bgtu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200 + }, +/* 011001mmmmmm1111nnnnnn000ccc0000 bgtu/u ,, */ + { "bgtu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0000 + }, +/* 010001000bbb0001111111dddddd0000 blink , */ + { "blink", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4401fc00 + }, +/* 011001mmmmmm0101nnnnnnl00ccc0000 bne ,, */ + { "bne/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200 + }, +/* 011001mmmmmm0101nnnnnnl00ccc0000 bne ,, */ + { "bne", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200 + }, +/* 011001mmmmmm0101nnnnnn000ccc0000 bne/u ,, */ + { "bne/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050000 + }, +/* 111001mmmmmm0101ssssssl00ccc0000 bnei ,, */ + { "bnei/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200 + }, +/* 111001mmmmmm0101ssssssl00ccc0000 bnei ,, */ + { "bnei", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200 + }, +/* 111001mmmmmm0101ssssss000ccc0000 bnei/u ,, */ + { "bnei/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050000 + }, +/* 01101111111101011111111111110000 brk */ + { "brk", {A_NONE}, {OFFSET_NONE}, 0x6ff5fff0 + }, +/* 000000mmmmmm1111111111dddddd0000 byterev , */ + { "byterev", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000ffc00 + }, +/* 000000mmmmmm0001nnnnnndddddd0000 cmpeq ,, */ + { "cmpeq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00010000 + }, +/* 000000mmmmmm0011nnnnnndddddd0000 cmpgt ,, */ + { "cmpgt", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00030000 + }, +/* 000000mmmmmm0111nnnnnndddddd0000 cmpgtu ,, */ + { "cmpgtu", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00070000 + }, +/* 001000mmmmmm0001nnnnnnwwwwww0000 cmveq ,, */ + { "cmveq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20010000 + }, +/* 001000mmmmmm0101nnnnnnwwwwww0000 cmvne ,, */ + { "cmvne", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20050000 + }, +/* 000110gggggg0001ggggggffffff0000 fabs.d , */ + { "fabs.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18010000 + }, +/* 000110gggggg0000ggggggffffff0000 fabs.s , */ + { "fabs.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18000000 + }, +/* 001101gggggg0001hhhhhhffffff0000 fadd.s ,, */ + { "fadd.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34010000 + }, +/* 001101gggggg0000hhhhhhffffff0000 fadd.s ,, */ + { "fadd.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34000000 + }, +/* 001100gggggg1001hhhhhhdddddd0000 fcmpeq.s ,, */ + { "fcmpeq.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30090000 + }, +/* 001100gggggg1000hhhhhhdddddd0000 fcmpeq.s ,, */ + { "fcmpeq.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30080000 + }, +/* 001100gggggg1111hhhhhhdddddd0000 fcmpge.d ,, */ + { "fcmpge.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300f0000 + }, +/* 001100gggggg1110hhhhhhdddddd0000 fcmpge.s ,, */ + { "fcmpge.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300e0000 + }, +/* 001100gggggg1101hhhhhhdddddd0000 fcmpgt.d ,, */ + { "fcmpgt.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300d0000 + }, +/* 001100gggggg1100hhhhhhdddddd0000 fcmpgt.s ,, */ + { "fcmpgt.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300c0000 + }, +/* 001100gggggg1011hhhhhhdddddd0000 fcmpun.d ,, */ + { "fcmpun.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300b0000 + }, +/* 001100gggggg1010hhhhhhdddddd0000 fcmpun.s ,, */ + { "fcmpun.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300a0000 + }, +/* 001110gggggg0111ggggggffffff0000 fcnv.ds , */ + { "fcnv.ds", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38070000 + }, +/* 001110gggggg0110ggggggffffff0000 fcnv.sd , */ + { "fcnv.sd", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38060000 + }, +/* 001101gggggg0101hhhhhhffffff0000 fdiv.d ,, */ + { "fdiv.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34050000 + }, +/* 001101gggggg0100hhhhhhffffff0000 fdiv.s ,, */ + { "fdiv.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34040000 + }, +/* 0001111111110010111111ffffff0000 fgetscr */ + { "fgetscr", {A_FREG_F}, {OFFSET_4}, 0x1ff2fc00 + }, +/* 000101gggggg0110hhhhhhffffff0000 fipr.s ,, */ + { "fipr.s", {A_FVREG_G,A_FVREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x14060000 + }, +/* 100111mmmmmmssssssssssffffff0000 fld.d ,, */ + { "fld.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x9c000000 + }, +/* 100110mmmmmmssssssssssffffff0000 fld.p ,, */ + { "fld.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x98000000 + }, +/* 100101mmmmmmssssssssssffffff0000 fld.s ,, */ + { "fld.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x94000000 + }, +/* 000111mmmmmm1001nnnnnnffffff0000 fldx.d ,, */ + { "fldx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c090000 + }, +/* 000111mmmmmm1101nnnnnnffffff0000 fldx.p ,, */ + { "fldx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c0d0000 + }, +/* 000111mmmmmm1000nnnnnnffffff0000 fldx.s ,, */ + { "fldx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c080000 + }, +/* 001110gggggg1110ggggggffffff0000 float.ld , */ + { "float.ld", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380e0000 + }, +/* 001110gggggg1100ggggggffffff0000 float.ls , */ + { "float.ls", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380c0000 + }, +/* 001110gggggg1101ggggggffffff0000 float.qd , */ + { "float.qd", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380d0000 + }, +/* 001110gggggg1111ggggggffffff0000 float.qs , */ + { "float.qs", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380f0000 + }, +/* 001101gggggg1110hhhhhhqqqqqq0000 fmac.s ,, */ + { "fmac.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x340e0000 + }, +/* 001110gggggg0001ggggggffffff0000 fmov.d , */ + { "fmov.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38010000 + }, +/* 001100gggggg0001ggggggdddddd0000 fmov.dq , */ + { "fmov.dq", {A_DREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30010000 + }, +/* 000111mmmmmm0000111111ffffff0000 fmov.ls , */ + { "fmov.ls", {A_GREG_M,A_FREG_F}, {OFFSET_20,OFFSET_4}, 0x1c00fc00 + }, +/* 000111mmmmmm0001111111ffffff0000 fmov.qd , */ + { "fmov.qd", {A_GREG_M,A_DREG_F}, {OFFSET_20,OFFSET_4}, 0x1c01fc00 + }, +/* 001110gggggg0000ggggggffffff0000 fmov.s , */ + { "fmov.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38000000 + }, +/* 001100gggggg0000ggggggdddddd0000 fmov.sl , */ + { "fmov.sl", {A_FREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30000000 + }, +/* 001101gggggg0111hhhhhhffffff0000 fmul.d ,, */ + { "fmul.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34070000 + }, +/* 001101gggggg0110hhhhhhffffff0000 fmul.s ,, */ + { "fmul.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34060000 + }, +/* 000110gggggg0011ggggggffffff0000 fneg.d , */ + { "fneg.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18030000 + }, +/* 000110gggggg0010ggggggffffff0000 fneg.s , */ + { "fneg.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18020000 + }, +/* 001100gggggg0010gggggg1111110000 fputscr */ + { "fputscr", {A_FREG_G,A_REUSE_PREV}, {OFFSET_20,OFFSET_10}, 0x300203f0 + }, +/* 001110gggggg0101ggggggffffff0000 fsqrt.d , */ + { "fsqrt.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38050000 + }, +/* 001110gggggg0100ggggggffffff0000 fsqrt.s , */ + { "fsqrt.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38040000 + }, +/* 101111mmmmmmsssssssssszzzzzz0000 fst.d ,, */ + { "fst.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xbc000000 + }, +/* 101110mmmmmmsssssssssszzzzzz0000 fst.p ,, */ + { "fst.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb8000000 + }, +/* 101101mmmmmmsssssssssszzzzzz0000 fst.s ,, */ + { "fst.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb4000000 + }, +/* 001111mmmmmm1001nnnnnnzzzzzz0000 fstx.d ,, */ + { "fstx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c090000 + }, +/* 001111mmmmmm1101nnnnnnzzzzzz0000 fstx.p ,, */ + { "fstx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c0d0000 + }, +/* 001111mmmmmm1000nnnnnnzzzzzz0000 fstx.s ,, */ + { "fstx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c080000 + }, +/* 001101gggggg0011hhhhhhffffff0000 fsub.d ,, */ + { "fsub.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34030000 + }, +/* 001101gggggg0010hhhhhhffffff0000 fsub.s ,, */ + { "fsub.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34020000 + }, +/* 001110gggggg1011ggggggffffff0000 ftrc.dl , */ + { "ftrc.dl", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380b0000 + }, +/* 001110gggggg1001ggggggffffff0000 ftrc.dq , */ + { "ftrc.dq", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38090000 + }, +/* 001110gggggg1000ggggggffffff0000 ftrc.sl , */ + { "ftrc.sl", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38080000 + }, +/* 001110gggggg1010ggggggffffff0000 ftrc.sq , */ + { "ftrc.sq", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380a0000 + }, +/* 000101gggggg1110hhhhhhffffff0000 ftrv.s ,, */ + { "ftrv.s", {A_FMREG_G,A_FVREG_H,A_FVREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x140e0000 + }, +/* 110000mmmmmm1111ssssssdddddd0000 getcfg ,, */ + { "getcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc00f0000 + }, +/* 001001kkkkkk1111111111dddddd0000 getcon , */ + { "getcon", {A_CREG_K,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x240ffc00 + }, +/* 010001rrrbbb0101111111dddddd0000 gettr , */ + { "gettr", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4405fc00 + }, +/* 111000mmmmmm0101ssssss1111110000 icbi , */ + { "icbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00503f0 + }, +/* 100000mmmmmmssssssssssdddddd0000 ld.b ,, */ + { "ld.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x80000000 + }, +/* 100010mmmmmmssssssssssdddddd0000 ld.l ,, */ + { "ld.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x88000000 + }, +/* 100011mmmmmmssssssssssdddddd0000 ld.q ,, */ + { "ld.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x8c000000 + }, +/* 100100mmmmmmssssssssssdddddd0000 ld.ub ,, */ + { "ld.ub", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x90000000 + }, +/* 101100mmmmmmssssssssssdddddd0000 ld.uw ,, */ + { "ld.uw", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb0000000 + }, +/* 100001mmmmmmssssssssssdddddd0000 ld.w ,, */ + { "ld.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x84000000 + }, +/* 110000mmmmmm0110ssssssdddddd0000 ldhi.l ,, */ + { "ldhi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0060000 + }, +/* 110000mmmmmm0111ssssssdddddd0000 ldhi.q ,, */ + { "ldhi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0070000 + }, +/* 110000mmmmmm0010ssssssdddddd0000 ldlo.l ,, */ + { "ldlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0020000 + }, +/* 110000mmmmmm0011ssssssdddddd0000 ldlo.q ,, */ + { "ldlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0030000 + }, +/* 010000mmmmmm0000nnnnnndddddd0000 ldx.b ,, */ + { "ldx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40000000 + }, +/* 010000mmmmmm0010nnnnnndddddd0000 ldx.l ,, */ + { "ldx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40020000 + }, +/* 010000mmmmmm0011nnnnnndddddd0000 ldx.q ,, */ + { "ldx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40030000 + }, +/* 010000mmmmmm0100nnnnnndddddd0000 ldx.ub ,, */ + { "ldx.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40040000 + }, +/* 010000mmmmmm0101nnnnnndddddd0000 ldx.uw ,, */ + { "ldx.uw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40050000 + }, +/* 010000mmmmmm0001nnnnnndddddd0000 ldx.w ,, */ + { "ldx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40010000 + }, +/* 001010mmmmmm1010111111dddddd0000 mabs.l , */ + { "mabs.l", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x280afc00 + }, +/* 001010mmmmmm1001111111dddddd0000 mabs.w , */ + { "mabs.w", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x2809fc00 + }, +/* 000010mmmmmm0010nnnnnndddddd0000 madd.l ,, */ + { "madd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08020000 + }, +/* 000010mmmmmm0001nnnnnndddddd0000 madd.w ,, */ + { "madd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08010000 + }, +/* 000010mmmmmm0110nnnnnndddddd0000 madds.l ,, */ + { "madds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08060000 + }, +/* 000010mmmmmm0100nnnnnndddddd0000 madds.ub ,, */ + { "madds.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08040000 + }, +/* 000010mmmmmm0101nnnnnndddddd0000 madds.w ,, */ + { "madds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08050000 + }, +/* 001010mmmmmm0000nnnnnndddddd0000 mcmpeq.b ,, */ + { "mcmpeq.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28000000 + }, +/* 001010mmmmmm0010nnnnnndddddd0000 mcmpeq.l ,, */ + { "mcmpeq.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28020000 + }, +/* 001010mmmmmm0001nnnnnndddddd0000 mcmpeq.w ,, */ + { "mcmpeq.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28010000 + }, +/* 001010mmmmmm0110nnnnnndddddd0000 mcmpgt.l ,, */ + { "mcmpgt.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28060000 + }, +/* 001010mmmmmm0100nnnnnndddddd0000 mcmpgt.ub ,, */ + { "mcmpgt.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28040000 + }, +/* 001010mmmmmm0101nnnnnndddddd0000 mcmpgt.w ,, */ + { "mcmpgt.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28050000 + }, +/* 010010mmmmmm0011nnnnnnwwwwww0000 mcmv ,, */ + { "mcmv", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48030000 + }, +/* 010011mmmmmm1101nnnnnndddddd0000 mcnvs.lw ,, */ + { "mcnvs.lw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0d0000 + }, +/* 010011mmmmmm1000nnnnnndddddd0000 mcnvs.wb ,, */ + { "mcnvs.wb", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c080000 + }, +/* 010011mmmmmm1100nnnnnndddddd0000 mcnvs.wub ,, */ + { "mcnvs.wub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0c0000 + }, +/* 001010mmmmmm0111nnnnnndddddd0000 mextr1 ,, */ + { "mextr1", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28070000 + }, +/* 001010mmmmmm1011nnnnnndddddd0000 mextr2 ,, */ + { "mextr2", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280b0000 + }, +/* 001010mmmmmm1111nnnnnndddddd0000 mextr3 ,, */ + { "mextr3", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280f0000 + }, +/* 001011mmmmmm0011nnnnnndddddd0000 mextr4 ,, */ + { "mextr4", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c030000 + }, +/* 001011mmmmmm0111nnnnnndddddd0000 mextr5 ,, */ + { "mextr5", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c070000 + }, +/* 001011mmmmmm1011nnnnnndddddd0000 mextr6 ,, */ + { "mextr6", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0b0000 + }, +/* 001011mmmmmm1111nnnnnndddddd0000 mextr7 ,, */ + { "mextr7", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0f0000 + }, +/* 010010mmmmmm0001nnnnnnwwwwww0000 mmacfx.wl ,, */ + { "mmacfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48010000 + }, +/* 010010mmmmmm0101nnnnnnwwwwww0000 mmacnfx.wl ,, */ + { "mmacnfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48050000 + }, +/* 010011mmmmmm0010nnnnnndddddd0000 mmul.l ,, */ + { "mmul.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c020000 + }, +/* 010011mmmmmm0001nnnnnndddddd0000 mmul.m ,, */ + { "mmul.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c010000 + }, +/* 010011mmmmmm0110nnnnnndddddd0000 mmulfx.l ,, */ + { "mmulfx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c060000 + }, +/* 010011mmmmmm0101nnnnnndddddd0000 mmulfx.w ,, */ + { "mmulfx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c050000 + }, +/* 010011mmmmmm1001nnnnnndddddd0000 mmulfxrp.w ,, */ + { "mmulfxrp.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c090000 + }, +/* 010011mmmmmm1110nnnnnndddddd0000 mmulhi.wl ,, */ + { "mmulhi.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0e0000 + }, +/* 010011mmmmmm1010nnnnnndddddd0000 mmullo.wl ,, */ + { "mmullo.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0a0000 + }, +/* 010010mmmmmm1001nnnnnnwwwwww0000 mmulsum.wq ,, */ + { "mmulsum.wq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48090000 + }, +/* 110011ssssssssssssssssdddddd0000 movi , */ + { "movi", {A_IMMS16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_MOVI_OPC + }, +/* 001010mmmmmm1101nnnnnndddddd0000 mperm.w ,, */ + { "mperm.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280d0000 + }, +/* 010010mmmmmm0000nnnnnnwwwwww0000 msad.ubq ,, */ + { "msad.ubq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48000000 + }, +/* 000011mmmmmm1010nnnnnndddddd0000 mshard.l ,, */ + { "mshard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0a0000 + }, +/* 000011mmmmmm1001nnnnnndddddd0000 mshard.w ,, */ + { "mshard.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c090000 + }, +/* 000011mmmmmm1011nnnnnndddddd0000 mshards.q ,, */ + { "mshards.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0b0000 + }, +/* 001011mmmmmm0100nnnnnndddddd0000 mshfhi.b ,, */ + { "mshfhi.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c040000 + }, +/* 001011mmmmmm0110nnnnnndddddd0000 mshfhi.l ,, */ + { "mshfhi.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c060000 + }, +/* 001011mmmmmm0101nnnnnndddddd0000 mshfhi.w ,, */ + { "mshfhi.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c050000 + }, +/* 001011mmmmmm0000nnnnnndddddd0000 mshflo.b ,, */ + { "mshflo.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c000000 + }, +/* 001011mmmmmm0010nnnnnndddddd0000 mshflo.l ,, */ + { "mshflo.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c020000 + }, +/* 001011mmmmmm0001nnnnnndddddd0000 mshflo.w ,, */ + { "mshflo.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c010000 + }, +/* 000011mmmmmm0010nnnnnndddddd0000 mshlld.l ,, */ + { "mshlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c020000 + }, +/* 000011mmmmmm0001nnnnnndddddd0000 mshlld.w ,, */ + { "mshlld.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c010000 + }, +/* 000011mmmmmm0110nnnnnndddddd0000 mshalds.l ,, */ + { "mshalds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c060000 + }, +/* 000011mmmmmm0101nnnnnndddddd0000 mshalds.w ,, */ + { "mshalds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c050000 + }, +/* 000011mmmmmm1110nnnnnndddddd0000 mshlrd.l ,, */ + { "mshlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0e0000 + }, +/* 000011mmmmmm1101nnnnnndddddd0000 mshlrd.w ,, */ + { "mshlrd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0d0000 + }, +/* 000010mmmmmm1010nnnnnndddddd0000 msub.l ,, */ + { "msub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080a0000 + }, +/* 000010mmmmmm1001nnnnnndddddd0000 msub.w ,, */ + { "msub.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08090000 + }, +/* 000010mmmmmm1110nnnnnndddddd0000 msubs.l ,, */ + { "msubs.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080e0000 + }, +/* 000010mmmmmm1100nnnnnndddddd0000 msubs.ub ,, */ + { "msubs.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080c0000 + }, +/* 000010mmmmmm1101nnnnnndddddd0000 msubs.w ,, */ + { "msubs.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080d0000 + }, +/* 000001mmmmmm1110nnnnnndddddd0000 muls.l ,, */ + { "muls.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040e0000 + }, +/* 000000mmmmmm1110nnnnnndddddd0000 mulu.l ,, */ + { "mulu.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000e0000 + }, +/* 01101111111100001111111111110000 nop */ + { "nop", {A_NONE}, {OFFSET_NONE}, + SHMEDIA_NOP_OPC + }, +/* 000000mmmmmm1101111111dddddd0000 nsb , */ + { "nsb", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000dfc00 + }, +/* 111000mmmmmm1001ssssss1111110000 ocbi , */ + { "ocbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00903f0 + }, +/* 111000mmmmmm1000ssssss1111110000 ocbp , */ + { "ocbp", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00803f0 + }, +/* 111000mmmmmm1100ssssss1111110000 ocbwb , */ + { "ocbwb", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00c03f0 + }, +/* 000001mmmmmm1001nnnnnndddddd0000 or ,, */ + { "or", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04090000 + }, +/* 110111mmmmmmssssssssssdddddd0000 ori ,, */ + { "ori", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xdc000000 + }, +/* 111000mmmmmm0001ssssss1111110000 prefi , */ + { "prefi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00103f0 + }, +/* 111010sssssssssssssssslrraaa0000 pta , */ + { "pta/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010sssssssssssssssslrraaa0000 pta , */ + { "pta", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010ssssssssssssssss0rraaa0000 pta/u , */ + { "pta/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTA_OPC + }, +/* 0110101111110001nnnnnnl00aaa0000 ptabs , */ + { "ptabs/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200 + }, +/* 0110101111110001nnnnnnl00aaa0000 ptabs , */ + { "ptabs", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200 + }, +/* 0110101111110001nnnnnn000aaa0000 ptabs/u , */ + { "ptabs/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10000 + }, +/* 111011sssssssssssssssslrraaa0000 ptb , */ + { "ptb/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111011sssssssssssssssslrraaa0000 ptb , */ + { "ptb", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111011ssssssssssssssss0rraaa0000 ptb/u , */ + { "ptb/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTB_OPC + }, +/* 111010sssssssssssssssslrraaa0000 pt/l , */ + { "pt/l", {A_PCIMMS16BY4_PT,A_TREG_A}, + {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010sssssssssssssssslrraaa0000 pt , */ + { "pt", {A_PCIMMS16BY4_PT,A_TREG_A}, + {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010ssssssssssssssss0rraaa0000 pt/u , */ + { "pt/u", {A_PCIMMS16BY4_PT,A_TREG_A}, + {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC + }, +/* 0110101111110101nnnnnnl00aaa0000 ptrel , */ + { "ptrel/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT + }, +/* 0110101111110101nnnnnnl00aaa0000 ptrel , */ + { "ptrel", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT + }, +/* 0110101111110101nnnnnn000aaa0000 ptrel/u , */ + { "ptrel/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTREL_OPC + }, +/* 111000mmmmmm1111ssssssyyyyyy0000 putcfg ,, */ + { "putcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe00f0000 + }, +/* 011011mmmmmm1111111111jjjjjj0000 putcon , */ + { "putcon", {A_GREG_M,A_CREG_J}, {OFFSET_20,OFFSET_4}, 0x6c0ffc00 + }, +/* 01101111111100111111111111110000 rte */ + { "rte", {A_NONE}, {OFFSET_NONE}, 0x6ff3fff0 + }, +/* 000001mmmmmm0111nnnnnndddddd0000 shard ,, */ + { "shard", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04070000 + }, +/* 000001mmmmmm0110nnnnnndddddd0000 shard.l ,, */ + { "shard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04060000 + }, +/* 110001mmmmmm0111ssssssdddddd0000 shari ,, */ + { "shari", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4070000 + }, +/* 110001mmmmmm0110ssssssdddddd0000 shari ,, */ + { "shari.l", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4060000 + }, +/* 000001mmmmmm0001nnnnnndddddd0000 shlld ,, */ + { "shlld", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04010000 + }, +/* 000001mmmmmm0000nnnnnndddddd0000 shlld.l ,, */ + { "shlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04000000 + }, +/* 110001mmmmmm0001ssssssdddddd0000 shlli ,, */ + { "shlli", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4010000 + }, +/* 110001mmmmmm0000ssssssdddddd0000 shlli.l ,, */ + { "shlli.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4000000 + }, +/* 000001mmmmmm0011nnnnnndddddd0000 shlrd ,, */ + { "shlrd", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04030000 + }, +/* 000001mmmmmm0010nnnnnndddddd0000 shlrd.l ,, */ + { "shlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04020000 + }, +/* 110001mmmmmm0011ssssssdddddd0000 shlri ,, */ + { "shlri", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4030000 + }, +/* 110001mmmmmm0010ssssssdddddd0000 shlri.l ,, */ + { "shlri.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4020000 + }, +/* 110010sssssssssssssssswwwwww0000 shori , */ + { "shori", {A_IMMU16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_SHORI_OPC + }, +/* 01101111111101111111111111110000 sleep */ + { "sleep", {A_NONE}, {OFFSET_NONE}, 0x6ff7fff0 + }, +/* 101000mmmmmmssssssssssdddddd0000 st.b ,, */ + { "st.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa0000000 + }, +/* 101010mmmmmmssssssssssdddddd0000 st.l ,, */ + { "st.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa8000000 + }, +/* 101011mmmmmmssssssssssdddddd0000 st.q ,, */ + { "st.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xac000000 + }, +/* 101001mmmmmmssssssssssdddddd0000 st.w ,, */ + { "st.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa4000000 + }, +/* 111000mmmmmm0110ssssssdddddd0000 sthi.l ,, */ + { "sthi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0060000 + }, +/* 111000mmmmmm0111ssssssdddddd0000 sthi.q ,, */ + { "sthi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0070000 + }, +/* 111000mmmmmm0010ssssssdddddd0000 stlo.l ,, */ + { "stlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0020000 + }, +/* 111000mmmmmm0011ssssssdddddd0000 stlo.q ,, */ + { "stlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0030000 + }, +/* 011000mmmmmm0000nnnnnndddddd0000 stx.b ,, */ + { "stx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60000000 + }, +/* 011000mmmmmm0010nnnnnndddddd0000 stx.l ,, */ + { "stx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60020000 + }, +/* 011000mmmmmm0011nnnnnndddddd0000 stx.q ,, */ + { "stx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60030000 + }, +/* 011000mmmmmm0001nnnnnndddddd0000 stx.w ,, */ + { "stx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60010000 + }, +/* 000000mmmmmm1011nnnnnndddddd0000 sub ,, */ + { "sub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000b0000 + }, +/* 000000mmmmmm1010nnnnnndddddd0000 sub.l ,, */ + { "sub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000a0000 + }, +/* 001000mmmmmm0011nnnnnnwwwwww0000 swap.q ,, */ + { "swap.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20030000 + }, +/* 01101111111100101111111111110000 synci */ + { "synci", {A_NONE}, {OFFSET_NONE}, 0x6ff2fff0 + }, +/* 01101111111101101111111111110000 synco */ + { "synco", {A_NONE}, {OFFSET_NONE}, 0x6ff6fff0 + }, +/* 011011mmmmmm00011111111111110000 trapa */ + { "trapa", {A_GREG_M}, {OFFSET_20}, 0x6c01fff0 + }, +/* 000001mmmmmm1101nnnnnndddddd0000 xor ,, */ + { "xor", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040d0000 + }, +/* 110001mmmmmm1101ssssssdddddd0000 xori ,, */ + { "xori", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc40d0000 + }, + + { NULL, {}, {}, 0 } +}; + +/* Predefined control register names as per SH-5/ST50-005-08. */ +const shmedia_creg_info shmedia_creg_table[] = { + { 0, "sr" }, + { 1, "ssr" }, + { 2, "pssr" }, + + { 4, "intevt" }, + { 5, "expevt" }, + { 6, "pexpevt" }, + { 7, "tra" }, + { 8, "spc" }, + { 9, "pspc" }, + { 10, "resvec" }, + { 11, "vbr" }, + + { 13, "tea" }, + + { 16, "dcr" }, + { 17, "kcr0" }, + { 18, "kcr1" }, + + { 62, "ctc" }, + { 63, "usr" }, + { -1, (char *) 0 } +}; + diff --git a/opcodes/sh64-opc.h b/opcodes/sh64-opc.h new file mode 100644 index 0000000..2ed6c11 --- /dev/null +++ b/opcodes/sh64-opc.h @@ -0,0 +1,139 @@ +/* Declarations for SH64 opcodes. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _SH64_OPC_INCLUDED_H +#define _SH64_OPC_INCLUDED_H + +typedef enum +{ + /* A placeholder. */ + OFFSET_NONE = 0, + + /* Bit number for where to insert operand. */ + OFFSET_4 = 4, + OFFSET_9 = 9, + OFFSET_10 = 10, + OFFSET_20 = 20 +} shmedia_nibble_type; + +typedef enum { + /* First a placeholder. */ + A_NONE = 0, + + /* Registers. */ + A_GREG_M, + A_GREG_N, + A_GREG_D, + A_FREG_G, + A_FREG_H, + A_FREG_F, + A_DREG_G, + A_DREG_H, + A_DREG_F, + A_FVREG_G, + A_FVREG_H, + A_FVREG_F, + A_FMREG_G, + A_FMREG_H, + A_FMREG_F, + A_FPREG_G, + A_FPREG_H, + A_FPREG_F, + A_TREG_A, + A_TREG_B, + A_CREG_K, + A_CREG_J, + + /* This one is only used in a shmedia_get_operand. */ + A_IMMM, + + /* Copy of previous register. */ + A_REUSE_PREV, + + /* Unsigned 5-bit operand. */ + A_IMMU5, + + /* Signed 6-bit operand. */ + A_IMMS6, + + /* Signed operand, 6 bits << 5. */ + A_IMMS6BY32, + + /* Unsigned 6-bit operand. */ + A_IMMU6, + + /* Signed 10-bit operand. */ + A_IMMS10, + + /* Signed operand, 10 bits << 0. */ + A_IMMS10BY1, + + /* Signed operand, 10 bits << 1. */ + A_IMMS10BY2, + + /* Signed operand, 10 bits << 2. */ + A_IMMS10BY4, + + /* Signed operand, 10 bits << 3. */ + A_IMMS10BY8, + + /* Signed 16-bit operand. */ + A_IMMS16, + + /* Unsigned 16-bit operand. */ + A_IMMU16, + + /* PC-relative signed operand, 16 bits << 2, for PTA and PTB insns. */ + A_PCIMMS16BY4, + + /* PC relative signed operand, 16 bits << 2, for PT insns. Also adjusts + the opcode to be PTA or PTB. */ + A_PCIMMS16BY4_PT, +} shmedia_arg_type; + +typedef struct { + char *name; + shmedia_arg_type arg[4]; + shmedia_nibble_type nibbles[4]; + unsigned long opcode_base; +} shmedia_opcode_info; + +extern const shmedia_opcode_info shmedia_table[]; + +typedef struct { + int cregno; + char *name; +} shmedia_creg_info; + +extern const shmedia_creg_info shmedia_creg_table[]; + +#define SHMEDIA_LIKELY_BIT 0x00000200 +#define SHMEDIA_PT_OPC 0xe8000000 +#define SHMEDIA_PTB_BIT 0x04000000 +#define SHMEDIA_PTA_OPC 0xe8000000 +#define SHMEDIA_PTB_OPC 0xec000000 + +/* Note that this is ptrel/u. "Or" in SHMEDIA_LIKELY_BIT for ptrel/l. */ +#define SHMEDIA_PTREL_OPC 0x6bf50000 +#define SHMEDIA_MOVI_OPC 0xcc000000 +#define SHMEDIA_SHORI_OPC 0xc8000000 +#define SHMEDIA_ADDI_OPC 0xd0000000 +#define SHMEDIA_ADD_OPC 0x00090000 +#define SHMEDIA_NOP_OPC 0x6ff0fff0 +#define SHMEDIA_TEMP_REG 25 + +#endif /* _SH64_OPC_INCLUDED_H */ diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c new file mode 100644 index 0000000..4c59398 --- /dev/null +++ b/opcodes/sparc-dis.c @@ -0,0 +1,983 @@ +/* Print SPARC instructions. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/sparc.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "opintl.h" + +/* Bitmask of v9 architectures. */ +#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ + | (1 << SPARC_OPCODE_ARCH_V9A) \ + | (1 << SPARC_OPCODE_ARCH_V9B)) +/* 1 if INSN is for v9 only. */ +#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) +/* 1 if INSN is for v9. */ +#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) + +/* The sorted opcode table. */ +static const struct sparc_opcode **sorted_opcodes; + +/* For faster lookup, after insns are sorted they are hashed. */ +/* ??? I think there is room for even more improvement. */ + +#define HASH_SIZE 256 +/* It is important that we only look at insn code bits as that is how the + opcode table is hashed. OPCODE_BITS is a table of valid bits for each + of the main types (0,1,2,3). */ +static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; +#define HASH_INSN(INSN) \ + ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) +struct opcode_hash { + struct opcode_hash *next; + const struct sparc_opcode *opcode; +}; +static struct opcode_hash *opcode_hash_table[HASH_SIZE]; + +static void build_hash_table + PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int)); +static int is_delayed_branch PARAMS ((unsigned long)); +static int compare_opcodes PARAMS ((const PTR, const PTR)); +static int compute_arch_mask PARAMS ((unsigned long)); + +/* Sign-extend a value which is N bits long. */ +#define SEX(value, bits) \ + ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ + >> ((8 * sizeof (int)) - bits) ) + +static char *reg_names[] = +{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", + "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", + "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", + "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", + "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", +/* psr, wim, tbr, fpsr, cpsr are v8 only. */ + "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" +}; + +#define freg_names (®_names[4 * 8]) + +/* These are ordered according to there register number in + rdpr and wrpr insns. */ +static char *v9_priv_reg_names[] = +{ + "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", + "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", + "wstate", "fq" + /* "ver" - special cased */ +}; + +/* These are ordered according to there register number in + rd and wr insns (-16). */ +static char *v9a_asr_reg_names[] = +{ + "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", + "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" +}; + +/* Macros used to extract instruction fields. Not all fields have + macros defined here, only those which are actually used. */ + +#define X_RD(i) (((i) >> 25) & 0x1f) +#define X_RS1(i) (((i) >> 14) & 0x1f) +#define X_LDST_I(i) (((i) >> 13) & 1) +#define X_ASI(i) (((i) >> 5) & 0xff) +#define X_RS2(i) (((i) >> 0) & 0x1f) +#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) +#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) +#define X_DISP22(i) (((i) >> 0) & 0x3fffff) +#define X_IMM22(i) X_DISP22 (i) +#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) + +/* These are for v9. */ +#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) +#define X_DISP19(i) (((i) >> 0) & 0x7ffff) +#define X_MEMBAR(i) ((i) & 0x7f) + +/* Here is the union which was used to extract instruction fields + before the shift and mask macros were written. + + union sparc_insn + { + unsigned long int code; + struct + { + unsigned int anop:2; + #define op ldst.anop + unsigned int anrd:5; + #define rd ldst.anrd + unsigned int op3:6; + unsigned int anrs1:5; + #define rs1 ldst.anrs1 + unsigned int i:1; + unsigned int anasi:8; + #define asi ldst.anasi + unsigned int anrs2:5; + #define rs2 ldst.anrs2 + #define shcnt rs2 + } ldst; + struct + { + unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; + unsigned int IMM13:13; + #define imm13 IMM13.IMM13 + } IMM13; + struct + { + unsigned int anop:2; + unsigned int a:1; + unsigned int cond:4; + unsigned int op2:3; + unsigned int DISP22:22; + #define disp22 branch.DISP22 + #define imm22 disp22 + } branch; + struct + { + unsigned int anop:2; + unsigned int a:1; + unsigned int z:1; + unsigned int rcond:3; + unsigned int op2:3; + unsigned int DISP16HI:2; + unsigned int p:1; + unsigned int _rs1:5; + unsigned int DISP16LO:14; + } branch16; + struct + { + unsigned int anop:2; + unsigned int adisp30:30; + #define disp30 call.adisp30 + } call; + }; + + */ + +/* Nonzero if INSN is the opcode for a delayed branch. */ +static int +is_delayed_branch (insn) + unsigned long insn; +{ + struct opcode_hash *op; + + for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) + { + CONST struct sparc_opcode *opcode = op->opcode; + if ((opcode->match & insn) == opcode->match + && (opcode->lose & insn) == 0) + return (opcode->flags & F_DELAYED); + } + return 0; +} + +/* extern void qsort (); */ + +/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value + to compare_opcodes. */ +static unsigned int current_arch_mask; + +/* Print one instruction from MEMADDR on INFO->STREAM. + + We suffix the instruction with a comment that gives the absolute + address involved, as well as its symbolic form, if the instruction + is preceded by a findable `sethi' and it either adds an immediate + displacement to that register, or it is an `add' or `or' instruction + on that register. */ + +int +print_insn_sparc (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + FILE *stream = info->stream; + bfd_byte buffer[4]; + unsigned long insn; + register struct opcode_hash *op; + /* Nonzero of opcode table has been initialized. */ + static int opcodes_initialized = 0; + /* bfd mach number of last call. */ + static unsigned long current_mach = 0; + bfd_vma (*getword) PARAMS ((const unsigned char *)); + + if (!opcodes_initialized + || info->mach != current_mach) + { + int i; + + current_arch_mask = compute_arch_mask (info->mach); + + if (!opcodes_initialized) + sorted_opcodes = (const struct sparc_opcode **) + xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); + /* Reset the sorted table so we can resort it. */ + for (i = 0; i < sparc_num_opcodes; ++i) + sorted_opcodes[i] = &sparc_opcodes[i]; + qsort ((char *) sorted_opcodes, sparc_num_opcodes, + sizeof (sorted_opcodes[0]), compare_opcodes); + + build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); + current_mach = info->mach; + opcodes_initialized = 1; + } + + { + int status = + (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + /* On SPARClite variants such as DANlite (sparc86x), instructions + are always big-endian even when the machine is in little-endian mode. */ + if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) + getword = bfd_getb32; + else + getword = bfd_getl32; + + insn = getword (buffer); + + info->insn_info_valid = 1; /* We do return this info */ + info->insn_type = dis_nonbranch; /* Assume non branch insn */ + info->branch_delay_insns = 0; /* Assume no delay */ + info->target = 0; /* Assume no target known */ + + for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) + { + CONST struct sparc_opcode *opcode = op->opcode; + + /* If the insn isn't supported by the current architecture, skip it. */ + if (! (opcode->architecture & current_arch_mask)) + continue; + + if ((opcode->match & insn) == opcode->match + && (opcode->lose & insn) == 0) + { + /* Nonzero means that we have found an instruction which has + the effect of adding or or'ing the imm13 field to rs1. */ + int imm_added_to_rs1 = 0; + int imm_ored_to_rs1 = 0; + + /* Nonzero means that we have found a plus sign in the args + field of the opcode table. */ + int found_plus = 0; + + /* Nonzero means we have an annulled branch. */ + int is_annulled = 0; + + /* Do we have an `add' or `or' instruction combining an + immediate with rs1? */ + if (opcode->match == 0x80102000) /* or */ + imm_ored_to_rs1 = 1; + if (opcode->match == 0x80002000) /* add */ + imm_added_to_rs1 = 1; + + if (X_RS1 (insn) != X_RD (insn) + && strchr (opcode->args, 'r') != 0) + /* Can't do simple format if source and dest are different. */ + continue; + if (X_RS2 (insn) != X_RD (insn) + && strchr (opcode->args, 'O') != 0) + /* Can't do simple format if source and dest are different. */ + continue; + + (*info->fprintf_func) (stream, opcode->name); + + { + register CONST char *s; + + if (opcode->args[0] != ',') + (*info->fprintf_func) (stream, " "); + for (s = opcode->args; *s != '\0'; ++s) + { + while (*s == ',') + { + (*info->fprintf_func) (stream, ","); + ++s; + switch (*s) { + case 'a': + (*info->fprintf_func) (stream, "a"); + is_annulled = 1; + ++s; + continue; + case 'N': + (*info->fprintf_func) (stream, "pn"); + ++s; + continue; + + case 'T': + (*info->fprintf_func) (stream, "pt"); + ++s; + continue; + + default: + break; + } /* switch on arg */ + } /* while there are comma started args */ + + (*info->fprintf_func) (stream, " "); + + switch (*s) + { + case '+': + found_plus = 1; + + /* note fall-through */ + default: + (*info->fprintf_func) (stream, "%c", *s); + break; + + case '#': + (*info->fprintf_func) (stream, "0"); + break; + +#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) + case '1': + case 'r': + reg (X_RS1 (insn)); + break; + + case '2': + case 'O': + reg (X_RS2 (insn)); + break; + + case 'd': + reg (X_RD (insn)); + break; +#undef reg + +#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) +#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) + case 'e': + freg (X_RS1 (insn)); + break; + case 'v': /* double/even */ + case 'V': /* quad/multiple of 4 */ + fregx (X_RS1 (insn)); + break; + + case 'f': + freg (X_RS2 (insn)); + break; + case 'B': /* double/even */ + case 'R': /* quad/multiple of 4 */ + fregx (X_RS2 (insn)); + break; + + case 'g': + freg (X_RD (insn)); + break; + case 'H': /* double/even */ + case 'J': /* quad/multiple of 4 */ + fregx (X_RD (insn)); + break; +#undef freg +#undef fregx + +#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) + case 'b': + creg (X_RS1 (insn)); + break; + + case 'c': + creg (X_RS2 (insn)); + break; + + case 'D': + creg (X_RD (insn)); + break; +#undef creg + + case 'h': + (*info->fprintf_func) (stream, "%%hi(%#x)", + ((unsigned) 0xFFFFFFFF + & ((int) X_IMM22 (insn) << 10))); + break; + + case 'i': /* 13 bit immediate */ + case 'I': /* 11 bit immediate */ + case 'j': /* 10 bit immediate */ + { + int imm; + + if (*s == 'i') + imm = X_SIMM (insn, 13); + else if (*s == 'I') + imm = X_SIMM (insn, 11); + else + imm = X_SIMM (insn, 10); + + /* Check to see whether we have a 1+i, and take + note of that fact. + + Note: because of the way we sort the table, + we will be matching 1+i rather than i+1, + so it is OK to assume that i is after +, + not before it. */ + if (found_plus) + imm_added_to_rs1 = 1; + + if (imm <= 9) + (*info->fprintf_func) (stream, "%d", imm); + else + (*info->fprintf_func) (stream, "%#x", imm); + } + break; + + case 'X': /* 5 bit unsigned immediate */ + case 'Y': /* 6 bit unsigned immediate */ + { + int imm = X_IMM (insn, *s == 'X' ? 5 : 6); + + if (imm <= 9) + (info->fprintf_func) (stream, "%d", imm); + else + (info->fprintf_func) (stream, "%#x", (unsigned) imm); + } + break; + + case '3': + (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); + break; + + case 'K': + { + int mask = X_MEMBAR (insn); + int bit = 0x40, printed_one = 0; + const char *name; + + if (mask == 0) + (info->fprintf_func) (stream, "0"); + else + while (bit) + { + if (mask & bit) + { + if (printed_one) + (info->fprintf_func) (stream, "|"); + name = sparc_decode_membar (bit); + (info->fprintf_func) (stream, "%s", name); + printed_one = 1; + } + bit >>= 1; + } + break; + } + + case 'k': + info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; + (*info->print_address_func) (info->target, info); + break; + + case 'G': + info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; + (*info->print_address_func) (info->target, info); + break; + + case '6': + case '7': + case '8': + case '9': + (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); + break; + + case 'z': + (*info->fprintf_func) (stream, "%%icc"); + break; + + case 'Z': + (*info->fprintf_func) (stream, "%%xcc"); + break; + + case 'E': + (*info->fprintf_func) (stream, "%%ccr"); + break; + + case 's': + (*info->fprintf_func) (stream, "%%fprs"); + break; + + case 'o': + (*info->fprintf_func) (stream, "%%asi"); + break; + + case 'W': + (*info->fprintf_func) (stream, "%%tick"); + break; + + case 'P': + (*info->fprintf_func) (stream, "%%pc"); + break; + + case '?': + if (X_RS1 (insn) == 31) + (*info->fprintf_func) (stream, "%%ver"); + else if ((unsigned) X_RS1 (insn) < 16) + (*info->fprintf_func) (stream, "%%%s", + v9_priv_reg_names[X_RS1 (insn)]); + else + (*info->fprintf_func) (stream, "%%reserved"); + break; + + case '!': + if ((unsigned) X_RD (insn) < 15) + (*info->fprintf_func) (stream, "%%%s", + v9_priv_reg_names[X_RD (insn)]); + else + (*info->fprintf_func) (stream, "%%reserved"); + break; + + case '/': + if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) + (*info->fprintf_func) (stream, "%%reserved"); + else + (*info->fprintf_func) (stream, "%%%s", + v9a_asr_reg_names[X_RS1 (insn)-16]); + break; + + case '_': + if (X_RD (insn) < 16 || X_RD (insn) > 25) + (*info->fprintf_func) (stream, "%%reserved"); + else + (*info->fprintf_func) (stream, "%%%s", + v9a_asr_reg_names[X_RD (insn)-16]); + break; + + case '*': + { + const char *name = sparc_decode_prefetch (X_RD (insn)); + + if (name) + (*info->fprintf_func) (stream, "%s", name); + else + (*info->fprintf_func) (stream, "%d", X_RD (insn)); + break; + } + + case 'M': + (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); + break; + + case 'm': + (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); + break; + + case 'L': + info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; + (*info->print_address_func) (info->target, info); + break; + + case 'n': + (*info->fprintf_func) + (stream, "%#x", SEX (X_DISP22 (insn), 22)); + break; + + case 'l': + info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; + (*info->print_address_func) (info->target, info); + break; + + case 'A': + { + const char *name = sparc_decode_asi (X_ASI (insn)); + + if (name) + (*info->fprintf_func) (stream, "%s", name); + else + (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); + break; + } + + case 'C': + (*info->fprintf_func) (stream, "%%csr"); + break; + + case 'F': + (*info->fprintf_func) (stream, "%%fsr"); + break; + + case 'p': + (*info->fprintf_func) (stream, "%%psr"); + break; + + case 'q': + (*info->fprintf_func) (stream, "%%fq"); + break; + + case 'Q': + (*info->fprintf_func) (stream, "%%cq"); + break; + + case 't': + (*info->fprintf_func) (stream, "%%tbr"); + break; + + case 'w': + (*info->fprintf_func) (stream, "%%wim"); + break; + + case 'x': + (*info->fprintf_func) (stream, "%d", + ((X_LDST_I (insn) << 8) + + X_ASI (insn))); + break; + + case 'y': + (*info->fprintf_func) (stream, "%%y"); + break; + + case 'u': + case 'U': + { + int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); + const char *name = sparc_decode_sparclet_cpreg (val); + + if (name) + (*info->fprintf_func) (stream, "%s", name); + else + (*info->fprintf_func) (stream, "%%cpreg(%d)", val); + break; + } + } + } + } + + /* If we are adding or or'ing something to rs1, then + check to see whether the previous instruction was + a sethi to the same register as in the sethi. + If so, attempt to print the result of the add or + or (in this context add and or do the same thing) + and its symbolic value. */ + if (imm_ored_to_rs1 || imm_added_to_rs1) + { + unsigned long prev_insn; + int errcode; + + errcode = + (*info->read_memory_func) + (memaddr - 4, buffer, sizeof (buffer), info); + prev_insn = getword (buffer); + + if (errcode == 0) + { + /* If it is a delayed branch, we need to look at the + instruction before the delayed branch. This handles + sequences such as + + sethi %o1, %hi(_foo), %o1 + call _printf + or %o1, %lo(_foo), %o1 + */ + + if (is_delayed_branch (prev_insn)) + { + errcode = (*info->read_memory_func) + (memaddr - 8, buffer, sizeof (buffer), info); + prev_insn = getword (buffer); + } + } + + /* If there was a problem reading memory, then assume + the previous instruction was not sethi. */ + if (errcode == 0) + { + /* Is it sethi to the same register? */ + if ((prev_insn & 0xc1c00000) == 0x01000000 + && X_RD (prev_insn) == X_RS1 (insn)) + { + (*info->fprintf_func) (stream, "\t! "); + info->target = + ((unsigned) 0xFFFFFFFF + & ((int) X_IMM22 (prev_insn) << 10)); + if (imm_added_to_rs1) + info->target += X_SIMM (insn, 13); + else + info->target |= X_SIMM (insn, 13); + (*info->print_address_func) (info->target, info); + info->insn_type = dis_dref; + info->data_size = 4; /* FIXME!!! */ + } + } + } + + if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) + { + /* FIXME -- check is_annulled flag */ + if (opcode->flags & F_UNBR) + info->insn_type = dis_branch; + if (opcode->flags & F_CONDBR) + info->insn_type = dis_condbranch; + if (opcode->flags & F_JSR) + info->insn_type = dis_jsr; + if (opcode->flags & F_DELAYED) + info->branch_delay_insns = 1; + } + + return sizeof (buffer); + } + } + + info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ + (*info->fprintf_func) (stream, _("unknown")); + return sizeof (buffer); +} + +/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ + +static int +compute_arch_mask (mach) + unsigned long mach; +{ + switch (mach) + { + case 0 : + case bfd_mach_sparc : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); + case bfd_mach_sparc_sparclet : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); + case bfd_mach_sparc_sparclite : + case bfd_mach_sparc_sparclite_le : + /* sparclites insns are recognized by default (because that's how + they've always been treated, for better or worse). Kludge this by + indicating generic v8 is also selected. */ + return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) + | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); + case bfd_mach_sparc_v8plus : + case bfd_mach_sparc_v9 : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); + case bfd_mach_sparc_v8plusa : + case bfd_mach_sparc_v9a : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); + case bfd_mach_sparc_v8plusb : + case bfd_mach_sparc_v9b : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); + } + abort (); +} + +/* Compare opcodes A and B. */ + +static int +compare_opcodes (a, b) + const PTR a; + const PTR b; +{ + struct sparc_opcode *op0 = * (struct sparc_opcode **) a; + struct sparc_opcode *op1 = * (struct sparc_opcode **) b; + unsigned long int match0 = op0->match, match1 = op1->match; + unsigned long int lose0 = op0->lose, lose1 = op1->lose; + register unsigned int i; + + /* If one (and only one) insn isn't supported by the current architecture, + prefer the one that is. If neither are supported, but they're both for + the same architecture, continue processing. Otherwise (both unsupported + and for different architectures), prefer lower numbered arch's (fudged + by comparing the bitmasks). */ + if (op0->architecture & current_arch_mask) + { + if (! (op1->architecture & current_arch_mask)) + return -1; + } + else + { + if (op1->architecture & current_arch_mask) + return 1; + else if (op0->architecture != op1->architecture) + return op0->architecture - op1->architecture; + } + + /* If a bit is set in both match and lose, there is something + wrong with the opcode table. */ + if (match0 & lose0) + { + fprintf + (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), + op0->name, match0, lose0); + op0->lose &= ~op0->match; + lose0 = op0->lose; + } + + if (match1 & lose1) + { + fprintf + (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), + op1->name, match1, lose1); + op1->lose &= ~op1->match; + lose1 = op1->lose; + } + + /* Because the bits that are variable in one opcode are constant in + another, it is important to order the opcodes in the right order. */ + for (i = 0; i < 32; ++i) + { + unsigned long int x = 1 << i; + int x0 = (match0 & x) != 0; + int x1 = (match1 & x) != 0; + + if (x0 != x1) + return x1 - x0; + } + + for (i = 0; i < 32; ++i) + { + unsigned long int x = 1 << i; + int x0 = (lose0 & x) != 0; + int x1 = (lose1 & x) != 0; + + if (x0 != x1) + return x1 - x0; + } + + /* They are functionally equal. So as long as the opcode table is + valid, we can put whichever one first we want, on aesthetic grounds. */ + + /* Our first aesthetic ground is that aliases defer to real insns. */ + { + int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); + if (alias_diff != 0) + /* Put the one that isn't an alias first. */ + return alias_diff; + } + + /* Except for aliases, two "identical" instructions had + better have the same opcode. This is a sanity check on the table. */ + i = strcmp (op0->name, op1->name); + if (i) + { + if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ + return i; + else + fprintf (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), + op0->name, op1->name); + } + + /* Fewer arguments are preferred. */ + { + int length_diff = strlen (op0->args) - strlen (op1->args); + if (length_diff != 0) + /* Put the one with fewer arguments first. */ + return length_diff; + } + + /* Put 1+i before i+1. */ + { + char *p0 = (char *) strchr (op0->args, '+'); + char *p1 = (char *) strchr (op1->args, '+'); + + if (p0 && p1) + { + /* There is a plus in both operands. Note that a plus + sign cannot be the first character in args, + so the following [-1]'s are valid. */ + if (p0[-1] == 'i' && p1[1] == 'i') + /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ + return 1; + if (p0[1] == 'i' && p1[-1] == 'i') + /* op0 is 1+i and op1 is i+1, so op0 goes first. */ + return -1; + } + } + + /* Put 1,i before i,1. */ + { + int i0 = strncmp (op0->args, "i,1", 3) == 0; + int i1 = strncmp (op1->args, "i,1", 3) == 0; + + if (i0 ^ i1) + return i0 - i1; + } + + /* They are, as far as we can tell, identical. + Since qsort may have rearranged the table partially, there is + no way to tell which one was first in the opcode table as + written, so just say there are equal. */ + /* ??? This is no longer true now that we sort a vector of pointers, + not the table itself. */ + return 0; +} + +/* Build a hash table from the opcode table. + OPCODE_TABLE is a sorted list of pointers into the opcode table. */ + +static void +build_hash_table (opcode_table, hash_table, num_opcodes) + const struct sparc_opcode **opcode_table; + struct opcode_hash **hash_table; + int num_opcodes; +{ + register int i; + int hash_count[HASH_SIZE]; + static struct opcode_hash *hash_buf = NULL; + + /* Start at the end of the table and work backwards so that each + chain is sorted. */ + + memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); + memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); + if (hash_buf != NULL) + free (hash_buf); + hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes); + for (i = num_opcodes - 1; i >= 0; --i) + { + register int hash = HASH_INSN (opcode_table[i]->match); + register struct opcode_hash *h = &hash_buf[i]; + h->next = hash_table[hash]; + h->opcode = opcode_table[i]; + hash_table[hash] = h; + ++hash_count[hash]; + } + +#if 0 /* for debugging */ + { + int min_count = num_opcodes, max_count = 0; + int total; + + for (i = 0; i < HASH_SIZE; ++i) + { + if (hash_count[i] < min_count) + min_count = hash_count[i]; + if (hash_count[i] > max_count) + max_count = hash_count[i]; + total += hash_count[i]; + } + + printf ("Opcode hash table stats: min %d, max %d, ave %f\n", + min_count, max_count, (double) total / HASH_SIZE); + } +#endif +} diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c new file mode 100644 index 0000000..5c06d01 --- /dev/null +++ b/opcodes/sparc-opc.c @@ -0,0 +1,2056 @@ +/* Table of opcodes for the sparc. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000 + Free Software Foundation, Inc. + +This file is part of the BFD library. + +BFD is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. + +BFD is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with this software; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* FIXME-someday: perhaps the ,a's and such should be embedded in the + instruction's name rather than the args. This would make gas faster, pinsn + slower, but would mess up some macros a bit. xoxorich. */ + +#include +#include "sysdep.h" +#include "opcode/sparc.h" + +/* Some defines to make life easy. */ +#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) +#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) +#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) +#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) +#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) +#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) +#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) +#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) + +/* Bit masks of architectures supporting the insn. */ + +#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) +/* v6 insns not supported on the sparclet */ +#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) +#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) +/* Although not all insns are implemented in hardware, sparclite is defined + to be a superset of v8. Unimplemented insns trap and are then theoretically + implemented in software. + It's not clear that the same is true for sparclet, although the docs + suggest it is. Rather than complicating things, the sparclet assembler + recognizes all v8 insns. */ +#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ + | MASK_V9 | MASK_V9A | MASK_V9B) +#define sparclet (MASK_SPARCLET) +#define sparclite (MASK_SPARCLITE) +#define v9 (MASK_V9 | MASK_V9A | MASK_V9B) +#define v9a (MASK_V9A | MASK_V9B) +#define v9b (MASK_V9B) +/* v6 insns not supported by v9 */ +#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ + | MASK_SPARCLET | MASK_SPARCLITE) +/* v9a instructions which would appear to be aliases to v9's impdep's + otherwise */ +#define v9notv9a (MASK_V9) + +/* Table of opcode architectures. + The order is defined in opcode/sparc.h. */ + +const struct sparc_opcode_arch sparc_opcode_archs[] = { + { "v6", MASK_V6 }, + { "v7", MASK_V6 | MASK_V7 }, + { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, + { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, + { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, + /* ??? Don't some v8 priviledged insns conflict with v9? */ + { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, + /* v9 with ultrasparc additions */ + { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, + /* v9 with cheetah additions */ + { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B }, + { NULL, 0 } +}; + +/* Given NAME, return it's architecture entry. */ + +enum sparc_opcode_arch_val +sparc_opcode_lookup_arch (name) + const char *name; +{ + const struct sparc_opcode_arch *p; + + for (p = &sparc_opcode_archs[0]; p->name; ++p) + { + if (strcmp (name, p->name) == 0) + return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); + } + + return SPARC_OPCODE_ARCH_BAD; +} + +/* Branch condition field. */ +#define COND(x) (((x)&0xf)<<25) + +/* v9: Move (MOVcc and FMOVcc) condition field. */ +#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ + +/* v9: Move register (MOVRcc and FMOVRcc) condition field. */ +#define RCOND(x) (((x)&0x7)<<10) /* v9 */ + +#define CONDA (COND(0x8)) +#define CONDCC (COND(0xd)) +#define CONDCS (COND(0x5)) +#define CONDE (COND(0x1)) +#define CONDG (COND(0xa)) +#define CONDGE (COND(0xb)) +#define CONDGU (COND(0xc)) +#define CONDL (COND(0x3)) +#define CONDLE (COND(0x2)) +#define CONDLEU (COND(0x4)) +#define CONDN (COND(0x0)) +#define CONDNE (COND(0x9)) +#define CONDNEG (COND(0x6)) +#define CONDPOS (COND(0xe)) +#define CONDVC (COND(0xf)) +#define CONDVS (COND(0x7)) + +#define CONDNZ CONDNE +#define CONDZ CONDE +#define CONDGEU CONDCC +#define CONDLU CONDCS + +#define FCONDA (COND(0x8)) +#define FCONDE (COND(0x9)) +#define FCONDG (COND(0x6)) +#define FCONDGE (COND(0xb)) +#define FCONDL (COND(0x4)) +#define FCONDLE (COND(0xd)) +#define FCONDLG (COND(0x2)) +#define FCONDN (COND(0x0)) +#define FCONDNE (COND(0x1)) +#define FCONDO (COND(0xf)) +#define FCONDU (COND(0x7)) +#define FCONDUE (COND(0xa)) +#define FCONDUG (COND(0x5)) +#define FCONDUGE (COND(0xc)) +#define FCONDUL (COND(0x3)) +#define FCONDULE (COND(0xe)) + +#define FCONDNZ FCONDNE +#define FCONDZ FCONDE + +#define ICC (0) /* v9 */ +#define XCC (1<<12) /* v9 */ +#define FCC(x) (((x)&0x3)<<11) /* v9 */ +#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ + +/* The order of the opcodes in the table is significant: + + * The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. + +*/ + +/* Entries for commutative arithmetic operations. */ +/* ??? More entries can make use of this. */ +#define COMMUTEOP(opcode, op3, arch_mask) \ +{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ +{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ +{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } + +const struct sparc_opcode sparc_opcodes[] = { + +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ + +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ + +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ + +/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the + 'ld' pseudo-op in v9. */ +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ + +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ + +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ + +{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ + +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ + +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ + +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ + +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ + +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ + +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ + +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ + +{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ + +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ +{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, +{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ + +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ + +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ + +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ + +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ + +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ + +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ + +{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, +{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ + +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ + +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ + +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ + +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ + +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ + +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ + +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ + +{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ + +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ + +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ + +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ + +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ + +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ + +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ + +{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, +{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ + +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ + +{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, +{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ + +{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, +{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ + +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ + +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ + +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ + +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ + +{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, +{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, + +{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ +{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ + +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, + +{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, + +{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, +{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, + +/* IFLUSH was renamed to FLUSH in v8. */ +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, + +{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, +{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, + +{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, + +{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, +{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, + +{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ +{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ + +{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, +{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, +{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, +{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, +{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, +{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, + +{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, +{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, +{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, +{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, +{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, +{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, + +{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, + +{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, +{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, + +{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, +{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, + +{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, +{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, + +{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ +{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ + +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ + +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ + +{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ + +{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, + +/* This is not a commutative instruction. */ +{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, + +/* This is not a commutative instruction. */ +{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, + +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ +{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ + +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ +{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ +{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ +{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ + +{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ +{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ +{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ +{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ +{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ +{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ + +{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ +{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ +{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ +{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ +{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ +{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ +{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ +{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ +{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ +{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ +{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ +{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ +{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ +{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ +{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ +{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ +{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ +{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ +{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ +{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ + +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ +{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ +{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ +{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ + +{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ +{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ +{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ +{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ + +{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ +{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ +{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ +{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ + +{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ +{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ +{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ + +/* ??? This group seems wrong. A three operand move? */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ + +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ +{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ +{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ +{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ + +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ + +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ + +{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, + +{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ +{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ + +/* This is not a commutative instruction. */ +{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, + +/* This is not a commutative instruction. */ +{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, + +{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ +{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ + +{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ +{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ + +{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, + +{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, + +{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, +{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, + +{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, +{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, + +{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, + +{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, + +{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ +{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ +{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ +{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ +{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ +{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ +{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ +{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ + +{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ +{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ + +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ + +{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, + +{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, +{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, +{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, + +{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, +{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, +{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, + +{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, + +{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, +{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, +{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, + +{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, +{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, + +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, + + +/* Conditional instructions. + + Because this part of the table was such a mess earlier, I have + macrofied it so that all the branches and traps are generated from + a single-line description of each condition value. John Gilmore. */ + +/* Define branches -- one annulled, one without, etc. */ +#define br(opcode, mask, lose, flags) \ + { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ + { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } + +#define brx(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ + { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } + +/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ +#define tr(opcode, mask, lose, flags) \ + { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ + { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ + { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ + { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ + { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ + { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ + { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ + { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ + { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ + { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ + { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ + { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ + +/* v9: We must put `brx' before `br', to ensure that we never match something + v9: against an expression unless it is an expression. Otherwise, we end + v9: up with undefined symbol tables entries, because they get added, but + v9: are not deleted if the pattern fails to match. */ + +/* Define both branches and traps based on condition mask */ +#define cond(bop, top, mask, flags) \ + brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ + br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ + tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) + +/* Define all the conditions, all the branches, all the traps. */ + +/* Standard branch, trap mnemonics */ +cond ("b", "ta", CONDA, F_UNBR), +/* Alternative form (just for assembly, not for disassembly) */ +cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), + +cond ("bcc", "tcc", CONDCC, F_CONDBR), +cond ("bcs", "tcs", CONDCS, F_CONDBR), +cond ("be", "te", CONDE, F_CONDBR), +cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), +cond ("bg", "tg", CONDG, F_CONDBR), +cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), +cond ("bge", "tge", CONDGE, F_CONDBR), +cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ +cond ("bgu", "tgu", CONDGU, F_CONDBR), +cond ("bl", "tl", CONDL, F_CONDBR), +cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), +cond ("ble", "tle", CONDLE, F_CONDBR), +cond ("bleu", "tleu", CONDLEU, F_CONDBR), +cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ +cond ("bn", "tn", CONDN, F_CONDBR), +cond ("bne", "tne", CONDNE, F_CONDBR), +cond ("bneg", "tneg", CONDNEG, F_CONDBR), +cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ +cond ("bpos", "tpos", CONDPOS, F_CONDBR), +cond ("bvc", "tvc", CONDVC, F_CONDBR), +cond ("bvs", "tvs", CONDVS, F_CONDBR), +cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ + +#undef cond +#undef br +#undef brr /* v9 */ +#undef tr + +#define brr(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } + +#define condr(bop, mask, flags) /* v9 */ \ + brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ + +/* v9 */ condr("brnz", 0x5, F_CONDBR), +/* v9 */ condr("brz", 0x1, F_CONDBR), +/* v9 */ condr("brgez", 0x7, F_CONDBR), +/* v9 */ condr("brlz", 0x3, F_CONDBR), +/* v9 */ condr("brlez", 0x2, F_CONDBR), +/* v9 */ condr("brgz", 0x6, F_CONDBR), + +#undef condr /* v9 */ +#undef brr /* v9 */ + +#define movr(opcode, mask, flags) /* v9 */ \ + { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ + { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } + +#define fmrrs(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } +#define fmrrd(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } +#define fmrrq(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } + +#define fmovrs(mop, mask, flags) /* v9 */ \ + fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ +#define fmovrd(mop, mask, flags) /* v9 */ \ + fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ +#define fmovrq(mop, mask, flags) /* v9 */ \ + fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ + +/* v9 */ movr("movrne", 0x5, 0), +/* v9 */ movr("movre", 0x1, 0), +/* v9 */ movr("movrgez", 0x7, 0), +/* v9 */ movr("movrlz", 0x3, 0), +/* v9 */ movr("movrlez", 0x2, 0), +/* v9 */ movr("movrgz", 0x6, 0), +/* v9 */ movr("movrnz", 0x5, F_ALIAS), +/* v9 */ movr("movrz", 0x1, F_ALIAS), + +/* v9 */ fmovrs("fmovrsne", 0x5, 0), +/* v9 */ fmovrs("fmovrse", 0x1, 0), +/* v9 */ fmovrs("fmovrsgez", 0x7, 0), +/* v9 */ fmovrs("fmovrslz", 0x3, 0), +/* v9 */ fmovrs("fmovrslez", 0x2, 0), +/* v9 */ fmovrs("fmovrsgz", 0x6, 0), +/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), +/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), + +/* v9 */ fmovrd("fmovrdne", 0x5, 0), +/* v9 */ fmovrd("fmovrde", 0x1, 0), +/* v9 */ fmovrd("fmovrdgez", 0x7, 0), +/* v9 */ fmovrd("fmovrdlz", 0x3, 0), +/* v9 */ fmovrd("fmovrdlez", 0x2, 0), +/* v9 */ fmovrd("fmovrdgz", 0x6, 0), +/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), +/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), + +/* v9 */ fmovrq("fmovrqne", 0x5, 0), +/* v9 */ fmovrq("fmovrqe", 0x1, 0), +/* v9 */ fmovrq("fmovrqgez", 0x7, 0), +/* v9 */ fmovrq("fmovrqlz", 0x3, 0), +/* v9 */ fmovrq("fmovrqlez", 0x2, 0), +/* v9 */ fmovrq("fmovrqgz", 0x6, 0), +/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), +/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), + +#undef movr /* v9 */ +#undef fmovr /* v9 */ +#undef fmrr /* v9 */ + +#define movicc(opcode, cond, flags) /* v9 */ \ + { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } + +#define movfcc(opcode, fcond, flags) /* v9 */ \ + { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } + +#define movcc(opcode, cond, fcond, flags) /* v9 */ \ + movfcc (opcode, fcond, flags), /* v9 */ \ + movicc (opcode, cond, flags) /* v9 */ + +/* v9 */ movcc ("mova", CONDA, FCONDA, 0), +/* v9 */ movicc ("movcc", CONDCC, 0), +/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), +/* v9 */ movicc ("movcs", CONDCS, 0), +/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), +/* v9 */ movcc ("move", CONDE, FCONDE, 0), +/* v9 */ movcc ("movg", CONDG, FCONDG, 0), +/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), +/* v9 */ movicc ("movgu", CONDGU, 0), +/* v9 */ movcc ("movl", CONDL, FCONDL, 0), +/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), +/* v9 */ movicc ("movleu", CONDLEU, 0), +/* v9 */ movfcc ("movlg", FCONDLG, 0), +/* v9 */ movcc ("movn", CONDN, FCONDN, 0), +/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), +/* v9 */ movicc ("movneg", CONDNEG, 0), +/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), +/* v9 */ movfcc ("movo", FCONDO, 0), +/* v9 */ movicc ("movpos", CONDPOS, 0), +/* v9 */ movfcc ("movu", FCONDU, 0), +/* v9 */ movfcc ("movue", FCONDUE, 0), +/* v9 */ movfcc ("movug", FCONDUG, 0), +/* v9 */ movfcc ("movuge", FCONDUGE, 0), +/* v9 */ movfcc ("movul", FCONDUL, 0), +/* v9 */ movfcc ("movule", FCONDULE, 0), +/* v9 */ movicc ("movvc", CONDVC, 0), +/* v9 */ movicc ("movvs", CONDVS, 0), +/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), + +#undef movicc /* v9 */ +#undef movfcc /* v9 */ +#undef movcc /* v9 */ + +#define FM_SF 1 /* v9 - values for fpsize */ +#define FM_DF 2 /* v9 */ +#define FM_QF 3 /* v9 */ + +#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \ +{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 } + +#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \ +{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 } + +/* FIXME: use fmovicc/fmovfcc? */ /* v9 */ +#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \ +{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 } + +/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0), +/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0), +/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0), +/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0), +/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0), +/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0), +/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0), +/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0), +/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0), +/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0), +/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0), +/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0), +/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0), +/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0), +/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0), +/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0), +/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0), +/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0), +/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS), +/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS), +/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS), +/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0), +/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0), +/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0), +/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0), +/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0), +/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0), +/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0), +/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0), +/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0), +/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0), +/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0), +/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0), +/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0), +/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0), +/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0), +/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS), +/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS), +/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS), +/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0), +/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0), +/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0), +/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0), +/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0), +/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0), +/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0), +/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0), +/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0), +/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS), +/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS), +/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS), +/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0), +/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0), +/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0), +/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0), +/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0), +/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0), +/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0), +/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0), +/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0), +/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0), +/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0), +/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0), +/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0), +/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0), +/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0), +/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0), +/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0), +/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0), +/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0), +/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0), +/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0), +/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0), +/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0), +/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0), +/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0), +/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0), +/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0), +/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0), +/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0), +/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0), +/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS), +/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS), +/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS), + +#undef fmovicc /* v9 */ +#undef fmovfcc /* v9 */ +#undef fmovcc /* v9 */ +#undef FM_DF /* v9 */ +#undef FM_QF /* v9 */ +#undef FM_SF /* v9 */ + +/* Coprocessor branches. */ +#define CBR(opcode, mask, lose, flags, arch) \ + { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \ + { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch } + +/* Floating point branches. */ +#define FBR(opcode, mask, lose, flags) \ + { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \ + { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 } + +/* V9 extended floating point branches. */ +#define FBRX(opcode, mask, lose, flags) /* v9 */ \ + { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } + +/* v9: We must put `FBRX' before `FBR', to ensure that we never match + v9: something against an expression unless it is an expression. Otherwise, + v9: we end up with undefined symbol tables entries, because they get added, + v9: but are not deleted if the pattern fails to match. */ + +#define CONDFC(fop, cop, mask, flags) \ + FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ + FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ + CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) + +#define CONDFCL(fop, cop, mask, flags) \ + FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ + FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ + CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) + +#define CONDF(fop, mask, flags) \ + FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ + FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) + +CONDFC ("fb", "cb", 0x8, 0), +CONDFCL ("fba", "cba", 0x8, F_ALIAS), +CONDFC ("fbe", "cb0", 0x9, 0), +CONDF ("fbz", 0x9, F_ALIAS), +CONDFC ("fbg", "cb2", 0x6, 0), +CONDFC ("fbge", "cb02", 0xb, 0), +CONDFC ("fbl", "cb1", 0x4, 0), +CONDFC ("fble", "cb01", 0xd, 0), +CONDFC ("fblg", "cb12", 0x2, 0), +CONDFCL ("fbn", "cbn", 0x0, 0), +CONDFC ("fbne", "cb123", 0x1, 0), +CONDF ("fbnz", 0x1, F_ALIAS), +CONDFC ("fbo", "cb012", 0xf, 0), +CONDFC ("fbu", "cb3", 0x7, 0), +CONDFC ("fbue", "cb03", 0xa, 0), +CONDFC ("fbug", "cb23", 0x5, 0), +CONDFC ("fbuge", "cb023", 0xc, 0), +CONDFC ("fbul", "cb13", 0x3, 0), +CONDFC ("fbule", "cb013", 0xe, 0), + +#undef CONDFC +#undef CONDFCL +#undef CONDF +#undef CBR +#undef FBR +#undef FBRX /* v9 */ + +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ + +{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ + +{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, +{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, +{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, +{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, + +{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, + +{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, + +{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, +{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, + +{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, +{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, + +/* This *is* a commutative instruction. */ +{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, +/* This *is* a commutative instruction. */ +{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, +{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, + +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ + +{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ +{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ + +/* FPop1 and FPop2 are not instructions. Don't accept them. */ + +{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, +{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, + +{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, +{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, +{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, + +{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, +{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, + +{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, +{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, +{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, + +{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, +{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, +{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, +{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, +{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, +{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, + +{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, +{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, +{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, +{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, +{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, +{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, + +{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, +{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, +{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, + +{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, +{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, +{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, + +{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, +{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, +{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, +{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, +{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, +{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, +{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, + +{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, +{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, +{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, +{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, +{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, +{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, + +#define CMPFCC(x) (((x)&0x3)<<25) + +{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, +{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, +{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, +{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, +{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, +{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, +{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, +{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, +{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, +{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, +{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, +{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, +{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, +{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, +{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, +{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, +{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, +{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, +{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, +{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, +{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, +{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, +{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, +{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, +{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, +{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, +{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, +{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, +{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, +{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, +{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, +{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, + +/* These Extended FPop (FIFO) instructions are new in the Fujitsu + MB86934, replacing the CPop instructions from v6 and later + processors. */ + +#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } +#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } +#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } + +EFPOP1_2 ("efitod", 0x0c8, "f,H"), +EFPOP1_2 ("efitos", 0x0c4, "f,g"), +EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), +EFPOP1_2 ("efstoi", 0x0d1, "f,g"), +EFPOP1_2 ("efstod", 0x0c9, "f,H"), +EFPOP1_2 ("efdtos", 0x0c6, "B,g"), +EFPOP1_2 ("efmovs", 0x001, "f,g"), +EFPOP1_2 ("efnegs", 0x005, "f,g"), +EFPOP1_2 ("efabss", 0x009, "f,g"), +EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), +EFPOP1_2 ("efsqrts", 0x029, "f,g"), +EFPOP1_3 ("efaddd", 0x042, "v,B,H"), +EFPOP1_3 ("efadds", 0x041, "e,f,g"), +EFPOP1_3 ("efsubd", 0x046, "v,B,H"), +EFPOP1_3 ("efsubs", 0x045, "e,f,g"), +EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), +EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), +EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), +EFPOP1_3 ("efmuls", 0x049, "e,f,g"), +EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), +EFPOP2_2 ("efcmpd", 0x052, "v,B"), +EFPOP2_2 ("efcmped", 0x056, "v,B"), +EFPOP2_2 ("efcmps", 0x051, "e,f"), +EFPOP2_2 ("efcmpes", 0x055, "e,f"), + +#undef EFPOP1_2 +#undef EFPOP1_3 +#undef EFPOP2_2 + +/* These are marked F_ALIAS, so that they won't conflict with sparclite insns + present. Otherwise, the F_ALIAS flag is ignored. */ +{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, +{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, + +/* sparclet specific insns */ + +COMMUTEOP ("umac", 0x3e, sparclet), +COMMUTEOP ("smac", 0x3f, sparclet), +COMMUTEOP ("umacd", 0x2e, sparclet), +COMMUTEOP ("smacd", 0x2f, sparclet), +COMMUTEOP ("umuld", 0x09, sparclet), +COMMUTEOP ("smuld", 0x0d, sparclet), + +{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, +{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, + +/* The manual isn't completely accurate on these insns. The `rs2' field is + treated as being 6 bits to account for 6 bit immediates to cpush. It is + assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ +#define BIT5 (1<<5) +{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, +{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, +{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, +{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, +{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, +{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, +{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, +#undef BIT5 + +/* sparclet coprocessor branch insns */ +#define SLCBCC2(opcode, mask, lose) \ + { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ + { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } +#define SLCBCC(opcode, mask) \ + SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) + +/* cbn,cba can't be defined here because they're defined elsewhere and GAS + requires all mnemonics of the same name to be consecutive. */ +/*SLCBCC("cbn", 0), - already defined */ +SLCBCC("cbe", 1), +SLCBCC("cbf", 2), +SLCBCC("cbef", 3), +SLCBCC("cbr", 4), +SLCBCC("cber", 5), +SLCBCC("cbfr", 6), +SLCBCC("cbefr", 7), +/*SLCBCC("cba", 8), - already defined */ +SLCBCC("cbne", 9), +SLCBCC("cbnf", 10), +SLCBCC("cbnef", 11), +SLCBCC("cbnr", 12), +SLCBCC("cbner", 13), +SLCBCC("cbnfr", 14), +SLCBCC("cbnefr", 15), + +#undef SLCBCC2 +#undef SLCBCC + +{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, +{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, +{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, +{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, + +/* v9 synthetic insns */ +{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ +{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ +{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ +{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ +{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ + +/* Ultrasparc extensions */ +{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, + +/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ +{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, +{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, +{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, +{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, +{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, +{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, +{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, +{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, + +{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, +{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, +{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, +{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, +{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, + +/* Note that the mixing of 32/64 bit regs is intentional. */ +{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, +{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, +{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, +{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, +{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, +{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, +{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, + +{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, +{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, +{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, + +{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, +{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, +{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, +{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, +{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, +{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, +{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, +{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, +{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, +{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, +{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, +{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, +{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, +{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, +{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, +{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, +{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, +{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, +{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, +{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, +{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, +{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, +{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, +{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, +{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, +{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, +{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, +{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, +{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, +{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, +{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, +{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, + +{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, +{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, +{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, +{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, +{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, +{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, +{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, +{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, + +{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, +{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, +{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, +{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, +{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, +{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, + +{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, + +{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, +{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, +{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, + +/* Cheetah instructions */ +{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, +{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b }, +{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b }, +{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b }, +{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b }, +{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b }, + +{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b }, +{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b }, + +{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, + +/* More v9 specific insns, these need to come last so they do not clash + with v9a instructions such as "edge8" which looks like impdep1. */ + +#define IMPDEP(name, code) \ +{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ +{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ +{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ +{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } + +IMPDEP ("impdep1", 0x36), +IMPDEP ("impdep2", 0x37), + +#undef IMPDEP + +}; + +const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); + +/* Utilities for argument parsing. */ + +typedef struct +{ + int value; + const char *name; +} arg; + +/* Look up NAME in TABLE. */ + +static int lookup_name PARAMS ((const arg *, const char *)); +static const char *lookup_value PARAMS ((const arg *, int)); + +static int +lookup_name (table, name) + const arg *table; + const char *name; +{ + const arg *p; + + for (p = table; p->name; ++p) + if (strcmp (name, p->name) == 0) + return p->value; + + return -1; +} + +/* Look up VALUE in TABLE. */ + +static const char * +lookup_value (table, value) + const arg *table; + int value; +{ + const arg *p; + + for (p = table; p->name; ++p) + if (value == p->value) + return p->name; + + return (char *) 0; +} + +/* Handle ASI's. */ + +static arg asi_table[] = +{ + /* These are in the v9 architecture manual. */ + /* The shorter versions appear first, they're here because Sun's as has them. + Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the + UltraSPARC architecture manual). */ + { 0x04, "#ASI_N" }, + { 0x0c, "#ASI_N_L" }, + { 0x10, "#ASI_AIUP" }, + { 0x11, "#ASI_AIUS" }, + { 0x18, "#ASI_AIUP_L" }, + { 0x19, "#ASI_AIUS_L" }, + { 0x80, "#ASI_P" }, + { 0x81, "#ASI_S" }, + { 0x82, "#ASI_PNF" }, + { 0x83, "#ASI_SNF" }, + { 0x88, "#ASI_P_L" }, + { 0x89, "#ASI_S_L" }, + { 0x8a, "#ASI_PNF_L" }, + { 0x8b, "#ASI_SNF_L" }, + { 0x04, "#ASI_NUCLEUS" }, + { 0x0c, "#ASI_NUCLEUS_LITTLE" }, + { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, + { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, + { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, + { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, + { 0x80, "#ASI_PRIMARY" }, + { 0x81, "#ASI_SECONDARY" }, + { 0x82, "#ASI_PRIMARY_NOFAULT" }, + { 0x83, "#ASI_SECONDARY_NOFAULT" }, + { 0x88, "#ASI_PRIMARY_LITTLE" }, + { 0x89, "#ASI_SECONDARY_LITTLE" }, + { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, + { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, + /* These are UltraSPARC extensions. */ + /* FIXME: There are dozens of them. Not sure we want them all. + Most are for kernel building but some are for vis type stuff. */ + { 0, 0 } +}; + +/* Return the value for ASI NAME, or -1 if not found. */ + +int +sparc_encode_asi (name) + const char *name; +{ + return lookup_name (asi_table, name); +} + +/* Return the name for ASI value VALUE or NULL if not found. */ + +const char * +sparc_decode_asi (value) + int value; +{ + return lookup_value (asi_table, value); +} + +/* Handle membar masks. */ + +static arg membar_table[] = +{ + { 0x40, "#Sync" }, + { 0x20, "#MemIssue" }, + { 0x10, "#Lookaside" }, + { 0x08, "#StoreStore" }, + { 0x04, "#LoadStore" }, + { 0x02, "#StoreLoad" }, + { 0x01, "#LoadLoad" }, + { 0, 0 } +}; + +/* Return the value for membar arg NAME, or -1 if not found. */ + +int +sparc_encode_membar (name) + const char *name; +{ + return lookup_name (membar_table, name); +} + +/* Return the name for membar value VALUE or NULL if not found. */ + +const char * +sparc_decode_membar (value) + int value; +{ + return lookup_value (membar_table, value); +} + +/* Handle prefetch args. */ + +static arg prefetch_table[] = +{ + { 0, "#n_reads" }, + { 1, "#one_read" }, + { 2, "#n_writes" }, + { 3, "#one_write" }, + { 4, "#page" }, + { 16, "#invalidate" }, + { 0, 0 } +}; + +/* Return the value for prefetch arg NAME, or -1 if not found. */ + +int +sparc_encode_prefetch (name) + const char *name; +{ + return lookup_name (prefetch_table, name); +} + +/* Return the name for prefetch value VALUE or NULL if not found. */ + +const char * +sparc_decode_prefetch (value) + int value; +{ + return lookup_value (prefetch_table, value); +} + +/* Handle sparclet coprocessor registers. */ + +static arg sparclet_cpreg_table[] = +{ + { 0, "%ccsr" }, + { 1, "%ccfr" }, + { 2, "%cccrcr" }, + { 3, "%ccpr" }, + { 4, "%ccsr2" }, + { 5, "%cccrr" }, + { 6, "%ccrstr" }, + { 0, 0 } +}; + +/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ + +int +sparc_encode_sparclet_cpreg (name) + const char *name; +{ + return lookup_name (sparclet_cpreg_table, name); +} + +/* Return the name for sparclet cpreg value VALUE or NULL if not found. */ + +const char * +sparc_decode_sparclet_cpreg (value) + int value; +{ + return lookup_value (sparclet_cpreg_table, value); +} diff --git a/opcodes/stamp-h.in b/opcodes/stamp-h.in new file mode 100644 index 0000000..9788f70 --- /dev/null +++ b/opcodes/stamp-h.in @@ -0,0 +1 @@ +timestamp diff --git a/opcodes/sysdep.h b/opcodes/sysdep.h new file mode 100644 index 0000000..ce9adde --- /dev/null +++ b/opcodes/sysdep.h @@ -0,0 +1,42 @@ +/* Random host-dependent support code. + Copyright 1995, 1997, 2000 Free Software Foundation, Inc. + Written by Ken Raeburn. + +This file is part of libopcodes, the opcodes library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Do system-dependent stuff, mainly driven by autoconf-detected info. + + Well, some generic common stuff is done here too, like including + ansidecl.h. That's because the .h files in bfd/hosts files I'm + trying to replace often did that. If it can be dropped from this + file (check in a non-ANSI environment!), it should be. */ + +#include "config.h" + +#include "ansidecl.h" + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c new file mode 100644 index 0000000..67956f7 --- /dev/null +++ b/opcodes/tic30-dis.c @@ -0,0 +1,710 @@ +/* Disassembly routines for TMS320C30 architecture + Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic30.h" + +#define NORMAL_INSN 1 +#define PARALLEL_INSN 2 + +/* Gets the type of instruction based on the top 2 or 3 bits of the + instruction word. */ +#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) + +/* Instruction types. */ +#define TWO_OPERAND_1 0x00000000 +#define TWO_OPERAND_2 0x40000000 +#define THREE_OPERAND 0x20000000 +#define PAR_STORE 0xC0000000 +#define MUL_ADDS 0x80000000 +#define BRANCHES 0x60000000 + +/* Specific instruction id bits. */ +#define NORMAL_IDEN 0x1F800000 +#define PAR_STORE_IDEN 0x3E000000 +#define MUL_ADD_IDEN 0x2C000000 +#define BR_IMM_IDEN 0x1F000000 +#define BR_COND_IDEN 0x1C3F0000 + +/* Addressing modes. */ +#define AM_REGISTER 0x00000000 +#define AM_DIRECT 0x00200000 +#define AM_INDIRECT 0x00400000 +#define AM_IMM 0x00600000 + +#define P_FIELD 0x03000000 + +#define REG_AR0 0x08 +#define LDP_INSN 0x08700000 + +/* TMS320C30 program counter for current instruction. */ +static unsigned int _pc; + +struct instruction +{ + int type; + template *tm; + partemplate *ptm; +}; + +int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); +int print_two_operand + PARAMS ((disassemble_info *, unsigned long, struct instruction *)); +int print_three_operand + PARAMS ((disassemble_info *, unsigned long, struct instruction *)); +int print_par_insn + PARAMS ((disassemble_info *, unsigned long, struct instruction *)); +int print_branch + PARAMS ((disassemble_info *, unsigned long, struct instruction *)); +int get_indirect_operand PARAMS ((unsigned short, int, char *)); +int get_register_operand PARAMS ((unsigned char, char *)); +int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *)); + +int +print_insn_tic30 (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + unsigned long insn_word; + struct instruction insn = { 0, NULL, NULL }; + bfd_vma bufaddr = pc - info->buffer_vma; + /* Obtain the current instruction word from the buffer. */ + insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | + (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); + _pc = pc / 4; + /* Get the instruction refered to by the current instruction word + and print it out based on its type. */ + if (!get_tic30_instruction (insn_word, &insn)) + return -1; + switch (GET_TYPE (insn_word)) + { + case TWO_OPERAND_1: + case TWO_OPERAND_2: + if (!print_two_operand (info, insn_word, &insn)) + return -1; + break; + case THREE_OPERAND: + if (!print_three_operand (info, insn_word, &insn)) + return -1; + break; + case PAR_STORE: + case MUL_ADDS: + if (!print_par_insn (info, insn_word, &insn)) + return -1; + break; + case BRANCHES: + if (!print_branch (info, insn_word, &insn)) + return -1; + break; + } + return 4; +} + +int +get_tic30_instruction (insn_word, insn) + unsigned long insn_word; + struct instruction *insn; +{ + switch (GET_TYPE (insn_word)) + { + case TWO_OPERAND_1: + case TWO_OPERAND_2: + case THREE_OPERAND: + insn->type = NORMAL_INSN; + { + template *current_optab = (template *) tic30_optab; + for (; current_optab < tic30_optab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if (current_optab->operands == 0) + { + if (current_optab->base_opcode == insn_word) + { + insn->tm = current_optab; + break; + } + } + else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) + { + insn->tm = current_optab; + break; + } + } + } + } + break; + case PAR_STORE: + insn->type = PARALLEL_INSN; + { + partemplate *current_optab = (partemplate *) tic30_paroptab; + for (; current_optab < tic30_paroptab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN)) + { + insn->ptm = current_optab; + break; + } + } + } + } + break; + case MUL_ADDS: + insn->type = PARALLEL_INSN; + { + partemplate *current_optab = (partemplate *) tic30_paroptab; + for (; current_optab < tic30_paroptab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN)) + { + insn->ptm = current_optab; + break; + } + } + } + } + break; + case BRANCHES: + insn->type = NORMAL_INSN; + { + template *current_optab = (template *) tic30_optab; + for (; current_optab < tic30_optab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if (current_optab->operand_types[0] & Imm24) + { + if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN)) + { + insn->tm = current_optab; + break; + } + } + else if (current_optab->operands > 0) + { + if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN)) + { + insn->tm = current_optab; + break; + } + } + else + { + if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000))) + { + insn->tm = current_optab; + break; + } + } + } + } + } + break; + default: + return 0; + } + return 1; +} + +int +print_two_operand (info, insn_word, insn) + disassemble_info *info; + unsigned long insn_word; + struct instruction *insn; +{ + char name[12]; + char operand[2][13] = + { + {0}, + {0}}; + float f_number; + + if (insn->tm == NULL) + return 0; + strcpy (name, insn->tm->name); + if (insn->tm->opcode_modifier == AddressMode) + { + int src_op, dest_op; + /* Determine whether instruction is a store or a normal instruction. */ + if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) + { + src_op = 1; + dest_op = 0; + } + else + { + src_op = 0; + dest_op = 1; + } + /* Get the destination register. */ + if (insn->tm->operands == 2) + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); + /* Get the source operand based on addressing mode. */ + switch (insn_word & AddressMode) + { + case AM_REGISTER: + /* Check for the NOP instruction before getting the operand. */ + if ((insn->tm->operand_types[0] & NotReq) == 0) + get_register_operand ((insn_word & 0x0000001F), operand[src_op]); + break; + case AM_DIRECT: + sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); + break; + case AM_INDIRECT: + get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); + break; + case AM_IMM: + /* Get the value of the immediate operand based on variable type. */ + switch (insn->tm->imm_arg_type) + { + case Imm_Float: + cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); + sprintf (operand[src_op], "%2.2f", f_number); + break; + case Imm_SInt: + sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); + break; + case Imm_UInt: + sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); + break; + default: + return 0; + } + /* Handle special case for LDP instruction. */ + if ((insn_word & 0xFFFFFF00) == LDP_INSN) + { + strcpy (name, "ldp"); + sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); + operand[1][0] = '\0'; + } + } + } + /* Handle case for stack and rotate instructions. */ + else if (insn->tm->operands == 1) + { + if (insn->tm->opcode_modifier == StackOp) + { + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); + } + } + /* Output instruction to stream. */ + info->fprintf_func (info->stream, " %s %s%c%s", name, + operand[0][0] ? operand[0] : "", + operand[1][0] ? ',' : ' ', + operand[1][0] ? operand[1] : ""); + return 1; +} + +int +print_three_operand (info, insn_word, insn) + disassemble_info *info; + unsigned long insn_word; + struct instruction *insn; +{ + char operand[3][13] = + { + {0}, + {0}, + {0}}; + + if (insn->tm == NULL) + return 0; + switch (insn_word & AddressMode) + { + case AM_REGISTER: + get_register_operand ((insn_word & 0x000000FF), operand[0]); + get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); + break; + case AM_DIRECT: + get_register_operand ((insn_word & 0x000000FF), operand[0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); + break; + case AM_INDIRECT: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); + get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); + break; + case AM_IMM: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); + break; + default: + return 0; + } + if (insn->tm->operands == 3) + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); + info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, + operand[0], operand[1], + operand[2][0] ? ',' : ' ', + operand[2][0] ? operand[2] : ""); + return 1; +} + +int +print_par_insn (info, insn_word, insn) + disassemble_info *info; + unsigned long insn_word; + struct instruction *insn; +{ + size_t i, len; + char *name1, *name2; + char operand[2][3][13] = + { + { + {0}, + {0}, + {0}}, + { + {0}, + {0}, + {0}}}; + + if (insn->ptm == NULL) + return 0; + /* Parse out the names of each of the parallel instructions from the + q_insn1_insn2 format. */ + name1 = (char *) strdup (insn->ptm->name + 2); + name2 = ""; + len = strlen (name1); + for (i = 0; i < len; i++) + { + if (name1[i] == '_') + { + name2 = &name1[i + 1]; + name1[i] = '\0'; + break; + } + } + /* Get the operands of the instruction based on the operand order. */ + switch (insn->ptm->oporder) + { + case OO_4op1: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); + break; + case OO_4op2: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); + break; + case OO_4op3: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); + break; + case OO_5op1: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); + break; + case OO_5op2: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); + break; + case OO_PField: + if (insn_word & 0x00800000) + get_register_operand (0x01, operand[0][2]); + else + get_register_operand (0x00, operand[0][2]); + if (insn_word & 0x00400000) + get_register_operand (0x03, operand[1][2]); + else + get_register_operand (0x02, operand[1][2]); + switch (insn_word & P_FIELD) + { + case 0x00000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); + get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); + break; + case 0x01000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); + break; + case 0x02000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); + break; + case 0x03000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); + break; + } + break; + default: + return 0; + } + info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, + operand[0][0], operand[0][1], + operand[0][2][0] ? ',' : ' ', + operand[0][2][0] ? operand[0][2] : ""); + info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, + operand[1][0], operand[1][1], + operand[1][2][0] ? ',' : ' ', + operand[1][2][0] ? operand[1][2] : ""); + free (name1); + return 1; +} + +int +print_branch (info, insn_word, insn) + disassemble_info *info; + unsigned long insn_word; + struct instruction *insn; +{ + char operand[2][13] = + { + {0}, + {0}}; + unsigned long address; + int print_label = 0; + + if (insn->tm == NULL) + return 0; + /* Get the operands for 24-bit immediate jumps. */ + if (insn->tm->operand_types[0] & Imm24) + { + address = insn_word & 0x00FFFFFF; + sprintf (operand[0], "0x%lX", address); + print_label = 1; + } + /* Get the operand for the trap instruction. */ + else if (insn->tm->operand_types[0] & IVector) + { + address = insn_word & 0x0000001F; + sprintf (operand[0], "0x%lX", address); + } + else + { + address = insn_word & 0x0000FFFF; + /* Get the operands for the DB instructions. */ + if (insn->tm->operands == 2) + { + get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); + if (insn_word & PCRel) + { + sprintf (operand[1], "%d", (short) address); + print_label = 1; + } + else + get_register_operand (insn_word & 0x0000001F, operand[1]); + } + /* Get the operands for the standard branches. */ + else if (insn->tm->operands == 1) + { + if (insn_word & PCRel) + { + address = (short) address; + sprintf (operand[0], "%ld", address); + print_label = 1; + } + else + get_register_operand (insn_word & 0x0000001F, operand[0]); + } + } + info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, + operand[0][0] ? operand[0] : "", + operand[1][0] ? ',' : ' ', + operand[1][0] ? operand[1] : ""); + /* Print destination of branch in relation to current symbol. */ + if (print_label && info->symbols) + { + asymbol *sym = *info->symbols; + + if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) + { + address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); + /* Check for delayed instruction, if so adjust destination. */ + if (insn_word & 0x00200000) + address += 2; + } + else + { + address -= ((sym->section->vma + sym->value) / 4); + } + if (address == 0) + info->fprintf_func (info->stream, " <%s>", sym->name); + else + info->fprintf_func (info->stream, " <%s %c %d>", sym->name, + ((short) address < 0) ? '-' : '+', + abs (address)); + } + return 1; +} + +int +get_indirect_operand (fragment, size, buffer) + unsigned short fragment; + int size; + char *buffer; +{ + unsigned char mod; + unsigned arnum; + unsigned char disp; + + if (buffer == NULL) + return 0; + /* Determine which bits identify the sections of the indirect + operand based on the size in bytes. */ + switch (size) + { + case 1: + mod = (fragment & 0x00F8) >> 3; + arnum = (fragment & 0x0007); + disp = 0; + break; + case 2: + mod = (fragment & 0xF800) >> 11; + arnum = (fragment & 0x0700) >> 8; + disp = (fragment & 0x00FF); + break; + default: + return 0; + } + { + const ind_addr_type *current_ind = tic30_indaddr_tab; + for (; current_ind < tic30_indaddrtab_end; current_ind++) + { + if (current_ind->modfield == mod) + { + if (current_ind->displacement == IMPLIED_DISP && size == 2) + { + continue; + } + else + { + size_t i, len; + int bufcnt; + + len = strlen (current_ind->syntax); + for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) + { + buffer[bufcnt] = current_ind->syntax[i]; + if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') + buffer[++bufcnt] = arnum + '0'; + if (buffer[bufcnt] == '(' + && current_ind->displacement == DISP_REQUIRED) + { + sprintf (&buffer[bufcnt + 1], "%u", disp); + bufcnt += strlen (&buffer[bufcnt + 1]); + } + } + buffer[bufcnt + 1] = '\0'; + break; + } + } + } + } + return 1; +} + +int +get_register_operand (fragment, buffer) + unsigned char fragment; + char *buffer; +{ + const reg *current_reg = tic30_regtab; + + if (buffer == NULL) + return 0; + for (; current_reg < tic30_regtab_end; current_reg++) + { + if ((fragment & 0x1F) == current_reg->opcode) + { + strcpy (buffer, current_reg->name); + return 1; + } + } + return 0; +} + +int +cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat) + unsigned long tmsfloat; + int size; + float *ieeefloat; +{ + unsigned long exp, sign, mant; + + if (size == 2) + { + if ((tmsfloat & 0x0000F000) == 0x00008000) + tmsfloat = 0x80000000; + else + { + tmsfloat <<= 16; + tmsfloat = (long) tmsfloat >> 4; + } + } + exp = tmsfloat & 0xFF000000; + if (exp == 0x80000000) + { + *ieeefloat = 0.0; + return 1; + } + exp += 0x7F000000; + sign = (tmsfloat & 0x00800000) << 8; + mant = tmsfloat & 0x007FFFFF; + if (exp == 0xFF000000) + { + if (mant == 0) + *ieeefloat = ERANGE; + if (sign == 0) + *ieeefloat = 1.0 / 0.0; + else + *ieeefloat = -1.0 / 0.0; + return 1; + } + exp >>= 1; + if (sign) + { + mant = (~mant) & 0x007FFFFF; + mant += 1; + exp += mant & 0x00800000; + exp &= 0x7F800000; + mant &= 0x007FFFFF; + } + if (tmsfloat == 0x80000000) + sign = mant = exp = 0; + tmsfloat = sign | exp | mant; + *ieeefloat = *((float *) &tmsfloat); + return 1; +} diff --git a/opcodes/tic54x-dis.c b/opcodes/tic54x-dis.c new file mode 100644 index 0000000..c531b0b --- /dev/null +++ b/opcodes/tic54x-dis.c @@ -0,0 +1,598 @@ +/* Disassembly routines for TMS320C54X architecture + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic54x.h" +#include "coff/tic54x.h" + +static int has_lkaddr (unsigned short, const template *); +static int get_insn_size (unsigned short, const template *); +static int print_instruction (disassemble_info *, bfd_vma, + unsigned short, const char *, + const enum optype [], int, int); +static int print_parallel_instruction (disassemble_info *, bfd_vma, + unsigned short, + const template *, int); +static int sprint_dual_address (disassemble_info *,char [], + unsigned short); +static int sprint_indirect_address (disassemble_info *,char [], + unsigned short); +static int sprint_direct_address (disassemble_info *,char [], + unsigned short); +static int sprint_mmr (disassemble_info *,char [],int); +static int sprint_condition (disassemble_info *,char *,unsigned short); +static int sprint_cc2 (disassemble_info *,char *,unsigned short); + +int +print_insn_tic54x (bfd_vma memaddr, disassemble_info *info) +{ + bfd_byte opbuf[2]; + unsigned short opcode; + int status, size; + const template* tm; + + status = (*info->read_memory_func) (memaddr, opbuf, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + opcode = bfd_getl16 (opbuf); + tm = tic54x_get_insn (info, memaddr, opcode, &size); + + info->bytes_per_line = 2; + info->bytes_per_chunk = 2; + info->octets_per_byte = 2; + info->display_endian = BFD_ENDIAN_LITTLE; + + if (tm->flags & FL_PAR) + { + if (!print_parallel_instruction (info, memaddr, opcode, tm, size)) + return -1; + } + else + { + if (!print_instruction (info, memaddr, opcode, + (char *) tm->name, + tm->operand_types, + size, (tm->flags & FL_EXT))) + return -1; + } + + return size * 2; +} + +static int +has_lkaddr (unsigned short memdata, const template *tm) +{ + return (IS_LKADDR (memdata) + && (OPTYPE (tm->operand_types[0]) == OP_Smem + || OPTYPE (tm->operand_types[1]) == OP_Smem + || OPTYPE (tm->operand_types[2]) == OP_Smem + || OPTYPE (tm->operand_types[1]) == OP_Sind + || OPTYPE (tm->operand_types[0]) == OP_Lmem + || OPTYPE (tm->operand_types[1]) == OP_Lmem)); +} + +/* always returns 1 (whether an insn template was found) since we provide an + "unknown instruction" template */ +const template* +tic54x_get_insn (disassemble_info *info, bfd_vma addr, + unsigned short memdata, int *size) +{ + const template *tm = NULL; + + for (tm = tic54x_optab; tm->name; tm++) + { + if (tm->opcode == (memdata & tm->mask)) + { + /* a few opcodes span two words */ + if (tm->flags & FL_EXT) + { + /* if lk addressing is used, the second half of the opcode gets + pushed one word later */ + bfd_byte opbuf[2]; + bfd_vma addr2 = addr + 1 + has_lkaddr (memdata, tm); + int status = (*info->read_memory_func) (addr2, opbuf, 2, info); + // FIXME handle errors + if (status == 0) + { + unsigned short data2 = bfd_getl16 (opbuf); + if (tm->opcode2 == (data2 & tm->mask2)) + { + if (size) *size = get_insn_size (memdata, tm); + return tm; + } + } + } + else + { + if (size) *size = get_insn_size (memdata, tm); + return tm; + } + } + } + for (tm = (template *) tic54x_paroptab; tm->name; tm++) + { + if (tm->opcode == (memdata & tm->mask)) + { + if (size) *size = get_insn_size (memdata, tm); + return tm; + } + } + + if (size) *size = 1; + return &tic54x_unknown_opcode; +} + +static int +get_insn_size (unsigned short memdata, const template *insn) +{ + int size; + + if (insn->flags & FL_PAR) + { + /* only non-parallel instructions support lk addressing */ + size = insn->words; + } + else + { + size = insn->words + has_lkaddr (memdata, insn); + } + + return size; +} + +int +print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext) + disassemble_info *info; + bfd_vma memaddr; + unsigned short opcode; + const char *tm_name; + const enum optype tm_operands[]; + int size; + int ext; +{ + static int n; + /* string storage for multiple operands */ + char operand[4][64] = { {0},{0},{0},{0}, }; + bfd_byte buf[2]; + unsigned long opcode2 = 0; + unsigned long lkaddr = 0; + enum optype src = OP_None; + enum optype dst = OP_None; + int i, shift; + char *comma = ""; + + info->fprintf_func (info->stream, "%-7s", tm_name); + + if (size > 1) + { + int status = (*info->read_memory_func) (memaddr + 1, buf, 2, info); + if (status != 0) + return 0; + lkaddr = opcode2 = bfd_getl16 (buf); + if (size > 2) + { + status = (*info->read_memory_func) (memaddr + 2, buf, 2, info); + if (status != 0) + return 0; + opcode2 = bfd_getl16 (buf); + } + } + + for (i = 0; i < MAX_OPERANDS && OPTYPE (tm_operands[i]) != OP_None; i++) + { + char *next_comma = ","; + int optional = (tm_operands[i] & OPT) != 0; + + switch (OPTYPE (tm_operands[i])) + { + case OP_Xmem: + sprint_dual_address (info, operand[i], XMEM (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_Ymem: + sprint_dual_address (info, operand[i], YMEM (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_Smem: + case OP_Sind: + case OP_Lmem: + info->fprintf_func (info->stream, "%s", comma); + if (INDIRECT (opcode)) + { + if (MOD (opcode) >= 12) + { + bfd_vma addr = lkaddr; + int arf = ARF (opcode); + int mod = MOD (opcode); + if (mod == 15) + info->fprintf_func (info->stream, "*("); + else + info->fprintf_func (info->stream, "*%sar%d(", + (mod == 13 || mod == 14 ? "+" : ""), + arf); + (*(info->print_address_func)) ((bfd_vma) addr, info); + info->fprintf_func (info->stream, ")%s", + mod == 14 ? "%" : ""); + } + else + { + sprint_indirect_address (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s", operand[i]); + } + } + else + { + /* FIXME -- use labels (print_address_func) */ + /* in order to do this, we need to guess what DP is */ + sprint_direct_address (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s", operand[i]); + } + break; + case OP_dmad: + info->fprintf_func (info->stream, "%s", comma); + (*(info->print_address_func)) ((bfd_vma) opcode2, info); + break; + case OP_xpmad: + /* upper 7 bits of address are in the opcode */ + opcode2 += ((unsigned long) opcode & 0x7F) << 16; + /* fall through */ + case OP_pmad: + info->fprintf_func (info->stream, "%s", comma); + (*(info->print_address_func)) ((bfd_vma) opcode2, info); + break; + case OP_MMRX: + sprint_mmr (info, operand[i], MMRX (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_MMRY: + sprint_mmr (info, operand[i], MMRY (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_MMR: + sprint_mmr (info, operand[i], MMR (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_PA: + sprintf (operand[i], "pa%d", (unsigned) opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SRC: + src = SRC (ext ? opcode2 : opcode) ? OP_B : OP_A; + sprintf (operand[i], (src == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SRC1: + src = SRC1 (ext ? opcode2 : opcode) ? OP_B : OP_A; + sprintf (operand[i], (src == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_RND: + dst = DST (opcode) ? OP_B : OP_A; + sprintf (operand[i], (dst == OP_B) ? "a" : "b"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_DST: + dst = DST (ext ? opcode2 : opcode) ? OP_B : OP_A; + if (!optional || dst != src) + { + sprintf (operand[i], (dst == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_B: + sprintf (operand[i], "b"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_A: + sprintf (operand[i], "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ARX: + sprintf (operand[i], "ar%d", (int) ARX (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SHIFT: + shift = SHIFT (ext ? opcode2 : opcode); + if (!optional || shift != 0) + { + sprintf (operand[i], "%d", shift); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_SHFT: + shift = SHFT (opcode); + if (!optional || shift != 0) + { + sprintf (operand[i], "%d", (unsigned) shift); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_lk: + sprintf (operand[i], "#%d", (int) (short) opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_T: + sprintf (operand[i], "t"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_TS: + sprintf (operand[i], "ts"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k8: + sprintf (operand[i], "%d", (int) ((signed char) (opcode & 0xFF))); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_16: + sprintf (operand[i], "16"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ASM: + sprintf (operand[i], "asm"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_BITC: + sprintf (operand[i], "%d", (int) (opcode & 0xF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_CC: + /* put all CC operands in the same operand */ + sprint_condition (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + i = MAX_OPERANDS; + break; + case OP_CC2: + sprint_cc2 (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_CC3: + { + const char *code[] = { "eq", "lt", "gt", "neq" }; + sprintf (operand[i], code[CC3 (opcode)]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_123: + { + int code = (opcode >> 8) & 0x3; + sprintf (operand[i], "%d", (code == 0) ? 1 : (code == 2) ? 2 : 3); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_k5: + sprintf (operand[i], "#%d", + (int) (((signed char) opcode & 0x1F) << 3) >> 3); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k8u: + sprintf (operand[i], "#%d", (unsigned) (opcode & 0xFF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k3: + sprintf (operand[i], "#%d", (int) (opcode & 0x7)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_lku: + sprintf (operand[i], "#%d", (unsigned) opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_N: + n = (opcode >> 9) & 0x1; + sprintf (operand[i], "st%d", n); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SBIT: + { + const char *status0[] = { + "0", "1", "2", "3", "4", "5", "6", "7", "8", + "ovb", "ova", "c", "tc", "13", "14", "15" + }; + const char *status1[] = { + "0", "1", "2", "3", "4", + "cmpt", "frct", "c16", "sxm", "ovm", "10", + "intm", "hm", "xf", "cpl", "braf" + }; + sprintf (operand[i], "%s", + n ? status1[SBIT (opcode)] : status0[SBIT (opcode)]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_12: + sprintf (operand[i], "%d", (int) ((opcode >> 9) & 1) + 1); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_TRN: + sprintf (operand[i], "trn"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_DP: + sprintf (operand[i], "dp"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k9: + /* FIXME-- this is DP, print the original address? */ + sprintf (operand[i], "#%d", (int) (opcode & 0x1FF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ARP: + sprintf (operand[i], "arp"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_031: + sprintf (operand[i], "%d", (int) (opcode & 0x1F)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + default: + sprintf (operand[i], "??? (0x%x)", tm_operands[i]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + comma = next_comma; + } + return 1; +} + +static int +print_parallel_instruction (info, memaddr, opcode, ptm, size) + disassemble_info *info; + bfd_vma memaddr; + unsigned short opcode; + const template *ptm; + int size; +{ + print_instruction (info, memaddr, opcode, + ptm->name, ptm->operand_types, size, 0); + info->fprintf_func (info->stream, " || "); + return print_instruction (info, memaddr, opcode, + ptm->parname, ptm->paroperand_types, size, 0); +} + +static int +sprint_dual_address (info, buf, code) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + unsigned short code; +{ + const char *formats[] = { + "*ar%d", + "*ar%d-", + "*ar%d+", + "*ar%d+0%%", + }; + return sprintf (buf, formats[XMOD (code)], XARX (code)); +} + +static int +sprint_indirect_address (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + unsigned short opcode; +{ + const char *formats[] = { + "*ar%d", + "*ar%d-", + "*ar%d+", + "*+ar%d", + "*ar%d-0B", + "*ar%d-0", + "*ar%d+0", + "*ar%d+0B", + "*ar%d-%%", + "*ar%d-0%%", + "*ar%d+%%", + "*ar%d+0%%", + }; + return sprintf (buf, formats[MOD (opcode)], ARF (opcode)); +} + +static int +sprint_direct_address (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + unsigned short opcode; +{ + /* FIXME -- look up relocation if available */ + return sprintf (buf, "DP+0x%02x", (int) (opcode & 0x7F)); +} + +static int +sprint_mmr (info, buf, mmr) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + int mmr; +{ + symbol *reg = (symbol *) mmregs; + while (reg->name != NULL) + { + if (mmr == reg->value) + { + sprintf (buf, "%s", (reg + 1)->name); + return 1; + } + ++reg; + } + sprintf (buf, "MMR(%d)", mmr); /* FIXME -- different targets. */ + return 0; +} + +static int +sprint_cc2 (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char *buf; + unsigned short opcode; +{ + const char *cc2[] = { + "??", "??", "ageq", "alt", "aneq", "aeq", "agt", "aleq", + "??", "??", "bgeq", "blt", "bneq", "beq", "bgt", "bleq", + }; + return sprintf (buf, "%s", cc2[opcode & 0xF]); +} + +static int +sprint_condition (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char *buf; + unsigned short opcode; +{ + char *start = buf; + const char *cmp[] = { + "??", "??", "geq", "lt", "neq", "eq", "gt", "leq" + }; + if (opcode & 0x40) + { + char acc = (opcode & 0x8) ? 'b' : 'a'; + if (opcode & 0x7) + buf += sprintf (buf, "%c%s%s", acc, cmp[(opcode & 0x7)], + (opcode & 0x20) ? ", " : ""); + if (opcode & 0x20) + buf += sprintf (buf, "%c%s", acc, (opcode & 0x10) ? "ov" : "nov"); + } + else if (opcode & 0x3F) + { + if (opcode & 0x30) + buf += sprintf (buf, "%s%s", + ((opcode & 0x30) == 0x30) ? "tc" : "ntc", + (opcode & 0x0F) ? ", " : ""); + if (opcode & 0x0C) + buf += sprintf (buf, "%s%s", + ((opcode & 0x0C) == 0x0C) ? "c" : "nc", + (opcode & 0x03) ? ", " : ""); + if (opcode & 0x03) + buf += sprintf (buf, "%s", + ((opcode & 0x03) == 0x03) ? "bio" : "nbio"); + } + else + buf += sprintf (buf, "unc"); + + return buf - start; +} diff --git a/opcodes/tic54x-opc.c b/opcodes/tic54x-opc.c new file mode 100644 index 0000000..a3977df --- /dev/null +++ b/opcodes/tic54x-opc.c @@ -0,0 +1,494 @@ +/* Table of opcodes for the Texas Instruments TMS320C54X + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic54x.h" + +/* these are the only register names not found in mmregs */ +const symbol regs[] = { + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { NULL, 0} +}; + +/* status bits, MM registers, condition codes, etc */ +/* some symbols are only valid for certain chips... */ +const symbol mmregs[] = { + { "IMR", 0 }, { "imr", 0 }, + { "IFR", 1 }, { "ifr", 1 }, + { "ST0", 6 }, { "st0", 6 }, + { "ST1", 7 }, { "st1", 7 }, + { "AL", 8 }, { "al", 8 }, + { "AH", 9 }, { "ah", 9 }, + { "AG", 10 }, { "ag", 10 }, + { "BL", 11 }, { "bl", 11 }, + { "BH", 12 }, { "bh", 12 }, + { "BG", 13 }, { "bg", 13 }, + { "T", 14 }, { "t", 14 }, + { "TRN", 15 }, { "trn", 15 }, + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { "SP", 24 }, { "sp", 24 }, + { "BK", 25 }, { "bk", 25 }, + { "BRC", 26 }, { "brc", 26 }, + { "RSA", 27 }, { "rsa", 27 }, + { "REA", 28 }, { "rea", 28 }, + { "PMST",29 }, { "pmst",29 }, + { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */ + /* optional peripherals */ /* optional peripherals */ + { "M1F", 31 }, { "m1f", 31 }, + { "DRR0",0x20 }, { "drr0",0x20 }, + { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */ + { "DXR0",0x21 }, { "dxr0",0x21 }, + { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */ + { "SPC0",0x22 }, { "spc0",0x22 }, + { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */ + { "SPCE0",0x23 }, { "spce0",0x23 }, + { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */ + { "TIM", 0x24 }, { "tim", 0x24 }, + { "PRD", 0x25 }, { "prd", 0x25 }, + { "TCR", 0x26 }, { "tcr", 0x26 }, + { "SWWSR",0x28 }, { "swwsr",0x28 }, + { "BSCR",0x29 }, { "bscr",0x29 }, + { "HPIC",0x2C }, { "hpic",0x2c }, + /* 'c541, 'c545 */ /* 'c541, 'c545 */ + { "DRR1",0x30 }, { "drr1",0x30 }, + { "DXR1",0x31 }, { "dxr1",0x31 }, + { "SPC1",0x32 }, { "spc1",0x32 }, + /* 'c542, 'c543 */ /* 'c542, 'c543 */ + { "TRCV",0x30 }, { "trcv",0x30 }, + { "TDXR",0x31 }, { "tdxr",0x31 }, + { "TSPC",0x32 }, { "tspc",0x32 }, + { "TCSR",0x33 }, { "tcsr",0x33 }, + { "TRTA",0x34 }, { "trta",0x34 }, + { "TRAD",0x35 }, { "trad",0x35 }, + { "AXR0",0x38 }, { "axr0",0x38 }, + { "BKX0",0x39 }, { "bkx0",0x39 }, + { "ARR0",0x3A }, { "arr0",0x3a }, + { "BKR0",0x3B }, { "bkr0",0x3b }, + /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */ + { "CLKMD",0x58 }, { "clkmd",0x58 }, + /* 'c548 */ /* 'c548 */ + { "AXR1",0x3C }, { "axr1",0x3c }, + { "BKX1",0x3D }, { "bkx1",0x3d }, + { "ARR1",0x3E }, { "arr1",0x3e }, + { "BKR1",0x3F }, { "bkr1",0x3f }, + { "BDRR1",0x40 }, { "bdrr1",0x40 }, + { "BDXR1",0x41 }, { "bdxr1",0x41 }, + { "BSPC1",0x42 }, { "bspc1",0x42 }, + { "BSPCE1",0x43 }, { "bspce1",0x43 }, + { NULL, 0}, +}; + +const symbol condition_codes[] = { + /* condition codes */ + { "UNC", 0 }, { "unc", 0 }, +#define CC1 0x40 +#define CCB 0x08 +#define CCEQ 0x05 +#define CCNEQ 0x04 +#define CCLT 0x03 +#define CCLEQ 0x07 +#define CCGT 0x06 +#define CCGEQ 0x02 +#define CCOV 0x70 +#define CCNOV 0x60 +#define CCBIO 0x03 +#define CCNBIO 0x02 +#define CCTC 0x30 +#define CCNTC 0x20 +#define CCC 0x0C +#define CCNC 0x08 + { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ }, + { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ }, + { "alt", CC1|CCLT }, { "ALT", CC1|CCLT }, + { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ }, + { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }, + { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ }, + { "aov", CC1|CCOV }, { "AOV", CC1|CCOV }, + { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV }, + { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ }, + { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ }, + { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT }, + { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ }, + { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT }, + { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ }, + { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV }, + { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV }, + { "tc", CCTC }, { "TC", CCTC }, + { "ntc", CCNTC }, { "NTC", CCNTC }, + { "c", CCC }, { "C", CCC }, + { "nc", CCNC }, { "NC", CCNC }, + { "bio", CCBIO }, { "BIO", CCBIO }, + { "nbio", CCNBIO }, { "NBIO", CCNBIO }, + { NULL, 0 } +}; + +const symbol cc2_codes[] = { + { "UNC", 0 }, { "unc", 0 }, + { "AEQ", 5 }, { "aeq", 5 }, + { "ANEQ", 4 }, { "aneq", 4 }, + { "AGT", 6 }, { "agt", 6 }, + { "ALT", 3 }, { "alt", 3 }, + { "ALEQ", 7 }, { "aleq", 7 }, + { "AGEQ", 2 }, { "ageq", 2 }, + { "BEQ", 13 }, { "beq", 13 }, + { "BNEQ", 12 },{ "bneq", 12 }, + { "BGT", 14 }, { "bgt", 14 }, + { "BLT", 11 }, { "blt", 11 }, + { "BLEQ", 15 },{ "bleq", 15 }, + { "BGEQ", 10 },{ "bgeq", 10 }, + { NULL, 0 }, +}; + +const symbol cc3_codes[] = { + { "EQ", 0x0000 }, { "eq", 0x0000 }, + { "LT", 0x0100 }, { "lt", 0x0100 }, + { "GT", 0x0200 }, { "gt", 0x0200 }, + { "NEQ", 0x0300 }, { "neq", 0x0300 }, + { "0", 0x0000 }, + { "1", 0x0100 }, + { "2", 0x0200 }, + { "3", 0x0300 }, + { "00", 0x0000 }, + { "01", 0x0100 }, + { "10", 0x0200 }, + { "11", 0x0300 }, + { NULL, 0 }, +}; + +/* FIXME -- also allow decimal digits */ +const symbol status_bits[] = { + /* status register 0 */ + { "TC", 12 }, { "tc", 12 }, + { "C", 11 }, { "c", 11 }, + { "OVA", 10 }, { "ova", 10 }, + { "OVB", 9 }, { "ovb", 9 }, + /* status register 1 */ + { "BRAF",15 }, { "braf",15 }, + { "CPL", 14 }, { "cpl", 14 }, + { "XF", 13 }, { "xf", 13 }, + { "HM", 12 }, { "hm", 12 }, + { "INTM",11 }, { "intm",11 }, + { "OVM", 9 }, { "ovm", 9 }, + { "SXM", 8 }, { "sxm", 8 }, + { "C16", 7 }, { "c16", 7 }, + { "FRCT", 6 }, { "frct", 6 }, + { "CMPT", 5 }, { "cmpt", 5 }, + { NULL, 0 }, +}; + +const char *misc_symbols[] = { + "ARP", "arp", + "DP", "dp", + "ASM", "asm", + "TS", "ts", + NULL +}; + +/* Due to the way instructions are hashed and scanned in + gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively + placed + + Items marked with "PREFER" have been moved prior to a more costly + instruction with a similar operand format. + + Mnemonics which can take either a predefined symbol or a memory reference + as an argument are arranged so that the more restrictive (predefined + symbol) version is checked first (marked "SRC"). +*/ +#define ZPAR 0,{OP_None} +#define REST 0,0,ZPAR +#define XREST ZPAR +const template tic54x_unknown_opcode = + { "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST}; +const template tic54x_optab[] = { + /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */ + { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST}, + { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST}, + { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST}, + { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST}, + + { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/ + { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST}, + { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST}, + { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/ + { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST}, + { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST}, + { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST}, + { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST}, + { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST }, + { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST}, + { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST}, + { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST}, + { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST}, + { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST}, + { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST}, + { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST}, + { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, REST}, + { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_DELAY|FL_NR, REST}, + { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST}, + { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST}, + { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST}, + { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST}, + { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST}, + { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST}, + { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, REST}, + { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_DELAY|FL_NR, REST}, + { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST}, + { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST}, + { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST}, + { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST}, + { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST}, + { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST}, + { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */ + { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST}, + { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST}, + { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST}, + { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST}, + { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST}, + { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST}, + { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST}, + { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST}, + { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST}, + { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST}, + { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST}, + { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST}, + { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST}, + { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/ + /* alternate syntax */ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/ + { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/ + { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/ + { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */ + { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/ + { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/ + { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/ + { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST}, + { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST}, + { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/ + { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST}, + FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST}, + { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST}, + { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST}, + { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST}, + { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/ + { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST}, + { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST}, + { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST}, + { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/ + { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST}, + { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/ + { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST}, + { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST}, + { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST}, + { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST}, + { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST}, + { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/ + { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST}, + { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST}, + { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST}, + { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST}, + { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST}, + { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST}, + { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST}, + { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/ + { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST}, + { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST}, + { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST}, + { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST}, + { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST}, + { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST}, + { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST}, + { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST}, + { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST}, + { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST}, + { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST}, + { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST}, + { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST}, + { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST}, + { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST}, + { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST}, + { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_NR, REST}, + { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_DELAY|FL_NR, REST}, + { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST}, + { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST}, + { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST}, + { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST}, + { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST}, + { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST}, + { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST}, + { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST}, + { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST}, + { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST}, + { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST}, + { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST}, + { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST}, + { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST}, + { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST}, + { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST}, + { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST}, + { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST}, + { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST}, + { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST}, + { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST}, + { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST}, + { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/ + { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST}, + { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST}, + { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST}, + { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST}, + { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST}, + { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST}, + { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST}, + { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST}, + { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + FL_EXT, 0x0C60, 0xFEE0, XREST}, + { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST}, + { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST}, + { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST}, + { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + FL_EXT, 0x0C80, 0xFEE0, XREST }, + { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST}, + { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST}, + { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST}, + { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/ + { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST}, + { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST}, + { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/ + { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST}, + { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST}, + { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST}, + { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST}, + { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST}, + { NULL, 0,0,0,0,0, {}, 0, REST}, +}; + +/* assume all parallel instructions have at least three operands */ +const template tic54x_paroptab[] = { + { "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "mac", {OP_Ymem,OPT|OP_RND},}, + { "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "macr", {OP_Ymem,OPT|OP_RND},}, + { "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "mas", {OP_Ymem,OPT|OP_RND},}, + { "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "masr", {OP_Ymem,OPT|OP_RND},}, + { "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "add", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "ld", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "ld", {OP_Xmem,OP_T}, }, + { "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "mac", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "macr", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "mas", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "masr", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "mpy", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "sub", {OP_Xmem,OP_DST}, }, + { NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST }, +}; diff --git a/opcodes/tic80-dis.c b/opcodes/tic80-dis.c new file mode 100644 index 0000000..d706bda --- /dev/null +++ b/opcodes/tic80-dis.c @@ -0,0 +1,387 @@ +/* Print TI TMS320C80 (MVP) instructions + Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/tic80.h" +#include "dis-asm.h" + +static int length; + +static void print_operand_bitnum PARAMS ((struct disassemble_info *, long)); +static void print_operand_condition_code PARAMS ((struct disassemble_info *, long)); +static void print_operand_control_register PARAMS ((struct disassemble_info *, long)); +static void print_operand_float PARAMS ((struct disassemble_info *, long)); +static void print_operand_integer PARAMS ((struct disassemble_info *, long)); +static void print_operand PARAMS ((struct disassemble_info *, long, unsigned long, + const struct tic80_operand *, bfd_vma)); +static int print_one_instruction PARAMS ((struct disassemble_info *, bfd_vma, + unsigned long, const struct tic80_opcode *)); +static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsigned long, + const struct tic80_opcode *)); +static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma, + unsigned long *)); + +/* Print an integer operand. Try to be somewhat smart about the + format by assuming that small positive or negative integers are + probably loop increment values, structure offsets, or similar + values that are more meaningful printed as signed decimal values. + Larger numbers are probably better printed as hex values. */ + +static void +print_operand_integer (info, value) + struct disassemble_info *info; + long value; +{ + if ((value > 9999 || value < -9999)) + { + (*info->fprintf_func) (info->stream, "%#lx", value); + } + else + { + (*info->fprintf_func) (info->stream, "%ld", value); + } +} + +/* FIXME: depends upon sizeof (long) == sizeof (float) and + also upon host floating point format matching target + floating point format. */ + +static void +print_operand_float (info, value) + struct disassemble_info *info; + long value; +{ + union { float f; long l; } fval; + + fval.l = value; + (*info->fprintf_func) (info->stream, "%g", fval.f); +} + +static void +print_operand_control_register (info, value) + struct disassemble_info *info; + long value; +{ + const char *tmp; + + tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR); + if (tmp != NULL) + { + (*info->fprintf_func) (info->stream, "%s", tmp); + } + else + { + (*info->fprintf_func) (info->stream, "%#lx", value); + } +} + +static void +print_operand_condition_code (info, value) + struct disassemble_info *info; + long value; +{ + const char *tmp; + + tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC); + if (tmp != NULL) + { + (*info->fprintf_func) (info->stream, "%s", tmp); + } + else + { + (*info->fprintf_func) (info->stream, "%ld", value); + } +} + +static void +print_operand_bitnum (info, value) + struct disassemble_info *info; + long value; +{ + int bitnum; + const char *tmp; + + bitnum = ~value & 0x1F; + tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM); + if (tmp != NULL) + { + (*info->fprintf_func) (info->stream, "%s", tmp); + } + else + { + (*info->fprintf_func) (info->stream, "%ld", bitnum); + } +} + +/* Print the operand as directed by the flags. */ + +#define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) +#define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) +#define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) + +static void +print_operand (info, value, insn, operand, memaddr) + struct disassemble_info *info; + long value; + unsigned long insn; + const struct tic80_operand *operand; + bfd_vma memaddr; +{ + if ((operand->flags & TIC80_OPERAND_GPR) != 0) + { + (*info->fprintf_func) (info->stream, "r%ld", value); + if (M_SI (insn, operand) || M_LI (insn, operand)) + { + (*info->fprintf_func) (info->stream, ":m"); + } + } + else if ((operand->flags & TIC80_OPERAND_FPA) != 0) + { + (*info->fprintf_func) (info->stream, "a%ld", value); + } + else if ((operand->flags & TIC80_OPERAND_PCREL) != 0) + { + (*info->print_address_func) (memaddr + 4 * value, info); + } + else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0) + { + (*info->print_address_func) (value, info); + } + else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0) + { + print_operand_bitnum (info, value); + } + else if ((operand->flags & TIC80_OPERAND_CC) != 0) + { + print_operand_condition_code (info, value); + } + else if ((operand->flags & TIC80_OPERAND_CR) != 0) + { + print_operand_control_register (info, value); + } + else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0) + { + print_operand_float (info, value); + } + else if ((operand->flags & TIC80_OPERAND_BITFIELD)) + { + (*info->fprintf_func) (info->stream, "%#lx", value); + } + else + { + print_operand_integer (info, value); + } + + /* If this is a scaled operand, then print the modifier. */ + + if (R_SCALED (insn, operand)) + { + (*info->fprintf_func) (info->stream, ":s"); + } +} + +/* We have chosen an opcode table entry. */ + +static int +print_one_instruction (info, memaddr, insn, opcode) + struct disassemble_info *info; + bfd_vma memaddr; + unsigned long insn; + const struct tic80_opcode *opcode; +{ + const struct tic80_operand *operand; + long value; + int status; + const unsigned char *opindex; + int close_paren; + + (*info->fprintf_func) (info->stream, "%-10s", opcode->name); + + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = tic80_operands + *opindex; + + /* Extract the value from the instruction. */ + if (operand->extract) + { + value = (*operand->extract) (insn, (int *) NULL); + } + else if (operand->bits == 32) + { + status = fill_instruction (info, memaddr, (unsigned long *) &value); + if (status == -1) + { + return (status); + } + } + else + { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & TIC80_OPERAND_SIGNED) != 0 + && (value & (1 << (operand->bits - 1))) != 0) + { + value -= 1 << operand->bits; + } + } + + /* If this operand is enclosed in parenthesis, then print + the open paren, otherwise just print the regular comma + separator, except for the first operand. */ + + if ((operand->flags & TIC80_OPERAND_PARENS) == 0) + { + close_paren = 0; + if (opindex != opcode->operands) + { + (*info->fprintf_func) (info->stream, ","); + } + } + else + { + close_paren = 1; + (*info->fprintf_func) (info->stream, "("); + } + + print_operand (info, value, insn, operand, memaddr); + + /* If we printed an open paren before printing this operand, close + it now. The flag gets reset on each loop. */ + + if (close_paren) + { + (*info->fprintf_func) (info->stream, ")"); + } + } + return (length); +} + +/* There are no specific bits that tell us for certain whether a vector + instruction opcode contains one or two instructions. However since + a destination register of r0 is illegal, we can check for nonzero + values in both destination register fields. Only opcodes that have + two valid instructions will have non-zero in both. */ + +#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) + +static int +print_instruction (info, memaddr, insn, vec_opcode) + struct disassemble_info *info; + bfd_vma memaddr; + unsigned long insn; + const struct tic80_opcode *vec_opcode; +{ + const struct tic80_opcode *opcode; + const struct tic80_opcode *opcode_end; + + /* Find the first opcode match in the opcodes table. For vector + opcodes (vec_opcode != NULL) find the first match that is not the + previously found match. FIXME: there should be faster ways to + search (hash table or binary search), but don't worry too much + about it until other TIc80 support is finished. */ + + opcode_end = tic80_opcodes + tic80_num_opcodes; + for (opcode = tic80_opcodes; opcode < opcode_end; opcode++) + { + if ((insn & opcode->mask) == opcode->opcode && + opcode != vec_opcode) + { + break; + } + } + + if (opcode == opcode_end) + { + /* No match found, just print the bits as a .word directive. */ + (*info->fprintf_func) (info->stream, ".word %#08lx", insn); + } + else + { + /* Match found, decode the instruction. */ + length = print_one_instruction (info, memaddr, insn, opcode); + if (opcode->flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) + { + /* There is another instruction to print from the same opcode. + Print the separator and then find and print the other + instruction. */ + (*info->fprintf_func) (info->stream, " || "); + length = print_instruction (info, memaddr, insn, opcode); + } + } + return (length); +} + +/* Get the next 32 bit word from the instruction stream and convert it + into internal format in the unsigned long INSN, for which we are + passed the address. Return 0 on success, -1 on error. */ + +static int +fill_instruction (info, memaddr, insnp) + struct disassemble_info *info; + bfd_vma memaddr; + unsigned long *insnp; +{ + bfd_byte buffer[4]; + int status; + + /* Get the bits for the next 32 bit word and put in buffer. */ + + status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return (-1); + } + + /* Read was successful, so increment count of bytes read and convert + the bits into internal format. */ + + length += 4; + if (info->endian == BFD_ENDIAN_LITTLE) + { + *insnp = bfd_getl32 (buffer); + } + else if (info->endian == BFD_ENDIAN_BIG) + { + *insnp = bfd_getb32 (buffer); + } + else + { + /* FIXME: Should probably just default to one or the other. */ + abort (); + } + return (0); +} + +int +print_insn_tic80 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + unsigned long insn; + int status; + + length = 0; + info->bytes_per_line = 8; + status = fill_instruction (info, memaddr, &insn); + if (status != -1) + { + status = print_instruction (info, memaddr, insn, NULL); + } + return (status); +} diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c new file mode 100644 index 0000000..a927759 --- /dev/null +++ b/opcodes/tic80-opc.c @@ -0,0 +1,1216 @@ +/* Opcode table for TI TMS320C80 (MVP). + Copyright 1996, 1997, 2000 Free Software Foundation, Inc. + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include +#include "sysdep.h" +#include "opcode/tic80.h" + +/* This file holds various tables for the TMS320C80 (MVP). + + The opcode table is strictly constant data, so the compiler should + be able to put it in the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. + + The predefined register table maps from register names to register + values. */ + + +/* Table of predefined symbol names, such as general purpose registers, + floating point registers, condition codes, control registers, and bit + numbers. + + The table is sorted case independently by name so that it is suitable for + searching via a binary search using a case independent comparison + function. + + Note that the type of the symbol is stored in the upper bits of the value + field, which allows the value and type to be passed around as a unit in a + single int. The types have to be masked off before using the numeric + value as a number. +*/ + +const struct predefined_symbol tic80_predefined_symbols[] = +{ + { "a0", TIC80_OPERAND_FPA | 0 }, + { "a1", TIC80_OPERAND_FPA | 1 }, + { "alw.b", TIC80_OPERAND_CC | 7 }, + { "alw.h", TIC80_OPERAND_CC | 15 }, + { "alw.w", TIC80_OPERAND_CC | 23 }, + { "ANASTAT", TIC80_OPERAND_CR | 0x34 }, + { "BRK1", TIC80_OPERAND_CR | 0x39 }, + { "BRK2", TIC80_OPERAND_CR | 0x3A }, + { "CONFIG", TIC80_OPERAND_CR | 2 }, + { "DLRU", TIC80_OPERAND_CR | 0x500 }, + { "DTAG0", TIC80_OPERAND_CR | 0x400 }, + { "DTAG1", TIC80_OPERAND_CR | 0x401 }, + { "DTAG10", TIC80_OPERAND_CR | 0x40A }, + { "DTAG11", TIC80_OPERAND_CR | 0x40B }, + { "DTAG12", TIC80_OPERAND_CR | 0x40C }, + { "DTAG13", TIC80_OPERAND_CR | 0x40D }, + { "DTAG14", TIC80_OPERAND_CR | 0x40E }, + { "DTAG15", TIC80_OPERAND_CR | 0x40F }, + { "DTAG2", TIC80_OPERAND_CR | 0x402 }, + { "DTAG3", TIC80_OPERAND_CR | 0x403 }, + { "DTAG4", TIC80_OPERAND_CR | 0x404 }, + { "DTAG5", TIC80_OPERAND_CR | 0x405 }, + { "DTAG6", TIC80_OPERAND_CR | 0x406 }, + { "DTAG7", TIC80_OPERAND_CR | 0x407 }, + { "DTAG8", TIC80_OPERAND_CR | 0x408 }, + { "DTAG9", TIC80_OPERAND_CR | 0x409 }, + { "ECOMCNTL", TIC80_OPERAND_CR | 0x33 }, + { "EIP", TIC80_OPERAND_CR | 1 }, + { "EPC", TIC80_OPERAND_CR | 0 }, + { "eq.b", TIC80_OPERAND_BITNUM | 0 }, + { "eq.f", TIC80_OPERAND_BITNUM | 20 }, + { "eq.h", TIC80_OPERAND_BITNUM | 10 }, + { "eq.w", TIC80_OPERAND_BITNUM | 20 }, + { "eq0.b", TIC80_OPERAND_CC | 2 }, + { "eq0.h", TIC80_OPERAND_CC | 10 }, + { "eq0.w", TIC80_OPERAND_CC | 18 }, + { "FLTADR", TIC80_OPERAND_CR | 0x11 }, + { "FLTDTH", TIC80_OPERAND_CR | 0x14 }, + { "FLTDTL", TIC80_OPERAND_CR | 0x13 }, + { "FLTOP", TIC80_OPERAND_CR | 0x10 }, + { "FLTTAG", TIC80_OPERAND_CR | 0x12 }, + { "FPST", TIC80_OPERAND_CR | 8 }, + { "ge.b", TIC80_OPERAND_BITNUM | 5 }, + { "ge.f", TIC80_OPERAND_BITNUM | 25 }, + { "ge.h", TIC80_OPERAND_BITNUM | 15 }, + { "ge.w", TIC80_OPERAND_BITNUM | 25 }, + { "ge0.b", TIC80_OPERAND_CC | 3 }, + { "ge0.h", TIC80_OPERAND_CC | 11 }, + { "ge0.w", TIC80_OPERAND_CC | 19 }, + { "gt.b", TIC80_OPERAND_BITNUM | 2 }, + { "gt.f", TIC80_OPERAND_BITNUM | 22 }, + { "gt.h", TIC80_OPERAND_BITNUM | 12 }, + { "gt.w", TIC80_OPERAND_BITNUM | 22 }, + { "gt0.b", TIC80_OPERAND_CC | 1 }, + { "gt0.h", TIC80_OPERAND_CC | 9 }, + { "gt0.w", TIC80_OPERAND_CC | 17 }, + { "hi.b", TIC80_OPERAND_BITNUM | 6 }, + { "hi.h", TIC80_OPERAND_BITNUM | 16 }, + { "hi.w", TIC80_OPERAND_BITNUM | 26 }, + { "hs.b", TIC80_OPERAND_BITNUM | 9 }, + { "hs.h", TIC80_OPERAND_BITNUM | 19 }, + { "hs.w", TIC80_OPERAND_BITNUM | 29 }, + { "ib.f", TIC80_OPERAND_BITNUM | 28 }, + { "IE", TIC80_OPERAND_CR | 6 }, + { "ILRU", TIC80_OPERAND_CR | 0x300 }, + { "in.f", TIC80_OPERAND_BITNUM | 27 }, + { "IN0P", TIC80_OPERAND_CR | 0x4000 }, + { "IN1P", TIC80_OPERAND_CR | 0x4001 }, + { "INTPEN", TIC80_OPERAND_CR | 4 }, + { "ITAG0", TIC80_OPERAND_CR | 0x200 }, + { "ITAG1", TIC80_OPERAND_CR | 0x201 }, + { "ITAG10", TIC80_OPERAND_CR | 0x20A }, + { "ITAG11", TIC80_OPERAND_CR | 0x20B }, + { "ITAG12", TIC80_OPERAND_CR | 0x20C }, + { "ITAG13", TIC80_OPERAND_CR | 0x20D }, + { "ITAG14", TIC80_OPERAND_CR | 0x20E }, + { "ITAG15", TIC80_OPERAND_CR | 0x20F }, + { "ITAG2", TIC80_OPERAND_CR | 0x202 }, + { "ITAG3", TIC80_OPERAND_CR | 0x203 }, + { "ITAG4", TIC80_OPERAND_CR | 0x204 }, + { "ITAG5", TIC80_OPERAND_CR | 0x205 }, + { "ITAG6", TIC80_OPERAND_CR | 0x206 }, + { "ITAG7", TIC80_OPERAND_CR | 0x207 }, + { "ITAG8", TIC80_OPERAND_CR | 0x208 }, + { "ITAG9", TIC80_OPERAND_CR | 0x209 }, + { "le.b", TIC80_OPERAND_BITNUM | 3 }, + { "le.f", TIC80_OPERAND_BITNUM | 23 }, + { "le.h", TIC80_OPERAND_BITNUM | 13 }, + { "le.w", TIC80_OPERAND_BITNUM | 23 }, + { "le0.b", TIC80_OPERAND_CC | 6 }, + { "le0.h", TIC80_OPERAND_CC | 14 }, + { "le0.w", TIC80_OPERAND_CC | 22 }, + { "lo.b", TIC80_OPERAND_BITNUM | 8 }, + { "lo.h", TIC80_OPERAND_BITNUM | 18 }, + { "lo.w", TIC80_OPERAND_BITNUM | 28 }, + { "ls.b", TIC80_OPERAND_BITNUM | 7 }, + { "ls.h", TIC80_OPERAND_BITNUM | 17 }, + { "ls.w", TIC80_OPERAND_BITNUM | 27 }, + { "lt.b", TIC80_OPERAND_BITNUM | 4 }, + { "lt.f", TIC80_OPERAND_BITNUM | 24 }, + { "lt.h", TIC80_OPERAND_BITNUM | 14 }, + { "lt.w", TIC80_OPERAND_BITNUM | 24 }, + { "lt0.b", TIC80_OPERAND_CC | 4 }, + { "lt0.h", TIC80_OPERAND_CC | 12 }, + { "lt0.w", TIC80_OPERAND_CC | 20 }, + { "MIP", TIC80_OPERAND_CR | 0x31 }, + { "MPC", TIC80_OPERAND_CR | 0x30 }, + { "ne.b", TIC80_OPERAND_BITNUM | 1 }, + { "ne.f", TIC80_OPERAND_BITNUM | 21 }, + { "ne.h", TIC80_OPERAND_BITNUM | 11 }, + { "ne.w", TIC80_OPERAND_BITNUM | 21 }, + { "ne0.b", TIC80_OPERAND_CC | 5 }, + { "ne0.h", TIC80_OPERAND_CC | 13 }, + { "ne0.w", TIC80_OPERAND_CC | 21 }, + { "nev.b", TIC80_OPERAND_CC | 0 }, + { "nev.h", TIC80_OPERAND_CC | 8 }, + { "nev.w", TIC80_OPERAND_CC | 16 }, + { "ob.f", TIC80_OPERAND_BITNUM | 29 }, + { "or.f", TIC80_OPERAND_BITNUM | 31 }, + { "ou.f", TIC80_OPERAND_BITNUM | 26 }, + { "OUTP", TIC80_OPERAND_CR | 0x4002 }, + { "PKTREQ", TIC80_OPERAND_CR | 0xD }, + { "PPERROR", TIC80_OPERAND_CR | 0xA }, + { "r0", TIC80_OPERAND_GPR | 0 }, + { "r1", TIC80_OPERAND_GPR | 1 }, + { "r10", TIC80_OPERAND_GPR | 10 }, + { "r11", TIC80_OPERAND_GPR | 11 }, + { "r12", TIC80_OPERAND_GPR | 12 }, + { "r13", TIC80_OPERAND_GPR | 13 }, + { "r14", TIC80_OPERAND_GPR | 14 }, + { "r15", TIC80_OPERAND_GPR | 15 }, + { "r16", TIC80_OPERAND_GPR | 16 }, + { "r17", TIC80_OPERAND_GPR | 17 }, + { "r18", TIC80_OPERAND_GPR | 18 }, + { "r19", TIC80_OPERAND_GPR | 19 }, + { "r2", TIC80_OPERAND_GPR | 2 }, + { "r20", TIC80_OPERAND_GPR | 20 }, + { "r21", TIC80_OPERAND_GPR | 21 }, + { "r22", TIC80_OPERAND_GPR | 22 }, + { "r23", TIC80_OPERAND_GPR | 23 }, + { "r24", TIC80_OPERAND_GPR | 24 }, + { "r25", TIC80_OPERAND_GPR | 25 }, + { "r26", TIC80_OPERAND_GPR | 26 }, + { "r27", TIC80_OPERAND_GPR | 27 }, + { "r28", TIC80_OPERAND_GPR | 28 }, + { "r29", TIC80_OPERAND_GPR | 29 }, + { "r3", TIC80_OPERAND_GPR | 3 }, + { "r30", TIC80_OPERAND_GPR | 30 }, + { "r31", TIC80_OPERAND_GPR | 31 }, + { "r4", TIC80_OPERAND_GPR | 4 }, + { "r5", TIC80_OPERAND_GPR | 5 }, + { "r6", TIC80_OPERAND_GPR | 6 }, + { "r7", TIC80_OPERAND_GPR | 7 }, + { "r8", TIC80_OPERAND_GPR | 8 }, + { "r9", TIC80_OPERAND_GPR | 9 }, + { "SYSSTK", TIC80_OPERAND_CR | 0x20 }, + { "SYSTMP", TIC80_OPERAND_CR | 0x21 }, + { "TCOUNT", TIC80_OPERAND_CR | 0xE }, + { "TSCALE", TIC80_OPERAND_CR | 0xF }, + { "uo.f", TIC80_OPERAND_BITNUM | 30 }, +}; + +const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol); + +/* This function takes a predefined symbol name in NAME, symbol class + in CLASS, and translates it to a numeric value, which it returns. + + If CLASS is zero, any symbol that matches NAME is translated. If + CLASS is non-zero, then only a symbol that has class CLASS is + matched. + + If no translation is possible, it returns -1, a value not used by + any predefined symbol. Note that the predefined symbol array is + presorted case independently by name. + + This function is implemented with the assumption that there are no + duplicate names in the predefined symbol array, which happens to be + true at the moment. + + */ + +int +tic80_symbol_to_value (name, class) + char *name; + int class; +{ + const struct predefined_symbol *pdsp; + int low = 0; + int middle; + int high = tic80_num_predefined_symbols - 1; + int cmp; + int rtnval = -1; + + while (low <= high) + { + middle = (low + high) / 2; + cmp = strcasecmp (name, tic80_predefined_symbols[middle].name); + if (cmp < 0) + { + high = middle - 1; + } + else if (cmp > 0) + { + low = middle + 1; + } + else + { + pdsp = &tic80_predefined_symbols[middle]; + if ((class == 0) || (class & PDS_VALUE (pdsp))) + { + rtnval = PDS_VALUE (pdsp); + } + /* For now we assume that there are no duplicate names */ + break; + } + } + return (rtnval); +} + +/* This function takes a value VAL and finds a matching predefined + symbol that is in the operand class specified by CLASS. If CLASS + is zero, the first matching symbol is returned. */ + +const char * +tic80_value_to_symbol (val, class) + int val; + int class; +{ + const struct predefined_symbol *pdsp; + int ival; + char *name; + + name = NULL; + for (pdsp = tic80_predefined_symbols; + pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols; + pdsp++) + { + ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; + if (ival == val) + { + if ((class == 0) || (class & PDS_VALUE (pdsp))) + { + /* Found the desired match */ + name = PDS_NAME (pdsp); + break; + } + } + } + return (name); +} + +/* This function returns a pointer to the next symbol in the predefined + symbol table after PDSP, or NULL if PDSP points to the last symbol. If + PDSP is NULL, it returns the first symbol in the table. Thus it can be + used to walk through the table by first calling it with NULL and then + calling it with each value it returned on the previous call, until it + returns NULL. */ + +const struct predefined_symbol * +tic80_next_predefined_symbol (pdsp) + const struct predefined_symbol *pdsp; +{ + if (pdsp == NULL) + { + pdsp = tic80_predefined_symbols; + } + else if (pdsp >= tic80_predefined_symbols && + pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1) + { + pdsp++; + } + else + { + pdsp = NULL; + } + return (pdsp); +} + + + +/* The operands table. The fields are: + + bits, shift, insertion function, extraction function, flags + */ + +const struct tic80_operand tic80_operands[] = +{ + + /* The zero index is used to indicate the end of the list of operands. */ + +#define UNUSED (0) + { 0, 0, 0, 0, 0 }, + + /* Short signed immediate value in bits 14-0. */ + +#define SSI (UNUSED + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, + + /* Short unsigned immediate value in bits 14-0 */ + +#define SUI (SSI + 1) + { 15, 0, NULL, NULL, 0 }, + + /* Short unsigned bitfield in bits 14-0. We distinguish this + from a regular unsigned immediate value only for the convenience + of the disassembler and the user. */ + +#define SUBF (SUI + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, + + /* Long signed immediate in following 32 bit word */ + +#define LSI (SUBF + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, + + /* Long unsigned immediate in following 32 bit word */ + +#define LUI (LSI + 1) + { 32, 0, NULL, NULL, 0 }, + + /* Long unsigned bitfield in following 32 bit word. We distinguish + this from a regular unsigned immediate value only for the + convenience of the disassembler and the user. */ + +#define LUBF (LUI + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, + + /* Single precision floating point immediate in following 32 bit + word. */ + +#define SPFI (LUBF + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT }, + + /* Register in bits 4-0 */ + +#define REG_0 (SPFI + 1) + { 5, 0, NULL, NULL, TIC80_OPERAND_GPR }, + + /* Even register in bits 4-0 */ + +#define REG_0_E (REG_0 + 1) + { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, + + /* Register in bits 26-22 */ + +#define REG_22 (REG_0_E + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR }, + + /* Even register in bits 26-22 */ + +#define REG_22_E (REG_22 + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, + + /* Register in bits 31-27 */ + +#define REG_DEST (REG_22_E + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_GPR }, + + /* Even register in bits 31-27 */ + +#define REG_DEST_E (REG_DEST + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, + + /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB) + and bit 11 (LSB) */ + /* FIXME! Needs to use functions to insert and extract the register + number in bits 16 and 11. */ + +#define REG_FPA (REG_DEST_E + 1) + { 0, 0, NULL, NULL, TIC80_OPERAND_FPA }, + + /* Short signed PC word offset in bits 14-0 */ + +#define OFF_SS_PC (REG_FPA + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, + + /* Long signed PC word offset in following 32 bit word */ + +#define OFF_SL_PC (OFF_SS_PC + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, + + /* Short signed base relative byte offset in bits 14-0 */ + +#define OFF_SS_BR (OFF_SL_PC + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, + + /* Long signed base relative byte offset in following 32 bit word */ + +#define OFF_SL_BR (OFF_SS_BR + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, + + /* Long signed base relative byte offset in following 32 bit word + with optional ":s" modifier flag in bit 11 */ + +#define OFF_SL_BR_SCALED (OFF_SL_BR + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, + + /* BITNUM in bits 31-27 */ + +#define BITNUM (OFF_SL_BR_SCALED + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM }, + + /* Condition code in bits 31-27 */ + +#define CC (BITNUM + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_CC }, + + /* Control register number in bits 14-0 */ + +#define CR_SI (CC + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_CR }, + + /* Control register number in next 32 bit word */ + +#define CR_LI (CR_SI + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_CR }, + + /* A base register in bits 26-22, enclosed in parens */ + +#define REG_BASE (CR_LI + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS }, + + /* A base register in bits 26-22, enclosed in parens, with optional ":m" + flag in bit 17 (short immediate instructions only) */ + +#define REG_BASE_M_SI (REG_BASE + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI }, + + /* A base register in bits 26-22, enclosed in parens, with optional ":m" + flag in bit 15 (long immediate and register instructions only) */ + +#define REG_BASE_M_LI (REG_BASE_M_SI + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI }, + + /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */ + +#define REG_SCALED (REG_BASE_M_LI + 1) + { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED }, + + /* Unsigned immediate in bits 4-0, used only for shift instructions */ + +#define ROTATE (REG_SCALED + 1) + { 5, 0, NULL, NULL, 0 }, + + /* Unsigned immediate in bits 9-5, used only for shift instructions */ +#define ENDMASK (ROTATE + 1) + { 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK }, + +}; + +const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); + + +/* Macros used to generate entries for the opcodes table. */ + +#define FIXME 0 + +/* Short-Immediate Format Instructions - basic opcode */ +#define OP_SI(x) (((x) & 0x7F) << 15) +#define MASK_SI OP_SI(0x7F) + +/* Long-Immediate Format Instructions - basic opcode */ +#define OP_LI(x) (((x) & 0x3FF) << 12) +#define MASK_LI OP_LI(0x3FF) + +/* Register Format Instructions - basic opcode */ +#define OP_REG(x) OP_LI(x) /* For readability */ +#define MASK_REG MASK_LI /* For readability */ + +/* The 'n' bit at bit 10 */ +#define n(x) ((x) << 10) + +/* The 'i' bit at bit 11 */ +#define i(x) ((x) << 11) + +/* The 'F' bit at bit 27 */ +#define F(x) ((x) << 27) + +/* The 'E' bit at bit 27 */ +#define E(x) ((x) << 27) + +/* The 'M' bit at bit 15 in register and long immediate opcodes */ +#define M_REG(x) ((x) << 15) +#define M_LI(x) ((x) << 15) + +/* The 'M' bit at bit 17 in short immediate opcodes */ +#define M_SI(x) ((x) << 17) + +/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */ +#define SZ_REG(x) ((x) << 13) +#define SZ_LI(x) ((x) << 13) + +/* The 'SZ' field at bits 16-15 in short immediate opcodes */ +#define SZ_SI(x) ((x) << 15) + +/* The 'D' (direct external memory access) bit at bit 10 in long immediate + and register opcodes. */ +#define D(x) ((x) << 10) + +/* The 'S' (scale offset by data size) bit at bit 11 in long immediate + and register opcodes. */ +#define S(x) ((x) << 11) + +/* The 'PD' field at bits 10-9 in floating point instructions */ +#define PD(x) ((x) << 9) + +/* The 'P2' field at bits 8-7 in floating point instructions */ +#define P2(x) ((x) << 7) + +/* The 'P1' field at bits 6-5 in floating point instructions */ +#define P1(x) ((x) << 5) + +/* The 'a' field at bit 16 in vector instructions */ +#define V_a1(x) ((x) << 16) + +/* The 'a' field at bit 11 in vector instructions */ +#define V_a0(x) ((x) << 11) + +/* The 'm' field at bit 10 in vector instructions */ +#define V_m(x) ((x) << 10) + +/* The 'S' field at bit 9 in vector instructions */ +#define V_S(x) ((x) << 9) + +/* The 'Z' field at bit 8 in vector instructions */ +#define V_Z(x) ((x) << 8) + +/* The 'p' field at bit 6 in vector instructions */ +#define V_p(x) ((x) << 6) + +/* The opcode field at bits 21-17 for vector instructions */ +#define OP_V(x) ((x) << 17) +#define MASK_V OP_V(0x1F) + + +/* The opcode table. Formatted for better readability on a wide screen. Also, all + entries with the same mnemonic are sorted so that they are adjacent in the table, + allowing the use of a hash table to locate the first of a sequence of opcodes that have + a particular name. The short immediate forms also come before the long immediate forms + so that the assembler will pick the "best fit" for the size of the operand, except for + the case of the PC relative forms, where the long forms come first and are the default + forms. */ + +const struct tic80_opcode tic80_opcodes[] = { + + /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this + specific bit pattern will get disassembled as a nop rather than an rdcr. The + mask of all ones ensures that this will happen. */ + + {"nop", OP_SI(0x4), ~0, 0, {0} }, + + /* The "br" instruction is really "bbz target,r0,31". We put it first so that + this specific bit pattern will get disassembled as a br rather than bbz. */ + + {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, + {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, + {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, + {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, + + /* Signed integer ADD */ + + {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Unsigned integer ADD */ + + {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND */ + + {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND with ones complement of both sources */ + + {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND with ones complement of source 1 */ + + {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND with ones complement of source 2 */ + + {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Branch Bit One - nonannulled */ + + {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Bit One - annulled */ + + {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Bit Zero - nonannulled */ + + {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Bit Zero - annulled */ + + {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Conditional - nonannulled */ + + {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, + {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, + {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, + + /* Branch Conditional - annulled */ + + {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, + {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, + {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, + + /* Branch Control Register */ + + {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, + {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} }, + {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} }, + + /* Branch and save return - nonannulled */ + + {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, + {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, + {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, + + /* Branch and save return - annulled */ + + {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, + {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, + {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, + + /* Send command */ + + {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, + {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} }, + {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} }, + + /* Integer compare */ + + {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Flush data cache subblock - don't clear subblock preset flag */ + + {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, + {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, + {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, + + /* Flush data cache subblock - clear subblock preset flag */ + + {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, + {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, + {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, + + /* Direct load signed data into register */ + + {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Direct load unsigned data into register */ + + {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Direct store data into memory */ + + {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Emulation stop */ + + {"estop", OP_LI(0x3FC), MASK_LI, 0, {0} }, + + /* Emulation trap */ + + {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, + {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} }, + {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} }, + + /* Floating-point addition */ + + {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Floating point compare */ + + {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} }, + {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} }, + {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} }, + {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} }, + {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Floating point divide */ + + {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Floating point multiply */ + + {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} }, + {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} }, + {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Convert/Round to Minus Infinity */ + + {"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Convert/Round to Nearest */ + + {"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Convert/Round to Positive Infinity */ + + {"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Convert/Round to Zero */ + + {"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Floating point square root */ + + {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Floating point subtraction */ + + { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Illegal instructions */ + + {"illop0", OP_SI(0x0), MASK_SI, 0, {0} }, + {"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} }, + + /* Jump and save return */ + + {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, + {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, + {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, + {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, + {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, + {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, + + /* Load Signed Data Into Register */ + + {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, + {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Load Unsigned Data Into Register */ + + {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Leftmost one */ + + {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, + + /* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */ + + {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Read Control Register */ + + {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, + {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} }, + {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} }, + + /* Rightmost one */ + + {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, + + /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions. + They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */ + + + {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Shift Register Left With Inverted Endmask */ + + {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions. + They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */ + + {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Shift Register Right With Inverted Endmask */ + + {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Store Data into Memory */ + + {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, + {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Signed Integer Subtract */ + + {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Unsigned Integer Subtract */ + + {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Write Control Register + Is a special form of the "swcr" instruction so comes before it in the table. */ + + {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, + {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} }, + {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} }, + + /* Swap Control Register */ + + {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, + {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} }, + {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Trap */ + + {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, + {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} }, + {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} }, + + /* Vector Floating-Point Add */ + + {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, + {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, + {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, + {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, + {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, + + /* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented. + From the documentation there appears to be no way to tell the difference between the opcodes for + instructions that have register destinations and instructions that have accumulator destinations. + Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up + and running, it is defered until later. */ + + /* Vector Floating-Point Multiply + Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */ + + {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} }, + {"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} }, + {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} }, + {"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, + {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, + + /* Vector Floating-Point Multiply and Subtract from Accumulator + FIXME: See note above for vmac instruction */ + + /* Vector Floating-Point Subtract Accumulator From Source + FIXME: See note above for vmac instruction */ + + /* Vector Round With Floating-Point Input + FIXME: See note above for vmac instruction */ + + /* Vector Round with Integer Input */ + + {"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}}, + {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, + {"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}}, + {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, + {"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}}, + {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, + {"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}}, + {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, + + /* Vector Floating-Point Subtract */ + + {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, + {"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, + {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, + {"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, + {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, + + /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other + vector instructions so that the disassembler will always print the load/store instruction second for + vector instructions that have two instructions in the same opcode. */ + + {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, + {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, + {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + + /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other + vector instructions so that the disassembler will always print the load/store instruction second for + vector instructions that have two instructions in the same opcode. */ + + {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, + {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + + {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + +}; + +const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]); diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c new file mode 100644 index 0000000..e72b1e8 --- /dev/null +++ b/opcodes/v850-dis.c @@ -0,0 +1,384 @@ +/* Disassemble V850 instructions. + Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include + +#include "sysdep.h" +#include "opcode/v850.h" +#include "dis-asm.h" +#include "opintl.h" + +static const char *const v850_reg_names[] = +{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" }; + +static const char *const v850_sreg_names[] = +{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", + "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", + "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", + "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", + "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", + "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" }; + +static const char *const v850_cc_names[] = +{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", + "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" }; + +static int disassemble + PARAMS ((bfd_vma, struct disassemble_info *, unsigned long)); + +static int +disassemble (memaddr, info, insn) + bfd_vma memaddr; + struct disassemble_info *info; + unsigned long insn; +{ + struct v850_opcode * op = (struct v850_opcode *)v850_opcodes; + const struct v850_operand * operand; + int match = 0; + int short_op = ((insn & 0x0600) != 0x0600); + int bytes_read; + int target_processor; + + /* Special case: 32 bit MOV */ + if ((insn & 0xffe0) == 0x0620) + short_op = true; + + bytes_read = short_op ? 2 : 4; + + /* If this is a two byte insn, then mask off the high bits. */ + if (short_op) + insn &= 0xffff; + + switch (info->mach) + { + case 0: + default: + target_processor = PROCESSOR_V850; + break; + + case bfd_mach_v850e: + target_processor = PROCESSOR_V850E; + break; + + case bfd_mach_v850ea: + target_processor = PROCESSOR_V850EA; + break; + } + + /* Find the opcode. */ + while (op->name) + { + if ((op->mask & insn) == op->opcode + && (op->processors & target_processor)) + { + const unsigned char * opindex_ptr; + unsigned int opnum; + unsigned int memop; + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); +/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/ + + memop = op->memop; + /* Now print the operands. + + MEMOP is the operand number at which a memory + address specification starts, or zero if this + instruction has no memory addresses. + + A memory address is always two arguments. + + This information allows us to determine when to + insert commas into the output stream as well as + when to insert disp[reg] expressions onto the + output stream. */ + + for (opindex_ptr = op->operands, opnum = 1; + *opindex_ptr != 0; + opindex_ptr++, opnum++) + { + long value; + int flag; + int status; + bfd_byte buffer[ 4 ]; + + operand = &v850_operands[*opindex_ptr]; + + if (operand->extract) + value = (operand->extract) (insn, 0); + else + { + if (operand->bits == -1) + value = (insn & operand->shift); + else + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + + if (operand->flags & V850_OPERAND_SIGNED) + value = ((long)(value << (32 - operand->bits)) + >> (32 - operand->bits)); + } + + /* The first operand is always output without any + special handling. + + For the following arguments: + + If memop && opnum == memop + 1, then we need '[' since + we're about to output the register used in a memory + reference. + + If memop && opnum == memop + 2, then we need ']' since + we just finished the register in a memory reference. We + also need a ',' before this operand. + + Else we just need a comma. + + We may need to output a trailing ']' if the last operand + in an instruction is the register for a memory address. + + The exception (and there's always an exception) is the + "jmp" insn which needs square brackets around it's only + register argument. */ + + if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "["); + else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],"); + else if (memop == 1 && opnum == 1 + && (operand->flags & V850_OPERAND_REG)) + info->fprintf_func (info->stream, "["); + else if (opnum > 1) info->fprintf_func (info->stream, ", "); + + /* extract the flags, ignorng ones which do not effect disassembly output. */ + flag = operand->flags; + flag &= ~ V850_OPERAND_SIGNED; + flag &= ~ V850_OPERAND_RELAX; + flag &= - flag; + + switch (flag) + { + case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break; + case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break; + case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break; + case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break; + default: info->fprintf_func (info->stream, "%d", value); break; + case V850_OPERAND_DISP: + { + bfd_vma addr = value + memaddr; + + /* On the v850 the top 8 bits of an address are used by an overlay manager. + Thus it may happen that when we are looking for a symbol to match + against an address with some of its top bits set, the search fails to + turn up an exact match. In this case we try to find an exact match + against a symbol in the lower address space, and if we find one, we + use that address. We only do this for JARL instructions however, as + we do not want to misinterpret branch instructions. */ + if (operand->bits == 22) + { + if ( ! info->symbol_at_address_func (addr, info) + && ((addr & 0xFF000000) != 0) + && info->symbol_at_address_func (addr & 0x00FFFFFF, info)) + { + addr &= 0x00FFFFFF; + } + } + info->print_address_func (addr, info); + break; + } + + case V850E_PUSH_POP: + { + static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; + static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; + static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 }; + int * regs; + int i; + unsigned long int mask = 0; + int pc = false; + int sr = false; + + + switch (operand->shift) + { + case 0xffe00001: regs = list12_regs; break; + case 0xfff8000f: regs = list18_h_regs; break; + case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */ + default: + /* xgettext:c-format */ + fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift ); + abort(); + } + + for (i = 0; i < 32; i++) + { + if (value & (1 << i)) + { + switch (regs[ i ]) + { + default: mask |= (1 << regs[ i ]); break; + /* xgettext:c-format */ + case 0: fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort(); + case -1: pc = true; break; + case -2: sr = true; break; + } + } + } + + info->fprintf_func (info->stream, "{"); + + if (mask || pc || sr) + { + if (mask) + { + unsigned int bit; + int shown_one = false; + + for (bit = 0; bit < 32; bit++) + if (mask & (1 << bit)) + { + unsigned long int first = bit; + unsigned long int last; + + if (shown_one) + info->fprintf_func (info->stream, ", "); + else + shown_one = true; + + info->fprintf_func (info->stream, v850_reg_names[first]); + + for (bit++; bit < 32; bit++) + if ((mask & (1 << bit)) == 0) + break; + + last = bit; + + if (last > first + 1) + { + info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]); + } + } + } + + if (pc) + info->fprintf_func (info->stream, "%sPC", mask ? ", " : ""); + if (sr) + info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : ""); + } + + info->fprintf_func (info->stream, "}"); + } + break; + + case V850E_IMMEDIATE16: + status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info); + if (status == 0) + { + bytes_read += 2; + value = bfd_getl16 (buffer); + + /* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */ + if ((insn & 0x001fffc0) == 0x00130780) + value <<= 16; + + info->fprintf_func (info->stream, "0x%x", value); + } + else + { + info->memory_error_func (status, memaddr + bytes_read, info); + } + break; + + case V850E_IMMEDIATE32: + status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info); + if (status == 0) + { + bytes_read += 4; + value = bfd_getl32 (buffer); + info->fprintf_func (info->stream, "0x%lx", value); + } + else + { + info->memory_error_func (status, memaddr + bytes_read, info); + } + break; + } + + /* Handle jmp correctly. */ + if (memop == 1 && opnum == 1 + && ((operand->flags & V850_OPERAND_REG) != 0)) + (*info->fprintf_func) (info->stream, "]"); + } + + /* Close any square bracket we left open. */ + if (memop && opnum == memop + 2) + (*info->fprintf_func) (info->stream, "]"); + + /* All done. */ + break; + } + op++; + } + + if (!match) + { + if (short_op) + info->fprintf_func (info->stream, ".short\t0x%04x", insn); + else + info->fprintf_func (info->stream, ".long\t0x%08x", insn); + } + + return bytes_read; +} + +int +print_insn_v850 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info * info; +{ + int status; + bfd_byte buffer[ 4 ]; + unsigned long insn = 0; + + /* First figure out how big the opcode is. */ + + status = info->read_memory_func (memaddr, buffer, 2, info); + if (status == 0) + { + insn = bfd_getl16 (buffer); + + if ( (insn & 0x0600) == 0x0600 + && (insn & 0xffe0) != 0x0620) + { + /* If this is a 4 byte insn, read 4 bytes of stuff. */ + status = info->read_memory_func (memaddr, buffer, 4, info); + + if (status == 0) + insn = bfd_getl32 (buffer); + } + } + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + + /* Make sure we tell our caller how many bytes we consumed. */ + return disassemble (memaddr, info, insn); +} diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c new file mode 100644 index 0000000..43ce2f1 --- /dev/null +++ b/opcodes/v850-opc.c @@ -0,0 +1,813 @@ +/* Assemble V850 instructions. + Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "opcode/v850.h" +#include +#include "opintl.h" + +/* regular opcode */ +#define OP(x) ((x & 0x3f) << 5) +#define OP_MASK OP (0x3f) + +/* conditional branch opcode */ +#define BOP(x) ((0x0b << 7) | (x & 0x0f)) +#define BOP_MASK ((0x0f << 7) | 0x0f) + +/* one-word opcodes */ +#define one(x) ((unsigned int) (x)) + +/* two-word opcodes */ +#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) + +static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d9 PARAMS ((long unsigned, int *)); +static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d22 PARAMS ((long unsigned, int *)); +static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d16_15 PARAMS ((long unsigned, int *)); +static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d8_7 PARAMS ((long unsigned, int *)); +static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d8_6 PARAMS ((long unsigned, int *)); +static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d5_4 PARAMS ((long unsigned, int *)); +static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_d16_16 PARAMS ((long unsigned, int *)); +static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_i9 PARAMS ((long unsigned, int *)); +static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_u9 PARAMS ((long unsigned, int *)); +static long unsigned insert_spe PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_spe PARAMS ((long unsigned, int *)); +static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **)); +static long unsigned extract_i5div PARAMS ((long unsigned, int *)); + + +/* The functions used to insert and extract complicated operands. */ + +/* Note: There is a conspiracy between these functions and + v850_insert_operand() in gas/config/tc-v850.c. Error messages + containing the string 'out of range' will be ignored unless a + specific command line option is given to GAS. */ + +static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); +static const char * out_of_range = N_ ("displacement value is out of range"); +static const char * not_aligned = N_ ("displacement value is not aligned"); + +static const char * immediate_out_of_range = N_ ("immediate value is out of range"); + +static unsigned long +insert_d9 (insn, value, errmsg) + unsigned long insn; + long value; + const char ** errmsg; +{ + if (value > 0xff || value < -0x100) + { + if ((value % 2) != 0) + * errmsg = _("branch value not in range and to odd offset"); + else + * errmsg = _("branch value out of range"); + } + else if ((value % 2) != 0) + * errmsg = _("branch to odd offset"); + + return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); +} + +static unsigned long +extract_d9 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); + + if ((insn & 0x8000) != 0) + ret -= 0x0200; + + return ret; +} + +static unsigned long +insert_d22 (insn, value, errmsg) + unsigned long insn; + long value; + const char ** errmsg; +{ + if (value > 0x1fffff || value < -0x200000) + { + if ((value % 2) != 0) + * errmsg = _("branch value not in range and to an odd offset"); + else + * errmsg = _("branch value out of range"); + } + else if ((value % 2) != 0) + * errmsg = _("branch to odd offset"); + + return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); +} + +static unsigned long +extract_d22 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); + + return (unsigned long) ((ret << 10) >> 10); +} + +static unsigned long +insert_d16_15 (insn, value, errmsg) + unsigned long insn; + long value; + const char ** errmsg; +{ + if (value > 0x7fff || value < -0x8000) + { + if ((value % 2) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 2) != 0) + * errmsg = _(not_aligned); + + return insn | ((value & 0xfffe) << 16); +} + +static unsigned long +extract_d16_15 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + signed long ret = (insn & 0xfffe0000); + + return ret >> 16; +} + +static unsigned long +insert_d8_7 (insn, value, errmsg) + unsigned long insn; + long value; + const char ** errmsg; +{ + if (value > 0xff || value < 0) + { + if ((value % 2) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 2) != 0) + * errmsg = _(not_aligned); + + value >>= 1; + + return (insn | (value & 0x7f)); +} + +static unsigned long +extract_d8_7 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + unsigned long ret = (insn & 0x7f); + + return ret << 1; +} + +static unsigned long +insert_d8_6 (insn, value, errmsg) + unsigned long insn; + long value; + const char ** errmsg; +{ + if (value > 0xff || value < 0) + { + if ((value % 4) != 0) + *errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 4) != 0) + * errmsg = _(not_aligned); + + value >>= 1; + + return (insn | (value & 0x7e)); +} + +static unsigned long +extract_d8_6 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + unsigned long ret = (insn & 0x7e); + + return ret << 1; +} + +static unsigned long +insert_d5_4 (insn, value, errmsg) + unsigned long insn; + long value; + const char ** errmsg; +{ + if (value > 0x1f || value < 0) + { + if (value & 1) + * errmsg = _(not_valid); + else + *errmsg = _(out_of_range); + } + else if (value & 1) + * errmsg = _(not_aligned); + + value >>= 1; + + return (insn | (value & 0x0f)); +} + +static unsigned long +extract_d5_4 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + unsigned long ret = (insn & 0x0f); + + return ret << 1; +} + +static unsigned long +insert_d16_16 (insn, value, errmsg) + unsigned long insn; + signed long value; + const char ** errmsg; +{ + if (value > 0x7fff || value < -0x8000) + * errmsg = _(out_of_range); + + return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); +} + +static unsigned long +extract_d16_16 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + signed long ret = insn & 0xfffe0000; + + ret >>= 16; + + ret |= ((insn & 0x20) >> 5); + + return ret; +} + +static unsigned long +insert_i9 (insn, value, errmsg) + unsigned long insn; + signed long value; + const char ** errmsg; +{ + if (value > 0xff || value < -0x100) + * errmsg = _(immediate_out_of_range); + + return insn | ((value & 0x1e0) << 13) | (value & 0x1f); +} + +static unsigned long +extract_i9 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + signed long ret = insn & 0x003c0000; + + ret <<= 10; + ret >>= 23; + + ret |= (insn & 0x1f); + + return ret; +} + +static unsigned long +insert_u9 (insn, v, errmsg) + unsigned long insn; + long v; + const char ** errmsg; +{ + unsigned long value = (unsigned long) v; + if (value > 0x1ff) + * errmsg = _(immediate_out_of_range); + + return insn | ((value & 0x1e0) << 13) | (value & 0x1f); +} + +static unsigned long +extract_u9 (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + unsigned long ret = insn & 0x003c0000; + + ret >>= 13; + + ret |= (insn & 0x1f); + + return ret; +} + +static unsigned long +insert_spe (insn, v, errmsg) + unsigned long insn; + long v; + const char ** errmsg; +{ + unsigned long value = (unsigned long) v; + + if (value != 3) + * errmsg = _("invalid register for stack adjustment"); + + return insn & (~ 0x180000); +} + +static unsigned long +extract_spe (insn, invalid) + unsigned long insn ATTRIBUTE_UNUSED; + int * invalid ATTRIBUTE_UNUSED; +{ + return 3; +} + +static unsigned long +insert_i5div (insn, v, errmsg) + unsigned long insn; + long v; + const char ** errmsg; +{ + unsigned long value = (unsigned long) v; + + if (value > 0x1ff) + { + if (value & 1) + * errmsg = _("immediate value not in range and not even"); + else + * errmsg = _(immediate_out_of_range); + } + else if (value & 1) + * errmsg = _("immediate value must be even"); + + value = 32 - value; + + return insn | ((value & 0x1e) << 17); +} + +static unsigned long +extract_i5div (insn, invalid) + unsigned long insn; + int * invalid ATTRIBUTE_UNUSED; +{ + unsigned long ret = insn & 0x3c0000; + + ret >>= 17; + + ret = 32 - ret; + + return ret; +} + + +/* Warning: code in gas/config/tc-v850.c examines the contents of this array. + If you change any of the values here, be sure to look for side effects in + that code. */ +const struct v850_operand v850_operands[] = +{ +#define UNUSED 0 + { 0, 0, NULL, NULL, 0 }, + +/* The R1 field in a format 1, 6, 7, or 9 insn. */ +#define R1 (UNUSED + 1) + { 5, 0, NULL, NULL, V850_OPERAND_REG }, + +/* As above, but register 0 is not allowed. */ +#define R1_NOTR0 (R1 + 1) + { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, + +/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ +#define R2 (R1_NOTR0 + 1) + { 5, 11, NULL, NULL, V850_OPERAND_REG }, + +/* As above, but register 0 is not allowed. */ +#define R2_NOTR0 (R2 + 1) + { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, + +/* The imm5 field in a format 2 insn. */ +#define I5 (R2_NOTR0 + 1) + { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, + +/* The unsigned imm5 field in a format 2 insn. */ +#define I5U (I5 + 1) + { 5, 0, NULL, NULL, 0 }, + +/* The imm16 field in a format 6 insn. */ +#define I16 (I5U + 1) + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, + +/* The signed disp7 field in a format 4 insn. */ +#define D7 (I16 + 1) + { 7, 0, NULL, NULL, 0}, + +/* The disp16 field in a format 6 insn. */ +#define D16_15 (D7 + 1) + { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, + +/* The 3 bit immediate field in format 8 insn. */ +#define B3 (D16_15 + 1) + { 3, 11, NULL, NULL, 0 }, + +/* The 4 bit condition code in a setf instruction */ +#define CCCC (B3 + 1) + { 4, 0, NULL, NULL, V850_OPERAND_CC }, + +/* The unsigned DISP8 field in a format 4 insn. */ +#define D8_7 (CCCC + 1) + { 7, 0, insert_d8_7, extract_d8_7, 0 }, + +/* The unsigned DISP8 field in a format 4 insn. */ +#define D8_6 (D8_7 + 1) + { 6, 1, insert_d8_6, extract_d8_6, 0 }, + +/* System register operands. */ +#define SR1 (D8_6 + 1) + { 5, 0, NULL, NULL, V850_OPERAND_SRG }, + +/* EP Register. */ +#define EP (SR1 + 1) + { 0, 0, NULL, NULL, V850_OPERAND_EP }, + +/* The imm16 field (unsigned) in a format 6 insn. */ +#define I16U (EP + 1) + { 16, 16, NULL, NULL, 0}, + +/* The R2 field as a system register. */ +#define SR2 (I16U + 1) + { 5, 11, NULL, NULL, V850_OPERAND_SRG }, + +/* The disp16 field in a format 8 insn. */ +#define D16 (SR2 + 1) + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, + +/* The DISP9 field in a format 3 insn, relaxable. */ +#define D9_RELAX (D16 + 1) + { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, + +/* The DISP22 field in a format 4 insn, relaxable. + This _must_ follow D9_RELAX; the assembler assumes that the longer + version immediately follows the shorter version for relaxing. */ +#define D22 (D9_RELAX + 1) + { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, + +/* The signed disp4 field in a format 4 insn. */ +#define D4 (D22 + 1) + { 4, 0, NULL, NULL, 0}, + +/* The unsigned disp5 field in a format 4 insn. */ +#define D5_4 (D4 + 1) + { 4, 0, insert_d5_4, extract_d5_4, 0 }, + +/* The disp16 field in an format 7 unsigned byte load insn. */ +#define D16_16 (D5_4 + 1) + { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, + +/* Third register in conditional moves. */ +#define R3 (D16_16 + 1) + { 5, 27, NULL, NULL, V850_OPERAND_REG }, + +/* Condition code in conditional moves. */ +#define MOVCC (R3 + 1) + { 4, 17, NULL, NULL, V850_OPERAND_CC }, + +/* The imm9 field in a multiply word. */ +#define I9 (MOVCC + 1) + { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, + +/* The unsigned imm9 field in a multiply word. */ +#define U9 (I9 + 1) + { 9, 0, insert_u9, extract_u9, 0 }, + +/* A list of registers in a prepare/dispose instruction. */ +#define LIST12 (U9 + 1) + { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, + +/* The IMM6 field in a call instruction. */ +#define I6 (LIST12 + 1) + { 6, 0, NULL, NULL, 0 }, + +/* The 16 bit immediate following a 32 bit instruction. */ +#define IMM16 (I6 + 1) + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, + +/* The 32 bit immediate following a 32 bit instruction. */ +#define IMM32 (IMM16 + 1) + { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, + +/* The imm5 field in a push/pop instruction. */ +#define IMM5 (IMM32 + 1) + { 5, 1, NULL, NULL, 0 }, + +/* Reg2 in dispose instruction. */ +#define R2DISPOSE (IMM5 + 1) + { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, + +/* Stack pointer in prepare instruction. */ +#define SP (R2DISPOSE + 1) + { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, + +/* The IMM5 field in a divide N step instruction. */ +#define I5DIV (SP + 1) + { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, + + /* The list of registers in a PUSHMH/POPMH instruction. */ +#define LIST18_H (I5DIV + 1) + { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, + + /* The list of registers in a PUSHML/POPML instruction. */ +#define LIST18_L (LIST18_H + 1) + { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ +} ; + + +/* reg-reg instruction format (Format I) */ +#define IF1 {R1, R2} + +/* imm-reg instruction format (Format II) */ +#define IF2 {I5, R2} + +/* conditional branch instruction format (Format III) */ +#define IF3 {D9_RELAX} + +/* 3 operand instruction (Format VI) */ +#define IF6 {I16, R1, R2} + +/* 3 operand instruction (Format VI) */ +#define IF6U {I16U, R1, R2} + + + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + MEMOP specifies which operand (if any) is a memory operand. + PROCESSORS specifies which CPU(s) support the opcode. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. + + The table is also sorted by name. This is used by the assembler. + When parsing an instruction the assembler finds the first occurance + of the name of the instruciton in this table and then attempts to + match the instruction's arguments with description of the operands + associated with the entry it has just found in this table. If the + match fails the assembler looks at the next entry in this table. + If that entry has the same name as the previous entry, then it + tries to match the instruction against that entry and so on. This + is how the assembler copes with multiple, different formats of the + same instruction. */ + +const struct v850_opcode v850_opcodes[] = +{ +{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, + +{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, + +/* load/store instructions */ +{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, +{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, + +{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, +{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, + +{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1, PROCESSOR_V850EA }, +{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, +{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, + +{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1, PROCESSOR_V850EA }, +{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, +{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, +{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, +{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, +{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, +{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, + +{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, +{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, +{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, +{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, +{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, +{ "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, +{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, + +{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, +{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, +{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, +{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, +{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, +{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, +{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, +{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, + +/* byte swap/extend instructions */ +{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, +{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, +{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, +{ "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, +{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, + +/* jump table instructions */ +{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, +{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, +{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, + +/* arithmetic operation instructions */ +{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, +{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, + +{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, +{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, +{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, +{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, +{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, + +/* saturated operation instructions */ +{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +/* logical operation instructions */ +{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, +{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, +{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, +{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, +{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, +{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, +{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, +{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, +{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, +{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, + +/* branch instructions */ + /* signed integer */ +{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* unsigned integer */ +{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* common */ +{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* others */ +{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + +/* Branch macros. + + We use the short form in the opcode/mask fields. The assembler + will twiddle bits as necessary if the long form is needed. */ + + /* signed integer */ +{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* unsigned integer */ +{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* common */ +{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* others */ +{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + +{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, +{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, + +/* bit manipulation instructions */ +{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, +{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, +{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, +{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, +{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, +{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, +{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, +{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, + +/* special instructions */ +{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, +{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, +{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, +{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, +{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, +{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, +{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, +{ 0, 0, 0, {0}, 0, 0 }, + +} ; + +const int v850_num_opcodes = + sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); + diff --git a/opcodes/vax-dis.c b/opcodes/vax-dis.c new file mode 100644 index 0000000..a97d4cd --- /dev/null +++ b/opcodes/vax-dis.c @@ -0,0 +1,339 @@ +/* Print VAX instructions. + Copyright 1995, 1998, 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by Pauline Middelink + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "sysdep.h" +#include "opcode/vax.h" +#include "dis-asm.h" + +/* Local function prototypes */ +static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); +static int print_insn_arg + PARAMS ((const char *, unsigned char *, bfd_vma, disassemble_info *)); +static int print_insn_mode + PARAMS ((const char *, int, unsigned char *, bfd_vma, disassemble_info *)); + + +static char *reg_names[] = +{ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "ap", "fp", "sp", "pc" +}; + +/* Sign-extend an (unsigned char). */ +#if __STDC__ == 1 +#define COERCE_SIGNED_CHAR(ch) ((signed char)(ch)) +#else +#define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128) +#endif + +/* Get a 1 byte signed integer. */ +#define NEXTBYTE(p) \ + (p += 1, FETCH_DATA (info, p), \ + COERCE_SIGNED_CHAR(p[-1])) + +/* Get a 2 byte signed integer. */ +#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) +#define NEXTWORD(p) \ + (p += 2, FETCH_DATA (info, p), \ + COERCE16 ((p[-1] << 8) + p[-2])) + +/* Get a 4 byte signed integer. */ +#define COERCE32(x) ((int) (((x) ^ 0x80000000) - 0x80000000)) +#define NEXTLONG(p) \ + (p += 4, FETCH_DATA (info, p), \ + (COERCE32 ((((((p[-1] << 8) + p[-2]) << 8) + p[-3]) << 8) + p[-4]))) + +/* Maximum length of an instruction. */ +#define MAXLEN 25 + +#include + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (info, addr) + struct disassemble_info *info; + bfd_byte *addr; +{ + int status; + struct private *priv = (struct private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + + return 1; +} + +/* Print the vax instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_vax (memaddr, info) + bfd_vma memaddr; + disassemble_info *info; +{ + const struct vot *votp; + const char *argp; + unsigned char *arg; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + + info->private_data = (PTR) &priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + + if (setjmp (priv.bailout) != 0) + { + /* Error return. */ + return -1; + } + + argp = NULL; + /* Check if the info buffer has more than one byte left since + the last opcode might be a single byte with no argument data. */ + if (info->buffer_length - (memaddr - info->buffer_vma) > 1) + { + FETCH_DATA (info, buffer + 2); + } + else + { + FETCH_DATA (info, buffer + 1); + buffer[1] = 0; + } + + for (votp = &votstrs[0]; votp->name[0]; votp++) + { + register vax_opcodeT opcode = votp->detail.code; + + /* 2 byte codes match 2 buffer pos. */ + if ((bfd_byte) opcode == buffer[0] + && (opcode >> 8 == 0 || opcode >> 8 == buffer[1])) + { + argp = votp->detail.args; + break; + } + } + if (argp == NULL) + { + /* Handle undefined instructions. */ + (*info->fprintf_func) (info->stream, ".word 0x%x", + (buffer[0] << 8) + buffer[1]); + return 2; + } + + /* Point at first byte of argument data, and at descriptor for first + argument. */ + arg = buffer + ((votp->detail.code >> 8) ? 2 : 1); + + /* Make sure we have it in mem */ + FETCH_DATA (info, arg); + + (*info->fprintf_func) (info->stream, "%s", votp->name); + if (*argp) + (*info->fprintf_func) (info->stream, " "); + + while (*argp) + { + arg += print_insn_arg (argp, arg, memaddr + arg - buffer, info); + argp += 2; + if (*argp) + (*info->fprintf_func) (info->stream, ","); + } + + return arg - buffer; +} + +/* Returns number of bytes "eaten" by the operand, or return -1 if an + invalid operand was found, or -2 if an opcode tabel error was + found. */ + +static int +print_insn_arg (d, p0, addr, info) + const char *d; + unsigned char *p0; + bfd_vma addr; /* PC for this arg to be relative to */ + disassemble_info *info; +{ + int arg_len; + + /* check validity of addressing length */ + switch (d[1]) + { + case 'b' : arg_len = 1; break; + case 'd' : arg_len = 8; break; + case 'f' : arg_len = 4; break; + case 'g' : arg_len = 8; break; + case 'h' : arg_len = 16; break; + case 'l' : arg_len = 4; break; + case 'o' : arg_len = 16; break; + case 'w' : arg_len = 2; break; + case 'q' : arg_len = 8; break; + default : abort(); + } + + /* branches have no mode byte */ + if (d[0] == 'b') + { + unsigned char *p = p0; + + if (arg_len == 1) + (*info->print_address_func) (addr + 1 + NEXTBYTE (p), info); + else + (*info->print_address_func) (addr + 2 + NEXTWORD (p), info); + + return p - p0; + } + + return print_insn_mode (d, arg_len, p0, addr, info); +} + +static int +print_insn_mode (d, size, p0, addr, info) + const char *d; + int size; + unsigned char *p0; + bfd_vma addr; /* PC for this arg to be relative to */ + disassemble_info *info; +{ + unsigned char *p = p0; + unsigned char mode, reg; + + /* fetch and interpret mode byte */ + mode = (unsigned char) NEXTBYTE (p); + reg = mode & 0xF; + switch (mode & 0xF0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: /* literal mode $number */ + if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') + (*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]); + else + (*info->fprintf_func) (info->stream, "$0x%x", mode); + break; + case 0x40: /* index: base-addr[Rn] */ + p += print_insn_mode (d, size, p0 + 1, addr + 1, info); + (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]); + break; + case 0x50: /* register: Rn */ + (*info->fprintf_func) (info->stream, "%s", reg_names[reg]); + break; + case 0x60: /* register deferred: (Rn) */ + (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]); + break; + case 0x70: /* autodecrement: -(Rn) */ + (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]); + break; + case 0x80: /* autoincrement: (Rn)+ */ + if (reg == 0xF) + { /* immediate? */ + int i; + + FETCH_DATA (info, p + size); + (*info->fprintf_func) (info->stream, "$0x"); + if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') + { + int float_word; + + float_word = p[0] | (p[1] << 8); + if ((d[1] == 'd' || d[1] == 'f') + && (float_word & 0xff80) == 0x8000) + { + (*info->fprintf_func) (info->stream, "[invalid %c-float]", + d[1]); + } + else + { + for (i = 0; i < size; i++) + (*info->fprintf_func) (info->stream, "%02x", + p[size - i - 1]); + (*info->fprintf_func) (info->stream, " [%c-float]", d[1]); + } + } + else + { + for (i = 0; i < size; i++) + (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]); + } + p += size; + } + else + (*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]); + break; + case 0x90: /* autoincrement deferred: @(Rn)+ */ + if (reg == 0xF) + (*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p)); + else + (*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]); + break; + case 0xB0: /* displacement byte deferred: *displ(Rn) */ + (*info->fprintf_func) (info->stream, "*"); + case 0xA0: /* displacement byte: displ(Rn) */ + if (reg == 0xF) + (*info->print_address_func) (addr + 2 + NEXTBYTE (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p), + reg_names[reg]); + break; + case 0xD0: /* displacement word deferred: *displ(Rn) */ + (*info->fprintf_func) (info->stream, "*"); + case 0xC0: /* displacement word: displ(Rn) */ + if (reg == 0xF) + (*info->print_address_func) (addr + 3 + NEXTWORD (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p), + reg_names[reg]); + break; + case 0xF0: /* displacement long deferred: *displ(Rn) */ + (*info->fprintf_func) (info->stream, "*"); + case 0xE0: /* displacement long: displ(Rn) */ + if (reg == 0xF) + (*info->print_address_func) (addr + 5 + NEXTLONG (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p), + reg_names[reg]); + break; + } + + return p - p0; +} diff --git a/opcodes/w65-dis.c b/opcodes/w65-dis.c new file mode 100644 index 0000000..8e9c724 --- /dev/null +++ b/opcodes/w65-dis.c @@ -0,0 +1,121 @@ +/* Disassemble WDC 65816 instructions. + Copyright 1995, 1998, 2000, 2001 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "w65-opc.h" +#include "dis-asm.h" + +static fprintf_ftype fpr; +static void *stream; +static struct disassemble_info *local_info; + +static void print_operand PARAMS ((int, char *, unsigned int *)); + +#if 0 +static char *lname[] = { "r0","r1","r2","r3","r4","r5","r6","r7","s0" }; + +static char * +findname (val) + unsigned int val; +{ + if (val >= 0x10 && val <= 0x20) + return lname[(val - 0x10) / 2]; + return 0; +} +#endif +static void +print_operand (lookup, format, args) + int lookup; + char *format; + unsigned int *args; +{ + int val; + int c; + + while (*format) + { + switch (c = *format++) + { + case '$': + val = args[(*format++) - '0']; + if (lookup) + { +#if 0 + name = findname (val); + if (name) + fpr (stream, "%s", name); + else +#endif + local_info->print_address_func (val, local_info); + } + else + fpr (stream, "0x%x", val); + + break; + default: + fpr (stream, "%c", c); + break; + } + } +} + +int +print_insn_w65 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status = 0; + unsigned char insn[4]; + register struct opinfo *op; + int i; + int X = 0; + int M = 0; + int args[2]; + stream = info->stream; + fpr = info->fprintf_func; + local_info = info; + for (i = 0; i < 4 && status == 0; i++) + { + status = info->read_memory_func (memaddr + i, insn + i, 1, info); + } + + for (op = optable; op->val != insn[0]; op++) + ; + + fpr (stream, "%s", op->name); + + /* Prepare all the posible operand values. */ + { + int size = 1; + int asR_W65_ABS8 = insn[1]; + int asR_W65_ABS16 = (insn[2] << 8) + asR_W65_ABS8; + int asR_W65_ABS24 = (insn[3] << 16) + asR_W65_ABS16; + int asR_W65_PCR8 = ((char) (asR_W65_ABS8)) + memaddr + 2; + int asR_W65_PCR16 = ((short) (asR_W65_ABS16)) + memaddr + 3; + + switch (op->amode) + { + DISASM (); + } + + return size; + } +} diff --git a/opcodes/w65-opc.h b/opcodes/w65-opc.h new file mode 100644 index 0000000..25be2e9 --- /dev/null +++ b/opcodes/w65-opc.h @@ -0,0 +1,569 @@ +/* Instruction opcode header for WDC 65816 + (generated by the program sim/w65/gencode -a) + +Copyright 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#define ADDR_IMMTOA 1 /* #a */ +#define ADDR_IMMCOP 2 /* #c */ +#define ADDR_IMMTOI 3 /* #i */ +#define ADDR_ACC 4 /* A */ +#define ADDR_PC_REL 5 /* r */ +#define ADDR_PC_REL_LONG 6 /* rl */ +#define ADDR_IMPLIED 7 /* i */ +#define ADDR_STACK 8 /* s */ +#define ADDR_DIR 9 /* d */ +#define ADDR_DIR_IDX_X 10 /* d,x */ +#define ADDR_DIR_IDX_Y 11 /* d,y */ +#define ADDR_DIR_IND 12 /* (d) */ +#define ADDR_DIR_IDX_IND_X 13 /* (d,x) */ +#define ADDR_DIR_IND_IDX_Y 14 /* (d),y */ +#define ADDR_DIR_IND_LONG 15 /* [d] */ +#define ADDR_DIR_IND_IDX_Y_LONG 16 /* [d],y */ +#define ADDR_ABS 17 /* a */ +#define ADDR_ABS_IDX_X 18 /* a,x */ +#define ADDR_ABS_IDX_Y 19 /* a,y */ +#define ADDR_ABS_LONG 20 /* al */ +#define ADDR_ABS_IND_LONG 21 /* [a] */ +#define ADDR_ABS_LONG_IDX_X 22 /* al,x */ +#define ADDR_STACK_REL 23 /* d,s */ +#define ADDR_STACK_REL_INDX_IDX 24 /* (d,s),y */ +#define ADDR_ABS_IND 25 /* (a) */ +#define ADDR_ABS_IND_IDX 26 /* (a,x) */ +#define ADDR_BLOCK_MOVE 27 /* xyz */ +struct opinfo { + int val; + int code; + char *name; + int amode; +}; +struct opinfo optable[257]={ +#define O_adc 1 +#define O_and 2 +#define O_asl 3 +#define O_bcc 4 +#define O_bcs 5 +#define O_beq 6 +#define O_bit 7 +#define O_bmi 8 +#define O_bne 9 +#define O_bpl 10 +#define O_bra 11 +#define O_brk 12 +#define O_brl 13 +#define O_bvc 14 +#define O_bvs 15 +#define O_clc 16 +#define O_cld 17 +#define O_cli 18 +#define O_clv 19 +#define O_cmp 20 +#define O_cop 21 +#define O_cpx 22 +#define O_cpy 23 +#define O_dec 24 +#define O_dex 25 +#define O_dey 26 +#define O_eor 27 +#define O_inc 28 +#define O_inx 29 +#define O_iny 30 +#define O_jmp 31 +#define O_jsr 32 +#define O_lda 33 +#define O_ldx 34 +#define O_ldy 35 +#define O_lsr 36 +#define O_mvn 37 +#define O_mvp 38 +#define O_nop 39 +#define O_ora 40 +#define O_pea 41 +#define O_pei 42 +#define O_per 43 +#define O_pha 44 +#define O_phb 45 +#define O_phd 46 +#define O_phk 47 +#define O_php 48 +#define O_phx 49 +#define O_phy 50 +#define O_pla 51 +#define O_plb 52 +#define O_pld 53 +#define O_plp 54 +#define O_plx 55 +#define O_ply 56 +#define O_rep 57 +#define O_rol 58 +#define O_ror 59 +#define O_rti 60 +#define O_rtl 61 +#define O_rts 62 +#define O_sbc 63 +#define O_sec 64 +#define O_sed 65 +#define O_sei 66 +#define O_sep 67 +#define O_sta 68 +#define O_stp 69 +#define O_stx 70 +#define O_sty 71 +#define O_stz 72 +#define O_tax 73 +#define O_tay 74 +#define O_tcd 75 +#define O_tcs 76 +#define O_tdc 77 +#define O_trb 78 +#define O_tsb 79 +#define O_tsc 80 +#define O_tsx 81 +#define O_txa 82 +#define O_txs 83 +#define O_txy 84 +#define O_tya 85 +#define O_tyx 86 +#define O_wai 87 +#define O_wdm 88 +#define O_xba 89 +#define O_xce 90 +#ifdef DEFINE_TABLE + {0x69, O_adc, "adc", ADDR_IMMTOA}, + {0x72, O_adc, "adc", ADDR_DIR_IND}, + {0x71, O_adc, "adc", ADDR_DIR_IND_IDX_Y}, + {0x73, O_adc, "adc", ADDR_STACK_REL_INDX_IDX}, + {0x61, O_adc, "adc", ADDR_DIR_IDX_IND_X}, + {0x67, O_adc, "adc", ADDR_DIR_IND_LONG}, + {0x77, O_adc, "adc", ADDR_DIR_IND_IDX_Y_LONG}, + {0x6D, O_adc, "adc", ADDR_ABS}, + {0x7D, O_adc, "adc", ADDR_ABS_IDX_X}, + {0x79, O_adc, "adc", ADDR_ABS_IDX_Y}, + {0x6F, O_adc, "adc", ADDR_ABS_LONG}, + {0x7F, O_adc, "adc", ADDR_ABS_LONG_IDX_X}, + {0x65, O_adc, "adc", ADDR_DIR}, + {0x63, O_adc, "adc", ADDR_STACK_REL}, + {0x75, O_adc, "adc", ADDR_DIR_IDX_X}, + {0x29, O_and, "and", ADDR_IMMTOA}, + {0x32, O_and, "and", ADDR_DIR_IND}, + {0x31, O_and, "and", ADDR_DIR_IND_IDX_Y}, + {0x33, O_and, "and", ADDR_STACK_REL_INDX_IDX}, + {0x21, O_and, "and", ADDR_DIR_IDX_IND_X}, + {0x27, O_and, "and", ADDR_DIR_IND_LONG}, + {0x37, O_and, "and", ADDR_DIR_IND_IDX_Y_LONG}, + {0x2D, O_and, "and", ADDR_ABS}, + {0x3D, O_and, "and", ADDR_ABS_IDX_X}, + {0x39, O_and, "and", ADDR_ABS_IDX_Y}, + {0x2F, O_and, "and", ADDR_ABS_LONG}, + {0x3F, O_and, "and", ADDR_ABS_LONG_IDX_X}, + {0x25, O_and, "and", ADDR_DIR}, + {0x23, O_and, "and", ADDR_STACK_REL}, + {0x35, O_and, "and", ADDR_DIR_IDX_X}, + {0x0A, O_asl, "asl", ADDR_ACC}, + {0x0E, O_asl, "asl", ADDR_ABS}, + {0x1E, O_asl, "asl", ADDR_ABS_IDX_X}, + {0x06, O_asl, "asl", ADDR_DIR}, + {0x16, O_asl, "asl", ADDR_DIR_IDX_X}, + {0x90, O_bcc, "bcc", ADDR_PC_REL}, + {0xB0, O_bcs, "bcs", ADDR_PC_REL}, + {0xF0, O_beq, "beq", ADDR_PC_REL}, + {0x89, O_bit, "bit", ADDR_IMMTOA}, + {0x24, O_bit, "bit", ADDR_DIR_IND}, + {0x34, O_bit, "bit", ADDR_DIR_IDX_IND_X}, + {0x2C, O_bit, "bit", ADDR_ABS}, + {0x3C, O_bit, "bit", ADDR_ABS_IDX_X}, + {0x30, O_bmi, "bmi", ADDR_PC_REL}, + {0xD0, O_bne, "bne", ADDR_PC_REL}, + {0x10, O_bpl, "bpl", ADDR_PC_REL}, + {0x80, O_bra, "bra", ADDR_PC_REL}, + {0x00, O_brk, "brk", ADDR_STACK}, + {0x82, O_brl, "brl", ADDR_PC_REL_LONG}, + {0x50, O_bvc, "bvc", ADDR_PC_REL}, + {0x70, O_bvs, "bvs", ADDR_PC_REL}, + {0x18, O_clc, "clc", ADDR_IMPLIED}, + {0xD8, O_cld, "cld", ADDR_IMPLIED}, + {0x58, O_cli, "cli", ADDR_IMPLIED}, + {0xB8, O_clv, "clv", ADDR_IMPLIED}, + {0xC9, O_cmp, "cmp", ADDR_IMMTOA}, + {0xD2, O_cmp, "cmp", ADDR_DIR_IND}, + {0xD1, O_cmp, "cmp", ADDR_DIR_IND_IDX_Y}, + {0xD3, O_cmp, "cmp", ADDR_STACK_REL_INDX_IDX}, + {0xC1, O_cmp, "cmp", ADDR_DIR_IDX_IND_X}, + {0xC7, O_cmp, "cmp", ADDR_DIR_IND_LONG}, + {0xD7, O_cmp, "cmp", ADDR_DIR_IND_IDX_Y_LONG}, + {0xCD, O_cmp, "cmp", ADDR_ABS}, + {0xDD, O_cmp, "cmp", ADDR_ABS_IDX_X}, + {0xD9, O_cmp, "cmp", ADDR_ABS_IDX_Y}, + {0xCF, O_cmp, "cmp", ADDR_ABS_LONG}, + {0xDF, O_cmp, "cmp", ADDR_ABS_LONG_IDX_X}, + {0xC5, O_cmp, "cmp", ADDR_DIR}, + {0xC3, O_cmp, "cmp", ADDR_STACK_REL}, + {0xD5, O_cmp, "cmp", ADDR_DIR_IDX_X}, + {0x02, O_cop, "cop", ADDR_IMMCOP}, + {0xE0, O_cpx, "cpx", ADDR_IMMTOI}, + {0xEC, O_cpx, "cpx", ADDR_ABS}, + {0xE4, O_cpx, "cpx", ADDR_DIR}, + {0xC0, O_cpy, "cpy", ADDR_IMMTOI}, + {0xCC, O_cpy, "cpy", ADDR_ABS}, + {0xC4, O_cpy, "cpy", ADDR_DIR}, + {0x3A, O_dec, "dec", ADDR_ACC}, + {0xCE, O_dec, "dec", ADDR_ABS}, + {0xDE, O_dec, "dec", ADDR_ABS_IDX_X}, + {0xC6, O_dec, "dec", ADDR_DIR}, + {0xD6, O_dec, "dec", ADDR_DIR_IDX_X}, + {0xCA, O_dex, "dex", ADDR_IMPLIED}, + {0x88, O_dey, "dey", ADDR_IMPLIED}, + {0x49, O_eor, "eor", ADDR_IMMTOA}, + {0x52, O_eor, "eor", ADDR_DIR_IND}, + {0x51, O_eor, "eor", ADDR_DIR_IND_IDX_Y}, + {0x53, O_eor, "eor", ADDR_STACK_REL_INDX_IDX}, + {0x41, O_eor, "eor", ADDR_DIR_IDX_IND_X}, + {0x47, O_eor, "eor", ADDR_DIR_IND_LONG}, + {0x57, O_eor, "eor", ADDR_DIR_IND_IDX_Y_LONG}, + {0x4D, O_eor, "eor", ADDR_ABS}, + {0x5D, O_eor, "eor", ADDR_ABS_IDX_X}, + {0x59, O_eor, "eor", ADDR_ABS_IDX_Y}, + {0x4F, O_eor, "eor", ADDR_ABS_LONG}, + {0x5F, O_eor, "eor", ADDR_ABS_LONG_IDX_X}, + {0x45, O_eor, "eor", ADDR_DIR}, + {0x43, O_eor, "eor", ADDR_STACK_REL}, + {0x55, O_eor, "eor", ADDR_DIR_IDX_X}, + {0x1A, O_inc, "inc", ADDR_ACC}, + {0xEE, O_inc, "inc", ADDR_ABS}, + {0xFE, O_inc, "inc", ADDR_ABS_IDX_X}, + {0xE6, O_inc, "inc", ADDR_DIR}, + {0xF6, O_inc, "inc", ADDR_DIR_IDX_X}, + {0xE8, O_inx, "inx", ADDR_IMPLIED}, + {0xC8, O_iny, "iny", ADDR_IMPLIED}, + {0x6C, O_jmp, "jmp", ADDR_ABS_IND}, + {0x7C, O_jmp, "jmp", ADDR_ABS_IND_IDX}, + {0xDC, O_jmp, "jmp", ADDR_ABS_IND_LONG}, + {0x4C, O_jmp, "jmp", ADDR_ABS}, + {0x5C, O_jmp, "jmp", ADDR_ABS_LONG}, + {0xFC, O_jsr, "jsr", ADDR_ABS_IND_IDX}, + {0x20, O_jsr, "jsr", ADDR_ABS}, + {0x22, O_jsr, "jsr", ADDR_ABS_LONG}, + {0xA9, O_lda, "lda", ADDR_IMMTOA}, + {0xB2, O_lda, "lda", ADDR_DIR_IND}, + {0xB1, O_lda, "lda", ADDR_DIR_IND_IDX_Y}, + {0xB3, O_lda, "lda", ADDR_STACK_REL_INDX_IDX}, + {0xA1, O_lda, "lda", ADDR_DIR_IDX_IND_X}, + {0xA7, O_lda, "lda", ADDR_DIR_IND_LONG}, + {0xB7, O_lda, "lda", ADDR_DIR_IND_IDX_Y_LONG}, + {0xAD, O_lda, "lda", ADDR_ABS}, + {0xBD, O_lda, "lda", ADDR_ABS_IDX_X}, + {0xB9, O_lda, "lda", ADDR_ABS_IDX_Y}, + {0xAF, O_lda, "lda", ADDR_ABS_LONG}, + {0xBF, O_lda, "lda", ADDR_ABS_LONG_IDX_X}, + {0xA5, O_lda, "lda", ADDR_DIR}, + {0xA3, O_lda, "lda", ADDR_STACK_REL}, + {0xB5, O_lda, "lda", ADDR_DIR_IDX_X}, + {0xA2, O_ldx, "ldx", ADDR_IMMTOI}, + {0xAE, O_ldx, "ldx", ADDR_ABS}, + {0xBE, O_ldx, "ldx", ADDR_ABS_IDX_Y}, + {0xA6, O_ldx, "ldx", ADDR_DIR}, + {0xB6, O_ldx, "ldx", ADDR_DIR_IDX_Y}, + {0xA0, O_ldy, "ldy", ADDR_IMMTOI}, + {0xAC, O_ldy, "ldy", ADDR_ABS}, + {0xBC, O_ldy, "ldy", ADDR_ABS_IDX_X}, + {0xA4, O_ldy, "ldy", ADDR_DIR}, + {0xB4, O_ldy, "ldy", ADDR_DIR_IDX_X}, + {0x4A, O_lsr, "lsr", ADDR_ACC}, + {0x4E, O_lsr, "lsr", ADDR_ABS}, + {0x5E, O_lsr, "lsr", ADDR_ABS_IDX_X}, + {0x46, O_lsr, "lsr", ADDR_DIR}, + {0x56, O_lsr, "lsr", ADDR_DIR_IDX_X}, + {0x54, O_mvn, "mvn", ADDR_BLOCK_MOVE}, + {0x44, O_mvp, "mvp", ADDR_BLOCK_MOVE}, + {0xEA, O_nop, "nop", ADDR_IMPLIED}, + {0x09, O_ora, "ora", ADDR_IMMTOA}, + {0x12, O_ora, "ora", ADDR_DIR_IND}, + {0x11, O_ora, "ora", ADDR_DIR_IND_IDX_Y}, + {0x13, O_ora, "ora", ADDR_STACK_REL_INDX_IDX}, + {0x01, O_ora, "ora", ADDR_DIR_IDX_IND_X}, + {0x07, O_ora, "ora", ADDR_DIR_IND_LONG}, + {0x17, O_ora, "ora", ADDR_DIR_IND_IDX_Y_LONG}, + {0x0D, O_ora, "ora", ADDR_ABS}, + {0x1D, O_ora, "ora", ADDR_ABS_IDX_X}, + {0x19, O_ora, "ora", ADDR_ABS_IDX_Y}, + {0x0F, O_ora, "ora", ADDR_ABS_LONG}, + {0x1F, O_ora, "ora", ADDR_ABS_LONG_IDX_X}, + {0x05, O_ora, "ora", ADDR_DIR}, + {0x03, O_ora, "ora", ADDR_STACK_REL}, + {0x15, O_ora, "ora", ADDR_DIR_IDX_X}, + {0xF4, O_pea, "pea", ADDR_ABS}, + {0xD4, O_pei, "pei", ADDR_DIR}, + {0x62, O_per, "per", ADDR_PC_REL_LONG}, + {0x48, O_pha, "pha", ADDR_STACK}, + {0x8B, O_phb, "phb", ADDR_STACK}, + {0x0B, O_phd, "phd", ADDR_STACK}, + {0x4B, O_phk, "phk", ADDR_STACK}, + {0x08, O_php, "php", ADDR_STACK}, + {0xDA, O_phx, "phx", ADDR_STACK}, + {0x5A, O_phy, "phy", ADDR_STACK}, + {0x68, O_pla, "pla", ADDR_STACK}, + {0xAB, O_plb, "plb", ADDR_STACK}, + {0x2B, O_pld, "pld", ADDR_STACK}, + {0x28, O_plp, "plp", ADDR_STACK}, + {0xFA, O_plx, "plx", ADDR_STACK}, + {0x7A, O_ply, "ply", ADDR_STACK}, + {0xC2, O_rep, "rep", ADDR_IMMCOP}, + {0x2A, O_rol, "rol", ADDR_ACC}, + {0x2E, O_rol, "rol", ADDR_ABS}, + {0x3E, O_rol, "rol", ADDR_ABS_IDX_X}, + {0x26, O_rol, "rol", ADDR_DIR}, + {0x36, O_rol, "rol", ADDR_DIR_IDX_X}, + {0x6A, O_ror, "ror", ADDR_ACC}, + {0x6E, O_ror, "ror", ADDR_ABS}, + {0x7E, O_ror, "ror", ADDR_ABS_IDX_X}, + {0x66, O_ror, "ror", ADDR_DIR}, + {0x76, O_ror, "ror", ADDR_DIR_IDX_X}, + {0x40, O_rti, "rti", ADDR_STACK}, + {0x6B, O_rtl, "rtl", ADDR_STACK}, + {0x60, O_rts, "rts", ADDR_STACK}, + {0xE9, O_sbc, "sbc", ADDR_IMMTOA}, + {0xF2, O_sbc, "sbc", ADDR_DIR_IND}, + {0xF1, O_sbc, "sbc", ADDR_DIR_IND_IDX_Y}, + {0xF3, O_sbc, "sbc", ADDR_STACK_REL_INDX_IDX}, + {0xE1, O_sbc, "sbc", ADDR_DIR_IDX_IND_X}, + {0xE7, O_sbc, "sbc", ADDR_DIR_IND_LONG}, + {0xF7, O_sbc, "sbc", ADDR_DIR_IND_IDX_Y_LONG}, + {0xED, O_sbc, "sbc", ADDR_ABS}, + {0xFD, O_sbc, "sbc", ADDR_ABS_IDX_X}, + {0xF9, O_sbc, "sbc", ADDR_ABS_IDX_Y}, + {0xEF, O_sbc, "sbc", ADDR_ABS_LONG}, + {0xFF, O_sbc, "sbc", ADDR_ABS_LONG_IDX_X}, + {0xE5, O_sbc, "sbc", ADDR_DIR}, + {0xE3, O_sbc, "sbc", ADDR_STACK_REL}, + {0xF5, O_sbc, "sbc", ADDR_DIR_IDX_X}, + {0x38, O_sec, "sec", ADDR_IMPLIED}, + {0xF8, O_sed, "sed", ADDR_IMPLIED}, + {0x78, O_sei, "sei", ADDR_IMPLIED}, + {0xE2, O_sep, "sep", ADDR_IMMCOP}, + {0x92, O_sta, "sta", ADDR_DIR_IND}, + {0x91, O_sta, "sta", ADDR_DIR_IND_IDX_Y}, + {0x93, O_sta, "sta", ADDR_STACK_REL_INDX_IDX}, + {0x81, O_sta, "sta", ADDR_DIR_IDX_IND_X}, + {0x87, O_sta, "sta", ADDR_DIR_IND_LONG}, + {0x97, O_sta, "sta", ADDR_DIR_IND_IDX_Y_LONG}, + {0x8D, O_sta, "sta", ADDR_ABS}, + {0x9D, O_sta, "sta", ADDR_ABS_IDX_X}, + {0x99, O_sta, "sta", ADDR_ABS_IDX_Y}, + {0x8F, O_sta, "sta", ADDR_ABS_LONG}, + {0x9F, O_sta, "sta", ADDR_ABS_LONG_IDX_X}, + {0x85, O_sta, "sta", ADDR_DIR}, + {0x83, O_sta, "sta", ADDR_STACK_REL}, + {0x95, O_sta, "sta", ADDR_DIR_IDX_X}, + {0xDB, O_stp, "stp", ADDR_IMPLIED}, + {0x8E, O_stx, "stx", ADDR_ABS}, + {0x86, O_stx, "stx", ADDR_DIR}, + {0x96, O_stx, "stx", ADDR_DIR_IDX_X}, + {0x8C, O_sty, "sty", ADDR_ABS}, + {0x84, O_sty, "sty", ADDR_DIR}, + {0x94, O_sty, "sty", ADDR_DIR_IDX_X}, + {0x9C, O_stz, "stz", ADDR_ABS}, + {0x9E, O_stz, "stz", ADDR_ABS_IDX_X}, + {0x64, O_stz, "stz", ADDR_DIR}, + {0x74, O_stz, "stz", ADDR_DIR_IDX_X}, + {0xAA, O_tax, "tax", ADDR_IMPLIED}, + {0xA8, O_tay, "tay", ADDR_IMPLIED}, + {0x5B, O_tcd, "tcd", ADDR_IMPLIED}, + {0x1B, O_tcs, "tcs", ADDR_IMPLIED}, + {0x7B, O_tdc, "tdc", ADDR_IMPLIED}, + {0x1C, O_trb, "trb", ADDR_ABS}, + {0x14, O_trb, "trb", ADDR_DIR}, + {0x0C, O_tsb, "tsb", ADDR_ABS}, + {0x04, O_tsb, "tsb", ADDR_DIR}, + {0x3B, O_tsc, "tsc", ADDR_IMPLIED}, + {0xBA, O_tsx, "tsx", ADDR_IMPLIED}, + {0x8A, O_txa, "txa", ADDR_IMPLIED}, + {0x9A, O_txs, "txs", ADDR_IMPLIED}, + {0x9B, O_txy, "txy", ADDR_IMPLIED}, + {0x98, O_tya, "tya", ADDR_IMPLIED}, + {0xBB, O_tyx, "tyx", ADDR_IMPLIED}, + {0xCB, O_wai, "wai", ADDR_IMPLIED}, + {0x42, O_wdm, "wdm", ADDR_IMPLIED}, + {0xEB, O_xba, "xba", ADDR_IMPLIED}, + {0xFB, O_xce, "xce", ADDR_IMPLIED}, + { 0, 0, NULL, 0 } +}; +#endif +#define DISASM()\ + case ADDR_IMMTOA:\ + args[0] = M==0 ? asR_W65_ABS16 : asR_W65_ABS8;\ + print_operand (0, " #$0", args);\ + size += M==0 ? 2:1;\ + break;\ + case ADDR_IMMCOP:\ + args[0] = asR_W65_ABS8;\ + print_operand (0, " #$0", args);\ + size += 1;\ + break;\ + case ADDR_IMMTOI:\ + args[0] = X==0 ? asR_W65_ABS16 : asR_W65_ABS8;\ + print_operand (0, " #$0", args);\ + size += X==0 ? 2:1;\ + break;\ + case ADDR_ACC:\ + print_operand (0, " a", 0);\ + size += 0;\ + break;\ + case ADDR_PC_REL:\ + args[0] = asR_W65_PCR8;\ + print_operand (0, " $0", args);\ + size += 1;\ + break;\ + case ADDR_PC_REL_LONG:\ + args[0] = asR_W65_PCR16;\ + print_operand (0, " $0", args);\ + size += 2;\ + break;\ + case ADDR_IMPLIED:\ + size += 0;\ + break;\ + case ADDR_STACK:\ + size += 0;\ + break;\ + case ADDR_DIR:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " <$0", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IDX_X:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " <$0,x", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IDX_Y:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " <$0,y", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " (<$0)", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IDX_IND_X:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " (<$0,x)", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND_IDX_Y:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " (<$0),y", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND_LONG:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " [$0]", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND_IDX_Y_LONG:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " [$0],y", args);\ + size += 1;\ + break;\ + case ADDR_ABS:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " !$0", args);\ + size += 2;\ + break;\ + case ADDR_ABS_IDX_X:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " !$0,x", args);\ + size += 2;\ + break;\ + case ADDR_ABS_IDX_Y:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " !$0,y", args);\ + size += 2;\ + break;\ + case ADDR_ABS_LONG:\ + args[0] = asR_W65_ABS24;\ + print_operand (1, " >$0", args);\ + size += 3;\ + break;\ + case ADDR_ABS_IND_LONG:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " [>$0]", args);\ + size += 2;\ + break;\ + case ADDR_ABS_LONG_IDX_X:\ + args[0] = asR_W65_ABS24;\ + print_operand (1, " >$0,x", args);\ + size += 3;\ + break;\ + case ADDR_STACK_REL:\ + args[0] = asR_W65_ABS8;\ + print_operand (0, " $0,s", args);\ + size += 1;\ + break;\ + case ADDR_STACK_REL_INDX_IDX:\ + args[0] = asR_W65_ABS8;\ + print_operand (0, " ($0,s),y", args);\ + size += 1;\ + break;\ + case ADDR_ABS_IND:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " ($0)", args);\ + size += 2;\ + break;\ + case ADDR_ABS_IND_IDX:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " ($0,x)", args);\ + size += 2;\ + break;\ + case ADDR_BLOCK_MOVE:\ + args[0] = (asR_W65_ABS16 >>8) &0xff;\ + args[1] = ( asR_W65_ABS16 & 0xff);\ + print_operand (0," $0,$1",args);\ + size += 2;\ + break;\ + +#define GETINFO(size,type,pcrel)\ + case ADDR_IMMTOA: size = M==0 ? 2:1;type=M==0 ? R_W65_ABS16 : R_W65_ABS8;pcrel=0;break;\ + case ADDR_IMMCOP: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_IMMTOI: size = X==0 ? 2:1;type=X==0 ? R_W65_ABS16 : R_W65_ABS8;pcrel=0;break;\ + case ADDR_ACC: size = 0;type=-1;pcrel=0;break;\ + case ADDR_PC_REL: size = 1;type=R_W65_PCR8;pcrel=0;break;\ + case ADDR_PC_REL_LONG: size = 2;type=R_W65_PCR16;pcrel=0;break;\ + case ADDR_IMPLIED: size = 0;type=-1;pcrel=0;break;\ + case ADDR_STACK: size = 0;type=-1;pcrel=0;break;\ + case ADDR_DIR: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IDX_X: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IDX_Y: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IDX_IND_X: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND_IDX_Y: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND_LONG: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND_IDX_Y_LONG: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_ABS: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_IDX_X: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_IDX_Y: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_LONG: size = 3;type=R_W65_ABS24;pcrel=0;break;\ + case ADDR_ABS_IND_LONG: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_LONG_IDX_X: size = 3;type=R_W65_ABS24;pcrel=0;break;\ + case ADDR_STACK_REL: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_STACK_REL_INDX_IDX: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_ABS_IND: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_IND_IDX: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_BLOCK_MOVE: size = 2;type=-1;pcrel=0;break;\ + diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c new file mode 100644 index 0000000..047339d --- /dev/null +++ b/opcodes/xstormy16-asm.c @@ -0,0 +1,659 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * parse_mem8 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_small_immediate + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); + +/* The machine-independent code doesn't know how to disambiguate + mov (foo),r3 + and + mov (r2),r3 + where 'foo' is a label. This helps it out. */ + +static const char * +parse_mem8 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + if (**strp == '(') + { + const char *s = *strp; + + if (s[1] == '-' && s[2] == '-') + return _("Bad register in preincrement"); + + while (isalnum (*++s)) + ; + if (s[0] == '+' && s[1] == '+' && (s[2] == ')' || s[2] == ',')) + return _("Bad register in postincrement"); + if (s[0] == ',' || s[0] == ')') + return _("Bad register name"); + } + else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, + valuep) == NULL) + return _("Label conflicts with register name"); + else if (strncasecmp (*strp, "rx,", 3) == 0 + || strncasecmp (*strp, "rxl,", 3) == 0 + || strncasecmp (*strp, "rxh,", 3) == 0) + return _("Label conflicts with `Rx'"); + else if (**strp == '#') + return _("Bad immediate expression"); + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* For the add and subtract instructions, there are two immediate forms, + one for small operands and one for large ones. We want to use + the small one when possible, but we do not want to generate relocs + of the small size. This is somewhat tricky. */ + +static const char * +parse_small_immediate (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + bfd_vma value; + enum cgen_parse_operand_result result; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, + &result, &value); + + if (errmsg) + return errmsg; + + if (result != CGEN_PARSE_OPERAND_RESULT_NUMBER) + return _("Small operand was not an immediate number"); + + *valuep = value; + return NULL; +} +/* -- */ + +const char * xstormy16_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +xstormy16_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_Rb_names, & fields->f_Rb); + break; + case XSTORMY16_OPERAND_RBJ : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_Rb_names, & fields->f_Rbj); + break; + case XSTORMY16_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rd); + break; + case XSTORMY16_OPERAND_RDM : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rdm); + break; + case XSTORMY16_OPERAND_RM : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rm); + break; + case XSTORMY16_OPERAND_RS : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rs); + break; + case XSTORMY16_OPERAND_ABS24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_ABS24, &fields->f_abs24); + break; + case XSTORMY16_OPERAND_BCOND2 : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_branchcond, & fields->f_op2); + break; + case XSTORMY16_OPERAND_BCOND5 : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_branchcond, & fields->f_op5); + break; + case XSTORMY16_OPERAND_HMEM8 : + errmsg = parse_mem8 (cd, strp, XSTORMY16_OPERAND_HMEM8, &fields->f_hmem8); + break; + case XSTORMY16_OPERAND_IMM12 : + errmsg = cgen_parse_signed_integer (cd, strp, XSTORMY16_OPERAND_IMM12, &fields->f_imm12); + break; + case XSTORMY16_OPERAND_IMM16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM16, &fields->f_imm16); + break; + case XSTORMY16_OPERAND_IMM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM2, &fields->f_imm2); + break; + case XSTORMY16_OPERAND_IMM3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM3, &fields->f_imm3); + break; + case XSTORMY16_OPERAND_IMM3B : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM3B, &fields->f_imm3b); + break; + case XSTORMY16_OPERAND_IMM4 : + errmsg = parse_small_immediate (cd, strp, XSTORMY16_OPERAND_IMM4, &fields->f_imm4); + break; + case XSTORMY16_OPERAND_IMM8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM8, &fields->f_imm8); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + errmsg = parse_small_immediate (cd, strp, XSTORMY16_OPERAND_IMM8SMALL, &fields->f_imm8); + break; + case XSTORMY16_OPERAND_LMEM8 : + errmsg = parse_mem8 (cd, strp, XSTORMY16_OPERAND_LMEM8, &fields->f_lmem8); + break; + case XSTORMY16_OPERAND_REL12 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL12, &fields->f_rel12); + break; + case XSTORMY16_OPERAND_REL12A : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL12A, &fields->f_rel12a); + break; + case XSTORMY16_OPERAND_REL8_2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL8_2, &fields->f_rel8_2); + break; + case XSTORMY16_OPERAND_REL8_4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL8_4, &fields->f_rel8_4); + break; + case XSTORMY16_OPERAND_WS2 : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_wordsize, & fields->f_op2m); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const xstormy16_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +xstormy16_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + xstormy16_cgen_init_opcode_table (cd); + xstormy16_cgen_init_ibld_table (cd); + cd->parse_handlers = & xstormy16_cgen_parse_handlers[0]; + cd->parse_operand = xstormy16_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by xstormy16_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +xstormy16_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +xstormy16_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! xstormy16_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +xstormy16_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! xstormy16_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c new file mode 100644 index 0000000..0c50625 --- /dev/null +++ b/opcodes/xstormy16-desc.c @@ -0,0 +1,1500 @@ +/* CPU data for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "xstormy16", MACH_XSTORMY16 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "xstormy16", ISA_XSTORMY16 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA xstormy16_cgen_isa_table[] = { + { "xstormy16", 32, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH xstormy16_cgen_mach_table[] = { + { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 }, + { "psw", 14, {0, {0}}, 0, 0 }, + { "sp", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_gr_names = +{ + & xstormy16_cgen_opval_gr_names_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] = +{ + { "r8", 0, {0, {0}}, 0, 0 }, + { "r9", 1, {0, {0}}, 0, 0 }, + { "r10", 2, {0, {0}}, 0, 0 }, + { "r11", 3, {0, {0}}, 0, 0 }, + { "r12", 4, {0, {0}}, 0, 0 }, + { "r13", 5, {0, {0}}, 0, 0 }, + { "r14", 6, {0, {0}}, 0, 0 }, + { "r15", 7, {0, {0}}, 0, 0 }, + { "psw", 6, {0, {0}}, 0, 0 }, + { "sp", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names = +{ + & xstormy16_cgen_opval_gr_Rb_names_entries[0], + 10, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] = +{ + { "ge", 0, {0, {0}}, 0, 0 }, + { "nc", 1, {0, {0}}, 0, 0 }, + { "lt", 2, {0, {0}}, 0, 0 }, + { "c", 3, {0, {0}}, 0, 0 }, + { "gt", 4, {0, {0}}, 0, 0 }, + { "hi", 5, {0, {0}}, 0, 0 }, + { "le", 6, {0, {0}}, 0, 0 }, + { "ls", 7, {0, {0}}, 0, 0 }, + { "pl", 8, {0, {0}}, 0, 0 }, + { "nv", 9, {0, {0}}, 0, 0 }, + { "mi", 10, {0, {0}}, 0, 0 }, + { "v", 11, {0, {0}}, 0, 0 }, + { "nz.b", 12, {0, {0}}, 0, 0 }, + { "nz", 13, {0, {0}}, 0, 0 }, + { "z.b", 14, {0, {0}}, 0, 0 }, + { "z", 15, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond = +{ + & xstormy16_cgen_opval_h_branchcond_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] = +{ + { ".b", 0, {0, {0}}, 0, 0 }, + { ".w", 1, {0, {0}}, 0, 0 }, + { "", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize = +{ + & xstormy16_cgen_opval_h_wordsize_entries[0], + 3, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & xstormy16_cgen_ifld_table[0]; +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */ + +static void +xstormy16_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = xstormy16_cgen_rebuild_tables; + xstormy16_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +xstormy16_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +xstormy16_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h new file mode 100644 index 0000000..fe18a13 --- /dev/null +++ b/opcodes/xstormy16-desc.h @@ -0,0 +1,292 @@ +/* CPU data header for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef XSTORMY16_CPU_H +#define XSTORMY16_CPU_H + +#define CGEN_ARCH xstormy16 + +/* Given symbol S, return xstormy16_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) xstormy16##_cgen_##s +#else +#define CGEN_SYM(s) xstormy16/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_XSTORMY16 + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 + +/* Enums. */ + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 + , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 + , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 + , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 + , H_GR_PSW = 14, H_GR_SP = 15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum gr_rb_names { + H_RBJ_R8 = 0, H_RBJ_R9 = 1, H_RBJ_R10 = 2, H_RBJ_R11 = 3 + , H_RBJ_R12 = 4, H_RBJ_R13 = 5, H_RBJ_R14 = 6, H_RBJ_R15 = 7 + , H_RBJ_PSW = 6, H_RBJ_SP = 7 +} GR_RB_NAMES; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_A, OP1_B + , OP1_C, OP1_D, OP1_E, OP1_F +} INSN_OP1; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_A, OP2_B + , OP2_C, OP2_D, OP2_E, OP2_F +} INSN_OP2; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op2a { + OP2A_0, OP2A_2, OP2A_4, OP2A_6 + , OP2A_8, OP2A_A, OP2A_C, OP2A_E +} INSN_OP2A; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op2m { + OP2M_0, OP2M_1 +} INSN_OP2M; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op3 { + OP3_0, OP3_1, OP3_2, OP3_3 + , OP3_4, OP3_5, OP3_6, OP3_7 + , OP3_8, OP3_9, OP3_A, OP3_B + , OP3_C, OP3_D, OP3_E, OP3_F +} INSN_OP3; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op3a { + OP3A_0, OP3A_1, OP3A_2, OP3A_3 +} INSN_OP3A; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op3b { + OP3B_0, OP3B_2, OP3B_4, OP3B_6 + , OP3B_8, OP3B_A, OP3B_C, OP3B_E +} INSN_OP3B; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op4 { + OP4_0, OP4_1, OP4_2, OP4_3 + , OP4_4, OP4_5, OP4_6, OP4_7 + , OP4_8, OP4_9, OP4_A, OP4_B + , OP4_C, OP4_D, OP4_E, OP4_F +} INSN_OP4; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op4m { + OP4M_0, OP4M_1 +} INSN_OP4M; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op4b { + OP4B_0, OP4B_1 +} INSN_OP4B; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op5 { + OP5_0, OP5_1, OP5_2, OP5_3 + , OP5_4, OP5_5, OP5_6, OP5_7 + , OP5_8, OP5_9, OP5_A, OP5_B + , OP5_C, OP5_D, OP5_E, OP5_F +} INSN_OP5; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op5a { + OP5A_0, OP5A_1 +} INSN_OP5A; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_XSTORMY16, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_XSTORMY16, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld xstormy16_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for xstormy16 ifield types. */ +typedef enum ifield_type { + XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM + , XSTORMY16_F_RM, XSTORMY16_F_RS, XSTORMY16_F_RB, XSTORMY16_F_RBJ + , XSTORMY16_F_OP1, XSTORMY16_F_OP2, XSTORMY16_F_OP2A, XSTORMY16_F_OP2M + , XSTORMY16_F_OP3, XSTORMY16_F_OP3A, XSTORMY16_F_OP3B, XSTORMY16_F_OP4 + , XSTORMY16_F_OP4M, XSTORMY16_F_OP4B, XSTORMY16_F_OP5, XSTORMY16_F_OP5A + , XSTORMY16_F_OP, XSTORMY16_F_IMM2, XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B + , XSTORMY16_F_IMM4, XSTORMY16_F_IMM8, XSTORMY16_F_IMM12, XSTORMY16_F_IMM16 + , XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8, XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4 + , XSTORMY16_F_REL12, XSTORMY16_F_REL12A, XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2 + , XSTORMY16_F_ABS24, XSTORMY16_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) XSTORMY16_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for xstormy16 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RB + , HW_H_RBJ, HW_H_RPSW, HW_H_Z8, HW_H_Z16 + , HW_H_CY, HW_H_HC, HW_H_OV, HW_H_PT + , HW_H_S, HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for xstormy16 operand types. */ +typedef enum cgen_operand_type { + XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY + , XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV, XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S + , XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM, XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS + , XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ, XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2 + , XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2, XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B + , XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8, XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12 + , XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8, XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2 + , XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12, XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24 + , XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW, XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0 + , XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2, XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 39 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD xstormy16_cgen_opval_gr_names; +extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names; +extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names; +extern CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond; +extern CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize; + + + + +#endif /* XSTORMY16_CPU_H */ diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c new file mode 100644 index 0000000..f3cc8e6 --- /dev/null +++ b/opcodes/xstormy16-dis.c @@ -0,0 +1,598 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + + +void xstormy16_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0); + break; + case XSTORMY16_OPERAND_RBJ : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0); + break; + case XSTORMY16_OPERAND_RD : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0); + break; + case XSTORMY16_OPERAND_RDM : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0); + break; + case XSTORMY16_OPERAND_RM : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0); + break; + case XSTORMY16_OPERAND_RS : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0); + break; + case XSTORMY16_OPERAND_ABS24 : + print_normal (cd, info, fields->f_abs24, 0|(1<f_op2, 0); + break; + case XSTORMY16_OPERAND_BCOND5 : + print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0); + break; + case XSTORMY16_OPERAND_HMEM8 : + print_normal (cd, info, fields->f_hmem8, 0|(1<f_imm12, 0|(1<f_imm16, 0|(1<f_imm2, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM3 : + print_normal (cd, info, fields->f_imm3, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM3B : + print_normal (cd, info, fields->f_imm3b, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM4 : + print_normal (cd, info, fields->f_imm4, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM8 : + print_normal (cd, info, fields->f_imm8, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + print_normal (cd, info, fields->f_imm8, 0, pc, length); + break; + case XSTORMY16_OPERAND_LMEM8 : + print_normal (cd, info, fields->f_lmem8, 0|(1<f_rel12, 0|(1<f_rel12a, 0|(1<f_rel8_2, 0|(1<f_rel8_4, 0|(1<f_op2m, 0); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const xstormy16_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +xstormy16_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + xstormy16_cgen_init_opcode_table (cd); + xstormy16_cgen_init_ibld_table (cd); + cd->print_handlers = & xstormy16_cgen_print_handlers[0]; + cd->print_operand = xstormy16_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! xstormy16_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_xstormy16 (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_xstormy16 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + xstormy16_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/xstormy16-ibld.c b/opcodes/xstormy16-ibld.c new file mode 100644 index 0000000..0e4876a --- /dev/null +++ b/opcodes/xstormy16-ibld.c @@ -0,0 +1,1246 @@ +/* Instruction building/extraction support for xstormy16. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * xstormy16_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +xstormy16_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + errmsg = insert_normal (cd, fields->f_Rb, 0, 0, 17, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RBJ : + errmsg = insert_normal (cd, fields->f_Rbj, 0, 0, 11, 1, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RD : + errmsg = insert_normal (cd, fields->f_Rd, 0, 0, 12, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RDM : + errmsg = insert_normal (cd, fields->f_Rdm, 0, 0, 13, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RM : + errmsg = insert_normal (cd, fields->f_Rm, 0, 0, 4, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RS : + errmsg = insert_normal (cd, fields->f_Rs, 0, 0, 8, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_ABS24 : + { +{ + FLD (f_abs24_1) = ((FLD (f_abs24)) & (255)); + FLD (f_abs24_2) = ((unsigned int) (FLD (f_abs24)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_abs24_1, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_abs24_2, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case XSTORMY16_OPERAND_BCOND2 : + errmsg = insert_normal (cd, fields->f_op2, 0, 0, 4, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_BCOND5 : + errmsg = insert_normal (cd, fields->f_op5, 0, 0, 16, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_HMEM8 : + { + long value = fields->f_hmem8; + value = ((value) - (32512)); + errmsg = insert_normal (cd, value, 0|(1<f_imm12, 0|(1<f_imm16, 0|(1<f_imm2, 0, 0, 10, 2, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM3 : + errmsg = insert_normal (cd, fields->f_imm3, 0, 0, 4, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM3B : + errmsg = insert_normal (cd, fields->f_imm3b, 0, 0, 17, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM4 : + errmsg = insert_normal (cd, fields->f_imm4, 0, 0, 8, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM8 : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_LMEM8 : + errmsg = insert_normal (cd, fields->f_lmem8, 0|(1<f_rel12; + value = ((value) - (((pc) + (4)))); + errmsg = insert_normal (cd, value, 0|(1<f_rel12a; + value = ((int) (((value) - (((pc) + (2))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_rel8_2; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_rel8_4; + value = ((value) - (((pc) + (4)))); + errmsg = insert_normal (cd, value, 0|(1<f_op2m, 0, 0, 7, 1, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int xstormy16_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +xstormy16_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_Rb); + break; + case XSTORMY16_OPERAND_RBJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_Rbj); + break; + case XSTORMY16_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_Rd); + break; + case XSTORMY16_OPERAND_RDM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_Rdm); + break; + case XSTORMY16_OPERAND_RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_Rm); + break; + case XSTORMY16_OPERAND_RS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_Rs); + break; + case XSTORMY16_OPERAND_ABS24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_abs24_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_abs24_2); + if (length <= 0) break; + FLD (f_abs24) = ((((FLD (f_abs24_2)) << (8))) | (FLD (f_abs24_1))); + } + break; + case XSTORMY16_OPERAND_BCOND2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_op2); + break; + case XSTORMY16_OPERAND_BCOND5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 4, 32, total_length, pc, & fields->f_op5); + break; + case XSTORMY16_OPERAND_HMEM8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_hmem8 = value; + } + break; + case XSTORMY16_OPERAND_IMM12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm12); + break; + case XSTORMY16_OPERAND_IMM16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16); + break; + case XSTORMY16_OPERAND_IMM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_imm2); + break; + case XSTORMY16_OPERAND_IMM3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_imm3); + break; + case XSTORMY16_OPERAND_IMM3B : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_imm3b); + break; + case XSTORMY16_OPERAND_IMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_imm4); + break; + case XSTORMY16_OPERAND_IMM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_imm8); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_imm8); + break; + case XSTORMY16_OPERAND_LMEM8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lmem8); + break; + case XSTORMY16_OPERAND_REL12 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel12 = value; + } + break; + case XSTORMY16_OPERAND_REL12A : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel12a = value; + } + break; + case XSTORMY16_OPERAND_REL8_2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel8_2 = value; + } + break; + case XSTORMY16_OPERAND_REL8_4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel8_4 = value; + } + break; + case XSTORMY16_OPERAND_WS2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_op2m); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const xstormy16_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const xstormy16_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int xstormy16_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma xstormy16_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +xstormy16_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + value = fields->f_Rb; + break; + case XSTORMY16_OPERAND_RBJ : + value = fields->f_Rbj; + break; + case XSTORMY16_OPERAND_RD : + value = fields->f_Rd; + break; + case XSTORMY16_OPERAND_RDM : + value = fields->f_Rdm; + break; + case XSTORMY16_OPERAND_RM : + value = fields->f_Rm; + break; + case XSTORMY16_OPERAND_RS : + value = fields->f_Rs; + break; + case XSTORMY16_OPERAND_ABS24 : + value = fields->f_abs24; + break; + case XSTORMY16_OPERAND_BCOND2 : + value = fields->f_op2; + break; + case XSTORMY16_OPERAND_BCOND5 : + value = fields->f_op5; + break; + case XSTORMY16_OPERAND_HMEM8 : + value = fields->f_hmem8; + break; + case XSTORMY16_OPERAND_IMM12 : + value = fields->f_imm12; + break; + case XSTORMY16_OPERAND_IMM16 : + value = fields->f_imm16; + break; + case XSTORMY16_OPERAND_IMM2 : + value = fields->f_imm2; + break; + case XSTORMY16_OPERAND_IMM3 : + value = fields->f_imm3; + break; + case XSTORMY16_OPERAND_IMM3B : + value = fields->f_imm3b; + break; + case XSTORMY16_OPERAND_IMM4 : + value = fields->f_imm4; + break; + case XSTORMY16_OPERAND_IMM8 : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_LMEM8 : + value = fields->f_lmem8; + break; + case XSTORMY16_OPERAND_REL12 : + value = fields->f_rel12; + break; + case XSTORMY16_OPERAND_REL12A : + value = fields->f_rel12a; + break; + case XSTORMY16_OPERAND_REL8_2 : + value = fields->f_rel8_2; + break; + case XSTORMY16_OPERAND_REL8_4 : + value = fields->f_rel8_4; + break; + case XSTORMY16_OPERAND_WS2 : + value = fields->f_op2m; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +xstormy16_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + value = fields->f_Rb; + break; + case XSTORMY16_OPERAND_RBJ : + value = fields->f_Rbj; + break; + case XSTORMY16_OPERAND_RD : + value = fields->f_Rd; + break; + case XSTORMY16_OPERAND_RDM : + value = fields->f_Rdm; + break; + case XSTORMY16_OPERAND_RM : + value = fields->f_Rm; + break; + case XSTORMY16_OPERAND_RS : + value = fields->f_Rs; + break; + case XSTORMY16_OPERAND_ABS24 : + value = fields->f_abs24; + break; + case XSTORMY16_OPERAND_BCOND2 : + value = fields->f_op2; + break; + case XSTORMY16_OPERAND_BCOND5 : + value = fields->f_op5; + break; + case XSTORMY16_OPERAND_HMEM8 : + value = fields->f_hmem8; + break; + case XSTORMY16_OPERAND_IMM12 : + value = fields->f_imm12; + break; + case XSTORMY16_OPERAND_IMM16 : + value = fields->f_imm16; + break; + case XSTORMY16_OPERAND_IMM2 : + value = fields->f_imm2; + break; + case XSTORMY16_OPERAND_IMM3 : + value = fields->f_imm3; + break; + case XSTORMY16_OPERAND_IMM3B : + value = fields->f_imm3b; + break; + case XSTORMY16_OPERAND_IMM4 : + value = fields->f_imm4; + break; + case XSTORMY16_OPERAND_IMM8 : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_LMEM8 : + value = fields->f_lmem8; + break; + case XSTORMY16_OPERAND_REL12 : + value = fields->f_rel12; + break; + case XSTORMY16_OPERAND_REL12A : + value = fields->f_rel12a; + break; + case XSTORMY16_OPERAND_REL8_2 : + value = fields->f_rel8_2; + break; + case XSTORMY16_OPERAND_REL8_4 : + value = fields->f_rel8_4; + break; + case XSTORMY16_OPERAND_WS2 : + value = fields->f_op2m; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void xstormy16_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void xstormy16_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +xstormy16_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + fields->f_Rb = value; + break; + case XSTORMY16_OPERAND_RBJ : + fields->f_Rbj = value; + break; + case XSTORMY16_OPERAND_RD : + fields->f_Rd = value; + break; + case XSTORMY16_OPERAND_RDM : + fields->f_Rdm = value; + break; + case XSTORMY16_OPERAND_RM : + fields->f_Rm = value; + break; + case XSTORMY16_OPERAND_RS : + fields->f_Rs = value; + break; + case XSTORMY16_OPERAND_ABS24 : + fields->f_abs24 = value; + break; + case XSTORMY16_OPERAND_BCOND2 : + fields->f_op2 = value; + break; + case XSTORMY16_OPERAND_BCOND5 : + fields->f_op5 = value; + break; + case XSTORMY16_OPERAND_HMEM8 : + fields->f_hmem8 = value; + break; + case XSTORMY16_OPERAND_IMM12 : + fields->f_imm12 = value; + break; + case XSTORMY16_OPERAND_IMM16 : + fields->f_imm16 = value; + break; + case XSTORMY16_OPERAND_IMM2 : + fields->f_imm2 = value; + break; + case XSTORMY16_OPERAND_IMM3 : + fields->f_imm3 = value; + break; + case XSTORMY16_OPERAND_IMM3B : + fields->f_imm3b = value; + break; + case XSTORMY16_OPERAND_IMM4 : + fields->f_imm4 = value; + break; + case XSTORMY16_OPERAND_IMM8 : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_LMEM8 : + fields->f_lmem8 = value; + break; + case XSTORMY16_OPERAND_REL12 : + fields->f_rel12 = value; + break; + case XSTORMY16_OPERAND_REL12A : + fields->f_rel12a = value; + break; + case XSTORMY16_OPERAND_REL8_2 : + fields->f_rel8_2 = value; + break; + case XSTORMY16_OPERAND_REL8_4 : + fields->f_rel8_4 = value; + break; + case XSTORMY16_OPERAND_WS2 : + fields->f_op2m = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +xstormy16_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + fields->f_Rb = value; + break; + case XSTORMY16_OPERAND_RBJ : + fields->f_Rbj = value; + break; + case XSTORMY16_OPERAND_RD : + fields->f_Rd = value; + break; + case XSTORMY16_OPERAND_RDM : + fields->f_Rdm = value; + break; + case XSTORMY16_OPERAND_RM : + fields->f_Rm = value; + break; + case XSTORMY16_OPERAND_RS : + fields->f_Rs = value; + break; + case XSTORMY16_OPERAND_ABS24 : + fields->f_abs24 = value; + break; + case XSTORMY16_OPERAND_BCOND2 : + fields->f_op2 = value; + break; + case XSTORMY16_OPERAND_BCOND5 : + fields->f_op5 = value; + break; + case XSTORMY16_OPERAND_HMEM8 : + fields->f_hmem8 = value; + break; + case XSTORMY16_OPERAND_IMM12 : + fields->f_imm12 = value; + break; + case XSTORMY16_OPERAND_IMM16 : + fields->f_imm16 = value; + break; + case XSTORMY16_OPERAND_IMM2 : + fields->f_imm2 = value; + break; + case XSTORMY16_OPERAND_IMM3 : + fields->f_imm3 = value; + break; + case XSTORMY16_OPERAND_IMM3B : + fields->f_imm3b = value; + break; + case XSTORMY16_OPERAND_IMM4 : + fields->f_imm4 = value; + break; + case XSTORMY16_OPERAND_IMM8 : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_LMEM8 : + fields->f_lmem8 = value; + break; + case XSTORMY16_OPERAND_REL12 : + fields->f_rel12 = value; + break; + case XSTORMY16_OPERAND_REL12A : + fields->f_rel12a = value; + break; + case XSTORMY16_OPERAND_REL8_2 : + fields->f_rel8_2 = value; + break; + case XSTORMY16_OPERAND_REL8_4 : + fields->f_rel8_4 = value; + break; + case XSTORMY16_OPERAND_WS2 : + fields->f_op2m = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +xstormy16_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & xstormy16_cgen_insert_handlers[0]; + cd->extract_handlers = & xstormy16_cgen_extract_handlers[0]; + + cd->insert_operand = xstormy16_cgen_insert_operand; + cd->extract_operand = xstormy16_cgen_extract_operand; + + cd->get_int_operand = xstormy16_cgen_get_int_operand; + cd->set_int_operand = xstormy16_cgen_set_int_operand; + cd->get_vma_operand = xstormy16_cgen_get_vma_operand; + cd->set_vma_operand = xstormy16_cgen_set_vma_operand; +} diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c new file mode 100644 index 0000000..8c6d7d3 --- /dev/null +++ b/opcodes/xstormy16-opc.c @@ -0,0 +1,1177 @@ +/* Instruction opcode table for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f] +#else +#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_movlmemimm = { + 32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_LMEM8) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhmemimm = { + 32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_HMEM8) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movlgrmem = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhgrmem = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrgri = { + 16, 16, 0xfe08, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrgrii = { + 32, 32, 0xfe08f000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5) }, { F (F_IMM12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrgr = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movwimm8 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movwgrimm8 = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movwgrimm16 = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movlowgr = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movfgrgrii = { + 32, 32, 0xfe088000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5A) }, { F (F_RB) }, { F (F_IMM12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addgrimm4 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_incgrimm2 = { + 16, 16, 0xffc0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_set1lmemimm = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_set1hmemimm = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bccgrgr = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bccgrimm8 = { + 32, 32, 0xf1000000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bccimm16 = { + 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_4) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bngrimm4 = { + 32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bngrgr = { + 32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnlmemimm = { + 32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_LMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnhmemimm = { + 32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_HMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcc = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_br = { + 16, 16, 0xf001, { { F (F_OP1) }, { F (F_REL12A) }, { F (F_OP4B) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp = { + 16, 16, 0xffe0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3B) }, { F (F_RBJ) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpf = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_ABS24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_iret = { + 16, 16, 0xffff, { { F (F_OP) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) XSTORMY16_OPERAND_##op +#else +#define OPERAND(op) XSTORMY16_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE xstormy16_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* mov$ws2 $lmem8,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', '#', OP (IMM16), 0 } }, + & ifmt_movlmemimm, { 0x78000000 } + }, +/* mov$ws2 $hmem8,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', '#', OP (IMM16), 0 } }, + & ifmt_movhmemimm, { 0x7a000000 } + }, +/* mov$ws2 $Rm,$lmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (LMEM8), 0 } }, + & ifmt_movlgrmem, { 0x8000 } + }, +/* mov$ws2 $Rm,$hmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (HMEM8), 0 } }, + & ifmt_movhgrmem, { 0xa000 } + }, +/* mov$ws2 $lmem8,$Rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', OP (RM), 0 } }, + & ifmt_movlgrmem, { 0x9000 } + }, +/* mov$ws2 $hmem8,$Rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', OP (RM), 0 } }, + & ifmt_movhgrmem, { 0xb000 } + }, +/* mov$ws2 $Rdm,($Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x7000 } + }, +/* mov$ws2 $Rdm,($Rs++) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } }, + & ifmt_movgrgri, { 0x6000 } + }, +/* mov$ws2 $Rdm,(--$Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x6800 } + }, +/* mov$ws2 ($Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x7200 } + }, +/* mov$ws2 ($Rs++),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6200 } + }, +/* mov$ws2 (--$Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6a00 } + }, +/* mov$ws2 $Rdm,($Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movgrgrii, { 0x70080000 } + }, +/* mov$ws2 $Rdm,($Rs++,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } }, + & ifmt_movgrgrii, { 0x60080000 } + }, +/* mov$ws2 $Rdm,(--$Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movgrgrii, { 0x68080000 } + }, +/* mov$ws2 ($Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgrii, { 0x72080000 } + }, +/* mov$ws2 ($Rs++,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgrii, { 0x62080000 } + }, +/* mov$ws2 (--$Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgrii, { 0x6a080000 } + }, +/* mov $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4600 } + }, +/* mov.w Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4700 } + }, +/* mov.w $Rm,#$imm8small */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), ',', '#', OP (IMM8SMALL), 0 } }, + & ifmt_movwgrimm8, { 0x2100 } + }, +/* mov.w $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31300000 } + }, +/* mov.b $Rd,RxL */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'L', 0 } }, + & ifmt_movlowgr, { 0x30c0 } + }, +/* mov.b $Rd,RxH */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'H', 0 } }, + & ifmt_movlowgr, { 0x30d0 } + }, +/* movf$ws2 $Rdm,($Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x7400 } + }, +/* movf$ws2 $Rdm,($Rs++) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } }, + & ifmt_movgrgri, { 0x6400 } + }, +/* movf$ws2 $Rdm,(--$Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x6c00 } + }, +/* movf$ws2 ($Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x7600 } + }, +/* movf$ws2 ($Rs++),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6600 } + }, +/* movf$ws2 (--$Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6e00 } + }, +/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movfgrgrii, { 0x74080000 } + }, +/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } }, + & ifmt_movfgrgrii, { 0x64080000 } + }, +/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movfgrgrii, { 0x6c080000 } + }, +/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movfgrgrii, { 0x76080000 } + }, +/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movfgrgrii, { 0x66080000 } + }, +/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movfgrgrii, { 0x6e080000 } + }, +/* mask $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3300 } + }, +/* mask $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x30e00000 } + }, +/* push $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x80 } + }, +/* pop $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x90 } + }, +/* swpn $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x3090 } + }, +/* swpb $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x3080 } + }, +/* swpw $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3200 } + }, +/* and $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4000 } + }, +/* and Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4100 } + }, +/* and $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31000000 } + }, +/* or $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4200 } + }, +/* or Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4300 } + }, +/* or $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31100000 } + }, +/* xor $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4400 } + }, +/* xor Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4500 } + }, +/* xor $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31200000 } + }, +/* not $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30b0 } + }, +/* add $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4900 } + }, +/* add $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5100 } + }, +/* add Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5900 } + }, +/* add $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31400000 } + }, +/* adc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4b00 } + }, +/* adc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5300 } + }, +/* adc Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5b00 } + }, +/* adc $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31500000 } + }, +/* sub $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4d00 } + }, +/* sub $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5500 } + }, +/* sub Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5d00 } + }, +/* sub $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31600000 } + }, +/* sbc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4f00 } + }, +/* sbc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5700 } + }, +/* sbc Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5f00 } + }, +/* sbc $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31700000 } + }, +/* inc $Rd,#$imm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } }, + & ifmt_incgrimm2, { 0x3000 } + }, +/* dec $Rd,#$imm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } }, + & ifmt_incgrimm2, { 0x3040 } + }, +/* rrc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3800 } + }, +/* rrc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3900 } + }, +/* rlc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3a00 } + }, +/* rlc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3b00 } + }, +/* shr $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3c00 } + }, +/* shr $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3d00 } + }, +/* shl $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3e00 } + }, +/* shl $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3f00 } + }, +/* asr $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3600 } + }, +/* asr $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3700 } + }, +/* set1 $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x900 } + }, +/* set1 $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0xb00 } + }, +/* set1 $lmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1lmemimm, { 0xe100 } + }, +/* set1 $hmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1hmemimm, { 0xf100 } + }, +/* clr1 $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x800 } + }, +/* clr1 $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0xa00 } + }, +/* clr1 $lmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1lmemimm, { 0xe000 } + }, +/* clr1 $hmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1hmemimm, { 0xf000 } + }, +/* cbw $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30a0 } + }, +/* rev $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30f0 } + }, +/* b$bcond5 $Rd,$Rs,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND5), ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } }, + & ifmt_bccgrgr, { 0xd000000 } + }, +/* b$bcond5 $Rm,#$imm8,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND5), ' ', OP (RM), ',', '#', OP (IMM8), ',', OP (REL12), 0 } }, + & ifmt_bccgrimm8, { 0x20000000 } + }, +/* b$bcond2 Rx,#$imm16,${rel8-4} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND2), ' ', 'R', 'x', ',', '#', OP (IMM16), ',', OP (REL8_4), 0 } }, + & ifmt_bccimm16, { 0xc0000000 } + }, +/* bn $Rd,#$imm4,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } }, + & ifmt_bngrimm4, { 0x4000000 } + }, +/* bn $Rd,$Rs,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } }, + & ifmt_bngrgr, { 0x6000000 } + }, +/* bn $lmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnlmemimm, { 0x7c000000 } + }, +/* bn $hmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnhmemimm, { 0x7e000000 } + }, +/* bp $Rd,#$imm4,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } }, + & ifmt_bngrimm4, { 0x5000000 } + }, +/* bp $Rd,$Rs,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } }, + & ifmt_bngrgr, { 0x7000000 } + }, +/* bp $lmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnlmemimm, { 0x7d000000 } + }, +/* bp $hmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnhmemimm, { 0x7f000000 } + }, +/* b$bcond2 ${rel8-2} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND2), ' ', OP (REL8_2), 0 } }, + & ifmt_bcc, { 0xd000 } + }, +/* br $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x20 } + }, +/* br $rel12a */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REL12A), 0 } }, + & ifmt_br, { 0x1000 } + }, +/* jmp $Rbj,$Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } }, + & ifmt_jmp, { 0x40 } + }, +/* jmpf $abs24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS24), 0 } }, + & ifmt_jmpf, { 0x2000000 } + }, +/* callr $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x10 } + }, +/* callr $rel12a */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REL12A), 0 } }, + & ifmt_br, { 0x1001 } + }, +/* call $Rbj,$Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } }, + & ifmt_jmp, { 0xa0 } + }, +/* callf $abs24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS24), 0 } }, + & ifmt_jmpf, { 0x1000000 } + }, +/* icallr $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30 } + }, +/* icall $Rbj,$Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } }, + & ifmt_jmp, { 0x60 } + }, +/* icallf $abs24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS24), 0 } }, + & ifmt_jmpf, { 0x3000000 } + }, +/* iret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x2 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x3 } + }, +/* mul */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xd0 } + }, +/* div */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xc0 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x0 } + }, +/* halt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x8 } + }, +/* hold */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xa } + }, +/* holdx */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xb } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x5 } + }, +/* --unused-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x1 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f] +#else +#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_/**/f] +#endif +static const CGEN_IFMT ifmt_movimm8 = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrimm8 = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrimm16 = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_incgr = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_decgr = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) XSTORMY16_OPERAND_##op +#else +#define OPERAND(op) XSTORMY16_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] = +{ +/* mov Rx,#$imm8 */ + { + -1, "movimm8", "mov", 16, + { 0|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & xstormy16_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + xstormy16_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/xstormy16-opc.h b/opcodes/xstormy16-opc.h new file mode 100644 index 0000000..337afec --- /dev/null +++ b/opcodes/xstormy16-opc.h @@ -0,0 +1,137 @@ +/* Instruction opcode header for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef XSTORMY16_OPC_H +#define XSTORMY16_OPC_H + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* We can't use the default hash size because many bits are used by + operands. */ +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +/* -- */ +/* Enum declaration for xstormy16 instruction types. */ +typedef enum cgen_insn_type { + XSTORMY16_INSN_INVALID, XSTORMY16_INSN_MOVLMEMIMM, XSTORMY16_INSN_MOVHMEMIMM, XSTORMY16_INSN_MOVLGRMEM + , XSTORMY16_INSN_MOVHGRMEM, XSTORMY16_INSN_MOVLMEMGR, XSTORMY16_INSN_MOVHMEMGR, XSTORMY16_INSN_MOVGRGRI + , XSTORMY16_INSN_MOVGRGRIPOSTINC, XSTORMY16_INSN_MOVGRGRIPREDEC, XSTORMY16_INSN_MOVGRIGR, XSTORMY16_INSN_MOVGRIPOSTINCGR + , XSTORMY16_INSN_MOVGRIPREDECGR, XSTORMY16_INSN_MOVGRGRII, XSTORMY16_INSN_MOVGRGRIIPOSTINC, XSTORMY16_INSN_MOVGRGRIIPREDEC + , XSTORMY16_INSN_MOVGRIIGR, XSTORMY16_INSN_MOVGRIIPOSTINCGR, XSTORMY16_INSN_MOVGRIIPREDECGR, XSTORMY16_INSN_MOVGRGR + , XSTORMY16_INSN_MOVWIMM8, XSTORMY16_INSN_MOVWGRIMM8, XSTORMY16_INSN_MOVWGRIMM16, XSTORMY16_INSN_MOVLOWGR + , XSTORMY16_INSN_MOVHIGHGR, XSTORMY16_INSN_MOVFGRGRI, XSTORMY16_INSN_MOVFGRGRIPOSTINC, XSTORMY16_INSN_MOVFGRGRIPREDEC + , XSTORMY16_INSN_MOVFGRIGR, XSTORMY16_INSN_MOVFGRIPOSTINCGR, XSTORMY16_INSN_MOVFGRIPREDECGR, XSTORMY16_INSN_MOVFGRGRII + , XSTORMY16_INSN_MOVFGRGRIIPOSTINC, XSTORMY16_INSN_MOVFGRGRIIPREDEC, XSTORMY16_INSN_MOVFGRIIGR, XSTORMY16_INSN_MOVFGRIIPOSTINCGR + , XSTORMY16_INSN_MOVFGRIIPREDECGR, XSTORMY16_INSN_MASKGRGR, XSTORMY16_INSN_MASKGRIMM16, XSTORMY16_INSN_PUSHGR + , XSTORMY16_INSN_POPGR, XSTORMY16_INSN_SWPN, XSTORMY16_INSN_SWPB, XSTORMY16_INSN_SWPW + , XSTORMY16_INSN_ANDGRGR, XSTORMY16_INSN_ANDIMM8, XSTORMY16_INSN_ANDGRIMM16, XSTORMY16_INSN_ORGRGR + , XSTORMY16_INSN_ORIMM8, XSTORMY16_INSN_ORGRIMM16, XSTORMY16_INSN_XORGRGR, XSTORMY16_INSN_XORIMM8 + , XSTORMY16_INSN_XORGRIMM16, XSTORMY16_INSN_NOTGR, XSTORMY16_INSN_ADDGRGR, XSTORMY16_INSN_ADDGRIMM4 + , XSTORMY16_INSN_ADDIMM8, XSTORMY16_INSN_ADDGRIMM16, XSTORMY16_INSN_ADCGRGR, XSTORMY16_INSN_ADCGRIMM4 + , XSTORMY16_INSN_ADCIMM8, XSTORMY16_INSN_ADCGRIMM16, XSTORMY16_INSN_SUBGRGR, XSTORMY16_INSN_SUBGRIMM4 + , XSTORMY16_INSN_SUBIMM8, XSTORMY16_INSN_SUBGRIMM16, XSTORMY16_INSN_SBCGRGR, XSTORMY16_INSN_SBCGRIMM4 + , XSTORMY16_INSN_SBCGRIMM8, XSTORMY16_INSN_SBCGRIMM16, XSTORMY16_INSN_INCGRIMM2, XSTORMY16_INSN_DECGRIMM2 + , XSTORMY16_INSN_RRCGRGR, XSTORMY16_INSN_RRCGRIMM4, XSTORMY16_INSN_RLCGRGR, XSTORMY16_INSN_RLCGRIMM4 + , XSTORMY16_INSN_SHRGRGR, XSTORMY16_INSN_SHRGRIMM, XSTORMY16_INSN_SHLGRGR, XSTORMY16_INSN_SHLGRIMM + , XSTORMY16_INSN_ASRGRGR, XSTORMY16_INSN_ASRGRIMM, XSTORMY16_INSN_SET1GRIMM, XSTORMY16_INSN_SET1GRGR + , XSTORMY16_INSN_SET1LMEMIMM, XSTORMY16_INSN_SET1HMEMIMM, XSTORMY16_INSN_CLR1GRIMM, XSTORMY16_INSN_CLR1GRGR + , XSTORMY16_INSN_CLR1LMEMIMM, XSTORMY16_INSN_CLR1HMEMIMM, XSTORMY16_INSN_CBWGR, XSTORMY16_INSN_REVGR + , XSTORMY16_INSN_BCCGRGR, XSTORMY16_INSN_BCCGRIMM8, XSTORMY16_INSN_BCCIMM16, XSTORMY16_INSN_BNGRIMM4 + , XSTORMY16_INSN_BNGRGR, XSTORMY16_INSN_BNLMEMIMM, XSTORMY16_INSN_BNHMEMIMM, XSTORMY16_INSN_BPGRIMM4 + , XSTORMY16_INSN_BPGRGR, XSTORMY16_INSN_BPLMEMIMM, XSTORMY16_INSN_BPHMEMIMM, XSTORMY16_INSN_BCC + , XSTORMY16_INSN_BGR, XSTORMY16_INSN_BR, XSTORMY16_INSN_JMP, XSTORMY16_INSN_JMPF + , XSTORMY16_INSN_CALLRGR, XSTORMY16_INSN_CALLRIMM, XSTORMY16_INSN_CALLGR, XSTORMY16_INSN_CALLFIMM + , XSTORMY16_INSN_ICALLRGR, XSTORMY16_INSN_ICALLGR, XSTORMY16_INSN_ICALLFIMM, XSTORMY16_INSN_IRET + , XSTORMY16_INSN_RET, XSTORMY16_INSN_MUL, XSTORMY16_INSN_DIV, XSTORMY16_INSN_NOP + , XSTORMY16_INSN_HALT, XSTORMY16_INSN_HOLD, XSTORMY16_INSN_HOLDX, XSTORMY16_INSN_BRK + , XSTORMY16_INSN_SYSCALL +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID XSTORMY16_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) XSTORMY16_INSN_SYSCALL + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_Rd; + long f_Rdm; + long f_Rm; + long f_Rs; + long f_Rb; + long f_Rbj; + long f_op1; + long f_op2; + long f_op2a; + long f_op2m; + long f_op3; + long f_op3a; + long f_op3b; + long f_op4; + long f_op4m; + long f_op4b; + long f_op5; + long f_op5a; + long f_op; + long f_imm2; + long f_imm3; + long f_imm3b; + long f_imm4; + long f_imm8; + long f_imm12; + long f_imm16; + long f_lmem8; + long f_hmem8; + long f_rel8_2; + long f_rel8_4; + long f_rel12; + long f_rel12a; + long f_abs24_1; + long f_abs24_2; + long f_abs24; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* XSTORMY16_OPC_H */ diff --git a/opcodes/z8k-dis.c b/opcodes/z8k-dis.c new file mode 100644 index 0000000..d375e69 --- /dev/null +++ b/opcodes/z8k-dis.c @@ -0,0 +1,600 @@ +/* Disassemble z8000 code. + Copyright 1992, 1993, 1998, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +#include "sysdep.h" +#include "dis-asm.h" + +#define DEFINE_TABLE +#include "z8k-opc.h" + +#include + +typedef struct +{ + /* These are all indexed by nibble number (i.e only every other entry + of bytes is used, and every 4th entry of words). */ + unsigned char nibbles[24]; + unsigned char bytes[24]; + unsigned short words[24]; + + /* Nibble number of first word not yet fetched. */ + int max_fetched; + bfd_vma insn_start; + jmp_buf bailout; + + long tabl_index; + char instr_asmsrc[80]; + unsigned long arg_reg[0x0f]; + unsigned long immediate; + unsigned long displacement; + unsigned long address; + unsigned long cond_code; + unsigned long ctrl_code; + unsigned long flags; + unsigned long interrupts; +} +instr_data_s; + +static int fetch_data PARAMS ((struct disassemble_info *, int)); + + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, nibble) \ + ((nibble) < ((instr_data_s *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (nibble))) + +static int +fetch_data (info, nibble) + struct disassemble_info *info; + int nibble; +{ + unsigned char mybuf[20]; + int status; + instr_data_s *priv = (instr_data_s *) info->private_data; + + if ((nibble % 4) != 0) + abort (); + + status = (*info->read_memory_func) (priv->insn_start, + (bfd_byte *) mybuf, + nibble / 2, + info); + if (status != 0) + { + (*info->memory_error_func) (status, priv->insn_start, info); + longjmp (priv->bailout, 1); + } + + { + int i; + unsigned char *p = mybuf; + + for (i = 0; i < nibble;) + { + priv->words[i] = (p[0] << 8) | p[1]; + + priv->bytes[i] = *p; + priv->nibbles[i++] = *p >> 4; + priv->nibbles[i++] = *p & 0xf; + + ++p; + priv->bytes[i] = *p; + priv->nibbles[i++] = *p >> 4; + priv->nibbles[i++] = *p & 0xf; + + ++p; + } + } + priv->max_fetched = nibble; + return 1; +} + +static char *codes[16] = + { + "f", + "lt", + "le", + "ule", + "ov/pe", + "mi", + "eq", + "c/ult", + "t", + "ge", + "gt", + "ugt", + "nov/po", + "pl", + "ne", + "nc/uge" + }; + +static char *ctrl_names[8] = + { + "", + "flags", + "fcw", + "refresh", + "psapseg", + "psapoff", + "nspseg", + "nspoff" + }; + +static int seg_length; +static int print_insn_z8k PARAMS ((bfd_vma, disassemble_info *, int)); +int z8k_lookup_instr PARAMS ((unsigned char *, disassemble_info *)); +static void output_instr + PARAMS ((instr_data_s *, unsigned long, disassemble_info *)); +static void unpack_instr PARAMS ((instr_data_s *, int, disassemble_info *)); +static void unparse_instr PARAMS ((instr_data_s *, int)); + +static int +print_insn_z8k (addr, info, is_segmented) + bfd_vma addr; + disassemble_info *info; + int is_segmented; +{ + instr_data_s instr_data; + + info->private_data = (PTR) &instr_data; + instr_data.max_fetched = 0; + instr_data.insn_start = addr; + if (setjmp (instr_data.bailout) != 0) + /* Error return. */ + return -1; + + info->bytes_per_chunk = 2; + info->bytes_per_line = 6; + info->display_endian = BFD_ENDIAN_BIG; + + instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info); + if (instr_data.tabl_index > 0) + { + unpack_instr (&instr_data, is_segmented, info); + unparse_instr (&instr_data, is_segmented); + output_instr (&instr_data, addr, info); + return z8k_table[instr_data.tabl_index].length + seg_length; + } + else + { + FETCH_DATA (info, 4); + (*info->fprintf_func) (info->stream, ".word %02x%02x", + instr_data.bytes[0], instr_data.bytes[2]); + return 2; + } +} + +int +print_insn_z8001 (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + return print_insn_z8k (addr, info, 1); +} + +int +print_insn_z8002 (addr, info) + bfd_vma addr; + disassemble_info *info; +{ + return print_insn_z8k (addr, info, 0); +} + +int +z8k_lookup_instr (nibbles, info) + unsigned char *nibbles; + disassemble_info *info; +{ + + int nibl_index, tabl_index; + int nibl_matched; + unsigned short instr_nibl; + unsigned short tabl_datum, datum_class, datum_value; + + nibl_matched = 0; + tabl_index = 0; + while (!nibl_matched && z8k_table[tabl_index].name) + { + nibl_matched = 1; + for (nibl_index = 0; + nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched; + nibl_index++) + { + if ((nibl_index % 4) == 0) + /* Fetch one word at a time. */ + FETCH_DATA (info, nibl_index + 4); + instr_nibl = nibbles[nibl_index]; + + tabl_datum = z8k_table[tabl_index].byte_info[nibl_index]; + datum_class = tabl_datum & CLASS_MASK; + datum_value = ~CLASS_MASK & tabl_datum; + + switch (datum_class) + { + case CLASS_BIT: + if (datum_value != instr_nibl) + nibl_matched = 0; + break; + case CLASS_IGNORE: + break; + case CLASS_00II: + if (!((~instr_nibl) & 0x4)) + nibl_matched = 0; + break; + case CLASS_01II: + if (!(instr_nibl & 0x4)) + nibl_matched = 0; + break; + case CLASS_0CCC: + if (!((~instr_nibl) & 0x8)) + nibl_matched = 0; + break; + case CLASS_1CCC: + if (!(instr_nibl & 0x8)) + nibl_matched = 0; + break; + case CLASS_0DISP7: + if (!((~instr_nibl) & 0x8)) + nibl_matched = 0; + nibl_index += 1; + break; + case CLASS_1DISP7: + if (!(instr_nibl & 0x8)) + nibl_matched = 0; + nibl_index += 1; + break; + case CLASS_REGN0: + if (instr_nibl == 0) + nibl_matched = 0; + break; + case CLASS_BIT_1OR2: + if ((instr_nibl | 0x2) != (datum_value | 0x2)) + nibl_matched = 0; + break; + default: + break; + } + } + + if (nibl_matched) + return tabl_index; + + tabl_index++; + } + return -1; +} + +static void +output_instr (instr_data, addr, info) + instr_data_s *instr_data; + unsigned long addr ATTRIBUTE_UNUSED; + disassemble_info *info; +{ + int num_bytes; + char out_str[100]; + + out_str[0] = 0; + + num_bytes = (z8k_table[instr_data->tabl_index].length + seg_length) * 2; + FETCH_DATA (info, num_bytes); + + strcat (out_str, instr_data->instr_asmsrc); + + (*info->fprintf_func) (info->stream, "%s", out_str); +} + +static void +unpack_instr (instr_data, is_segmented, info) + instr_data_s *instr_data; + int is_segmented; + disassemble_info *info; +{ + int nibl_count, loop; + unsigned short instr_nibl, instr_byte, instr_word; + long instr_long; + unsigned int tabl_datum, datum_class; + unsigned short datum_value; + + nibl_count = 0; + loop = 0; + seg_length = 0; + + while (z8k_table[instr_data->tabl_index].byte_info[loop] != 0) + { + FETCH_DATA (info, nibl_count + 4 - (nibl_count % 4)); + instr_nibl = instr_data->nibbles[nibl_count]; + instr_byte = instr_data->bytes[nibl_count & ~1]; + instr_word = instr_data->words[nibl_count & ~3]; + + tabl_datum = z8k_table[instr_data->tabl_index].byte_info[loop]; + datum_class = tabl_datum & CLASS_MASK; + datum_value = tabl_datum & ~CLASS_MASK; + + switch (datum_class) + { + case CLASS_DISP: + switch (datum_value) + { + case ARG_DISP16: + instr_data->displacement = instr_data->insn_start + 4 + + (signed short) (instr_word & 0xffff); + nibl_count += 3; + break; + case ARG_DISP12: + if (instr_word & 0x800) + /* Negative 12 bit displacement. */ + instr_data->displacement = instr_data->insn_start + 2 + - (signed short) ((instr_word & 0xfff) | 0xf000) * 2; + else + instr_data->displacement = instr_data->insn_start + 2 + - (instr_word & 0x0fff) * 2; + + nibl_count += 2; + break; + default: + break; + } + break; + case CLASS_IMM: + switch (datum_value) + { + case ARG_IMM4: + instr_data->immediate = instr_nibl; + break; + case ARG_NIM4: + instr_data->immediate = (- instr_nibl) & 0xf; + break; + case ARG_NIM8: + instr_data->immediate = (- instr_byte) & 0xff; + nibl_count += 1; + break; + case ARG_IMM8: + instr_data->immediate = instr_byte; + nibl_count += 1; + break; + case ARG_IMM16: + instr_data->immediate = instr_word; + nibl_count += 3; + break; + case ARG_IMM32: + FETCH_DATA (info, nibl_count + 8); + instr_long = (instr_data->words[nibl_count] << 16) + | (instr_data->words[nibl_count + 4]); + instr_data->immediate = instr_long; + nibl_count += 7; + break; + case ARG_IMMN: + instr_data->immediate = instr_nibl - 1; + break; + case ARG_IMM4M1: + instr_data->immediate = instr_nibl + 1; + break; + case ARG_IMM_1: + instr_data->immediate = 1; + break; + case ARG_IMM_2: + instr_data->immediate = 2; + break; + case ARG_IMM2: + instr_data->immediate = instr_nibl & 0x3; + break; + default: + break; + } + break; + case CLASS_CC: + instr_data->cond_code = instr_nibl; + break; + case CLASS_ADDRESS: + if (is_segmented) + { + if (instr_nibl & 0x8) + { + FETCH_DATA (info, nibl_count + 8); + instr_long = (instr_data->words[nibl_count] << 16) + | (instr_data->words[nibl_count + 4]); + instr_data->address = ((instr_word & 0x7f00) << 8) + + (instr_long & 0xffff); + nibl_count += 7; + seg_length = 2; + } + else + { + instr_data->address = ((instr_word & 0x7f00) << 8) + + (instr_word & 0x00ff); + nibl_count += 3; + } + } + else + { + instr_data->address = instr_word; + nibl_count += 3; + } + break; + case CLASS_0CCC: + case CLASS_1CCC: + instr_data->ctrl_code = instr_nibl & 0x7; + break; + case CLASS_0DISP7: + instr_data->displacement = + instr_data->insn_start + 2 - (instr_byte & 0x7f) * 2; + nibl_count += 1; + break; + case CLASS_1DISP7: + instr_data->displacement = + instr_data->insn_start + 2 - (instr_byte & 0x7f) * 2; + nibl_count += 1; + break; + case CLASS_01II: + instr_data->interrupts = instr_nibl & 0x3; + break; + case CLASS_00II: + instr_data->interrupts = instr_nibl & 0x3; + break; + case CLASS_IGNORE: + case CLASS_BIT: + instr_data->ctrl_code = instr_nibl & 0x7; + break; + case CLASS_FLAGS: + instr_data->flags = instr_nibl; + break; + case CLASS_REG: + instr_data->arg_reg[datum_value] = instr_nibl; + break; + case CLASS_REGN0: + instr_data->arg_reg[datum_value] = instr_nibl; + break; + case CLASS_DISP8: + instr_data->displacement = + instr_data->insn_start + 2 + (signed char) instr_byte * 2; + nibl_count += 1; + break; + case CLASS_BIT_1OR2: + instr_data->immediate = ((instr_nibl >> 1) & 0x1) + 1; + nibl_count += 1; + break; + default: + abort (); + break; + } + + loop += 1; + nibl_count += 1; + } +} + +static void +unparse_instr (instr_data, is_segmented) + instr_data_s *instr_data; + int is_segmented; +{ + unsigned short datum_value; + unsigned int tabl_datum, datum_class; + int loop, loop_limit; + char out_str[80], tmp_str[25]; + + sprintf (out_str, "%s\t", z8k_table[instr_data->tabl_index].name); + + loop_limit = z8k_table[instr_data->tabl_index].noperands; + for (loop = 0; loop < loop_limit; loop++) + { + if (loop) + strcat (out_str, ","); + + tabl_datum = z8k_table[instr_data->tabl_index].arg_info[loop]; + datum_class = tabl_datum & CLASS_MASK; + datum_value = tabl_datum & ~CLASS_MASK; + + switch (datum_class) + { + case CLASS_X: + sprintf (tmp_str, "0x%0lx(r%ld)", instr_data->address, + instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_BA: + if (is_segmented) + sprintf (tmp_str, "rr%ld(#%lx)", instr_data->arg_reg[datum_value], + instr_data->immediate); + else + sprintf (tmp_str, "r%ld(#%lx)", instr_data->arg_reg[datum_value], + instr_data->immediate); + strcat (out_str, tmp_str); + break; + case CLASS_BX: + if (is_segmented) + sprintf (tmp_str, "rr%ld(r%ld)", instr_data->arg_reg[datum_value], + instr_data->arg_reg[ARG_RX]); + else + sprintf (tmp_str, "r%ld(r%ld)", instr_data->arg_reg[datum_value], + instr_data->arg_reg[ARG_RX]); + strcat (out_str, tmp_str); + break; + case CLASS_DISP: + sprintf (tmp_str, "0x%0lx", instr_data->displacement); + strcat (out_str, tmp_str); + break; + case CLASS_IMM: + sprintf (tmp_str, "#0x%0lx", instr_data->immediate); + strcat (out_str, tmp_str); + break; + case CLASS_CC: + sprintf (tmp_str, "%s", codes[instr_data->cond_code]); + strcat (out_str, tmp_str); + break; + case CLASS_CTRL: + sprintf (tmp_str, "%s", ctrl_names[instr_data->ctrl_code]); + strcat (out_str, tmp_str); + break; + case CLASS_DA: + case CLASS_ADDRESS: + sprintf (tmp_str, "0x%0lx", instr_data->address); + strcat (out_str, tmp_str); + break; + case CLASS_IR: + if (is_segmented) + sprintf (tmp_str, "@rr%ld", instr_data->arg_reg[datum_value]); + else + sprintf (tmp_str, "@r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_FLAGS: + sprintf (tmp_str, "0x%0lx", instr_data->flags); + strcat (out_str, tmp_str); + break; + case CLASS_REG_BYTE: + if (instr_data->arg_reg[datum_value] >= 0x8) + sprintf (tmp_str, "rl%ld", + instr_data->arg_reg[datum_value] - 0x8); + else + sprintf (tmp_str, "rh%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_REG_WORD: + sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_REG_QUAD: + sprintf (tmp_str, "rq%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_REG_LONG: + sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_PR: + if (is_segmented) + sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); + else + sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + default: + abort (); + break; + } + } + + strcpy (instr_data->instr_asmsrc, out_str); +} diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h new file mode 100644 index 0000000..025cfab --- /dev/null +++ b/opcodes/z8k-opc.h @@ -0,0 +1,4481 @@ + /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */ +#define ARG_MASK 0x0f +#define ARG_SRC 0x01 +#define ARG_DST 0x02 +#define ARG_RS 0x01 +#define ARG_RD 0x02 +#define ARG_RA 0x03 +#define ARG_RB 0x04 +#define ARG_RR 0x05 +#define ARG_RX 0x06 +#define ARG_IMM4 0x01 +#define ARG_IMM8 0x02 +#define ARG_IMM16 0x03 +#define ARG_IMM32 0x04 +#define ARG_IMMN 0x05 +#define ARG_IMMNMINUS1 0x05 +#define ARG_IMM_1 0x06 +#define ARG_IMM_2 0x07 +#define ARG_DISP16 0x08 +#define ARG_NIM8 0x09 +#define ARG_IMM2 0x0a +#define ARG_IMM1OR2 0x0b +#define ARG_DISP12 0x0b +#define ARG_NIM4 0x0c +#define ARG_DISP8 0x0c +#define ARG_IMM4M1 0x0d +#define CLASS_MASK 0x1fff0 +#define CLASS_X 0x10 +#define CLASS_BA 0x20 +#define CLASS_DA 0x30 +#define CLASS_BX 0x40 +#define CLASS_DISP 0x50 +#define CLASS_IMM 0x60 +#define CLASS_CC 0x70 +#define CLASS_CTRL 0x80 +#define CLASS_IGNORE 0x90 +#define CLASS_ADDRESS 0xd0 +#define CLASS_0CCC 0xe0 +#define CLASS_1CCC 0xf0 +#define CLASS_0DISP7 0x100 +#define CLASS_1DISP7 0x200 +#define CLASS_01II 0x300 +#define CLASS_00II 0x400 +#define CLASS_BIT 0x500 +#define CLASS_FLAGS 0x600 +#define CLASS_IR 0x700 +#define CLASS_DISP8 0x800 +#define CLASS_BIT_1OR2 0x900 +#define CLASS_REG 0x7000 +#define CLASS_REG_BYTE 0x2000 +#define CLASS_REG_WORD 0x3000 +#define CLASS_REG_QUAD 0x4000 +#define CLASS_REG_LONG 0x5000 +#define CLASS_REGN0 0x8000 +#define CLASS_PR 0x10000 +#define OPC_adc 0 +#define OPC_adcb 1 +#define OPC_add 2 +#define OPC_addb 3 +#define OPC_addl 4 +#define OPC_and 5 +#define OPC_andb 6 +#define OPC_bit 7 +#define OPC_bitb 8 +#define OPC_call 9 +#define OPC_calr 10 +#define OPC_clr 11 +#define OPC_clrb 12 +#define OPC_com 13 +#define OPC_comb 14 +#define OPC_comflg 15 +#define OPC_cp 16 +#define OPC_cpb 17 +#define OPC_cpd 18 +#define OPC_cpdb 19 +#define OPC_cpdr 20 +#define OPC_cpdrb 21 +#define OPC_cpi 22 +#define OPC_cpib 23 +#define OPC_cpir 24 +#define OPC_cpirb 25 +#define OPC_cpl 26 +#define OPC_cpsd 27 +#define OPC_cpsdb 28 +#define OPC_cpsdr 29 +#define OPC_cpsdrb 30 +#define OPC_cpsi 31 +#define OPC_cpsib 32 +#define OPC_cpsir 33 +#define OPC_cpsirb 34 +#define OPC_dab 35 +#define OPC_dbjnz 36 +#define OPC_dec 37 +#define OPC_decb 38 +#define OPC_di 39 +#define OPC_div 40 +#define OPC_divl 41 +#define OPC_djnz 42 +#define OPC_ei 43 +#define OPC_ex 44 +#define OPC_exb 45 +#define OPC_exts 46 +#define OPC_extsb 47 +#define OPC_extsl 48 +#define OPC_halt 49 +#define OPC_in 50 +#define OPC_inb 51 +#define OPC_inc 52 +#define OPC_incb 53 +#define OPC_ind 54 +#define OPC_indb 55 +#define OPC_inib 56 +#define OPC_inibr 57 +#define OPC_iret 58 +#define OPC_jp 59 +#define OPC_jr 60 +#define OPC_ld 61 +#define OPC_lda 62 +#define OPC_ldar 63 +#define OPC_ldb 64 +#define OPC_ldctl 65 +#define OPC_ldir 66 +#define OPC_ldirb 67 +#define OPC_ldk 68 +#define OPC_ldl 69 +#define OPC_ldm 70 +#define OPC_ldps 71 +#define OPC_ldr 72 +#define OPC_ldrb 73 +#define OPC_ldrl 74 +#define OPC_mbit 75 +#define OPC_mreq 76 +#define OPC_mres 77 +#define OPC_mset 78 +#define OPC_mult 79 +#define OPC_multl 80 +#define OPC_neg 81 +#define OPC_negb 82 +#define OPC_nop 83 +#define OPC_or 84 +#define OPC_orb 85 +#define OPC_out 86 +#define OPC_outb 87 +#define OPC_outd 88 +#define OPC_outdb 89 +#define OPC_outib 90 +#define OPC_outibr 91 +#define OPC_pop 92 +#define OPC_popl 93 +#define OPC_push 94 +#define OPC_pushl 95 +#define OPC_res 96 +#define OPC_resb 97 +#define OPC_resflg 98 +#define OPC_ret 99 +#define OPC_rl 100 +#define OPC_rlb 101 +#define OPC_rlc 102 +#define OPC_rlcb 103 +#define OPC_rldb 104 +#define OPC_rr 105 +#define OPC_rrb 106 +#define OPC_rrc 107 +#define OPC_rrcb 108 +#define OPC_rrdb 109 +#define OPC_sbc 110 +#define OPC_sbcb 111 +#define OPC_sda 112 +#define OPC_sdab 113 +#define OPC_sdal 114 +#define OPC_sdl 115 +#define OPC_sdlb 116 +#define OPC_sdll 117 +#define OPC_set 118 +#define OPC_setb 119 +#define OPC_setflg 120 +#define OPC_sinb 121 +#define OPC_sind 122 +#define OPC_sindb 123 +#define OPC_sinib 124 +#define OPC_sinibr 125 +#define OPC_sla 126 +#define OPC_slab 127 +#define OPC_slal 128 +#define OPC_sll 129 +#define OPC_sllb 130 +#define OPC_slll 131 +#define OPC_sout 132 +#define OPC_soutb 133 +#define OPC_soutd 134 +#define OPC_soutdb 135 +#define OPC_soutib 136 +#define OPC_soutibr 137 +#define OPC_sra 138 +#define OPC_srab 139 +#define OPC_sral 140 +#define OPC_srl 141 +#define OPC_srlb 142 +#define OPC_srll 143 +#define OPC_sub 144 +#define OPC_subb 145 +#define OPC_subl 146 +#define OPC_tcc 147 +#define OPC_tccb 148 +#define OPC_test 149 +#define OPC_testb 150 +#define OPC_testl 151 +#define OPC_trdb 152 +#define OPC_trdrb 153 +#define OPC_trib 154 +#define OPC_trirb 155 +#define OPC_trtdrb 156 +#define OPC_trtib 157 +#define OPC_trtirb 158 +#define OPC_trtrb 159 +#define OPC_tset 160 +#define OPC_tsetb 161 +#define OPC_xor 162 +#define OPC_xorb 163 +#define OPC_ldd 164 +#define OPC_lddb 165 +#define OPC_lddr 166 +#define OPC_lddrb 167 +#define OPC_ldi 168 +#define OPC_ldib 169 +#define OPC_sc 170 +#define OPC_bpt 171 +#define OPC_ext0e 172 +#define OPC_ext0f 172 +#define OPC_ext8e 172 +#define OPC_ext8f 172 +#define OPC_rsvd36 172 +#define OPC_rsvd38 172 +#define OPC_rsvd78 172 +#define OPC_rsvd7e 172 +#define OPC_rsvd9d 172 +#define OPC_rsvd9f 172 +#define OPC_rsvdb9 172 +#define OPC_rsvdbf 172 +#define OPC_outi 173 +#define OPC_ldctlb 174 +#define OPC_sin 175 +#define OPC_trtdb 176 +typedef struct { +#ifdef NICENAMES +char *nicename; +int type; +int cycles; +int flags; +#endif +char *name; +unsigned char opcode; +void (*func) PARAMS ((void)); +unsigned int arg_info[4]; +unsigned int byte_info[10]; +int noperands; +int length; +int idx; +} opcode_entry_type; +#ifdef DEFINE_TABLE +opcode_entry_type z8k_table[] = { + + +/* 1011 0101 ssss dddd *** adc rd,rs */ +{ +#ifdef NICENAMES +"adc rd,rs",16,5, +0x3c, +#endif +"adc",OPC_adc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,0}, + + +/* 1011 0100 ssss dddd *** adcb rbd,rbs */ +{ +#ifdef NICENAMES +"adcb rbd,rbs",8,5, +0x3f, +#endif +"adcb",OPC_adcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,1}, + + +/* 0000 0001 ssN0 dddd *** add rd,@rs */ +{ +#ifdef NICENAMES +"add rd,@rs",16,7, +0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2}, + + +/* 0100 0001 0000 dddd address_src *** add rd,address_src */ +{ +#ifdef NICENAMES +"add rd,address_src",16,9, +0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,3}, + + +/* 0100 0001 ssN0 dddd address_src *** add rd,address_src(rs) */ +{ +#ifdef NICENAMES +"add rd,address_src(rs)",16,10, +0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,4}, + + +/* 0000 0001 0000 dddd imm16 *** add rd,imm16 */ +{ +#ifdef NICENAMES +"add rd,imm16",16,7, +0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,5}, + + +/* 1000 0001 ssss dddd *** add rd,rs */ +{ +#ifdef NICENAMES +"add rd,rs",16,4, +0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6}, + + +/* 0000 0000 ssN0 dddd *** addb rbd,@rs */ +{ +#ifdef NICENAMES +"addb rbd,@rs",8,7, +0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,7}, + + +/* 0100 0000 0000 dddd address_src *** addb rbd,address_src */ +{ +#ifdef NICENAMES +"addb rbd,address_src",8,9, +0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,8}, + + +/* 0100 0000 ssN0 dddd address_src *** addb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"addb rbd,address_src(rs)",8,10, +0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,9}, + + +/* 0000 0000 0000 dddd imm8 imm8 *** addb rbd,imm8 */ +{ +#ifdef NICENAMES +"addb rbd,imm8",8,7, +0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,10}, + + +/* 1000 0000 ssss dddd *** addb rbd,rbs */ +{ +#ifdef NICENAMES +"addb rbd,rbs",8,4, +0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,11}, + + +/* 0001 0110 ssN0 dddd *** addl rrd,@rs */ +{ +#ifdef NICENAMES +"addl rrd,@rs",32,14, +0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,12}, + + +/* 0101 0110 0000 dddd address_src *** addl rrd,address_src */ +{ +#ifdef NICENAMES +"addl rrd,address_src",32,15, +0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,13}, + + +/* 0101 0110 ssN0 dddd address_src *** addl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"addl rrd,address_src(rs)",32,16, +0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,14}, + + +/* 0001 0110 0000 dddd imm32 *** addl rrd,imm32 */ +{ +#ifdef NICENAMES +"addl rrd,imm32",32,14, +0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,15}, + + +/* 1001 0110 ssss dddd *** addl rrd,rrs */ +{ +#ifdef NICENAMES +"addl rrd,rrs",32,8, +0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,16}, + + +/* 0000 0111 ssN0 dddd *** and rd,@rs */ +{ +#ifdef NICENAMES +"and rd,@rs",16,7, +0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17}, + + +/* 0100 0111 0000 dddd address_src *** and rd,address_src */ +{ +#ifdef NICENAMES +"and rd,address_src",16,9, +0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, + + +/* 0100 0111 ssN0 dddd address_src *** and rd,address_src(rs) */ +{ +#ifdef NICENAMES +"and rd,address_src(rs)",16,10, +0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, + + +/* 0000 0111 0000 dddd imm16 *** and rd,imm16 */ +{ +#ifdef NICENAMES +"and rd,imm16",16,7, +0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,20}, + + +/* 1000 0111 ssss dddd *** and rd,rs */ +{ +#ifdef NICENAMES +"and rd,rs",16,4, +0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,21}, + + +/* 0000 0110 ssN0 dddd *** andb rbd,@rs */ +{ +#ifdef NICENAMES +"andb rbd,@rs",8,7, +0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,22}, + + +/* 0100 0110 0000 dddd address_src *** andb rbd,address_src */ +{ +#ifdef NICENAMES +"andb rbd,address_src",8,9, +0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,23}, + + +/* 0100 0110 ssN0 dddd address_src *** andb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"andb rbd,address_src(rs)",8,10, +0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,24}, + + +/* 0000 0110 0000 dddd imm8 imm8 *** andb rbd,imm8 */ +{ +#ifdef NICENAMES +"andb rbd,imm8",8,7, +0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,25}, + + +/* 1000 0110 ssss dddd *** andb rbd,rbs */ +{ +#ifdef NICENAMES +"andb rbd,rbs",8,4, +0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,26}, + + +/* 0010 0111 ddN0 imm4 *** bit @rd,imm4 */ +{ +#ifdef NICENAMES +"bit @rd,imm4",16,8, +0x10, +#endif +"bit",OPC_bit,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,27}, + + +/* 0110 0111 ddN0 imm4 address_dst *** bit address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"bit address_dst(rd),imm4",16,11, +0x10, +#endif +"bit",OPC_bit,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,28}, + + +/* 0110 0111 0000 imm4 address_dst *** bit address_dst,imm4 */ +{ +#ifdef NICENAMES +"bit address_dst,imm4",16,10, +0x10, +#endif +"bit",OPC_bit,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+7,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,29}, + + +/* 1010 0111 dddd imm4 *** bit rd,imm4 */ +{ +#ifdef NICENAMES +"bit rd,imm4",16,4, +0x10, +#endif +"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+7,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,30}, + + +/* 0010 0111 0000 ssss 0000 dddd 0000 0000 *** bit rd,rs */ +{ +#ifdef NICENAMES +"bit rd,rs",16,10, +0x10, +#endif +"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,31}, + + +/* 0010 0110 ddN0 imm4 *** bitb @rd,imm4 */ +{ +#ifdef NICENAMES +"bitb @rd,imm4",8,8, +0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,32}, + + +/* 0110 0110 ddN0 imm4 address_dst *** bitb address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"bitb address_dst(rd),imm4",8,11, +0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,33}, + + +/* 0110 0110 0000 imm4 address_dst *** bitb address_dst,imm4 */ +{ +#ifdef NICENAMES +"bitb address_dst,imm4",8,10, +0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+6,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,34}, + + +/* 1010 0110 dddd imm4 *** bitb rbd,imm4 */ +{ +#ifdef NICENAMES +"bitb rbd,imm4",8,4, +0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+6,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,35}, + + +/* 0010 0110 0000 ssss 0000 dddd 0000 0000 *** bitb rbd,rs */ +{ +#ifdef NICENAMES +"bitb rbd,rs",8,10, +0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,36}, + + +/* 0011 0110 0000 0000 *** bpt */ +{ +#ifdef NICENAMES +"bpt",8,2, +0x00, +#endif +"bpt",OPC_bpt,0,{0}, + {CLASS_BIT+3,CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,37}, + + +/* 0001 1111 ddN0 0000 *** call @rd */ +{ +#ifdef NICENAMES +"call @rd",32,10, +0x00, +#endif +"call",OPC_call,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+1,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,38}, + + +/* 0101 1111 0000 0000 address_dst *** call address_dst */ +{ +#ifdef NICENAMES +"call address_dst",32,12, +0x00, +#endif +"call",OPC_call,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,39}, + + +/* 0101 1111 ddN0 0000 address_dst *** call address_dst(rd) */ +{ +#ifdef NICENAMES +"call address_dst(rd)",32,13, +0x00, +#endif +"call",OPC_call,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,40}, + + +/* 1101 disp12 *** calr disp12 */ +{ +#ifdef NICENAMES +"calr disp12",16,10, +0x00, +#endif +"calr",OPC_calr,0,{CLASS_DISP,}, + {CLASS_BIT+0xd,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,41}, + + +/* 0000 1101 ddN0 1000 *** clr @rd */ +{ +#ifdef NICENAMES +"clr @rd",16,8, +0x00, +#endif +"clr",OPC_clr,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,42}, + + +/* 0100 1101 0000 1000 address_dst *** clr address_dst */ +{ +#ifdef NICENAMES +"clr address_dst",16,11, +0x00, +#endif +"clr",OPC_clr,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,43}, + + +/* 0100 1101 ddN0 1000 address_dst *** clr address_dst(rd) */ +{ +#ifdef NICENAMES +"clr address_dst(rd)",16,12, +0x00, +#endif +"clr",OPC_clr,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,44}, + + +/* 1000 1101 dddd 1000 *** clr rd */ +{ +#ifdef NICENAMES +"clr rd",16,7, +0x00, +#endif +"clr",OPC_clr,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,45}, + + +/* 0000 1100 ddN0 1000 *** clrb @rd */ +{ +#ifdef NICENAMES +"clrb @rd",8,8, +0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,46}, + + +/* 0100 1100 0000 1000 address_dst *** clrb address_dst */ +{ +#ifdef NICENAMES +"clrb address_dst",8,11, +0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,47}, + + +/* 0100 1100 ddN0 1000 address_dst *** clrb address_dst(rd) */ +{ +#ifdef NICENAMES +"clrb address_dst(rd)",8,12, +0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,48}, + + +/* 1000 1100 dddd 1000 *** clrb rbd */ +{ +#ifdef NICENAMES +"clrb rbd",8,7, +0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,49}, + + +/* 0000 1101 ddN0 0000 *** com @rd */ +{ +#ifdef NICENAMES +"com @rd",16,12, +0x18, +#endif +"com",OPC_com,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,50}, + + +/* 0100 1101 0000 0000 address_dst *** com address_dst */ +{ +#ifdef NICENAMES +"com address_dst",16,15, +0x18, +#endif +"com",OPC_com,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,51}, + + +/* 0100 1101 ddN0 0000 address_dst *** com address_dst(rd) */ +{ +#ifdef NICENAMES +"com address_dst(rd)",16,16, +0x18, +#endif +"com",OPC_com,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,52}, + + +/* 1000 1101 dddd 0000 *** com rd */ +{ +#ifdef NICENAMES +"com rd",16,7, +0x18, +#endif +"com",OPC_com,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53}, + + +/* 0000 1100 ddN0 0000 *** comb @rd */ +{ +#ifdef NICENAMES +"comb @rd",8,12, +0x1c, +#endif +"comb",OPC_comb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,54}, + + +/* 0100 1100 0000 0000 address_dst *** comb address_dst */ +{ +#ifdef NICENAMES +"comb address_dst",8,15, +0x1c, +#endif +"comb",OPC_comb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,55}, + + +/* 0100 1100 ddN0 0000 address_dst *** comb address_dst(rd) */ +{ +#ifdef NICENAMES +"comb address_dst(rd)",8,16, +0x1c, +#endif +"comb",OPC_comb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,56}, + + +/* 1000 1100 dddd 0000 *** comb rbd */ +{ +#ifdef NICENAMES +"comb rbd",8,7, +0x1c, +#endif +"comb",OPC_comb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,57}, + + +/* 1000 1101 flags 0101 *** comflg flags */ +{ +#ifdef NICENAMES +"comflg flags",16,7, +0x3c, +#endif +"comflg",OPC_comflg,0,{CLASS_FLAGS,}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+5,0,0,0,0,0,},1,2,58}, + + +/* 0000 1101 ddN0 0001 imm16 *** cp @rd,imm16 */ +{ +#ifdef NICENAMES +"cp @rd,imm16",16,11, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,59}, + + +/* 0100 1101 ddN0 0001 address_dst imm16 *** cp address_dst(rd),imm16 */ +{ +#ifdef NICENAMES +"cp address_dst(rd),imm16",16,15, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,60}, + + +/* 0100 1101 0000 0001 address_dst imm16 *** cp address_dst,imm16 */ +{ +#ifdef NICENAMES +"cp address_dst,imm16",16,14, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,61}, + + +/* 0000 1011 ssN0 dddd *** cp rd,@rs */ +{ +#ifdef NICENAMES +"cp rd,@rs",16,7, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,62}, + + +/* 0100 1011 0000 dddd address_src *** cp rd,address_src */ +{ +#ifdef NICENAMES +"cp rd,address_src",16,9, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,63}, + + +/* 0100 1011 ssN0 dddd address_src *** cp rd,address_src(rs) */ +{ +#ifdef NICENAMES +"cp rd,address_src(rs)",16,10, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,64}, + + +/* 0000 1011 0000 dddd imm16 *** cp rd,imm16 */ +{ +#ifdef NICENAMES +"cp rd,imm16",16,7, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,65}, + + +/* 1000 1011 ssss dddd *** cp rd,rs */ +{ +#ifdef NICENAMES +"cp rd,rs",16,4, +0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,66}, + + +/* 0000 1100 ddN0 0001 imm8 imm8 *** cpb @rd,imm8 */ +{ +#ifdef NICENAMES +"cpb @rd,imm8",8,11, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,67}, + + +/* 0100 1100 ddN0 0001 address_dst imm8 imm8 *** cpb address_dst(rd),imm8 */ +{ +#ifdef NICENAMES +"cpb address_dst(rd),imm8",8,15, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,68}, + + +/* 0100 1100 0000 0001 address_dst imm8 imm8 *** cpb address_dst,imm8 */ +{ +#ifdef NICENAMES +"cpb address_dst,imm8",8,14, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,69}, + + +/* 0000 1010 ssN0 dddd *** cpb rbd,@rs */ +{ +#ifdef NICENAMES +"cpb rbd,@rs",8,7, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,70}, + + +/* 0100 1010 0000 dddd address_src *** cpb rbd,address_src */ +{ +#ifdef NICENAMES +"cpb rbd,address_src",8,9, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, + + +/* 0100 1010 ssN0 dddd address_src *** cpb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"cpb rbd,address_src(rs)",8,10, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, + + +/* 0000 1010 0000 dddd imm8 imm8 *** cpb rbd,imm8 */ +{ +#ifdef NICENAMES +"cpb rbd,imm8",8,7, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,73}, + + +/* 1000 1010 ssss dddd *** cpb rbd,rbs */ +{ +#ifdef NICENAMES +"cpb rbd,rbs",8,4, +0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, + + +/* 1011 1011 ssN0 1000 0000 rrrr dddd cccc *** cpd rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpd rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpd",OPC_cpd,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,75}, + + +/* 1011 1010 ssN0 1000 0000 rrrr dddd cccc *** cpdb rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpdb rbd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpdb",OPC_cpdb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,76}, + + +/* 1011 1011 ssN0 1100 0000 rrrr dddd cccc *** cpdr rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpdr rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpdr",OPC_cpdr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,77}, + + +/* 1011 1010 ssN0 1100 0000 rrrr dddd cccc *** cpdrb rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpdrb rbd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpdrb",OPC_cpdrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,78}, + + +/* 1011 1011 ssN0 0000 0000 rrrr dddd cccc *** cpi rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpi rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpi",OPC_cpi,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,79}, + + +/* 1011 1010 ssN0 0000 0000 rrrr dddd cccc *** cpib rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpib rbd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpib",OPC_cpib,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,80}, + + +/* 1011 1011 ssN0 0100 0000 rrrr dddd cccc *** cpir rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpir rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpir",OPC_cpir,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,81}, + + +/* 1011 1010 ssN0 0100 0000 rrrr dddd cccc *** cpirb rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpirb rbd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpirb",OPC_cpirb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,82}, + + +/* 0001 0000 ssN0 dddd *** cpl rrd,@rs */ +{ +#ifdef NICENAMES +"cpl rrd,@rs",32,14, +0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,83}, + + +/* 0101 0000 0000 dddd address_src *** cpl rrd,address_src */ +{ +#ifdef NICENAMES +"cpl rrd,address_src",32,15, +0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,84}, + + +/* 0101 0000 ssN0 dddd address_src *** cpl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"cpl rrd,address_src(rs)",32,16, +0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,85}, + + +/* 0001 0000 0000 dddd imm32 *** cpl rrd,imm32 */ +{ +#ifdef NICENAMES +"cpl rrd,imm32",32,14, +0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,86}, + + +/* 1001 0000 ssss dddd *** cpl rrd,rrs */ +{ +#ifdef NICENAMES +"cpl rrd,rrs",32,8, +0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,87}, + + +/* 1011 1011 ssN0 1010 0000 rrrr ddN0 cccc *** cpsd @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsd @rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpsd",OPC_cpsd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,88}, + + +/* 1011 1010 ssN0 1010 0000 rrrr ddN0 cccc *** cpsdb @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsdb @rd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpsdb",OPC_cpsdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,89}, + + +/* 1011 1011 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdr @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsdr @rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpsdr",OPC_cpsdr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,90}, + + +/* 1011 1010 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdrb @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsdrb @rd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpsdrb",OPC_cpsdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,91}, + + +/* 1011 1011 ssN0 0010 0000 rrrr ddN0 cccc *** cpsi @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsi @rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpsi",OPC_cpsi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,92}, + + +/* 1011 1010 ssN0 0010 0000 rrrr ddN0 cccc *** cpsib @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsib @rd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpsib",OPC_cpsib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,93}, + + +/* 1011 1011 ssN0 0110 0000 rrrr ddN0 cccc *** cpsir @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsir @rd,@rs,rr,cc",16,11, +0x3c, +#endif +"cpsir",OPC_cpsir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,94}, + + +/* 1011 1010 ssN0 0110 0000 rrrr ddN0 cccc *** cpsirb @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsirb @rd,@rs,rr,cc",8,11, +0x3c, +#endif +"cpsirb",OPC_cpsirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,95}, + + +/* 1011 0000 dddd 0000 *** dab rbd */ +{ +#ifdef NICENAMES +"dab rbd",8,5, +0x38, +#endif +"dab",OPC_dab,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,96}, + + +/* 1111 dddd 0disp7 *** dbjnz rbd,disp7 */ +{ +#ifdef NICENAMES +"dbjnz rbd,disp7",16,11, +0x00, +#endif +"dbjnz",OPC_dbjnz,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,97}, + + +/* 0010 1011 ddN0 imm4m1 *** dec @rd,imm4m1 */ +{ +#ifdef NICENAMES +"dec @rd,imm4m1",16,11, +0x1c, +#endif +"dec",OPC_dec,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,98}, + + +/* 0110 1011 ddN0 imm4m1 address_dst *** dec address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"dec address_dst(rd),imm4m1",16,14, +0x1c, +#endif +"dec",OPC_dec,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,99}, + + +/* 0110 1011 0000 imm4m1 address_dst *** dec address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"dec address_dst,imm4m1",16,13, +0x1c, +#endif +"dec",OPC_dec,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,100}, + + +/* 1010 1011 dddd imm4m1 *** dec rd,imm4m1 */ +{ +#ifdef NICENAMES +"dec rd,imm4m1",16,4, +0x1c, +#endif +"dec",OPC_dec,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,101}, + + +/* 0010 1010 ddN0 imm4m1 *** decb @rd,imm4m1 */ +{ +#ifdef NICENAMES +"decb @rd,imm4m1",8,11, +0x1c, +#endif +"decb",OPC_decb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,102}, + + +/* 0110 1010 ddN0 imm4m1 address_dst *** decb address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"decb address_dst(rd),imm4m1",8,14, +0x1c, +#endif +"decb",OPC_decb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,103}, + + +/* 0110 1010 0000 imm4m1 address_dst *** decb address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"decb address_dst,imm4m1",8,13, +0x1c, +#endif +"decb",OPC_decb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,104}, + + +/* 1010 1010 dddd imm4m1 *** decb rbd,imm4m1 */ +{ +#ifdef NICENAMES +"decb rbd,imm4m1",8,4, +0x1c, +#endif +"decb",OPC_decb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,105}, + + +/* 0111 1100 0000 00ii *** di i2 */ +{ +#ifdef NICENAMES +"di i2",16,7, +0x00, +#endif +"di",OPC_di,0,{CLASS_IMM+(ARG_IMM2),}, + {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,106}, + + +/* 0001 1011 ssN0 dddd *** div rrd,@rs */ +{ +#ifdef NICENAMES +"div rrd,@rs",16,107, +0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,107}, + + +/* 0101 1011 0000 dddd address_src *** div rrd,address_src */ +{ +#ifdef NICENAMES +"div rrd,address_src",16,107, +0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,108}, + + +/* 0101 1011 ssN0 dddd address_src *** div rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"div rrd,address_src(rs)",16,107, +0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,109}, + + +/* 0001 1011 0000 dddd imm16 *** div rrd,imm16 */ +{ +#ifdef NICENAMES +"div rrd,imm16",16,107, +0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,110}, + + +/* 1001 1011 ssss dddd *** div rrd,rs */ +{ +#ifdef NICENAMES +"div rrd,rs",16,107, +0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,111}, + + +/* 0001 1010 ssN0 dddd *** divl rqd,@rs */ +{ +#ifdef NICENAMES +"divl rqd,@rs",32,744, +0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,112}, + + +/* 0101 1010 0000 dddd address_src *** divl rqd,address_src */ +{ +#ifdef NICENAMES +"divl rqd,address_src",32,745, +0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,113}, + + +/* 0101 1010 ssN0 dddd address_src *** divl rqd,address_src(rs) */ +{ +#ifdef NICENAMES +"divl rqd,address_src(rs)",32,746, +0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,114}, + + +/* 0001 1010 0000 dddd imm32 *** divl rqd,imm32 */ +{ +#ifdef NICENAMES +"divl rqd,imm32",32,744, +0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,115}, + + +/* 1001 1010 ssss dddd *** divl rqd,rrs */ +{ +#ifdef NICENAMES +"divl rqd,rrs",32,744, +0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,116}, + + +/* 1111 dddd 1disp7 *** djnz rd,disp7 */ +{ +#ifdef NICENAMES +"djnz rd,disp7",16,11, +0x00, +#endif +"djnz",OPC_djnz,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,117}, + + +/* 0111 1100 0000 01ii *** ei i2 */ +{ +#ifdef NICENAMES +"ei i2",16,7, +0x00, +#endif +"ei",OPC_ei,0,{CLASS_IMM+(ARG_IMM2),}, + {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,118}, + + +/* 0010 1101 ssN0 dddd *** ex rd,@rs */ +{ +#ifdef NICENAMES +"ex rd,@rs",16,12, +0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,119}, + + +/* 0110 1101 0000 dddd address_src *** ex rd,address_src */ +{ +#ifdef NICENAMES +"ex rd,address_src",16,15, +0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,120}, + + +/* 0110 1101 ssN0 dddd address_src *** ex rd,address_src(rs) */ +{ +#ifdef NICENAMES +"ex rd,address_src(rs)",16,16, +0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,121}, + + +/* 1010 1101 ssss dddd *** ex rd,rs */ +{ +#ifdef NICENAMES +"ex rd,rs",16,6, +0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,122}, + + +/* 0010 1100 ssN0 dddd *** exb rbd,@rs */ +{ +#ifdef NICENAMES +"exb rbd,@rs",8,12, +0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,123}, + + +/* 0110 1100 0000 dddd address_src *** exb rbd,address_src */ +{ +#ifdef NICENAMES +"exb rbd,address_src",8,15, +0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,124}, + + +/* 0110 1100 ssN0 dddd address_src *** exb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"exb rbd,address_src(rs)",8,16, +0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,125}, + + +/* 1010 1100 ssss dddd *** exb rbd,rbs */ +{ +#ifdef NICENAMES +"exb rbd,rbs",8,6, +0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,126}, + + +/* 0000 1110 imm8 *** ext0e imm8 */ +{ +#ifdef NICENAMES +"ext0e imm8",8,10, +0x00, +#endif +"ext0e",OPC_ext0e,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,127}, + + +/* 0000 1111 imm8 *** ext0f imm8 */ +{ +#ifdef NICENAMES +"ext0f imm8",8,10, +0x00, +#endif +"ext0f",OPC_ext0f,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,128}, + + +/* 1000 1110 imm8 *** ext8e imm8 */ +{ +#ifdef NICENAMES +"ext8e imm8",8,10, +0x00, +#endif +"ext8e",OPC_ext8e,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+8,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,129}, + + +/* 1000 1111 imm8 *** ext8f imm8 */ +{ +#ifdef NICENAMES +"ext8f imm8",8,10, +0x00, +#endif +"ext8f",OPC_ext8f,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+8,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,130}, + + +/* 1011 0001 dddd 1010 *** exts rrd */ +{ +#ifdef NICENAMES +"exts rrd",16,11, +0x00, +#endif +"exts",OPC_exts,0,{CLASS_REG_LONG+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0xa,0,0,0,0,0,},1,2,131}, + + +/* 1011 0001 dddd 0000 *** extsb rd */ +{ +#ifdef NICENAMES +"extsb rd",8,11, +0x00, +#endif +"extsb",OPC_extsb,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,132}, + + +/* 1011 0001 dddd 0111 *** extsl rqd */ +{ +#ifdef NICENAMES +"extsl rqd",32,11, +0x00, +#endif +"extsl",OPC_extsl,0,{CLASS_REG_QUAD+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,133}, + + +/* 0111 1010 0000 0000 *** halt */ +{ +#ifdef NICENAMES +"halt",16,8, +0x00, +#endif +"halt",OPC_halt,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,134}, + + +/* 0011 1101 ssN0 dddd *** in rd,@rs */ +{ +#ifdef NICENAMES +"in rd,@rs",16,10, +0x00, +#endif +"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,135}, + + +/* 0011 1101 dddd 0100 imm16 *** in rd,imm16 */ +{ +#ifdef NICENAMES +"in rd,imm16",16,12, +0x00, +#endif +"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,136}, + + +/* 0011 1100 ssN0 dddd *** inb rbd,@rs */ +{ +#ifdef NICENAMES +"inb rbd,@rs",8,12, +0x00, +#endif +"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,137}, + + +/* 0011 1010 dddd 0100 imm16 *** inb rbd,imm16 */ +{ +#ifdef NICENAMES +"inb rbd,imm16",8,10, +0x00, +#endif +"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,138}, + + +/* 0010 1001 ddN0 imm4m1 *** inc @rd,imm4m1 */ +{ +#ifdef NICENAMES +"inc @rd,imm4m1",16,11, +0x1c, +#endif +"inc",OPC_inc,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,139}, + + +/* 0110 1001 ddN0 imm4m1 address_dst *** inc address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"inc address_dst(rd),imm4m1",16,14, +0x1c, +#endif +"inc",OPC_inc,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,140}, + + +/* 0110 1001 0000 imm4m1 address_dst *** inc address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"inc address_dst,imm4m1",16,13, +0x1c, +#endif +"inc",OPC_inc,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,141}, + + +/* 1010 1001 dddd imm4m1 *** inc rd,imm4m1 */ +{ +#ifdef NICENAMES +"inc rd,imm4m1",16,4, +0x1c, +#endif +"inc",OPC_inc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,142}, + + +/* 0010 1000 ddN0 imm4m1 *** incb @rd,imm4m1 */ +{ +#ifdef NICENAMES +"incb @rd,imm4m1",8,11, +0x1c, +#endif +"incb",OPC_incb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,143}, + + +/* 0110 1000 ddN0 imm4m1 address_dst *** incb address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"incb address_dst(rd),imm4m1",8,14, +0x1c, +#endif +"incb",OPC_incb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,144}, + + +/* 0110 1000 0000 imm4m1 address_dst *** incb address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"incb address_dst,imm4m1",8,13, +0x1c, +#endif +"incb",OPC_incb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,145}, + + +/* 1010 1000 dddd imm4m1 *** incb rbd,imm4m1 */ +{ +#ifdef NICENAMES +"incb rbd,imm4m1",8,4, +0x1c, +#endif +"incb",OPC_incb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,146}, + + +/* 0011 1011 ssN0 1000 0000 aaaa ddN0 1000 *** ind @rd,@rs,ra */ +{ +#ifdef NICENAMES +"ind @rd,@rs,ra",16,21, +0x04, +#endif +"ind",OPC_ind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,147}, + + +/* 0011 1010 ssN0 1000 0000 aaaa ddN0 1000 *** indb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"indb @rd,@rs,rba",8,21, +0x04, +#endif +"indb",OPC_indb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,148}, + + +/* 0011 1010 ssN0 0000 0000 aaaa ddN0 1000 *** inib @rd,@rs,ra */ +{ +#ifdef NICENAMES +"inib @rd,@rs,ra",8,21, +0x04, +#endif +"inib",OPC_inib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,149}, + + +/* 0011 1010 ssN0 0000 0000 aaaa ddN0 0000 *** inibr @rd,@rs,ra */ +{ +#ifdef NICENAMES +"inibr @rd,@rs,ra",16,21, +0x04, +#endif +"inibr",OPC_inibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,150}, + + +/* 0111 1011 0000 0000 *** iret */ +{ +#ifdef NICENAMES +"iret",16,13, +0x3f, +#endif +"iret",OPC_iret,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,151}, + + +/* 0001 1110 ddN0 cccc *** jp cc,@rd */ +{ +#ifdef NICENAMES +"jp cc,@rd",16,10, +0x00, +#endif +"jp",OPC_jp,0,{CLASS_CC,CLASS_IR+(ARG_RD),}, + {CLASS_BIT+1,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,152}, + + +/* 0101 1110 0000 cccc address_dst *** jp cc,address_dst */ +{ +#ifdef NICENAMES +"jp cc,address_dst",16,7, +0x00, +#endif +"jp",OPC_jp,0,{CLASS_CC,CLASS_DA+(ARG_DST),}, + {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,153}, + + +/* 0101 1110 ddN0 cccc address_dst *** jp cc,address_dst(rd) */ +{ +#ifdef NICENAMES +"jp cc,address_dst(rd)",16,8, +0x00, +#endif +"jp",OPC_jp,0,{CLASS_CC,CLASS_X+(ARG_RD),}, + {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,154}, + + +/* 1110 cccc disp8 *** jr cc,disp8 */ +{ +#ifdef NICENAMES +"jr cc,disp8",16,6, +0x00, +#endif +"jr",OPC_jr,0,{CLASS_CC,CLASS_DISP,}, + {CLASS_BIT+0xe,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,155}, + + +/* 0000 1101 ddN0 0101 imm16 *** ld @rd,imm16 */ +{ +#ifdef NICENAMES +"ld @rd,imm16",16,7, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,156}, + + +/* 0010 1111 ddN0 ssss *** ld @rd,rs */ +{ +#ifdef NICENAMES +"ld @rd,rs",16,8, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,157}, + + +/* 0100 1101 ddN0 0101 address_dst imm16 *** ld address_dst(rd),imm16 */ +{ +#ifdef NICENAMES +"ld address_dst(rd),imm16",16,15, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,158}, + + +/* 0110 1111 ddN0 ssss address_dst *** ld address_dst(rd),rs */ +{ +#ifdef NICENAMES +"ld address_dst(rd),rs",16,12, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,159}, + + +/* 0100 1101 0000 0101 address_dst imm16 *** ld address_dst,imm16 */ +{ +#ifdef NICENAMES +"ld address_dst,imm16",16,14, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,160}, + + +/* 0110 1111 0000 ssss address_dst *** ld address_dst,rs */ +{ +#ifdef NICENAMES +"ld address_dst,rs",16,11, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,161}, + + +/* 0011 0011 ddN0 ssss imm16 *** ld rd(imm16),rs */ +{ +#ifdef NICENAMES +"ld rd(imm16),rs",16,14, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,162}, + + +/* 0111 0011 ddN0 ssss 0000 xxxx 0000 0000 *** ld rd(rx),rs */ +{ +#ifdef NICENAMES +"ld rd(rx),rs",16,14, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,163}, + + +/* 0010 0001 ssN0 dddd *** ld rd,@rs */ +{ +#ifdef NICENAMES +"ld rd,@rs",16,7, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,164}, + + +/* 0110 0001 0000 dddd address_src *** ld rd,address_src */ +{ +#ifdef NICENAMES +"ld rd,address_src",16,9, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,165}, + + +/* 0110 0001 ssN0 dddd address_src *** ld rd,address_src(rs) */ +{ +#ifdef NICENAMES +"ld rd,address_src(rs)",16,10, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,166}, + + +/* 0010 0001 0000 dddd imm16 *** ld rd,imm16 */ +{ +#ifdef NICENAMES +"ld rd,imm16",16,7, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,167}, + + +/* 1010 0001 ssss dddd *** ld rd,rs */ +{ +#ifdef NICENAMES +"ld rd,rs",16,3, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,168}, + + +/* 0011 0001 ssN0 dddd imm16 *** ld rd,rs(imm16) */ +{ +#ifdef NICENAMES +"ld rd,rs(imm16)",16,14, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,169}, + + +/* 0111 0001 ssN0 dddd 0000 xxxx 0000 0000 *** ld rd,rs(rx) */ +{ +#ifdef NICENAMES +"ld rd,rs(rx)",16,14, +0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,170}, + + +/* 0111 0110 0000 dddd address_src *** lda prd,address_src */ +{ +#ifdef NICENAMES +"lda prd,address_src",16,12, +0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,171}, + + +/* 0111 0110 ssN0 dddd address_src *** lda prd,address_src(rs) */ +{ +#ifdef NICENAMES +"lda prd,address_src(rs)",16,13, +0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,172}, + + +/* 0011 0100 ssN0 dddd imm16 *** lda prd,rs(imm16) */ +{ +#ifdef NICENAMES +"lda prd,rs(imm16)",16,15, +0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,173}, + + +/* 0111 0100 ssN0 dddd 0000 xxxx 0000 0000 *** lda prd,rs(rx) */ +{ +#ifdef NICENAMES +"lda prd,rs(rx)",16,15, +0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,174}, + + +/* 0011 0100 0000 dddd disp16 *** ldar prd,disp16 */ +{ +#ifdef NICENAMES +"ldar prd,disp16",16,15, +0x00, +#endif +"ldar",OPC_ldar,0,{CLASS_PR+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,175}, + + +/* 0000 1100 ddN0 0101 imm8 imm8 *** ldb @rd,imm8 */ +{ +#ifdef NICENAMES +"ldb @rd,imm8",8,7, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,176}, + + +/* 0010 1110 ddN0 ssss *** ldb @rd,rbs */ +{ +#ifdef NICENAMES +"ldb @rd,rbs",8,8, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,177}, + + +/* 0100 1100 ddN0 0101 address_dst imm8 imm8 *** ldb address_dst(rd),imm8 */ +{ +#ifdef NICENAMES +"ldb address_dst(rd),imm8",8,15, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,178}, + + +/* 0110 1110 ddN0 ssss address_dst *** ldb address_dst(rd),rbs */ +{ +#ifdef NICENAMES +"ldb address_dst(rd),rbs",8,12, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,179}, + + +/* 0100 1100 0000 0101 address_dst imm8 imm8 *** ldb address_dst,imm8 */ +{ +#ifdef NICENAMES +"ldb address_dst,imm8",8,14, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,180}, + + +/* 0110 1110 0000 ssss address_dst *** ldb address_dst,rbs */ +{ +#ifdef NICENAMES +"ldb address_dst,rbs",8,11, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,181}, + + +/* 0010 0000 ssN0 dddd *** ldb rbd,@rs */ +{ +#ifdef NICENAMES +"ldb rbd,@rs",8,7, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,182}, + + +/* 0110 0000 0000 dddd address_src *** ldb rbd,address_src */ +{ +#ifdef NICENAMES +"ldb rbd,address_src",8,9, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, + + +/* 0110 0000 ssN0 dddd address_src *** ldb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"ldb rbd,address_src(rs)",8,10, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, + + +/* 1100 dddd imm8 *** ldb rbd,imm8 */ +{ +#ifdef NICENAMES +"ldb rbd,imm8",8,5, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,185}, + + +/* 1010 0000 ssss dddd *** ldb rbd,rbs */ +{ +#ifdef NICENAMES +"ldb rbd,rbs",8,3, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,186}, + + +/* 0011 0000 ssN0 dddd imm16 *** ldb rbd,rs(imm16) */ +{ +#ifdef NICENAMES +"ldb rbd,rs(imm16)",8,14, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,187}, + + +/* 0111 0000 ssN0 dddd 0000 xxxx 0000 0000 *** ldb rbd,rs(rx) */ +{ +#ifdef NICENAMES +"ldb rbd,rs(rx)",8,14, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,188}, + + +/* 0011 0010 ddN0 ssss imm16 *** ldb rd(imm16),rbs */ +{ +#ifdef NICENAMES +"ldb rd(imm16),rbs",8,14, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,189}, + + +/* 0111 0010 ddN0 ssss 0000 xxxx 0000 0000 *** ldb rd(rx),rbs */ +{ +#ifdef NICENAMES +"ldb rd(rx),rbs",8,14, +0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,190}, + + +/* 0111 1101 ssss 1ccc *** ldctl ctrl,rs */ +{ +#ifdef NICENAMES +"ldctl ctrl,rs",32,7, +0x00, +#endif +"ldctl",OPC_ldctl,0,{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,191}, + + +/* 0111 1101 dddd 0ccc *** ldctl rd,ctrl */ +{ +#ifdef NICENAMES +"ldctl rd,ctrl",32,7, +0x00, +#endif +"ldctl",OPC_ldctl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,}, + {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,192}, + + +/* 1000 1100 ssss 1001 *** ldctlb ctrl,rbs */ +{ +#ifdef NICENAMES +"ldctlb ctrl,rbs",32,7, +0x3f, +#endif +"ldctlb",OPC_ldctlb,0,{CLASS_CTRL,CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_BIT+9,0,0,0,0,0,},2,2,193}, + + +/* 1000 1100 dddd 0001 *** ldctlb rbd,ctrl */ +{ +#ifdef NICENAMES +"ldctlb rbd,ctrl",32,7, +0x00, +#endif +"ldctlb",OPC_ldctlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_CTRL,}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+1,0,0,0,0,0,},2,2,194}, + + +/* 1011 1011 ssN0 1001 0000 rrrr ddN0 1000 *** ldd @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldd @rd,@rs,rr",16,11, +0x04, +#endif +"ldd",OPC_ldd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,195}, + + +/* 1011 1010 ssN0 1001 0000 rrrr ddN0 1000 *** lddb @rd,@rs,rr */ +{ +#ifdef NICENAMES +"lddb @rd,@rs,rr",8,11, +0x04, +#endif +"lddb",OPC_lddb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,196}, + + +/* 1011 1011 ssN0 1001 0000 rrrr ddN0 0000 *** lddr @rd,@rs,rr */ +{ +#ifdef NICENAMES +"lddr @rd,@rs,rr",16,11, +0x04, +#endif +"lddr",OPC_lddr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,197}, + + +/* 1011 1010 ssN0 1001 0000 rrrr ddN0 0000 *** lddrb @rd,@rs,rr */ +{ +#ifdef NICENAMES +"lddrb @rd,@rs,rr",8,11, +0x04, +#endif +"lddrb",OPC_lddrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,198}, + + +/* 1011 1011 ssN0 0001 0000 rrrr ddN0 1000 *** ldi @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldi @rd,@rs,rr",16,11, +0x04, +#endif +"ldi",OPC_ldi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,199}, + + +/* 1011 1010 ssN0 0001 0000 rrrr ddN0 1000 *** ldib @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldib @rd,@rs,rr",8,11, +0x04, +#endif +"ldib",OPC_ldib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,200}, + + +/* 1011 1011 ssN0 0001 0000 rrrr ddN0 0000 *** ldir @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldir @rd,@rs,rr",16,11, +0x04, +#endif +"ldir",OPC_ldir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,201}, + + +/* 1011 1010 ssN0 0001 0000 rrrr ddN0 0000 *** ldirb @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldirb @rd,@rs,rr",8,11, +0x04, +#endif +"ldirb",OPC_ldirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,202}, + + +/* 1011 1101 dddd imm4 *** ldk rd,imm4 */ +{ +#ifdef NICENAMES +"ldk rd,imm4",16,5, +0x00, +#endif +"ldk",OPC_ldk,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,203}, + + +/* 0001 1101 ddN0 ssss *** ldl @rd,rrs */ +{ +#ifdef NICENAMES +"ldl @rd,rrs",32,11, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,204}, + + +/* 0101 1101 ddN0 ssss address_dst *** ldl address_dst(rd),rrs */ +{ +#ifdef NICENAMES +"ldl address_dst(rd),rrs",32,14, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,205}, + + +/* 0101 1101 0000 ssss address_dst *** ldl address_dst,rrs */ +{ +#ifdef NICENAMES +"ldl address_dst,rrs",32,15, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_DA+(ARG_DST),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,206}, + + +/* 0011 0111 ddN0 ssss imm16 *** ldl rd(imm16),rrs */ +{ +#ifdef NICENAMES +"ldl rd(imm16),rrs",32,17, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,207}, + + +/* 0111 0111 ddN0 ssss 0000 xxxx 0000 0000 *** ldl rd(rx),rrs */ +{ +#ifdef NICENAMES +"ldl rd(rx),rrs",32,17, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,208}, + + +/* 0001 0100 ssN0 dddd *** ldl rrd,@rs */ +{ +#ifdef NICENAMES +"ldl rrd,@rs",32,11, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,209}, + + +/* 0101 0100 0000 dddd address_src *** ldl rrd,address_src */ +{ +#ifdef NICENAMES +"ldl rrd,address_src",32,12, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,210}, + + +/* 0101 0100 ssN0 dddd address_src *** ldl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"ldl rrd,address_src(rs)",32,13, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,211}, + + +/* 0001 0100 0000 dddd imm32 *** ldl rrd,imm32 */ +{ +#ifdef NICENAMES +"ldl rrd,imm32",32,11, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,212}, + + +/* 1001 0100 ssss dddd *** ldl rrd,rrs */ +{ +#ifdef NICENAMES +"ldl rrd,rrs",32,5, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,213}, + + +/* 0011 0101 ssN0 dddd imm16 *** ldl rrd,rs(imm16) */ +{ +#ifdef NICENAMES +"ldl rrd,rs(imm16)",32,17, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,214}, + + +/* 0111 0101 ssN0 dddd 0000 xxxx 0000 0000 *** ldl rrd,rs(rx) */ +{ +#ifdef NICENAMES +"ldl rrd,rs(rx)",32,17, +0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,215}, + + +/* 0001 1100 ddN0 1001 0000 ssss 0000 imm4m1 *** ldm @rd,rs,n */ +{ +#ifdef NICENAMES +"ldm @rd,rs,n",16,11, +0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,216}, + + +/* 0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst(rd),rs,n */ +{ +#ifdef NICENAMES +"ldm address_dst(rd),rs,n",16,15, +0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,217}, + + +/* 0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst,rs,n */ +{ +#ifdef NICENAMES +"ldm address_dst,rs,n",16,14, +0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,218}, + + +/* 0001 1100 ssN0 0001 0000 dddd 0000 imm4m1 *** ldm rd,@rs,n */ +{ +#ifdef NICENAMES +"ldm rd,@rs,n",16,11, +0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,219}, + + +/* 0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src(rs),n */ +{ +#ifdef NICENAMES +"ldm rd,address_src(rs),n",16,15, +0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,220}, + + +/* 0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src,n */ +{ +#ifdef NICENAMES +"ldm rd,address_src,n",16,14, +0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,221}, + + +/* 0011 1001 ssN0 0000 *** ldps @rs */ +{ +#ifdef NICENAMES +"ldps @rs",16,12, +0x3f, +#endif +"ldps",OPC_ldps,0,{CLASS_IR+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,222}, + + +/* 0111 1001 0000 0000 address_src *** ldps address_src */ +{ +#ifdef NICENAMES +"ldps address_src",16,16, +0x3f, +#endif +"ldps",OPC_ldps,0,{CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,223}, + + +/* 0111 1001 ssN0 0000 address_src *** ldps address_src(rs) */ +{ +#ifdef NICENAMES +"ldps address_src(rs)",16,17, +0x3f, +#endif +"ldps",OPC_ldps,0,{CLASS_X+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,224}, + + +/* 0011 0011 0000 ssss disp16 *** ldr disp16,rs */ +{ +#ifdef NICENAMES +"ldr disp16,rs",16,14, +0x00, +#endif +"ldr",OPC_ldr,0,{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,225}, + + +/* 0011 0001 0000 dddd disp16 *** ldr rd,disp16 */ +{ +#ifdef NICENAMES +"ldr rd,disp16",16,14, +0x00, +#endif +"ldr",OPC_ldr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,226}, + + +/* 0011 0010 0000 ssss disp16 *** ldrb disp16,rbs */ +{ +#ifdef NICENAMES +"ldrb disp16,rbs",8,14, +0x00, +#endif +"ldrb",OPC_ldrb,0,{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,227}, + + +/* 0011 0000 0000 dddd disp16 *** ldrb rbd,disp16 */ +{ +#ifdef NICENAMES +"ldrb rbd,disp16",8,14, +0x00, +#endif +"ldrb",OPC_ldrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,228}, + + +/* 0011 0111 0000 ssss disp16 *** ldrl disp16,rrs */ +{ +#ifdef NICENAMES +"ldrl disp16,rrs",32,17, +0x00, +#endif +"ldrl",OPC_ldrl,0,{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,229}, + + +/* 0011 0101 0000 dddd disp16 *** ldrl rrd,disp16 */ +{ +#ifdef NICENAMES +"ldrl rrd,disp16",32,17, +0x00, +#endif +"ldrl",OPC_ldrl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,230}, + + +/* 0111 1011 0000 1010 *** mbit */ +{ +#ifdef NICENAMES +"mbit",16,7, +0x38, +#endif +"mbit",OPC_mbit,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0xa,0,0,0,0,0,},0,2,231}, + + +/* 0111 1011 dddd 1101 *** mreq rd */ +{ +#ifdef NICENAMES +"mreq rd",16,12, +0x18, +#endif +"mreq",OPC_mreq,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,0,0,0,0,0,},1,2,232}, + + +/* 0111 1011 0000 1001 *** mres */ +{ +#ifdef NICENAMES +"mres",16,5, +0x00, +#endif +"mres",OPC_mres,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,233}, + + +/* 0111 1011 0000 1000 *** mset */ +{ +#ifdef NICENAMES +"mset",16,5, +0x00, +#endif +"mset",OPC_mset,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,234}, + + +/* 0001 1001 ssN0 dddd *** mult rrd,@rs */ +{ +#ifdef NICENAMES +"mult rrd,@rs",16,70, +0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,235}, + + +/* 0101 1001 0000 dddd address_src *** mult rrd,address_src */ +{ +#ifdef NICENAMES +"mult rrd,address_src",16,70, +0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,236}, + + +/* 0101 1001 ssN0 dddd address_src *** mult rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"mult rrd,address_src(rs)",16,70, +0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,237}, + + +/* 0001 1001 0000 dddd imm16 *** mult rrd,imm16 */ +{ +#ifdef NICENAMES +"mult rrd,imm16",16,70, +0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,238}, + + +/* 1001 1001 ssss dddd *** mult rrd,rs */ +{ +#ifdef NICENAMES +"mult rrd,rs",16,70, +0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,239}, + + +/* 0001 1000 ssN0 dddd *** multl rqd,@rs */ +{ +#ifdef NICENAMES +"multl rqd,@rs",32,282, +0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,240}, + + +/* 0101 1000 0000 dddd address_src *** multl rqd,address_src */ +{ +#ifdef NICENAMES +"multl rqd,address_src",32,282, +0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,241}, + + +/* 0101 1000 ssN0 dddd address_src *** multl rqd,address_src(rs) */ +{ +#ifdef NICENAMES +"multl rqd,address_src(rs)",32,282, +0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,242}, + + +/* 0001 1000 0000 dddd imm32 *** multl rqd,imm32 */ +{ +#ifdef NICENAMES +"multl rqd,imm32",32,282, +0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,243}, + + +/* 1001 1000 ssss dddd *** multl rqd,rrs */ +{ +#ifdef NICENAMES +"multl rqd,rrs",32,282, +0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,244}, + + +/* 0000 1101 ddN0 0010 *** neg @rd */ +{ +#ifdef NICENAMES +"neg @rd",16,12, +0x3c, +#endif +"neg",OPC_neg,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,245}, + + +/* 0100 1101 0000 0010 address_dst *** neg address_dst */ +{ +#ifdef NICENAMES +"neg address_dst",16,15, +0x3c, +#endif +"neg",OPC_neg,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,246}, + + +/* 0100 1101 ddN0 0010 address_dst *** neg address_dst(rd) */ +{ +#ifdef NICENAMES +"neg address_dst(rd)",16,16, +0x3c, +#endif +"neg",OPC_neg,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,247}, + + +/* 1000 1101 dddd 0010 *** neg rd */ +{ +#ifdef NICENAMES +"neg rd",16,7, +0x3c, +#endif +"neg",OPC_neg,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,248}, + + +/* 0000 1100 ddN0 0010 *** negb @rd */ +{ +#ifdef NICENAMES +"negb @rd",8,12, +0x3c, +#endif +"negb",OPC_negb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,249}, + + +/* 0100 1100 0000 0010 address_dst *** negb address_dst */ +{ +#ifdef NICENAMES +"negb address_dst",8,15, +0x3c, +#endif +"negb",OPC_negb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,250}, + + +/* 0100 1100 ddN0 0010 address_dst *** negb address_dst(rd) */ +{ +#ifdef NICENAMES +"negb address_dst(rd)",8,16, +0x3c, +#endif +"negb",OPC_negb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,251}, + + +/* 1000 1100 dddd 0010 *** negb rbd */ +{ +#ifdef NICENAMES +"negb rbd",8,7, +0x3c, +#endif +"negb",OPC_negb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,252}, + + +/* 1000 1101 0000 0111 *** nop */ +{ +#ifdef NICENAMES +"nop",16,7, +0x00, +#endif +"nop",OPC_nop,0,{0}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,253}, + + +/* 0000 0101 ssN0 dddd *** or rd,@rs */ +{ +#ifdef NICENAMES +"or rd,@rs",16,7, +0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,254}, + + +/* 0100 0101 0000 dddd address_src *** or rd,address_src */ +{ +#ifdef NICENAMES +"or rd,address_src",16,9, +0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,255}, + + +/* 0100 0101 ssN0 dddd address_src *** or rd,address_src(rs) */ +{ +#ifdef NICENAMES +"or rd,address_src(rs)",16,10, +0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,256}, + + +/* 0000 0101 0000 dddd imm16 *** or rd,imm16 */ +{ +#ifdef NICENAMES +"or rd,imm16",16,7, +0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,257}, + + +/* 1000 0101 ssss dddd *** or rd,rs */ +{ +#ifdef NICENAMES +"or rd,rs",16,4, +0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,258}, + + +/* 0000 0100 ssN0 dddd *** orb rbd,@rs */ +{ +#ifdef NICENAMES +"orb rbd,@rs",8,7, +0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,259}, + + +/* 0100 0100 0000 dddd address_src *** orb rbd,address_src */ +{ +#ifdef NICENAMES +"orb rbd,address_src",8,9, +0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,260}, + + +/* 0100 0100 ssN0 dddd address_src *** orb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"orb rbd,address_src(rs)",8,10, +0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,261}, + + +/* 0000 0100 0000 dddd imm8 imm8 *** orb rbd,imm8 */ +{ +#ifdef NICENAMES +"orb rbd,imm8",8,7, +0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,262}, + + +/* 1000 0100 ssss dddd *** orb rbd,rbs */ +{ +#ifdef NICENAMES +"orb rbd,rbs",8,4, +0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,263}, + + +/* 0011 1111 ddN0 ssss *** out @rd,rs */ +{ +#ifdef NICENAMES +"out @rd,rs",16,0, +0x04, +#endif +"out",OPC_out,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,264}, + + +/* 0011 1011 ssss 0110 imm16 *** out imm16,rs */ +{ +#ifdef NICENAMES +"out imm16,rs",16,0, +0x04, +#endif +"out",OPC_out,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,265}, + + +/* 0011 1110 ddN0 ssss *** outb @rd,rbs */ +{ +#ifdef NICENAMES +"outb @rd,rbs",8,0, +0x04, +#endif +"outb",OPC_outb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,266}, + + +/* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */ +{ +#ifdef NICENAMES +"outb imm16,rbs",8,0, +0x04, +#endif +"outb",OPC_outb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,267}, + + +/* 0011 1011 ssN0 1010 0000 aaaa ddN0 1000 *** outd @rd,@rs,ra */ +{ +#ifdef NICENAMES +"outd @rd,@rs,ra",16,0, +0x04, +#endif +"outd",OPC_outd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,268}, + + +/* 0011 1010 ssN0 1010 0000 aaaa ddN0 1000 *** outdb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"outdb @rd,@rs,rba",16,0, +0x04, +#endif +"outdb",OPC_outdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,269}, + + +/* 0011 1011 ssN0 0010 0000 aaaa ddN0 1000 *** outi @rd,@rs,ra */ +{ +#ifdef NICENAMES +"outi @rd,@rs,ra",16,0, +0x04, +#endif +"outi",OPC_outi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,270}, + + +/* 0011 1010 ssN0 0010 0000 aaaa ddN0 1000 *** outib @rd,@rs,ra */ +{ +#ifdef NICENAMES +"outib @rd,@rs,ra",16,0, +0x04, +#endif +"outib",OPC_outib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,271}, + + +/* 0011 1010 ssN0 0010 0000 aaaa ddN0 0000 *** outibr @rd,@rs,ra */ +{ +#ifdef NICENAMES +"outibr @rd,@rs,ra",16,0, +0x04, +#endif +"outibr",OPC_outibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,272}, + + +/* 0001 0111 ssN0 ddN0 *** pop @rd,@rs */ +{ +#ifdef NICENAMES +"pop @rd,@rs",16,12, +0x00, +#endif +"pop",OPC_pop,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,273}, + + +/* 0101 0111 ssN0 ddN0 address_dst *** pop address_dst(rd),@rs */ +{ +#ifdef NICENAMES +"pop address_dst(rd),@rs",16,16, +0x00, +#endif +"pop",OPC_pop,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,274}, + + +/* 0101 0111 ssN0 0000 address_dst *** pop address_dst,@rs */ +{ +#ifdef NICENAMES +"pop address_dst,@rs",16,16, +0x00, +#endif +"pop",OPC_pop,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,275}, + + +/* 1001 0111 ssN0 dddd *** pop rd,@rs */ +{ +#ifdef NICENAMES +"pop rd,@rs",16,8, +0x00, +#endif +"pop",OPC_pop,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,276}, + + +/* 0001 0101 ssN0 ddN0 *** popl @rd,@rs */ +{ +#ifdef NICENAMES +"popl @rd,@rs",32,19, +0x00, +#endif +"popl",OPC_popl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,277}, + + +/* 0101 0101 ssN0 ddN0 address_dst *** popl address_dst(rd),@rs */ +{ +#ifdef NICENAMES +"popl address_dst(rd),@rs",32,23, +0x00, +#endif +"popl",OPC_popl,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,278}, + + +/* 0101 0101 ssN0 0000 address_dst *** popl address_dst,@rs */ +{ +#ifdef NICENAMES +"popl address_dst,@rs",32,23, +0x00, +#endif +"popl",OPC_popl,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,279}, + + +/* 1001 0101 ssN0 dddd *** popl rrd,@rs */ +{ +#ifdef NICENAMES +"popl rrd,@rs",32,12, +0x00, +#endif +"popl",OPC_popl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,280}, + + +/* 0001 0011 ddN0 ssN0 *** push @rd,@rs */ +{ +#ifdef NICENAMES +"push @rd,@rs",16,13, +0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,281}, + + +/* 0101 0011 ddN0 0000 address_src *** push @rd,address_src */ +{ +#ifdef NICENAMES +"push @rd,address_src",16,14, +0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,282}, + + +/* 0101 0011 ddN0 ssN0 address_src *** push @rd,address_src(rs) */ +{ +#ifdef NICENAMES +"push @rd,address_src(rs)",16,14, +0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,283}, + + +/* 0000 1101 ddN0 1001 imm16 *** push @rd,imm16 */ +{ +#ifdef NICENAMES +"push @rd,imm16",16,12, +0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,284}, + + +/* 1001 0011 ddN0 ssss *** push @rd,rs */ +{ +#ifdef NICENAMES +"push @rd,rs",16,9, +0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,285}, + + +/* 0001 0001 ddN0 ssN0 *** pushl @rd,@rs */ +{ +#ifdef NICENAMES +"pushl @rd,@rs",32,20, +0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,286}, + + +/* 0101 0001 ddN0 0000 address_src *** pushl @rd,address_src */ +{ +#ifdef NICENAMES +"pushl @rd,address_src",32,21, +0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,287}, + + +/* 0101 0001 ddN0 ssN0 address_src *** pushl @rd,address_src(rs) */ +{ +#ifdef NICENAMES +"pushl @rd,address_src(rs)",32,21, +0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,288}, + + +/* 1001 0001 ddN0 ssss *** pushl @rd,rrs */ +{ +#ifdef NICENAMES +"pushl @rd,rrs",32,12, +0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,289}, + + +/* 0010 0011 ddN0 imm4 *** res @rd,imm4 */ +{ +#ifdef NICENAMES +"res @rd,imm4",16,11, +0x00, +#endif +"res",OPC_res,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,290}, + + +/* 0110 0011 ddN0 imm4 address_dst *** res address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"res address_dst(rd),imm4",16,14, +0x00, +#endif +"res",OPC_res,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,291}, + + +/* 0110 0011 0000 imm4 address_dst *** res address_dst,imm4 */ +{ +#ifdef NICENAMES +"res address_dst,imm4",16,13, +0x00, +#endif +"res",OPC_res,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,292}, + + +/* 1010 0011 dddd imm4 *** res rd,imm4 */ +{ +#ifdef NICENAMES +"res rd,imm4",16,4, +0x00, +#endif +"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,293}, + + +/* 0010 0011 0000 ssss 0000 dddd 0000 0000 *** res rd,rs */ +{ +#ifdef NICENAMES +"res rd,rs",16,10, +0x00, +#endif +"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,294}, + + +/* 0010 0010 ddN0 imm4 *** resb @rd,imm4 */ +{ +#ifdef NICENAMES +"resb @rd,imm4",8,11, +0x00, +#endif +"resb",OPC_resb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,295}, + + +/* 0110 0010 ddN0 imm4 address_dst *** resb address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"resb address_dst(rd),imm4",8,14, +0x00, +#endif +"resb",OPC_resb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,296}, + + +/* 0110 0010 0000 imm4 address_dst *** resb address_dst,imm4 */ +{ +#ifdef NICENAMES +"resb address_dst,imm4",8,13, +0x00, +#endif +"resb",OPC_resb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,297}, + + +/* 1010 0010 dddd imm4 *** resb rbd,imm4 */ +{ +#ifdef NICENAMES +"resb rbd,imm4",8,4, +0x00, +#endif +"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,298}, + + +/* 0010 0010 0000 ssss 0000 dddd 0000 0000 *** resb rbd,rs */ +{ +#ifdef NICENAMES +"resb rbd,rs",8,10, +0x00, +#endif +"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,299}, + + +/* 1000 1101 flags 0011 *** resflg flags */ +{ +#ifdef NICENAMES +"resflg flags",16,7, +0x3c, +#endif +"resflg",OPC_resflg,0,{CLASS_FLAGS,}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+3,0,0,0,0,0,},1,2,300}, + + +/* 1001 1110 0000 cccc *** ret cc */ +{ +#ifdef NICENAMES +"ret cc",16,10, +0x00, +#endif +"ret",OPC_ret,0,{CLASS_CC,}, + {CLASS_BIT+9,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,301}, + + +/* 1011 0011 dddd 00I0 *** rl rd,imm1or2 */ +{ +#ifdef NICENAMES +"rl rd,imm1or2",16,6, +0x3c, +#endif +"rl",OPC_rl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,302}, + + +/* 1011 0010 dddd 00I0 *** rlb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rlb rbd,imm1or2",8,6, +0x3c, +#endif +"rlb",OPC_rlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,303}, + + +/* 1011 0011 dddd 10I0 *** rlc rd,imm1or2 */ +{ +#ifdef NICENAMES +"rlc rd,imm1or2",16,6, +0x3c, +#endif +"rlc",OPC_rlc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,304}, + + +/* 1011 0010 dddd 10I0 *** rlcb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rlcb rbd,imm1or2",8,9, +0x10, +#endif +"rlcb",OPC_rlcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,305}, + + +/* 1011 1110 aaaa bbbb *** rldb rbb,rba */ +{ +#ifdef NICENAMES +"rldb rbb,rba",8,9, +0x10, +#endif +"rldb",OPC_rldb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+0xe,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,306}, + + +/* 1011 0011 dddd 01I0 *** rr rd,imm1or2 */ +{ +#ifdef NICENAMES +"rr rd,imm1or2",16,6, +0x3c, +#endif +"rr",OPC_rr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,307}, + + +/* 1011 0010 dddd 01I0 *** rrb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rrb rbd,imm1or2",8,6, +0x3c, +#endif +"rrb",OPC_rrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,308}, + + +/* 1011 0011 dddd 11I0 *** rrc rd,imm1or2 */ +{ +#ifdef NICENAMES +"rrc rd,imm1or2",16,6, +0x3c, +#endif +"rrc",OPC_rrc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,309}, + + +/* 1011 0010 dddd 11I0 *** rrcb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rrcb rbd,imm1or2",8,9, +0x10, +#endif +"rrcb",OPC_rrcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,310}, + + +/* 1011 1100 aaaa bbbb *** rrdb rbb,rba */ +{ +#ifdef NICENAMES +"rrdb rbb,rba",8,9, +0x10, +#endif +"rrdb",OPC_rrdb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+0xc,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,311}, + + +/* 0011 0110 imm8 *** rsvd36 */ +{ +#ifdef NICENAMES +"rsvd36",8,10, +0x00, +#endif +"rsvd36",OPC_rsvd36,0,{0}, + {CLASS_BIT+3,CLASS_BIT+6,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,312}, + + +/* 0011 1000 imm8 *** rsvd38 */ +{ +#ifdef NICENAMES +"rsvd38",8,10, +0x00, +#endif +"rsvd38",OPC_rsvd38,0,{0}, + {CLASS_BIT+3,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,313}, + + +/* 0111 1000 imm8 *** rsvd78 */ +{ +#ifdef NICENAMES +"rsvd78",8,10, +0x00, +#endif +"rsvd78",OPC_rsvd78,0,{0}, + {CLASS_BIT+7,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,314}, + + +/* 0111 1110 imm8 *** rsvd7e */ +{ +#ifdef NICENAMES +"rsvd7e",8,10, +0x00, +#endif +"rsvd7e",OPC_rsvd7e,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,315}, + + +/* 1001 1101 imm8 *** rsvd9d */ +{ +#ifdef NICENAMES +"rsvd9d",8,10, +0x00, +#endif +"rsvd9d",OPC_rsvd9d,0,{0}, + {CLASS_BIT+9,CLASS_BIT+0xd,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,316}, + + +/* 1001 1111 imm8 *** rsvd9f */ +{ +#ifdef NICENAMES +"rsvd9f",8,10, +0x00, +#endif +"rsvd9f",OPC_rsvd9f,0,{0}, + {CLASS_BIT+9,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,317}, + + +/* 1011 1001 imm8 *** rsvdb9 */ +{ +#ifdef NICENAMES +"rsvdb9",8,10, +0x00, +#endif +"rsvdb9",OPC_rsvdb9,0,{0}, + {CLASS_BIT+0xb,CLASS_BIT+9,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,318}, + + +/* 1011 1111 imm8 *** rsvdbf */ +{ +#ifdef NICENAMES +"rsvdbf",8,10, +0x00, +#endif +"rsvdbf",OPC_rsvdbf,0,{0}, + {CLASS_BIT+0xb,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,319}, + + +/* 1011 0111 ssss dddd *** sbc rd,rs */ +{ +#ifdef NICENAMES +"sbc rd,rs",16,5, +0x3c, +#endif +"sbc",OPC_sbc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,320}, + + +/* 1011 0110 ssss dddd *** sbcb rbd,rbs */ +{ +#ifdef NICENAMES +"sbcb rbd,rbs",8,5, +0x3f, +#endif +"sbcb",OPC_sbcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,321}, + + +/* 0111 1111 imm8 *** sc imm8 */ +{ +#ifdef NICENAMES +"sc imm8",8,33, +0x3f, +#endif +"sc",OPC_sc,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+7,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,322}, + + +/* 1011 0011 dddd 1011 0000 ssss 0000 0000 *** sda rd,rs */ +{ +#ifdef NICENAMES +"sda rd,rs",16,15, +0x3c, +#endif +"sda",OPC_sda,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,323}, + + +/* 1011 0010 dddd 1011 0000 ssss 0000 0000 *** sdab rbd,rs */ +{ +#ifdef NICENAMES +"sdab rbd,rs",8,15, +0x3c, +#endif +"sdab",OPC_sdab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,324}, + + +/* 1011 0011 dddd 1111 0000 ssss 0000 0000 *** sdal rrd,rs */ +{ +#ifdef NICENAMES +"sdal rrd,rs",32,15, +0x3c, +#endif +"sdal",OPC_sdal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,325}, + + +/* 1011 0011 dddd 0011 0000 ssss 0000 0000 *** sdl rd,rs */ +{ +#ifdef NICENAMES +"sdl rd,rs",16,15, +0x38, +#endif +"sdl",OPC_sdl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,326}, + + +/* 1011 0010 dddd 0011 0000 ssss 0000 0000 *** sdlb rbd,rs */ +{ +#ifdef NICENAMES +"sdlb rbd,rs",8,15, +0x38, +#endif +"sdlb",OPC_sdlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,327}, + + +/* 1011 0011 dddd 0111 0000 ssss 0000 0000 *** sdll rrd,rs */ +{ +#ifdef NICENAMES +"sdll rrd,rs",32,15, +0x38, +#endif +"sdll",OPC_sdll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,328}, + + +/* 0010 0101 ddN0 imm4 *** set @rd,imm4 */ +{ +#ifdef NICENAMES +"set @rd,imm4",16,11, +0x00, +#endif +"set",OPC_set,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,329}, + + +/* 0110 0101 ddN0 imm4 address_dst *** set address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"set address_dst(rd),imm4",16,14, +0x00, +#endif +"set",OPC_set,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,330}, + + +/* 0110 0101 0000 imm4 address_dst *** set address_dst,imm4 */ +{ +#ifdef NICENAMES +"set address_dst,imm4",16,13, +0x00, +#endif +"set",OPC_set,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,331}, + + +/* 1010 0101 dddd imm4 *** set rd,imm4 */ +{ +#ifdef NICENAMES +"set rd,imm4",16,4, +0x00, +#endif +"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,332}, + + +/* 0010 0101 0000 ssss 0000 dddd 0000 0000 *** set rd,rs */ +{ +#ifdef NICENAMES +"set rd,rs",16,10, +0x00, +#endif +"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,333}, + + +/* 0010 0100 ddN0 imm4 *** setb @rd,imm4 */ +{ +#ifdef NICENAMES +"setb @rd,imm4",8,11, +0x00, +#endif +"setb",OPC_setb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,334}, + + +/* 0110 0100 ddN0 imm4 address_dst *** setb address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"setb address_dst(rd),imm4",8,14, +0x00, +#endif +"setb",OPC_setb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,335}, + + +/* 0110 0100 0000 imm4 address_dst *** setb address_dst,imm4 */ +{ +#ifdef NICENAMES +"setb address_dst,imm4",8,13, +0x00, +#endif +"setb",OPC_setb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,336}, + + +/* 1010 0100 dddd imm4 *** setb rbd,imm4 */ +{ +#ifdef NICENAMES +"setb rbd,imm4",8,4, +0x00, +#endif +"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,337}, + + +/* 0010 0100 0000 ssss 0000 dddd 0000 0000 *** setb rbd,rs */ +{ +#ifdef NICENAMES +"setb rbd,rs",8,10, +0x00, +#endif +"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,338}, + + +/* 1000 1101 flags 0001 *** setflg flags */ +{ +#ifdef NICENAMES +"setflg flags",16,7, +0x3c, +#endif +"setflg",OPC_setflg,0,{CLASS_FLAGS,}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+1,0,0,0,0,0,},1,2,339}, + + +/* 0011 1011 dddd 0101 imm16 *** sin rd,imm16 */ +{ +#ifdef NICENAMES +"sin rd,imm16",8,0, +0x00, +#endif +"sin",OPC_sin,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,340}, + + +/* 0011 1010 dddd 0101 imm16 *** sinb rbd,imm16 */ +{ +#ifdef NICENAMES +"sinb rbd,imm16",8,0, +0x00, +#endif +"sinb",OPC_sinb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,341}, + + +/* 0011 1011 ssN0 1000 0001 aaaa ddN0 1000 *** sind @rd,@rs,ra */ +{ +#ifdef NICENAMES +"sind @rd,@rs,ra",16,0, +0x00, +#endif +"sind",OPC_sind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,342}, + + +/* 0011 1010 ssN0 1000 0001 aaaa ddN0 1000 *** sindb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"sindb @rd,@rs,rba",8,0, +0x00, +#endif +"sindb",OPC_sindb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,343}, + + +/* 0011 1010 ssN0 0001 0000 aaaa ddN0 1000 *** sinib @rd,@rs,ra */ +{ +#ifdef NICENAMES +"sinib @rd,@rs,ra",8,0, +0x00, +#endif +"sinib",OPC_sinib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,344}, + + +/* 0011 1010 ssN0 0001 0000 aaaa ddN0 0000 *** sinibr @rd,@rs,ra */ +{ +#ifdef NICENAMES +"sinibr @rd,@rs,ra",16,0, +0x00, +#endif +"sinibr",OPC_sinibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,345}, + + +/* 1011 0011 dddd 1001 0000 0000 imm8 *** sla rd,imm8 */ +{ +#ifdef NICENAMES +"sla rd,imm8",16,13, +0x3c, +#endif +"sla",OPC_sla,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,346}, + + +/* 1011 0010 dddd 1001 iiii iiii 0000 imm4 *** slab rbd,imm4 */ +{ +#ifdef NICENAMES +"slab rbd,imm4",8,13, +0x3c, +#endif +"slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,347}, + + +/* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */ +{ +#ifdef NICENAMES +"slal rrd,imm8",32,13, +0x3c, +#endif +"slal",OPC_slal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,348}, + + +/* 1011 0011 dddd 0001 0000 0000 imm8 *** sll rd,imm8 */ +{ +#ifdef NICENAMES +"sll rd,imm8",16,13, +0x38, +#endif +"sll",OPC_sll,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,349}, + + +/* 1011 0010 dddd 0001 iiii iiii 0000 imm4 *** sllb rbd,imm4 */ +{ +#ifdef NICENAMES +"sllb rbd,imm4",8,13, +0x38, +#endif +"sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,350}, + + +/* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */ +{ +#ifdef NICENAMES +"slll rrd,imm8",32,13, +0x38, +#endif +"slll",OPC_slll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,351}, + + +/* 0011 1011 ssss 0111 imm16 *** sout imm16,rs */ +{ +#ifdef NICENAMES +"sout imm16,rs",16,0, +0x00, +#endif +"sout",OPC_sout,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,352}, + + +/* 0011 1010 ssss 0111 imm16 *** soutb imm16,rbs */ +{ +#ifdef NICENAMES +"soutb imm16,rbs",8,0, +0x00, +#endif +"soutb",OPC_soutb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,353}, + + +/* 0011 1011 ssN0 1011 0000 aaaa ddN0 1000 *** soutd @rd,@rs,ra */ +{ +#ifdef NICENAMES +"soutd @rd,@rs,ra",16,0, +0x00, +#endif +"soutd",OPC_soutd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,354}, + + +/* 0011 1010 ssN0 1011 0000 aaaa ddN0 1000 *** soutdb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"soutdb @rd,@rs,rba",8,0, +0x00, +#endif +"soutdb",OPC_soutdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,355}, + + +/* 0011 1010 ssN0 0011 0000 aaaa ddN0 1000 *** soutib @rd,@rs,ra */ +{ +#ifdef NICENAMES +"soutib @rd,@rs,ra",8,0, +0x00, +#endif +"soutib",OPC_soutib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,356}, + + +/* 0011 1010 ssN0 0011 0000 aaaa ddN0 0000 *** soutibr @rd,@rs,ra */ +{ +#ifdef NICENAMES +"soutibr @rd,@rs,ra",16,0, +0x00, +#endif +"soutibr",OPC_soutibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,357}, + + +/* 1011 0011 dddd 1001 1111 1111 nim8 *** sra rd,imm8 */ +{ +#ifdef NICENAMES +"sra rd,imm8",16,13, +0x3c, +#endif +"sra",OPC_sra,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,358}, + + +/* 1011 0010 dddd 1001 iiii iiii 1111 nim4 *** srab rbd,imm4 */ +{ +#ifdef NICENAMES +"srab rbd,imm4",8,13, +0x3c, +#endif +"srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,359}, + + +/* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */ +{ +#ifdef NICENAMES +"sral rrd,imm8",32,13, +0x3c, +#endif +"sral",OPC_sral,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,360}, + + +/* 1011 0011 dddd 0001 1111 1111 nim8 *** srl rd,imm8 */ +{ +#ifdef NICENAMES +"srl rd,imm8",16,13, +0x3c, +#endif +"srl",OPC_srl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,361}, + + +/* 1011 0010 dddd 0001 iiii iiii 1111 nim4 *** srlb rbd,imm4 */ +{ +#ifdef NICENAMES +"srlb rbd,imm4",8,13, +0x3c, +#endif +"srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,362}, + + +/* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */ +{ +#ifdef NICENAMES +"srll rrd,imm8",32,13, +0x3c, +#endif +"srll",OPC_srll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,363}, + + +/* 0000 0011 ssN0 dddd *** sub rd,@rs */ +{ +#ifdef NICENAMES +"sub rd,@rs",16,7, +0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,364}, + + +/* 0100 0011 0000 dddd address_src *** sub rd,address_src */ +{ +#ifdef NICENAMES +"sub rd,address_src",16,9, +0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,365}, + + +/* 0100 0011 ssN0 dddd address_src *** sub rd,address_src(rs) */ +{ +#ifdef NICENAMES +"sub rd,address_src(rs)",16,10, +0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,366}, + + +/* 0000 0011 0000 dddd imm16 *** sub rd,imm16 */ +{ +#ifdef NICENAMES +"sub rd,imm16",16,7, +0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,367}, + + +/* 1000 0011 ssss dddd *** sub rd,rs */ +{ +#ifdef NICENAMES +"sub rd,rs",16,4, +0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,368}, + + +/* 0000 0010 ssN0 dddd *** subb rbd,@rs */ +{ +#ifdef NICENAMES +"subb rbd,@rs",8,7, +0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,369}, + + +/* 0100 0010 0000 dddd address_src *** subb rbd,address_src */ +{ +#ifdef NICENAMES +"subb rbd,address_src",8,9, +0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,370}, + + +/* 0100 0010 ssN0 dddd address_src *** subb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"subb rbd,address_src(rs)",8,10, +0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,371}, + + +/* 0000 0010 0000 dddd imm8 imm8 *** subb rbd,imm8 */ +{ +#ifdef NICENAMES +"subb rbd,imm8",8,7, +0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,372}, + + +/* 1000 0010 ssss dddd *** subb rbd,rbs */ +{ +#ifdef NICENAMES +"subb rbd,rbs",8,4, +0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,373}, + + +/* 0001 0010 ssN0 dddd *** subl rrd,@rs */ +{ +#ifdef NICENAMES +"subl rrd,@rs",32,14, +0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,374}, + + +/* 0101 0010 0000 dddd address_src *** subl rrd,address_src */ +{ +#ifdef NICENAMES +"subl rrd,address_src",32,15, +0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,375}, + + +/* 0101 0010 ssN0 dddd address_src *** subl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"subl rrd,address_src(rs)",32,16, +0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,376}, + + +/* 0001 0010 0000 dddd imm32 *** subl rrd,imm32 */ +{ +#ifdef NICENAMES +"subl rrd,imm32",32,14, +0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,377}, + + +/* 1001 0010 ssss dddd *** subl rrd,rrs */ +{ +#ifdef NICENAMES +"subl rrd,rrs",32,8, +0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,378}, + + +/* 1010 1111 dddd cccc *** tcc cc,rd */ +{ +#ifdef NICENAMES +"tcc cc,rd",16,5, +0x00, +#endif +"tcc",OPC_tcc,0,{CLASS_CC,CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+0xa,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,379}, + + +/* 1010 1110 dddd cccc *** tccb cc,rbd */ +{ +#ifdef NICENAMES +"tccb cc,rbd",8,5, +0x00, +#endif +"tccb",OPC_tccb,0,{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+0xa,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,380}, + + +/* 0000 1101 ddN0 0100 *** test @rd */ +{ +#ifdef NICENAMES +"test @rd",16,8, +0x18, +#endif +"test",OPC_test,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,381}, + + +/* 0100 1101 0000 0100 address_dst *** test address_dst */ +{ +#ifdef NICENAMES +"test address_dst",16,11, +0x00, +#endif +"test",OPC_test,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,382}, + + +/* 0100 1101 ddN0 0100 address_dst *** test address_dst(rd) */ +{ +#ifdef NICENAMES +"test address_dst(rd)",16,12, +0x00, +#endif +"test",OPC_test,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,383}, + + +/* 1000 1101 dddd 0100 *** test rd */ +{ +#ifdef NICENAMES +"test rd",16,7, +0x00, +#endif +"test",OPC_test,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,384}, + + +/* 0000 1100 ddN0 0100 *** testb @rd */ +{ +#ifdef NICENAMES +"testb @rd",8,8, +0x1c, +#endif +"testb",OPC_testb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,385}, + + +/* 0100 1100 0000 0100 address_dst *** testb address_dst */ +{ +#ifdef NICENAMES +"testb address_dst",8,11, +0x1c, +#endif +"testb",OPC_testb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,386}, + + +/* 0100 1100 ddN0 0100 address_dst *** testb address_dst(rd) */ +{ +#ifdef NICENAMES +"testb address_dst(rd)",8,12, +0x1c, +#endif +"testb",OPC_testb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,387}, + + +/* 1000 1100 dddd 0100 *** testb rbd */ +{ +#ifdef NICENAMES +"testb rbd",8,7, +0x1c, +#endif +"testb",OPC_testb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,388}, + + +/* 0001 1100 ddN0 1000 *** testl @rd */ +{ +#ifdef NICENAMES +"testl @rd",32,13, +0x18, +#endif +"testl",OPC_testl,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,389}, + + +/* 0101 1100 0000 1000 address_dst *** testl address_dst */ +{ +#ifdef NICENAMES +"testl address_dst",32,16, +0x18, +#endif +"testl",OPC_testl,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,390}, + + +/* 0101 1100 ddN0 1000 address_dst *** testl address_dst(rd) */ +{ +#ifdef NICENAMES +"testl address_dst(rd)",32,17, +0x18, +#endif +"testl",OPC_testl,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,391}, + + +/* 1001 1100 dddd 1000 *** testl rrd */ +{ +#ifdef NICENAMES +"testl rrd",32,13, +0x18, +#endif +"testl",OPC_testl,0,{CLASS_REG_LONG+(ARG_RD),}, + {CLASS_BIT+9,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,392}, + + +/* 1011 1000 ddN0 1000 0000 aaaa ssN0 0000 *** trdb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"trdb @rd,@rs,rba",8,25, +0x1c, +#endif +"trdb",OPC_trdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,393}, + + +/* 1011 1000 ddN0 1100 0000 aaaa ssN0 0000 *** trdrb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"trdrb @rd,@rs,rba",8,25, +0x1c, +#endif +"trdrb",OPC_trdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,394}, + + +/* 1011 1000 ddN0 0000 0000 rrrr ssN0 0000 *** trib @rd,@rs,rbr */ +{ +#ifdef NICENAMES +"trib @rd,@rs,rbr",8,25, +0x1c, +#endif +"trib",OPC_trib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,395}, + + +/* 1011 1000 ddN0 0100 0000 rrrr ssN0 0000 *** trirb @rd,@rs,rbr */ +{ +#ifdef NICENAMES +"trirb @rd,@rs,rbr",8,25, +0x1c, +#endif +"trirb",OPC_trirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,396}, + + +/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtdb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtdb @ra,@rb,rbr",8,25, +0x1c, +#endif +"trtdb",OPC_trtdb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,397}, + + +/* 1011 1000 aaN0 1110 0000 rrrr bbN0 1110 *** trtdrb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtdrb @ra,@rb,rbr",8,25, +0x1c, +#endif +"trtdrb",OPC_trtdrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,398}, + + +/* 1011 1000 aaN0 0010 0000 rrrr bbN0 0000 *** trtib @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtib @ra,@rb,rbr",8,25, +0x1c, +#endif +"trtib",OPC_trtib,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,399}, + + +/* 1011 1000 aaN0 0110 0000 rrrr bbN0 1110 *** trtirb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtirb @ra,@rb,rbr",8,25, +0x1c, +#endif +"trtirb",OPC_trtirb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,400}, + + +/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtrb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtrb @ra,@rb,rbr",8,25, +0x1c, +#endif +"trtrb",OPC_trtrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,401}, + + +/* 0000 1101 ddN0 0110 *** tset @rd */ +{ +#ifdef NICENAMES +"tset @rd",16,11, +0x08, +#endif +"tset",OPC_tset,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,402}, + + +/* 0100 1101 0000 0110 address_dst *** tset address_dst */ +{ +#ifdef NICENAMES +"tset address_dst",16,14, +0x08, +#endif +"tset",OPC_tset,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,403}, + + +/* 0100 1101 ddN0 0110 address_dst *** tset address_dst(rd) */ +{ +#ifdef NICENAMES +"tset address_dst(rd)",16,15, +0x08, +#endif +"tset",OPC_tset,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,404}, + + +/* 1000 1101 dddd 0110 *** tset rd */ +{ +#ifdef NICENAMES +"tset rd",16,7, +0x08, +#endif +"tset",OPC_tset,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,405}, + + +/* 0000 1100 ddN0 0110 *** tsetb @rd */ +{ +#ifdef NICENAMES +"tsetb @rd",8,11, +0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,406}, + + +/* 0100 1100 0000 0110 address_dst *** tsetb address_dst */ +{ +#ifdef NICENAMES +"tsetb address_dst",8,14, +0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,407}, + + +/* 0100 1100 ddN0 0110 address_dst *** tsetb address_dst(rd) */ +{ +#ifdef NICENAMES +"tsetb address_dst(rd)",8,15, +0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,408}, + + +/* 1000 1100 dddd 0110 *** tsetb rbd */ +{ +#ifdef NICENAMES +"tsetb rbd",8,7, +0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,409}, + + +/* 0000 1001 ssN0 dddd *** xor rd,@rs */ +{ +#ifdef NICENAMES +"xor rd,@rs",16,7, +0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,410}, + + +/* 0100 1001 0000 dddd address_src *** xor rd,address_src */ +{ +#ifdef NICENAMES +"xor rd,address_src",16,9, +0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,411}, + + +/* 0100 1001 ssN0 dddd address_src *** xor rd,address_src(rs) */ +{ +#ifdef NICENAMES +"xor rd,address_src(rs)",16,10, +0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,412}, + + +/* 0000 1001 0000 dddd imm16 *** xor rd,imm16 */ +{ +#ifdef NICENAMES +"xor rd,imm16",16,7, +0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,413}, + + +/* 1000 1001 ssss dddd *** xor rd,rs */ +{ +#ifdef NICENAMES +"xor rd,rs",16,4, +0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,414}, + + +/* 0000 1000 ssN0 dddd *** xorb rbd,@rs */ +{ +#ifdef NICENAMES +"xorb rbd,@rs",8,7, +0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,415}, + + +/* 0100 1000 0000 dddd address_src *** xorb rbd,address_src */ +{ +#ifdef NICENAMES +"xorb rbd,address_src",8,9, +0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,416}, + + +/* 0100 1000 ssN0 dddd address_src *** xorb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"xorb rbd,address_src(rs)",8,10, +0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,417}, + + +/* 0000 1000 0000 dddd imm8 imm8 *** xorb rbd,imm8 */ +{ +#ifdef NICENAMES +"xorb rbd,imm8",8,7, +0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,418}, + + +/* 1000 1000 ssss dddd *** xorb rbd,rbs */ +{ +#ifdef NICENAMES +"xorb rbd,rbs",8,4, +0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,419}, + + +/* 1000 1000 ssss dddd *** xorb rbd,rbs */ +{ +#ifdef NICENAMES +"xorb rbd,rbs",8,4, +0x01, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,420}, + +/* end marker */ +{ +#ifdef NICENAMES +NULL,0,0, +0, +#endif +NULL,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0} +}; +#endif diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c new file mode 100644 index 0000000..fa85059 --- /dev/null +++ b/opcodes/z8kgen.c @@ -0,0 +1,1330 @@ +/* Copyright 2001, 2002 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ + +/* This program generates z8k-opc.h. */ + +#include +#include "sysdep.h" + +#define BYTE_INFO_LEN 10 + +struct op +{ + char *flags; + int cycles; + char type; + char *bits; + char *name; + char *flavor; +}; + +#define iswhite(x) ((x) == ' ' || (x) == '\t') +struct op opt[] = +{ + "------", 10, 8, "0000 1110 imm8", "ext0e imm8", 0, + "------", 10, 8, "0000 1111 imm8", "ext0f imm8", 0, + "------", 10, 8, "1000 1110 imm8", "ext8e imm8", 0, + "------", 10, 8, "1000 1111 imm8", "ext8f imm8", 0, + + "------", 10, 8, "0011 0110 imm8", "rsvd36", 0, + "------", 10, 8, "0011 1000 imm8", "rsvd38", 0, + "------", 10, 8, "0111 1000 imm8", "rsvd78", 0, + "------", 10, 8, "0111 1110 imm8", "rsvd7e", 0, + + "------", 10, 8, "1001 1101 imm8", "rsvd9d", 0, + "------", 10, 8, "1001 1111 imm8", "rsvd9f", 0, + + "------", 10, 8, "1011 1001 imm8", "rsvdb9", 0, + "------", 10, 8, "1011 1111 imm8", "rsvdbf", 0, + + "---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 1000", "ldd @rd,@rs,rr", 0, + "---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 0000", "lddr @rd,@rs,rr", 0, + "---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 0000", "lddrb @rd,@rs,rr", 0, + "---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 0000", "ldir @rd,@rs,rr", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 0000 0000 rrrr dddd cccc", "cpi rd,@rs,rr,cc", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 0100 0000 rrrr dddd cccc", "cpir rd,@rs,rr,cc", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 1100 0000 rrrr dddd cccc", "cpdr rd,@rs,rr,cc", 0, + "---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 1000", "ldi @rd,@rs,rr", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 1000 0000 rrrr dddd cccc", "cpd rd,@rs,rr,cc", 0, + "---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 0000", "ldirb @rd,@rs,rr", 0, + "---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 1000", "lddb @rd,@rs,rr", 0, + "---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 1000", "ldib @rd,@rs,rr", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 1000 0000 rrrr dddd cccc", "cpdb rbd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 1100 0000 rrrr dddd cccc", "cpdrb rbd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 0000 0000 rrrr dddd cccc", "cpib rbd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 0100 0000 rrrr dddd cccc", "cpirb rbd,@rs,rr,cc", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 1010 0000 rrrr ddN0 cccc", "cpsd @rd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 1010 0000 rrrr ddN0 cccc", "cpsdb @rd,@rs,rr,cc", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdr @rd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdrb @rd,@rs,rr,cc", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 0010 0000 rrrr ddN0 cccc", "cpsi @rd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 0010 0000 rrrr ddN0 cccc", "cpsib @rd,@rs,rr,cc", 0, + "CZSV--", 11, 16, "1011 1011 ssN0 0110 0000 rrrr ddN0 cccc", "cpsir @rd,@rs,rr,cc", 0, + "CZSV--", 11, 8, "1011 1010 ssN0 0110 0000 rrrr ddN0 cccc", "cpsirb @rd,@rs,rr,cc", 0, + + "------", 2, 8, "0011 0110 0000 0000", "bpt", 0, + "CZSV--", 5, 16, "1011 0101 ssss dddd", "adc rd,rs", 0, + "CZSVDH", 5, 8, "1011 0100 ssss dddd", "adcb rbd,rbs", 0, + "CZSV--", 7, 16, "0000 0001 ssN0 dddd", "add rd,@rs", 0, + "CZSV--", 9, 16, "0100 0001 0000 dddd address_src", "add rd,address_src", 0, + "CZSV--", 10, 16, "0100 0001 ssN0 dddd address_src", "add rd,address_src(rs)", 0, + "CZSV--", 7, 16, "0000 0001 0000 dddd imm16", "add rd,imm16", 0, + "CZSV--", 4, 16, "1000 0001 ssss dddd", "add rd,rs", 0, + "CZSVDH", 7, 8, "0000 0000 ssN0 dddd", "addb rbd,@rs", 0, + "CZSVDH", 9, 8, "0100 0000 0000 dddd address_src", "addb rbd,address_src", 0, + "CZSVDH", 10, 8, "0100 0000 ssN0 dddd address_src", "addb rbd,address_src(rs)", 0, + "CZSVDH", 7, 8, "0000 0000 0000 dddd imm8 imm8", "addb rbd,imm8", 0, + "CZSVDH", 4, 8, "1000 0000 ssss dddd", "addb rbd,rbs", 0, + "CZSV--", 14, 32, "0001 0110 ssN0 dddd", "addl rrd,@rs", 0, + "CZSV--", 15, 32, "0101 0110 0000 dddd address_src", "addl rrd,address_src", 0, + "CZSV--", 16, 32, "0101 0110 ssN0 dddd address_src", "addl rrd,address_src(rs)", 0, + "CZSV--", 14, 32, "0001 0110 0000 dddd imm32", "addl rrd,imm32", 0, + "CZSV--", 8, 32, "1001 0110 ssss dddd", "addl rrd,rrs", 0, + + "-ZS---", 7, 16, "0000 0111 ssN0 dddd", "and rd,@rs", 0, + "-ZS---", 9, 16, "0100 0111 0000 dddd address_src", "and rd,address_src", 0, + "-ZS---", 10, 16, "0100 0111 ssN0 dddd address_src", "and rd,address_src(rs)", 0, + "-ZS---", 7, 16, "0000 0111 0000 dddd imm16", "and rd,imm16", 0, + "-ZS---", 4, 16, "1000 0111 ssss dddd", "and rd,rs", 0, + "-ZSP--", 7, 8, "0000 0110 ssN0 dddd", "andb rbd,@rs", 0, + "-ZSP--", 9, 8, "0100 0110 0000 dddd address_src", "andb rbd,address_src", 0, + "-ZSP--", 10, 8, "0100 0110 ssN0 dddd address_src", "andb rbd,address_src(rs)", 0, + "-ZSP--", 7, 8, "0000 0110 0000 dddd imm8 imm8", "andb rbd,imm8", 0, + "-ZSP--", 4, 8, "1000 0110 ssss dddd", "andb rbd,rbs", 0, + + "-Z----", 8, 16, "0010 0111 ddN0 imm4", "bit @rd,imm4", 0, + "-Z----", 11, 16, "0110 0111 ddN0 imm4 address_dst", "bit address_dst(rd),imm4", 0, + "-Z----", 10, 16, "0110 0111 0000 imm4 address_dst", "bit address_dst,imm4", 0, + "-Z----", 4, 16, "1010 0111 dddd imm4", "bit rd,imm4", 0, + "-Z----", 10, 16, "0010 0111 0000 ssss 0000 dddd 0000 0000", "bit rd,rs", 0, + + "-Z----", 8, 8, "0010 0110 ddN0 imm4", "bitb @rd,imm4", 0, + "-Z----", 11, 8, "0110 0110 ddN0 imm4 address_dst", "bitb address_dst(rd),imm4", 0, + "-Z----", 10, 8, "0110 0110 0000 imm4 address_dst", "bitb address_dst,imm4", 0, + "-Z----", 4, 8, "1010 0110 dddd imm4", "bitb rbd,imm4", 0, + "-Z----", 10, 8, "0010 0110 0000 ssss 0000 dddd 0000 0000", "bitb rbd,rs", 0, + + "------", 10, 32, "0001 1111 ddN0 0000", "call @rd", 0, + "------", 12, 32, "0101 1111 0000 0000 address_dst", "call address_dst", 0, + "------", 13, 32, "0101 1111 ddN0 0000 address_dst", "call address_dst(rd)", 0, + "------", 10, 16, "1101 disp12", "calr disp12", 0, + + "------", 8, 16, "0000 1101 ddN0 1000", "clr @rd", 0, + "------", 11, 16, "0100 1101 0000 1000 address_dst", "clr address_dst", 0, + "------", 12, 16, "0100 1101 ddN0 1000 address_dst", "clr address_dst(rd)", 0, + "------", 7, 16, "1000 1101 dddd 1000", "clr rd", 0, + "------", 8, 8, "0000 1100 ddN0 1000", "clrb @rd", 0, + "------", 11, 8, "0100 1100 0000 1000 address_dst", "clrb address_dst", 0, + "------", 12, 8, "0100 1100 ddN0 1000 address_dst", "clrb address_dst(rd)", 0, + "------", 7, 8, "1000 1100 dddd 1000", "clrb rbd", 0, + "-ZS---", 12, 16, "0000 1101 ddN0 0000", "com @rd", 0, + "-ZS---", 15, 16, "0100 1101 0000 0000 address_dst", "com address_dst", 0, + "-ZS---", 16, 16, "0100 1101 ddN0 0000 address_dst", "com address_dst(rd)", 0, + "-ZS---", 7, 16, "1000 1101 dddd 0000", "com rd", 0, + "-ZSP--", 12, 8, "0000 1100 ddN0 0000", "comb @rd", 0, + "-ZSP--", 15, 8, "0100 1100 0000 0000 address_dst", "comb address_dst", 0, + "-ZSP--", 16, 8, "0100 1100 ddN0 0000 address_dst", "comb address_dst(rd)", 0, + "-ZSP--", 7, 8, "1000 1100 dddd 0000", "comb rbd", 0, + "CZSP--", 7, 16, "1000 1101 flags 0101", "comflg flags", 0, + + "CZSV--", 11, 16, "0000 1101 ddN0 0001 imm16", "cp @rd,imm16", 0, + "CZSV--", 15, 16, "0100 1101 ddN0 0001 address_dst imm16", "cp address_dst(rd),imm16", 0, + "CZSV--", 14, 16, "0100 1101 0000 0001 address_dst imm16", "cp address_dst,imm16", 0, + + "CZSV--", 7, 16, "0000 1011 ssN0 dddd", "cp rd,@rs", 0, + "CZSV--", 9, 16, "0100 1011 0000 dddd address_src", "cp rd,address_src", 0, + "CZSV--", 10, 16, "0100 1011 ssN0 dddd address_src", "cp rd,address_src(rs)", 0, + "CZSV--", 7, 16, "0000 1011 0000 dddd imm16", "cp rd,imm16", 0, + "CZSV--", 4, 16, "1000 1011 ssss dddd", "cp rd,rs", 0, + + "CZSV--", 11, 8, "0000 1100 ddN0 0001 imm8 imm8", "cpb @rd,imm8", 0, + "CZSV--", 15, 8, "0100 1100 ddN0 0001 address_dst imm8 imm8", "cpb address_dst(rd),imm8", 0, + "CZSV--", 14, 8, "0100 1100 0000 0001 address_dst imm8 imm8", "cpb address_dst,imm8", 0, + "CZSV--", 7, 8, "0000 1010 ssN0 dddd", "cpb rbd,@rs", 0, + "CZSV--", 9, 8, "0100 1010 0000 dddd address_src", "cpb rbd,address_src", 0, + "CZSV--", 10, 8, "0100 1010 ssN0 dddd address_src", "cpb rbd,address_src(rs)", 0, + "CZSV--", 7, 8, "0000 1010 0000 dddd imm8 imm8", "cpb rbd,imm8", 0, + "CZSV--", 4, 8, "1000 1010 ssss dddd", "cpb rbd,rbs", 0, + + "CZSV--", 14, 32, "0001 0000 ssN0 dddd", "cpl rrd,@rs", 0, + "CZSV--", 15, 32, "0101 0000 0000 dddd address_src", "cpl rrd,address_src", 0, + "CZSV--", 16, 32, "0101 0000 ssN0 dddd address_src", "cpl rrd,address_src(rs)", 0, + "CZSV--", 14, 32, "0001 0000 0000 dddd imm32", "cpl rrd,imm32", 0, + "CZSV--", 8, 32, "1001 0000 ssss dddd", "cpl rrd,rrs", 0, + + "CZS---", 5, 8, "1011 0000 dddd 0000", "dab rbd", 0, + "------", 11, 16, "1111 dddd 0disp7", "dbjnz rbd,disp7", 0, + "-ZSV--", 11, 16, "0010 1011 ddN0 imm4m1", "dec @rd,imm4m1", 0, + "-ZSV--", 14, 16, "0110 1011 ddN0 imm4m1 address_dst", "dec address_dst(rd),imm4m1", 0, + "-ZSV--", 13, 16, "0110 1011 0000 imm4m1 address_dst", "dec address_dst,imm4m1", 0, + "-ZSV--", 4, 16, "1010 1011 dddd imm4m1", "dec rd,imm4m1", 0, + "-ZSV--", 11, 8, "0010 1010 ddN0 imm4m1", "decb @rd,imm4m1", 0, + "-ZSV--", 14, 8, "0110 1010 ddN0 imm4m1 address_dst", "decb address_dst(rd),imm4m1", 0, + "-ZSV--", 13, 8, "0110 1010 0000 imm4m1 address_dst", "decb address_dst,imm4m1", 0, + "-ZSV--", 4, 8, "1010 1010 dddd imm4m1", "decb rbd,imm4m1", 0, + + "------", 7, 16, "0111 1100 0000 00ii", "di i2", 0, + "CZSV--", 107, 16, "0001 1011 ssN0 dddd", "div rrd,@rs", 0, + "CZSV--", 107, 16, "0101 1011 0000 dddd address_src", "div rrd,address_src", 0, + "CZSV--", 107, 16, "0101 1011 ssN0 dddd address_src", "div rrd,address_src(rs)", 0, + "CZSV--", 107, 16, "0001 1011 0000 dddd imm16", "div rrd,imm16", 0, + "CZSV--", 107, 16, "1001 1011 ssss dddd", "div rrd,rs", 0, + "CZSV--", 744, 32, "0001 1010 ssN0 dddd", "divl rqd,@rs", 0, + "CZSV--", 745, 32, "0101 1010 0000 dddd address_src", "divl rqd,address_src", 0, + "CZSV--", 746, 32, "0101 1010 ssN0 dddd address_src", "divl rqd,address_src(rs)", 0, + "CZSV--", 744, 32, "0001 1010 0000 dddd imm32", "divl rqd,imm32", 0, + "CZSV--", 744, 32, "1001 1010 ssss dddd", "divl rqd,rrs", 0, + + "------", 11, 16, "1111 dddd 1disp7", "djnz rd,disp7", 0, + "------", 7, 16, "0111 1100 0000 01ii", "ei i2", 0, + "------", 6, 16, "1010 1101 ssss dddd", "ex rd,rs", 0, + "------", 12, 16, "0010 1101 ssN0 dddd", "ex rd,@rs", 0, + "------", 15, 16, "0110 1101 0000 dddd address_src", "ex rd,address_src", 0, + "------", 16, 16, "0110 1101 ssN0 dddd address_src", "ex rd,address_src(rs)", 0, + + "------", 12, 8, "0010 1100 ssN0 dddd", "exb rbd,@rs", 0, + "------", 15, 8, "0110 1100 0000 dddd address_src", "exb rbd,address_src", 0, + "------", 16, 8, "0110 1100 ssN0 dddd address_src", "exb rbd,address_src(rs)", 0, + "------", 6, 8, "1010 1100 ssss dddd", "exb rbd,rbs", 0, + + "------", 11, 16, "1011 0001 dddd 1010", "exts rrd", 0, + "------", 11, 8, "1011 0001 dddd 0000", "extsb rd", 0, + "------", 11, 32, "1011 0001 dddd 0111", "extsl rqd", 0, + + "------", 8, 16, "0111 1010 0000 0000", "halt", 0, + "------", 10, 16, "0011 1101 ssN0 dddd", "in rd,@rs", 0, + "------", 12, 16, "0011 1101 dddd 0100 imm16", "in rd,imm16", 0, + "------", 12, 8, "0011 1100 ssN0 dddd", "inb rbd,@rs", 0, + "------", 10, 8, "0011 1010 dddd 0100 imm16", "inb rbd,imm16", 0, + "-ZSV--", 11, 16, "0010 1001 ddN0 imm4m1", "inc @rd,imm4m1", 0, + "-ZSV--", 14, 16, "0110 1001 ddN0 imm4m1 address_dst", "inc address_dst(rd),imm4m1", 0, + "-ZSV--", 13, 16, "0110 1001 0000 imm4m1 address_dst", "inc address_dst,imm4m1", 0, + "-ZSV--", 4, 16, "1010 1001 dddd imm4m1", "inc rd,imm4m1", 0, + "-ZSV--", 11, 8, "0010 1000 ddN0 imm4m1", "incb @rd,imm4m1", 0, + "-ZSV--", 14, 8, "0110 1000 ddN0 imm4m1 address_dst", "incb address_dst(rd),imm4m1", 0, + "-ZSV--", 13, 8, "0110 1000 0000 imm4m1 address_dst", "incb address_dst,imm4m1", 0, + "-ZSV--", 4, 8, "1010 1000 dddd imm4m1", "incb rbd,imm4m1", 0, + "---V--", 21, 16, "0011 1011 ssN0 1000 0000 aaaa ddN0 1000", "ind @rd,@rs,ra", 0, + "---V--", 21, 8, "0011 1010 ssN0 1000 0000 aaaa ddN0 1000", "indb @rd,@rs,rba", 0, + "---V--", 21, 8, "0011 1010 ssN0 0000 0000 aaaa ddN0 1000", "inib @rd,@rs,ra", 0, + "---V--", 21, 16, "0011 1010 ssN0 0000 0000 aaaa ddN0 0000", "inibr @rd,@rs,ra", 0, + "CZSVDH", 13, 16, "0111 1011 0000 0000", "iret", 0, + "------", 10, 16, "0001 1110 ddN0 cccc", "jp cc,@rd", 0, + "------", 7, 16, "0101 1110 0000 cccc address_dst", "jp cc,address_dst", 0, + "------", 8, 16, "0101 1110 ddN0 cccc address_dst", "jp cc,address_dst(rd)", 0, + "------", 6, 16, "1110 cccc disp8", "jr cc,disp8", 0, + + "------", 7, 16, "0000 1101 ddN0 0101 imm16", "ld @rd,imm16", 0, + "------", 8, 16, "0010 1111 ddN0 ssss", "ld @rd,rs", 0, + "------", 15, 16, "0100 1101 ddN0 0101 address_dst imm16", "ld address_dst(rd),imm16", 0, + "------", 12, 16, "0110 1111 ddN0 ssss address_dst", "ld address_dst(rd),rs", 0, + "------", 14, 16, "0100 1101 0000 0101 address_dst imm16", "ld address_dst,imm16", 0, + "------", 11, 16, "0110 1111 0000 ssss address_dst", "ld address_dst,rs", 0, + "------", 14, 16, "0011 0011 ddN0 ssss imm16", "ld rd(imm16),rs", 0, + "------", 14, 16, "0111 0011 ddN0 ssss 0000 xxxx 0000 0000", "ld rd(rx),rs", 0, + "------", 7, 16, "0010 0001 ssN0 dddd", "ld rd,@rs", 0, + "------", 9, 16, "0110 0001 0000 dddd address_src", "ld rd,address_src", 0, + "------", 10, 16, "0110 0001 ssN0 dddd address_src", "ld rd,address_src(rs)", 0, + "------", 7, 16, "0010 0001 0000 dddd imm16", "ld rd,imm16", 0, + "------", 3, 16, "1010 0001 ssss dddd", "ld rd,rs", 0, + "------", 14, 16, "0011 0001 ssN0 dddd imm16", "ld rd,rs(imm16)", 0, + "------", 14, 16, "0111 0001 ssN0 dddd 0000 xxxx 0000 0000", "ld rd,rs(rx)", 0, + + "------", 7, 8, "0000 1100 ddN0 0101 imm8 imm8", "ldb @rd,imm8", 0, + "------", 8, 8, "0010 1110 ddN0 ssss", "ldb @rd,rbs", 0, + "------", 15, 8, "0100 1100 ddN0 0101 address_dst imm8 imm8", "ldb address_dst(rd),imm8", 0, + "------", 12, 8, "0110 1110 ddN0 ssss address_dst", "ldb address_dst(rd),rbs", 0, + "------", 14, 8, "0100 1100 0000 0101 address_dst imm8 imm8", "ldb address_dst,imm8", 0, + "------", 11, 8, "0110 1110 0000 ssss address_dst", "ldb address_dst,rbs", 0, + "------", 14, 8, "0011 0010 ddN0 ssss imm16", "ldb rd(imm16),rbs", 0, + "------", 14, 8, "0111 0010 ddN0 ssss 0000 xxxx 0000 0000", "ldb rd(rx),rbs", 0, + "------", 7, 8, "0010 0000 ssN0 dddd", "ldb rbd,@rs", 0, + "------", 9, 8, "0110 0000 0000 dddd address_src", "ldb rbd,address_src", 0, + "------", 10, 8, "0110 0000 ssN0 dddd address_src", "ldb rbd,address_src(rs)", 0, + "------", 5, 8, "1100 dddd imm8", "ldb rbd,imm8", 0, + "------", 3, 8, "1010 0000 ssss dddd", "ldb rbd,rbs", 0, + "------", 14, 8, "0011 0000 ssN0 dddd imm16", "ldb rbd,rs(imm16)", 0, + "------", 14, 8, "0111 0000 ssN0 dddd 0000 xxxx 0000 0000", "ldb rbd,rs(rx)", 0, + + "------", 11, 32, "0001 1101 ddN0 ssss", "ldl @rd,rrs", 0, + "------", 14, 32, "0101 1101 ddN0 ssss address_dst", "ldl address_dst(rd),rrs", 0, + "------", 15, 32, "0101 1101 0000 ssss address_dst", "ldl address_dst,rrs", 0, + "------", 17, 32, "0011 0111 ddN0 ssss imm16", "ldl rd(imm16),rrs", 0, + "------", 17, 32, "0111 0111 ddN0 ssss 0000 xxxx 0000 0000", "ldl rd(rx),rrs", 0, + "------", 11, 32, "0001 0100 ssN0 dddd", "ldl rrd,@rs", 0, + "------", 12, 32, "0101 0100 0000 dddd address_src", "ldl rrd,address_src", 0, + "------", 13, 32, "0101 0100 ssN0 dddd address_src", "ldl rrd,address_src(rs)", 0, + "------", 11, 32, "0001 0100 0000 dddd imm32", "ldl rrd,imm32", 0, + "------", 5, 32, "1001 0100 ssss dddd", "ldl rrd,rrs", 0, + "------", 17, 32, "0011 0101 ssN0 dddd imm16", "ldl rrd,rs(imm16)", 0, + "------", 17, 32, "0111 0101 ssN0 dddd 0000 xxxx 0000 0000", "ldl rrd,rs(rx)", 0, + + "------", 12, 16, "0111 0110 0000 dddd address_src", "lda prd,address_src", 0, + "------", 13, 16, "0111 0110 ssN0 dddd address_src", "lda prd,address_src(rs)", 0, + "------", 15, 16, "0011 0100 ssN0 dddd imm16", "lda prd,rs(imm16)", 0, + "------", 15, 16, "0111 0100 ssN0 dddd 0000 xxxx 0000 0000", "lda prd,rs(rx)", 0, + "------", 15, 16, "0011 0100 0000 dddd disp16", "ldar prd,disp16", 0, + "------", 7, 32, "0111 1101 ssss 1ccc", "ldctl ctrl,rs", 0, + "------", 7, 32, "0111 1101 dddd 0ccc", "ldctl rd,ctrl", 0, + + "------", 5, 16, "1011 1101 dddd imm4", "ldk rd,imm4", 0, + + "------", 11, 16, "0001 1100 ddN0 1001 0000 ssss 0000 imm4m1", "ldm @rd,rs,n", 0, + "------", 15, 16, "0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst", "ldm address_dst(rd),rs,n", 0, + "------", 14, 16, "0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst", "ldm address_dst,rs,n", 0, + "------", 11, 16, "0001 1100 ssN0 0001 0000 dddd 0000 imm4m1", "ldm rd,@rs,n", 0, + "------", 15, 16, "0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src", "ldm rd,address_src(rs),n", 0, + "------", 14, 16, "0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src", "ldm rd,address_src,n", 0, + + "CZSVDH", 12, 16, "0011 1001 ssN0 0000", "ldps @rs", 0, + "CZSVDH", 16, 16, "0111 1001 0000 0000 address_src", "ldps address_src", 0, + "CZSVDH", 17, 16, "0111 1001 ssN0 0000 address_src", "ldps address_src(rs)", 0, + + "------", 14, 16, "0011 0011 0000 ssss disp16", "ldr disp16,rs", 0, + "------", 14, 16, "0011 0001 0000 dddd disp16", "ldr rd,disp16", 0, + "------", 14, 8, "0011 0010 0000 ssss disp16", "ldrb disp16,rbs", 0, + "------", 14, 8, "0011 0000 0000 dddd disp16", "ldrb rbd,disp16", 0, + "------", 17, 32, "0011 0111 0000 ssss disp16", "ldrl disp16,rrs", 0, + "------", 17, 32, "0011 0101 0000 dddd disp16", "ldrl rrd,disp16", 0, + + "CZS---", 7, 16, "0111 1011 0000 1010", "mbit", 0, + "-ZS---", 12, 16, "0111 1011 dddd 1101", "mreq rd", 0, + "------", 5, 16, "0111 1011 0000 1001", "mres", 0, + "------", 5, 16, "0111 1011 0000 1000", "mset", 0, + + "CZSV--", 70, 16, "0001 1001 ssN0 dddd", "mult rrd,@rs", 0, + "CZSV--", 70, 16, "0101 1001 0000 dddd address_src", "mult rrd,address_src", 0, + "CZSV--", 70, 16, "0101 1001 ssN0 dddd address_src", "mult rrd,address_src(rs)", 0, + "CZSV--", 70, 16, "0001 1001 0000 dddd imm16", "mult rrd,imm16", 0, + "CZSV--", 70, 16, "1001 1001 ssss dddd", "mult rrd,rs", 0, + "CZSV--", 282, 32, "0001 1000 ssN0 dddd", "multl rqd,@rs", 0, + "CZSV--", 282, 32, "0101 1000 0000 dddd address_src", "multl rqd,address_src", 0, + "CZSV--", 282, 32, "0101 1000 ssN0 dddd address_src", "multl rqd,address_src(rs)", 0, + "CZSV--", 282, 32, "0001 1000 0000 dddd imm32", "multl rqd,imm32", 0, + "CZSV--", 282, 32, "1001 1000 ssss dddd", "multl rqd,rrs", 0, + "CZSV--", 12, 16, "0000 1101 ddN0 0010", "neg @rd", 0, + "CZSV--", 15, 16, "0100 1101 0000 0010 address_dst", "neg address_dst", 0, + "CZSV--", 16, 16, "0100 1101 ddN0 0010 address_dst", "neg address_dst(rd)", 0, + "CZSV--", 7, 16, "1000 1101 dddd 0010", "neg rd", 0, + "CZSV--", 12, 8, "0000 1100 ddN0 0010", "negb @rd", 0, + "CZSV--", 15, 8, "0100 1100 0000 0010 address_dst", "negb address_dst", 0, + "CZSV--", 16, 8, "0100 1100 ddN0 0010 address_dst", "negb address_dst(rd)", 0, + "CZSV--", 7, 8, "1000 1100 dddd 0010", "negb rbd", 0, + + "------", 7, 16, "1000 1101 0000 0111", "nop", 0, + + "CZS---", 7, 16, "0000 0101 ssN0 dddd", "or rd,@rs", 0, + "CZS---", 9, 16, "0100 0101 0000 dddd address_src", "or rd,address_src", 0, + "CZS---", 10, 16, "0100 0101 ssN0 dddd address_src", "or rd,address_src(rs)", 0, + "CZS---", 7, 16, "0000 0101 0000 dddd imm16", "or rd,imm16", 0, + "CZS---", 4, 16, "1000 0101 ssss dddd", "or rd,rs", 0, + + "CZSP--", 7, 8, "0000 0100 ssN0 dddd", "orb rbd,@rs", 0, + "CZSP--", 9, 8, "0100 0100 0000 dddd address_src", "orb rbd,address_src", 0, + "CZSP--", 10, 8, "0100 0100 ssN0 dddd address_src", "orb rbd,address_src(rs)", 0, + "CZSP--", 7, 8, "0000 0100 0000 dddd imm8 imm8", "orb rbd,imm8", 0, + "CZSP--", 4, 8, "1000 0100 ssss dddd", "orb rbd,rbs", 0, + + "---V--", 0, 16, "0011 1111 ddN0 ssss", "out @rd,rs", 0, + "---V--", 0, 16, "0011 1011 ssss 0110 imm16", "out imm16,rs", 0, + "---V--", 0, 8, "0011 1110 ddN0 ssss", "outb @rd,rbs", 0, + "---V--", 0, 8, "0011 1010 ssss 0110 imm16", "outb imm16,rbs", 0, + "---V--", 0, 16, "0011 1011 ssN0 1010 0000 aaaa ddN0 1000", "outd @rd,@rs,ra", 0, + "---V--", 0, 16, "0011 1010 ssN0 1010 0000 aaaa ddN0 1000", "outdb @rd,@rs,rba", 0, + "---V--", 0, 16, "0011 1011 ssN0 0010 0000 aaaa ddN0 1000", "outi @rd,@rs,ra", 0, + "---V--", 0, 16, "0011 1010 ssN0 0010 0000 aaaa ddN0 1000", "outib @rd,@rs,ra", 0, + "---V--", 0, 16, "0011 1010 ssN0 0010 0000 aaaa ddN0 0000", "outibr @rd,@rs,ra", 0, + + "------", 12, 16, "0001 0111 ssN0 ddN0", "pop @rd,@rs", 0, + "------", 16, 16, "0101 0111 ssN0 ddN0 address_dst", "pop address_dst(rd),@rs", 0, + "------", 16, 16, "0101 0111 ssN0 0000 address_dst", "pop address_dst,@rs", 0, + "------", 8, 16, "1001 0111 ssN0 dddd", "pop rd,@rs", 0, + + "------", 19, 32, "0001 0101 ssN0 ddN0", "popl @rd,@rs", 0, + "------", 23, 32, "0101 0101 ssN0 ddN0 address_dst", "popl address_dst(rd),@rs", 0, + "------", 23, 32, "0101 0101 ssN0 0000 address_dst", "popl address_dst,@rs", 0, + "------", 12, 32, "1001 0101 ssN0 dddd", "popl rrd,@rs", 0, + + "------", 13, 16, "0001 0011 ddN0 ssN0", "push @rd,@rs", 0, + "------", 14, 16, "0101 0011 ddN0 0000 address_src", "push @rd,address_src", 0, + "------", 14, 16, "0101 0011 ddN0 ssN0 address_src", "push @rd,address_src(rs)", 0, + "------", 12, 16, "0000 1101 ddN0 1001 imm16", "push @rd,imm16", 0, + "------", 9, 16, "1001 0011 ddN0 ssss", "push @rd,rs", 0, + + "------", 20, 32, "0001 0001 ddN0 ssN0", "pushl @rd,@rs", 0, + "------", 21, 32, "0101 0001 ddN0 ssN0 address_src", "pushl @rd,address_src(rs)", 0, + "------", 21, 32, "0101 0001 ddN0 0000 address_src", "pushl @rd,address_src", 0, + "------", 12, 32, "1001 0001 ddN0 ssss", "pushl @rd,rrs", 0, + + "------", 11, 16, "0010 0011 ddN0 imm4", "res @rd,imm4", 0, + "------", 14, 16, "0110 0011 ddN0 imm4 address_dst", "res address_dst(rd),imm4", 0, + "------", 13, 16, "0110 0011 0000 imm4 address_dst", "res address_dst,imm4", 0, + "------", 4, 16, "1010 0011 dddd imm4", "res rd,imm4", 0, + "------", 10, 16, "0010 0011 0000 ssss 0000 dddd 0000 0000", "res rd,rs", 0, + + "------", 11, 8, "0010 0010 ddN0 imm4", "resb @rd,imm4", 0, + "------", 14, 8, "0110 0010 ddN0 imm4 address_dst", "resb address_dst(rd),imm4", 0, + "------", 13, 8, "0110 0010 0000 imm4 address_dst", "resb address_dst,imm4", 0, + "------", 4, 8, "1010 0010 dddd imm4", "resb rbd,imm4", 0, + "------", 10, 8, "0010 0010 0000 ssss 0000 dddd 0000 0000", "resb rbd,rs", 0, + + "CZSV--", 7, 16, "1000 1101 flags 0011", "resflg flags", 0, + "------", 10, 16, "1001 1110 0000 cccc", "ret cc", 0, + + "CZSV--", 6, 16, "1011 0011 dddd 00I0", "rl rd,imm1or2", 0, + "CZSV--", 6, 8, "1011 0010 dddd 00I0", "rlb rbd,imm1or2", 0, + "CZSV--", 6, 16, "1011 0011 dddd 10I0", "rlc rd,imm1or2", 0, + + "-Z----", 9, 8, "1011 0010 dddd 10I0", "rlcb rbd,imm1or2", 0, + "-Z----", 9, 8, "1011 1110 aaaa bbbb", "rldb rbb,rba", 0, + + "CZSV--", 6, 16, "1011 0011 dddd 01I0", "rr rd,imm1or2", 0, + "CZSV--", 6, 8, "1011 0010 dddd 01I0", "rrb rbd,imm1or2", 0, + "CZSV--", 6, 16, "1011 0011 dddd 11I0", "rrc rd,imm1or2", 0, + + "-Z----", 9, 8, "1011 0010 dddd 11I0", "rrcb rbd,imm1or2", 0, + "-Z----", 9, 8, "1011 1100 aaaa bbbb", "rrdb rbb,rba", 0, + "CZSV--", 5, 16, "1011 0111 ssss dddd", "sbc rd,rs", 0, + "CZSVDH", 5, 8, "1011 0110 ssss dddd", "sbcb rbd,rbs", 0, + + "CZSVDH", 33, 8, "0111 1111 imm8", "sc imm8", 0, + + "CZSV--", 15, 16, "1011 0011 dddd 1011 0000 ssss 0000 0000", "sda rd,rs", 0, + "CZSV--", 15, 8, "1011 0010 dddd 1011 0000 ssss 0000 0000", "sdab rbd,rs", 0, + "CZSV--", 15, 32, "1011 0011 dddd 1111 0000 ssss 0000 0000", "sdal rrd,rs", 0, + + "CZS---", 15, 16, "1011 0011 dddd 0011 0000 ssss 0000 0000", "sdl rd,rs", 0, + "CZS---", 15, 8, "1011 0010 dddd 0011 0000 ssss 0000 0000", "sdlb rbd,rs", 0, + "CZS---", 15, 32, "1011 0011 dddd 0111 0000 ssss 0000 0000", "sdll rrd,rs", 0, + + "------", 11, 16, "0010 0101 ddN0 imm4", "set @rd,imm4", 0, + "------", 14, 16, "0110 0101 ddN0 imm4 address_dst", "set address_dst(rd),imm4", 0, + "------", 13, 16, "0110 0101 0000 imm4 address_dst", "set address_dst,imm4", 0, + "------", 4, 16, "1010 0101 dddd imm4", "set rd,imm4", 0, + "------", 10, 16, "0010 0101 0000 ssss 0000 dddd 0000 0000", "set rd,rs", 0, + "------", 11, 8, "0010 0100 ddN0 imm4", "setb @rd,imm4", 0, + "------", 14, 8, "0110 0100 ddN0 imm4 address_dst", "setb address_dst(rd),imm4", 0, + "------", 13, 8, "0110 0100 0000 imm4 address_dst", "setb address_dst,imm4", 0, + "------", 4, 8, "1010 0100 dddd imm4", "setb rbd,imm4", 0, + "------", 10, 8, "0010 0100 0000 ssss 0000 dddd 0000 0000", "setb rbd,rs", 0, + + "CZSV--", 7, 16, "1000 1101 flags 0001", "setflg flags", 0, + + "------", 0, 8, "0011 1010 dddd 0101 imm16", "sinb rbd,imm16", 0, + "------", 0, 8, "0011 1011 dddd 0101 imm16", "sin rd,imm16", 0, + "------", 0, 16, "0011 1011 ssN0 1000 0001 aaaa ddN0 1000", "sind @rd,@rs,ra", 0, + "------", 0, 8, "0011 1010 ssN0 1000 0001 aaaa ddN0 1000", "sindb @rd,@rs,rba", 0, + "------", 0, 8, "0011 1010 ssN0 0001 0000 aaaa ddN0 1000", "sinib @rd,@rs,ra", 0, + "------", 0, 16, "0011 1010 ssN0 0001 0000 aaaa ddN0 0000", "sinibr @rd,@rs,ra", 0, + + "CZSV--", 13, 16, "1011 0011 dddd 1001 0000 0000 imm8", "sla rd,imm8", 0, + "CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 0000 imm4", "slab rbd,imm4", 0, + "CZSV--", 13, 32, "1011 0011 dddd 1101 0000 0000 imm8", "slal rrd,imm8", 0, + + "CZS---", 13, 16, "1011 0011 dddd 0001 0000 0000 imm8", "sll rd,imm8", 0, + "CZS---", 13, 8, "1011 0010 dddd 0001 iiii iiii 0000 imm4", "sllb rbd,imm4", 0, + "CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0, + + "------", 0, 16, "0011 1011 ssss 0111 imm16", "sout imm16,rs", 0, + "------", 0, 8, "0011 1010 ssss 0111 imm16", "soutb imm16,rbs", 0, + "------", 0, 16, "0011 1011 ssN0 1011 0000 aaaa ddN0 1000", "soutd @rd,@rs,ra", 0, + "------", 0, 8, "0011 1010 ssN0 1011 0000 aaaa ddN0 1000", "soutdb @rd,@rs,rba", 0, + "------", 0, 8, "0011 1010 ssN0 0011 0000 aaaa ddN0 1000", "soutib @rd,@rs,ra", 0, + "------", 0, 16, "0011 1010 ssN0 0011 0000 aaaa ddN0 0000", "soutibr @rd,@rs,ra", 0, + + "CZSV--", 13, 16, "1011 0011 dddd 1001 1111 1111 nim8", "sra rd,imm8", 0, + "CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 1111 nim4", "srab rbd,imm4", 0, + "CZSV--", 13, 32, "1011 0011 dddd 1101 1111 1111 nim8", "sral rrd,imm8", 0, + + "CZSV--", 13, 16, "1011 0011 dddd 0001 1111 1111 nim8", "srl rd,imm8", 0, + "CZSV--", 13, 8, "1011 0010 dddd 0001 iiii iiii 1111 nim4", "srlb rbd,imm4", 0, + "CZSV--", 13, 32, "1011 0011 dddd 0101 1111 1111 nim8", "srll rrd,imm8", 0, + + "CZSV--", 7, 16, "0000 0011 ssN0 dddd", "sub rd,@rs", 0, + "CZSV--", 9, 16, "0100 0011 0000 dddd address_src", "sub rd,address_src", 0, + "CZSV--", 10, 16, "0100 0011 ssN0 dddd address_src", "sub rd,address_src(rs)", 0, + "CZSV--", 7, 16, "0000 0011 0000 dddd imm16", "sub rd,imm16", 0, + "CZSV--", 4, 16, "1000 0011 ssss dddd", "sub rd,rs", 0, + + "CZSVDH", 7, 8, "0000 0010 ssN0 dddd", "subb rbd,@rs", 0, + "CZSVDH", 9, 8, "0100 0010 0000 dddd address_src", "subb rbd,address_src", 0, + "CZSVDH", 10, 8, "0100 0010 ssN0 dddd address_src", "subb rbd,address_src(rs)", 0, + "CZSVDH", 7, 8, "0000 0010 0000 dddd imm8 imm8", "subb rbd,imm8", 0, + "CZSVDH", 4, 8, "1000 0010 ssss dddd", "subb rbd,rbs", 0, + + "CZSV--", 14, 32, "0001 0010 ssN0 dddd", "subl rrd,@rs", 0, + "CZSV--", 15, 32, "0101 0010 0000 dddd address_src", "subl rrd,address_src", 0, + "CZSV--", 16, 32, "0101 0010 ssN0 dddd address_src", "subl rrd,address_src(rs)", 0, + "CZSV--", 14, 32, "0001 0010 0000 dddd imm32", "subl rrd,imm32", 0, + "CZSV--", 8, 32, "1001 0010 ssss dddd", "subl rrd,rrs", 0, + + "------", 5, 16, "1010 1111 dddd cccc", "tcc cc,rd", 0, + "------", 5, 8, "1010 1110 dddd cccc", "tccb cc,rbd", 0, + + "-ZS---", 8, 16, "0000 1101 ddN0 0100", "test @rd", 0, + "------", 11, 16, "0100 1101 0000 0100 address_dst", "test address_dst", 0, + "------", 12, 16, "0100 1101 ddN0 0100 address_dst", "test address_dst(rd)", 0, + "------", 7, 16, "1000 1101 dddd 0100", "test rd", 0, + + "-ZSP--", 8, 8, "0000 1100 ddN0 0100", "testb @rd", 0, + "-ZSP--", 11, 8, "0100 1100 0000 0100 address_dst", "testb address_dst", 0, + "-ZSP--", 12, 8, "0100 1100 ddN0 0100 address_dst", "testb address_dst(rd)", 0, + "-ZSP--", 7, 8, "1000 1100 dddd 0100", "testb rbd", 0, + + "-ZS---", 13, 32, "0001 1100 ddN0 1000", "testl @rd", 0, + "-ZS---", 16, 32, "0101 1100 0000 1000 address_dst", "testl address_dst", 0, + "-ZS---", 17, 32, "0101 1100 ddN0 1000 address_dst", "testl address_dst(rd)", 0, + "-ZS---", 13, 32, "1001 1100 dddd 1000", "testl rrd", 0, + + "-ZSV--", 25, 8, "1011 1000 ddN0 1000 0000 aaaa ssN0 0000", "trdb @rd,@rs,rba", 0, + "-ZSV--", 25, 8, "1011 1000 ddN0 1100 0000 aaaa ssN0 0000", "trdrb @rd,@rs,rba", 0, + "-ZSV--", 25, 8, "1011 1000 ddN0 0000 0000 rrrr ssN0 0000", "trib @rd,@rs,rbr", 0, + "-ZSV--", 25, 8, "1011 1000 ddN0 0100 0000 rrrr ssN0 0000", "trirb @rd,@rs,rbr", 0, + "-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtdb @ra,@rb,rbr", 0, + "-ZSV--", 25, 8, "1011 1000 aaN0 1110 0000 rrrr bbN0 1110", "trtdrb @ra,@rb,rbr", 0, + "-ZSV--", 25, 8, "1011 1000 aaN0 0010 0000 rrrr bbN0 0000", "trtib @ra,@rb,rbr", 0, + "-ZSV--", 25, 8, "1011 1000 aaN0 0110 0000 rrrr bbN0 1110", "trtirb @ra,@rb,rbr", 0, + "-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtrb @ra,@rb,rbr", 0, + + "--S---", 11, 16, "0000 1101 ddN0 0110", "tset @rd", 0, + "--S---", 14, 16, "0100 1101 0000 0110 address_dst", "tset address_dst", 0, + "--S---", 15, 16, "0100 1101 ddN0 0110 address_dst", "tset address_dst(rd)", 0, + "--S---", 7, 16, "1000 1101 dddd 0110", "tset rd", 0, + + "--S---", 11, 8, "0000 1100 ddN0 0110", "tsetb @rd", 0, + "--S---", 14, 8, "0100 1100 0000 0110 address_dst", "tsetb address_dst", 0, + "--S---", 15, 8, "0100 1100 ddN0 0110 address_dst", "tsetb address_dst(rd)", 0, + "--S---", 7, 8, "1000 1100 dddd 0110", "tsetb rbd", 0, + + "-ZS---", 7, 16, "0000 1001 ssN0 dddd", "xor rd,@rs", 0, + "-ZS---", 9, 16, "0100 1001 0000 dddd address_src", "xor rd,address_src", 0, + "-ZS---", 10, 16, "0100 1001 ssN0 dddd address_src", "xor rd,address_src(rs)", 0, + "-ZS---", 7, 16, "0000 1001 0000 dddd imm16", "xor rd,imm16", 0, + "-ZS---", 4, 16, "1000 1001 ssss dddd", "xor rd,rs", 0, + + "-ZSP--", 7, 8, "0000 1000 ssN0 dddd", "xorb rbd,@rs", 0, + "-ZSP--", 9, 8, "0100 1000 0000 dddd address_src", "xorb rbd,address_src", 0, + "-ZSP--", 10, 8, "0100 1000 ssN0 dddd address_src", "xorb rbd,address_src(rs)", 0, + "-ZSP--", 7, 8, "0000 1000 0000 dddd imm8 imm8", "xorb rbd,imm8", 0, + "-ZSP--", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0, + + "------", 7, 32, "1000 1100 dddd 0001", "ldctlb rbd,ctrl", 0, + "CZSVDH", 7, 32, "1000 1100 ssss 1001", "ldctlb ctrl,rbs", 0, + + "*", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0, + "*", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +int +count () +{ + struct op *p = opt; + int r = 0; + + while (p->name) + { + r++; + p++; + } + return r; + +} + +static +int +func (a, b) + struct op *a; + struct op *b; +{ + return strcmp ((a)->name, (b)->name); +} + + +/* opcode + + literal 0000 nnnn insert nnn into stream + operand 0001 nnnn insert operand reg nnn into stream +*/ + +struct tok_struct +{ + + char *match; + char *token; + int length; +}; + +struct tok_struct args[] = +{ + + {"address_src(rs)", "CLASS_X+(ARG_RS)",}, + {"address_dst(rd)", "CLASS_X+(ARG_RD)",}, + + {"rs(imm16)", "CLASS_BA+(ARG_RS)",}, + {"rd(imm16)", "CLASS_BA+(ARG_RD)",}, + {"prd", "CLASS_PR+(ARG_RD)",}, + {"address_src", "CLASS_DA+(ARG_SRC)",}, + {"address_dst", "CLASS_DA+(ARG_DST)",}, + {"rd(rx)", "CLASS_BX+(ARG_RD)",}, + {"rs(rx)", "CLASS_BX+(ARG_RS)",}, + + {"disp16", "CLASS_DISP",}, + {"disp12", "CLASS_DISP",}, + {"disp7", "CLASS_DISP",}, + {"disp8", "CLASS_DISP",}, + {"flags", "CLASS_FLAGS",}, + + {"imm16", "CLASS_IMM+(ARG_IMM16)",}, + {"imm1or2", "CLASS_IMM+(ARG_IMM1OR2)",}, + {"imm32", "CLASS_IMM+(ARG_IMM32)",}, + {"imm4m1", "CLASS_IMM +(ARG_IMM4M1)",}, + {"imm4", "CLASS_IMM +(ARG_IMM4)",}, + {"n", "CLASS_IMM + (ARG_IMM4M1)",}, + {"ctrl", "CLASS_CTRL",}, + {"rba", "CLASS_REG_BYTE+(ARG_RA)",}, + {"rbb", "CLASS_REG_BYTE+(ARG_RB)",}, + {"rbd", "CLASS_REG_BYTE+(ARG_RD)",}, + {"rbs", "CLASS_REG_BYTE+(ARG_RS)",}, + {"rbr", "CLASS_REG_BYTE+(ARG_RR)",}, + + {"rrd", "CLASS_REG_LONG+(ARG_RD)",}, + {"rrs", "CLASS_REG_LONG+(ARG_RS)",}, + + {"rqd", "CLASS_REG_QUAD+(ARG_RD)",}, + + {"rd", "CLASS_REG_WORD+(ARG_RD)",}, + {"rs", "CLASS_REG_WORD+(ARG_RS)",}, + + {"@rd", "CLASS_IR+(ARG_RD)",}, + {"@ra", "CLASS_IR+(ARG_RA)",}, + {"@rb", "CLASS_IR+(ARG_RB)",}, + {"@rs", "CLASS_IR+(ARG_RS)",}, + + {"imm8", "CLASS_IMM+(ARG_IMM8)",}, + {"i2", "CLASS_IMM+(ARG_IMM2)",}, + {"cc", "CLASS_CC",}, + + {"rr", "CLASS_REG_WORD+(ARG_RR)",}, + {"ra", "CLASS_REG_WORD+(ARG_RA)",}, + {"rs", "CLASS_REG_WORD+(ARG_RS)",}, + + {"1", "CLASS_IMM+(ARG_IMM_1)",}, + {"2", "CLASS_IMM+(ARG_IMM_2)",}, + + 0, 0 +}; + +struct tok_struct toks[] = +{ + "0000", "CLASS_BIT+0", 1, + "0001", "CLASS_BIT+1", 1, + "0010", "CLASS_BIT+2", 1, + "0011", "CLASS_BIT+3", 1, + "0100", "CLASS_BIT+4", 1, + "0101", "CLASS_BIT+5", 1, + "0110", "CLASS_BIT+6", 1, + "0111", "CLASS_BIT+7", 1, + "1000", "CLASS_BIT+8", 1, + "1001", "CLASS_BIT+9", 1, + "1010", "CLASS_BIT+0xa", 1, + "1011", "CLASS_BIT+0xb", 1, + "1100", "CLASS_BIT+0xc", 1, + "1101", "CLASS_BIT+0xd", 1, + "1110", "CLASS_BIT+0xe", 1, + "1111", "CLASS_BIT+0xf", 1, + + "00I0", "CLASS_BIT_1OR2+0", 1, + "00I0", "CLASS_BIT_1OR2+1", 1, + "00I0", "CLASS_BIT_1OR2+2", 1, + "00I0", "CLASS_BIT_1OR2+3", 1, + "01I0", "CLASS_BIT_1OR2+4", 1, + "01I0", "CLASS_BIT_1OR2+5", 1, + "01I0", "CLASS_BIT_1OR2+6", 1, + "01I0", "CLASS_BIT_1OR2+7", 1, + "10I0", "CLASS_BIT_1OR2+8", 1, + "10I0", "CLASS_BIT_1OR2+9", 1, + "10I0", "CLASS_BIT_1OR2+0xa", 1, + "10I0", "CLASS_BIT_1OR2+0xb", 1, + "11I0", "CLASS_BIT_1OR2+0xc", 1, + "11I0", "CLASS_BIT_1OR2+0xd", 1, + "11I0", "CLASS_BIT_1OR2+0xe", 1, + "11I0", "CLASS_BIT_1OR2+0xf", 1, + + "ssss", "CLASS_REG+(ARG_RS)", 1, + "dddd", "CLASS_REG+(ARG_RD)", 1, + "aaaa", "CLASS_REG+(ARG_RA)", 1, + "bbbb", "CLASS_REG+(ARG_RB)", 1, + "rrrr", "CLASS_REG+(ARG_RR)", 1, + + "ssN0", "CLASS_REGN0+(ARG_RS)", 1, + "ddN0", "CLASS_REGN0+(ARG_RD)", 1, + "aaN0", "CLASS_REGN0+(ARG_RA)", 1, + "bbN0", "CLASS_REGN0+(ARG_RB)", 1, + "rrN0", "CLASS_REGN0+(ARG_RR)", 1, + + "cccc", "CLASS_CC", 1, + "nnnn", "CLASS_IMM+(ARG_IMMN)", 1, + "xxxx", "CLASS_REG+(ARG_RX)", 1, + "xxN0", "CLASS_REGN0+(ARG_RX)", 1, + "nminus1", "CLASS_IMM+(ARG_IMMNMINUS1)", 1, + + "disp16", "CLASS_DISP+(ARG_DISP16)", 4, + "disp12", "CLASS_DISP+(ARG_DISP12)", 3, + "flags", "CLASS_FLAGS", 1, + "address_dst", "CLASS_ADDRESS+(ARG_DST)", 4, + "address_src", "CLASS_ADDRESS+(ARG_SRC)", 4, + "imm4m1", "CLASS_IMM+(ARG_IMM4M1)", 1, + "imm4", "CLASS_IMM+(ARG_IMM4)", 1, + + "imm8", "CLASS_IMM+(ARG_IMM8)", 2, + "imm16", "CLASS_IMM+(ARG_IMM16)", 4, + "imm32", "CLASS_IMM+(ARG_IMM32)", 8, + "nim4", "CLASS_IMM+(ARG_NIM4)", 2, + "nim8", "CLASS_IMM+(ARG_NIM8)", 2, + "0ccc", "CLASS_0CCC", 1, + "1ccc", "CLASS_1CCC", 1, + "disp8", "CLASS_DISP8", 2, + "0disp7", "CLASS_0DISP7", 2, + "1disp7", "CLASS_1DISP7", 2, + "01ii", "CLASS_01II", 1, + "00ii", "CLASS_00II", 1, + + "iiii", "CLASS_IGNORE", 1, + 0, 0 +}; + +char * +translate (table, x, length) + struct tok_struct *table; + char *x; + int *length; +{ + + int found; + + found = 0; + while (table->match) + { + int l = strlen (table->match); + + if (strncmp (table->match, x, l) == 0) + { + /* Got a hit */ + printf ("%s", table->token); + *length += table->length; + return x + l; + } + + table++; + } + fprintf (stderr, "Can't find %s\n", x); + printf ("**** Can't find %s\n", x); + while (*x) + x++; + return x; +} + +void +chewbits (bits, length) + char *bits; + int *length; +{ + int n = 0; + + *length = 0; + printf ("{"); + while (*bits) + { + while (*bits == ' ') + { + bits++; + } + bits = translate (toks, bits, length); + n++; + printf (","); + + } + while (n < BYTE_INFO_LEN - 1) + { + printf ("0,"); + n++; + } + printf ("}"); +} + + +static +int +chewname (name) + char *name; +{ + char *n; + int nargs = 0; + + n = name; + printf ("\""); + while (*n && !iswhite (*n)) + { + printf ("%c", *n); + n++; + } + printf ("\","); /* Scan the operands and make entires for + them -remember indirect things */ + + n = name; + printf ("OPC_"); + while (*n && !iswhite (*n)) + { + printf ("%c", *n); + n++; + } + printf (",0,{"); + + while (*n) + { + int d; + + while (*n == ',' || iswhite (*n)) + n++; + nargs++; + n = translate (args, n, &d); + printf (","); + } + if (nargs == 0) + { + printf ("0"); + } + printf ("},"); + return nargs; +} + +static +void +sub (x, c) + char *x; + char c; +{ + while (*x) + { + if (x[0] == c && x[1] == c && + x[2] == c && x[3] == c) + { + x[2] = 'N'; + x[3] = '0'; + } + x++; + } +} + + +#if 0 +#define D(x) ((x) == '1' || (x) =='0') +#define M(y) (strncmp(y,x,4)==0) +printmangled (x) + char *x; +{ + return; + while (*x) + { + if (D (x[0]) && D (x[1]) && D (x[2]) && D (x[3])) + { + printf ("XXXX"); + } + else if (M ("ssss")) + { + printf ("ssss"); + } + else if (M ("dddd")) + { + printf ("dddd"); + } + else + printf ("____"); + + x += 4; + + if (x[0] == ' ') + { + printf ("_"); + x++; + } + } + +} + +#endif +/*#define WORK_TYPE*/ +void +print_type (n) + struct op *n; +{ +#ifdef WORK_TYPE + while (*s && !iswhite (*s)) + { + l = *s; + s++; + } + switch (l) + { + case 'l': + printf ("32,"); + break; + case 'b': + printf ("8,"); + break; + default: + printf ("16,"); + break; + } +#else + printf ("%2d,", n->type); +#endif +} + + +void +internal () +{ + int c = count (); + struct op *new = (struct op *) xmalloc (sizeof (struct op) * c); + struct op *p = opt; + memcpy (new, p, c * sizeof (struct op)); + + /* sort all names in table alphabetically */ + qsort (new, c, sizeof (struct op), func); + + p = new; + while (p->flags[0] != '*') + { + /* If there are any @rs, sub the ssss into a ssn0, + (rs), (ssn0) + */ + int loop = 1; + + printf ("\"%s\",%2d, ", p->flags, p->cycles); + while (loop) + { + char *s = p->name; + + loop = 0; + while (*s) + { + if (s[0] == '@') + { + char c; + + /* skip the r and sub the string */ + s++; + c = s[1]; + sub (p->bits, c); + } + if (s[0] == '(' && s[3] == ')') + { + sub (p->bits, s[2]); + } + if (s[0] == '(') + { + sub (p->bits, s[-1]); + } + + s++; + } + + } + print_type (p); + printf ("\"%s\",\"%s\",0,\n", p->bits, p->name); + p++; + } +} + +static +void +gas () +{ + int c = count (); + struct op *p = opt; + int idx = 0; + char *oldname = ""; + struct op *new = (struct op *) xmalloc (sizeof (struct op) * c); + + memcpy (new, p, c * sizeof (struct op)); + + /* sort all names in table alphabetically */ + qsort (new, c, sizeof (struct op), func); + + printf (" /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */\n"); + + printf ("#define ARG_MASK 0x0f\n"); + + printf ("#define ARG_SRC 0x01\n"); + printf ("#define ARG_DST 0x02\n"); + + printf ("#define ARG_RS 0x01\n"); + printf ("#define ARG_RD 0x02\n"); + printf ("#define ARG_RA 0x03\n"); + printf ("#define ARG_RB 0x04\n"); + printf ("#define ARG_RR 0x05\n"); + printf ("#define ARG_RX 0x06\n"); + printf ("#define ARG_IMM4 0x01\n"); + printf ("#define ARG_IMM8 0x02\n"); + printf ("#define ARG_IMM16 0x03\n"); + printf ("#define ARG_IMM32 0x04\n"); + printf ("#define ARG_IMMN 0x05\n"); + printf ("#define ARG_IMMNMINUS1 0x05\n"); + printf ("#define ARG_IMM_1 0x06\n"); + printf ("#define ARG_IMM_2 0x07\n"); + printf ("#define ARG_DISP16 0x08\n"); + printf ("#define ARG_NIM8 0x09\n"); + printf ("#define ARG_IMM2 0x0a\n"); + printf ("#define ARG_IMM1OR2 0x0b\n"); + + printf ("#define ARG_DISP12 0x0b\n"); + printf ("#define ARG_NIM4 0x0c\n"); + printf ("#define ARG_DISP8 0x0c\n"); + printf ("#define ARG_IMM4M1 0x0d\n"); + printf ("#define CLASS_MASK 0x1fff0\n"); + printf ("#define CLASS_X 0x10\n"); + printf ("#define CLASS_BA 0x20\n"); + printf ("#define CLASS_DA 0x30\n"); + printf ("#define CLASS_BX 0x40\n"); + printf ("#define CLASS_DISP 0x50\n"); + printf ("#define CLASS_IMM 0x60\n"); + printf ("#define CLASS_CC 0x70\n"); + printf ("#define CLASS_CTRL 0x80\n"); + printf ("#define CLASS_IGNORE 0x90\n"); + printf ("#define CLASS_ADDRESS 0xd0\n"); + printf ("#define CLASS_0CCC 0xe0\n"); + printf ("#define CLASS_1CCC 0xf0\n"); + printf ("#define CLASS_0DISP7 0x100\n"); + printf ("#define CLASS_1DISP7 0x200\n"); + printf ("#define CLASS_01II 0x300\n"); + printf ("#define CLASS_00II 0x400\n"); + printf ("#define CLASS_BIT 0x500\n"); + printf ("#define CLASS_FLAGS 0x600\n"); + printf ("#define CLASS_IR 0x700\n"); + printf ("#define CLASS_DISP8 0x800\n"); + + printf ("#define CLASS_BIT_1OR2 0x900\n"); + printf ("#define CLASS_REG 0x7000\n"); + printf ("#define CLASS_REG_BYTE 0x2000\n"); + printf ("#define CLASS_REG_WORD 0x3000\n"); + printf ("#define CLASS_REG_QUAD 0x4000\n"); + printf ("#define CLASS_REG_LONG 0x5000\n"); + printf ("#define CLASS_REGN0 0x8000\n"); + printf ("#define CLASS_PR 0x10000\n"); + + printf ("#define OPC_adc 0\n"); + printf ("#define OPC_adcb 1\n"); + printf ("#define OPC_add 2\n"); + printf ("#define OPC_addb 3\n"); + printf ("#define OPC_addl 4\n"); + printf ("#define OPC_and 5\n"); + printf ("#define OPC_andb 6\n"); + printf ("#define OPC_bit 7\n"); + printf ("#define OPC_bitb 8\n"); + printf ("#define OPC_call 9\n"); + printf ("#define OPC_calr 10\n"); + printf ("#define OPC_clr 11\n"); + printf ("#define OPC_clrb 12\n"); + printf ("#define OPC_com 13\n"); + printf ("#define OPC_comb 14\n"); + printf ("#define OPC_comflg 15\n"); + printf ("#define OPC_cp 16\n"); + printf ("#define OPC_cpb 17\n"); + printf ("#define OPC_cpd 18\n"); + printf ("#define OPC_cpdb 19\n"); + printf ("#define OPC_cpdr 20\n"); + printf ("#define OPC_cpdrb 21\n"); + printf ("#define OPC_cpi 22\n"); + printf ("#define OPC_cpib 23\n"); + printf ("#define OPC_cpir 24\n"); + printf ("#define OPC_cpirb 25\n"); + printf ("#define OPC_cpl 26\n"); + printf ("#define OPC_cpsd 27\n"); + printf ("#define OPC_cpsdb 28\n"); + printf ("#define OPC_cpsdr 29\n"); + printf ("#define OPC_cpsdrb 30\n"); + printf ("#define OPC_cpsi 31\n"); + printf ("#define OPC_cpsib 32\n"); + printf ("#define OPC_cpsir 33\n"); + printf ("#define OPC_cpsirb 34\n"); + printf ("#define OPC_dab 35\n"); + printf ("#define OPC_dbjnz 36\n"); + printf ("#define OPC_dec 37\n"); + printf ("#define OPC_decb 38\n"); + printf ("#define OPC_di 39\n"); + printf ("#define OPC_div 40\n"); + printf ("#define OPC_divl 41\n"); + printf ("#define OPC_djnz 42\n"); + printf ("#define OPC_ei 43\n"); + printf ("#define OPC_ex 44\n"); + printf ("#define OPC_exb 45\n"); + printf ("#define OPC_exts 46\n"); + printf ("#define OPC_extsb 47\n"); + printf ("#define OPC_extsl 48\n"); + printf ("#define OPC_halt 49\n"); + printf ("#define OPC_in 50\n"); + printf ("#define OPC_inb 51\n"); + printf ("#define OPC_inc 52\n"); + printf ("#define OPC_incb 53\n"); + printf ("#define OPC_ind 54\n"); + printf ("#define OPC_indb 55\n"); + printf ("#define OPC_inib 56\n"); + printf ("#define OPC_inibr 57\n"); + printf ("#define OPC_iret 58\n"); + printf ("#define OPC_jp 59\n"); + printf ("#define OPC_jr 60\n"); + printf ("#define OPC_ld 61\n"); + printf ("#define OPC_lda 62\n"); + printf ("#define OPC_ldar 63\n"); + printf ("#define OPC_ldb 64\n"); + printf ("#define OPC_ldctl 65\n"); + printf ("#define OPC_ldir 66\n"); + printf ("#define OPC_ldirb 67\n"); + printf ("#define OPC_ldk 68\n"); + printf ("#define OPC_ldl 69\n"); + printf ("#define OPC_ldm 70\n"); + printf ("#define OPC_ldps 71\n"); + printf ("#define OPC_ldr 72\n"); + printf ("#define OPC_ldrb 73\n"); + printf ("#define OPC_ldrl 74\n"); + printf ("#define OPC_mbit 75\n"); + printf ("#define OPC_mreq 76\n"); + printf ("#define OPC_mres 77\n"); + printf ("#define OPC_mset 78\n"); + printf ("#define OPC_mult 79\n"); + printf ("#define OPC_multl 80\n"); + printf ("#define OPC_neg 81\n"); + printf ("#define OPC_negb 82\n"); + printf ("#define OPC_nop 83\n"); + printf ("#define OPC_or 84\n"); + printf ("#define OPC_orb 85\n"); + printf ("#define OPC_out 86\n"); + printf ("#define OPC_outb 87\n"); + printf ("#define OPC_outd 88\n"); + printf ("#define OPC_outdb 89\n"); + printf ("#define OPC_outib 90\n"); + printf ("#define OPC_outibr 91\n"); + printf ("#define OPC_pop 92\n"); + printf ("#define OPC_popl 93\n"); + printf ("#define OPC_push 94\n"); + printf ("#define OPC_pushl 95\n"); + printf ("#define OPC_res 96\n"); + printf ("#define OPC_resb 97\n"); + printf ("#define OPC_resflg 98\n"); + printf ("#define OPC_ret 99\n"); + printf ("#define OPC_rl 100\n"); + printf ("#define OPC_rlb 101\n"); + printf ("#define OPC_rlc 102\n"); + printf ("#define OPC_rlcb 103\n"); + printf ("#define OPC_rldb 104\n"); + printf ("#define OPC_rr 105\n"); + printf ("#define OPC_rrb 106\n"); + printf ("#define OPC_rrc 107\n"); + printf ("#define OPC_rrcb 108\n"); + printf ("#define OPC_rrdb 109\n"); + printf ("#define OPC_sbc 110\n"); + printf ("#define OPC_sbcb 111\n"); + printf ("#define OPC_sda 112\n"); + printf ("#define OPC_sdab 113\n"); + printf ("#define OPC_sdal 114\n"); + printf ("#define OPC_sdl 115\n"); + printf ("#define OPC_sdlb 116\n"); + printf ("#define OPC_sdll 117\n"); + printf ("#define OPC_set 118\n"); + printf ("#define OPC_setb 119\n"); + printf ("#define OPC_setflg 120\n"); + printf ("#define OPC_sinb 121\n"); + printf ("#define OPC_sind 122\n"); + printf ("#define OPC_sindb 123\n"); + printf ("#define OPC_sinib 124\n"); + printf ("#define OPC_sinibr 125\n"); + printf ("#define OPC_sla 126\n"); + printf ("#define OPC_slab 127\n"); + printf ("#define OPC_slal 128\n"); + printf ("#define OPC_sll 129\n"); + printf ("#define OPC_sllb 130\n"); + printf ("#define OPC_slll 131\n"); + printf ("#define OPC_sout 132\n"); + printf ("#define OPC_soutb 133\n"); + printf ("#define OPC_soutd 134\n"); + printf ("#define OPC_soutdb 135\n"); + printf ("#define OPC_soutib 136\n"); + printf ("#define OPC_soutibr 137\n"); + printf ("#define OPC_sra 138\n"); + printf ("#define OPC_srab 139\n"); + printf ("#define OPC_sral 140\n"); + printf ("#define OPC_srl 141\n"); + printf ("#define OPC_srlb 142\n"); + printf ("#define OPC_srll 143\n"); + printf ("#define OPC_sub 144\n"); + printf ("#define OPC_subb 145\n"); + printf ("#define OPC_subl 146\n"); + printf ("#define OPC_tcc 147\n"); + printf ("#define OPC_tccb 148\n"); + printf ("#define OPC_test 149\n"); + printf ("#define OPC_testb 150\n"); + printf ("#define OPC_testl 151\n"); + printf ("#define OPC_trdb 152\n"); + printf ("#define OPC_trdrb 153\n"); + printf ("#define OPC_trib 154\n"); + printf ("#define OPC_trirb 155\n"); + printf ("#define OPC_trtdrb 156\n"); + printf ("#define OPC_trtib 157\n"); + printf ("#define OPC_trtirb 158\n"); + printf ("#define OPC_trtrb 159\n"); + printf ("#define OPC_tset 160\n"); + printf ("#define OPC_tsetb 161\n"); + printf ("#define OPC_xor 162\n"); + printf ("#define OPC_xorb 163\n"); + + printf ("#define OPC_ldd 164 \n"); + printf ("#define OPC_lddb 165 \n"); + printf ("#define OPC_lddr 166 \n"); + printf ("#define OPC_lddrb 167 \n"); + printf ("#define OPC_ldi 168 \n"); + printf ("#define OPC_ldib 169 \n"); + printf ("#define OPC_sc 170\n"); + printf ("#define OPC_bpt 171\n"); + printf ("#define OPC_ext0e 172\n"); + printf ("#define OPC_ext0f 172\n"); + printf ("#define OPC_ext8e 172\n"); + printf ("#define OPC_ext8f 172\n"); + printf ("#define OPC_rsvd36 172\n"); + printf ("#define OPC_rsvd38 172\n"); + printf ("#define OPC_rsvd78 172\n"); + printf ("#define OPC_rsvd7e 172\n"); + printf ("#define OPC_rsvd9d 172\n"); + printf ("#define OPC_rsvd9f 172\n"); + printf ("#define OPC_rsvdb9 172\n"); + printf ("#define OPC_rsvdbf 172\n"); + printf ("#define OPC_outi 173\n"); + printf ("#define OPC_ldctlb 174\n"); + printf ("#define OPC_sin 175\n"); + printf ("#define OPC_trtdb 176\n"); +#if 0 + for (i = 0; toks[i].token; i++) + printf ("#define %s\t0x%x\n", toks[i].token, i * 16); +#endif + printf ("typedef struct {\n"); + + printf ("#ifdef NICENAMES\n"); + printf ("char *nicename;\n"); + printf ("int type;\n"); + printf ("int cycles;\n"); + printf ("int flags;\n"); + printf ("#endif\n"); + printf ("char *name;\n"); + printf ("unsigned char opcode;\n"); + printf ("void (*func) PARAMS ((void));\n"); + printf ("unsigned int arg_info[4];\n"); + printf ("unsigned int byte_info[%d];\n", BYTE_INFO_LEN); + printf ("int noperands;\n"); + printf ("int length;\n"); + printf ("int idx;\n"); + printf ("} opcode_entry_type;\n"); + printf ("#ifdef DEFINE_TABLE\n"); + printf ("opcode_entry_type z8k_table[] = {\n"); + + while (new->flags && new->flags[0]) + { + int nargs; + int length; + + printf ("\n\n/* %s *** %s */\n", new->bits, new->name); + printf ("{\n"); + + printf ("#ifdef NICENAMES\n"); + printf ("\"%s\",%d,%d,\n", new->name, new->type, new->cycles); + { + int answer = 0; + char *p = new->flags; + + while (*p) + { + answer <<= 1; + + if (*p != '-') + answer |= 1; + p++; + } + printf ("0x%02x,\n", answer); + } + + printf ("#endif\n"); + + nargs = chewname (new->name); + + printf ("\n\t"); + chewbits (new->bits, &length); + length /= 2; + if (length & 1) + abort(); + + printf (",%d,%d,%d", nargs, length, idx); + idx++; + oldname = new->name; + printf ("},\n"); + new++; + } + printf ("\n/* end marker */\n"); + printf ("{\n#ifdef NICENAMES\nNULL,0,0,\n0,\n#endif\n"); + printf ("NULL,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0}\n};\n"); + printf ("#endif\n"); +} + + +int +main (ac, av) + int ac; + char **av; +{ + struct op *p = opt; + + if (ac == 2 && strcmp (av[1], "-t") == 0) + { + internal (); + } + else if (ac == 2 && strcmp (av[1], "-h") == 0) + { + while (p->name) + { + printf ("%-25s\t%s\n", p->name, p->bits); + p++; + } + } + + else if (ac == 2 && strcmp (av[1], "-a") == 0) + { + gas (); + } + else if (ac == 2 && strcmp (av[1], "-d") == 0) + { + /*dis();*/ + } + else + { + printf ("Usage: %s -t\n", av[0]); + printf ("-t : generate new z8.c internal table\n"); + printf ("-a : generate new table for gas\n"); + printf ("-d : generate new table for disassemble\n"); + printf ("-h : generate new table for humans\n"); + } + return 0; +} -- cgit v1.1