From dac0b8a4af48e1c5739a19cd5501c7a81bc44ab0 Mon Sep 17 00:00:00 2001 From: Jiawei Date: Wed, 28 Feb 2024 16:27:17 +0800 Subject: RISC-V: Support Zabha extension. The Zabha extension[1] supports for byte and halfword atomic memory operations. This patch add all instructions include in Zabha. Further work is waiting Zacas[2] merge. [1] https://github.com/riscv/riscv-zabha/tags [2] https://sourceware.org/pipermail/binutils/2023-May/127700.html Version log: Add new imply relation that Zabha extension implies A extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): New imply. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New test. * testsuite/gas/riscv/zabha.d: New test. * testsuite/gas/riscv/zabha.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. (MASK_AMOADD_B): Ditto. (MATCH_AMOXOR_B): Ditto. (MASK_AMOXOR_B): Ditto. (MATCH_AMOOR_B): Ditto. (MASK_AMOOR_B): Ditto. (MATCH_AMOAND_B): Ditto. (MASK_AMOAND_B): Ditto. (MATCH_AMOMIN_B): Ditto. (MASK_AMOMIN_B): Ditto. (MATCH_AMOMAX_B): Ditto. (MASK_AMOMAX_B): Ditto. (MATCH_AMOMINU_B): Ditto. (MASK_AMOMINU_B): Ditto. (MATCH_AMOMAXU_B): Ditto. (MASK_AMOMAXU_B): Ditto. (MATCH_AMOSWAP_B): Ditto. (MASK_AMOSWAP_B): Ditto. (MATCH_AMOADD_H): Ditto. (MASK_AMOADD_H): Ditto. (MATCH_AMOXOR_H): Ditto. (MASK_AMOXOR_H): Ditto. (MATCH_AMOOR_H): Ditto. (MASK_AMOOR_H): Ditto. (MATCH_AMOAND_H): Ditto. (MASK_AMOAND_H): Ditto. (MATCH_AMOMIN_H): Ditto. (MASK_AMOMIN_H): Ditto. (MATCH_AMOMAX_H): Ditto. (MASK_AMOMAX_H): Ditto. (MATCH_AMOMINU_H): Ditto. (MASK_AMOMINU_H): Ditto. (MATCH_AMOMAXU_H): Ditto. (MASK_AMOMAXU_H): Ditto. (MATCH_AMOSWAP_H): Ditto. (MASK_AMOSWAP_H): Ditto. (DECLARE_INSN): New declare. * opcode/riscv.h (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-opc.c: New instructions. --- opcodes/riscv-opc.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'opcodes/riscv-opc.c') diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index dcc592e..daa888d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -660,6 +660,80 @@ const struct riscv_opcode riscv_opcodes[] = {"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +/* Byte and Halfword Atomic Memory Operations instruction subset. */ +{"amoadd.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQ, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQ, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQ, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQ, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQ, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQ, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQ, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQ, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQ, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_RL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_RL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_RL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_RL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_RL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_RL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_RL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_RL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_RL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQRL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQRL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQRL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQRL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQRL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQRL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQRL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQRL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQRL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQ, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQ, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQ, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQ, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQ, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQ, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQ, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQ, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQ, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_RL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_RL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_RL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_RL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_RL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_RL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_RL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_RL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_RL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQRL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQRL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQRL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQRL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQRL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQRL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQRL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + /* Multiply/Divide instruction subset. */ {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, -- cgit v1.1