From b416fe873ef44b2a613c9266c6462a481926d986 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Tue, 7 Mar 2017 18:15:02 +0800 Subject: RISC-V: Fix assembler for c.li, c.andi and c.addiw - They can accept 0 in imm field 2017-03-14 Kito Cheng * riscv-opc.c (riscv_opcodes> : Use the 'o' immediate encoding. : Likewise. Likewise. --- opcodes/riscv-opc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'opcodes/riscv-opc.c') diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 4a2ab7b..c629d2f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -622,7 +622,7 @@ const struct riscv_opcode riscv_opcodes[] = {"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, {"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, {"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, -{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, +{"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, {"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, {"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, {"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, @@ -634,8 +634,8 @@ const struct riscv_opcode riscv_opcodes[] = {"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, {"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, {"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, -{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, -{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, +{"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +{"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, {"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, {"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, {"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, -- cgit v1.1