From e4c4ac46e8e7ef92311181f85b193af369897151 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Thu, 13 Jun 2019 06:16:19 +0900 Subject: opcodes/or1k: Regenerate opcodes This picks up changes for: - new orfpx64a32 spec additions - new unordered instructions - symbol and documentation updates opcodes/ChangeLog: * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated. --- opcodes/or1k-opinst.c | 100 +++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 86 insertions(+), 14 deletions(-) (limited to 'opcodes/or1k-opinst.c') diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c index 6b18dab..84a0dfe 100644 --- a/opcodes/or1k-opinst.c +++ b/opcodes/or1k-opinst.c @@ -461,6 +461,13 @@ static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, @@ -475,6 +482,13 @@ static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 }, + { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, @@ -489,20 +503,34 @@ static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; -static const CGEN_OPINST sfmt_lf_eq_s_ops[] ATTRIBUTE_UNUSED = { +static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, + { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; -static const CGEN_OPINST sfmt_lf_eq_d_ops[] ATTRIBUTE_UNUSED = { +static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, + { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = { { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, @@ -519,6 +547,14 @@ static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = { { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } }; +static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, + { INPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + #undef OP_ENT #undef INPUT #undef OUTPUT @@ -629,32 +665,68 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = { & sfmt_l_msync_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_add_s_ops[0], & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], & sfmt_lf_itof_s_ops[0], & sfmt_lf_itof_d_ops[0], + & sfmt_lf_itof_d32_ops[0], & sfmt_lf_ftoi_s_ops[0], & sfmt_lf_ftoi_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], - & sfmt_lf_eq_s_ops[0], - & sfmt_lf_eq_d_ops[0], + & sfmt_lf_ftoi_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], + & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], & sfmt_lf_madd_s_ops[0], & sfmt_lf_madd_d_ops[0], + & sfmt_lf_madd_d32_ops[0], + & sfmt_l_msync_ops[0], & sfmt_l_msync_ops[0], & sfmt_l_msync_ops[0], }; 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