From 38bf472a15210c222bb3885820e763c47760a704 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 28 Jun 2017 02:07:36 +0100 Subject: MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) : New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) : New case. (mips_set_isa_flags) : Likewise. (bfd_mips_isa_ext) : Likewise. (print_mips_isa_ext) : Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) : Update comment. (validate_insn_args) : Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) : New case. (print_mips_isa_ext) : Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list. --- opcodes/mips16-opc.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'opcodes/mips16-opc.c') diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 83663ad..0ee71be 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -82,6 +82,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p) case 'i': JALX (26, 0, 2); case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST); case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST); + case 'n': INT_BIAS (2, 0, 3, 1, 0, FALSE); /* (1 .. 4) */ + case 'o': INT_ADJ (5, 16, 31, 4, FALSE); /* (0 .. 31) << 4 */ case 'r': MAPPED_REG (3, 16, GP, reg_m16_map); case 's': HINT (3, 24); case 'u': HINT (16, 0); @@ -201,6 +203,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p) #define I32 INSN_ISA32 #define I64 INSN_ISA64 #define T3 INSN_3900 +#define IAMR2 INSN_INTERAPTIV_MR2 #define E2 ASE_MIPS16E2 #define E2MT ASE_MIPS16E2_MT @@ -465,6 +468,9 @@ const struct mips_opcode mips16_opcodes[] = {"evpe", "", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, {"evpe", ".", 0xf0276700, 0xffffffff, WR_C0, 0, 0, E2MT, 0 }, {"evpe", "y", 0xf0236700, 0xffffff1f, WR_1|WR_C0, 0, 0, E2MT, 0 }, + /* interAptiv MR2 instruction extensions. */ +{"copyw", "x,y,o,n", 0xf020e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 }, +{"ucopyw", "x,y,o,n", 0xf000e000, 0xffe0f81c, RD_1|RD_2|NODS, 0, IAMR2, 0, 0 }, /* Place asmacro at the bottom so that it catches any implementation specific macros that didn't match anything. */ {"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 }, -- cgit v1.1