From 646cc3e0109e4a45a232af8354feafc36c3249ee Mon Sep 17 00:00:00 2001
From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
Date: Tue, 20 Oct 2020 23:56:58 +0530
Subject: Add AMD znver3 processor support

gas/

	* config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
	(i386_align_code): Add PROCESSOR_ZNVER cases.
	* doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
	* gas/i386/i386.exp: Add new znver3 test cases.
	* gas/i386/arch-14-znver3.d: New.
	* gas/i386/arch-14.d: New.
	* gas/i386/arch-14.s: New.
	* gas/i386/invlpgb.d: New.
	* gas/i386/invlpgb64.d: New.
	* gas/i386/invlpgb.s: New.
	* gas/i386/snp.d: New.
	* gas/i386/snp64.d: New.
	* gas/i386/snp.s: New.
	* gas/i386/tlbsync.d: New.
	* gas/i386/tlbsync.s: New.
	* gas/i386/x86-64-arch-4-znver3.d: New.
	* gas/i386/x86-64-arch-4.d: New.
	* gas/i386/x86-64-arch-4.s: New.

opcodes/

	* i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
	* i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
	CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
	Add CPU_ZNVER3_FLAGS.
	(cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
	* i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
	* i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
	rmpupdate, rmpadjust.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.
---
 opcodes/i386-opc.tbl | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'opcodes/i386-opc.tbl')

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 56c2838..ede9e98 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3960,6 +3960,19 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=
 
 // AVX512 + VPCLMULQDQ instructions end
 
+// INVLPGB instructions
+
+invlpgb, 0, 0xf01fe, None, 3, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+invlpgb, 2, 0xf01fe, None, 3, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegD|Dword }
+
+// INVLPGB instructions end
+
+// TLBSYNC instructions
+
+tlbsync, 0, 0xf01ff, None, 3, CpuTLBSYNC, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// TLBSYNC instructions end
+
 // CLZERO instructions
 
 clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@@ -4092,6 +4105,19 @@ mcommit, 0, 0x0f01fa, None, 3, CpuMCOMMIT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|N
 
 // MCOMMIT instruction end
 
+// SNP instructions
+
+psmash, 0, 0xf01ff, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+psmash, 1, 0xf01ff, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
+pvalidate, 0, 0xf01ff, None, 3, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+pvalidate, 1, 0xf01ff, None, 3, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
+rmpupdate, 0, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+rmpupdate, 1, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
+rmpadjust, 0, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+rmpadjust, 1, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
+
+// SNP instructions end
+
 // RDPRU instruction
 
 rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-- 
cgit v1.1