From 0cc7872125efa71879e34403cc644cd19434eae3 Mon Sep 17 00:00:00 2001 From: "Cui,Lili" Date: Mon, 14 Jun 2021 11:05:05 +0800 Subject: [PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist H.J. Lu Wei Xiao Lili Cui * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist H.J. Lu Wei Xiao Lili Cui * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto. --- opcodes/i386-dis-evex-prefix.h | 221 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) (limited to 'opcodes/i386-dis-evex-prefix.h') diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index 5c24618..9c8156a 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -375,3 +375,224 @@ { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 }, { "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 }, }, + /* PREFIX_EVEX_0F3A08_W_0 */ + { + { "vrndscaleph", { XM, EXxh, EXxEVexS, Ib }, 0 }, + { Bad_Opcode }, + { "vrndscaleps", { XM, EXx, EXxEVexS, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A0A_W_0 */ + { + { "vrndscalesh", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 }, + { Bad_Opcode }, + { "vrndscaless", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A26 */ + { + { "vgetmantp%XH", { XM, EXxh, EXxEVexS, Ib }, 0 }, + { Bad_Opcode }, + { "vgetmantp%XW", { XM, EXx, EXxEVexS, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A27 */ + { + { "vgetmants%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 }, + { Bad_Opcode }, + { "vgetmants%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A56 */ + { + { "vreducep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 }, + { Bad_Opcode }, + { "vreducep%XW", { XM, EXx, EXxEVexS, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A57 */ + { + { "vreduces%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 }, + { Bad_Opcode }, + { "vreduces%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A66 */ + { + { "vfpclassp%XH%XZ", { MaskG, EXxh, Ib }, 0 }, + { Bad_Opcode }, + { "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3A67 */ + { + { "vfpclasss%XH", { MaskG, EXw, Ib }, 0 }, + { Bad_Opcode }, + { "vfpclasss%XW", { MaskG, EXdq, Ib }, 0 }, + }, + /* PREFIX_EVEX_0F3AC2 */ + { + { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 }, + { "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 }, + }, + /* PREFIX_EVEX_MAP5_10 */ + { + { Bad_Opcode }, + { "vmovs%XH", { XMScalar, VexScalarR, EXw }, 0 }, + }, + /* PREFIX_EVEX_MAP5_11 */ + { + { Bad_Opcode }, + { "vmovs%XH", { EXwS, VexScalarR, XMScalar }, 0 }, + }, + /* PREFIX_EVEX_MAP5_1D */ + { + { "vcvtss2s%XH", { XMM, VexScalar, EXd, EXxEVexR }, 0 }, + { Bad_Opcode }, + { "vcvtps2p%XHx%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_2A */ + { + { Bad_Opcode }, + { "vcvtsi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 }, + }, + /* PREFIX_EVEX_MAP5_2C */ + { + { Bad_Opcode }, + { "vcvttsh2si", { Gdq, EXw, EXxEVexS }, 0 }, + }, + /* PREFIX_EVEX_MAP5_2D */ + { + { Bad_Opcode }, + { "vcvtsh2si", { Gdq, EXw, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_2E */ + { + { "vucomis%XH", { XMScalar, EXw, EXxEVexS }, 0 }, + }, + /* PREFIX_EVEX_MAP5_2F */ + { + { "vcomis%XH", { XMScalar, EXw, EXxEVexS }, 0 }, + }, + /* PREFIX_EVEX_MAP5_51 */ + { + { "vsqrtp%XH", { XM, EXxh, EXxEVexR }, 0 }, + { "vsqrts%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_58 */ + { + { "vaddp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 }, + { "vadds%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_59 */ + { + { "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 }, + { "vmuls%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5A_W_0 */ + { + { "vcvtph2pd", { XM, EXxmmqdh, EXxEVexS }, 0 }, + { "vcvtsh2sd", { XMM, VexScalar, EXw, EXxEVexS }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5A_W_1 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vcvtpd2ph%XZ", { XMM, EXx, EXxEVexR }, 0 }, + { "vcvtsd2sh", { XMM, VexScalar, EXq, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5B_W_0 */ + { + { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, + { "vcvttph2dq", { XM, EXxmmqh, EXxEVexS }, 0 }, + { "vcvtph2dq", { XM, EXxmmqh, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5B_W_1 */ + { + { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5C */ + { + { "vsubp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 }, + { "vsubs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5D */ + { + { "vminp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 }, + { "vmins%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5E */ + { + { "vdivp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 }, + { "vdivs%XH", { XMM, VexScalar, EXw, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP5_5F */ + { + { "vmaxp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 }, + { "vmaxs%XH", { XMM, VexScalar, EXw, EXxEVexS }, 0 }, + }, + /* PREFIX_EVEX_MAP5_78 */ + { + { VEX_W_TABLE (EVEX_W_MAP5_78_P_0) }, + { "vcvttsh2usi", { Gdq, EXw, EXxEVexS }, 0 }, + { VEX_W_TABLE (EVEX_W_MAP5_78_P_2) }, + }, + /* PREFIX_EVEX_MAP5_79 */ + { + { VEX_W_TABLE (EVEX_W_MAP5_79_P_0) }, + { "vcvtsh2usi", { Gdq, EXw, EXxEVexR }, 0 }, + { VEX_W_TABLE (EVEX_W_MAP5_79_P_2) }, + }, + /* PREFIX_EVEX_MAP5_7A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_MAP5_7A_P_2) }, + { VEX_W_TABLE (EVEX_W_MAP5_7A_P_3) }, + }, + /* PREFIX_EVEX_MAP5_7B */ + { + { Bad_Opcode }, + { "vcvtusi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 }, + { VEX_W_TABLE (EVEX_W_MAP5_7B_P_2) }, + }, + /* PREFIX_EVEX_MAP5_7C */ + { + { VEX_W_TABLE (EVEX_W_MAP5_7C_P_0) }, + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_MAP5_7C_P_2) }, + }, + /* PREFIX_EVEX_MAP5_7D_W_0 */ + { + { "vcvtph2uw", { XM, EXxh, EXxEVexR }, 0 }, + { "vcvtw2ph", { XM, EXxh, EXxEVexR }, 0 }, + { "vcvtph2w", { XM, EXxh, EXxEVexR }, 0 }, + { "vcvtuw2ph", { XM, EXxh, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP6_13 */ + { + { VEX_W_TABLE (EVEX_W_MAP6_13_P_0) }, + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_MAP6_13_P_2) }, + }, + /* PREFIX_EVEX_MAP6_56 */ + { + { Bad_Opcode }, + { "vfmaddcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 }, + { Bad_Opcode }, + { "vfcmaddcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP6_57 */ + { + { Bad_Opcode }, + { "vfmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 }, + { Bad_Opcode }, + { "vfcmaddcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP6_D6 */ + { + { Bad_Opcode }, + { "vfmulcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 }, + { Bad_Opcode }, + { "vfcmulcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 }, + }, + /* PREFIX_EVEX_MAP6_D7 */ + { + { Bad_Opcode }, + { "vfmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 }, + { Bad_Opcode }, + { "vfcmulcs%XH", { { DistinctDest_Fixup, xmm_mode }, VexScalar, EXd, EXxEVexR }, 0 }, + }, -- cgit v1.1