From e950b3453948830c5ce9c2f70d114d0b38a4b4ac Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 21 Sep 2016 16:56:57 +0100 Subject: [AArch64][SVE 27/32] Add SVE integer immediate operands This patch adds the new SVE integer immediate operands. There are three kinds: - simple signed and unsigned ranges, but with new widths and positions. - 13-bit logical immediates. These have the same form as in base AArch64, but at a different bit position. In the case of the "MOV Zn., #" alias of DUPM, the logical immediate is not allowed to be a valid DUP immediate, since DUP is preferred over DUPM for constants that both instructions can handle. - a new 9-bit arithmetic immediate, of the form "{, LSL #8}". In some contexts the operand is signed and in others it's unsigned. As an extension, we allow shifted immediates to be written as a single integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the shiftless form as the preferred disassembly, except for the special case of "#0, LSL #8" (a redundant encoding of 0). include/ * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) (AARCH64_OPND_SVE_UIMM8_53): Likewise. (aarch64_sve_dupm_mov_immediate_p): Declare. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE integer immediate operands. * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (operand_general_constraint_met_p): Handle the new SVE integer immediate operands. (aarch64_print_operand): Likewise. (aarch64_sve_dupm_mov_immediate_p): New function. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... (aarch64_ins_limm): ...here. (aarch64_ins_inv_limm): New function. (aarch64_ins_sve_aimm): Likewise. (aarch64_ins_sve_asimm): Likewise. (aarch64_ins_sve_limm_mov): Likewise. (aarch64_ins_sve_shlimm): Likewise. (aarch64_ins_sve_shrimm): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. * aarch64-dis.c (decode_limm): New function, split out from... (aarch64_ext_limm): ...here. (aarch64_ext_inv_limm): New function. (decode_sve_aimm): Likewise. (aarch64_ext_sve_aimm): Likewise. (aarch64_ext_sve_asimm): Likewise. (aarch64_ext_sve_limm_mov): Likewise. (aarch64_top_bit): Likewise. (aarch64_ext_sve_shlimm): Likewise. (aarch64_ext_sve_shrimm): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer immediate operands. --- opcodes/aarch64-tbl.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'opcodes/aarch64-tbl.h') diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 986cef6..edb2d79 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2761,6 +2761,8 @@ struct aarch64_opcode aarch64_opcode_table[] = "a 16-bit unsigned immediate") \ Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ "a 5-bit unsigned immediate") \ + Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ + "a 5-bit signed immediate") \ Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ "a flag bit specifier giving an alternative value for each flag") \ Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ @@ -2925,6 +2927,19 @@ struct aarch64_opcode aarch64_opcode_table[] = Y(ADDRESS, sve_addr_zz_uxtw, "SVE_ADDR_ZZ_UXTW", 0, \ F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ "an address with a vector register offset") \ + Y(IMMEDIATE, sve_aimm, "SVE_AIMM", 0, F(FLD_SVE_imm9), \ + "a 9-bit unsigned arithmetic operand") \ + Y(IMMEDIATE, sve_asimm, "SVE_ASIMM", 0, F(FLD_SVE_imm9), \ + "a 9-bit signed arithmetic operand") \ + Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \ + F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ + "an inverted 13-bit logical immediate") \ + Y(IMMEDIATE, limm, "SVE_LIMM", 0, \ + F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ + "a 13-bit logical immediate") \ + Y(IMMEDIATE, sve_limm_mov, "SVE_LIMM_MOV", 0, \ + F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ + "a 13-bit logical move immediate") \ Y(IMMEDIATE, imm, "SVE_PATTERN", 0, F(FLD_SVE_pattern), \ "an enumeration value such as POW2") \ Y(IMMEDIATE, sve_scale, "SVE_PATTERN_SCALED", 0, \ @@ -2947,6 +2962,30 @@ struct aarch64_opcode aarch64_opcode_table[] = "an SVE predicate register") \ Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ "an SVE predicate register") \ + Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \ + F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ + Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ + F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0, \ + F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0, \ + F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ + Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ + "a 5-bit signed immediate") \ + Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ + "a 5-bit signed immediate") \ + Y(IMMEDIATE, imm, "SVE_SIMM6", OPD_F_SEXT, F(FLD_SVE_imms), \ + "a 6-bit signed immediate") \ + Y(IMMEDIATE, imm, "SVE_SIMM8", OPD_F_SEXT, F(FLD_SVE_imm8), \ + "an 8-bit signed immediate") \ + Y(IMMEDIATE, imm, "SVE_UIMM3", 0, F(FLD_SVE_imm3), \ + "a 3-bit unsigned immediate") \ + Y(IMMEDIATE, imm, "SVE_UIMM7", 0, F(FLD_SVE_imm7), \ + "a 7-bit unsigned immediate") \ + Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ + "an 8-bit unsigned immediate") \ + Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \ + "an 8-bit unsigned immediate") \ Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ "an SVE vector register") \ Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ -- cgit v1.1