From adccc50753467ac66573471f180a60d8d96ce223 Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Thu, 9 May 2019 10:29:15 +0100 Subject: [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. --- opcodes/aarch64-opc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'opcodes/aarch64-opc.h') diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index f6c506d..b1060d4 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -136,6 +136,7 @@ enum aarch64_field_kind FLD_SVE_prfop, FLD_SVE_rot1, FLD_SVE_rot2, + FLD_SVE_rot3, FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszh, -- cgit v1.1