From 6456d318aaa7ea35511dad1f2facf0fb984972e5 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 7 Feb 2019 16:55:23 +0000 Subject: AArch64: Add verifier for By elem Single and Double sized instructions. The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns. --- opcodes/aarch64-opc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'opcodes/aarch64-opc.h') diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index ffb3b83..f6c506d 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -146,7 +146,8 @@ enum aarch64_field_kind FLD_rotate1, FLD_rotate2, FLD_rotate3, - FLD_SM3_imm2 + FLD_SM3_imm2, + FLD_sz }; /* Field description. */ -- cgit v1.1