From ee804238f097e91088a340c15891170f2748b4fd Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Wed, 3 Sep 2014 14:40:41 +0100
Subject: [PATCH/AArch64] Implement LSE feature

2014-09-03  Jiong Wang  <jiong.wang@arm.com>

  gas/
	* config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
	(aarch64_features): Add entry for lse extension.

  include/opcode/
	* aarch64.h (AARCH64_FEATURE_LSE): New feature added.
	(aarch64_opnd): Add AARCH64_OPND_PAIRREG.
	(aarch64_insn_class): Add lse_atomic.
	(F_LSE_SZ): New field added.
	(opcode_has_special_coder): Recognize F_LSE_SZ.

  opcode/
	* aarch64-tbl.h (QL_R4NIL): New qualifiers.
	(aarch64_feature_lse): New feature added.
	(LSE): New Added.
	(aarch64_opcode_table): New LSE instructions added.  Improve
	descriptions for ldarb/ldarh/ldar.
	(aarch64_opcode_table): Describe PAIRREG.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
	* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
	(aarch64_print_operand): Recognize PAIRREG.
	(operand_general_constraint_met_p): Check reg pair constraints for CASP
	instructions.
	* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
	(do_special_decoding): Recognize F_LSE_SZ.
	* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.

  gas/testsuite/
	* gas/aarch64/lse-atomic.d: New.
	* gas/aarch64/lse-atomic.s: Likewise.
	* gas/aarch64/illegal-lse.d: Likewise.
	* gas/aarch64/illegal-lse.l: Likewise.
	* gas/aarch64/illegal-lse.s: Likewise.
	* gas/aarch64/diagnostic.s: Check processor feature detect for lse
	instruction.
	* gas/aarch64/diagnostic.l: Likewise.
---
 opcodes/aarch64-opc-2.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'opcodes/aarch64-opc-2.c')

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 1831fe4..3d84d37 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -35,6 +35,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
   {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
   {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
   {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"},
@@ -151,12 +152,12 @@ static const unsigned op_enum_table [] =
   12,
   510,
   511,
-  776,
-  778,
-  780,
+  948,
+  950,
+  952,
   760,
-  779,
-  777,
+  951,
+  949,
   259,
   499,
   509,
-- 
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