From c84364ece4faa7b3eb0f60f4dc301282e9693e1e Mon Sep 17 00:00:00 2001
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri, 11 Nov 2016 10:39:46 +0000
Subject: [AArch64] Add ARMv8.3 PACGA instruction

Add support for the ARMv8.3 PACGA instruction.

include/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.

opcodes/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (arch64_opcode_table): Add pacga.
	(AARCH64_OPERANDS): Add Rm_SP.
	* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/pac.s: Add pacga.
	* testsuite/gas/aarch64/pac.d: Add pacga.
---
 opcodes/aarch64-opc-2.c | 53 +++++++++++++++++++++++++------------------------
 1 file changed, 27 insertions(+), 26 deletions(-)

(limited to 'opcodes/aarch64-opc-2.c')

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index ea44cfe..5e5b70b 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -35,6 +35,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"},
   {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
+  {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"},
   {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"},
   {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"},
   {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"},
@@ -208,48 +209,48 @@ const struct aarch64_operand aarch64_operands[] =
 static const unsigned op_enum_table [] =
 {
   0,
-  846,
   847,
   848,
-  851,
+  849,
   852,
   853,
   854,
   855,
-  849,
-  850,
   856,
+  850,
+  851,
   857,
-  879,
+  858,
   880,
   881,
-  884,
+  882,
   885,
   886,
   887,
   888,
-  882,
-  883,
   889,
+  883,
+  884,
   890,
-  933,
+  891,
   934,
   935,
   936,
+  937,
   12,
   627,
   628,
-  1128,
-  1130,
-  1132,
-  940,
-  1131,
   1129,
+  1131,
+  1133,
+  941,
+  1132,
+  1130,
   311,
   615,
   626,
   625,
-  938,
+  939,
   622,
   619,
   611,
@@ -259,34 +260,34 @@ static const unsigned op_enum_table [] =
   621,
   623,
   624,
-  948,
+  949,
   643,
   646,
   649,
   644,
   647,
-  790,
+  791,
   171,
   172,
   173,
   174,
   507,
-  731,
+  732,
   380,
   382,
   404,
   406,
-  1193,
-  1198,
-  1191,
-  1190,
   1194,
-  1201,
-  1203,
+  1199,
+  1192,
+  1191,
+  1195,
+  1202,
   1204,
-  1200,
-  1206,
   1205,
+  1201,
+  1207,
+  1206,
 };
 
 /* Given the opcode enumerator OP, return the pointer to the corresponding
-- 
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