From 00c2093f698e8f40c04340cb1832d09e11ece237 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Tue, 19 Dec 2017 12:05:20 +0000 Subject: Correct disassembly of dot product instructions. Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B. --- opcodes/aarch64-dis.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'opcodes/aarch64-dis.c') diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 8fd1ecf..aa38adb 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -331,7 +331,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->qualifier = get_expected_qualifier (inst, info->idx); switch (info->qualifier) { - case AARCH64_OPND_QLF_S_B: + case AARCH64_OPND_QLF_S_4B: /* L:H */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; -- cgit v1.1