From c2c4ff8d52a2cd3263a547b0384692498714aa1b Mon Sep 17 00:00:00 2001 From: Szabolcs Nagy Date: Fri, 18 Nov 2016 10:02:16 +0000 Subject: [AArch64] Add ARMv8.3 FCMLA and FCADD instructions Add support for FCMLA and FCADD complex arithmetic SIMD instructions. FCMLA has an indexed element variant where the index range has to be treated specially because a complex number takes two elements and the indexed vector size depends on the other operands. These complex number SIMD instructions are part of ARMv8.3 https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions include/ 2016-11-18 Szabolcs Nagy * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1, AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3. (enum aarch64_op): Add OP_FCMLA_ELEM. opcodes/ 2016-11-18 Szabolcs Nagy * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. (aarch64_opcode_table): Add fcmla and fcadd. (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. * aarch64-asm.c (aarch64_ins_imm_rotate): Define. * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. * aarch64-dis.c (aarch64_ext_imm_rotate): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. (operand_general_constraint_met_p): Rotate and index range check. (aarch64_print_operand): Handle rotate operand. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ 2016-11-18 Szabolcs Nagy * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*. * testsuite/gas/aarch64/advsimd-armv8_3.d: New. * testsuite/gas/aarch64/advsimd-armv8_3.s: New. * testsuite/gas/aarch64/illegal-fcmla.s: New. * testsuite/gas/aarch64/illegal-fcmla.l: New. * testsuite/gas/aarch64/illegal-fcmla.d: New. --- opcodes/aarch64-asm.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 3 deletions(-) (limited to 'opcodes/aarch64-asm.c') diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 64051a9..cfe6630 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -125,19 +125,28 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, { /* index for e.g. SQDMLAL , , .[] or SQDMLAL , , .[]. */ + unsigned index = info->reglane.index; + + if (inst->opcode->op == OP_FCMLA_ELEM) + /* Complex operand takes two elements. */ + index *= 2; + switch (info->qualifier) { case AARCH64_OPND_QLF_S_H: /* H:L:M */ - insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H); + assert (index < 8); + insert_fields (code, index, 0, 3, FLD_M, FLD_L, FLD_H); break; case AARCH64_OPND_QLF_S_S: /* H:L */ - insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H); + assert (index < 4); + insert_fields (code, index, 0, 2, FLD_L, FLD_H); break; case AARCH64_OPND_QLF_S_D: /* H */ - insert_field (FLD_H, code, info->reglane.index, 0); + assert (index < 2); + insert_field (FLD_H, code, index, 0); break; default: assert (0); @@ -427,6 +436,41 @@ aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info, return NULL; } +/* Insert field rot for the rotate immediate in + FCMLA ., ., ., #. */ +const char * +aarch64_ins_imm_rotate (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, const aarch64_inst *inst) +{ + uint64_t rot = info->imm.value / 90; + + switch (info->type) + { + case AARCH64_OPND_IMM_ROT1: + case AARCH64_OPND_IMM_ROT2: + /* value rot + 0 0 + 90 1 + 180 2 + 270 3 */ + assert (rot < 4U); + break; + case AARCH64_OPND_IMM_ROT3: + /* value rot + 90 0 + 270 1 */ + rot = (rot - 1) / 2; + assert (rot < 2U); + break; + default: + assert (0); + } + insert_field (self->fields[0], code, rot, inst->opcode->mask); + + return NULL; +} + /* Insert # for the immediate operand in fp fix-point instructions, e.g. SCVTF
, , #. */ const char * -- cgit v1.1