From b408ebbf526e7293f08825d04b34c7d2ad7fc753 Mon Sep 17 00:00:00 2001
From: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu, 30 Mar 2023 11:09:12 +0100
Subject: aarch64: Add the SME2 multivector LD1 and ST1 instructions

SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided.  In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.

The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15.  Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound.  The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound.  This in turn required adding
an extra bit to the field.
---
 opcodes/aarch64-asm-2.c | 44 ++++++++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 20 deletions(-)

(limited to 'opcodes/aarch64-asm-2.c')

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index daba55b..6775d22 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -667,9 +667,10 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 203:
     case 209:
     case 212:
-    case 218:
-    case 219:
-    case 224:
+    case 220:
+    case 221:
+    case 226:
+    case 227:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 15:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -681,7 +682,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 33:
     case 34:
     case 35:
-    case 234:
+    case 237:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 36:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -726,10 +727,10 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 192:
     case 193:
     case 194:
-    case 225:
-    case 233:
-    case 238:
-    case 239:
+    case 228:
+    case 236:
+    case 241:
+    case 242:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 44:
     case 45:
@@ -894,26 +895,29 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 216:
     case 217:
       return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
-    case 220:
+    case 218:
+    case 219:
+      return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
     case 222:
-    case 226:
+    case 224:
+    case 229:
       return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
-    case 221:
     case 223:
+    case 225:
       return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
-    case 227:
-    case 228:
-    case 229:
-      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 230:
-      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 231:
-      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
     case 232:
-      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
+    case 233:
+      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+    case 234:
+      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
     case 235:
-    case 236:
-    case 237:
+      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+    case 238:
+    case 239:
+    case 240:
       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
-- 
cgit v1.1